1 Wed Jun 10 13:22:32 1998 Frank Ch. Eigler <fche@cygnus.com>
3 * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
5 (interrupt_event): Made non-static.
8 * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
9 interchange of configuration values for external vs. internal
13 Tue Jun 9 12:46:24 1998 Ian Carmichael <iancarm@cygnus.com>
15 * mips.igen (BREAK): Moved code to here for
16 simulator-reserved break instructions.
17 * gencode.c (build_instruction): Ditto.
18 * interp.c (signal_exception): Code moved from here. Non-
19 reserved instructions now use exception vector, rather
21 * sim-main.h: Moved magic constants to here.
24 Tue Jun 9 12:29:50 1998 Frank Ch. Eigler <fche@cygnus.com>
26 * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
27 register upon non-zero interrupt event level, clear upon zero
29 * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
30 by passing zero event value.
31 (*_io_{read,write}_buffer): Endianness fixes.
32 * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
33 (deliver_*_tick): Reduce sim event interval to 75% of count interval.
35 * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
36 serial I/O and timer module at base address 0xFFFF0000.
39 Tue Jun 9 11:52:29 1998 Gavin Koch <gavin@cygnus.com>
41 * mips.igen (SWC1) : Correct the handling of ReverseEndian
44 Tue Jun 9 11:40:57 1998 Gavin Koch <gavin@cygnus.com>
46 * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
51 Thu Jun 4 15:37:33 1998 Frank Ch. Eigler <fche@cygnus.com>
53 * dv-tx3904tmr.c: New file - implements tx3904 timer.
54 * dv-tx3904{irc,cpu}.c: Mild reformatting.
55 * configure.in: Include tx3904tmr in hw_device list.
57 * interp.c (sim_open): Instantiate three timer instances.
58 Fix address typo of tx3904irc instance.
62 Thu Jun 4 16:47:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
64 * mips.igen (check_mt_hilo): 2.1 of r5900 spec stalls for HILO.
65 Select corresponding check_mt_hilo function.
66 (check_mult_hilo, check_div_hilo, check_mf_hilo, check_mt_hilo):
69 * r5900.igen (check_mult_hilo_hi1lo1, check_div_hilo_hi1lo1): Mark
73 Tue Jun 2 15:48:02 1998 Ian Carmichael <iancarm@cygnus.com>
75 * interp.c (signal_exception): SystemCall exception now uses
78 Mon Jun 1 18:18:26 1998 Frank Ch. Eigler <fche@cygnus.com>
80 * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
84 Mon Jun 1 10:28:25 1998 Jeffrey A Law (law@cygnus.com)
86 * r5900.igen (rsqrt.s): Update based on r5900 ISA manual version 2.1.
90 Fri May 29 11:40:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
92 * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
95 Mon May 25 20:47:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
97 * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
99 * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
100 sim-main.h. Declare a struct hw_descriptor instead of struct
101 hw_device_descriptor.
104 Mon May 25 12:41:38 1998 Andrew Cagney <cagney@b1.cygnus.com>
106 * mips.igen (do_store_left, do_load_left): Compute nr of left and
107 right bits and then re-align left hand bytes to correct byte
108 lanes. Fix incorrect computation in do_store_left when loading
109 bytes from second word.
111 start-sanitize-tx3904
112 Fri May 22 13:34:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
114 * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
115 * interp.c (sim_open): Only create a device tree when HW is
118 * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
119 * interp.c (signal_exception): Ditto.
122 Thu May 21 14:24:11 1998 Gavin Koch <gavin@cygnus.com>
124 * gencode.c: Mark BEGEZALL as LIKELY.
126 Thu May 21 18:57:19 1998 Andrew Cagney <cagney@b1.cygnus.com>
128 * sim-main.h (ALU32_END): Sign extend 32 bit results.
129 * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
132 Thu May 21 17:15:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
134 * interp.c (sim_fetch_register): Convert internal r5900 regs to
138 Mon May 18 18:22:42 1998 Frank Ch. Eigler <fche@cygnus.com>
140 * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
141 modules. Recognize TX39 target with "mips*tx39" pattern.
142 * configure: Rebuilt.
143 * sim-main.h (*): Added many macros defining bits in
144 TX39 control registers.
145 (SignalInterrupt): Send actual PC instead of NULL.
146 (SignalNMIReset): New exception type.
147 * interp.c (board): New variable for future use to identify
148 a particular board being simulated.
149 (mips_option_handler,mips_options): Added "--board" option.
150 (interrupt_event): Send actual PC.
151 (sim_open): Make memory layout conditional on board setting.
152 (signal_exception): Initial implementation of hardware interrupt
153 handling. Accept another break instruction variant for simulator
155 (decode_coproc): Implement RFE instruction for TX39.
156 (mips.igen): Decode RFE instruction as such.
157 start-sanitize-tx3904
158 * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
159 * interp.c: Define "jmr3904" and "jmr3904debug" board types and
160 bbegin to implement memory map.
161 * dv-tx3904cpu.c: New file.
162 * dv-tx3904irc.c: New file.
165 Wed May 13 14:40:11 1998 Gavin Koch <gavin@cygnus.com>
167 * mips.igen (check_mt_hilo): Create a separate r3900 version.
170 Wed May 13 14:27:53 1998 Gavin Koch <gavin@cygnus.com>
172 * r5900.igen: Replace the calls and the definition of the
173 function check_op_hilo_hi1lo1 with the pair
174 check_mult_hilo_hi1lo1 and check_mult_hilo_hi1lo1.
177 Wed May 13 14:11:46 1998 Gavin Koch <gavin@cygnus.com>
179 * tx.igen (madd,maddu): Replace calls to check_op_hilo
180 with calls to check_div_hilo.
182 Wed May 13 09:59:27 1998 Gavin Koch <gavin@cygnus.com>
184 * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
185 Replace check_op_hilo with check_mult_hilo and check_div_hilo.
186 Add special r3900 version of do_mult_hilo.
187 (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
188 with calls to check_mult_hilo.
189 (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
190 with calls to check_div_hilo.
192 Tue May 12 15:22:11 1998 Andrew Cagney <cagney@b1.cygnus.com>
194 * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
195 Document a replacement.
197 Fri May 8 17:48:19 1998 Ian Carmichael <iancarm@cygnus.com>
199 * interp.c (sim_monitor): Make mon_printf work.
201 Wed May 6 19:42:19 1998 Doug Evans <devans@canuck.cygnus.com>
203 * sim-main.h (INSN_NAME): New arg `cpu'.
206 Thu Apr 30 18:51:26 1998 Andrew Cagney <cagney@b1.cygnus.com>
208 * sky-libvpe.c (FMAdd, FMSub): Replace r59fp_op3 call with
213 Wed Apr 29 22:54:45 1998 Andrew Cagney <cagney@b1.cygnus.com>
215 * sim-main.h (R5900_FP_MAX, R5900_FP_MIN): Define.
216 * r5900.igen (r59fp_overflow): Use.
218 * r5900.igen (r59fp_op3): Rename to
219 (r59fp_mula): This, delete opm argument.
220 (MADD.S, MADDA.S, MSUB.S, MSUBS.S): Update.
221 (r59fp_mula): Overflowing product propogates through to result.
222 (r59fp_mula): ACC to the MAX propogates to result.
223 (r59fp_mula): Underflow during multiply only sets SU.
226 Tue Apr 28 18:33:31 1998 Geoffrey Noer <noer@cygnus.com>
228 * configure: Regenerated to track ../common/aclocal.m4 changes.
230 Sun Apr 26 15:31:55 1998 Tom Tromey <tromey@creche>
232 * configure: Regenerated to track ../common/aclocal.m4 changes.
235 Sun Apr 26 15:20:01 1998 Tom Tromey <tromey@cygnus.com>
237 * acconfig.h: New file.
238 * configure.in: Reverted change of Apr 24; use sinclude again.
240 Fri Apr 24 14:16:40 1998 Tom Tromey <tromey@creche>
242 * configure: Regenerated to track ../common/aclocal.m4 changes.
245 Fri Apr 24 11:19:20 1998 Tom Tromey <tromey@cygnus.com>
247 * configure.in: Don't call sinclude.
249 Fri Apr 24 11:35:01 1998 Andrew Cagney <cagney@chook.cygnus.com>
251 * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
253 Tue Apr 21 11:59:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
255 * mips.igen (ERET): Implement.
257 * interp.c (decode_coproc): Return sign-extended EPC.
259 * mips.igen (ANDI, LUI, MFC0): Add tracing code.
261 * interp.c (signal_exception): Do not ignore Trap.
262 (signal_exception): On TRAP, restart at exception address.
263 (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
264 (signal_exception): Update.
265 (sim_open): Patch V_COMMON interrupt vector with an abort sequence
266 so that TRAP instructions are caught.
268 Mon Apr 20 11:26:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
270 * sim-main.h (struct hilo_access, struct hilo_history): Define,
271 contains HI/LO access history.
272 (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
273 (HIACCESS, LOACCESS): Delete, replace with
274 (HIHISTORY, LOHISTORY): New macros.
275 (start-sanitize-r5900):
276 (struct sim_5900_cpu): Make hi1access, lo1access of type
278 (HI1ACCESS, LO1ACCESS): Delete, replace with
279 (HI1HISTORY, LO1HISTORY): New macros.
280 (end-sanitize-r5900):
281 (CHECKHILO): Delete all, moved to mips.igen
283 * gencode.c (build_instruction): Do not generate checks for
284 correct HI/LO register usage.
286 * interp.c (old_engine_run): Delete checks for correct HI/LO
289 * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
290 check_mf_cycles): New functions.
291 (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
292 do_divu, domultx, do_mult, do_multu): Use.
294 * tx.igen ("madd", "maddu"): Use.
295 (start-sanitize-r5900):
297 r5900.igen: Update all HI/LO checks.
298 ("mfhi1", "mflo1", "mthi1", "mthi1", "pmfhi", "pmflo", "pmfhl",
299 "pmthi", "pmtlo", "mpthl"): Check MF/MT HI/LO.
300 ("mult1", "div1", "divu1", "multu1", "madd1", "maddu1", "pdivbw",
301 "pdivuw", "pdivw", "phmaddh", "phmsubh", "pmaddh", "madduw",
302 "pmaddw", "pmsubh", "pmsubw", "pmulth", "pmultuw", "pmultw"):
304 (end-sanitize-r5900):
307 Mon Apr 20 18:39:47 1998 Frank Ch. Eigler <fche@cygnus.com>
309 * interp.c (decode_coproc): Correct CMFC2/QMTC2
312 * r5900.igen (LQ,SQ): Use a pair of 64-bit accesses
313 instead of a single 128-bit access.
317 Fri Apr 17 14:50:39 1998 Frank Ch. Eigler <fche@cygnus.com>
319 * r5900.igen (COP_[LS]Q): Transfer COP2 quadwords.
320 * interp.c (cop_[ls]q): Fixes corresponding to above.
324 Thu Apr 16 15:24:14 1998 Frank Ch. Eigler <fche@cygnus.com>
326 * interp.c (decode_coproc): Adapt COP2 micro interlock to
327 clarified specs. Reset "M" bit; exit also on "E" bit.
331 Thu Apr 16 10:40:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
333 * r5900.igen (CFC1, CTC1): Implement R5900 specific version.
334 * mips.igen (CFC1, CTC1): R5900 des not use generic version.
336 * r5900.igen (r59fp_unpack): New function.
337 (r59fp_op1, r59fp_op2, r59fp_op3, C.cond.S, CVT.S.W, DIV.S,
338 RSQRT.S, SQRT.S): Use.
339 (r59fp_zero): New function.
340 (r59fp_overflow): Generate r5900 specific overflow value.
341 (r59fp_store): Re-write, overflow to MAX_R5900_FP value, underflow
343 (CVT.S.W, CVT.W.S): Exchange implementations.
345 * sim-main.h (R5900_EXPMAX, R5900_EXPMIN, R5900_EXPBIAS): Defile.
349 Thu Apr 16 09:14:44 1998 Andrew Cagney <cagney@b1.cygnus.com>
351 * configure.in (tx19, sim_use_gen): Switch to igen.
352 * configure: Re-build.
356 Wed Apr 15 12:41:18 1998 Frank Ch. Eigler <fche@cygnus.com>
358 * interp.c (decode_coproc): Make COP2 branch code compile after
359 igen signature changes.
362 Wed Apr 15 18:31:54 1998 Andrew Cagney <cagney@b1.cygnus.com>
364 * mips.igen (DSRAV): Use function do_dsrav.
365 (SRAV): Use new function do_srav.
367 * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
368 (B): Sign extend 11 bit immediate.
369 (EXT-B*): Shift 16 bit immediate left by 1.
370 (ADDIU*): Don't sign extend immediate value.
372 Wed Apr 15 10:32:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
374 * m16run.c (sim_engine_run): Restore CIA after handling an event.
377 * mips.igen (mtc0): Valid tx19 instruction.
380 * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
383 * mips.igen (delayslot32, nullify_next_insn): New functions.
384 (m16.igen): Always include.
385 (do_*): Add more tracing.
387 * m16.igen (delayslot16): Add NIA argument, could be called by a
388 32 bit MIPS16 instruction.
390 * interp.c (ifetch16): Move function from here.
391 * sim-main.c (ifetch16): To here.
393 * sim-main.c (ifetch16, ifetch32): Update to match current
394 implementations of LH, LW.
395 (signal_exception): Don't print out incorrect hex value of illegal
398 Wed Apr 15 00:17:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
400 * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
403 * m16.igen: Implement MIPS16 instructions.
405 * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
406 do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
407 do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
408 do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
409 do_srl, do_srlv, do_subu, do_xor, do_xori): New functions. Move
410 bodies of corresponding code from 32 bit insn to these. Also used
411 by MIPS16 versions of functions.
413 * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
414 (IMEM16): Drop NR argument from macro.
417 Mon Apr 13 16:28:52 1998 Frank Ch. Eigler <fche@cygnus.com>
419 * interp.c (decode_coproc): Add proper 1000000 bit-string at top
420 of VU lower instruction.
424 Thu Apr 9 16:38:23 1998 Frank Ch. Eigler <fche@cygnus.com>
426 * r5900.igen (LQC,SQC): Adapted code to DOUBLEWORD accesses
429 * sim-main.h: Removed attempt at allowing 128-bit access.
433 Wed Apr 8 18:12:13 1998 Frank Ch. Eigler <fche@cygnus.com>
435 * Makefile.in (SIM_SKY_OBJS): Added sky-vudis.o.
437 * interp.c (decode_coproc): Refer to VU CIA as a "special"
438 register, not as a "misc" register. Aha. Add activity
439 assertions after VCALLMS* instructions.
443 Tue Apr 7 18:32:49 1998 Frank Ch. Eigler <fche@cygnus.com>
445 * interp.c (decode_coproc): Do not apply superfluous E (end) flag
446 to upper code of generated VU instruction.
450 Mon Apr 6 19:55:56 1998 Frank Ch. Eigler <fche@cygnus.com>
452 * interp.c (cop_[ls]q): Replaced stub with proper COP2 code.
454 * sim-main.h (LOADADDRMASK): Redefine to allow 128-bit accesses
457 * r5900.igen (SQC2): Thinko.
461 Sun Apr 5 12:05:44 1998 Frank Ch. Eigler <fche@cygnus.com>
463 * interp.c (*): Adapt code to merged VU device & state structs.
464 (decode_coproc): Execute COP2 each macroinstruction without
465 pipelining, by stepping VU to completion state. Adapted to
466 read_vu_*_reg style of register access.
468 * mips.igen ([SL]QC2): Removed these COP2 instructions.
470 * r5900.igen ([SL]QC2): Transplanted these COP2 instructions here.
472 * sim-main.h (cop_[ls]q): Enclosed in TARGET_SKY guards.
475 Sat Apr 4 22:39:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
477 * Makefile.in (SIM_OBJS): Add sim-main.o.
479 * sim-main.h (address_translation, load_memory, store_memory,
480 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
482 (pr_addr, pr_uword64): Declare.
483 (sim-main.c): Include when H_REVEALS_MODULE_P.
485 * interp.c (address_translation, load_memory, store_memory,
486 cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
488 * sim-main.c: To here. Fix compilation problems.
490 * configure.in: Enable inlining.
491 * configure: Re-config.
493 Sat Apr 4 20:36:25 1998 Andrew Cagney <cagney@b1.cygnus.com>
495 * configure: Regenerated to track ../common/aclocal.m4 changes.
497 Fri Apr 3 04:32:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
499 * mips.igen: Include tx.igen.
500 * Makefile.in (IGEN_INCLUDE): Add tx.igen.
501 * tx.igen: New file, contains MADD and MADDU.
503 * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
504 the hardwired constant `7'.
505 (store_memory): Ditto.
506 (LOADDRMASK): Move definition to sim-main.h.
508 mips.igen (MTC0): Enable for r3900.
511 mips.igen (do_load_byte): Delete.
512 (do_load, do_store, do_load_left, do_load_write, do_store_left,
513 do_store_right): New functions.
514 (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
516 configure.in: Let the tx39 use igen again.
519 Thu Apr 2 10:59:39 1998 Andrew Cagney <cagney@b1.cygnus.com>
521 * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
522 not an address sized quantity. Return zero for cache sizes.
524 Wed Apr 1 23:47:53 1998 Andrew Cagney <cagney@b1.cygnus.com>
526 * mips.igen (r3900): r3900 does not support 64 bit integer
530 Wed Apr 1 08:20:31 1998 Frank Ch. Eigler <fche@cygnus.com>
532 * mips.igen (SQC2/LQC2): Make bodies sky-target-only also.
536 Mon Mar 30 18:41:43 1998 Frank Ch. Eigler <fche@cygnus.com>
538 * interp.c (decode_coproc): Continuing COP2 work.
539 (cop_[ls]q): Make sky-target-only.
541 * sim-main.h (COP_[LS]Q): Make sky-target-only.
543 Mon Mar 30 14:46:05 1998 Gavin Koch <gavin@cygnus.com>
545 * configure.in (mipstx39*-*-*): Use gencode simulator rather
547 * configure : Rebuild.
550 Sun Mar 29 17:50:11 Frank Ch. Eigler <fche@cygnus.com>
552 * interp.c (decode_coproc): Added a missing TARGET_SKY check
553 around COP2 implementation skeleton.
557 Fri Mar 27 16:19:29 1998 Frank Ch. Eigler <fche@cygnus.com>
559 * Makefile.in (SIM_SKY_OBJS): Replaced sky-vu[01].o with sky-vu.o.
561 * interp.c (sim_{load,store}_register): Use new vu[01]_device
562 static to access VU registers.
563 (decode_coproc): Added skeleton of sky COP2 (VU) instruction
564 decoding. Work in progress.
566 * mips.igen (LDCzz, SDCzz): Removed *5900 case for this
567 overlapping/redundant bit pattern.
568 (LQC2, SQC2): Added *5900 COP2 instruction skeleta. Work in
571 * sim-main.h (status_CU[012]): Added COP[n]-enabled flags for
574 * interp.c (cop_lq, cop_sq): New functions for future 128-bit
575 access to coprocessor registers.
577 * sim-main.h (COP_LQ, COP_SQ): New macro front-ends for above.
579 Fri Mar 27 16:15:52 1998 Andrew Cagney <cagney@b1.cygnus.com>
581 * configure: Regenerated to track ../common/aclocal.m4 changes.
583 Fri Mar 27 15:01:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
585 * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
587 Wed Mar 25 16:44:27 1998 Ian Carmichael <iancarm@cygnus.com>
589 * configure: Regenerated to track ../common/aclocal.m4 changes.
590 * config.in: Regenerated to track ../common/aclocal.m4 changes.
592 Wed Mar 25 12:35:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
594 * configure: Regenerated to track ../common/aclocal.m4 changes.
596 Wed Mar 25 10:05:46 1998 Andrew Cagney <cagney@b1.cygnus.com>
598 * interp.c (Max, Min): Comment out functions. Not yet used.
600 start-sanitize-vr4320
601 Wed Mar 25 10:04:13 1998 Andrew Cagney <cagney@b1.cygnus.com>
603 * vr4320.igen (DCLZ): Pacify GCC, 64 bit arg, int format.
606 Wed Mar 18 12:38:12 1998 Andrew Cagney <cagney@b1.cygnus.com>
608 * configure: Regenerated to track ../common/aclocal.m4 changes.
610 Tue Mar 17 19:05:20 1998 Frank Ch. Eigler <fche@cygnus.com>
612 * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
613 configurable settings for stand-alone simulator.
616 * configure.in: Added --with-sim-gpu2 option to specify path of
617 sky GPU2 library. Triggers -DSKY_GPU2 for sky-gpuif.c, and
618 links/compiles stand-alone simulator with this library.
620 * interp.c (MEM_SIZE): Increased default sky memory size to 16MB.
622 * configure.in: Added X11 search, just in case.
624 * configure: Regenerated.
626 Wed Mar 11 14:09:10 1998 Andrew Cagney <cagney@b1.cygnus.com>
628 * interp.c (sim_write, sim_read, load_memory, store_memory):
629 Replace sim_core_*_map with read_map, write_map, exec_map resp.
631 start-sanitize-vr4320
632 Tue Mar 10 10:32:22 1998 Gavin Koch <gavin@cygnus.com>
634 * vr4320.igen (clz,dclz) : Added.
635 (dmac): Replaced 99, with LO.
638 start-sanitize-vr5400
639 Fri Mar 6 08:30:58 1998 Andrew Cagney <cagney@b1.cygnus.com>
641 * mdmx.igen (SHFL.REPA.fmt, SHFL.REPB.fmt): Fix bit fields.
644 start-sanitize-vr4320
645 Tue Mar 3 11:56:29 1998 Gavin Koch <gavin@cygnus.com>
647 * vr4320.igen: New file.
648 * Makefile.in (vr4320.igen) : Added.
649 * configure.in (mips64vr4320-*-*): Added.
650 * configure : Rebuilt.
651 * mips.igen : Correct the bfd-names in the mips-ISA model entries.
652 Add the vr4320 model entry and mark the vr4320 insn as necessary.
655 Tue Mar 3 13:58:43 1998 Andrew Cagney <cagney@b1.cygnus.com>
657 * sim-main.h (GETFCC): Return an unsigned value.
660 * r5900.igen: Use an unsigned array index variable `i'.
661 (QFSRV): Ditto for variable bytes.
664 Tue Mar 3 13:21:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
666 * mips.igen (DIV): Fix check for -1 / MIN_INT.
667 (DADD): Result destination is RD not RT.
670 * r5900.igen (DIV1): Fix check for -1 / MIN_INT.
671 (DIVU1): Don't check for MIN_INT / -1 as performing unsigned
675 Fri Feb 27 13:49:49 1998 Andrew Cagney <cagney@b1.cygnus.com>
677 * sim-main.h (HIACCESS, LOACCESS): Always define.
679 * mdmx.igen (Maxi, Mini): Rename Max, Min.
681 * interp.c (sim_info): Delete.
683 Fri Feb 27 18:41:01 1998 Doug Evans <devans@canuck.cygnus.com>
685 * interp.c (DECLARE_OPTION_HANDLER): Use it.
686 (mips_option_handler): New argument `cpu'.
687 (sim_open): Update call to sim_add_option_table.
689 Wed Feb 25 18:56:22 1998 Andrew Cagney <cagney@b1.cygnus.com>
691 * mips.igen (CxC1): Add tracing.
694 Wed Feb 25 13:59:03 1998 Andrew Cagney <cagney@b1.cygnus.com>
696 * r5900.igen (StoreFP): Delete.
697 (r59fp_store, r59fp_overflow, r59fp_op1, r59fp_op2, r59fp_op3):
699 (rsqrt.s, sqrt.s): Implement.
700 (r59cond): New function.
701 (C.COND.S): Call r59cond in assembler line.
702 (cvt.w.s, cvt.s.w): Implement.
704 * mips.igen (rsqrt.fmt, sqrt.fmt, cvt.*.*): Remove from r5900
707 * sim-main.h: Define an enum of r5900 FCSR bit fields.
711 Tue Feb 24 14:44:18 1998 Andrew Cagney <cagney@b1.cygnus.com>
713 * r5900.igen: Add tracing to all p* instructions.
715 Tue Feb 24 02:47:33 1998 Andrew Cagney <cagney@b1.cygnus.com>
717 * interp.c (sim_store_register, sim_fetch_register): Pull swifty
718 to get gdb talking to re-aranged sim_cpu register structure.
721 Fri Feb 20 17:43:21 1998 Andrew Cagney <cagney@b1.cygnus.com>
723 * sim-main.h (Max, Min): Declare.
725 * interp.c (Max, Min): New functions.
727 * mips.igen (BC1): Add tracing.
729 start-sanitize-vr5400
730 Fri Feb 20 16:27:17 1998 Andrew Cagney <cagney@b1.cygnus.com>
732 * mdmx.igen: Tag all functions as requiring either with mdmx or
737 Fri Feb 20 15:55:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
739 * configure.in (SIM_AC_OPTION_FLOAT): For r5900, set FP bit size
741 (SIM_AC_OPTION_BITSIZE): For r5900, set nr address bits to 32.
743 * mips.igen (C.cond.fmt, ..): Not part of r5900 insn set.
745 * r5900.igen: Rewrite.
747 * sim-main.h: Move r5900 registers to a separate _sim_r5900_cpu
749 (GPR_SB, GPR_SH, GPR_SW, GPR_SD, GPR_UB, GPR_UH, GPR_UW, GPR_UD):
750 Define in terms of GPR/GPR1 instead of REGISTERS/REGISTERS.1
753 Thu Feb 19 14:50:00 1998 John Metzler <jmetzler@cygnus.com>
755 * interp.c Added memory map for stack in vr4100
757 Thu Feb 19 10:21:21 1998 Gavin Koch <gavin@cygnus.com>
759 * interp.c (load_memory): Add missing "break"'s.
761 Tue Feb 17 12:45:35 1998 Andrew Cagney <cagney@b1.cygnus.com>
763 * interp.c (sim_store_register, sim_fetch_register): Pass in
764 length parameter. Return -1.
766 Tue Feb 10 11:57:40 1998 Ian Carmichael <iancarm@cygnus.com>
768 * interp.c: Added hardware init hook, fixed warnings.
770 Sat Feb 7 17:16:20 1998 Andrew Cagney <cagney@b1.cygnus.com>
772 * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
774 Tue Feb 3 11:36:02 1998 Andrew Cagney <cagney@b1.cygnus.com>
776 * interp.c (ifetch16): New function.
778 * sim-main.h (IMEM32): Rename IMEM.
779 (IMEM16_IMMED): Define.
781 (DELAY_SLOT): Update.
783 * m16run.c (sim_engine_run): New file.
785 * m16.igen: All instructions except LB.
786 (LB): Call do_load_byte.
787 * mips.igen (do_load_byte): New function.
788 (LB): Call do_load_byte.
790 * mips.igen: Move spec for insn bit size and high bit from here.
791 * Makefile.in (tmp-igen, tmp-m16): To here.
793 * m16.dc: New file, decode mips16 instructions.
795 * Makefile.in (SIM_NO_ALL): Define.
796 (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
799 * m16.igen: Mark all mips16 insns as being part of the tx19 insn
803 Tue Feb 3 11:28:00 1998 Andrew Cagney <cagney@b1.cygnus.com>
805 * configure.in (mips_fpu_bitsize): For tx39, restrict floating
806 point unit to 32 bit registers.
807 * configure: Re-generate.
809 Sun Feb 1 15:47:14 1998 Andrew Cagney <cagney@b1.cygnus.com>
811 * configure.in (sim_use_gen): Make IGEN the default simulator
812 generator for generic 32 and 64 bit mips targets.
813 * configure: Re-generate.
815 Sun Feb 1 16:52:37 1998 Andrew Cagney <cagney@b1.cygnus.com>
817 * sim-main.h (SizeFGR): Determine from floating-point and not gpr
820 * interp.c (sim_fetch_register, sim_store_register): Read/write
821 FGR from correct location.
822 (sim_open): Set size of FGR's according to
823 WITH_TARGET_FLOATING_POINT_BITSIZE.
825 * sim-main.h (FGR): Store floating point registers in a separate
828 Sun Feb 1 16:47:51 1998 Andrew Cagney <cagney@b1.cygnus.com>
830 * configure: Regenerated to track ../common/aclocal.m4 changes.
832 start-sanitize-vr5400
833 * mdmx.igen: Mark all instructions as 64bit/fp specific.
836 Tue Feb 3 00:10:50 1998 Andrew Cagney <cagney@b1.cygnus.com>
838 * interp.c (ColdReset): Call PENDING_INVALIDATE.
840 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
842 * interp.c (pending_tick): New function. Deliver pending writes.
844 * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
845 PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
846 it can handle mixed sized quantites and single bits.
848 Mon Feb 2 17:43:15 1998 Andrew Cagney <cagney@b1.cygnus.com>
850 * interp.c (oengine.h): Do not include when building with IGEN.
851 (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
852 (sim_info): Ditto for PROCESSOR_64BIT.
853 (sim_monitor): Replace ut_reg with unsigned_word.
854 (*): Ditto for t_reg.
855 (LOADDRMASK): Define.
856 (sim_open): Remove defunct check that host FP is IEEE compliant,
857 using software to emulate floating point.
858 (value_fpr, ...): Always compile, was conditional on HASFPU.
860 Sun Feb 1 11:15:29 1998 Andrew Cagney <cagney@b1.cygnus.com>
862 * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
865 * interp.c (SD, CPU): Define.
866 (mips_option_handler): Set flags in each CPU.
867 (interrupt_event): Assume CPU 0 is the one being iterrupted.
868 (sim_close): Do not clear STATE, deleted anyway.
869 (sim_write, sim_read): Assume CPU zero's vm should be used for
871 (sim_create_inferior): Set the PC for all processors.
872 (sim_monitor, store_word, load_word, mips16_entry): Add cpu
874 (mips16_entry): Pass correct nr of args to store_word, load_word.
875 (ColdReset): Cold reset all cpu's.
876 (signal_exception): Pass cpu to sim_monitor & mips16_entry.
877 (sim_monitor, load_memory, store_memory, signal_exception): Use
878 `CPU' instead of STATE_CPU.
881 * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
884 * sim-main.h (signal_exception): Add sim_cpu arg.
885 (SignalException*): Pass both SD and CPU to signal_exception.
886 * interp.c (signal_exception): Update.
888 * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
890 (sync_operation, prefetch, cache_op, store_memory, load_memory,
891 address_translation): Ditto
892 (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
894 start-sanitize-vr5400
895 * mdmx.igen (get_scale): Pass CPU_ to semantic_illegal instead of
897 (ByteAlign): Use StoreFPR, pass args in correct order.
901 Sun Feb 1 10:59:55 1998 Andrew Cagney <cagney@b1.cygnus.com>
903 * configure.in (sim_igen_filter): For r5900, configure as SMP.
906 Sat Jan 31 18:15:41 1998 Andrew Cagney <cagney@b1.cygnus.com>
908 * configure: Regenerated to track ../common/aclocal.m4 changes.
910 Sat Jan 31 14:49:24 1998 Andrew Cagney <cagney@b1.cygnus.com>
913 * configure.in (sim_igen_filter): For r5900, use igen.
914 * configure: Re-generate.
917 * interp.c (sim_engine_run): Add `nr_cpus' argument.
919 * mips.igen (model): Map processor names onto BFD name.
921 * sim-main.h (CPU_CIA): Delete.
922 (SET_CIA, GET_CIA): Define
924 Wed Jan 21 16:16:27 1998 Andrew Cagney <cagney@b1.cygnus.com>
926 * sim-main.h (GPR_SET): Define, used by igen when zeroing a
929 * configure.in (default_endian): Configure a big-endian simulator
931 * configure: Re-generate.
933 Mon Jan 19 22:26:29 1998 Doug Evans <devans@seba>
935 * configure: Regenerated to track ../common/aclocal.m4 changes.
937 Mon Jan 5 20:38:54 1998 Mark Alexander <marka@cygnus.com>
939 * interp.c (sim_monitor): Handle Densan monitor outbyte
940 and inbyte functions.
942 1997-12-29 Felix Lee <flee@cygnus.com>
944 * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
946 Wed Dec 17 14:48:20 1997 Jeffrey A Law (law@cygnus.com)
948 * Makefile.in (tmp-igen): Arrange for $zero to always be
949 reset to zero after every instruction.
951 Mon Dec 15 23:17:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
953 * configure: Regenerated to track ../common/aclocal.m4 changes.
956 start-sanitize-vr5400
957 Sat Dec 13 15:18:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
959 * vr5400.igen (Low32Bits, High32Bits): Sign extend extracted 32
963 start-sanitize-vr5400
964 Fri Dec 12 12:26:07 1997 Jeffrey A Law (law@cygnus.com)
966 * configure.in (sim_igen_filter): Multi-sim vr5000 - vr5000 or
967 vr5400 with the vr5000 as the default.
970 Wed Dec 10 17:10:45 1997 Jeffrey A Law (law@cygnus.com)
972 * mips.igen (MSUB): Fix to work like MADD.
973 * gencode.c (MSUB): Similarly.
975 start-sanitize-vr5400
976 Tue Dec 9 12:02:12 1997 Andrew Cagney <cagney@b1.cygnus.com>
978 * configure.in (sim_igen_filter): Multi-sim vr5400 - vr5000 or
982 Thu Dec 4 09:21:05 1997 Doug Evans <devans@canuck.cygnus.com>
984 * configure: Regenerated to track ../common/aclocal.m4 changes.
986 Wed Nov 26 11:00:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
988 * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
990 start-sanitize-vr5400
991 * mdmx.igen (value_vr): Correct sim_io_eprintf format argument.
992 (value_cc, store_cc): Implement.
994 * sim-main.h: Add 8*3*8 bit accumulator.
996 * vr5400.igen: Move mdmx instructins from here
997 * mdmx.igen: To here - new file. Add/fix missing instructions.
998 * mips.igen: Include mdmx.igen.
999 * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
1002 Sun Nov 23 01:45:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1004 * sim-main.h (sim-fpu.h): Include.
1006 * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1007 Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1008 using host independant sim_fpu module.
1010 Thu Nov 20 19:56:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1012 * interp.c (signal_exception): Report internal errors with SIGABRT
1015 * sim-main.h (C0_CONFIG): New register.
1016 (signal.h): No longer include.
1018 * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1020 Tue Nov 18 15:33:48 1997 Doug Evans <devans@canuck.cygnus.com>
1022 * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
1024 Fri Nov 14 11:56:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1026 * mips.igen: Tag vr5000 instructions.
1027 (ANDI): Was missing mipsIV model, fix assembler syntax.
1028 (do_c_cond_fmt): New function.
1029 (C.cond.fmt): Handle mips I-III which do not support CC field
1031 (bc1): Handle mips IV which do not have a delaed FCC separatly.
1032 (SDR): Mask paddr when BigEndianMem, not the converse as specified
1034 (DMULT, DMULTU): Force use of hosts 64bit multiplication. Handle
1035 vr5000 which saves LO in a GPR separatly.
1037 * configure.in (enable-sim-igen): For vr5000, select vr5000
1038 specific instructions.
1039 * configure: Re-generate.
1041 Wed Nov 12 14:42:52 1997 Andrew Cagney <cagney@b1.cygnus.com>
1043 * Makefile.in (SIM_OBJS): Add sim-fpu module.
1045 * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
1046 fmt_uninterpreted_64 bit cases to switch. Convert to
1049 * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
1051 * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
1052 as specified in IV3.2 spec.
1053 (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
1055 Tue Nov 11 12:38:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1057 * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
1058 (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
1059 (start-sanitize-r5900):
1060 (LWXC1, SWXC1): Delete from r5900 instruction set.
1061 (end-sanitize-r5900):
1062 (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
1063 PENDING_FILL versions of instructions. Simplify.
1065 (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
1067 (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
1069 (MTHI, MFHI): Disable code checking HI-LO.
1071 * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
1073 (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
1075 Thu Nov 6 16:36:35 1997 Andrew Cagney <cagney@b1.cygnus.com>
1077 * gencode.c (build_mips16_operands): Replace IPC with cia.
1079 * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
1080 value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
1082 (UndefinedResult): Replace function with macro/function
1084 (sim_engine_run): Don't save PC in IPC.
1086 * sim-main.h (IPC): Delete.
1088 start-sanitize-vr5400
1089 * vr5400.igen (vr): Add missing cia argument to value_fpr.
1090 (do_select): Rename function select.
1093 * interp.c (signal_exception, store_word, load_word,
1094 address_translation, load_memory, store_memory, cache_op,
1095 prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
1096 cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
1097 current instruction address - cia - argument.
1098 (sim_read, sim_write): Call address_translation directly.
1099 (sim_engine_run): Rename variable vaddr to cia.
1100 (signal_exception): Pass cia to sim_monitor
1102 * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
1103 Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
1104 COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
1106 * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
1107 * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
1110 * interp.c (signal_exception): Pass restart address to
1113 * Makefile.in (semantics.o, engine.o, support.o, itable.o,
1114 idecode.o): Add dependency.
1116 * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
1118 (DELAY_SLOT): Update NIA not PC with branch address.
1119 (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
1121 * mips.igen: Use CIA not PC in branch calculations.
1122 (illegal): Call SignalException.
1123 (BEQ, ADDIU): Fix assembler.
1125 Wed Nov 5 12:19:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1127 * m16.igen (JALX): Was missing.
1129 * configure.in (enable-sim-igen): New configuration option.
1130 * configure: Re-generate.
1132 * sim-main.h (MAX_INSNS, INSN_NAME): Define.
1134 * interp.c (load_memory, store_memory): Delete parameter RAW.
1135 (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
1136 bypassing {load,store}_memory.
1138 * sim-main.h (ByteSwapMem): Delete definition.
1140 * Makefile.in (SIM_OBJS): Add sim-memopt module.
1142 * interp.c (sim_do_command, sim_commands): Delete mips specific
1143 commands. Handled by module sim-options.
1145 * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
1146 (WITH_MODULO_MEMORY): Define.
1148 * interp.c (sim_info): Delete code printing memory size.
1150 * interp.c (mips_size): Nee sim_size, delete function.
1152 (monitor, monitor_base, monitor_size): Delete global variables.
1153 (sim_open, sim_close): Delete code creating monitor and other
1154 memory regions. Use sim-memopts module, via sim_do_commandf, to
1155 manage memory regions.
1156 (load_memory, store_memory): Use sim-core for memory model.
1158 * interp.c (address_translation): Delete all memory map code
1159 except line forcing 32 bit addresses.
1161 Wed Nov 5 11:21:11 1997 Andrew Cagney <cagney@b1.cygnus.com>
1163 * sim-main.h (WITH_TRACE): Delete definition. Enables common
1166 * interp.c (logfh, logfile): Delete globals.
1167 (sim_open, sim_close): Delete code opening & closing log file.
1168 (mips_option_handler): Delete -l and -n options.
1169 (OPTION mips_options): Ditto.
1171 * interp.c (OPTION mips_options): Rename option trace to dinero.
1172 (mips_option_handler): Update.
1174 Wed Nov 5 09:35:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1176 * interp.c (fetch_str): New function.
1177 (sim_monitor): Rewrite using sim_read & sim_write.
1178 (sim_open): Check magic number.
1179 (sim_open): Write monitor vectors into memory using sim_write.
1180 (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
1181 (sim_read, sim_write): Simplify - transfer data one byte at a
1183 (load_memory, store_memory): Clarify meaning of parameter RAW.
1185 * sim-main.h (isHOST): Defete definition.
1186 (isTARGET): Mark as depreciated.
1187 (address_translation): Delete parameter HOST.
1189 * interp.c (address_translation): Delete parameter HOST.
1192 Wed Oct 29 14:21:32 1997 Gavin Koch <gavin@cygnus.com>
1194 * gencode.c: Add tx49 configury and insns.
1195 * configure.in: Add tx49 configury.
1196 * configure: Update.
1199 Wed Oct 29 11:13:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1203 * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
1204 (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
1206 Tue Oct 28 11:06:47 1997 Andrew Cagney <cagney@b1.cygnus.com>
1208 * mips.igen: Add model filter field to records.
1210 Mon Oct 27 17:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1212 * Makefile.in (SIM_NO_CFLAGS): Define. Define WITH_IGEN=0.
1214 interp.c (sim_engine_run): Do not compile function sim_engine_run
1215 when WITH_IGEN == 1.
1217 * configure.in (sim_igen_flags, sim_m16_flags): Set according to
1218 target architecture.
1220 Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
1221 igen. Replace with configuration variables sim_igen_flags /
1224 start-sanitize-r5900
1225 * r5900.igen: New file. Copy r5900 insns here.
1227 start-sanitize-vr5400
1228 * vr5400.igen: New file.
1230 * m16.igen: New file. Copy mips16 insns here.
1231 * mips.igen: From here.
1233 Mon Oct 27 13:53:59 1997 Andrew Cagney <cagney@b1.cygnus.com>
1235 start-sanitize-vr5400
1236 * mips.igen: Tag all mipsIV instructions with vr5400 model.
1238 * configure.in: Add mips64vr5400 target.
1239 * configure: Re-generate.
1242 * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
1244 (tmp-igen, tmp-m16): Pass -I srcdir to igen.
1246 Sat Oct 25 16:51:40 1997 Gavin Koch <gavin@cygnus.com>
1248 * gencode.c (build_instruction): Follow sim_write's lead in using
1249 BigEndianMem instead of !ByteSwapMem.
1251 Fri Oct 24 17:41:49 1997 Andrew Cagney <cagney@b1.cygnus.com>
1253 * configure.in (sim_gen): Dependent on target, select type of
1254 generator. Always select old style generator.
1256 configure: Re-generate.
1258 Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
1260 (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
1261 SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
1262 IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
1263 (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
1264 SIM_@sim_gen@_*, set by autoconf.
1266 Wed Oct 22 12:52:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1268 * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
1270 * interp.c (ColdReset): Remove #ifdef HASFPU, check
1271 CURRENT_FLOATING_POINT instead.
1273 * interp.c (ifetch32): New function. Fetch 32 bit instruction.
1274 (address_translation): Raise exception InstructionFetch when
1275 translation fails and isINSTRUCTION.
1277 * interp.c (sim_open, sim_write, sim_monitor, store_word,
1278 sim_engine_run): Change type of of vaddr and paddr to
1280 (address_translation, prefetch, load_memory, store_memory,
1281 cache_op): Change type of vAddr and pAddr to address_word.
1283 * gencode.c (build_instruction): Change type of vaddr and paddr to
1286 Mon Oct 20 15:29:04 1997 Andrew Cagney <cagney@b1.cygnus.com>
1288 * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
1289 macro to obtain result of ALU op.
1291 Tue Oct 21 17:39:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1293 * interp.c (sim_info): Call profile_print.
1295 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1297 * Makefile.in (SIM_OBJS): Add sim-profile.o module.
1299 * sim-main.h (WITH_PROFILE): Do not define, defined in
1300 common/sim-config.h. Use sim-profile module.
1301 (simPROFILE): Delete defintion.
1303 * interp.c (PROFILE): Delete definition.
1304 (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
1305 (sim_close): Delete code writing profile histogram.
1306 (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
1308 (sim_engine_run): Delete code profiling the PC.
1310 Mon Oct 20 13:31:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1312 * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
1314 * interp.c (sim_monitor): Make register pointers of type
1317 * sim-main.h: Make registers of type unsigned_word not
1320 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1322 start-sanitize-r5900
1323 * sim-main.h (BYTES_IN_MMI_REGS, ..., SUB_REG_FETCH, ..., GPR_SB,
1324 ...): Move to sim-main.h
1327 * interp.c (sync_operation): Rename from SyncOperation, make
1328 global, add SD argument.
1329 (prefetch): Rename from Prefetch, make global, add SD argument.
1330 (decode_coproc): Make global.
1332 * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
1334 * gencode.c (build_instruction): Generate DecodeCoproc not
1335 decode_coproc calls.
1337 * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
1338 (SizeFGR): Move to sim-main.h
1339 (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
1340 simSIGINT, simJALDELAYSLOT): Move to sim-main.h
1341 (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
1343 (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
1344 FP_RM_TOMINF, GETRM): Move to sim-main.h.
1345 (Uncached, CachedNoncoherent, CachedCoherent, Cached,
1346 isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
1347 (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
1348 BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
1350 * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
1352 (sim-alu.h): Include.
1353 (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
1354 (sim_cia): Typedef to instruction_address.
1356 Thu Oct 16 10:31:41 1997 Andrew Cagney <cagney@b1.cygnus.com>
1358 * Makefile.in (interp.o): Rename generated file engine.c to
1363 Thu Oct 16 10:31:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
1365 * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
1367 Thu Oct 16 10:31:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1369 * gencode.c (build_instruction): For "FPSQRT", output correct
1370 number of arguments to Recip.
1372 Tue Oct 14 17:38:18 1997 Andrew Cagney <cagney@b1.cygnus.com>
1374 * Makefile.in (interp.o): Depends on sim-main.h
1376 * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
1378 * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
1379 ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
1380 (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
1381 STATE, DSSTATE): Define
1382 (GPR, FGRIDX, ..): Define.
1384 * interp.c (registers, register_widths, fpr_state, ipc, dspc,
1385 pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
1386 (GPR, FGRIDX, ...): Delete macros.
1388 * interp.c: Update names to match defines from sim-main.h
1390 Tue Oct 14 15:11:45 1997 Andrew Cagney <cagney@b1.cygnus.com>
1392 * interp.c (sim_monitor): Add SD argument.
1393 (sim_warning): Delete. Replace calls with calls to
1395 (sim_error): Delete. Replace calls with sim_io_error.
1396 (open_trace, writeout32, writeout16, getnum): Add SD argument.
1397 (mips_set_profile): Rename from sim_set_profile. Add SD argument.
1398 (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
1400 (mips_size): Rename from sim_size. Add SD argument.
1402 * interp.c (simulator): Delete global variable.
1403 (callback): Delete global variable.
1404 (mips_option_handler, sim_open, sim_write, sim_read,
1405 sim_store_register, sim_fetch_register, sim_info, sim_do_command,
1406 sim_size,sim_monitor): Use sim_io_* not callback->*.
1407 (sim_open): ZALLOC simulator struct.
1408 (PROFILE): Do not define.
1410 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1412 * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
1413 support.h with corresponding code.
1415 * sim-main.h (word64, uword64), support.h: Move definition to
1417 (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
1420 * Makefile.in: Update dependencies
1421 * interp.c: Do not include.
1423 Tue Oct 14 13:35:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1425 * interp.c (address_translation, load_memory, store_memory,
1426 cache_op): Rename to from AddressTranslation et.al., make global,
1429 * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
1432 * interp.c (SignalException): Rename to signal_exception, make
1435 * interp.c (Interrupt, ...): Move definitions to sim-main.h.
1437 * sim-main.h (SignalException, SignalExceptionInterrupt,
1438 SignalExceptionInstructionFetch, SignalExceptionAddressStore,
1439 SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
1440 SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
1443 * interp.c, support.h: Use.
1445 Tue Oct 14 13:19:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1447 * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
1448 to value_fpr / store_fpr. Add SD argument.
1449 (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
1450 Multiply, Divide, Recip, SquareRoot, Convert): Make global.
1452 * sim-main.h (ValueFPR, StoreFPR): Define.
1454 Tue Oct 14 13:06:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
1456 * interp.c (sim_engine_run): Check consistency between configure
1457 WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
1460 * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
1461 (mips_fpu): Configure WITH_FLOATING_POINT.
1462 (mips_endian): Configure WITH_TARGET_ENDIAN.
1463 * configure: Update.
1465 Fri Oct 3 09:28:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1467 * configure: Regenerated to track ../common/aclocal.m4 changes.
1469 start-sanitize-r5900
1470 Mon Aug 25 19:11:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1472 * interp.c (MAX_REG): Allow up-to 128 registers.
1473 (LO1, HI1): Define value that matches REGISTER_NAMES in gdb.
1474 (REGISTER_SA): Ditto.
1475 (sim_open): Initialize register_widths for r5900 specific
1477 (sim_fetch_register, sim_store_register): Check for request of
1478 r5900 specific SA register. Check for request for hi 64 bits of
1479 r5900 specific registers.
1482 Mon Sep 29 14:45:00 1997 Bob Manson <manson@charmed.cygnus.com>
1484 * configure: Regenerated.
1486 Fri Sep 26 12:48:18 1997 Mark Alexander <marka@cygnus.com>
1488 * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
1490 Thu Sep 25 11:15:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1492 * gencode.c (print_igen_insn_models): Assume certain architectures
1493 include all mips* instructions.
1494 (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
1497 * Makefile.in (tmp.igen): Add target. Generate igen input from
1500 * gencode.c (FEATURE_IGEN): Define.
1501 (main): Add --igen option. Generate output in igen format.
1502 (process_instructions): Format output according to igen option.
1503 (print_igen_insn_format): New function.
1504 (print_igen_insn_models): New function.
1505 (process_instructions): Only issue warnings and ignore
1506 instructions when no FEATURE_IGEN.
1508 Wed Sep 24 17:38:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1510 * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
1513 Tue Sep 23 11:04:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1515 * configure: Regenerated to track ../common/aclocal.m4 changes.
1517 Tue Sep 23 10:19:51 1997 Andrew Cagney <cagney@b1.cygnus.com>
1519 * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
1520 SIM_RESERVED_BITS): Delete, moved to common.
1521 (SIM_EXTRA_CFLAGS): Update.
1523 Mon Sep 22 11:46:20 1997 Andrew Cagney <cagney@b1.cygnus.com>
1525 * configure.in: Configure non-strict memory alignment.
1526 * configure: Regenerated to track ../common/aclocal.m4 changes.
1528 Fri Sep 19 17:45:25 1997 Andrew Cagney <cagney@b1.cygnus.com>
1530 * configure: Regenerated to track ../common/aclocal.m4 changes.
1532 Sat Sep 20 14:07:28 1997 Gavin Koch <gavin@cygnus.com>
1534 * gencode.c (SDBBP,DERET): Added (3900) insns.
1535 (RFE): Turn on for 3900.
1536 * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
1537 (dsstate): Made global.
1538 (SUBTARGET_R3900): Added.
1539 (CANCELDELAYSLOT): New.
1540 (SignalException): Ignore SystemCall rather than ignore and
1541 terminate. Add DebugBreakPoint handling.
1542 (decode_coproc): New insns RFE, DERET; and new registers Debug
1543 and DEPC protected by SUBTARGET_R3900.
1544 (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
1546 * Makefile.in,configure.in: Add mips subtarget option.
1547 * configure: Update.
1549 Fri Sep 19 09:33:27 1997 Gavin Koch <gavin@cygnus.com>
1551 * gencode.c: Add r3900 (tx39).
1554 * gencode.c: Fix some configuration problems by improving
1555 the relationship between tx19 and tx39.
1558 Tue Sep 16 15:52:04 1997 Gavin Koch <gavin@cygnus.com>
1560 * gencode.c (build_instruction): Don't need to subtract 4 for
1563 Tue Sep 16 11:32:28 1997 Gavin Koch <gavin@cygnus.com>
1565 * interp.c: Correct some HASFPU problems.
1567 Mon Sep 15 17:36:15 1997 Andrew Cagney <cagney@b1.cygnus.com>
1569 * configure: Regenerated to track ../common/aclocal.m4 changes.
1571 Fri Sep 12 12:01:39 1997 Andrew Cagney <cagney@b1.cygnus.com>
1573 * interp.c (mips_options): Fix samples option short form, should
1576 Thu Sep 11 09:35:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1578 * interp.c (sim_info): Enable info code. Was just returning.
1580 Tue Sep 9 17:30:57 1997 Andrew Cagney <cagney@b1.cygnus.com>
1582 * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
1585 Tue Sep 9 16:28:28 1997 Andrew Cagney <cagney@b1.cygnus.com>
1587 * gencode.c (build_instruction): Use SIGNED64 for 64 bit
1589 (build_instruction): Ditto for LL.
1592 Sun Sep 7 16:05:46 1997 Gavin Koch <gavin@cygnus.com>
1594 * mips/configure.in, mips/gencode: Add tx19/r1900.
1597 Thu Sep 4 17:21:23 1997 Doug Evans <dje@seba>
1599 * configure: Regenerated to track ../common/aclocal.m4 changes.
1601 start-sanitize-r5900
1602 Mon Sep 1 18:43:30 1997 Andrew Cagney <cagney@b1.cygnus.com>
1604 * gencode.c (build_instruction): For "pabsw" and "pabsh", check
1605 for overflow due to ABS of MININT, set result to MAXINT.
1606 (build_instruction): For "psrlvw", signextend bit 31.
1609 Wed Aug 27 18:13:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1611 * configure: Regenerated to track ../common/aclocal.m4 changes.
1614 Wed Aug 27 14:12:27 1997 Andrew Cagney <cagney@b1.cygnus.com>
1616 * interp.c (sim_open): Add call to sim_analyze_program, update
1619 Tue Aug 26 10:40:07 1997 Andrew Cagney <cagney@b1.cygnus.com>
1621 * interp.c (sim_kill): Delete.
1622 (sim_create_inferior): Add ABFD argument. Set PC from same.
1623 (sim_load): Move code initializing trap handlers from here.
1624 (sim_open): To here.
1625 (sim_load): Delete, use sim-hload.c.
1627 * Makefile.in (SIM_OBJS): Add sim-hload.o module.
1629 Mon Aug 25 17:50:22 1997 Andrew Cagney <cagney@b1.cygnus.com>
1631 * configure: Regenerated to track ../common/aclocal.m4 changes.
1634 Mon Aug 25 15:59:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1636 * interp.c (sim_open): Add ABFD argument.
1637 (sim_load): Move call to sim_config from here.
1638 (sim_open): To here. Check return status.
1640 start-sanitize-r5900
1641 * gencode.c (build_instruction): Do not define x8000000000000000,
1642 x7FFFFFFFFFFFFFFF, or xFFFFFFFF80000000.
1645 start-sanitize-r5900
1646 Mon Jul 28 19:49:29 1997 Andrew Cagney <cagney@b1.cygnus.com>
1648 * gencode.c (build_instruction): For "pdivw", "pdivbw" and
1649 "pdivuw" check for overflow due to signed divide by -1.
1652 Fri Jul 25 15:00:45 1997 Gavin Koch <gavin@cygnus.com>
1654 * gencode.c (build_instruction): Two arg MADD should
1655 not assign result to $0.
1657 start-sanitize-r5900
1658 Thu Jul 10 11:58:48 1997 Andrew Cagney <cagney@critters.cygnus.com>
1660 * gencode.c (build_instruction): For "ppac5" use unsigned
1661 arrithmetic so that the sign bit doesn't smear when right shifted.
1662 (build_instruction): For "pdiv" perform sign extension when
1663 storing results in HI and LO.
1664 (build_instructions): For "pdiv" and "pdivbw" check for
1666 (build_instruction): For "pmfhl.slw" update hi part of dest
1667 register as well as low part.
1668 (build_instruction): For "pmfhl" portably handle long long values.
1669 (build_instruction): For "pmfhl.sh" correctly negative values.
1670 Store half words 2 and three in the correct place.
1671 (build_instruction): For "psllvw", sign extend value after shift.
1674 Thu Jun 26 12:13:17 1997 Angela Marie Thomas (angela@cygnus.com)
1676 * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
1677 * sim/mips/configure.in: Regenerate.
1679 Wed Jul 9 10:29:21 1997 Andrew Cagney <cagney@critters.cygnus.com>
1681 * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
1682 signed8, unsigned8 et.al. types.
1684 start-sanitize-r5900
1685 * gencode.c (build_instruction): For PMULTU* do not sign extend
1686 registers. Make generated code easier to debug.
1689 * interp.c (SUB_REG_FETCH): Handle both little and big endian
1690 hosts when selecting subreg.
1692 start-sanitize-r5900
1693 Tue Jul 8 18:07:20 1997 Andrew Cagney <cagney@andros.cygnus.com>
1695 * gencode.c (type_for_data_len): For 32bit operations concerned
1696 with overflow, perform op using 64bits.
1697 (build_instruction): For PADD, always compute operation using type
1698 returned by type_for_data_len.
1699 (build_instruction): For PSUBU, when overflow, saturate to zero as
1703 Wed Jul 2 11:54:10 1997 Jeffrey A Law (law@cygnus.com)
1705 start-sanitize-r5900
1706 * gencode.c (build_instruction): Handle "pext5" according to
1707 version 1.95 of the r5900 ISA.
1709 * gencode.c (build_instruction): Handle "ppac5" according to
1710 version 1.95 of the r5900 ISA.
1713 * interp.c (sim_engine_run): Reset the ZERO register to zero
1714 regardless of FEATURE_WARN_ZERO.
1715 * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
1717 Wed Jun 4 10:43:14 1997 Andrew Cagney <cagney@b1.cygnus.com>
1719 * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
1720 (SignalException): For BreakPoints ignore any mode bits and just
1722 (SignalException): Always set the CAUSE register.
1724 Tue Jun 3 05:00:33 1997 Andrew Cagney <cagney@b1.cygnus.com>
1726 * interp.c (SignalException): Clear the simDELAYSLOT flag when an
1727 exception has been taken.
1729 * interp.c: Implement the ERET and mt/f sr instructions.
1731 start-sanitize-r5900
1732 Mon Jun 2 23:28:19 1997 Andrew Cagney <cagney@b1.cygnus.com>
1734 * gencode.c (build_instruction): For paddu, extract unsigned
1737 * gencode.c (build_instruction): Saturate padds instead of padd
1741 Sat May 31 00:44:16 1997 Andrew Cagney <cagney@b1.cygnus.com>
1743 * interp.c (SignalException): Don't bother restarting an
1746 Fri May 30 23:41:48 1997 Andrew Cagney <cagney@b1.cygnus.com>
1748 * interp.c (SignalException): Really take an interrupt.
1749 (interrupt_event): Only deliver interrupts when enabled.
1751 Tue May 27 20:08:06 1997 Andrew Cagney <cagney@b1.cygnus.com>
1753 * interp.c (sim_info): Only print info when verbose.
1754 (sim_info) Use sim_io_printf for output.
1756 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1758 * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
1761 Tue May 27 14:22:23 1997 Andrew Cagney <cagney@b1.cygnus.com>
1763 * interp.c (sim_do_command): Check for common commands if a
1764 simulator specific command fails.
1766 Thu May 22 09:32:03 1997 Gavin Koch <gavin@cygnus.com>
1768 * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
1769 and simBE when DEBUG is defined.
1771 Wed May 21 09:08:10 1997 Andrew Cagney <cagney@b1.cygnus.com>
1773 * interp.c (interrupt_event): New function. Pass exception event
1774 onto exception handler.
1776 * configure.in: Check for stdlib.h.
1777 * configure: Regenerate.
1779 * gencode.c (build_instruction): Add UNUSED attribute to tempS
1780 variable declaration.
1781 (build_instruction): Initialize memval1.
1782 (build_instruction): Add UNUSED attribute to byte, bigend,
1784 (build_operands): Ditto.
1786 * interp.c: Fix GCC warnings.
1787 (sim_get_quit_code): Delete.
1789 * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
1790 * Makefile.in: Ditto.
1791 * configure: Re-generate.
1793 * Makefile.in (SIM_OBJS): Add sim-watch.o module.
1795 Tue May 20 15:08:56 1997 Andrew Cagney <cagney@b1.cygnus.com>
1797 * interp.c (mips_option_handler): New function parse argumes using
1799 (myname): Replace with STATE_MY_NAME.
1800 (sim_open): Delete check for host endianness - performed by
1802 (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
1803 (sim_open): Move much of the initialization from here.
1804 (sim_load): To here. After the image has been loaded and
1806 (sim_open): Move ColdReset from here.
1807 (sim_create_inferior): To here.
1808 (sim_open): Make FP check less dependant on host endianness.
1810 * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
1812 * interp.c (sim_set_callbacks): Delete.
1814 * interp.c (membank, membank_base, membank_size): Replace with
1815 STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
1816 (sim_open): Remove call to callback->init. gdb/run do this.
1820 * sim-main.h (SIM_HAVE_FLATMEM): Define.
1822 * interp.c (big_endian_p): Delete, replaced by
1823 current_target_byte_order.
1825 Tue May 20 13:55:00 1997 Andrew Cagney <cagney@b1.cygnus.com>
1827 * interp.c (host_read_long, host_read_word, host_swap_word,
1828 host_swap_long): Delete. Using common sim-endian.
1829 (sim_fetch_register, sim_store_register): Use H2T.
1830 (pipeline_ticks): Delete. Handled by sim-events.
1832 (sim_engine_run): Update.
1834 Tue May 20 13:42:03 1997 Andrew Cagney <cagney@b1.cygnus.com>
1836 * interp.c (sim_stop_reason): Move code determining simEXCEPTION
1838 (SignalException): To here. Signal using sim_engine_halt.
1839 (sim_stop_reason): Delete, moved to common.
1841 Tue May 20 10:19:48 1997 Andrew Cagney <cagney@b2.cygnus.com>
1843 * interp.c (sim_open): Add callback argument.
1844 (sim_set_callbacks): Delete SIM_DESC argument.
1847 Mon May 19 18:20:38 1997 Andrew Cagney <cagney@b1.cygnus.com>
1849 * Makefile.in (SIM_OBJS): Add common modules.
1851 * interp.c (sim_set_callbacks): Also set SD callback.
1852 (set_endianness, xfer_*, swap_*): Delete.
1853 (host_read_word, host_read_long, host_swap_word, host_swap_long):
1854 Change to functions using sim-endian macros.
1855 (control_c, sim_stop): Delete, use common version.
1856 (simulate): Convert into.
1857 (sim_engine_run): This function.
1858 (sim_resume): Delete.
1860 * interp.c (simulation): New variable - the simulator object.
1861 (sim_kind): Delete global - merged into simulation.
1862 (sim_load): Cleanup. Move PC assignment from here.
1863 (sim_create_inferior): To here.
1865 * sim-main.h: New file.
1866 * interp.c (sim-main.h): Include.
1868 Thu Apr 24 00:39:51 1997 Doug Evans <dje@canuck.cygnus.com>
1870 * configure: Regenerated to track ../common/aclocal.m4 changes.
1872 Wed Apr 23 17:32:19 1997 Doug Evans <dje@canuck.cygnus.com>
1874 * tconfig.in (SIM_HAVE_BIENDIAN): Define.
1876 Mon Apr 21 17:16:13 1997 Gavin Koch <gavin@cygnus.com>
1878 * gencode.c (build_instruction): DIV instructions: check
1879 for division by zero and integer overflow before using
1880 host's division operation.
1882 Thu Apr 17 03:18:14 1997 Doug Evans <dje@canuck.cygnus.com>
1884 * Makefile.in (SIM_OBJS): Add sim-load.o.
1885 * interp.c: #include bfd.h.
1886 (target_byte_order): Delete.
1887 (sim_kind, myname, big_endian_p): New static locals.
1888 (sim_open): Set sim_kind, myname. Move call to set_endianness to
1889 after argument parsing. Recognize -E arg, set endianness accordingly.
1890 (sim_load): Return SIM_RC. New arg abfd. Call sim_load_file to
1891 load file into simulator. Set PC from bfd.
1892 (sim_create_inferior): Return SIM_RC. Delete arg start_address.
1893 (set_endianness): Use big_endian_p instead of target_byte_order.
1895 Wed Apr 16 17:55:37 1997 Andrew Cagney <cagney@b1.cygnus.com>
1897 * interp.c (sim_size): Delete prototype - conflicts with
1898 definition in remote-sim.h. Correct definition.
1900 Mon Apr 7 15:45:02 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1902 * configure: Regenerated to track ../common/aclocal.m4 changes.
1905 Wed Apr 2 15:06:28 1997 Doug Evans <dje@canuck.cygnus.com>
1907 * interp.c (sim_open): New arg `kind'.
1909 * configure: Regenerated to track ../common/aclocal.m4 changes.
1911 Wed Apr 2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1913 * configure: Regenerated to track ../common/aclocal.m4 changes.
1915 Tue Mar 25 11:38:22 1997 Doug Evans <dje@canuck.cygnus.com>
1917 * interp.c (sim_open): Set optind to 0 before calling getopt.
1919 Wed Mar 19 01:14:00 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1921 * configure: Regenerated to track ../common/aclocal.m4 changes.
1923 Mon Mar 17 10:52:59 1997 Gavin Koch <gavin@cetus.cygnus.com>
1925 * interp.c : Replace uses of pr_addr with pr_uword64
1926 where the bit length is always 64 independent of SIM_ADDR.
1927 (pr_uword64) : added.
1929 Mon Mar 17 15:10:07 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
1931 * configure: Re-generate.
1933 Fri Mar 14 10:34:11 1997 Michael Meissner <meissner@cygnus.com>
1935 * configure: Regenerate to track ../common/aclocal.m4 changes.
1937 Thu Mar 13 12:51:36 1997 Doug Evans <dje@canuck.cygnus.com>
1939 * interp.c (sim_open): New SIM_DESC result. Argument is now
1941 (other sim_*): New SIM_DESC argument.
1943 start-sanitize-r5900
1944 Wed Feb 26 18:32:21 1997 Gavin Koch <gavin@cygnus.com>
1946 * gencode.c (POP_AND,POP_OR,POP_NOR,POP_XOR):
1947 Change values to avoid overloading DOUBLEWORD which is tested
1949 * gencode.c: reinstate "offending code".
1952 Mon Feb 24 22:47:14 1997 Dawn Perchik <dawn@cygnus.com>
1954 * interp.c: Fix printing of addresses for non-64-bit targets.
1955 (pr_addr): Add function to print address based on size.
1956 start-sanitize-r5900
1957 * gencode.c: #ifdef out offending code until a permanent fix
1958 can be added. Code is causing build errors for non-5900 mips targets.
1961 start-sanitize-r5900
1962 Thu Feb 20 10:40:24 1997 Gavin Koch <gavin@cetus.cygnus.com>
1964 * gencode.c (process_instructions): Correct test for ISA dependent
1965 architecture bits in isa field of MIPS_DECODE.
1968 Wed Feb 19 14:42:09 1997 Mark Alexander <marka@cygnus.com>
1970 * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
1972 start-sanitize-r5900
1973 Tue Feb 18 17:03:47 1997 Gavin Koch <gavin@cygnus.com>
1975 * gencode.c (MIPS_DECODE): Correct instruction feature flags for
1979 Thu Feb 13 14:08:30 1997 Ian Lance Taylor <ian@cygnus.com>
1981 * gencode.c (build_mips16_operands): Correct computation of base
1982 address for extended PC relative instruction.
1984 start-sanitize-r5900
1985 Fri Feb 7 11:12:44 1997 Gavin Koch <gavin@cygnus.com>
1987 * Makefile.in, configure, configure.in, gencode.c,
1988 interp.c, support.h: add r5900.
1991 Thu Feb 6 17:16:15 1997 Ian Lance Taylor <ian@cygnus.com>
1993 * interp.c (mips16_entry): Add support for floating point cases.
1994 (SignalException): Pass floating point cases to mips16_entry.
1995 (ValueFPR): Don't restrict fmt_single and fmt_word to even
1997 (StoreFPR): Likewise. Also, don't clobber fpr + 1 for fmt_single
1999 (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2000 and then set the state to fmt_uninterpreted.
2001 (COP_SW): Temporarily set the state to fmt_word while calling
2004 Tue Feb 4 16:48:25 1997 Ian Lance Taylor <ian@cygnus.com>
2006 * gencode.c (build_instruction): The high order may be set in the
2007 comparison flags at any ISA level, not just ISA 4.
2009 Tue Feb 4 13:33:30 1997 Doug Evans <dje@canuck.cygnus.com>
2011 * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2012 COMMON_{PRE,POST}_CONFIG_FRAG instead.
2013 * configure.in: sinclude ../common/aclocal.m4.
2014 * configure: Regenerated.
2016 Fri Jan 31 11:11:45 1997 Ian Lance Taylor <ian@cygnus.com>
2018 * configure: Rebuild after change to aclocal.m4.
2020 Thu Jan 23 11:46:23 1997 Stu Grossman (grossman@critters.cygnus.com)
2022 * configure configure.in Makefile.in: Update to new configure
2023 scheme which is more compatible with WinGDB builds.
2024 * configure.in: Improve comment on how to run autoconf.
2025 * configure: Re-run autoconf to get new ../common/aclocal.m4.
2026 * Makefile.in: Use autoconf substitution to install common
2029 Wed Jan 8 12:39:03 1997 Jim Wilson <wilson@cygnus.com>
2031 * gencode.c (build_instruction): Use BigEndianCPU instead of
2034 Thu Jan 02 22:23:04 1997 Mark Alexander <marka@cygnus.com>
2036 * interp.c (sim_monitor): Make output to stdout visible in
2037 wingdb's I/O log window.
2039 Tue Dec 31 07:04:00 1996 Mark Alexander <marka@cygnus.com>
2041 * support.h: Undo previous change to SIGTRAP
2044 Mon Dec 30 17:36:06 1996 Ian Lance Taylor <ian@cygnus.com>
2046 * interp.c (store_word, load_word): New static functions.
2047 (mips16_entry): New static function.
2048 (SignalException): Look for mips16 entry and exit instructions.
2049 (simulate): Use the correct index when setting fpr_state after
2050 doing a pending move.
2052 Sun Dec 29 09:37:18 1996 Mark Alexander <marka@cygnus.com>
2054 * interp.c: Fix byte-swapping code throughout to work on
2055 both little- and big-endian hosts.
2057 Sun Dec 29 09:18:32 1996 Mark Alexander <marka@cygnus.com>
2059 * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2060 with gdb/config/i386/xm-windows.h.
2062 Fri Dec 27 22:48:51 1996 Mark Alexander <marka@cygnus.com>
2064 * gencode.c (build_instruction): Work around MSVC++ code gen bug
2065 that messes up arithmetic shifts.
2067 Fri Dec 20 11:04:05 1996 Stu Grossman (grossman@critters.cygnus.com)
2069 * support.h: Use _WIN32 instead of __WIN32__. Also add defs for
2070 SIGTRAP and SIGQUIT for _WIN32.
2072 Thu Dec 19 14:07:27 1996 Ian Lance Taylor <ian@cygnus.com>
2074 * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2075 force a 64 bit multiplication.
2076 (build_instruction) [OR]: In mips16 mode, don't do anything if the
2077 destination register is 0, since that is the default mips16 nop
2080 Mon Dec 16 14:59:38 1996 Ian Lance Taylor <ian@cygnus.com>
2082 * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2083 (build_endian_shift): Don't check proc64.
2084 (build_instruction): Always set memval to uword64. Cast op2 to
2085 uword64 when shifting it left in memory instructions. Always use
2086 the same code for stores--don't special case proc64.
2088 * gencode.c (build_mips16_operands): Fix base PC value for PC
2090 (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2092 * interp.c (simJALDELAYSLOT): Define.
2093 (JALDELAYSLOT): Define.
2094 (INDELAYSLOT, INJALDELAYSLOT): Define.
2095 (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2097 Tue Dec 24 22:11:20 1996 Angela Marie Thomas (angela@cygnus.com)
2099 * interp.c (sim_open): add flush_cache as a PMON routine
2100 (sim_monitor): handle flush_cache by ignoring it
2102 Wed Dec 11 13:53:51 1996 Jim Wilson <wilson@cygnus.com>
2104 * gencode.c (build_instruction): Use !ByteSwapMem instead of
2106 * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2107 (BigEndianMem): Rename to ByteSwapMem and change sense.
2108 (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2109 BigEndianMem references to !ByteSwapMem.
2110 (set_endianness): New function, with prototype.
2111 (sim_open): Call set_endianness.
2112 (sim_info): Use simBE instead of BigEndianMem.
2113 (xfer_direct_word, xfer_direct_long, swap_direct_word,
2114 swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2115 xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2116 ifdefs, keeping the prototype declaration.
2117 (swap_word): Rewrite correctly.
2118 (ColdReset): Delete references to CONFIG. Delete endianness related
2119 code; moved to set_endianness.
2121 Tue Dec 10 11:32:04 1996 Jim Wilson <wilson@cygnus.com>
2123 * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2124 * interp.c (CHECKHILO): Define away.
2125 (simSIGINT): New macro.
2126 (membank_size): Increase from 1MB to 2MB.
2127 (control_c): New function.
2128 (sim_resume): Rename parameter signal to signal_number. Add local
2129 variable prev. Call signal before and after simulate.
2130 (sim_stop_reason): Add simSIGINT support.
2131 (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2133 (sim_warning): Delete call to SignalException. Do call printf_filtered
2135 (AddressTranslation): Add #ifdef DEBUG around debugging message and
2136 a call to sim_warning.
2138 Wed Nov 27 11:53:50 1996 Ian Lance Taylor <ian@cygnus.com>
2140 * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2141 16 bit instructions.
2143 Tue Nov 26 11:53:12 1996 Ian Lance Taylor <ian@cygnus.com>
2145 Add support for mips16 (16 bit MIPS implementation):
2146 * gencode.c (inst_type): Add mips16 instruction encoding types.
2147 (GETDATASIZEINSN): Define.
2148 (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv. Add
2149 jalx. Add LEFT flag to mfhi and mflo. Add RIGHT flag to mthi and
2151 (MIPS16_DECODE): New table, for mips16 instructions.
2152 (bitmap_val): New static function.
2153 (struct mips16_op): Define.
2154 (mips16_op_table): New table, for mips16 operands.
2155 (build_mips16_operands): New static function.
2156 (process_instructions): If PC is odd, decode a mips16
2157 instruction. Break out instruction handling into new
2158 build_instruction function.
2159 (build_instruction): New static function, broken out of
2160 process_instructions. Check modifiers rather than flags for SHIFT
2161 bit count and m[ft]{hi,lo} direction.
2162 (usage): Pass program name to fprintf.
2163 (main): Remove unused variable this_option_optind. Change
2164 ``*loptarg++'' to ``loptarg++''.
2165 (my_strtoul): Parenthesize && within ||.
2166 * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2167 (simulate): If PC is odd, fetch a 16 bit instruction, and
2168 increment PC by 2 rather than 4.
2169 * configure.in: Add case for mips16*-*-*.
2170 * configure: Rebuild.
2172 Fri Nov 22 08:49:36 1996 Mark Alexander <marka@cygnus.com>
2174 * interp.c: Allow -t to enable tracing in standalone simulator.
2175 Fix garbage output in trace file and error messages.
2177 Wed Nov 20 01:54:37 1996 Doug Evans <dje@canuck.cygnus.com>
2179 * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2180 (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2181 * configure.in: Simplify using macros in ../common/aclocal.m4.
2182 * configure: Regenerated.
2183 * tconfig.in: New file.
2185 Tue Nov 12 13:34:00 1996 Dawn Perchik <dawn@cygnus.com>
2187 * interp.c: Fix bugs in 64-bit port.
2188 Use ansi function declarations for msvc compiler.
2189 Initialize and test file pointer in trace code.
2190 Prevent duplicate definition of LAST_EMED_REGNUM.
2192 Tue Oct 15 11:07:06 1996 Mark Alexander <marka@cygnus.com>
2194 * interp.c (xfer_big_long): Prevent unwanted sign extension.
2196 Thu Sep 26 17:35:00 1996 James G. Smith <jsmith@cygnus.co.uk>
2198 * interp.c (SignalException): Check for explicit terminating
2200 * gencode.c: Pass instruction value through SignalException()
2201 calls for Trap, Breakpoint and Syscall.
2203 Thu Sep 26 11:35:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2205 * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
2206 only used on those hosts that provide it.
2207 * configure.in: Add sqrt() to list of functions to be checked for.
2208 * config.in: Re-generated.
2209 * configure: Re-generated.
2211 Fri Sep 20 15:47:12 1996 Ian Lance Taylor <ian@cygnus.com>
2213 * gencode.c (process_instructions): Call build_endian_shift when
2214 expanding STORE RIGHT, to fix swr.
2215 * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
2216 clear the high bits.
2217 * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
2218 Fix float to int conversions to produce signed values.
2220 Thu Sep 19 15:34:17 1996 Ian Lance Taylor <ian@cygnus.com>
2222 * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
2223 (process_instructions): Correct handling of nor instruction.
2224 Correct shift count for 32 bit shift instructions. Correct sign
2225 extension for arithmetic shifts to not shift the number of bits in
2226 the type. Fix 64 bit multiply high word calculation. Fix 32 bit
2227 unsigned multiply. Fix ldxc1 and friends to use coprocessor 1.
2229 * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
2230 It's OK to have a mult follow a mult. What's not OK is to have a
2231 mult follow an mfhi.
2232 (Convert): Comment out incorrect rounding code.
2234 Mon Sep 16 11:38:16 1996 James G. Smith <jsmith@cygnus.co.uk>
2236 * interp.c (sim_monitor): Improved monitor printf
2237 simulation. Tidied up simulator warnings, and added "--log" option
2238 for directing warning message output.
2239 * gencode.c: Use sim_warning() rather than WARNING macro.
2241 Thu Aug 22 15:03:12 1996 Ian Lance Taylor <ian@cygnus.com>
2243 * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
2244 getopt1.o, rather than on gencode.c. Link objects together.
2245 Don't link against -liberty.
2246 (gencode.o, getopt.o, getopt1.o): New targets.
2247 * gencode.c: Include <ctype.h> and "ansidecl.h".
2248 (AND): Undefine after including "ansidecl.h".
2249 (ULONG_MAX): Define if not defined.
2250 (OP_*): Don't define macros; now defined in opcode/mips.h.
2251 (main): Call my_strtoul rather than strtoul.
2252 (my_strtoul): New static function.
2254 Wed Jul 17 18:12:38 1996 Stu Grossman (grossman@critters.cygnus.com)
2256 * gencode.c (process_instructions): Generate word64 and uword64
2257 instead of `long long' and `unsigned long long' data types.
2258 * interp.c: #include sysdep.h to get signals, and define default
2260 * (Convert): Work around for Visual-C++ compiler bug with type
2262 * support.h: Make things compile under Visual-C++ by using
2263 __int64 instead of `long long'. Change many refs to long long
2264 into word64/uword64 typedefs.
2266 Wed Jun 26 12:24:55 1996 Jason Molenda (crash@godzilla.cygnus.co.jp)
2268 * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
2269 INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
2271 * configure.in (AC_PREREQ): autoconf 2.5 or higher.
2272 (AC_PROG_INSTALL): Added.
2273 (AC_PROG_CC): Moved to before configure.host call.
2274 * configure: Rebuilt.
2276 Wed Jun 5 08:28:13 1996 James G. Smith <jsmith@cygnus.co.uk>
2278 * configure.in: Define @SIMCONF@ depending on mips target.
2279 * configure: Rebuild.
2280 * Makefile.in (run): Add @SIMCONF@ to control simulator
2282 * gencode.c: Change LOADDRMASK to 64bit memory model only.
2283 * interp.c: Remove some debugging, provide more detailed error
2284 messages, update memory accesses to use LOADDRMASK.
2286 Mon Jun 3 11:55:03 1996 Ian Lance Taylor <ian@cygnus.com>
2288 * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
2289 AC_CHECK_LIB, and AC_CHECK_FUNCS. Change AC_OUTPUT to set
2291 * configure: Rebuild.
2292 * config.in: New file, generated by autoheader.
2293 * interp.c: Include "config.h". Include <stdlib.h>, <string.h>,
2294 and <strings.h> if they exist. Replace #ifdef sun with #ifdef
2295 HAVE_ANINT and HAVE_AINT, as appropriate.
2296 * Makefile.in (run): Use @LIBS@ rather than -lm.
2297 (interp.o): Depend upon config.h.
2298 (Makefile): Just rebuild Makefile.
2299 (clean): Remove stamp-h.
2300 (mostlyclean): Make the same as clean, not as distclean.
2301 (config.h, stamp-h): New targets.
2303 Fri May 10 00:41:17 1996 James G. Smith <jsmith@cygnus.co.uk>
2305 * interp.c (ColdReset): Fix boolean test. Make all simulator
2308 Wed May 8 15:12:58 1996 James G. Smith <jsmith@cygnus.co.uk>
2310 * interp.c (xfer_direct_word, xfer_direct_long,
2311 swap_direct_word, swap_direct_long, xfer_big_word,
2312 xfer_big_long, xfer_little_word, xfer_little_long,
2313 swap_word,swap_long): Added.
2314 * interp.c (ColdReset): Provide function indirection to
2315 host<->simulated_target transfer routines.
2316 * interp.c (sim_store_register, sim_fetch_register): Updated to
2317 make use of indirected transfer routines.
2319 Fri Apr 19 15:48:24 1996 James G. Smith <jsmith@cygnus.co.uk>
2321 * gencode.c (process_instructions): Ensure FP ABS instruction
2323 * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
2324 system call support.
2326 Wed Apr 10 09:51:38 1996 James G. Smith <jsmith@cygnus.co.uk>
2328 * interp.c (sim_do_command): Complain if callback structure not
2331 Thu Mar 28 13:50:51 1996 James G. Smith <jsmith@cygnus.co.uk>
2333 * interp.c (Convert): Provide round-to-nearest and round-to-zero
2334 support for Sun hosts.
2335 * Makefile.in (gencode): Ensure the host compiler and libraries
2336 used for cross-hosted build.
2338 Wed Mar 27 14:42:12 1996 James G. Smith <jsmith@cygnus.co.uk>
2340 * interp.c, gencode.c: Some more (TODO) tidying.
2342 Thu Mar 7 11:19:33 1996 James G. Smith <jsmith@cygnus.co.uk>
2344 * gencode.c, interp.c: Replaced explicit long long references with
2345 WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
2346 * support.h (SET64LO, SET64HI): Macros added.
2348 Wed Feb 21 12:16:21 1996 Ian Lance Taylor <ian@cygnus.com>
2350 * configure: Regenerate with autoconf 2.7.
2352 Tue Jan 30 08:48:18 1996 Fred Fish <fnf@cygnus.com>
2354 * interp.c (LoadMemory): Enclose text following #endif in /* */.
2355 * support.h: Remove superfluous "1" from #if.
2356 * support.h (CHECKSIM): Remove stray 'a' at end of line.
2358 Mon Dec 4 11:44:40 1995 Jamie Smith <jsmith@cygnus.com>
2360 * interp.c (StoreFPR): Control UndefinedResult() call on
2361 WARN_RESULT manifest.
2363 Fri Dec 1 16:37:19 1995 James G. Smith <jsmith@cygnus.co.uk>
2365 * gencode.c: Tidied instruction decoding, and added FP instruction
2368 * interp.c: Added dineroIII, and BSD profiling support. Also
2369 run-time FP handling.
2371 Sun Oct 22 00:57:18 1995 James G. Smith <jsmith@pasanda.cygnus.co.uk>
2373 * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
2374 gencode.c, interp.c, support.h: created.