sim/mips/ChangeLog

   1 2007-06-25  Richard Sandiford  <richard@codesourcery.com>
   2
   3         * Makefile.in (m16_run.o): New rule.
   4
   5 2007-05-15  Thiemo Seufer  <ths@mips.com>
   6
   7         * mips3264r2.igen (DSHD): Fix compile warning.
   8
   9 2007-05-14  Thiemo Seufer  <ths@mips.com>
  10
  11         * mips.igen (ALNV.PS, CEIL.L.fmt, CVT.L.fmt, CVT.PS.S, CVT.S.PL,
  12         CVT.S.PU, FLOOR.L.fmt, LDXC1, LUXC1, LWXC1, MADD.fmt, MSUB.fmt,
  13         NMADD.fmt, NMSUB.fmt, PLL.PS, PLU.PS, PREFX, PUL.PS, PUU.PS,
  14         RECIP.fmt, ROUND.L.fmt, RSQRT.fmt, SWXC1, TRUNC.L.fmt): Add support
  15         for mips32r2.
  16
  17 2007-03-01  Thiemo Seufer  <ths@mips.com>
  18
  19         * mips.igen (MFHI, MFLO, MTHI, MTLO): Restore support for mips32
  20         and mips64.
  21
  22 2007-02-20  Thiemo Seufer  <ths@mips.com>
  23
  24         * dsp.igen: Update copyright notice.
  25         * dsp2.igen: Fix copyright notice.
  26
  27 2007-02-20  Thiemo Seufer  <ths@mips.com>
  28             Chao-Ying Fu  <fu@mips.com>
  29
  30         * Makefile.in (IGEN_INCLUDE): Add dsp2.igen.
  31         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
  32         Add dsp2 to sim_igen_machine.
  33         * configure: Regenerate.
  34         * dsp.igen (do_ph_op): Add MUL support when op = 2.
  35         (do_ph_mulq): New function to support mulq_rs.ph and mulq_s.ph.
  36         (mulq_rs.ph): Use do_ph_mulq.
  37         (MFHI, MFLO, MTHI, MTLO): Move these instructions to mips.igen.
  38         * mips.igen: Add dsp2 model and include dsp2.igen.
  39         (MFHI, MFLO, MTHI, MTLO): Extend these instructions for
  40         for *mips32r2, *mips64r2, *dsp.
  41         (MADD, MADDU, MSUB, MSUBU, MULT, MULTU): Extend these instructions
  42         for *mips32r2, *mips64r2, *dsp2.
  43         * dsp2.igen: New file for MIPS DSP REV 2 ASE.
  44
  45 2007-02-19  Thiemo Seufer  <ths@mips.com>
  46             Nigel Stephens  <nigel@mips.com>
  47
  48         * mips.igen (jalr.hb, jr.hb): Add decoder for mip32r2/mips64r2
  49         jumps with hazard barrier.
  50
  51 2007-02-19  Thiemo Seufer  <ths@mips.com>
  52             Nigel Stephens  <nigel@mips.com>
  53
  54         * interp.c (sim_monitor): Flush stdout and stderr file descriptors
  55         after each call to sim_io_write.
  56
  57 2007-02-19  Thiemo Seufer  <ths@mips.com>
  58             Nigel Stephens  <nigel@mips.com>
  59
  60         * interp.c (ColdReset): Set CP0 Config0 to reflect the address size
  61         supported by this simulator.
  62         (decode_coproc): Recognise additional CP0 Config registers
  63         correctly.
  64
  65 2007-02-19  Thiemo Seufer  <ths@mips.com>
  66             Nigel Stephens  <nigel@mips.com>
  67             David Ung  <davidu@mips.com>
  68
  69         * cp1.c (value_fpr): Don't inherit existing FPR_STATE for
  70         uninterpreted formats. If fmt is one of the uninterpreted types
  71         don't update the FPR_STATE. Handle fmt_uninterpreted_32 like
  72         fmt_word, and fmt_uninterpreted_64 like fmt_long.
  73         (store_fpr): When writing an invalid odd register, set the
  74         matching even register to fmt_unknown, not the following register.
  75         * interp.c (sim_open): If STATE_MEM_SIZE isn't set then set it to
  76         the the memory window at offset 0 set by --memory-size command
  77         line option.
  78         (sim_store_register): Handle storing 4 bytes to an 8 byte floating
  79         point register.
  80         (sim_fetch_register): Likewise for reading 4 bytes from an 8 byte
  81         register.
  82         (sim_monitor): When returning the memory size to the MIPS
  83         application, use the value in STATE_MEM_SIZE, not an arbitrary
  84         hardcoded value.
  85         (cop_lw): Don' mess around with FPR_STATE, just pass
  86         fmt_uninterpreted_32 to StoreFPR.
  87         (cop_sw): Similarly.
  88         (cop_ld): Pass fmt_uninterpreted_64 not fmt_uninterpreted.
  89         (cop_sd): Similarly.
  90         * mips.igen (not_word_value): Single version for mips32, mips64
  91         and mips16.
  92
  93 2007-02-19  Thiemo Seufer <ths@mips.com>
  94             Nigel Stephens  <nigel@mips.com>
  95
  96         * interp.c (MEM_SIZE): Increase default memory size from 2 to 8
  97         MBytes.
  98
  99 2007-02-17  Thiemo Seufer  <ths@mips.com>
 100
 101         * configure.ac (mips*-sde-elf*): Move in front of generic machine
 102         configuration.
 103         * configure: Regenerate.
 104
 105 2007-02-17  Thiemo Seufer  <ths@mips.com>
 106
 107         * configure.ac (mips*-sde-elf*, mipsisa32r2*-*-*, mipsisa64r2*-*-*):
 108         Add mdmx to sim_igen_machine.
 109         (mipsisa64*-*-*): Likewise. Remove dsp.
 110         (mipsisa32*-*-*): Remove dsp.
 111         * configure: Regenerate.
 112
 113 2007-02-13  Thiemo Seufer  <ths@mips.com>
 114
 115         * configure.ac: Add mips*-sde-elf* target.
 116         * configure: Regenerate.
 117
 118 2006-12-21  Hans-Peter Nilsson  <hp@axis.com>
 119
 120         * acconfig.h: Remove.
 121         * config.in, configure: Regenerate.
 122
 123 2006-11-07  Thiemo Seufer  <ths@mips.com>
 124
 125         * dsp.igen (do_w_op): Fix compiler warning.
 126
 127 2006-08-29  Thiemo Seufer  <ths@mips.com>
 128             David Ung  <davidu@mips.com>
 129
 130         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*): Add smartmips to
 131         sim_igen_machine.
 132         * configure: Regenerate.
 133         * mips.igen (model): Add smartmips.
 134         (MADDU): Increment ACX if carry.
 135         (do_mult): Clear ACX.
 136         (ROR,RORV): Add smartmips.
 137         (include): Include smartmips.igen.
 138         * sim-main.h (ACX): Set to REGISTERS[89].
 139         * smartmips.igen: New file.
 140
 141 2006-08-29  Thiemo Seufer  <ths@mips.com>
 142             David Ung  <davidu@mips.com>
 143
 144         * Makefile.in (IGEN_INCLUDE): Add missing includes for m16e.igen and
 145         mips3264r2.igen. Add missing dependency rules.
 146         * m16e.igen: Support for mips16e save/restore instructions.
 147
 148 2006-06-13  Richard Earnshaw  <rearnsha@arm.com>
 149
 150         * configure: Regenerated.
 151
 152 2006-06-05  Daniel Jacobowitz  <dan@codesourcery.com>
 153
 154         * configure: Regenerated.
 155
 156 2006-05-31  Daniel Jacobowitz  <dan@codesourcery.com>
 157
 158         * configure: Regenerated.
 159
 160 2006-05-15 Chao-ying Fu  <fu@mips.com>
 161
 162         * dsp.igen (do_ph_shift, do_w_shra): Fix bugs for rounding instructions.
 163
 164 2006-04-18  Nick Clifton  <nickc@redhat.com>
 165
 166         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Add missing break
 167         statement.
 168
 169 2006-03-29  Hans-Peter Nilsson  <hp@axis.com>
 170
 171         * configure: Regenerate.
 172
 173 2005-12-14  Chao-ying Fu  <fu@mips.com>
 174
 175         * Makefile.in (SIM_OBJS): Add dsp.o.
 176         (dsp.o): New dependency.
 177         (IGEN_INCLUDE): Add dsp.igen.
 178         * configure.ac (mipsisa32r2*-*-*, mipsisa32*-*-*, mipsisa64r2*-*-*,
 179         mipsisa64*-*-*): Add dsp to sim_igen_machine.
 180         * configure: Regenerate.
 181         * mips.igen: Add dsp model and include dsp.igen.
 182         (MFHI, MFLO, MTHI, MTLO): Remove mips32, mips32r2, mips64, mips64r2,
 183         because these instructions are extended in DSP ASE.
 184         * sim-main.h (LAST_EMBED_REGNUM): Change from 89 to 96 because of
 185         adding 6 DSP accumulator registers and 1 DSP control register.
 186         (AC0LOIDX, AC0HIIDX, AC1LOIDX, AC1HIIDX, AC2LOIDX, AC2HIIDX, AC3LOIDX,
 187         AC3HIIDX, DSPLO, DSPHI, DSPCRIDX, DSPCR, DSPCR_POS_SHIFT,
 188         DSPCR_POS_MASK, DSPCR_POS_SMASK, DSPCR_SCOUNT_SHIFT, DSPCR_SCOUNT_MASK,
 189         DSPCR_SCOUNT_SMASK, DSPCR_CARRY_SHIFT, DSPCR_CARRY_MASK,
 190         DSPCR_CARRY_SMASK, DSPCR_CARRY, DSPCR_EFI_SHIFT, DSPCR_EFI_MASK,
 191         DSPCR_EFI_SMASK, DSPCR_EFI, DSPCR_OUFLAG_SHIFT, DSPCR_OUFLAG_MASK,
 192         DSPCR_OUFLAG_SMASK, DSPCR_OUFLAG4, DSPCR_OUFLAG5, DSPCR_OUFLAG6,
 193         DSPCR_OUFLAG7, DSPCR_CCOND_SHIFT, DSPCR_CCOND_MASK,
 194         DSPCR_CCOND_SMASK): New define.
 195         (DSPLO_REGNUM, DSPHI_REGNUM): New array for DSP accumulators.
 196         * dsp.c, dsp.igen: New files for MIPS DSP ASE.
 197
 198 2005-07-08  Ian Lance Taylor  <ian@airs.com>
 199
 200         * tconfig.in (SIM_QUIET_NAN_NEGATED): Define.
 201
 202 2005-06-16  David Ung  <davidu@mips.com>
 203             Nigel Stephens  <nigel@mips.com>
 204
 205         * mips.igen: New mips16e model and include m16e.igen.
 206         (check_u64): Add mips16e tag.
 207         * m16e.igen: New file for MIPS16e instructions.
 208         * configure.ac (mipsisa32*-*-*, mipsisa32r2*-*-*, mipsisa64*-*-*,
 209         mipsisa64r2*-*-*): Change sim_gen to M16, add mips16 and mips16e
 210         models.
 211         * configure: Regenerate.
 212
 213 2005-05-26  David Ung  <davidu@mips.com>
 214
 215         * mips.igen (mips32r2, mips64r2): New ISA models.  Add new model
 216         tags to all instructions which are applicable to the new ISAs.
 217         (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Add, moved from
 218         vr.igen.
 219         * mips3264r2.igen: New file for MIPS 32/64 revision 2 specific
 220         instructions.
 221         * vr.igen (do_ror, do_dror, ROR, RORV, DROR, DROR32, DRORV): Move
 222         to mips.igen.
 223         * configure.ac (mipsisa32r2*-*-*, mipsisa64r2*-*-*): Add new targets.
 224         * configure: Regenerate.
 225
 226 2005-03-23  Mark Kettenis  <kettenis@gnu.org>
 227
 228         * configure: Regenerate.
 229
 230 2005-01-14  Andrew Cagney  <cagney@gnu.org>
 231
 232         * configure.ac: Sinclude aclocal.m4 before common.m4.  Add
 233         explicit call to AC_CONFIG_HEADER.
 234         * configure: Regenerate.
 235
 236 2005-01-12  Andrew Cagney  <cagney@gnu.org>
 237
 238         * configure.ac: Update to use ../common/common.m4.
 239         * configure: Re-generate.
 240
 241 2005-01-11  Andrew Cagney  <cagney@localhost.localdomain>
 242
 243         * configure: Regenerated to track ../common/aclocal.m4 changes.
 244
 245 2005-01-07  Andrew Cagney  <cagney@gnu.org>
 246
 247         * configure.ac: Rename configure.in, require autoconf 2.59.
 248         * configure: Re-generate.
 249
 250 2004-12-08  Hans-Peter Nilsson  <hp@axis.com>
 251
 252         * configure: Regenerate for ../common/aclocal.m4 update.
 253
 254 2004-09-24  Monika Chaddha  <monika@acmet.com>
 255
 256         Committed by Andrew Cagney.
 257         * m16.igen (CMP, CMPI): Fix assembler.
 258
 259 2004-08-18  Chris Demetriou  <cgd@broadcom.com>
 260
 261         * configure.in (mipsisa64sb1*-*-*): Add mips3d to sim_igen_machine.
 262         * configure: Regenerate.
 263
 264 2004-06-25  Chris Demetriou  <cgd@broadcom.com>
 265
 266         * configure.in (sim_m16_machine): Include mipsIII.
 267         * configure: Regenerate.
 268
 269 2004-05-11  Maciej W. Rozycki  <macro@ds2.pg.gda.pl>
 270
 271         * mips/interp.c (decode_coproc): Sign-extend the address retrieved
 272         from COP0_BADVADDR.
 273         * mips/sim-main.h (COP0_BADVADDR): Remove a cast.
 274
 275 2004-04-10  Chris Demetriou  <cgd@broadcom.com>
 276
 277         * sb1.igen (DIV.PS, RECIP.PS, RSQRT.PS, SQRT.PS): New.
 278
 279 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 280
 281         * mips.igen (check_fmt): Remove.
 282         (ABS.fmt, ADD.fmt, C.cond.fmta, C.cond.fmtb, CEIL.L.fmt, CEIL.W)
 283         (CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt, FLOOR.L.fmt)
 284         (FLOOR.W.fmt, MADD.fmt, MOV.fmt, MOVtf.fmt, MOVN.fmt, MOVZ.fmt)
 285         (MSUB.fmt, MUL.fmt, NEG.fmt, NMADD.fmt, NMSUB.fmt, RECIP.fmt)
 286         (ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt)
 287         (TRUNC.L.fmt, TRUNC.W): Explicitly specify allowed FPU formats.
 288         (check_fmt_p, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 289         (FLOOR.W.fmt, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt)
 290         (SQRT.fmt, TRUNC.L.fmt, TRUNC.W): Remove all uses of check_fmt.
 291         (C.cnd.fmta): Remove incorrect call to check_fmt_p.
 292
 293 2004-04-09  Chris Demetriou  <cgd@broadcom.com>
 294
 295         * sb1.igen (check_sbx): New function.
 296         (PABSDIFF.fmt, PABSDIFC.fmt, PAVG.fmt): Use check_sbx.
 297
 298 2004-03-29  Chris Demetriou  <cgd@broadcom.com>
 299             Richard Sandiford  <rsandifo@redhat.com>
 300
 301         * sim-main.h (MIPS_MACH_HAS_MT_HILO_HAZARD)
 302         (MIPS_MACH_HAS_MULT_HILO_HAZARD, MIPS_MACH_HAS_DIV_HILO_HAZARD): New.
 303         * mips.igen (check_mt_hilo, check_mult_hilo, check_div_hilo): Provide
 304         separate implementations for mipsIV and mipsV.  Use new macros to
 305         determine whether the restrictions apply.
 306
 307 2004-01-19  Chris Demetriou  <cgd@broadcom.com>
 308
 309         * mips.igen (check_mf_cycles, check_mt_hilo, check_mf_hilo)
 310         (check_mult_hilo): Improve comments.
 311         (check_div_hilo): Likewise.  Also, fork off a new version
 312         to handle mips32/mips64 (since there are no hazards to check
 313         in MIPS32/MIPS64).
 314
 315 2003-06-17  Richard Sandiford  <rsandifo@redhat.com>
 316
 317         * mips.igen (do_dmultx): Fix check for negative operands.
 318
 319 2003-05-16  Ian Lance Taylor  <ian@airs.com>
 320
 321         * Makefile.in (SHELL): Make sure this is defined.
 322         (various): Use $(SHELL) whenever we invoke move-if-change.
 323
 324 2003-05-03  Chris Demetriou  <cgd@broadcom.com>
 325
 326         * cp1.c: Tweak attribution slightly.
 327         * cp1.h: Likewise.
 328         * mdmx.c: Likewise.
 329         * mdmx.igen: Likewise.
 330         * mips3d.igen: Likewise.
 331         * sb1.igen: Likewise.
 332
 333 2003-04-15  Richard Sandiford  <rsandifo@redhat.com>
 334
 335         * vr.igen (do_vr_mul_op): Zero-extend the low 32 bits of
 336         unsigned operands.
 337
 338 2003-02-27  Andrew Cagney  <cagney@redhat.com>
 339
 340         * interp.c (sim_open): Rename _bfd to bfd.
 341         (sim_create_inferior): Ditto.
 342
 343 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 344
 345         * mips.igen (LUXC1, SUXC1): New, for mipsV and mips64.
 346
 347 2003-01-14  Chris Demetriou  <cgd@broadcom.com>
 348
 349         * mips.igen (EI, DI): Remove.
 350
 351 2003-01-05  Richard Sandiford  <rsandifo@redhat.com>
 352
 353         * Makefile.in (tmp-run-multi): Fix mips16 filter.
 354
 355 2003-01-04  Richard Sandiford  <rsandifo@redhat.com>
 356             Andrew Cagney  <ac131313@redhat.com>
 357             Gavin Romig-Koch  <gavin@redhat.com>
 358             Graydon Hoare  <graydon@redhat.com>
 359             Aldy Hernandez  <aldyh@redhat.com>
 360             Dave Brolley  <brolley@redhat.com>
 361             Chris Demetriou  <cgd@broadcom.com>
 362
 363         * configure.in (mips64vr*): Define TARGET_ENABLE_FR to 1.
 364         (sim_mach_default): New variable.
 365         (mips64vr-*-*, mips64vrel-*-*): New configurations.
 366         Add a new simulator generator, MULTI.
 367         * configure: Regenerate.
 368         * Makefile.in (SIM_MULTI_OBJ, SIM_EXTRA_DISTCLEAN): New variables.
 369         (multi-run.o): New dependency.
 370         (SIM_MULTI_ALL, SIM_MULTI_IGEN_CONFIGS): New variables.
 371         (tmp-mach-multi, tmp-itable-multi, tmp-run-multi): New rules.
 372         (tmp-multi): Combine them.
 373         (BUILT_SRC_FROM_MULTI): New variable.  Depend on tmp-multi.
 374         (clean-extra): Remove sources in BUILT_SRC_FROM_MULTI.
 375         (distclean-extra): New rule.
 376         * sim-main.h: Include bfd.h.
 377         (MIPS_MACH): New macro.
 378         * mips.igen (vr4120, vr5400, vr5500): New models.
 379         (clo, clz, dclo, dclz, madd, maddu, msub, msub, mul): Add *vr5500.
 380         * vr.igen: Replace with new version.
 381
 382 2003-01-04  Chris Demetriou  <cgd@broadcom.com>
 383
 384         * configure.in: Use SIM_AC_OPTION_RESERVED_BITS(1).
 385         * configure: Regenerate.
 386
 387 2002-12-31  Chris Demetriou  <cgd@broadcom.com>
 388
 389         * sim-main.h (check_branch_bug, mark_branch_bug): Remove.
 390         * mips.igen: Remove all invocations of check_branch_bug and
 391         mark_branch_bug.
 392
 393 2002-12-16  Chris Demetriou  <cgd@broadcom.com>
 394
 395         * tconfig.in: Include "gdb/callback.h" and "gdb/remote-sim.h".
 396
 397 2002-07-30  Chris Demetriou  <cgd@broadcom.com>
 398
 399         * mips.igen (do_load_double, do_store_double): New functions.
 400         (LDC1, SDC1): Rename to...
 401         (LDC1b, SDC1b): respectively.
 402         (LDC1a, SDC1a): New instructions for MIPS II and MIPS32 support.
 403
 404 2002-07-29  Michael Snyder  <msnyder@redhat.com>
 405
 406         * cp1.c (fp_recip2): Modify initialization expression so that
 407         GCC will recognize it as constant.
 408
 409 2002-06-18  Chris Demetriou  <cgd@broadcom.com>
 410
 411         * mdmx.c (SD_): Delete.
 412         (Unpredictable): Re-define, for now, to directly invoke
 413         unpredictable_action().
 414         (mdmx_acc_op): Fix error in .ob immediate handling.
 415
 416 2002-06-18  Andrew Cagney  <cagney@redhat.com>
 417
 418         * interp.c (sim_firmware_command): Initialize `address'.
 419
 420 2002-06-16  Andrew Cagney  <ac131313@redhat.com>
 421
 422         * configure: Regenerated to track ../common/aclocal.m4 changes.
 423
 424 2002-06-14  Chris Demetriou  <cgd@broadcom.com>
 425             Ed Satterthwaite  <ehs@broadcom.com>
 426
 427         * mips3d.igen: New file which contains MIPS-3D ASE instructions.
 428         * Makefile.in (IGEN_INCLUDE): Add mips3d.igen.
 429         * mips.igen: Include mips3d.igen.
 430         (mips3d): New model name for MIPS-3D ASE instructions.
 431         (CVT.W.fmt): Don't use this instruction for word (source) format
 432         instructions.
 433         * cp1.c (fp_binary_r, fp_add_r, fp_mul_r, fpu_inv1, fpu_inv1_32)
 434         (fpu_inv1_64, fp_recip1, fp_recip2, fpu_inv_sqrt1, fpu_inv_sqrt1_32)
 435         (fpu_inv_sqrt1_64, fp_rsqrt1, fp_rsqrt2): New functions.
 436         (NR_FRAC_GUARD, IMPLICIT_1): New macros.
 437         * sim-main.h (fmt_pw, CompareAbs, AddR, MultiplyR, Recip1, Recip2)
 438         (RSquareRoot1, RSquareRoot2): New macros.
 439         (fp_add_r, fp_mul_r, fp_recip1, fp_recip2, fp_rsqrt1)
 440         (fp_rsqrt2): New functions.
 441         * configure.in: Add MIPS-3D support to mipsisa64 simulator.
 442         * configure: Regenerate.
 443
 444 2002-06-13  Chris Demetriou  <cgd@broadcom.com>
 445             Ed Satterthwaite  <ehs@broadcom.com>
 446
 447         * cp1.c (FP_PS_upper, FP_PS_lower, FP_PS_cat, FPQNaN_PS): New macros.
 448         (value_fpr, store_fpr, fp_cmp, fp_unary, fp_binary, fp_mac)
 449         (fp_inv_sqrt, fpu_format_name): Add paired-single support.
 450         (convert): Note that this function is not used for paired-single
 451         format conversions.
 452         (ps_lower, ps_upper, pack_ps, convert_ps): New functions.
 453         * mips.igen (FMT, MOVtf.fmt): Add paired-single support.
 454         (check_fmt_p): Enable paired-single support.
 455         (ALNV.PS, CVT.PS.S, CVT.S.PL, CVT.S.PU, PLL.PS, PLU.PS, PUL.PS)
 456         (PUU.PS): New instructions.
 457         (CVT.S.fmt): Don't use this instruction for paired-single format
 458         destinations.
 459         * sim-main.h (FP_formats): New value 'fmt_ps.'
 460         (ps_lower, ps_upper, pack_ps, convert_ps): New prototypes.
 461         (PSLower, PSUpper, PackPS, ConvertPS): New macros.
 462
 463 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 464
 465         * mips.igen: Fix formatting of function calls in
 466         many FP operations.
 467
 468 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 469
 470         * mips.igen (MOVN, MOVZ): Trace result.
 471         (TNEI): Print "tnei" as the opcode name in traces.
 472         (CEIL.W): Add disassembly string for traces.
 473         (RSQRT.fmt): Make location of disassembly string consistent
 474         with other instructions.
 475
 476 2002-06-12  Chris Demetriou  <cgd@broadcom.com>
 477
 478         * mips.igen (X): Delete unused function.
 479
 480 2002-06-08  Andrew Cagney  <cagney@redhat.com>
 481
 482         * interp.c: Include "gdb/callback.h" and "gdb/remote-sim.h".
 483
 484 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 485             Ed Satterthwaite  <ehs@broadcom.com>
 486
 487         * cp1.c (inner_mac, fp_mac, inner_rsqrt, fp_inv_sqrt)
 488         (fp_rsqrt, fp_madd, fp_msub, fp_nmadd, fp_nmsub): New functions.
 489         * sim-main.h (fp_rsqrt, fp_madd, fp_msub, fp_nmadd)
 490         (fp_nmsub): New prototypes.
 491         (RSquareRoot, MultiplyAdd, MultiplySub, NegMultiplyAdd)
 492         (NegMultiplySub): New defines.
 493         * mips.igen (RSQRT.fmt): Use RSquareRoot().
 494         (MADD.D, MADD.S): Replace with...
 495         (MADD.fmt): New instruction.
 496         (MSUB.D, MSUB.S): Replace with...
 497         (MSUB.fmt): New instruction.
 498         (NMADD.D, NMADD.S): Replace with...
 499         (NMADD.fmt): New instruction.
 500         (NMSUB.D, MSUB.S): Replace with...
 501         (NMSUB.fmt): New instruction.
 502
 503 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 504             Ed Satterthwaite  <ehs@broadcom.com>
 505
 506         * cp1.c: Fix more comment spelling and formatting.
 507         (value_fcr, store_fcr): Use fenr_FS rather than hard-coding value.
 508         (denorm_mode): New function.
 509         (fpu_unary, fpu_binary): Round results after operation, collect
 510         status from rounding operations, and update the FCSR.
 511         (convert): Collect status from integer conversions and rounding
 512         operations, and update the FCSR.  Adjust NaN values that result
 513         from conversions.  Convert to use sim_io_eprintf rather than
 514         fprintf, and remove some debugging code.
 515         * cp1.h (fenr_FS): New define.
 516
 517 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 518
 519         * cp1.c (convert): Remove unusable debugging code, and move MIPS
 520         rounding mode to sim FP rounding mode flag conversion code into...
 521         (rounding_mode): New function.
 522
 523 2002-06-07  Chris Demetriou  <cgd@broadcom.com>
 524
 525         * cp1.c: Clean up formatting of a few comments.
 526         (value_fpr): Reformat switch statement.
 527
 528 2002-06-06  Chris Demetriou  <cgd@broadcom.com>
 529             Ed Satterthwaite  <ehs@broadcom.com>
 530
 531         * cp1.h: New file.
 532         * sim-main.h: Include cp1.h.
 533         (SETFCC, GETFCC, IR, UF, OF, DX, IO, UO, FP_FLAGS, FP_ENABLE)
 534         (FP_CAUSE, GETFS, FP_RM_NEAREST, FP_RM_TOZERO, FP_RM_TOPINF)
 535         (FP_RM_TOMINF, GETRM): Remove.  Moved to cp1.h.
 536         (FP_FS, FP_MASK_RM, FP_SH_RM, Nan, Less, Equal): Remove.
 537         (value_fcr, store_fcr, test_fcsr, fp_cmp): New prototypes.
 538         (ValueFCR, StoreFCR, TestFCSR, Compare): New macros.
 539         * cp1.c: Don't include sim-fpu.h; already included by
 540         sim-main.h.  Clean up formatting of some comments.
 541         (NaN, Equal, Less): Remove.
 542         (test_fcsr, value_fcr, store_fcr, update_fcsr, fp_test)
 543         (fp_cmp): New functions.
 544         * mips.igen (do_c_cond_fmt): Remove.
 545         (C.cond.fmta, C.cond.fmtb): Replace uses of do_c_cond_fmt_a with
 546         Compare.  Add result tracing.
 547         (CxC1): Remove, replace with...
 548         (CFC1a, CFC1b, CFC1c, CTC1a, CTC1b, CTC1c): New instructions.
 549         (DMxC1): Remove, replace with...
 550         (DMFC1a, DMFC1b, DMTC1a, DMTC1b): New instructions.
 551         (MxC1): Remove, replace with...
 552         (MFC1a, MFC1b, MTC1a, MTC1b): New instructions.
 553
 554 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 555
 556         * sim-main.h (FGRIDX): Remove, replace all uses with...
 557         (FGR_BASE): New macro.
 558         (FP0_REGNUM, FCRCS_REGNUM, FCRIR_REGNUM): New macros.
 559         (_sim_cpu): Move 'fgr' member to be right before 'fpr_state' member.
 560         (NR_FGR, FGR): Likewise.
 561         * interp.c: Replace all uses of FGRIDX with FGR_BASE.
 562         * mips.igen: Likewise.
 563
 564 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 565
 566         * cp1.c: Add an FSF Copyright notice to this file.
 567
 568 2002-06-04  Chris Demetriou  <cgd@broadcom.com>
 569             Ed Satterthwaite  <ehs@broadcom.com>
 570
 571         * cp1.c (Infinity): Remove.
 572         * sim-main.h (Infinity): Likewise.
 573
 574         * cp1.c (fp_unary, fp_binary): New functions.
 575         (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div, fp_recip)
 576         (fp_sqrt): New functions, implemented in terms of the above.
 577         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 578         (Recip, SquareRoot): Remove (replaced by functions above).
 579         * sim-main.h (fp_abs, fp_neg, fp_add, fp_sub, fp_mul, fp_div)
 580         (fp_recip, fp_sqrt): New prototypes.
 581         (AbsoluteValue, Negate, Add, Sub, Multiply, Divide)
 582         (Recip, SquareRoot): Replace prototypes with #defines which
 583         invoke the functions above.
 584
 585 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 586
 587         * sim-main.h (Nan, Infinity, Less, Equal, AbsoluteValue, Negate)
 588         (Add, Sub, Multiply, Divide, Recip, SquareRoot): Move lower in
 589         file, remove PARAMS from prototypes.
 590         (value_fpr, store_fpr, convert): Likewise.  Use SIM_STATE to provide
 591         simulator state arguments.
 592         (ValueFPR, StoreFPR, Convert): Move lower in file.  Use SIM_ARGS to
 593         pass simulator state arguments.
 594         * cp1.c (SD): Redefine as CPU_STATE(cpu).
 595         (store_fpr, convert): Remove 'sd' argument.
 596         (value_fpr): Likewise.  Convert to use 'SD' instead.
 597
 598 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 599
 600         * cp1.c (Min, Max): Remove #if 0'd functions.
 601         * sim-main.h (Min, Max): Remove.
 602
 603 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 604
 605         * cp1.c: fix formatting of switch case and default labels.
 606         * interp.c: Likewise.
 607         * sim-main.c: Likewise.
 608
 609 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 610
 611         * cp1.c: Clean up comments which describe FP formats.
 612          (FPQNaN_DOUBLE, FPQNaN_LONG): Generate using UNSIGNED64.
 613
 614 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 615             Ed Satterthwaite  <ehs@broadcom.com>
 616
 617         * configure.in (mipsisa64sb1*-*-*): New target for supporting
 618         Broadcom SiByte SB-1 processor configurations.
 619         * configure: Regenerate.
 620         * sb1.igen: New file.
 621         * mips.igen: Include sb1.igen.
 622         (sb1): New model.
 623         * Makefile.in (IGEN_INCLUDE): Add sb1.igen.
 624         * mdmx.igen: Add "sb1" model to all appropriate functions and
 625         instructions.
 626         * mdmx.c (AbsDiffOB, AvgOB, AccAbsDiffOB): New functions.
 627         (ob_func, ob_acc): Reference the above.
 628         (qh_acc): Adjust to keep the same size as ob_acc.
 629         * sim-main.h (status_SBX, MX_VECT_ABSD, MX_VECT_AVG, MX_AbsDiff)
 630         (MX_Avg, MX_VECT_ABSDA, MX_AbsDiffC): New macros.
 631
 632 2002-06-03  Chris Demetriou  <cgd@broadcom.com>
 633
 634         * Makefile.in (IGEN_INCLUDE): Add mdmx.igen.
 635
 636 2002-06-02  Chris Demetriou  <cgd@broadcom.com>
 637             Ed Satterthwaite  <ehs@broadcom.com>
 638
 639         * mips.igen (mdmx): New (pseudo-)model.
 640         * mdmx.c, mdmx.igen: New files.
 641         * Makefile.in (SIM_OBJS): Add mdmx.o.
 642         * sim-main.h (MDMX_accumulator, MX_fmtsel, signed24, signed48):
 643         New typedefs.
 644         (ACC, MX_Add, MX_AddA, MX_AddL, MX_And, MX_C_EQ, MX_C_LT, MX_Comp)
 645         (MX_FMT_OB, MX_FMT_QH, MX_Max, MX_Min, MX_Msgn, MX_Mul, MX_MulA)
 646         (MX_MulL, MX_MulS, MX_MulSL, MX_Nor, MX_Or, MX_Pick, MX_RAC)
 647         (MX_RAC_H, MX_RAC_L, MX_RAC_M, MX_RNAS, MX_RNAU, MX_RND_AS)
 648         (MX_RND_AU, MX_RND_ES, MX_RND_EU, MX_RND_ZS, MX_RND_ZU, MX_RNES)
 649         (MX_RNEU, MX_RZS, MX_RZU, MX_SHFL, MX_ShiftLeftLogical)
 650         (MX_ShiftRightArith, MX_ShiftRightLogical, MX_Sub, MX_SubA, MX_SubL)
 651         (MX_VECT_ADD, MX_VECT_ADDA, MX_VECT_ADDL, MX_VECT_AND)
 652         (MX_VECT_MAX, MX_VECT_MIN, MX_VECT_MSGN, MX_VECT_MUL, MX_VECT_MULA)
 653         (MX_VECT_MULL, MX_VECT_MULS, MX_VECT_MULSL, MX_VECT_NOR)
 654         (MX_VECT_OR, MX_VECT_SLL, MX_VECT_SRA, MX_VECT_SRL, MX_VECT_SUB)
 655         (MX_VECT_SUBA, MX_VECT_SUBL, MX_VECT_XOR, MX_WACH, MX_WACL, MX_Xor)
 656         (SIM_ARGS, SIM_STATE, UnpredictableResult, fmt_mdmx, ob_fmtsel)
 657         (qh_fmtsel): New macros.
 658         (_sim_cpu): New member "acc".
 659         (mdmx_acc_op, mdmx_cc_op, mdmx_cpr_op, mdmx_pick_op, mdmx_rac_op)
 660         (mdmx_round_op, mdmx_shuffle, mdmx_wach, mdmx_wacl): New functions.
 661
 662 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 663
 664         * interp.c: Use 'deprecated' rather than 'depreciated.'
 665         * sim-main.h: Likewise.
 666
 667 2002-05-01  Chris Demetriou  <cgd@broadcom.com>
 668
 669         * cp1.c (store_fpr): Remove #ifdef'd out call to UndefinedResult
 670         which wouldn't compile anyway.
 671         * sim-main.h (unpredictable_action): New function prototype.
 672         (Unpredictable): Define to call igen function unpredictable().
 673         (NotWordValue): New macro to call igen function not_word_value().
 674         (UndefinedResult): Remove.
 675         * interp.c (undefined_result): Remove.
 676         (unpredictable_action): New function.
 677         * mips.igen (not_word_value, unpredictable): New functions.
 678         (ADD, ADDI, do_addiu, do_addu, BGEZAL, BGEZALL, BLTZAL, BLTZALL)
 679         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, do_mult, do_multu)
 680         (do_sra, do_srav, do_srl, do_srlv, SUB, do_subu): Invoke
 681         NotWordValue() to check for unpredictable inputs, then
 682         Unpredictable() to handle them.
 683
 684 2002-02-24  Chris Demetriou  <cgd@broadcom.com>
 685
 686         * mips.igen: Fix formatting of calls to Unpredictable().
 687
 688 2002-04-20  Andrew Cagney  <ac131313@redhat.com>
 689
 690         * interp.c (sim_open): Revert previous change.
 691
 692 2002-04-18  Alexandre Oliva  <aoliva@redhat.com>
 693
 694         * interp.c (sim_open): Disable chunk of code that wrote code in
 695         vector table entries.
 696
 697 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 698
 699         * cp1.c (FP_S_s, FP_D_s, FP_S_be, FP_D_be, FP_S_e, FP_D_e, FP_S_f)
 700         (FP_D_f, FP_S_fb, FP_D_fb, FPINF_SINGLE, FPINF_DOUBLE): Remove
 701         unused definitions.
 702
 703 2002-03-19  Chris Demetriou  <cgd@broadcom.com>
 704
 705         * cp1.c: Fix many formatting issues.
 706
 707 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 708
 709         * cp1.c (fpu_format_name): New function to replace...
 710         (DOFMT): This.  Delete, and update all callers.
 711         (fpu_rounding_mode_name): New function to replace...
 712         (RMMODE): This.  Delete, and update all callers.
 713
 714 2002-03-19  Chris G. Demetriou  <cgd@broadcom.com>
 715
 716         * interp.c: Move FPU support routines from here to...
 717         * cp1.c: Here.  New file.
 718         * Makefile.in (SIM_OBJS): Add cp1.o to object list.
 719         (cp1.o): New target.
 720
 721 2002-03-12  Chris Demetriou  <cgd@broadcom.com>
 722
 723         * configure.in (mipsisa32*-*-*, mipsisa64*-*-*): New targets.
 724         * mips.igen (mips32, mips64): New models, add to all instructions
 725         and functions as appropriate.
 726         (loadstore_ea, check_u64): New variant for model mips64.
 727         (check_fmt_p): New variant for models mipsV and mips64, remove
 728         mipsV model marking fro other variant.
 729         (SLL) Rename to...
 730         (SLLa) this.
 731         (CLO, CLZ, MADD, MADDU, MSUB, MSUBU, MUL, SLLb): New instructions
 732         for mips32 and mips64.
 733         (DCLO, DCLZ): New instructions for mips64.
 734
 735 2002-03-07  Chris Demetriou  <cgd@broadcom.com>
 736
 737         * mips.igen (BREAK, LUI, ORI, SYSCALL, XORI): Print
 738         immediate or code as a hex value with the "%#lx" format.
 739         (ANDI): Likewise, and fix printed instruction name.
 740
 741 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 742
 743         * sim-main.h (UndefinedResult, Unpredictable): New macros
 744         which currently do nothing.
 745
 746 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 747
 748         * sim-main.h (status_UX, status_SX, status_KX, status_TS)
 749         (status_PX, status_MX, status_CU0, status_CU1, status_CU2)
 750         (status_CU3): New definitions.
 751
 752         * sim-main.h (ExceptionCause): Add new values for MIPS32
 753         and MIPS64: MDMX, MCheck, CacheErr.  Update comments
 754         for DebugBreakPoint and NMIReset to note their status in
 755         MIPS32 and MIPS64.
 756         (SignalExceptionMDMX, SignalExceptionWatch, SignalExceptionMCheck)
 757         (SignalExceptionCacheErr): New exception macros.
 758
 759 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 760
 761         * mips.igen (check_fpu): Enable check for coprocessor 1 usability.
 762         * sim-main.h (COP_Usable): Define, but for now coprocessor 1
 763         is always enabled.
 764         (SignalExceptionCoProcessorUnusable): Take as argument the
 765         unusable coprocessor number.
 766
 767 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 768
 769         * mips.igen: Fix formatting of all SignalException calls.
 770
 771 2002-03-05  Chris Demetriou  <cgd@broadcom.com>
 772
 773         * sim-main.h (SIGNEXTEND): Remove.
 774
 775 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 776
 777         * mips.igen: Remove gencode comment from top of file, fix
 778         spelling in another comment.
 779
 780 2002-03-04  Chris Demetriou  <cgd@broadcom.com>
 781
 782         * mips.igen (check_fmt, check_fmt_p): New functions to check
 783         whether specific floating point formats are usable.
 784         (ABS.fmt, ADD.fmt, CEIL.L.fmt, CEIL.W, DIV.fmt, FLOOR.L.fmt)
 785         (FLOOR.W.fmt, MOV.fmt, MUL.fmt, NEG.fmt, RECIP.fmt, ROUND.L.fmt)
 786         (ROUND.W.fmt, RSQRT.fmt, SQRT.fmt, SUB.fmt, TRUNC.L.fmt, TRUNC.W):
 787         Use the new functions.
 788         (do_c_cond_fmt): Remove format checks...
 789         (C.cond.fmta, C.cond.fmtb): And move them into all callers.
 790
 791 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 792
 793         * mips.igen: Fix formatting of check_fpu calls.
 794
 795 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 796
 797         * mips.igen (FLOOR.L.fmt): Store correct destination register.
 798
 799 2002-03-03  Chris Demetriou  <cgd@broadcom.com>
 800
 801         * mips.igen: Remove whitespace at end of lines.
 802
 803 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 804
 805         * mips.igen (loadstore_ea): New function to do effective
 806         address calculations.
 807         (do_load, do_load_left, do_load_right, LL, LDD, PREF, do_store,
 808         do_store_left, do_store_right, SC, SCD, PREFX, SWC1, SWXC1,
 809         CACHE): Use loadstore_ea to do effective address computations.
 810
 811 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 812
 813         * interp.c (load_word): Use EXTEND32 rather than SIGNEXTEND.
 814         * mips.igen (LL, CxC1, MxC1): Likewise.
 815
 816 2002-03-02  Chris Demetriou  <cgd@broadcom.com>
 817
 818         * mips.igen (LL, LLD, PREF, SC, SCD, ABS.fmt, ADD.fmt, CEIL.L.fmt,
 819         CEIL.W, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt, CVT.W.fmt, DIV.fmt,
 820         FLOOR.L.fmt, FLOOR.W.fmt, MADD.D, MADD.S, MOV.fmt, MOVtf.fmt,
 821         MSUB.D, MSUB.S, MUL.fmt, NEG.fmt, NMADD.D, NMADD.S, NMSUB.D,
 822         NMSUB.S, PREFX, RECIP.fmt, ROUND.L.fmt, ROUND.W.fmt, RSQRT.fmt,
 823         SQRT.fmt, SUB.fmt, SWC1, SWXC1, TRUNC.L.fmt, TRUNC.W, CACHE):
 824         Don't split opcode fields by hand, use the opcode field values
 825         provided by igen.
 826
 827 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 828
 829         * mips.igen (do_divu): Fix spacing.
 830
 831         * mips.igen (do_dsllv): Move to be right before DSLLV,
 832         to match the rest of the do_<shift> functions.
 833
 834 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 835
 836         * mips.igen (do_dsll, do_dsllv, DSLL32, do_dsra, DSRA32, do_dsrl,
 837         DSRL32, do_dsrlv): Trace inputs and results.
 838
 839 2002-03-01  Chris Demetriou  <cgd@broadcom.com>
 840
 841         * mips.igen (CACHE): Provide instruction-printing string.
 842
 843         * interp.c (signal_exception): Comment tokens after #endif.
 844
 845 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 846
 847         * mips.igen (LWXC1): Mark with filter "64,f", rather than just "32".
 848         (MOVtf, MxC1, MxC1, DMxC1, DMxC1, CxC1, CxC1, SQRT.fmt, MOV.fmt,
 849         NEG.fmt, ROUND.L.fmt, TRUNC.L.fmt, CEIL.L.fmt, FLOOR.L.fmt,
 850         ROUND.W.fmt, TRUNC.W, CEIL.W, FLOOR.W.fmt, RECIP.fmt, RSQRT.fmt,
 851         CVT.S.fmt, CVT.D.fmt, CVT.W.fmt, CVT.L.fmt, MOVtf.fmt, C.cond.fmta,
 852         C.cond.fmtb, SUB.fmt, MUL.fmt, DIV.fmt, MOVZ.fmt, MOVN.fmt, LDXC1,
 853         SWXC1, SDXC1, MSUB.D, MSUB.S, NMADD.S, NMADD.D, NMSUB.S, NMSUB.D,
 854         LWC1, SWC1): Add "f" to filter, since these are FP instructions.
 855
 856 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 857
 858         * mips.igen (DSRA32, DSRAV): Fix order of arguments in
 859         instruction-printing string.
 860         (LWU): Use '64' as the filter flag.
 861
 862 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 863
 864         * mips.igen (SDXC1): Fix instruction-printing string.
 865
 866 2002-02-28  Chris Demetriou  <cgd@broadcom.com>
 867
 868         * mips.igen (LDC1, SDC1): Remove mipsI model, and mark with
 869         filter flags "32,f".
 870
 871 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 872
 873         * mips.igen (PREFX): This is a 64-bit instruction, use '64'
 874         as the filter flag.
 875
 876 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 877
 878         * mips.igen (PREFX): Tweak instruction opcode fields (i.e.,
 879         add a comma) so that it more closely match the MIPS ISA
 880         documentation opcode partitioning.
 881         (PREF): Put useful names on opcode fields, and include
 882         instruction-printing string.
 883
 884 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 885
 886         * mips.igen (check_u64): New function which in the future will
 887         check whether 64-bit instructions are usable and signal an
 888         exception if not.  Currently a no-op.
 889         (DADD, DADDI, DADDIU, DADDU, DDIV, DDIVU, DMULT, DMULTU, DSLL,
 890         DSLL32, DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB,
 891         DSUBU, LD, LDL, LDR, LLD, LWU, SCD, SD, SDL, SDR, DMxC1, LDXC1,
 892         LWXC1, SDXC1, SWXC1, DMFC0, DMTC0): Use check_u64.
 893
 894         * mips.igen (check_fpu): New function which in the future will
 895         check whether FPU instructions are usable and signal an exception
 896         if not.  Currently a no-op.
 897         (ABS.fmt, ADD.fmt, BC1a, BC1b, C.cond.fmta, C.cond.fmtb,
 898         CEIL.L.fmt, CEIL.W, CxC1, CVT.D.fmt, CVT.L.fmt, CVT.S.fmt,
 899         CVT.W.fmt, DIV.fmt, DMxC1, DMxC1, FLOOR.L.fmt, FLOOR.W.fmt, LDC1,
 900         LDXC1, LWC1, LWXC1, MADD.D, MADD.S, MxC1, MOV.fmt, MOVtf,
 901         MOVtf.fmt, MOVN.fmt, MOVZ.fmt, MSUB.D, MSUB.S, MUL.fmt, NEG.fmt,
 902         NMADD.D, NMADD.S, NMSUB.D, NMSUB.S, RECIP.fmt, ROUND.L.fmt,
 903         ROUND.W.fmt, RSQRT.fmt, SDC1, SDXC1, SQRT.fmt, SUB.fmt, SWC1,
 904         SWXC1, TRUNC.L.fmt, TRUNC.W): Use check_fpu.
 905
 906 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 907
 908         * mips.igen (do_load_left, do_load_right): Move to be immediately
 909         following do_load.
 910         (do_store_left, do_store_right): Move to be immediately following
 911         do_store.
 912
 913 2002-02-27  Chris Demetriou  <cgd@broadcom.com>
 914
 915         * mips.igen (mipsV): New model name.  Also, add it to
 916         all instructions and functions where it is appropriate.
 917
 918 2002-02-18  Chris Demetriou  <cgd@broadcom.com>
 919
 920         * mips.igen: For all functions and instructions, list model
 921         names that support that instruction one per line.
 922
 923 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 924
 925         * mips.igen: Add some additional comments about supported
 926         models, and about which instructions go where.
 927         (BC1b, MFC0, MTC0, RFE): Sort supported models in the same
 928         order as is used in the rest of the file.
 929
 930 2002-02-11  Chris Demetriou  <cgd@broadcom.com>
 931
 932         * mips.igen (ADD, ADDI, DADDI, DSUB, SUB): Add comment
 933         indicating that ALU32_END or ALU64_END are there to check
 934         for overflow.
 935         (DADD): Likewise, but also remove previous comment about
 936         overflow checking.
 937
 938 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 939
 940         * mips.igen (DDIV, DIV, DIVU, DMULT, DMULTU, DSLL, DSLL32,
 941         DSLLV, DSRA, DSRA32, DSRAV, DSRL, DSRL32, DSRLV, DSUB, DSUBU,
 942         JALR, JR, MOVN, MOVZ, MTLO, MULT, MULTU, SLL, SLLV, SLT, SLTU,
 943         SRAV, SRLV, SUB, SUBU, SYNC, XOR, MOVtf, DI, DMFC0, DMTC0, EI,
 944         ERET, RFE, TLBP, TLBR, TLBWI, TLBWR): Tweak instruction opcode
 945         fields (i.e., add and move commas) so that they more closely
 946         match the MIPS ISA documentation opcode partitioning.
 947
 948 2002-02-10  Chris Demetriou  <cgd@broadcom.com>
 949
 950         * mips.igen (ADDI): Print immediate value.
 951         (BREAK): Print code.
 952         (DADDIU, DSRAV, DSRLV): Print correct instruction name.
 953         (SLL): Print "nop" specially, and don't run the code
 954         that does the shift for the "nop" case.
 955
 956 2001-11-17  Fred Fish  <fnf@redhat.com>
 957
 958         * sim-main.h (float_operation): Move enum declaration outside
 959         of _sim_cpu struct declaration.
 960
 961 2001-04-12  Jim Blandy  <jimb@redhat.com>
 962
 963         * mips.igen (CFC1, CTC1): Pass the correct register numbers to
 964         PENDING_FILL.  Use PENDING_SCHED directly to handle the pending
 965         set of the FCSR.
 966         * sim-main.h (COCIDX): Remove definition; this isn't supported by
 967         PENDING_FILL, and you can get the intended effect gracefully by
 968         calling PENDING_SCHED directly.
 969
 970 2001-02-23  Ben Elliston  <bje@redhat.com>
 971
 972         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Only define if not
 973         already defined elsewhere.
 974
 975 2001-02-19  Ben Elliston  <bje@redhat.com>
 976
 977         * sim-main.h (sim_monitor): Return an int.
 978         * interp.c (sim_monitor): Add return values.
 979         (signal_exception): Handle error conditions from sim_monitor.
 980
 981 2001-02-08  Ben Elliston  <bje@redhat.com>
 982
 983         * sim-main.c (load_memory): Pass cia to sim_core_read* functions.
 984         (store_memory): Likewise, pass cia to sim_core_write*.
 985
 986 2000-10-19  Frank Ch. Eigler  <fche@redhat.com>
 987
 988         On advice from Chris G. Demetriou <cgd@sibyte.com>:
 989         * sim-main.h (GPR_CLEAR): Remove unused alternative macro.
 990
 991 Thu Jul 27 22:02:05 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 992
 993         From Maciej W. Rozycki <macro@ds2.pg.gda.pl>:
 994         * Makefile.in: Don't delete *.igen when cleaning directory.
 995
 996 Wed Jul 19 18:50:51 2000  Andrew Cagney  <cagney@b1.cygnus.com>
 997
 998         * m16.igen (break): Call SignalException not sim_engine_halt.
 999
1000 Mon Jul  3 11:13:20 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1001
1002         From Jason Eckhardt:
1003         * mips.igen (MOVZ.fmt, MOVN.fmt): Move conditional on GPR[RT].
1004
1005 Tue Jun 13 20:52:07 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1006
1007         * mips.igen (MxC1, DMxC1): Fix printf formatting.
1008
1009 2000-05-24  Michael Hayes  <mhayes@cygnus.com>
1010
1011         * mips.igen (do_dmultx): Fix typo.
1012
1013 Tue May 23 21:39:23 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1014
1015         * configure: Regenerated to track ../common/aclocal.m4 changes.
1016
1017 Fri Apr 28 20:48:36 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1018
1019         * mips.igen (DMxC1): Fix format arguments for sim_io_eprintf call.
1020
1021 2000-04-12  Frank Ch. Eigler  <fche@redhat.com>
1022
1023         * sim-main.h (GPR_CLEAR): Define macro.
1024
1025 Mon Apr 10 00:07:09 2000  Andrew Cagney  <cagney@b1.cygnus.com>
1026
1027         * interp.c (decode_coproc): Output long using %lx and not %s.
1028
1029 2000-03-21  Frank Ch. Eigler  <fche@redhat.com>
1030
1031         * interp.c (sim_open): Sort & extend dummy memory regions for
1032         --board=jmr3904 for eCos.
1033
1034 2000-03-02  Frank Ch. Eigler  <fche@redhat.com>
1035
1036         * configure: Regenerated.
1037
1038 Tue Feb  8 18:35:01 2000  Donald Lindsay  <dlindsay@hound.cygnus.com>
1039
1040         * interp.c, mips.igen: all 5 DEADC0DE situations now have sim_io_eprintf
1041         calls, conditional on the simulator being in verbose mode.
1042
1043 Fri Feb  4 09:45:15 2000  Donald Lindsay  <dlindsay@cygnus.com>
1044
1045         * sim-main.c (cache_op): Added case arm so that CACHE ops to a secondary
1046         cache don't get ReservedInstruction traps.
1047
1048 1999-11-29  Mark Salter  <msalter@cygnus.com>
1049
1050         * dv-tx3904sio.c (tx3904sio_io_write_buffer): Use write value as a mask
1051         to clear status bits in sdisr register. This is how the hardware works.
1052
1053         * interp.c (sim_open): Added more memory aliases for jmr3904 hardware
1054         being used by cygmon.
1055
1056 1999-11-11  Andrew Haley  <aph@cygnus.com>
1057
1058         * interp.c (decode_coproc): Correctly handle DMFC0 and DMTC0
1059         instructions.
1060
1061 Thu Sep  9 15:12:08 1999  Geoffrey Keating  <geoffk@cygnus.com>
1062
1063         * mips.igen (MULT): Correct previous mis-applied patch.
1064
1065 Tue Sep  7 13:34:54 1999  Geoffrey Keating  <geoffk@cygnus.com>
1066
1067         * mips.igen (delayslot32): Handle sequence like
1068         mtc1 $at,$f12 ; jal fp_add ; mov.s $f13,$f12
1069         correctly by calling ENGINE_ISSUE_PREFIX_HOOK() before issue.
1070         (MULT): Actually pass the third register...
1071
1072 1999-09-03  Mark Salter  <msalter@cygnus.com>
1073
1074         * interp.c (sim_open): Added more memory aliases for additional
1075         hardware being touched by cygmon on jmr3904 board.
1076
1077 Thu Sep  2 18:15:53 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1078
1079         * configure: Regenerated to track ../common/aclocal.m4 changes.
1080
1081 Tue Jul 27 16:36:51 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1082
1083         * interp.c (sim_store_register): Handle case where client - GDB -
1084         specifies that a 4 byte register is 8 bytes in size.
1085         (sim_fetch_register): Ditto.
1086
1087 1999-07-14  Frank Ch. Eigler  <fche@cygnus.com>
1088
1089         Implement "sim firmware" option, inspired by jimb's version of 1998-01.
1090         * interp.c (firmware_option_p): New global flag: "sim firmware" given.
1091         (idt_monitor_base): Base address for IDT monitor traps.
1092         (pmon_monitor_base): Ditto for PMON.
1093         (lsipmon_monitor_base): Ditto for LSI PMON.
1094         (MONITOR_BASE, MONITOR_SIZE): Removed macros.
1095         (mips_option): Add "firmware" option with new OPTION_FIRMWARE key.
1096         (sim_firmware_command): New function.
1097         (mips_option_handler): Call it for OPTION_FIRMWARE.
1098         (sim_open): Allocate memory for idt_monitor region.  If "--board"
1099         option was given, add no monitor by default.  Add BREAK hooks only if
1100         monitors are also there.
1101
1102 Mon Jul 12 00:02:27 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1103
1104         * interp.c (sim_monitor): Flush output before reading input.
1105
1106 Sun Jul 11 19:28:11 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1107
1108         * tconfig.in (SIM_HANDLES_LMA): Always define.
1109
1110 Thu Jul  8 16:06:59 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1111
1112         From Mark Salter <msalter@cygnus.com>:
1113         * interp.c (BOARD_BSP): Define.  Add to list of possible boards.
1114         (sim_open): Add setup for BSP board.
1115
1116 Wed Jul  7 12:45:58 1999  Andrew Cagney  <cagney@b1.cygnus.com>
1117
1118         * mips.igen (MULT, MULTU): Add syntax for two operand version.
1119         (DMFC0, DMTC0): Recognize.  Call DecodeCoproc which will report
1120         them as unimplemented.
1121
1122 1999-05-08  Felix Lee  <flee@cygnus.com>
1123
1124         * configure: Regenerated to track ../common/aclocal.m4 changes.
1125
1126 1999-04-21  Frank Ch. Eigler  <fche@cygnus.com>
1127
1128         * mips.igen (bc0f): For the TX39 only, decode this as a no-op stub.
1129
1130 Thu Apr 15 14:15:17 1999  Andrew Cagney  <cagney@amy.cygnus.com>
1131
1132         * configure.in: Any mips64vr5*-*-* target should have
1133         -DTARGET_ENABLE_FR=1.
1134         (default_endian): Any mips64vr*el-*-* target should default to
1135         LITTLE_ENDIAN.
1136         * configure: Re-generate.
1137
1138 1999-02-19  Gavin Romig-Koch  <gavin@cygnus.com>
1139
1140         * mips.igen (ldl): Extend from _16_, not 32.
1141
1142 Wed Jan 27 18:51:38 1999  Andrew Cagney  <cagney@chook.cygnus.com>
1143
1144         * interp.c (sim_store_register): Force registers written to by GDB
1145         into an un-interpreted state.
1146
1147 1999-02-05  Frank Ch. Eigler  <fche@cygnus.com>
1148
1149         * dv-tx3904sio.c (tx3904sio_tickle): After a polled I/O from the
1150         CPU, start periodic background I/O polls.
1151         (tx3904sio_poll): New function: periodic I/O poller.
1152
1153 1998-12-30  Frank Ch. Eigler  <fche@cygnus.com>
1154
1155         * mips.igen (BREAK): Call signal_exception instead of sim_engine_halt.
1156
1157 Tue Dec 29 16:03:53 1998  Rainer Orth  <ro@TechFak.Uni-Bielefeld.DE>
1158
1159         * configure.in, configure (mips64vr5*-*-*): Added missing ;; in
1160         case statement.
1161
1162 1998-12-29  Frank Ch. Eigler  <fche@cygnus.com>
1163
1164         * interp.c (sim_open): Allocate jm3904 memory in smaller chunks.
1165         (load_word): Call SIM_CORE_SIGNAL hook on error.
1166         (signal_exception): Call SIM_CPU_EXCEPTION_TRIGGER hook before
1167         starting.  For exception dispatching, pass PC instead of NULL_CIA.
1168         (decode_coproc): Use COP0_BADVADDR to store faulting address.
1169         * sim-main.h (COP0_BADVADDR): Define.
1170         (SIM_CORE_SIGNAL): Define hook to call mips_core_signal.
1171         (SIM_CPU_EXCEPTION*): Define hooks to call mips_cpu_exception*().
1172         (_sim_cpu): Add exc_* fields to store register value snapshots.
1173         * mips.igen (*): Replace memory-related SignalException* calls
1174         with references to SIM_CORE_SIGNAL hook.
1175
1176         * dv-tx3904irc.c (tx3904irc_port_event): printf format warning
1177         fix.
1178         * sim-main.c (*): Minor warning cleanups.
1179
1180 1998-12-24  Gavin Romig-Koch  <gavin@cygnus.com>
1181
1182         * m16.igen (DADDIU5): Correct type-o.
1183
1184 Mon Dec 21 10:34:48 1998  Andrew Cagney  <cagney@chook>
1185
1186         * mips.igen (do_ddiv, do_ddivu): Pacify GCC. Update hi/lo via tmp
1187         variables.
1188
1189 Wed Dec 16 18:20:28 1998  Andrew Cagney  <cagney@chook>
1190
1191         * Makefile.in (SIM_EXTRA_CFLAGS): No longer need to add .../newlib
1192         to include path.
1193         (interp.o): Add dependency on itable.h
1194         (oengine.c, gencode): Delete remaining references.
1195         (BUILT_SRC_FROM_GEN): Clean up.
1196
1197 1998-12-16  Gavin Romig-Koch  <gavin@cygnus.com>
1198
1199         * vr4run.c: New.
1200         * Makefile.in (SIM_HACK_OBJ,HACK_OBJS,HACK_GEN_SRCS,libhack.a,
1201         tmp-hack,tmp-m32-hack,tmp-m16-hack,tmp-itable-hack,
1202         tmp-run-hack) : New.
1203         * m16.igen (LD,DADDIU,DADDUI5,DADJSP,DADDIUSP,DADDI,DADDU,DSUBU,
1204         DSLL,DSRL,DSRA,DSLLV,DSRAV,DMULT,DMULTU,DDIV,DDIVU,JALX32,JALX):
1205         Drop the "64" qualifier to get the HACK generator working.
1206         Use IMMEDIATE rather than IMMED.  Use SHAMT rather than SHIFT.
1207         * mips.igen (do_daddiu,do_ddiv,do_divu): Remove the 64-only
1208         qualifier to get the hack generator working.
1209         (do_dsll,do_dsllv,do_dsra,do_dsrl,do_dsrlv): New.
1210         (DSLL): Use do_dsll.
1211         (DSLLV): Use do_dsllv.
1212         (DSRA): Use do_dsra.
1213         (DSRL): Use do_dsrl.
1214         (DSRLV): Use do_dsrlv.
1215         (BC1): Move *vr4100 to get the HACK generator working.
1216         (CxC1, DMxC1, MxC1,MACCU,MACCHI,MACCHIU): Rename to
1217         get the HACK generator working.
1218         (MACC) Rename to get the HACK generator working.
1219         (DMACC,MACCS,DMACCS): Add the 64.
1220
1221 1998-12-12  Gavin Romig-Koch  <gavin@cygnus.com>
1222
1223         * mips.igen (BC1): Renamed to BC1a and BC1b to avoid conflicts.
1224         * sim-main.h (SizeFGR): Handle TARGET_ENABLE_FR.
1225
1226 1998-12-11  Gavin Romig-Koch  <gavin@cygnus.com>
1227
1228     * mips/interp.c (DEBUG): Cleanups.
1229
1230 1998-12-10  Frank Ch. Eigler  <fche@cygnus.com>
1231
1232         * dv-tx3904sio.c (tx3904sio_io_read_buffer): Endianness fixes.
1233         (tx3904sio_tickle): fflush after a stdout character output.
1234
1235 1998-12-03  Frank Ch. Eigler  <fche@cygnus.com>
1236
1237         * interp.c (sim_close): Uninstall modules.
1238
1239 Wed Nov 25 13:41:03 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1240
1241         * sim-main.h, interp.c (sim_monitor): Change to global
1242         function.
1243
1244 Wed Nov 25 17:33:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1245
1246         * configure.in (vr4100): Only include vr4100 instructions in
1247         simulator.
1248         * configure: Re-generate.
1249         * m16.igen (*): Tag all mips16 instructions as also being vr4100.
1250
1251 Mon Nov 23 18:20:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1252
1253         * Makefile.in (SIM_CFLAGS): Do not define WITH_IGEN.
1254         * sim-main.h, sim-main.c, interp.c: Delete #if WITH_IGEN keeping
1255         true alternative.
1256
1257         * configure.in (sim_default_gen, sim_use_gen): Replace with
1258         sim_gen.
1259         (--enable-sim-igen): Delete config option. Always using IGEN.
1260         * configure: Re-generate.
1261
1262         * Makefile.in (gencode): Kill, kill, kill.
1263         * gencode.c: Ditto.
1264
1265 Mon Nov 23 18:07:36 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1266
1267         * configure.in: Configure mips64vr4100-elf nee mips64vr41* as a 64
1268         bit mips16 igen simulator.
1269         * configure: Re-generate.
1270
1271         * mips.igen (check_div_hilo, check_mult_hilo, check_mf_hilo): Mark
1272         as part of vr4100 ISA.
1273         * vr.igen: Mark all instructions as 64 bit only.
1274
1275 Mon Nov 23 17:07:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1276
1277         * interp.c (get_cell, sim_monitor, fetch_str, CoProcPresent):
1278         Pacify GCC.
1279
1280 Mon Nov 23 13:23:40 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1281
1282         * configure.in: Configure mips-lsi-elf nee mips*lsi* as a
1283         mipsIII/mips16 igen simulator.  Fix sim_gen VS sim_igen typos.
1284         * configure: Re-generate.
1285
1286         * m16.igen (BREAK): Define breakpoint instruction.
1287         (JALX32): Mark instruction as mips16 and not r3900.
1288         * mips.igen (C.cond.fmt): Fix typo in instruction format.
1289
1290         * sim-main.h (PENDING_FILL): Wrap C statements in do/while.
1291
1292 Sat Nov  7 09:54:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1293
1294         * gencode.c (build_instruction - BREAK): For MIPS16, handle BREAK
1295         insn as a debug breakpoint.
1296
1297         * sim-main.h (PENDING_SLOT_BIT): Fix, was incorrectly defined as
1298         pending.slot_size.
1299         (PENDING_SCHED): Clean up trace statement.
1300         (PENDING_SCHED): Increment PENDING_IN and PENDING_TOTAL.
1301         (PENDING_FILL): Delay write by only one cycle.
1302         (PENDING_FILL): For FSRs, write fmt_uninterpreted to FPR_STATE.
1303
1304         * sim-main.c (pending_tick): Clean up trace statements. Add trace
1305         of pending writes.
1306         (pending_tick): Fix sizes in switch statements, 4 & 8 instead of
1307         32 & 64.
1308         (pending_tick): Move incrementing of index to FOR statement.
1309         (pending_tick): Only update PENDING_OUT after a write has occured.
1310
1311         * configure.in: Add explicit mips-lsi-* target.  Use gencode to
1312         build simulator.
1313         * configure: Re-generate.
1314
1315         * interp.c (sim_engine_run OLD): Delete explicit call to
1316         PENDING_TICK. Now called via ENGINE_ISSUE_PREFIX_HOOK.
1317
1318 Sat Oct 30 09:49:10 1998  Frank Ch. Eigler  <fche@cygnus.com>
1319
1320         * dv-tx3904cpu.c (deliver_tx3904cpu_interrupt): Add dummy
1321         interrupt level number to match changed SignalExceptionInterrupt
1322         macro.
1323
1324 Fri Oct  9 18:02:25 1998  Doug Evans  <devans@canuck.cygnus.com>
1325
1326         * interp.c: #include "itable.h" if WITH_IGEN.
1327         (get_insn_name): New function.
1328         (sim_open): Initialize CPU_INSN_NAME,CPU_MAX_INSNS.
1329         * sim-main.h (MAX_INSNS,INSN_NAME): Delete.
1330
1331 Mon Sep 14 12:36:44 1998  Frank Ch. Eigler  <fche@cygnus.com>
1332
1333         * configure: Rebuilt to inhale new common/aclocal.m4.
1334
1335 Tue Sep  1 15:39:18 1998  Frank Ch. Eigler  <fche@cygnus.com>
1336
1337         * dv-tx3904sio.c: Include sim-assert.h.
1338
1339 Tue Aug 25 12:49:46 1998  Frank Ch. Eigler  <fche@cygnus.com>
1340
1341         * dv-tx3904sio.c: New file: tx3904 serial I/O module.
1342         * configure.in: Add dv-tx3904sio, dv-sockser for tx39 target.
1343         Reorganize target-specific sim-hardware checks.
1344         * configure: rebuilt.
1345         * interp.c (sim_open): For tx39 target boards, set
1346         OPERATING_ENVIRONMENT, add tx3904sio devices.
1347         * tconfig.in: For tx39 target, set SIM_HANDLES_LMA for loading
1348         ROM executables.  Install dv-sockser into sim-modules list.
1349
1350         * dv-tx3904irc.c: Compiler warning clean-up.
1351         * dv-tx3904tmr.c: Compiler warning clean-up.  Remove particularly
1352         frequent hw-trace messages.
1353
1354 Fri Jul 31 18:14:16 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1355
1356         * vr.igen (MulAcc): Identify as a vr4100 specific function.
1357
1358 Sat Jul 25 16:03:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1359
1360         * Makefile.in (IGEN_INCLUDE): Add vr.igen.
1361
1362         * vr.igen: New file.
1363         (MAC/MADD16, DMAC/DMADD16): Implement using code from gencode.c.
1364         * mips.igen: Define vr4100 model. Include vr.igen.
1365 Mon Jun 29 09:21:07 1998  Gavin Koch  <gavin@cygnus.com>
1366
1367         * mips.igen (check_mf_hilo): Correct check.
1368
1369 Wed Jun 17 12:20:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1370
1371         * sim-main.h (interrupt_event): Add prototype.
1372
1373         * dv-tx3904tmr.c (tx3904tmr_io_write_buffer): Delete unused
1374         register_ptr, register_value.
1375         (deliver_tx3904tmr_tick): Fix types passed to printf fmt.
1376
1377         * sim-main.h (tracefh): Make extern.
1378
1379 Tue Jun 16 14:39:00 1998  Frank Ch. Eigler  <fche@cygnus.com>
1380
1381         * dv-tx3904tmr.c: Deschedule timer event after dispatching.
1382         Reduce unnecessarily high timer event frequency.
1383         * dv-tx3904cpu.c: Ditto for interrupt event.
1384
1385 Wed Jun 10 13:22:32 1998  Frank Ch. Eigler  <fche@cygnus.com>
1386
1387         * interp.c (decode_coproc): For TX39, add stub COP0 register #7,
1388         to allay warnings.
1389         (interrupt_event): Made non-static.
1390
1391         * dv-tx3904tmr.c (deliver_tx3904tmr_tick): Correct accidental
1392         interchange of configuration values for external vs. internal
1393         clock dividers.
1394
1395 Tue Jun  9 12:46:24 1998  Ian Carmichael  <iancarm@cygnus.com>
1396
1397         * mips.igen (BREAK): Moved code to here for
1398         simulator-reserved break instructions.
1399         * gencode.c (build_instruction): Ditto.
1400         * interp.c (signal_exception): Code moved from here.  Non-
1401         reserved instructions now use exception vector, rather
1402         than halting sim.
1403         * sim-main.h: Moved magic constants to here.
1404
1405 Tue Jun  9 12:29:50 1998  Frank Ch. Eigler  <fche@cygnus.com>
1406
1407         * dv-tx3904cpu.c (deliver_*_interrupt,*_port_event): Set the CAUSE
1408         register upon non-zero interrupt event level, clear upon zero
1409         event value.
1410         * dv-tx3904irc.c (*_port_event): Handle deactivated interrupt signal
1411         by passing zero event value.
1412         (*_io_{read,write}_buffer): Endianness fixes.
1413         * dv-tx3904tmr.c (*_io_{read,write}_buffer): Endianness fixes.
1414         (deliver_*_tick): Reduce sim event interval to 75% of count interval.
1415
1416         * interp.c (sim_open): Added jmr3904pal board type that adds PAL-based
1417         serial I/O and timer module at base address 0xFFFF0000.
1418
1419 Tue Jun  9 11:52:29 1998  Gavin Koch  <gavin@cygnus.com>
1420
1421         * mips.igen (SWC1) : Correct the handling of ReverseEndian
1422         and BigEndianCPU.
1423
1424 Tue Jun  9 11:40:57 1998  Gavin Koch  <gavin@cygnus.com>
1425
1426         * configure.in (mips_fpu_bitsize) : Set this correctly for 32-bit mips
1427         parts.
1428         * configure: Update.
1429
1430 Thu Jun  4 15:37:33 1998  Frank Ch. Eigler  <fche@cygnus.com>
1431
1432         * dv-tx3904tmr.c: New file - implements tx3904 timer.
1433         * dv-tx3904{irc,cpu}.c: Mild reformatting.
1434         * configure.in: Include tx3904tmr in hw_device list.
1435         * configure: Rebuilt.
1436         * interp.c (sim_open): Instantiate three timer instances.
1437         Fix address typo of tx3904irc instance.
1438
1439 Tue Jun  2 15:48:02 1998  Ian Carmichael  <iancarm@cygnus.com>
1440
1441         * interp.c (signal_exception): SystemCall exception now uses
1442         the exception vector.
1443
1444 Mon Jun  1 18:18:26 1998  Frank Ch. Eigler  <fche@cygnus.com>
1445
1446         * interp.c (decode_coproc): For TX39, add stub COP0 register #3,
1447         to allay warnings.
1448
1449 Fri May 29 11:40:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1450
1451         * configure.in (sim_igen_filter): Match mips*tx39 not mipst*tx39.
1452
1453 Mon May 25 20:47:45 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1454
1455         * dv-tx3904cpu.c, dv-tx3904irc.c: Rename *_callback to *_method.
1456
1457         * dv-tx3904cpu.c, dv-tx3904irc.c: Include hw-main.h and
1458         sim-main.h. Declare a struct hw_descriptor instead of struct
1459         hw_device_descriptor.
1460
1461 Mon May 25 12:41:38 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1462
1463         * mips.igen (do_store_left, do_load_left): Compute nr of left and
1464         right bits and then re-align left hand bytes to correct byte
1465         lanes.  Fix incorrect computation in do_store_left when loading
1466         bytes from second word.
1467
1468 Fri May 22 13:34:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1469
1470         * configure.in (SIM_AC_OPTION_HARDWARE): Only enable when tx3904.
1471         * interp.c (sim_open): Only create a device tree when HW is
1472         enabled.
1473
1474         * dv-tx3904irc.c (tx3904irc_finish): Pacify GCC.
1475         * interp.c (signal_exception): Ditto.
1476
1477 Thu May 21 14:24:11 1998  Gavin Koch  <gavin@cygnus.com>
1478
1479         * gencode.c: Mark BEGEZALL as LIKELY.
1480
1481 Thu May 21 18:57:19 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1482
1483         * sim-main.h (ALU32_END): Sign extend 32 bit results.
1484         * mips.igen (ADD, SUB, ADDI, DADD, DSUB): Trace.
1485
1486 Mon May 18 18:22:42 1998  Frank Ch. Eigler  <fche@cygnus.com>
1487
1488         * configure.in (SIM_AC_OPTION_HARDWARE): Added common hardware
1489         modules.  Recognize TX39 target with "mips*tx39" pattern.
1490         * configure: Rebuilt.
1491         * sim-main.h (*): Added many macros defining bits in
1492         TX39 control registers.
1493         (SignalInterrupt): Send actual PC instead of NULL.
1494         (SignalNMIReset): New exception type.
1495         * interp.c (board): New variable for future use to identify
1496         a particular board being simulated.
1497         (mips_option_handler,mips_options): Added "--board" option.
1498         (interrupt_event): Send actual PC.
1499         (sim_open): Make memory layout conditional on board setting.
1500         (signal_exception): Initial implementation of hardware interrupt
1501         handling.  Accept another break instruction variant for simulator
1502         exit.
1503         (decode_coproc): Implement RFE instruction for TX39.
1504         (mips.igen): Decode RFE instruction as such.
1505         * configure.in (tx3904cpu,tx3904irc): Added devices for tx3904.
1506         * interp.c: Define "jmr3904" and "jmr3904debug" board types and
1507         bbegin to implement memory map.
1508         * dv-tx3904cpu.c: New file.
1509         * dv-tx3904irc.c: New file.
1510
1511 Wed May 13 14:40:11 1998  Gavin Koch  <gavin@cygnus.com>
1512
1513         * mips.igen (check_mt_hilo): Create a separate r3900 version.
1514
1515 Wed May 13 14:11:46 1998  Gavin Koch  <gavin@cygnus.com>
1516
1517         * tx.igen (madd,maddu):  Replace calls to check_op_hilo
1518         with calls to check_div_hilo.
1519
1520 Wed May 13 09:59:27 1998  Gavin Koch  <gavin@cygnus.com>
1521
1522         * mips/mips.igen (check_op_hilo,check_mult_hilo,check_div_hilo):
1523         Replace check_op_hilo with check_mult_hilo and check_div_hilo.
1524         Add special r3900 version of do_mult_hilo.
1525         (do_dmultx,do_mult,do_multu): Replace calls to check_op_hilo
1526         with calls to check_mult_hilo.
1527         (do_ddiv,do_ddivu,do_div,do_divu): Replace calls to check_op_hilo
1528         with calls to check_div_hilo.
1529
1530 Tue May 12 15:22:11 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1531
1532         * configure.in (SUBTARGET_R3900): Define for mipstx39 target.
1533         Document a replacement.
1534
1535 Fri May  8 17:48:19 1998  Ian Carmichael  <iancarm@cygnus.com>
1536
1537         * interp.c (sim_monitor): Make mon_printf work.
1538
1539 Wed May  6 19:42:19 1998  Doug Evans  <devans@canuck.cygnus.com>
1540
1541         * sim-main.h (INSN_NAME): New arg `cpu'.
1542
1543 Tue Apr 28 18:33:31 1998  Geoffrey Noer  <noer@cygnus.com>
1544
1545         * configure: Regenerated to track ../common/aclocal.m4 changes.
1546
1547 Sun Apr 26 15:31:55 1998  Tom Tromey  <tromey@creche>
1548
1549         * configure: Regenerated to track ../common/aclocal.m4 changes.
1550         * config.in: Ditto.
1551
1552 Sun Apr 26 15:20:01 1998  Tom Tromey  <tromey@cygnus.com>
1553
1554         * acconfig.h: New file.
1555         * configure.in: Reverted change of Apr 24; use sinclude again.
1556
1557 Fri Apr 24 14:16:40 1998  Tom Tromey  <tromey@creche>
1558
1559         * configure: Regenerated to track ../common/aclocal.m4 changes.
1560         * config.in: Ditto.
1561
1562 Fri Apr 24 11:19:20 1998  Tom Tromey  <tromey@cygnus.com>
1563
1564         * configure.in: Don't call sinclude.
1565
1566 Fri Apr 24 11:35:01 1998  Andrew Cagney  <cagney@chook.cygnus.com>
1567
1568         * mips.igen (do_store_left): Pass 0 not NULL to store_memory.
1569
1570 Tue Apr 21 11:59:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1571
1572         * mips.igen (ERET): Implement.
1573
1574         * interp.c (decode_coproc): Return sign-extended EPC.
1575
1576         * mips.igen (ANDI, LUI, MFC0): Add tracing code.
1577
1578         * interp.c (signal_exception): Do not ignore Trap.
1579         (signal_exception): On TRAP, restart at exception address.
1580         (HALT_INSTRUCTION, HALT_INSTRUCTION_MASK): Define.
1581         (signal_exception): Update.
1582         (sim_open): Patch V_COMMON interrupt vector with an abort sequence
1583         so that TRAP instructions are caught.
1584
1585 Mon Apr 20 11:26:55 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1586
1587         * sim-main.h (struct hilo_access, struct hilo_history): Define,
1588         contains HI/LO access history.
1589         (struct _sim_cpu): Make hiaccess and loaccess of type hilo_access.
1590         (HIACCESS, LOACCESS): Delete, replace with
1591         (HIHISTORY, LOHISTORY): New macros.
1592         (CHECKHILO): Delete all, moved to mips.igen
1593
1594         * gencode.c (build_instruction): Do not generate checks for
1595         correct HI/LO register usage.
1596
1597         * interp.c (old_engine_run): Delete checks for correct HI/LO
1598         register usage.
1599
1600         * mips.igen (check_mt_hilo, check_mf_hilo, check_op_hilo,
1601         check_mf_cycles): New functions.
1602         (do_mfhi, do_mflo, "mthi", "mtlo", do_ddiv, do_ddivu, do_div,
1603         do_divu, domultx, do_mult, do_multu): Use.
1604
1605         * tx.igen ("madd", "maddu"): Use.
1606
1607 Wed Apr 15 18:31:54 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1608
1609         * mips.igen (DSRAV): Use function do_dsrav.
1610         (SRAV): Use new function do_srav.
1611
1612         * m16.igen (BEQZ, BNEZ): Compare GPR[TRX] not GPR[RX].
1613         (B): Sign extend 11 bit immediate.
1614         (EXT-B*): Shift 16 bit immediate left by 1.
1615         (ADDIU*): Don't sign extend immediate value.
1616
1617 Wed Apr 15 10:32:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1618
1619         * m16run.c (sim_engine_run): Restore CIA after handling an event.
1620
1621         * sim-main.h (DELAY_SLOT, NULLIFY_NEXT_INSTRUCTION): For IGEN, use
1622         functions.
1623
1624         * mips.igen (delayslot32, nullify_next_insn): New functions.
1625         (m16.igen): Always include.
1626         (do_*): Add more tracing.
1627
1628         * m16.igen (delayslot16): Add NIA argument, could be called by a
1629         32 bit MIPS16 instruction.
1630
1631         * interp.c (ifetch16): Move function from here.
1632         * sim-main.c (ifetch16): To here.
1633
1634         * sim-main.c (ifetch16, ifetch32): Update to match current
1635         implementations of LH, LW.
1636         (signal_exception): Don't print out incorrect hex value of illegal
1637         instruction.
1638
1639 Wed Apr 15 00:17:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1640
1641         * m16run.c (sim_engine_run): Use IMEM16 and IMEM32 to fetch an
1642         instruction.
1643
1644         * m16.igen: Implement MIPS16 instructions.
1645
1646         * mips.igen (do_addiu, do_addu, do_and, do_daddiu, do_daddu,
1647         do_ddiv, do_ddivu, do_div, do_divu, do_dmultx, do_dmultu, do_srav,
1648         do_dsubu, do_mfhi, do_mflo, do_mult, do_multu, do_nor, do_or,
1649         do_sll, do_sllv, do_slt, do_slti, do_sltiu, do_sltu, do_sra,
1650         do_srl, do_srlv, do_subu, do_xor, do_xori): New functions.  Move
1651         bodies of corresponding code from 32 bit insn to these.  Also used
1652         by MIPS16 versions of functions.
1653
1654         * sim-main.h (RAIDX, T8IDX, T8, SPIDX): Define.
1655         (IMEM16): Drop NR argument from macro.
1656
1657 Sat Apr  4 22:39:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1658
1659         * Makefile.in (SIM_OBJS): Add sim-main.o.
1660
1661         * sim-main.h (address_translation, load_memory, store_memory,
1662         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Mark
1663         as INLINE_SIM_MAIN.
1664         (pr_addr, pr_uword64): Declare.
1665         (sim-main.c): Include when H_REVEALS_MODULE_P.
1666
1667         * interp.c (address_translation, load_memory, store_memory,
1668         cache_op, sync_operation, prefetch, ifetch32, pending_tick): Move
1669         from here.
1670         * sim-main.c: To here. Fix compilation problems.
1671
1672         * configure.in: Enable inlining.
1673         * configure: Re-config.
1674
1675 Sat Apr  4 20:36:25 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1676
1677         * configure: Regenerated to track ../common/aclocal.m4 changes.
1678
1679 Fri Apr  3 04:32:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1680
1681         * mips.igen: Include tx.igen.
1682         * Makefile.in (IGEN_INCLUDE): Add tx.igen.
1683         * tx.igen: New file, contains MADD and MADDU.
1684
1685         * interp.c (load_memory): When shifting bytes, use LOADDRMASK not
1686         the hardwired constant `7'.
1687         (store_memory): Ditto.
1688         (LOADDRMASK): Move definition to sim-main.h.
1689
1690         mips.igen (MTC0): Enable for r3900.
1691         (ADDU): Add trace.
1692
1693         mips.igen (do_load_byte): Delete.
1694         (do_load, do_store, do_load_left, do_load_write, do_store_left,
1695         do_store_right): New functions.
1696         (SW*, LW*, SD*, LD*, SH, LH, SB, LB): Use.
1697
1698         configure.in: Let the tx39 use igen again.
1699         configure: Update.
1700
1701 Thu Apr  2 10:59:39 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1702
1703         * interp.c (sim_monitor): get_mem_info returns a 4 byte quantity,
1704         not an address sized quantity.  Return zero for cache sizes.
1705
1706 Wed Apr  1 23:47:53 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1707
1708         * mips.igen (r3900): r3900 does not support 64 bit integer
1709         operations.
1710
1711 Mon Mar 30 14:46:05 1998  Gavin Koch  <gavin@cygnus.com>
1712
1713         * configure.in (mipstx39*-*-*): Use gencode simulator rather
1714         than igen one.
1715         * configure : Rebuild.
1716
1717 Fri Mar 27 16:15:52 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1718
1719         * configure: Regenerated to track ../common/aclocal.m4 changes.
1720
1721 Fri Mar 27 15:01:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1722
1723         * interp.c (mips_option_handler): Iterate over MAX_NR_PROCESSORS.
1724
1725 Wed Mar 25 16:44:27 1998  Ian Carmichael  <iancarm@cygnus.com>
1726
1727         * configure: Regenerated to track ../common/aclocal.m4 changes.
1728         * config.in: Regenerated to track ../common/aclocal.m4 changes.
1729
1730 Wed Mar 25 12:35:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1731
1732         * configure: Regenerated to track ../common/aclocal.m4 changes.
1733
1734 Wed Mar 25 10:05:46 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1735
1736         * interp.c (Max, Min): Comment out functions. Not yet used.
1737
1738 Wed Mar 18 12:38:12 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1739
1740         * configure: Regenerated to track ../common/aclocal.m4 changes.
1741
1742 Tue Mar 17 19:05:20 1998  Frank Ch. Eigler  <fche@cygnus.com>
1743
1744         * Makefile.in (MIPS_EXTRA_LIBS, SIM_EXTRA_LIBS): Added
1745         configurable settings for stand-alone simulator.
1746
1747         * configure.in: Added X11 search, just in case.
1748
1749         * configure: Regenerated.
1750
1751 Wed Mar 11 14:09:10 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1752
1753         * interp.c (sim_write, sim_read, load_memory, store_memory):
1754         Replace sim_core_*_map with read_map, write_map, exec_map resp.
1755
1756 Tue Mar  3 13:58:43 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1757
1758         * sim-main.h (GETFCC): Return an unsigned value.
1759
1760 Tue Mar  3 13:21:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1761
1762         * mips.igen (DIV): Fix check for -1 / MIN_INT.
1763         (DADD): Result destination is RD not RT.
1764
1765 Fri Feb 27 13:49:49 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1766
1767         * sim-main.h (HIACCESS, LOACCESS): Always define.
1768
1769         * mdmx.igen (Maxi, Mini): Rename Max, Min.
1770
1771         * interp.c (sim_info): Delete.
1772
1773 Fri Feb 27 18:41:01 1998  Doug Evans  <devans@canuck.cygnus.com>
1774
1775         * interp.c (DECLARE_OPTION_HANDLER): Use it.
1776         (mips_option_handler): New argument `cpu'.
1777         (sim_open): Update call to sim_add_option_table.
1778
1779 Wed Feb 25 18:56:22 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1780
1781         * mips.igen (CxC1): Add tracing.
1782
1783 Fri Feb 20 17:43:21 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1784
1785         * sim-main.h (Max, Min): Declare.
1786
1787         * interp.c (Max, Min): New functions.
1788
1789         * mips.igen (BC1): Add tracing.
1790
1791 Thu Feb 19 14:50:00 1998  John Metzler  <jmetzler@cygnus.com>
1792
1793         * interp.c Added memory map for stack in vr4100
1794
1795 Thu Feb 19 10:21:21 1998  Gavin Koch  <gavin@cygnus.com>
1796
1797         * interp.c (load_memory): Add missing "break"'s.
1798
1799 Tue Feb 17 12:45:35 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1800
1801         * interp.c (sim_store_register, sim_fetch_register): Pass in
1802         length parameter.  Return -1.
1803
1804 Tue Feb 10 11:57:40 1998  Ian Carmichael  <iancarm@cygnus.com>
1805
1806         * interp.c: Added hardware init hook, fixed warnings.
1807
1808 Sat Feb  7 17:16:20 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1809
1810         * Makefile.in (itable.h itable.c): Depend on SIM_@sim_gen@_ALL.
1811
1812 Tue Feb  3 11:36:02 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1813
1814         * interp.c (ifetch16): New function.
1815
1816         * sim-main.h (IMEM32): Rename IMEM.
1817         (IMEM16_IMMED): Define.
1818         (IMEM16): Define.
1819         (DELAY_SLOT): Update.
1820
1821         * m16run.c (sim_engine_run): New file.
1822
1823         * m16.igen: All instructions except LB.
1824         (LB): Call do_load_byte.
1825         * mips.igen (do_load_byte): New function.
1826         (LB): Call do_load_byte.
1827
1828         * mips.igen: Move spec for insn bit size and high bit from here.
1829         * Makefile.in (tmp-igen, tmp-m16): To here.
1830
1831         * m16.dc: New file, decode mips16 instructions.
1832
1833         * Makefile.in (SIM_NO_ALL): Define.
1834         (tmp-m16): Generate both 16 bit and 32 bit simulator engines.
1835
1836 Tue Feb  3 11:28:00 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1837
1838         * configure.in (mips_fpu_bitsize): For tx39, restrict floating
1839         point unit to 32 bit registers.
1840         * configure: Re-generate.
1841
1842 Sun Feb  1 15:47:14 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1843
1844         * configure.in (sim_use_gen): Make IGEN the default simulator
1845         generator for generic 32 and 64 bit mips targets.
1846         * configure: Re-generate.
1847
1848 Sun Feb  1 16:52:37 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1849
1850         * sim-main.h (SizeFGR): Determine from floating-point and not gpr
1851         bitsize.
1852
1853         * interp.c (sim_fetch_register, sim_store_register): Read/write
1854         FGR from correct location.
1855         (sim_open): Set size of FGR's according to
1856         WITH_TARGET_FLOATING_POINT_BITSIZE.
1857
1858         * sim-main.h (FGR): Store floating point registers in a separate
1859         array.
1860
1861 Sun Feb  1 16:47:51 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1862
1863         * configure: Regenerated to track ../common/aclocal.m4 changes.
1864
1865 Tue Feb  3 00:10:50 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1866
1867         * interp.c (ColdReset): Call PENDING_INVALIDATE.
1868
1869         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Call PENDING_TICK.
1870
1871         * interp.c (pending_tick): New function.  Deliver pending writes.
1872
1873         * sim-main.h (PENDING_FILL, PENDING_TICK, PENDING_SCHED,
1874         PENDING_BIT, PENDING_INVALIDATE): Re-write pipeline code so that
1875         it can handle mixed sized quantites and single bits.
1876
1877 Mon Feb  2 17:43:15 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1878
1879         * interp.c (oengine.h): Do not include when building with IGEN.
1880         (sim_open): Replace GPRLEN by WITH_TARGET_WORD_BITSIZE.
1881         (sim_info): Ditto for PROCESSOR_64BIT.
1882         (sim_monitor): Replace ut_reg with unsigned_word.
1883         (*): Ditto for t_reg.
1884         (LOADDRMASK): Define.
1885         (sim_open): Remove defunct check that host FP is IEEE compliant,
1886         using software to emulate floating point.
1887         (value_fpr, ...): Always compile, was conditional on HASFPU.
1888
1889 Sun Feb  1 11:15:29 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1890
1891         * sim-main.h (sim_state): Make the cpu array MAX_NR_PROCESSORS in
1892         size.
1893
1894         * interp.c (SD, CPU): Define.
1895         (mips_option_handler): Set flags in each CPU.
1896         (interrupt_event): Assume CPU 0 is the one being iterrupted.
1897         (sim_close): Do not clear STATE, deleted anyway.
1898         (sim_write, sim_read): Assume CPU zero's vm should be used for
1899         data transfers.
1900         (sim_create_inferior): Set the PC for all processors.
1901         (sim_monitor, store_word, load_word, mips16_entry): Add cpu
1902         argument.
1903         (mips16_entry): Pass correct nr of args to store_word, load_word.
1904         (ColdReset): Cold reset all cpu's.
1905         (signal_exception): Pass cpu to sim_monitor & mips16_entry.
1906         (sim_monitor, load_memory, store_memory, signal_exception): Use
1907         `CPU' instead of STATE_CPU.
1908
1909
1910         * sim-main.h: Replace uses of STATE_CPU with CPU. Replace sd with
1911         SD or CPU_.
1912
1913         * sim-main.h (signal_exception): Add sim_cpu arg.
1914         (SignalException*): Pass both SD and CPU to signal_exception.
1915         * interp.c (signal_exception): Update.
1916
1917         * sim-main.h (value_fpr, store_fpr, dotrace, ifetch32), interp.c:
1918         Ditto
1919         (sync_operation, prefetch, cache_op, store_memory, load_memory,
1920         address_translation): Ditto
1921         (decode_coproc, cop_lw, cop_ld, cop_sw, cop_sd): Ditto.
1922
1923 Sat Jan 31 18:15:41 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1924
1925         * configure: Regenerated to track ../common/aclocal.m4 changes.
1926
1927 Sat Jan 31 14:49:24 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1928
1929         * interp.c (sim_engine_run): Add `nr_cpus' argument.
1930
1931         * mips.igen (model): Map processor names onto BFD name.
1932
1933         * sim-main.h (CPU_CIA): Delete.
1934         (SET_CIA, GET_CIA): Define
1935
1936 Wed Jan 21 16:16:27 1998  Andrew Cagney  <cagney@b1.cygnus.com>
1937
1938         * sim-main.h (GPR_SET): Define, used by igen when zeroing a
1939         regiser.
1940
1941         * configure.in (default_endian): Configure a big-endian simulator
1942         by default.
1943         * configure: Re-generate.
1944
1945 Mon Jan 19 22:26:29 1998  Doug Evans  <devans@seba>
1946
1947         * configure: Regenerated to track ../common/aclocal.m4 changes.
1948
1949 Mon Jan  5 20:38:54 1998  Mark Alexander  <marka@cygnus.com>
1950
1951         * interp.c (sim_monitor): Handle Densan monitor outbyte
1952         and inbyte functions.
1953
1954 1997-12-29  Felix Lee  <flee@cygnus.com>
1955
1956         * interp.c (sim_engine_run): msvc cpp barfs on #if (a==b!=c).
1957
1958 Wed Dec 17 14:48:20 1997  Jeffrey A Law  (law@cygnus.com)
1959
1960         * Makefile.in (tmp-igen): Arrange for $zero to always be
1961         reset to zero after every instruction.
1962
1963 Mon Dec 15 23:17:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1964
1965         * configure: Regenerated to track ../common/aclocal.m4 changes.
1966         * config.in: Ditto.
1967
1968 Wed Dec 10 17:10:45 1997  Jeffrey A Law  (law@cygnus.com)
1969
1970         * mips.igen (MSUB): Fix to work like MADD.
1971         * gencode.c (MSUB): Similarly.
1972
1973 Thu Dec  4 09:21:05 1997  Doug Evans  <devans@canuck.cygnus.com>
1974
1975         * configure: Regenerated to track ../common/aclocal.m4 changes.
1976
1977 Wed Nov 26 11:00:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1978
1979         * mips.igen (LWC1): Correct assembler - lwc1 not swc1.
1980
1981 Sun Nov 23 01:45:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1982
1983         * sim-main.h (sim-fpu.h): Include.
1984
1985         * interp.c (convert, SquareRoot, Recip, Divide, Multiply, Sub,
1986         Add, Negate, AbsoluteValue, Equal, Less, Infinity, NaN): Rewrite
1987         using host independant sim_fpu module.
1988
1989 Thu Nov 20 19:56:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
1990
1991         * interp.c (signal_exception): Report internal errors with SIGABRT
1992         not SIGQUIT.
1993
1994         * sim-main.h (C0_CONFIG): New register.
1995         (signal.h): No longer include.
1996
1997         * interp.c (decode_coproc): Allow access C0_CONFIG to register.
1998
1999 Tue Nov 18 15:33:48 1997  Doug Evans  <devans@canuck.cygnus.com>
2000
2001         * Makefile.in (SIM_OBJS): Use $(SIM_NEW_COMMON_OBJS).
2002
2003 Fri Nov 14 11:56:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2004
2005         * mips.igen: Tag vr5000 instructions.
2006         (ANDI): Was missing mipsIV model, fix assembler syntax.
2007         (do_c_cond_fmt): New function.
2008         (C.cond.fmt): Handle mips I-III which do not support CC field
2009         separatly.
2010         (bc1): Handle mips IV which do not have a delaed FCC separatly.
2011         (SDR): Mask paddr when BigEndianMem, not the converse as specified
2012         in IV3.2 spec.
2013         (DMULT, DMULTU): Force use of hosts 64bit multiplication.  Handle
2014         vr5000 which saves LO in a GPR separatly.
2015
2016         * configure.in (enable-sim-igen): For vr5000, select vr5000
2017         specific instructions.
2018         * configure: Re-generate.
2019
2020 Wed Nov 12 14:42:52 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2021
2022         * Makefile.in (SIM_OBJS): Add sim-fpu module.
2023
2024         * interp.c (store_fpr), sim-main.h: Add separate fmt_uninterpreted_32 and
2025         fmt_uninterpreted_64 bit cases to switch.  Convert to
2026         fmt_formatted,
2027
2028         * sim-main.h (ENGINE_ISSUE_PREFIX_HOOK): Define,
2029
2030         * mips.igen (SWR): Mask paddr when BigEndianMem, not the converse
2031         as specified in IV3.2 spec.
2032         (MTC1, DMTC1): Call StoreFPR to store the GPR in the FPR.
2033
2034 Tue Nov 11 12:38:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2035
2036         * mips.igen: Delay slot branches add OFFSET to NIA not CIA.
2037         (MFC0, MTC0, SWC1, LWC1, SDC1, LDC1): Implement.
2038         (MTC1, MFC1, DMTC1, DMFC1, CFC1, CTC1): Implement separate non
2039         PENDING_FILL versions of instructions.  Simplify.
2040         (X): New function.
2041         (MULT, MULTU): Implement separate RD==0 and RD!=0 versions of
2042         instructions.
2043         (BEQZ, ..., SLT, SLTI, TLT, TLE, TLI, ...): Explicitly cast GPR to
2044         a signed value.
2045         (MTHI, MFHI): Disable code checking HI-LO.
2046
2047         * sim-main.h (dotrace,tracefh), interp.c: Make dotrace & tracefh
2048         global.
2049         (NULLIFY_NEXT_INSTRUCTION): Call dotrace.
2050
2051 Thu Nov  6 16:36:35 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2052
2053         * gencode.c (build_mips16_operands): Replace IPC with cia.
2054
2055         * interp.c (sim_monitor, signal_exception, cache_op, store_fpr,
2056         value_fpr, cop_ld, cop_lw, cop_sw, cop_sd, decode_coproc): Replace
2057         IPC to `cia'.
2058         (UndefinedResult): Replace function with macro/function
2059         combination.
2060         (sim_engine_run): Don't save PC in IPC.
2061
2062         * sim-main.h (IPC): Delete.
2063
2064
2065         * interp.c (signal_exception, store_word, load_word,
2066         address_translation, load_memory, store_memory, cache_op,
2067         prefetch, sync_operation, ifetch, value_fpr, store_fpr, convert,
2068         cop_lw, cop_ld, cop_sw, cop_sd, decode_coproc, sim_monitor): Add
2069         current instruction address - cia - argument.
2070         (sim_read, sim_write): Call address_translation directly.
2071         (sim_engine_run): Rename variable vaddr to cia.
2072         (signal_exception): Pass cia to sim_monitor
2073
2074         * sim-main.h (SignalException, LoadWord, StoreWord, CacheOp,
2075         Prefetch, SyncOperation, ValueFPR, StoreFPR, Convert, COP_LW,
2076         COP_LD, COP_SW, COP_SD, DecodeCoproc): Update.
2077
2078         * sim-main.h (SignalExceptionSimulatorFault): Delete definition.
2079         * interp.c (sim_open): Replace SignalExceptionSimulatorFault with
2080         SIM_ASSERT.
2081
2082         * interp.c (signal_exception): Pass restart address to
2083         sim_engine_restart.
2084
2085         * Makefile.in (semantics.o, engine.o, support.o, itable.o,
2086         idecode.o): Add dependency.
2087
2088         * sim-main.h (SIM_ENGINE_HALT_HOOK, SIM_ENGINE_RESUME_HOOK):
2089         Delete definitions
2090         (DELAY_SLOT): Update NIA not PC with branch address.
2091         (NULLIFY_NEXT_INSTRUCTION): Set NIA to instruction after next.
2092
2093         * mips.igen: Use CIA not PC in branch calculations.
2094         (illegal): Call SignalException.
2095         (BEQ, ADDIU): Fix assembler.
2096
2097 Wed Nov  5 12:19:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2098
2099         * m16.igen (JALX): Was missing.
2100
2101         * configure.in (enable-sim-igen): New configuration option.
2102         * configure: Re-generate.
2103
2104         * sim-main.h (MAX_INSNS, INSN_NAME): Define.
2105
2106         * interp.c (load_memory, store_memory): Delete parameter RAW.
2107         (sim_read, sim_write): Use sim_core_{read,write}_buffer directly
2108         bypassing {load,store}_memory.
2109
2110         * sim-main.h (ByteSwapMem): Delete definition.
2111
2112         * Makefile.in (SIM_OBJS): Add sim-memopt module.
2113
2114         * interp.c (sim_do_command, sim_commands): Delete mips specific
2115         commands.  Handled by module sim-options.
2116
2117         * sim-main.h (SIM_HAVE_FLATMEM): Undefine, use sim-core.o module.
2118         (WITH_MODULO_MEMORY): Define.
2119
2120         * interp.c (sim_info): Delete code printing memory size.
2121
2122         * interp.c (mips_size): Nee sim_size, delete function.
2123         (power2): Delete.
2124         (monitor, monitor_base, monitor_size): Delete global variables.
2125         (sim_open, sim_close): Delete code creating monitor and other
2126         memory regions.  Use sim-memopts module, via sim_do_commandf, to
2127         manage memory regions.
2128         (load_memory, store_memory): Use sim-core for memory model.
2129
2130         * interp.c (address_translation): Delete all memory map code
2131         except line forcing 32 bit addresses.
2132
2133 Wed Nov  5 11:21:11 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2134
2135         * sim-main.h (WITH_TRACE): Delete definition.  Enables common
2136         trace options.
2137
2138         * interp.c (logfh, logfile): Delete globals.
2139         (sim_open, sim_close): Delete code opening & closing log file.
2140         (mips_option_handler): Delete -l and -n options.
2141         (OPTION mips_options): Ditto.
2142
2143         * interp.c (OPTION mips_options): Rename option trace to dinero.
2144         (mips_option_handler): Update.
2145
2146 Wed Nov  5 09:35:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2147
2148         * interp.c (fetch_str): New function.
2149         (sim_monitor): Rewrite using sim_read & sim_write.
2150         (sim_open): Check magic number.
2151         (sim_open): Write monitor vectors into memory using sim_write.
2152         (MONITOR_BASE, MONITOR_SIZE, MEM_SIZE): Define.
2153         (sim_read, sim_write): Simplify - transfer data one byte at a
2154         time.
2155         (load_memory, store_memory): Clarify meaning of parameter RAW.
2156
2157         * sim-main.h (isHOST): Defete definition.
2158         (isTARGET): Mark as depreciated.
2159         (address_translation): Delete parameter HOST.
2160
2161         * interp.c (address_translation): Delete parameter HOST.
2162
2163 Wed Oct 29 11:13:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2164
2165         * mips.igen:
2166
2167         * Makefile.in (IGEN_INCLUDE): Files included by mips.igen.
2168         (tmp-igen, tmp-m16): Depend on IGEN_INCLUDE.
2169
2170 Tue Oct 28 11:06:47 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2171
2172         * mips.igen: Add model filter field to records.
2173
2174 Mon Oct 27 17:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2175
2176         * Makefile.in (SIM_NO_CFLAGS): Define.  Define WITH_IGEN=0.
2177
2178         interp.c (sim_engine_run): Do not compile function sim_engine_run
2179         when WITH_IGEN == 1.
2180
2181         * configure.in (sim_igen_flags, sim_m16_flags): Set according to
2182         target architecture.
2183
2184         Makefile.in (tmp-igen, tmp-m16): Drop -F and -M options to
2185         igen. Replace with configuration variables sim_igen_flags /
2186         sim_m16_flags.
2187
2188         * m16.igen: New file.  Copy mips16 insns here.
2189         * mips.igen: From here.
2190
2191 Mon Oct 27 13:53:59 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2192
2193         * Makefile.in (SIM_NO_OBJ): Define, move SIM_M16_OBJ, SIM_IGEN_OBJ
2194         to top.
2195         (tmp-igen, tmp-m16): Pass -I srcdir to igen.
2196
2197 Sat Oct 25 16:51:40 1997  Gavin Koch  <gavin@cygnus.com>
2198
2199         * gencode.c (build_instruction): Follow sim_write's lead in using
2200         BigEndianMem instead of !ByteSwapMem.
2201
2202 Fri Oct 24 17:41:49 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2203
2204         * configure.in (sim_gen): Dependent on target, select type of
2205         generator.  Always select old style generator.
2206
2207         configure: Re-generate.
2208
2209         Makefile.in (tmp-igen, tmp-m16, clean-m16, clean-igen): New
2210         targets.
2211         (SIM_M16_CFLAGS, SIM_M16_ALL, SIM_M16_OBJ, BUILT_SRC_FROM_M16,
2212         SIM_IGEN_CFLAGS, SIM_IGEN_ALL, SIM_IGEN_OBJ, BUILT_SRC_FROM_IGEN,
2213         IGEN_TRACE, IGEN_INSN, IGEN_DC): Define
2214         (SIM_EXTRA_CFLAGS, SIM_EXTRA_ALL, SIM_OBJS): Add member
2215         SIM_@sim_gen@_*, set by autoconf.
2216
2217 Wed Oct 22 12:52:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2218
2219         * sim-main.h (NULLIFY_NEXT_INSTRUCTION, DELAY_SLOT): Define.
2220
2221         * interp.c (ColdReset): Remove #ifdef HASFPU, check
2222         CURRENT_FLOATING_POINT instead.
2223
2224         * interp.c (ifetch32): New function. Fetch 32 bit instruction.
2225         (address_translation): Raise exception InstructionFetch when
2226         translation fails and isINSTRUCTION.
2227
2228         * interp.c (sim_open, sim_write, sim_monitor, store_word,
2229         sim_engine_run): Change type of of vaddr and paddr to
2230         address_word.
2231         (address_translation, prefetch, load_memory, store_memory,
2232         cache_op): Change type of vAddr and pAddr to address_word.
2233
2234         * gencode.c (build_instruction): Change type of vaddr and paddr to
2235         address_word.
2236
2237 Mon Oct 20 15:29:04 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2238
2239         * sim-main.h (ALU64_END, ALU32_END): Use ALU*_OVERFLOW_RESULT
2240         macro to obtain result of ALU op.
2241
2242 Tue Oct 21 17:39:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2243
2244         * interp.c (sim_info): Call profile_print.
2245
2246 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2247
2248         * Makefile.in (SIM_OBJS): Add sim-profile.o module.
2249
2250         * sim-main.h (WITH_PROFILE): Do not define, defined in
2251         common/sim-config.h.  Use sim-profile module.
2252         (simPROFILE): Delete defintion.
2253
2254         * interp.c (PROFILE): Delete definition.
2255         (mips_option_handler): Delete 'p', 'y' and 'x' profile options.
2256         (sim_close): Delete code writing profile histogram.
2257         (mips_set_profile, mips_set_profile_size, writeout16, writeout32):
2258         Delete.
2259         (sim_engine_run): Delete code profiling the PC.
2260
2261 Mon Oct 20 13:31:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2262
2263         * sim-main.h (SIGNEXTEND): Force type of result to unsigned_word.
2264
2265         * interp.c (sim_monitor): Make register pointers of type
2266         unsigned_word*.
2267
2268         * sim-main.h: Make registers of type unsigned_word not
2269         signed_word.
2270
2271 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2272
2273         * interp.c (sync_operation): Rename from SyncOperation, make
2274         global, add SD argument.
2275         (prefetch): Rename from Prefetch, make global, add SD argument.
2276         (decode_coproc): Make global.
2277
2278         * sim-main.h (SyncOperation, DecodeCoproc, Pefetch): Define.
2279
2280         * gencode.c (build_instruction): Generate DecodeCoproc not
2281         decode_coproc calls.
2282
2283         * interp.c (SETFCC, GETFCC, PREVCOC1): Move to sim-main.h
2284         (SizeFGR): Move to sim-main.h
2285         (simHALTEX, simHALTIN, simTRACE, simPROFILE, simDELAYSLOT,
2286         simSIGINT, simJALDELAYSLOT): Move to sim-main.h
2287         (FP_FLAGS, FP_ENABLE, FP_CAUSE, IR, UF, OF, DZ, IO, UO): Move to
2288         sim-main.h.
2289         (FP_FS, FP_MASK_RM, FP_SH_RM, FP_RM_NEAREST, FP_RM_TOPINF,
2290         FP_RM_TOMINF, GETRM): Move to sim-main.h.
2291         (Uncached, CachedNoncoherent, CachedCoherent, Cached,
2292         isINSTRUCTION, ..., AccessLength_BYTE, ...): Move to sim-main.h.
2293         (UserMode, BigEndianMem, ByteSwapMem, ReverseEndian,
2294         BigEndianCPU, status_KSU_mask, ...). Moved to sim-main.h
2295
2296         * sim-main.h (ALU32_END, ALU64_END): Define. When overflow raise
2297         exception.
2298         (sim-alu.h): Include.
2299         (NULLIFY_NIA, NULL_CIA, CPU_CIA): Define.
2300         (sim_cia): Typedef to instruction_address.
2301
2302 Thu Oct 16 10:31:41 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2303
2304         * Makefile.in (interp.o): Rename generated file engine.c to
2305         oengine.c.
2306
2307         * interp.c: Update.
2308
2309 Thu Oct 16 10:31:40 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2310
2311         * gencode.c (build_instruction): Use FPR_STATE not fpr_state.
2312
2313 Thu Oct 16 10:31:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2314
2315         * gencode.c (build_instruction): For "FPSQRT", output correct
2316         number of arguments to Recip.
2317
2318 Tue Oct 14 17:38:18 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2319
2320         * Makefile.in (interp.o): Depends on sim-main.h
2321
2322         * interp.c (mips16_entry, ColdReset,dotrace): Add SD argument. Use GPR not registers.
2323
2324         * sim-main.h (sim_cpu): Add registers, register_widths, fpr_state,
2325         ipc, dspc, pending_*, hiaccess, loaccess, state, dsstate fields.
2326         (REGISTERS, REGISTER_WIDTHS, FPR_STATE, IPC, DSPC, PENDING_*,
2327         STATE, DSSTATE): Define
2328         (GPR, FGRIDX, ..): Define.
2329
2330         * interp.c (registers, register_widths, fpr_state, ipc, dspc,
2331         pending_*, hiaccess, loaccess, state, dsstate): Delete globals.
2332         (GPR, FGRIDX, ...): Delete macros.
2333
2334         * interp.c: Update names to match defines from sim-main.h
2335
2336 Tue Oct 14 15:11:45 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2337
2338         * interp.c (sim_monitor): Add SD argument.
2339         (sim_warning): Delete.  Replace calls with calls to
2340         sim_io_eprintf.
2341         (sim_error): Delete. Replace calls with sim_io_error.
2342         (open_trace, writeout32, writeout16, getnum): Add SD argument.
2343         (mips_set_profile): Rename from sim_set_profile. Add SD argument.
2344         (mips_set_profile_size): Rename from sim_set_profile_size. Add SD
2345         argument.
2346         (mips_size): Rename from sim_size. Add SD argument.
2347
2348         * interp.c (simulator): Delete global variable.
2349         (callback): Delete global variable.
2350         (mips_option_handler, sim_open, sim_write, sim_read,
2351         sim_store_register, sim_fetch_register, sim_info, sim_do_command,
2352         sim_size,sim_monitor): Use sim_io_* not callback->*.
2353         (sim_open): ZALLOC simulator struct.
2354         (PROFILE): Do not define.
2355
2356 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2357
2358         * interp.c (sim_open), support.h: Replace CHECKSIM macro found in
2359         support.h with corresponding code.
2360
2361         * sim-main.h (word64, uword64), support.h: Move definition to
2362         sim-main.h.
2363         (WORD64LO, WORD64HI, SET64LO, SET64HI, WORD64, UWORD64): Ditto.
2364
2365         * support.h: Delete
2366         * Makefile.in: Update dependencies
2367         * interp.c: Do not include.
2368
2369 Tue Oct 14 13:35:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2370
2371         * interp.c (address_translation, load_memory, store_memory,
2372         cache_op): Rename to from AddressTranslation et.al., make global,
2373         add SD argument
2374
2375         * sim-main.h (AddressTranslation, LoadMemory, StoreMemory,
2376         CacheOp): Define.
2377
2378         * interp.c (SignalException): Rename to signal_exception, make
2379         global.
2380
2381         * interp.c (Interrupt, ...): Move definitions to sim-main.h.
2382
2383         * sim-main.h (SignalException, SignalExceptionInterrupt,
2384         SignalExceptionInstructionFetch, SignalExceptionAddressStore,
2385         SignalExceptionAddressLoad, SignalExceptionSimulatorFault,
2386         SignalExceptionIntegerOverflow, SignalExceptionCoProcessorUnusable):
2387         Define.
2388
2389         * interp.c, support.h: Use.
2390
2391 Tue Oct 14 13:19:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2392
2393         * interp.c (ValueFPR, StoreFPR), sim-main.h: Make global, rename
2394         to value_fpr / store_fpr. Add SD argument.
2395         (NaN, Infinity, Less, Equal, AbsoluteValue, Negate, Add, Sub,
2396         Multiply, Divide, Recip, SquareRoot, Convert): Make global.
2397
2398         * sim-main.h (ValueFPR, StoreFPR): Define.
2399
2400 Tue Oct 14 13:06:55 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2401
2402         * interp.c (sim_engine_run): Check consistency between configure
2403         WITH_TARGET_WORD_BITSIZE and WITH_FLOATING_POINT and gensim GPRLEN
2404         and HASFPU.
2405
2406         * configure.in (mips_bitsize): Configure WITH_TARGET_WORD_BITSIZE.
2407         (mips_fpu): Configure WITH_FLOATING_POINT.
2408         (mips_endian): Configure WITH_TARGET_ENDIAN.
2409         * configure: Update.
2410
2411 Fri Oct  3 09:28:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2412
2413         * configure: Regenerated to track ../common/aclocal.m4 changes.
2414
2415 Mon Sep 29 14:45:00 1997  Bob Manson  <manson@charmed.cygnus.com>
2416
2417         * configure: Regenerated.
2418
2419 Fri Sep 26 12:48:18 1997  Mark Alexander  <marka@cygnus.com>
2420
2421         * interp.c: Allow Debug, DEPC, and EPC registers to be examined in GDB.
2422
2423 Thu Sep 25 11:15:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2424
2425         * gencode.c (print_igen_insn_models): Assume certain architectures
2426         include all mips* instructions.
2427         (print_igen_insn_format): Use data_size==-1 as marker for MIPS16
2428         instruction.
2429
2430         * Makefile.in (tmp.igen): Add target. Generate igen input from
2431         gencode file.
2432
2433         * gencode.c (FEATURE_IGEN): Define.
2434         (main): Add --igen option.  Generate output in igen format.
2435         (process_instructions): Format output according to igen option.
2436         (print_igen_insn_format): New function.
2437         (print_igen_insn_models): New function.
2438         (process_instructions): Only issue warnings and ignore
2439         instructions when no FEATURE_IGEN.
2440
2441 Wed Sep 24 17:38:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2442
2443         * interp.c (COP_SD, COP_LD): Add UNUSED to pacify GCC for some
2444         MIPS targets.
2445
2446 Tue Sep 23 11:04:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2447
2448         * configure: Regenerated to track ../common/aclocal.m4 changes.
2449
2450 Tue Sep 23 10:19:51 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2451
2452         * Makefile.in (SIM_ALIGNMENT, SIM_ENDIAN, SIM_HOSTENDIAN,
2453         SIM_RESERVED_BITS): Delete, moved to common.
2454         (SIM_EXTRA_CFLAGS): Update.
2455
2456 Mon Sep 22 11:46:20 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2457
2458         * configure.in: Configure non-strict memory alignment.
2459         * configure: Regenerated to track ../common/aclocal.m4 changes.
2460
2461 Fri Sep 19 17:45:25 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2462
2463         * configure: Regenerated to track ../common/aclocal.m4 changes.
2464
2465 Sat Sep 20 14:07:28 1997  Gavin Koch  <gavin@cygnus.com>
2466
2467         * gencode.c (SDBBP,DERET): Added (3900) insns.
2468         (RFE): Turn on for 3900.
2469         * interp.c (DebugBreakPoint,DEPC,Debug,Debug_*): Added.
2470         (dsstate): Made global.
2471         (SUBTARGET_R3900): Added.
2472         (CANCELDELAYSLOT): New.
2473         (SignalException): Ignore SystemCall rather than ignore and
2474         terminate.  Add DebugBreakPoint handling.
2475         (decode_coproc): New insns RFE, DERET; and new registers Debug
2476         and DEPC protected by SUBTARGET_R3900.
2477         (sim_engine_run): Use CANCELDELAYSLOT rather than clearing
2478         bits explicitly.
2479         * Makefile.in,configure.in: Add mips subtarget option.
2480         * configure: Update.
2481
2482 Fri Sep 19 09:33:27 1997  Gavin Koch  <gavin@cygnus.com>
2483
2484         * gencode.c: Add r3900 (tx39).
2485
2486
2487 Tue Sep 16 15:52:04 1997  Gavin Koch  <gavin@cygnus.com>
2488
2489         * gencode.c (build_instruction): Don't need to subtract 4 for
2490         JALR, just 2.
2491
2492 Tue Sep 16 11:32:28 1997  Gavin Koch  <gavin@cygnus.com>
2493
2494         * interp.c: Correct some HASFPU problems.
2495
2496 Mon Sep 15 17:36:15 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2497
2498         * configure: Regenerated to track ../common/aclocal.m4 changes.
2499
2500 Fri Sep 12 12:01:39 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2501
2502         * interp.c (mips_options): Fix samples option short form, should
2503         be `x'.
2504
2505 Thu Sep 11 09:35:29 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2506
2507         * interp.c (sim_info): Enable info code.  Was just returning.
2508
2509 Tue Sep  9 17:30:57 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2510
2511         * interp.c (decode_coproc): Clarify warning about unsuported MTC0,
2512         MFC0.
2513
2514 Tue Sep  9 16:28:28 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2515
2516         * gencode.c (build_instruction): Use SIGNED64 for 64 bit
2517         constants.
2518         (build_instruction): Ditto for LL.
2519
2520 Thu Sep  4 17:21:23 1997  Doug Evans  <dje@seba>
2521
2522         * configure: Regenerated to track ../common/aclocal.m4 changes.
2523
2524 Wed Aug 27 18:13:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2525
2526         * configure: Regenerated to track ../common/aclocal.m4 changes.
2527         * config.in: Ditto.
2528
2529 Wed Aug 27 14:12:27 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2530
2531         * interp.c (sim_open): Add call to sim_analyze_program, update
2532         call to sim_config.
2533
2534 Tue Aug 26 10:40:07 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2535
2536         * interp.c (sim_kill): Delete.
2537         (sim_create_inferior): Add ABFD argument. Set PC from same.
2538         (sim_load): Move code initializing trap handlers from here.
2539         (sim_open): To here.
2540         (sim_load): Delete, use sim-hload.c.
2541
2542         * Makefile.in (SIM_OBJS): Add sim-hload.o module.
2543
2544 Mon Aug 25 17:50:22 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2545
2546         * configure: Regenerated to track ../common/aclocal.m4 changes.
2547         * config.in: Ditto.
2548
2549 Mon Aug 25 15:59:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2550
2551         * interp.c (sim_open): Add ABFD argument.
2552         (sim_load): Move call to sim_config from here.
2553         (sim_open): To here.  Check return status.
2554
2555 Fri Jul 25 15:00:45 1997  Gavin Koch  <gavin@cygnus.com>
2556
2557         * gencode.c (build_instruction): Two arg MADD should
2558         not assign result to $0.
2559
2560 Thu Jun 26 12:13:17 1997  Angela Marie Thomas (angela@cygnus.com)
2561
2562         * sim/mips/configure: Change default_sim_endian to 0 (bi-endian)
2563         * sim/mips/configure.in: Regenerate.
2564
2565 Wed Jul  9 10:29:21 1997  Andrew Cagney  <cagney@critters.cygnus.com>
2566
2567         * interp.c (SUB_REG_UW, SUB_REG_SW, SUB_REG_*): Use more explicit
2568         signed8, unsigned8 et.al. types.
2569
2570         * interp.c (SUB_REG_FETCH): Handle both little and big endian
2571         hosts when selecting subreg.
2572
2573 Wed Jul  2 11:54:10 1997  Jeffrey A Law  (law@cygnus.com)
2574
2575         * interp.c (sim_engine_run): Reset the ZERO register to zero
2576         regardless of FEATURE_WARN_ZERO.
2577         * gencode.c (FEATURE_WARNINGS): Remove FEATURE_WARN_ZERO.
2578
2579 Wed Jun  4 10:43:14 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2580
2581         * interp.c (decode_coproc): Implement MTC0 N, CAUSE.
2582         (SignalException): For BreakPoints ignore any mode bits and just
2583         save the PC.
2584         (SignalException): Always set the CAUSE register.
2585
2586 Tue Jun  3 05:00:33 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2587
2588         * interp.c (SignalException): Clear the simDELAYSLOT flag when an
2589         exception has been taken.
2590
2591         * interp.c: Implement the ERET and mt/f sr instructions.
2592
2593 Sat May 31 00:44:16 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2594
2595         * interp.c (SignalException): Don't bother restarting an
2596         interrupt.
2597
2598 Fri May 30 23:41:48 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2599
2600         * interp.c (SignalException): Really take an interrupt.
2601         (interrupt_event): Only deliver interrupts when enabled.
2602
2603 Tue May 27 20:08:06 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2604
2605         * interp.c (sim_info): Only print info when verbose.
2606         (sim_info) Use sim_io_printf for output.
2607
2608 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2609
2610         * interp.c (CoProcPresent): Add UNUSED attribute - not used by all
2611         mips architectures.
2612
2613 Tue May 27 14:22:23 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2614
2615         * interp.c (sim_do_command): Check for common commands if a
2616         simulator specific command fails.
2617
2618 Thu May 22 09:32:03 1997  Gavin Koch  <gavin@cygnus.com>
2619
2620         * interp.c (sim_engine_run): ifdef out uses of simSTOP, simSTEP
2621         and simBE when DEBUG is defined.
2622
2623 Wed May 21 09:08:10 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2624
2625         * interp.c (interrupt_event): New function.  Pass exception event
2626         onto exception handler.
2627
2628         * configure.in: Check for stdlib.h.
2629         * configure: Regenerate.
2630
2631         * gencode.c (build_instruction): Add UNUSED attribute to tempS
2632         variable declaration.
2633         (build_instruction): Initialize memval1.
2634         (build_instruction): Add UNUSED attribute to byte, bigend,
2635         reverse.
2636         (build_operands): Ditto.
2637
2638         * interp.c: Fix GCC warnings.
2639         (sim_get_quit_code): Delete.
2640
2641         * configure.in: Add INLINE, ENDIAN, HOSTENDIAN and WARNINGS.
2642         * Makefile.in: Ditto.
2643         * configure: Re-generate.
2644
2645         * Makefile.in (SIM_OBJS): Add sim-watch.o module.
2646
2647 Tue May 20 15:08:56 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2648
2649         * interp.c (mips_option_handler): New function parse argumes using
2650         sim-options.
2651         (myname): Replace with STATE_MY_NAME.
2652         (sim_open): Delete check for host endianness - performed by
2653         sim_config.
2654         (simHOSTBE, simBE): Delete, replaced by sim-endian flags.
2655         (sim_open): Move much of the initialization from here.
2656         (sim_load): To here.  After the image has been loaded and
2657         endianness set.
2658         (sim_open): Move ColdReset from here.
2659         (sim_create_inferior): To here.
2660         (sim_open): Make FP check less dependant on host endianness.
2661
2662         * Makefile.in (SIM_RUN_OBJS): Set to nrun.o - use new version or
2663         run.
2664         * interp.c (sim_set_callbacks): Delete.
2665
2666         * interp.c (membank, membank_base, membank_size): Replace with
2667         STATE_MEMORY, STATE_MEM_SIZE, STATE_MEM_BASE.
2668         (sim_open): Remove call to callback->init. gdb/run do this.
2669
2670         * interp.c: Update
2671
2672         * sim-main.h (SIM_HAVE_FLATMEM): Define.
2673
2674         * interp.c (big_endian_p): Delete, replaced by
2675         current_target_byte_order.
2676
2677 Tue May 20 13:55:00 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2678
2679         * interp.c (host_read_long, host_read_word, host_swap_word,
2680         host_swap_long): Delete. Using common sim-endian.
2681         (sim_fetch_register, sim_store_register): Use H2T.
2682         (pipeline_ticks): Delete.  Handled by sim-events.
2683         (sim_info): Update.
2684         (sim_engine_run): Update.
2685
2686 Tue May 20 13:42:03 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2687
2688         * interp.c (sim_stop_reason): Move code determining simEXCEPTION
2689         reason from here.
2690         (SignalException): To here. Signal using sim_engine_halt.
2691         (sim_stop_reason): Delete, moved to common.
2692
2693 Tue May 20 10:19:48 1997  Andrew Cagney  <cagney@b2.cygnus.com>
2694
2695         * interp.c (sim_open): Add callback argument.
2696         (sim_set_callbacks): Delete SIM_DESC argument.
2697         (sim_size): Ditto.
2698
2699 Mon May 19 18:20:38 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2700
2701         * Makefile.in (SIM_OBJS): Add common modules.
2702
2703         * interp.c (sim_set_callbacks): Also set SD callback.
2704         (set_endianness, xfer_*, swap_*): Delete.
2705         (host_read_word, host_read_long, host_swap_word, host_swap_long):
2706         Change to functions using sim-endian macros.
2707         (control_c, sim_stop): Delete, use common version.
2708         (simulate): Convert into.
2709         (sim_engine_run): This function.
2710         (sim_resume): Delete.
2711
2712         * interp.c (simulation): New variable - the simulator object.
2713         (sim_kind): Delete global - merged into simulation.
2714         (sim_load): Cleanup.  Move PC assignment from here.
2715         (sim_create_inferior): To here.
2716
2717         * sim-main.h: New file.
2718         * interp.c (sim-main.h): Include.
2719
2720 Thu Apr 24 00:39:51 1997  Doug Evans  <dje@canuck.cygnus.com>
2721
2722         * configure: Regenerated to track ../common/aclocal.m4 changes.
2723
2724 Wed Apr 23 17:32:19 1997  Doug Evans  <dje@canuck.cygnus.com>
2725
2726         * tconfig.in (SIM_HAVE_BIENDIAN): Define.
2727
2728 Mon Apr 21 17:16:13 1997  Gavin Koch  <gavin@cygnus.com>
2729
2730         * gencode.c (build_instruction): DIV instructions: check
2731         for division by zero and integer overflow before using
2732         host's division operation.
2733
2734 Thu Apr 17 03:18:14 1997  Doug Evans  <dje@canuck.cygnus.com>
2735
2736         * Makefile.in (SIM_OBJS): Add sim-load.o.
2737         * interp.c: #include bfd.h.
2738         (target_byte_order): Delete.
2739         (sim_kind, myname, big_endian_p): New static locals.
2740         (sim_open): Set sim_kind, myname.  Move call to set_endianness to
2741         after argument parsing.  Recognize -E arg, set endianness accordingly.
2742         (sim_load): Return SIM_RC.  New arg abfd.  Call sim_load_file to
2743         load file into simulator.  Set PC from bfd.
2744         (sim_create_inferior): Return SIM_RC.  Delete arg start_address.
2745         (set_endianness): Use big_endian_p instead of target_byte_order.
2746
2747 Wed Apr 16 17:55:37 1997  Andrew Cagney  <cagney@b1.cygnus.com>
2748
2749         * interp.c (sim_size): Delete prototype - conflicts with
2750         definition in remote-sim.h.  Correct definition.
2751
2752 Mon Apr  7 15:45:02 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2753
2754         * configure: Regenerated to track ../common/aclocal.m4 changes.
2755         * config.in: Ditto.
2756
2757 Wed Apr  2 15:06:28 1997  Doug Evans  <dje@canuck.cygnus.com>
2758
2759         * interp.c (sim_open): New arg `kind'.
2760
2761         * configure: Regenerated to track ../common/aclocal.m4 changes.
2762
2763 Wed Apr  2 14:34:19 1997 Andrew Cagney <cagney@kremvax.cygnus.com>
2764
2765         * configure: Regenerated to track ../common/aclocal.m4 changes.
2766
2767 Tue Mar 25 11:38:22 1997  Doug Evans  <dje@canuck.cygnus.com>
2768
2769         * interp.c (sim_open): Set optind to 0 before calling getopt.
2770
2771 Wed Mar 19 01:14:00 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2772
2773         * configure: Regenerated to track ../common/aclocal.m4 changes.
2774
2775 Mon Mar 17 10:52:59 1997  Gavin Koch  <gavin@cetus.cygnus.com>
2776
2777         * interp.c : Replace uses of pr_addr with pr_uword64
2778         where the bit length is always 64 independent of SIM_ADDR.
2779         (pr_uword64) : added.
2780
2781 Mon Mar 17 15:10:07 1997  Andrew Cagney  <cagney@kremvax.cygnus.com>
2782
2783         * configure: Re-generate.
2784
2785 Fri Mar 14 10:34:11 1997  Michael Meissner  <meissner@cygnus.com>
2786
2787         * configure: Regenerate to track ../common/aclocal.m4 changes.
2788
2789 Thu Mar 13 12:51:36 1997  Doug Evans  <dje@canuck.cygnus.com>
2790
2791         * interp.c (sim_open): New SIM_DESC result.  Argument is now
2792         in argv form.
2793         (other sim_*): New SIM_DESC argument.
2794
2795 Mon Feb 24 22:47:14 1997  Dawn Perchik  <dawn@cygnus.com>
2796
2797         * interp.c: Fix printing of addresses for non-64-bit targets.
2798         (pr_addr): Add function to print address based on size.
2799
2800 Wed Feb 19 14:42:09 1997  Mark Alexander  <marka@cygnus.com>
2801
2802         * interp.c (simopen): Add support for LSI MiniRISC PMON vectors.
2803
2804 Thu Feb 13 14:08:30 1997  Ian Lance Taylor  <ian@cygnus.com>
2805
2806         * gencode.c (build_mips16_operands): Correct computation of base
2807         address for extended PC relative instruction.
2808
2809 Thu Feb  6 17:16:15 1997  Ian Lance Taylor  <ian@cygnus.com>
2810
2811         * interp.c (mips16_entry): Add support for floating point cases.
2812         (SignalException): Pass floating point cases to mips16_entry.
2813         (ValueFPR): Don't restrict fmt_single and fmt_word to even
2814         registers.
2815         (StoreFPR): Likewise.  Also, don't clobber fpr + 1 for fmt_single
2816         or fmt_word.
2817         (COP_LW): Pass fmt_word rather than fmt_uninterpreted to StoreFPR,
2818         and then set the state to fmt_uninterpreted.
2819         (COP_SW): Temporarily set the state to fmt_word while calling
2820         ValueFPR.
2821
2822 Tue Feb  4 16:48:25 1997  Ian Lance Taylor  <ian@cygnus.com>
2823
2824         * gencode.c (build_instruction): The high order may be set in the
2825         comparison flags at any ISA level, not just ISA 4.
2826
2827 Tue Feb  4 13:33:30 1997  Doug Evans  <dje@canuck.cygnus.com>
2828
2829         * Makefile.in (@COMMON_MAKEFILE_FRAG): Use
2830         COMMON_{PRE,POST}_CONFIG_FRAG instead.
2831         * configure.in: sinclude ../common/aclocal.m4.
2832         * configure: Regenerated.
2833
2834 Fri Jan 31 11:11:45 1997  Ian Lance Taylor  <ian@cygnus.com>
2835
2836         * configure: Rebuild after change to aclocal.m4.
2837
2838 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
2839
2840         * configure configure.in Makefile.in:  Update to new configure
2841         scheme which is more compatible with WinGDB builds.
2842         * configure.in:  Improve comment on how to run autoconf.
2843         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
2844         * Makefile.in:  Use autoconf substitution to install common
2845         makefile fragment.
2846
2847 Wed Jan  8 12:39:03 1997  Jim Wilson  <wilson@cygnus.com>
2848
2849         * gencode.c (build_instruction): Use BigEndianCPU instead of
2850         ByteSwapMem.
2851
2852 Thu Jan 02 22:23:04 1997  Mark Alexander  <marka@cygnus.com>
2853
2854         * interp.c (sim_monitor): Make output to stdout visible in
2855         wingdb's I/O log window.
2856
2857 Tue Dec 31 07:04:00 1996  Mark Alexander  <marka@cygnus.com>
2858
2859         * support.h: Undo previous change to SIGTRAP
2860         and SIGQUIT values.
2861
2862 Mon Dec 30 17:36:06 1996  Ian Lance Taylor  <ian@cygnus.com>
2863
2864         * interp.c (store_word, load_word): New static functions.
2865         (mips16_entry): New static function.
2866         (SignalException): Look for mips16 entry and exit instructions.
2867         (simulate): Use the correct index when setting fpr_state after
2868         doing a pending move.
2869
2870 Sun Dec 29 09:37:18 1996  Mark Alexander  <marka@cygnus.com>
2871
2872         * interp.c: Fix byte-swapping code throughout to work on
2873         both little- and big-endian hosts.
2874
2875 Sun Dec 29 09:18:32 1996  Mark Alexander  <marka@cygnus.com>
2876
2877         * support.h: Make definitions of SIGTRAP and SIGQUIT consistent
2878         with gdb/config/i386/xm-windows.h.
2879
2880 Fri Dec 27 22:48:51 1996  Mark Alexander  <marka@cygnus.com>
2881
2882         * gencode.c (build_instruction): Work around MSVC++ code gen bug
2883         that messes up arithmetic shifts.
2884
2885 Fri Dec 20 11:04:05 1996  Stu Grossman  (grossman@critters.cygnus.com)
2886
2887         * support.h:  Use _WIN32 instead of __WIN32__.  Also add defs for
2888         SIGTRAP and SIGQUIT for _WIN32.
2889
2890 Thu Dec 19 14:07:27 1996  Ian Lance Taylor  <ian@cygnus.com>
2891
2892         * gencode.c (build_instruction) [MUL]: Cast operands to word64, to
2893         force a 64 bit multiplication.
2894         (build_instruction) [OR]: In mips16 mode, don't do anything if the
2895         destination register is 0, since that is the default mips16 nop
2896         instruction.
2897
2898 Mon Dec 16 14:59:38 1996  Ian Lance Taylor  <ian@cygnus.com>
2899
2900         * gencode.c (MIPS16_DECODE): SWRASP is I8, not RI.
2901         (build_endian_shift): Don't check proc64.
2902         (build_instruction): Always set memval to uword64.  Cast op2 to
2903         uword64 when shifting it left in memory instructions.  Always use
2904         the same code for stores--don't special case proc64.
2905
2906         * gencode.c (build_mips16_operands): Fix base PC value for PC
2907         relative operands.
2908         (build_instruction): Call JALDELAYSLOT rather than DELAYSLOT for a
2909         jal instruction.
2910         * interp.c (simJALDELAYSLOT): Define.
2911         (JALDELAYSLOT): Define.
2912         (INDELAYSLOT, INJALDELAYSLOT): Define.
2913         (simulate): Clear simJALDELAYSLOT when simDELAYSLOT is cleared.
2914
2915 Tue Dec 24 22:11:20 1996  Angela Marie Thomas (angela@cygnus.com)
2916
2917         * interp.c (sim_open): add flush_cache as a PMON routine
2918         (sim_monitor): handle flush_cache by ignoring it
2919
2920 Wed Dec 11 13:53:51 1996  Jim Wilson  <wilson@cygnus.com>
2921
2922         * gencode.c (build_instruction): Use !ByteSwapMem instead of
2923         BigEndianMem.
2924         * interp.c (CONFIG, config_EP_{mask,shift,D,DxxDxx, config_BE): Delete.
2925         (BigEndianMem): Rename to ByteSwapMem and change sense.
2926         (BigEndianCPU, sim_write, LoadMemory, StoreMemory): Change
2927         BigEndianMem references to !ByteSwapMem.
2928         (set_endianness): New function, with prototype.
2929         (sim_open): Call set_endianness.
2930         (sim_info): Use simBE instead of BigEndianMem.
2931         (xfer_direct_word, xfer_direct_long, swap_direct_word,
2932         swap_direct_long, xfer_big_word, xfer_big_long, xfer_little_word,
2933         xfer_little_long, swap_word, swap_long): Delete unnecessary MSC_VER
2934         ifdefs, keeping the prototype declaration.
2935         (swap_word): Rewrite correctly.
2936         (ColdReset): Delete references to CONFIG.  Delete endianness related
2937         code; moved to set_endianness.
2938
2939 Tue Dec 10 11:32:04 1996  Jim Wilson  <wilson@cygnus.com>
2940
2941         * gencode.c (build_instruction, case JUMP): Truncate PC to 32 bits.
2942         * interp.c (CHECKHILO): Define away.
2943         (simSIGINT): New macro.
2944         (membank_size): Increase from 1MB to 2MB.
2945         (control_c): New function.
2946         (sim_resume): Rename parameter signal to signal_number.  Add local
2947         variable prev.  Call signal before and after simulate.
2948         (sim_stop_reason): Add simSIGINT support.
2949         (sim_warning, sim_error, dotrace, SignalException): Define as stdarg
2950         functions always.
2951         (sim_warning): Delete call to SignalException.  Do call printf_filtered
2952         if logfh is NULL.
2953         (AddressTranslation): Add #ifdef DEBUG around debugging message and
2954         a call to sim_warning.
2955
2956 Wed Nov 27 11:53:50 1996  Ian Lance Taylor  <ian@cygnus.com>
2957
2958         * gencode.c (process_instructions): If ! proc64, skip DOUBLEWORD
2959         16 bit instructions.
2960
2961 Tue Nov 26 11:53:12 1996  Ian Lance Taylor  <ian@cygnus.com>
2962
2963         Add support for mips16 (16 bit MIPS implementation):
2964         * gencode.c (inst_type): Add mips16 instruction encoding types.
2965         (GETDATASIZEINSN): Define.
2966         (MIPS_DECODE): Add REG flag to dsllv, dsrav, and dsrlv.  Add
2967         jalx.  Add LEFT flag to mfhi and mflo.  Add RIGHT flag to mthi and
2968         mtlo.
2969         (MIPS16_DECODE): New table, for mips16 instructions.
2970         (bitmap_val): New static function.
2971         (struct mips16_op): Define.
2972         (mips16_op_table): New table, for mips16 operands.
2973         (build_mips16_operands): New static function.
2974         (process_instructions): If PC is odd, decode a mips16
2975         instruction.  Break out instruction handling into new
2976         build_instruction function.
2977         (build_instruction): New static function, broken out of
2978         process_instructions.  Check modifiers rather than flags for SHIFT
2979         bit count and m[ft]{hi,lo} direction.
2980         (usage): Pass program name to fprintf.
2981         (main): Remove unused variable this_option_optind.  Change
2982         ``*loptarg++'' to ``loptarg++''.
2983         (my_strtoul): Parenthesize && within ||.
2984         * interp.c (LoadMemory): Accept a halfword pAddr if vAddr is odd.
2985         (simulate): If PC is odd, fetch a 16 bit instruction, and
2986         increment PC by 2 rather than 4.
2987         * configure.in: Add case for mips16*-*-*.
2988         * configure: Rebuild.
2989
2990 Fri Nov 22 08:49:36 1996  Mark Alexander  <marka@cygnus.com>
2991
2992         * interp.c: Allow -t to enable tracing in standalone simulator.
2993         Fix garbage output in trace file and error messages.
2994
2995 Wed Nov 20 01:54:37 1996  Doug Evans  <dje@canuck.cygnus.com>
2996
2997         * Makefile.in: Delete stuff moved to ../common/Make-common.in.
2998         (SIM_{OBJS,EXTRA_CFLAGS,EXTRA_CLEAN}): Define.
2999         * configure.in: Simplify using macros in ../common/aclocal.m4.
3000         * configure: Regenerated.
3001         * tconfig.in: New file.
3002
3003 Tue Nov 12 13:34:00 1996  Dawn Perchik  <dawn@cygnus.com>
3004
3005         * interp.c: Fix bugs in 64-bit port.
3006         Use ansi function declarations for msvc compiler.
3007         Initialize and test file pointer in trace code.
3008         Prevent duplicate definition of LAST_EMED_REGNUM.
3009
3010 Tue Oct 15 11:07:06 1996  Mark Alexander  <marka@cygnus.com>
3011
3012         * interp.c (xfer_big_long): Prevent unwanted sign extension.
3013
3014 Thu Sep 26 17:35:00 1996  James G. Smith  <jsmith@cygnus.co.uk>
3015
3016         * interp.c (SignalException): Check for explicit terminating
3017         breakpoint value.
3018         * gencode.c: Pass instruction value through SignalException()
3019         calls for Trap, Breakpoint and Syscall.
3020
3021 Thu Sep 26 11:35:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3022
3023         * interp.c (SquareRoot): Add HAVE_SQRT check to ensure sqrt() is
3024         only used on those hosts that provide it.
3025         * configure.in: Add sqrt() to list of functions to be checked for.
3026         * config.in: Re-generated.
3027         * configure: Re-generated.
3028
3029 Fri Sep 20 15:47:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3030
3031         * gencode.c (process_instructions): Call build_endian_shift when
3032         expanding STORE RIGHT, to fix swr.
3033         * support.h (SIGNEXTEND): If the sign bit is not set, explicitly
3034         clear the high bits.
3035         * interp.c (Convert): Fix fmt_single to fmt_long to not truncate.
3036         Fix float to int conversions to produce signed values.
3037
3038 Thu Sep 19 15:34:17 1996  Ian Lance Taylor  <ian@cygnus.com>
3039
3040         * gencode.c (MIPS_DECODE): Set UNSIGNED for multu instruction.
3041         (process_instructions): Correct handling of nor instruction.
3042         Correct shift count for 32 bit shift instructions. Correct sign
3043         extension for arithmetic shifts to not shift the number of bits in
3044         the type.  Fix 64 bit multiply high word calculation.  Fix 32 bit
3045         unsigned multiply.  Fix ldxc1 and friends to use coprocessor 1.
3046         Fix madd.
3047         * interp.c (CHECKHILO): Don't set HIACCESS, LOACCESS, or HLPC.
3048         It's OK to have a mult follow a mult.  What's not OK is to have a
3049         mult follow an mfhi.
3050         (Convert): Comment out incorrect rounding code.
3051
3052 Mon Sep 16 11:38:16 1996  James G. Smith  <jsmith@cygnus.co.uk>
3053
3054         * interp.c (sim_monitor): Improved monitor printf
3055         simulation. Tidied up simulator warnings, and added "--log" option
3056         for directing warning message output.
3057         * gencode.c: Use sim_warning() rather than WARNING macro.
3058
3059 Thu Aug 22 15:03:12 1996  Ian Lance Taylor  <ian@cygnus.com>
3060
3061         * Makefile.in (gencode): Depend upon gencode.o, getopt.o, and
3062         getopt1.o, rather than on gencode.c.  Link objects together.
3063         Don't link against -liberty.
3064         (gencode.o, getopt.o, getopt1.o): New targets.
3065         * gencode.c: Include <ctype.h> and "ansidecl.h".
3066         (AND): Undefine after including "ansidecl.h".
3067         (ULONG_MAX): Define if not defined.
3068         (OP_*): Don't define macros; now defined in opcode/mips.h.
3069         (main): Call my_strtoul rather than strtoul.
3070         (my_strtoul): New static function.
3071
3072 Wed Jul 17 18:12:38 1996  Stu Grossman  (grossman@critters.cygnus.com)
3073
3074         * gencode.c (process_instructions):  Generate word64 and uword64
3075         instead of `long long' and `unsigned long long' data types.
3076         * interp.c:  #include sysdep.h to get signals, and define default
3077         for SIGBUS.
3078         * (Convert):  Work around for Visual-C++ compiler bug with type
3079         conversion.
3080         * support.h:  Make things compile under Visual-C++ by using
3081         __int64 instead of `long long'.  Change many refs to long long
3082         into word64/uword64 typedefs.
3083
3084 Wed Jun 26 12:24:55 1996  Jason Molenda  (crash@godzilla.cygnus.co.jp)
3085
3086         * Makefile.in (bindir, libdir, datadir, mandir, infodir, includedir,
3087         INSTALL_PROGRAM, INSTALL_DATA): Use autoconf-set values.
3088         (docdir): Removed.
3089         * configure.in (AC_PREREQ): autoconf 2.5 or higher.
3090         (AC_PROG_INSTALL): Added.
3091         (AC_PROG_CC): Moved to before configure.host call.
3092         * configure: Rebuilt.
3093
3094 Wed Jun  5 08:28:13 1996  James G. Smith  <jsmith@cygnus.co.uk>
3095
3096         * configure.in: Define @SIMCONF@ depending on mips target.
3097         * configure: Rebuild.
3098         * Makefile.in (run): Add @SIMCONF@ to control simulator
3099         construction.
3100         * gencode.c: Change LOADDRMASK to 64bit memory model only.
3101         * interp.c: Remove some debugging, provide more detailed error
3102         messages, update memory accesses to use LOADDRMASK.
3103
3104 Mon Jun  3 11:55:03 1996  Ian Lance Taylor  <ian@cygnus.com>
3105
3106         * configure.in: Add calls to AC_CONFIG_HEADER, AC_CHECK_HEADERS,
3107         AC_CHECK_LIB, and AC_CHECK_FUNCS.  Change AC_OUTPUT to set
3108         stamp-h.
3109         * configure: Rebuild.
3110         * config.in: New file, generated by autoheader.
3111         * interp.c: Include "config.h".  Include <stdlib.h>, <string.h>,
3112         and <strings.h> if they exist.  Replace #ifdef sun with #ifdef
3113         HAVE_ANINT and HAVE_AINT, as appropriate.
3114         * Makefile.in (run): Use @LIBS@ rather than -lm.
3115         (interp.o): Depend upon config.h.
3116         (Makefile): Just rebuild Makefile.
3117         (clean): Remove stamp-h.
3118         (mostlyclean): Make the same as clean, not as distclean.
3119         (config.h, stamp-h): New targets.
3120
3121 Fri May 10 00:41:17 1996  James G. Smith  <jsmith@cygnus.co.uk>
3122
3123         * interp.c (ColdReset): Fix boolean test. Make all simulator
3124         globals static.
3125
3126 Wed May  8 15:12:58 1996  James G. Smith  <jsmith@cygnus.co.uk>
3127
3128         * interp.c (xfer_direct_word, xfer_direct_long,
3129         swap_direct_word, swap_direct_long, xfer_big_word,
3130         xfer_big_long, xfer_little_word, xfer_little_long,
3131         swap_word,swap_long): Added.
3132         * interp.c (ColdReset): Provide function indirection to
3133         host<->simulated_target transfer routines.
3134         * interp.c (sim_store_register, sim_fetch_register): Updated to
3135         make use of indirected transfer routines.
3136
3137 Fri Apr 19 15:48:24 1996  James G. Smith  <jsmith@cygnus.co.uk>
3138
3139         * gencode.c (process_instructions): Ensure FP ABS instruction
3140         recognised.
3141         * interp.c (AbsoluteValue): Add routine. Also provide simple PMON
3142         system call support.
3143
3144 Wed Apr 10 09:51:38 1996  James G. Smith  <jsmith@cygnus.co.uk>
3145
3146         * interp.c (sim_do_command): Complain if callback structure not
3147         initialised.
3148
3149 Thu Mar 28 13:50:51 1996  James G. Smith  <jsmith@cygnus.co.uk>
3150
3151         * interp.c (Convert): Provide round-to-nearest and round-to-zero
3152         support for Sun hosts.
3153         * Makefile.in (gencode): Ensure the host compiler and libraries
3154         used for cross-hosted build.
3155
3156 Wed Mar 27 14:42:12 1996  James G. Smith  <jsmith@cygnus.co.uk>
3157
3158         * interp.c, gencode.c: Some more (TODO) tidying.
3159
3160 Thu Mar  7 11:19:33 1996  James G. Smith  <jsmith@cygnus.co.uk>
3161
3162         * gencode.c, interp.c: Replaced explicit long long references with
3163         WORD64HI, WORD64LO, SET64HI and SET64LO macro calls.
3164         * support.h (SET64LO, SET64HI): Macros added.
3165
3166 Wed Feb 21 12:16:21 1996  Ian Lance Taylor  <ian@cygnus.com>
3167
3168         * configure: Regenerate with autoconf 2.7.
3169
3170 Tue Jan 30 08:48:18 1996  Fred Fish  <fnf@cygnus.com>
3171
3172         * interp.c (LoadMemory): Enclose text following #endif in /* */.
3173         * support.h: Remove superfluous "1" from #if.
3174         * support.h (CHECKSIM): Remove stray 'a' at end of line.
3175
3176 Mon Dec  4 11:44:40 1995  Jamie Smith  <jsmith@cygnus.com>
3177
3178         * interp.c (StoreFPR): Control UndefinedResult() call on
3179         WARN_RESULT manifest.
3180
3181 Fri Dec  1 16:37:19 1995  James G. Smith  <jsmith@cygnus.co.uk>
3182
3183         * gencode.c: Tidied instruction decoding, and added FP instruction
3184         support.
3185
3186         * interp.c: Added dineroIII, and BSD profiling support. Also
3187         run-time FP handling.
3188
3189 Sun Oct 22 00:57:18 1995  James G. Smith  <jsmith@pasanda.cygnus.co.uk>
3190
3191         * Changelog, Makefile.in, README.Cygnus, configure, configure.in,
3192         gencode.c, interp.c, support.h: created.