2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
83 /* The following reserved instruction value is used when a simulator
84 trap is required. NOTE: Care must be taken, since this value may be
85 used in later revisions of the MIPS ISA. */
86 #define RSVD_INSTRUCTION (0x00000005)
87 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
89 #define RSVD_INSTRUCTION_ARG_SHIFT 6
90 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
93 /* Bits in the Debug register */
94 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
95 #define Debug_DM 0x40000000 /* Debug Mode */
96 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
102 /*---------------------------------------------------------------------------*/
103 /*-- GDB simulator interface ------------------------------------------------*/
104 /*---------------------------------------------------------------------------*/
106 static void ColdReset
PARAMS((SIM_DESC sd
));
108 /*---------------------------------------------------------------------------*/
112 #define DELAYSLOT() {\
113 if (STATE & simDELAYSLOT)\
114 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
115 STATE |= simDELAYSLOT;\
118 #define JALDELAYSLOT() {\
120 STATE |= simJALDELAYSLOT;\
124 STATE &= ~simDELAYSLOT;\
125 STATE |= simSKIPNEXT;\
128 #define CANCELDELAYSLOT() {\
130 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
133 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
134 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
136 #define K0BASE (0x80000000)
137 #define K0SIZE (0x20000000)
138 #define K1BASE (0xA0000000)
139 #define K1SIZE (0x20000000)
140 #define MONITOR_BASE (0xBFC00000)
141 #define MONITOR_SIZE (1 << 11)
142 #define MEM_SIZE (2 << 20)
145 static char *tracefile
= "trace.din"; /* default filename for trace log */
146 FILE *tracefh
= NULL
;
147 static void open_trace
PARAMS((SIM_DESC sd
));
150 #define OPTION_DINERO_TRACE 200
151 #define OPTION_DINERO_FILE 201
154 mips_option_handler (sd
, opt
, arg
)
161 case OPTION_DINERO_TRACE
: /* ??? */
163 /* Eventually the simTRACE flag could be treated as a toggle, to
164 allow external control of the program points being traced
165 (i.e. only from main onwards, excluding the run-time setup,
169 else if (strcmp (arg
, "yes") == 0)
171 else if (strcmp (arg
, "no") == 0)
173 else if (strcmp (arg
, "on") == 0)
175 else if (strcmp (arg
, "off") == 0)
179 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
185 Simulator constructed without dinero tracing support (for performance).\n\
186 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
190 case OPTION_DINERO_FILE
:
192 if (optarg
!= NULL
) {
194 tmp
= (char *)malloc(strlen(optarg
) + 1);
197 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
203 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
214 static const OPTION mips_options
[] =
216 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
217 '\0', "on|off", "Enable dinero tracing",
218 mips_option_handler
},
219 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
220 '\0', "FILE", "Write dinero trace to FILE",
221 mips_option_handler
},
222 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
226 int interrupt_pending
;
229 interrupt_event (SIM_DESC sd
, void *data
)
233 interrupt_pending
= 0;
234 SignalExceptionInterrupt ();
236 else if (!interrupt_pending
)
237 sim_events_schedule (sd
, 1, interrupt_event
, data
);
242 /*---------------------------------------------------------------------------*/
243 /*-- GDB simulator interface ------------------------------------------------*/
244 /*---------------------------------------------------------------------------*/
247 sim_open (kind
, cb
, abfd
, argv
)
253 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
254 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
256 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
258 /* FIXME: watchpoints code shouldn't need this */
259 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
260 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
261 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
265 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
267 sim_add_option_table (sd
, mips_options
);
269 /* Allocate core managed memory */
272 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
273 /* For compatibility with the old code - under this (at level one)
274 are the kernel spaces K0 & K1. Both of these map to a single
275 smaller sub region */
276 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
278 MEM_SIZE
, /* actual size */
281 /* getopt will print the error message so we just have to exit if this fails.
282 FIXME: Hmmm... in the case of gdb we need getopt to call
284 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
286 /* Uninstall the modules to avoid memory leaks,
287 file descriptor leaks, etc. */
288 sim_module_uninstall (sd
);
292 /* check for/establish the a reference program image */
293 if (sim_analyze_program (sd
,
294 (STATE_PROG_ARGV (sd
) != NULL
295 ? *STATE_PROG_ARGV (sd
)
299 sim_module_uninstall (sd
);
303 /* Configure/verify the target byte order and other runtime
304 configuration options */
305 if (sim_config (sd
) != SIM_RC_OK
)
307 sim_module_uninstall (sd
);
311 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
313 /* Uninstall the modules to avoid memory leaks,
314 file descriptor leaks, etc. */
315 sim_module_uninstall (sd
);
319 /* verify assumptions the simulator made about the host type system.
320 This macro does not return if there is a problem */
321 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
322 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
325 /* Check that the host FPU conforms to IEEE 754-1985 for the SINGLE
326 and DOUBLE binary formats. This is a bit nasty, requiring that we
327 trust the explicit manifests held in the source: */
328 /* TODO: We need to cope with the simulated target and the host not
329 having the same endianness. This will require the high and low
330 words of a (double) to be swapped when converting between the
331 host and the simulated target. */
339 s
.d
= (double)523.2939453125;
341 if ((s
.i
[0] == 0 && (s
.f
[1] != (float)4.01102924346923828125
342 || s
.i
[1] != 0x40805A5A))
343 || (s
.i
[1] == 0 && (s
.f
[0] != (float)4.01102924346923828125
344 || s
.i
[0] != 0x40805A5A)))
346 fprintf(stderr
,"The host executing the simulator does not seem to have IEEE 754-1985 std FP\n");
352 /* This is NASTY, in that we are assuming the size of specific
356 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++) {
358 cpu
->register_widths
[rn
] = GPRLEN
;
359 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ 32)))
360 cpu
->register_widths
[rn
] = GPRLEN
;
361 else if ((rn
>= 33) && (rn
<= 37))
362 cpu
->register_widths
[rn
] = GPRLEN
;
363 else if ((rn
== SRIDX
) || (rn
== FCR0IDX
) || (rn
== FCR31IDX
) || ((rn
>= 72) && (rn
<= 89)))
364 cpu
->register_widths
[rn
] = 32;
366 cpu
->register_widths
[rn
] = 0;
368 /* start-sanitize-r5900 */
370 /* set the 5900 "upper" registers to 64 bits */
371 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
372 cpu
->register_widths
[rn
] = 64;
373 /* end-sanitize-r5900 */
377 if (STATE
& simTRACE
)
381 /* Write the monitor trap address handlers into the monitor (eeprom)
382 address space. This can only be done once the target endianness
383 has been determined. */
386 /* Entry into the IDT monitor is via fixed address vectors, and
387 not using machine instructions. To avoid clashing with use of
388 the MIPS TRAP system, we place our own (simulator specific)
389 "undefined" instructions into the relevant vector slots. */
390 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
392 address_word vaddr
= (MONITOR_BASE
+ loop
);
393 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
395 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
397 /* The PMON monitor uses the same address space, but rather than
398 branching into it the address of a routine is loaded. We can
399 cheat for the moment, and direct the PMON routine to IDT style
400 instructions within the monitor space. This relies on the IDT
401 monitor not using the locations from 0xBFC00500 onwards as its
403 for (loop
= 0; (loop
< 24); loop
++)
405 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
406 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
422 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
424 case 8: /* cliexit */
427 case 11: /* flush_cache */
431 /* FIXME - should monitor_base be SIM_ADDR?? */
432 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
434 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
436 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
438 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
450 tracefh
= fopen(tracefile
,"wb+");
453 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
460 sim_close (sd
, quitting
)
465 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
468 /* "quitting" is non-zero if we cannot hang on errors */
470 /* Ensure that any resources allocated through the callback
471 mechanism are released: */
472 sim_io_shutdown (sd
);
475 if (tracefh
!= NULL
&& tracefh
!= stderr
)
486 sim_write (sd
,addr
,buffer
,size
)
489 unsigned char *buffer
;
494 /* Return the number of bytes written, or zero if error. */
496 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
499 /* We use raw read and write routines, since we do not want to count
500 the GDB memory accesses in our statistics gathering. */
502 for (index
= 0; index
< size
; index
++)
504 address_word vaddr
= (address_word
)addr
+ index
;
507 if (!address_translation (sd
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
509 if (sim_core_write_buffer (sd
, NULL
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
517 sim_read (sd
,addr
,buffer
,size
)
520 unsigned char *buffer
;
525 /* Return the number of bytes read, or zero if error. */
527 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
530 for (index
= 0; (index
< size
); index
++)
532 address_word vaddr
= (address_word
)addr
+ index
;
535 if (!address_translation (sd
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
537 if (sim_core_read_buffer (sd
, NULL
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
545 sim_store_register (sd
,rn
,memory
)
548 unsigned char *memory
;
550 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
551 /* NOTE: gdb (the client) stores registers in target byte order
552 while the simulator uses host byte order */
554 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
557 /* Unfortunately this suffers from the same problem as the register
558 numbering one. We need to know what the width of each logical
559 register number is for the architecture being simulated. */
561 if (cpu
->register_widths
[rn
] == 0)
562 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
563 /* start-sanitize-r5900 */
564 else if (rn
== REGISTER_SA
)
565 SA
= T2H_8(*(uword64
*)memory
);
566 else if (rn
> LAST_EMBED_REGNUM
)
567 cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1] = T2H_8(*(uword64
*)memory
);
568 /* end-sanitize-r5900 */
569 else if (cpu
->register_widths
[rn
] == 32)
570 cpu
->registers
[rn
] = T2H_4 (*(unsigned int*)memory
);
572 cpu
->registers
[rn
] = T2H_8 (*(uword64
*)memory
);
578 sim_fetch_register (sd
,rn
,memory
)
581 unsigned char *memory
;
583 sim_cpu
*cpu
= STATE_CPU (sd
, 0);
584 /* NOTE: gdb (the client) stores registers in target byte order
585 while the simulator uses host byte order */
587 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
590 if (cpu
->register_widths
[rn
] == 0)
591 sim_io_eprintf(sd
,"Invalid register width for %d (register fetch ignored)\n",rn
);
592 /* start-sanitize-r5900 */
593 else if (rn
== REGISTER_SA
)
594 *((uword64
*)memory
) = H2T_8(SA
);
595 else if (rn
> LAST_EMBED_REGNUM
)
596 *((uword64
*)memory
) = H2T_8(cpu
->registers1
[rn
- LAST_EMBED_REGNUM
- 1]);
597 /* end-sanitize-r5900 */
598 else if (cpu
->register_widths
[rn
] == 32)
599 *((unsigned int *)memory
) = H2T_4 ((unsigned int)(cpu
->registers
[rn
] & 0xFFFFFFFF));
600 else /* 64bit register */
601 *((uword64
*)memory
) = H2T_8 (cpu
->registers
[rn
]);
608 sim_info (sd
,verbose
)
612 /* Accessed from the GDB "info files" command: */
613 if (STATE_VERBOSE_P (sd
) || verbose
)
616 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
617 (PROCESSOR_64BIT
? 64 : 32),
618 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
620 #if !defined(FASTSIM)
621 /* It would be a useful feature, if when performing multi-cycle
622 simulations (rather than single-stepping) we keep the start and
623 end times of the execution, so that we can give a performance
624 figure for the simulator. */
625 #endif /* !FASTSIM */
626 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
627 (long) sim_events_time (sd
));
629 /* print information pertaining to MIPS ISA and architecture being simulated */
630 /* things that may be interesting */
631 /* instructions executed - if available */
632 /* cycles executed - if available */
633 /* pipeline stalls - if available */
634 /* virtual time taken */
636 /* profiling frequency */
640 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
645 sim_create_inferior (sd
, abfd
, argv
,env
)
653 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
660 /* override PC value set by ColdReset () */
661 PC
= (unsigned64
) bfd_get_start_address (abfd
);
663 #if 0 /* def DEBUG */
666 /* We should really place the argv slot values into the argument
667 registers, and onto the stack as required. However, this
668 assumes that we have a stack defined, which is not
669 necessarily true at the moment. */
671 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
672 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
673 printf("DBG: arg \"%s\"\n",*cptr
);
681 sim_do_command (sd
,cmd
)
685 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
686 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
690 /*---------------------------------------------------------------------------*/
691 /*-- Private simulator support interface ------------------------------------*/
692 /*---------------------------------------------------------------------------*/
694 /* Read a null terminated string from memory, return in a buffer */
703 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
705 buf
= NZALLOC (char, nr
+ 1);
706 sim_read (sd
, addr
, buf
, nr
);
710 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
712 sim_monitor(sd
,cia
,reason
)
718 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
721 /* The IDT monitor actually allows two instructions per vector
722 slot. However, the simulator currently causes a trap on each
723 individual instruction. We cheat, and lose the bottom bit. */
726 /* The following callback functions are available, however the
727 monitor we are simulating does not make use of them: get_errno,
728 isatty, lseek, rename, system, time and unlink */
732 case 6: /* int open(char *path,int flags) */
734 char *path
= fetch_str (sd
, A0
);
735 V0
= sim_io_open (sd
, path
, (int)A1
);
740 case 7: /* int read(int file,char *ptr,int len) */
744 char *buf
= zalloc (nr
);
745 V0
= sim_io_read (sd
, fd
, buf
, nr
);
746 sim_write (sd
, A1
, buf
, nr
);
751 case 8: /* int write(int file,char *ptr,int len) */
755 char *buf
= zalloc (nr
);
756 sim_read (sd
, A1
, buf
, nr
);
757 V0
= sim_io_write (sd
, fd
, buf
, nr
);
762 case 10: /* int close(int file) */
764 V0
= sim_io_close (sd
, (int)A0
);
768 case 11: /* char inbyte(void) */
771 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
773 sim_io_error(sd
,"Invalid return from character read");
781 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
783 char tmp
= (char)(A0
& 0xFF);
784 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
788 case 17: /* void _exit() */
790 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
791 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
, sim_exited
,
792 (unsigned int)(A0
& 0xFFFFFFFF));
796 case 28 : /* PMON flush_cache */
799 case 55: /* void get_mem_info(unsigned int *ptr) */
800 /* in: A0 = pointer to three word memory location */
801 /* out: [A0 + 0] = size */
802 /* [A0 + 4] = instruction cache size */
803 /* [A0 + 8] = data cache size */
805 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
807 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
808 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
812 case 158 : /* PMON printf */
813 /* in: A0 = pointer to format string */
814 /* A1 = optional argument 1 */
815 /* A2 = optional argument 2 */
816 /* A3 = optional argument 3 */
818 /* The following is based on the PMON printf source */
822 signed_word
*ap
= &A1
; /* 1st argument */
823 /* This isn't the quickest way, since we call the host print
824 routine for every character almost. But it does avoid
825 having to allocate and manage a temporary string buffer. */
826 /* TODO: Include check that we only use three arguments (A1,
828 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
833 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
834 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
835 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
837 if (strchr ("dobxXulscefg%", s
))
852 else if (c
>= '1' && c
<= '9')
856 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
859 n
= (unsigned int)strtol(tmp
,NULL
,10);
872 sim_io_printf (sd
, "%%");
877 address_word p
= *ap
++;
879 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
880 sim_io_printf(sd
, "%c", ch
);
883 sim_io_printf(sd
,"(null)");
886 sim_io_printf (sd
, "%c", (int)*ap
++);
891 sim_read (sd
, s
++, &c
, 1);
895 sim_read (sd
, s
++, &c
, 1);
898 if (strchr ("dobxXu", c
))
900 word64 lv
= (word64
) *ap
++;
902 sim_io_printf(sd
,"<binary not supported>");
905 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
907 sim_io_printf(sd
, tmp
, lv
);
909 sim_io_printf(sd
, tmp
, (int)lv
);
912 else if (strchr ("eEfgG", c
))
914 double dbl
= *(double*)(ap
++);
915 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
916 sim_io_printf (sd
, tmp
, dbl
);
922 sim_io_printf(sd
, "%c", c
);
928 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
929 reason
, pr_addr(cia
));
935 /* Store a word into memory. */
938 store_word (sd
, cia
, vaddr
, val
)
947 if ((vaddr
& 3) != 0)
948 SignalExceptionAddressStore ();
951 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
954 const uword64 mask
= 7;
958 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
959 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
960 memval
= ((uword64
) val
) << (8 * byte
);
961 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
967 /* Load a word from memory. */
970 load_word (sd
, cia
, vaddr
)
975 if ((vaddr
& 3) != 0)
976 SignalExceptionAddressLoad ();
982 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
985 const uword64 mask
= 0x7;
986 const unsigned int reverse
= ReverseEndian
? 1 : 0;
987 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
991 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
992 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
994 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
995 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1002 /* Simulate the mips16 entry and exit pseudo-instructions. These
1003 would normally be handled by the reserved instruction exception
1004 code, but for ease of simulation we just handle them directly. */
1007 mips16_entry (sd
,insn
)
1011 int aregs
, sregs
, rreg
;
1014 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1017 aregs
= (insn
& 0x700) >> 8;
1018 sregs
= (insn
& 0x0c0) >> 6;
1019 rreg
= (insn
& 0x020) >> 5;
1021 /* This should be checked by the caller. */
1030 /* This is the entry pseudo-instruction. */
1032 for (i
= 0; i
< aregs
; i
++)
1033 store_word ((uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1041 store_word ((uword64
) tsp
, RA
);
1044 for (i
= 0; i
< sregs
; i
++)
1047 store_word ((uword64
) tsp
, GPR
[16 + i
]);
1055 /* This is the exit pseudo-instruction. */
1062 RA
= load_word ((uword64
) tsp
);
1065 for (i
= 0; i
< sregs
; i
++)
1068 GPR
[i
+ 16] = load_word ((uword64
) tsp
);
1076 FGR
[0] = WORD64LO (GPR
[4]);
1077 FPR_STATE
[0] = fmt_uninterpreted
;
1079 else if (aregs
== 6)
1081 FGR
[0] = WORD64LO (GPR
[5]);
1082 FGR
[1] = WORD64LO (GPR
[4]);
1083 FPR_STATE
[0] = fmt_uninterpreted
;
1084 FPR_STATE
[1] = fmt_uninterpreted
;
1086 #endif /* defined(HASFPU) */
1092 /*-- trace support ----------------------------------------------------------*/
1094 /* The TRACE support is provided (if required) in the memory accessing
1095 routines. Since we are also providing the architecture specific
1096 features, the architecture simulation code can also deal with
1097 notifying the TRACE world of cache flushes, etc. Similarly we do
1098 not need to provide profiling support in the simulator engine,
1099 since we can sample in the instruction fetch control loop. By
1100 defining the TRACE manifest, we add tracing as a run-time
1104 /* Tracing by default produces "din" format (as required by
1105 dineroIII). Each line of such a trace file *MUST* have a din label
1106 and address field. The rest of the line is ignored, so comments can
1107 be included if desired. The first field is the label which must be
1108 one of the following values:
1113 3 escape record (treated as unknown access type)
1114 4 escape record (causes cache flush)
1116 The address field is a 32bit (lower-case) hexadecimal address
1117 value. The address should *NOT* be preceded by "0x".
1119 The size of the memory transfer is not important when dealing with
1120 cache lines (as long as no more than a cache line can be
1121 transferred in a single operation :-), however more information
1122 could be given following the dineroIII requirement to allow more
1123 complete memory and cache simulators to provide better
1124 results. i.e. the University of Pisa has a cache simulator that can
1125 also take bus size and speed as (variable) inputs to calculate
1126 complete system performance (a much more useful ability when trying
1127 to construct an end product, rather than a processor). They
1128 currently have an ARM version of their tool called ChARM. */
1132 dotrace (SIM_DESC sd
,FILE *tracefh
,int type
,SIM_ADDR address
,int width
,char *comment
,...)
1134 if (STATE
& simTRACE
) {
1136 fprintf(tracefh
,"%d %s ; width %d ; ",
1140 va_start(ap
,comment
);
1141 vfprintf(tracefh
,comment
,ap
);
1143 fprintf(tracefh
,"\n");
1145 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1146 we may be generating 64bit ones, we should put the hi-32bits of the
1147 address into the comment field. */
1149 /* TODO: Provide a buffer for the trace lines. We can then avoid
1150 performing writes until the buffer is filled, or the file is
1153 /* NOTE: We could consider adding a comment field to the "din" file
1154 produced using type 3 markers (unknown access). This would then
1155 allow information about the program that the "din" is for, and
1156 the MIPs world that was being simulated, to be placed into the
1163 /*---------------------------------------------------------------------------*/
1164 /*-- simulator engine -------------------------------------------------------*/
1165 /*---------------------------------------------------------------------------*/
1171 /* RESET: Fixed PC address: */
1172 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1173 /* The reset vector address is in the unmapped, uncached memory space. */
1175 SR
&= ~(status_SR
| status_TS
| status_RP
);
1176 SR
|= (status_ERL
| status_BEV
);
1178 /* Cheat and allow access to the complete register set immediately */
1179 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1180 && WITH_TARGET_WORD_BITSIZE
== 64)
1181 SR
|= status_FR
; /* 64bit registers */
1183 /* Ensure that any instructions with pending register updates are
1187 for (loop
= 0; (loop
< PSLOTS
); loop
++)
1188 PENDING_SLOT_REG
[loop
] = (LAST_EMBED_REGNUM
+ 1);
1189 PENDING_IN
= PENDING_OUT
= PENDING_TOTAL
= 0;
1192 /* Initialise the FPU registers to the unknown state */
1193 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1196 for (rn
= 0; (rn
< 32); rn
++)
1197 FPR_STATE
[rn
] = fmt_uninterpreted
;
1203 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1205 /* Translate a virtual address to a physical address and cache
1206 coherence algorithm describing the mechanism used to resolve the
1207 memory reference. Given the virtual address vAddr, and whether the
1208 reference is to Instructions ot Data (IorD), find the corresponding
1209 physical address (pAddr) and the cache coherence algorithm (CCA)
1210 used to resolve the reference. If the virtual address is in one of
1211 the unmapped address spaces the physical address and the CCA are
1212 determined directly by the virtual address. If the virtual address
1213 is in one of the mapped address spaces then the TLB is used to
1214 determine the physical address and access type; if the required
1215 translation is not present in the TLB or the desired access is not
1216 permitted the function fails and an exception is taken.
1218 NOTE: Normally (RAW == 0), when address translation fails, this
1219 function raises an exception and does not return. */
1222 address_translation(sd
,cia
,vAddr
,IorD
,LorS
,pAddr
,CCA
,raw
)
1228 address_word
*pAddr
;
1232 int res
= -1; /* TRUE : Assume good return */
1235 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1238 /* Check that the address is valid for this memory model */
1240 /* For a simple (flat) memory model, we simply pass virtual
1241 addressess through (mostly) unchanged. */
1242 vAddr
&= 0xFFFFFFFF;
1244 *pAddr
= vAddr
; /* default for isTARGET */
1245 *CCA
= Uncached
; /* not used for isHOST */
1250 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1252 /* Prefetch data from memory. Prefetch is an advisory instruction for
1253 which an implementation specific action is taken. The action taken
1254 may increase performance, but must not change the meaning of the
1255 program, or alter architecturally-visible state. */
1258 prefetch(sd
,cia
,CCA
,pAddr
,vAddr
,DATA
,hint
)
1268 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1271 /* For our simple memory model we do nothing */
1275 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1277 /* Load a value from memory. Use the cache and main memory as
1278 specified in the Cache Coherence Algorithm (CCA) and the sort of
1279 access (IorD) to find the contents of AccessLength memory bytes
1280 starting at physical location pAddr. The data is returned in the
1281 fixed width naturally-aligned memory element (MemElem). The
1282 low-order two (or three) bits of the address and the AccessLength
1283 indicate which of the bytes within MemElem needs to be given to the
1284 processor. If the memory access type of the reference is uncached
1285 then only the referenced bytes are read from memory and valid
1286 within the memory element. If the access type is cached, and the
1287 data is not present in cache, an implementation specific size and
1288 alignment block of memory is read and loaded into the cache to
1289 satisfy a load reference. At a minimum, the block is the entire
1292 load_memory(sd
,cia
,memvalp
,memval1p
,CCA
,AccessLength
,pAddr
,vAddr
,IorD
)
1307 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1310 #if defined(WARN_MEM)
1311 if (CCA
!= uncached
)
1312 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1313 #endif /* WARN_MEM */
1315 /* If instruction fetch then we need to check that the two lo-order
1316 bits are zero, otherwise raise a InstructionFetch exception: */
1317 if ((IorD
== isINSTRUCTION
)
1318 && ((pAddr
& 0x3) != 0)
1319 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1320 SignalExceptionInstructionFetch ();
1322 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1324 /* In reality this should be a Bus Error */
1325 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1327 (LOADDRMASK
+ 1) << 2,
1332 dotrace(sd
,tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1335 /* Read the specified number of bytes from memory. Adjust for
1336 host/target byte ordering/ Align the least significant byte
1339 switch (AccessLength
)
1341 case AccessLength_QUADWORD
:
1343 unsigned_16 val
= sim_core_read_aligned_16 (STATE_CPU (sd
, 0), NULL_CIA
,
1344 sim_core_read_map
, pAddr
);
1345 value1
= VH8_16 (val
);
1346 value
= VL8_16 (val
);
1349 case AccessLength_DOUBLEWORD
:
1350 value
= sim_core_read_aligned_8 (STATE_CPU (sd
, 0), NULL_CIA
,
1351 sim_core_read_map
, pAddr
);
1353 case AccessLength_SEPTIBYTE
:
1354 value
= sim_core_read_misaligned_7 (STATE_CPU (sd
, 0), NULL_CIA
,
1355 sim_core_read_map
, pAddr
);
1356 case AccessLength_SEXTIBYTE
:
1357 value
= sim_core_read_misaligned_6 (STATE_CPU (sd
, 0), NULL_CIA
,
1358 sim_core_read_map
, pAddr
);
1359 case AccessLength_QUINTIBYTE
:
1360 value
= sim_core_read_misaligned_5 (STATE_CPU (sd
, 0), NULL_CIA
,
1361 sim_core_read_map
, pAddr
);
1362 case AccessLength_WORD
:
1363 value
= sim_core_read_aligned_4 (STATE_CPU (sd
, 0), NULL_CIA
,
1364 sim_core_read_map
, pAddr
);
1366 case AccessLength_TRIPLEBYTE
:
1367 value
= sim_core_read_misaligned_3 (STATE_CPU (sd
, 0), NULL_CIA
,
1368 sim_core_read_map
, pAddr
);
1369 case AccessLength_HALFWORD
:
1370 value
= sim_core_read_aligned_2 (STATE_CPU (sd
, 0), NULL_CIA
,
1371 sim_core_read_map
, pAddr
);
1373 case AccessLength_BYTE
:
1374 value
= sim_core_read_aligned_1 (STATE_CPU (sd
, 0), NULL_CIA
,
1375 sim_core_read_map
, pAddr
);
1382 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1383 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1386 /* See also store_memory. */
1387 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1390 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1391 shifted to the most significant byte position. */
1392 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1394 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1395 is already in the correct postition. */
1396 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1400 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1401 pr_uword64(value1
),pr_uword64(value
));
1405 if (memval1p
) *memval1p
= value1
;
1409 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1411 /* Store a value to memory. The specified data is stored into the
1412 physical location pAddr using the memory hierarchy (data caches and
1413 main memory) as specified by the Cache Coherence Algorithm
1414 (CCA). The MemElem contains the data for an aligned, fixed-width
1415 memory element (word for 32-bit processors, doubleword for 64-bit
1416 processors), though only the bytes that will actually be stored to
1417 memory need to be valid. The low-order two (or three) bits of pAddr
1418 and the AccessLength field indicates which of the bytes within the
1419 MemElem data should actually be stored; only these bytes in memory
1423 store_memory(sd
,cia
,CCA
,AccessLength
,MemElem
,MemElem1
,pAddr
,vAddr
)
1429 uword64 MemElem1
; /* High order 64 bits */
1434 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1437 #if defined(WARN_MEM)
1438 if (CCA
!= uncached
)
1439 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1440 #endif /* WARN_MEM */
1442 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1443 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1446 dotrace(sd
,tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1450 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1453 /* See also load_memory */
1454 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1457 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1458 shifted to the most significant byte position. */
1459 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1461 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1462 is already in the correct postition. */
1463 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1467 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1470 switch (AccessLength
)
1472 case AccessLength_QUADWORD
:
1474 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1475 sim_core_write_aligned_16 (STATE_CPU (sd
, 0), NULL_CIA
,
1476 sim_core_write_map
, pAddr
, val
);
1479 case AccessLength_DOUBLEWORD
:
1480 sim_core_write_aligned_8 (STATE_CPU (sd
, 0), NULL_CIA
,
1481 sim_core_write_map
, pAddr
, MemElem
);
1483 case AccessLength_SEPTIBYTE
:
1484 sim_core_write_misaligned_7 (STATE_CPU (sd
, 0), NULL_CIA
,
1485 sim_core_write_map
, pAddr
, MemElem
);
1487 case AccessLength_SEXTIBYTE
:
1488 sim_core_write_misaligned_6 (STATE_CPU (sd
, 0), NULL_CIA
,
1489 sim_core_write_map
, pAddr
, MemElem
);
1491 case AccessLength_QUINTIBYTE
:
1492 sim_core_write_misaligned_5 (STATE_CPU (sd
, 0), NULL_CIA
,
1493 sim_core_write_map
, pAddr
, MemElem
);
1495 case AccessLength_WORD
:
1496 sim_core_write_aligned_4 (STATE_CPU (sd
, 0), NULL_CIA
,
1497 sim_core_write_map
, pAddr
, MemElem
);
1499 case AccessLength_TRIPLEBYTE
:
1500 sim_core_write_misaligned_3 (STATE_CPU (sd
, 0), NULL_CIA
,
1501 sim_core_write_map
, pAddr
, MemElem
);
1503 case AccessLength_HALFWORD
:
1504 sim_core_write_aligned_2 (STATE_CPU (sd
, 0), NULL_CIA
,
1505 sim_core_write_map
, pAddr
, MemElem
);
1507 case AccessLength_BYTE
:
1508 sim_core_write_aligned_1 (STATE_CPU (sd
, 0), NULL_CIA
,
1509 sim_core_write_map
, pAddr
, MemElem
);
1520 ifetch32 (SIM_DESC sd
,
1524 /* Copy the action of the LW instruction */
1525 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1526 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1529 unsigned32 instruction
;
1532 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1533 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1534 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1535 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1536 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1541 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1542 /* Order loads and stores to synchronise shared memory. Perform the
1543 action necessary to make the effects of groups of synchronizable
1544 loads and stores indicated by stype occur in the same order for all
1547 sync_operation(sd
,cia
,stype
)
1553 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1558 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1559 /* Signal an exception condition. This will result in an exception
1560 that aborts the instruction. The instruction operation pseudocode
1561 will never see a return from this function call. */
1564 signal_exception (SIM_DESC sd
,
1571 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1574 /* Ensure that any active atomic read/modify/write operation will fail: */
1577 switch (exception
) {
1578 /* TODO: For testing purposes I have been ignoring TRAPs. In
1579 reality we should either simulate them, or allow the user to
1580 ignore them at run-time.
1583 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1589 unsigned int instruction
;
1592 va_start(ap
,exception
);
1593 instruction
= va_arg(ap
,unsigned int);
1596 code
= (instruction
>> 6) & 0xFFFFF;
1598 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1599 code
, pr_addr(cia
));
1603 case DebugBreakPoint
:
1604 if (! (Debug
& Debug_DM
))
1610 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1611 DEPC
= cia
- 4; /* reference the branch instruction */
1615 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1619 Debug
|= Debug_DM
; /* in debugging mode */
1620 Debug
|= Debug_DBp
; /* raising a DBp exception */
1622 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
);
1626 case ReservedInstruction
:
1629 unsigned int instruction
;
1630 va_start(ap
,exception
);
1631 instruction
= va_arg(ap
,unsigned int);
1633 /* Provide simple monitor support using ReservedInstruction
1634 exceptions. The following code simulates the fixed vector
1635 entry points into the IDT monitor by causing a simulator
1636 trap, performing the monitor operation, and returning to
1637 the address held in the $ra register (standard PCS return
1638 address). This means we only need to pre-load the vector
1639 space with suitable instruction values. For systems were
1640 actual trap instructions are used, we would not need to
1641 perform this magic. */
1642 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1644 sim_monitor(sd
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1645 /* NOTE: This assumes that a branch-and-link style
1646 instruction was used to enter the vector (which is the
1647 case with the current IDT monitor). */
1648 sim_engine_restart (sd
, STATE_CPU (sd
, 0), NULL
, RA
);
1650 /* Look for the mips16 entry and exit instructions, and
1651 simulate a handler for them. */
1652 else if ((cia
& 1) != 0
1653 && (instruction
& 0xf81f) == 0xe809
1654 && (instruction
& 0x0c0) != 0x0c0)
1656 mips16_entry (instruction
);
1657 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1659 /* else fall through to normal exception processing */
1660 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1665 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1667 /* Keep a copy of the current A0 in-case this is the program exit
1671 unsigned int instruction
;
1672 va_start(ap
,exception
);
1673 instruction
= va_arg(ap
,unsigned int);
1675 /* Check for our special terminating BREAK: */
1676 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1677 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, cia
,
1678 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1681 if (STATE
& simDELAYSLOT
)
1682 PC
= cia
- 4; /* reference the branch instruction */
1685 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, cia
,
1686 sim_stopped
, SIM_SIGTRAP
);
1689 /* Store exception code into current exception id variable (used
1692 /* TODO: If not simulating exceptions then stop the simulator
1693 execution. At the moment we always stop the simulation. */
1695 /* See figure 5-17 for an outline of the code below */
1696 if (! (SR
& status_EXL
))
1698 CAUSE
= (exception
<< 2);
1699 if (STATE
& simDELAYSLOT
)
1701 STATE
&= ~simDELAYSLOT
;
1703 EPC
= (cia
- 4); /* reference the branch instruction */
1707 /* FIXME: TLB et.al. */
1712 CAUSE
= (exception
<< 2);
1716 /* Store exception code into current exception id variable (used
1718 if (SR
& status_BEV
)
1719 PC
= (signed)0xBFC00200 + 0x180;
1721 PC
= (signed)0x80000000 + 0x180;
1723 switch ((CAUSE
>> 2) & 0x1F)
1726 /* Interrupts arrive during event processing, no need to
1730 case TLBModification
:
1735 case InstructionFetch
:
1737 /* The following is so that the simulator will continue from the
1738 exception address on breakpoint operations. */
1740 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1741 sim_stopped
, SIM_SIGBUS
);
1743 case ReservedInstruction
:
1744 case CoProcessorUnusable
:
1746 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1747 sim_stopped
, SIM_SIGILL
);
1749 case IntegerOverflow
:
1751 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1752 sim_stopped
, SIM_SIGFPE
);
1758 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1759 sim_stopped
, SIM_SIGTRAP
);
1763 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
1764 "FATAL: Should not encounter a breakpoint\n");
1766 default : /* Unknown internal exception */
1768 sim_engine_halt (sd
, STATE_CPU (sd
, 0), NULL
, NULL_CIA
,
1769 sim_stopped
, SIM_SIGABRT
);
1773 case SimulatorFault
:
1777 va_start(ap
,exception
);
1778 msg
= va_arg(ap
,char *);
1780 sim_engine_abort (sd
, STATE_CPU (sd
, 0), NULL_CIA
,
1781 "FATAL: Simulator error \"%s\"\n",msg
);
1788 #if defined(WARN_RESULT)
1789 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790 /* This function indicates that the result of the operation is
1791 undefined. However, this should not affect the instruction
1792 stream. All that is meant to happen is that the destination
1793 register is set to an undefined result. To keep the simulator
1794 simple, we just don't bother updating the destination register, so
1795 the overall result will be undefined. If desired we can stop the
1796 simulator by raising a pseudo-exception. */
1797 #define UndefinedResult() undefined_result (sd,cia)
1799 undefined_result(sd
,cia
)
1803 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
1804 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1809 #endif /* WARN_RESULT */
1812 cache_op(sd
,cia
,op
,pAddr
,vAddr
,instruction
)
1818 unsigned int instruction
;
1820 #if 1 /* stop warning message being displayed (we should really just remove the code) */
1821 static int icache_warning
= 1;
1822 static int dcache_warning
= 1;
1824 static int icache_warning
= 0;
1825 static int dcache_warning
= 0;
1828 /* If CP0 is not useable (User or Supervisor mode) and the CP0
1829 enable bit in the Status Register is clear - a coprocessor
1830 unusable exception is taken. */
1832 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
1836 case 0: /* instruction cache */
1838 case 0: /* Index Invalidate */
1839 case 1: /* Index Load Tag */
1840 case 2: /* Index Store Tag */
1841 case 4: /* Hit Invalidate */
1843 case 6: /* Hit Writeback */
1844 if (!icache_warning
)
1846 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
1852 SignalException(ReservedInstruction
,instruction
);
1857 case 1: /* data cache */
1859 case 0: /* Index Writeback Invalidate */
1860 case 1: /* Index Load Tag */
1861 case 2: /* Index Store Tag */
1862 case 3: /* Create Dirty */
1863 case 4: /* Hit Invalidate */
1864 case 5: /* Hit Writeback Invalidate */
1865 case 6: /* Hit Writeback */
1866 if (!dcache_warning
)
1868 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
1874 SignalException(ReservedInstruction
,instruction
);
1879 default: /* unrecognised cache ID */
1880 SignalException(ReservedInstruction
,instruction
);
1887 /*-- FPU support routines ---------------------------------------------------*/
1889 #if defined(HASFPU) /* Only needed when building FPU aware simulators */
1891 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1892 formats conform to ANSI/IEEE Std 754-1985. */
1893 /* SINGLE precision floating:
1894 * seeeeeeeefffffffffffffffffffffff
1896 * e = 8bits = exponent
1897 * f = 23bits = fraction
1899 /* SINGLE precision fixed:
1900 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1902 * i = 31bits = integer
1904 /* DOUBLE precision floating:
1905 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
1907 * e = 11bits = exponent
1908 * f = 52bits = fraction
1910 /* DOUBLE precision fixed:
1911 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1913 * i = 63bits = integer
1916 /* Extract sign-bit: */
1917 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
1918 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
1919 /* Extract biased exponent: */
1920 #define FP_S_be(v) (((v) >> 23) & 0xFF)
1921 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
1922 /* Extract unbiased Exponent: */
1923 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
1924 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
1925 /* Extract complete fraction field: */
1926 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
1927 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
1928 /* Extract numbered fraction bit: */
1929 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
1930 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
1932 /* Explicit QNaN values used when value required: */
1933 #define FPQNaN_SINGLE (0x7FBFFFFF)
1934 #define FPQNaN_WORD (0x7FFFFFFF)
1935 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
1936 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
1938 /* Explicit Infinity values used when required: */
1939 #define FPINF_SINGLE (0x7F800000)
1940 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
1942 #if 1 /* def DEBUG */
1943 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
1944 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
1948 value_fpr(sd
,cia
,fpr
,fmt
)
1957 /* Treat unused register values, as fixed-point 64bit values: */
1958 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
1960 /* If request to read data as "uninterpreted", then use the current
1962 fmt
= FPR_STATE
[fpr
];
1967 /* For values not yet accessed, set to the desired format: */
1968 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
1969 FPR_STATE
[fpr
] = fmt
;
1971 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
1974 if (fmt
!= FPR_STATE
[fpr
]) {
1975 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
1976 FPR_STATE
[fpr
] = fmt_unknown
;
1979 if (FPR_STATE
[fpr
] == fmt_unknown
) {
1980 /* Set QNaN value: */
1983 value
= FPQNaN_SINGLE
;
1987 value
= FPQNaN_DOUBLE
;
1991 value
= FPQNaN_WORD
;
1995 value
= FPQNaN_LONG
;
2002 } else if (SizeFGR() == 64) {
2006 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2009 case fmt_uninterpreted
:
2023 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2026 case fmt_uninterpreted
:
2029 if ((fpr
& 1) == 0) { /* even registers only */
2030 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2032 SignalException(ReservedInstruction
,0);
2043 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2046 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2053 store_fpr(sd
,cia
,fpr
,fmt
,value
)
2063 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2066 if (SizeFGR() == 64) {
2068 case fmt_uninterpreted_32
:
2069 fmt
= fmt_uninterpreted
;
2072 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2073 FPR_STATE
[fpr
] = fmt
;
2076 case fmt_uninterpreted_64
:
2077 fmt
= fmt_uninterpreted
;
2078 case fmt_uninterpreted
:
2082 FPR_STATE
[fpr
] = fmt
;
2086 FPR_STATE
[fpr
] = fmt_unknown
;
2092 case fmt_uninterpreted_32
:
2093 fmt
= fmt_uninterpreted
;
2096 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2097 FPR_STATE
[fpr
] = fmt
;
2100 case fmt_uninterpreted_64
:
2101 fmt
= fmt_uninterpreted
;
2102 case fmt_uninterpreted
:
2105 if ((fpr
& 1) == 0) { /* even register number only */
2106 FGR
[fpr
+1] = (value
>> 32);
2107 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2108 FPR_STATE
[fpr
+ 1] = fmt
;
2109 FPR_STATE
[fpr
] = fmt
;
2111 FPR_STATE
[fpr
] = fmt_unknown
;
2112 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2113 SignalException(ReservedInstruction
,0);
2118 FPR_STATE
[fpr
] = fmt_unknown
;
2123 #if defined(WARN_RESULT)
2126 #endif /* WARN_RESULT */
2129 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2132 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2149 sim_fpu_32to (&wop
, op
);
2150 boolean
= sim_fpu_is_nan (&wop
);
2157 sim_fpu_64to (&wop
, op
);
2158 boolean
= sim_fpu_is_nan (&wop
);
2162 fprintf (stderr
, "Bad switch\n");
2167 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2181 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2188 sim_fpu_32to (&wop
, op
);
2189 boolean
= sim_fpu_is_infinity (&wop
);
2195 sim_fpu_64to (&wop
, op
);
2196 boolean
= sim_fpu_is_infinity (&wop
);
2200 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2205 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2219 /* Argument checking already performed by the FPCOMPARE code */
2222 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2225 /* The format type should already have been checked: */
2231 sim_fpu_32to (&wop1
, op1
);
2232 sim_fpu_32to (&wop2
, op2
);
2233 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2240 sim_fpu_64to (&wop1
, op1
);
2241 sim_fpu_64to (&wop2
, op2
);
2242 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2246 fprintf (stderr
, "Bad switch\n");
2251 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2265 /* Argument checking already performed by the FPCOMPARE code */
2268 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2271 /* The format type should already have been checked: */
2277 sim_fpu_32to (&wop1
, op1
);
2278 sim_fpu_32to (&wop2
, op2
);
2279 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2286 sim_fpu_64to (&wop1
, op1
);
2287 sim_fpu_64to (&wop2
, op2
);
2288 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2292 fprintf (stderr
, "Bad switch\n");
2297 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2304 AbsoluteValue(op
,fmt
)
2311 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2314 /* The format type should already have been checked: */
2320 sim_fpu_32to (&wop
, op
);
2321 sim_fpu_abs (&wop
, &wop
);
2322 sim_fpu_to32 (&ans
, &wop
);
2330 sim_fpu_64to (&wop
, op
);
2331 sim_fpu_abs (&wop
, &wop
);
2332 sim_fpu_to64 (&ans
, &wop
);
2337 fprintf (stderr
, "Bad switch\n");
2352 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2355 /* The format type should already have been checked: */
2361 sim_fpu_32to (&wop
, op
);
2362 sim_fpu_neg (&wop
, &wop
);
2363 sim_fpu_to32 (&ans
, &wop
);
2371 sim_fpu_64to (&wop
, op
);
2372 sim_fpu_neg (&wop
, &wop
);
2373 sim_fpu_to64 (&ans
, &wop
);
2378 fprintf (stderr
, "Bad switch\n");
2394 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2397 /* The registers must specify FPRs valid for operands of type
2398 "fmt". If they are not valid, the result is undefined. */
2400 /* The format type should already have been checked: */
2408 sim_fpu_32to (&wop1
, op1
);
2409 sim_fpu_32to (&wop2
, op2
);
2410 sim_fpu_add (&ans
, &wop1
, &wop2
);
2411 sim_fpu_to32 (&res
, &ans
);
2421 sim_fpu_64to (&wop1
, op1
);
2422 sim_fpu_64to (&wop2
, op2
);
2423 sim_fpu_add (&ans
, &wop1
, &wop2
);
2424 sim_fpu_to64 (&res
, &ans
);
2429 fprintf (stderr
, "Bad switch\n");
2434 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2449 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2452 /* The registers must specify FPRs valid for operands of type
2453 "fmt". If they are not valid, the result is undefined. */
2455 /* The format type should already have been checked: */
2463 sim_fpu_32to (&wop1
, op1
);
2464 sim_fpu_32to (&wop2
, op2
);
2465 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2466 sim_fpu_to32 (&res
, &ans
);
2476 sim_fpu_64to (&wop1
, op1
);
2477 sim_fpu_64to (&wop2
, op2
);
2478 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2479 sim_fpu_to64 (&res
, &ans
);
2484 fprintf (stderr
, "Bad switch\n");
2489 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2496 Multiply(op1
,op2
,fmt
)
2504 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2507 /* The registers must specify FPRs valid for operands of type
2508 "fmt". If they are not valid, the result is undefined. */
2510 /* The format type should already have been checked: */
2518 sim_fpu_32to (&wop1
, op1
);
2519 sim_fpu_32to (&wop2
, op2
);
2520 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2521 sim_fpu_to32 (&res
, &ans
);
2531 sim_fpu_64to (&wop1
, op1
);
2532 sim_fpu_64to (&wop2
, op2
);
2533 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2534 sim_fpu_to64 (&res
, &ans
);
2539 fprintf (stderr
, "Bad switch\n");
2544 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2559 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2562 /* The registers must specify FPRs valid for operands of type
2563 "fmt". If they are not valid, the result is undefined. */
2565 /* The format type should already have been checked: */
2573 sim_fpu_32to (&wop1
, op1
);
2574 sim_fpu_32to (&wop2
, op2
);
2575 sim_fpu_div (&ans
, &wop1
, &wop2
);
2576 sim_fpu_to32 (&res
, &ans
);
2586 sim_fpu_64to (&wop1
, op1
);
2587 sim_fpu_64to (&wop2
, op2
);
2588 sim_fpu_div (&ans
, &wop1
, &wop2
);
2589 sim_fpu_to64 (&res
, &ans
);
2594 fprintf (stderr
, "Bad switch\n");
2599 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2613 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2616 /* The registers must specify FPRs valid for operands of type
2617 "fmt". If they are not valid, the result is undefined. */
2619 /* The format type should already have been checked: */
2626 sim_fpu_32to (&wop
, op
);
2627 sim_fpu_inv (&ans
, &wop
);
2628 sim_fpu_to32 (&res
, &ans
);
2637 sim_fpu_64to (&wop
, op
);
2638 sim_fpu_inv (&ans
, &wop
);
2639 sim_fpu_to64 (&res
, &ans
);
2644 fprintf (stderr
, "Bad switch\n");
2649 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2663 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2666 /* The registers must specify FPRs valid for operands of type
2667 "fmt". If they are not valid, the result is undefined. */
2669 /* The format type should already have been checked: */
2676 sim_fpu_32to (&wop
, op
);
2677 sim_fpu_sqrt (&ans
, &wop
);
2678 sim_fpu_to32 (&res
, &ans
);
2687 sim_fpu_64to (&wop
, op
);
2688 sim_fpu_sqrt (&ans
, &wop
);
2689 sim_fpu_to64 (&res
, &ans
);
2694 fprintf (stderr
, "Bad switch\n");
2699 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2706 convert(sd
,cia
,rm
,op
,from
,to
)
2715 sim_fpu_round round
;
2716 unsigned32 result32
;
2717 unsigned64 result64
;
2720 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
2726 /* Round result to nearest representable value. When two
2727 representable values are equally near, round to the value
2728 that has a least significant bit of zero (i.e. is even). */
2729 round
= sim_fpu_round_near
;
2732 /* Round result to the value closest to, and not greater in
2733 magnitude than, the result. */
2734 round
= sim_fpu_round_zero
;
2737 /* Round result to the value closest to, and not less than,
2739 round
= sim_fpu_round_up
;
2743 /* Round result to the value closest to, and not greater than,
2745 round
= sim_fpu_round_down
;
2749 fprintf (stderr
, "Bad switch\n");
2753 /* Convert the input to sim_fpu internal format */
2757 sim_fpu_64to (&wop
, op
);
2760 sim_fpu_32to (&wop
, op
);
2763 sim_fpu_i32to (&wop
, op
, round
);
2766 sim_fpu_i64to (&wop
, op
, round
);
2769 fprintf (stderr
, "Bad switch\n");
2773 /* Convert sim_fpu format into the output */
2774 /* The value WOP is converted to the destination format, rounding
2775 using mode RM. When the destination is a fixed-point format, then
2776 a source value of Infinity, NaN or one which would round to an
2777 integer outside the fixed point range then an IEEE Invalid
2778 Operation condition is raised. */
2782 sim_fpu_round_32 (&wop
, round
, 0);
2783 sim_fpu_to32 (&result32
, &wop
);
2784 result64
= result32
;
2787 sim_fpu_round_64 (&wop
, round
, 0);
2788 sim_fpu_to64 (&result64
, &wop
);
2791 sim_fpu_to32i (&result32
, &wop
, round
);
2792 result64
= result32
;
2795 sim_fpu_to64i (&result64
, &wop
, round
);
2799 fprintf (stderr
, "Bad switch\n");
2804 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
2812 /*-- co-processor support routines ------------------------------------------*/
2815 CoProcPresent(coproc_number
)
2816 unsigned int coproc_number
;
2818 /* Return TRUE if simulator provides a model for the given co-processor number */
2823 cop_lw(sd
,cia
,coproc_num
,coproc_reg
,memword
)
2826 int coproc_num
, coproc_reg
;
2827 unsigned int memword
;
2829 switch (coproc_num
) {
2833 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
2835 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
2836 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
2841 #if 0 /* this should be controlled by a configuration option */
2842 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
2851 cop_ld(sd
,cia
,coproc_num
,coproc_reg
,memword
)
2854 int coproc_num
, coproc_reg
;
2857 switch (coproc_num
) {
2860 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
2865 #if 0 /* this message should be controlled by a configuration option */
2866 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
2875 cop_sw(sd
,cia
,coproc_num
,coproc_reg
)
2878 int coproc_num
, coproc_reg
;
2880 unsigned int value
= 0;
2882 switch (coproc_num
) {
2888 hold
= FPR_STATE
[coproc_reg
];
2889 FPR_STATE
[coproc_reg
] = fmt_word
;
2890 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
2891 FPR_STATE
[coproc_reg
] = hold
;
2895 value
= (unsigned int)ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
2898 printf("DBG: COP_SW: reg in format %s (will be accessing as single)\n",DOFMT(FPR_STATE
[coproc_reg
]));
2900 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_single
);
2907 #if 0 /* should be controlled by configuration option */
2908 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2917 cop_sd(sd
,cia
,coproc_num
,coproc_reg
)
2920 int coproc_num
, coproc_reg
;
2923 switch (coproc_num
) {
2927 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
2930 value
= ValueFPR(coproc_reg
,FPR_STATE
[coproc_reg
]);
2933 printf("DBG: COP_SD: reg in format %s (will be accessing as double)\n",DOFMT(FPR_STATE
[coproc_reg
]));
2935 value
= ValueFPR(coproc_reg
,fmt_double
);
2942 #if 0 /* should be controlled by configuration option */
2943 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
2952 decode_coproc(sd
,cia
,instruction
)
2955 unsigned int instruction
;
2957 int coprocnum
= ((instruction
>> 26) & 3);
2961 case 0: /* standard CPU control and cache registers */
2963 int code
= ((instruction
>> 21) & 0x1F);
2964 /* R4000 Users Manual (second edition) lists the following CP0
2966 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
2967 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
2968 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
2969 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
2970 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
2971 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
2972 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
2973 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
2974 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
2975 ERET Exception return (VR4100 = 01000010000000000000000000011000)
2977 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
2979 int rt
= ((instruction
>> 16) & 0x1F);
2980 int rd
= ((instruction
>> 11) & 0x1F);
2982 switch (rd
) /* NOTEs: Standard CP0 registers */
2984 /* 0 = Index R4000 VR4100 VR4300 */
2985 /* 1 = Random R4000 VR4100 VR4300 */
2986 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
2987 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
2988 /* 4 = Context R4000 VR4100 VR4300 */
2989 /* 5 = PageMask R4000 VR4100 VR4300 */
2990 /* 6 = Wired R4000 VR4100 VR4300 */
2991 /* 8 = BadVAddr R4000 VR4100 VR4300 */
2992 /* 9 = Count R4000 VR4100 VR4300 */
2993 /* 10 = EntryHi R4000 VR4100 VR4300 */
2994 /* 11 = Compare R4000 VR4100 VR4300 */
2995 /* 12 = SR R4000 VR4100 VR4300 */
3002 /* 13 = Cause R4000 VR4100 VR4300 */
3009 /* 14 = EPC R4000 VR4100 VR4300 */
3010 /* 15 = PRId R4000 VR4100 VR4300 */
3011 #ifdef SUBTARGET_R3900
3020 /* 16 = Config R4000 VR4100 VR4300 */
3023 GPR
[rt
] = C0_CONFIG
;
3025 C0_CONFIG
= GPR
[rt
];
3028 #ifdef SUBTARGET_R3900
3037 /* 17 = LLAddr R4000 VR4100 VR4300 */
3039 /* 18 = WatchLo R4000 VR4100 VR4300 */
3040 /* 19 = WatchHi R4000 VR4100 VR4300 */
3041 /* 20 = XContext R4000 VR4100 VR4300 */
3042 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3043 /* 27 = CacheErr R4000 VR4100 */
3044 /* 28 = TagLo R4000 VR4100 VR4300 */
3045 /* 29 = TagHi R4000 VR4100 VR4300 */
3046 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3047 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3048 /* CPR[0,rd] = GPR[rt]; */
3051 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3053 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3056 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3059 if (SR
& status_ERL
)
3061 /* Oops, not yet available */
3062 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3072 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3076 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3084 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3085 /* TODO: When executing an ERET or RFE instruction we should
3086 clear LLBIT, to ensure that any out-standing atomic
3087 read/modify/write sequence fails. */
3091 case 2: /* undefined co-processor */
3092 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3095 case 1: /* should not occur (FPU co-processor) */
3096 case 3: /* should not occur (FPU co-processor) */
3097 SignalException(ReservedInstruction
,instruction
);
3104 /*-- instruction simulation -------------------------------------------------*/
3106 /* When the IGEN simulator is being built, the function below is be
3107 replaced by a generated version. However, WITH_IGEN == 2 indicates
3108 that the fubction below should be compiled but under a different
3109 name (to allow backward compatibility) */
3111 #if (WITH_IGEN != 1)
3113 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3115 old_engine_run (sd
, next_cpu_nr
, siggnal
)
3118 sim_engine_run (sd
, next_cpu_nr
, siggnal
)
3121 int next_cpu_nr
; /* ignore */
3122 int siggnal
; /* ignore */
3124 #if !defined(FASTSIM)
3125 unsigned int pipeline_count
= 1;
3129 if (STATE_MEMORY (sd
) == NULL
) {
3130 printf("DBG: simulate() entered with no memory\n");
3135 #if 0 /* Disabled to check that everything works OK */
3136 /* The VR4300 seems to sign-extend the PC on its first
3137 access. However, this may just be because it is currently
3138 configured in 32bit mode. However... */
3139 PC
= SIGNEXTEND(PC
,32);
3142 /* main controlling loop */
3144 /* vaddr is slowly being replaced with cia - current instruction
3146 address_word cia
= (uword64
)PC
;
3147 address_word vaddr
= cia
;
3150 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3154 printf("DBG: state = 0x%08X :",state
);
3155 if (state
& simHALTEX
) printf(" simHALTEX");
3156 if (state
& simHALTIN
) printf(" simHALTIN");
3161 DSSTATE
= (STATE
& simDELAYSLOT
);
3164 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3167 /* Fetch the next instruction from the simulator memory: */
3168 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3169 if ((vaddr
& 1) == 0) {
3170 /* Copy the action of the LW instruction */
3171 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3172 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3175 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3176 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3177 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3178 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3180 /* Copy the action of the LH instruction */
3181 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3182 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3185 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3186 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3187 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3188 paddr
& ~ (uword64
) 1,
3189 vaddr
, isINSTRUCTION
, isREAL
);
3190 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3191 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3194 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3199 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3202 /* This is required by exception processing, to ensure that we can
3203 cope with exceptions in the delay slots of branches that may
3204 already have changed the PC. */
3205 if ((vaddr
& 1) == 0)
3206 PC
+= 4; /* increment ready for the next fetch */
3209 /* NOTE: If we perform a delay slot change to the PC, this
3210 increment is not requuired. However, it would make the
3211 simulator more complicated to try and avoid this small hit. */
3213 /* Currently this code provides a simple model. For more
3214 complicated models we could perform exception status checks at
3215 this point, and set the simSTOP state as required. This could
3216 also include processing any hardware interrupts raised by any
3217 I/O model attached to the simulator context.
3219 Support for "asynchronous" I/O events within the simulated world
3220 could be providing by managing a counter, and calling a I/O
3221 specific handler when a particular threshold is reached. On most
3222 architectures a decrement and check for zero operation is
3223 usually quicker than an increment and compare. However, the
3224 process of managing a known value decrement to zero, is higher
3225 than the cost of using an explicit value UINT_MAX into the
3226 future. Which system is used will depend on how complicated the
3227 I/O model is, and how much it is likely to affect the simulator
3230 If events need to be scheduled further in the future than
3231 UINT_MAX event ticks, then the I/O model should just provide its
3232 own counter, triggered from the event system. */
3234 /* MIPS pipeline ticks. To allow for future support where the
3235 pipeline hit of individual instructions is known, this control
3236 loop manages a "pipeline_count" variable. It is initialised to
3237 1 (one), and will only be changed by the simulator engine when
3238 executing an instruction. If the engine does not have access to
3239 pipeline cycle count information then all instructions will be
3240 treated as using a single cycle. NOTE: A standard system is not
3241 provided by the default simulator because different MIPS
3242 architectures have different cycle counts for the same
3245 [NOTE: pipeline_count has been replaced the event queue] */
3247 /* shuffle the floating point status pipeline state */
3248 ENGINE_ISSUE_PREFIX_HOOK();
3250 /* NOTE: For multi-context simulation environments the "instruction"
3251 variable should be local to this routine. */
3253 /* Shorthand accesses for engine. Note: If we wanted to use global
3254 variables (and a single-threaded simulator engine), then we can
3255 create the actual variables with these names. */
3257 if (!(STATE
& simSKIPNEXT
)) {
3258 /* Include the simulator engine */
3259 #include "oengine.c"
3260 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3261 #error "Mismatch between run-time simulator code and simulation engine"
3263 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3264 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3266 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3267 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3270 #if defined(WARN_LOHI)
3271 /* Decrement the HI/LO validity ticks */
3276 /* start-sanitize-r5900 */
3281 /* end-sanitize-r5900 */
3282 #endif /* WARN_LOHI */
3284 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3285 should check for it being changed. It is better doing it here,
3286 than within the simulator, since it will help keep the simulator
3289 #if defined(WARN_ZERO)
3290 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3291 #endif /* WARN_ZERO */
3292 ZERO
= 0; /* reset back to zero before next instruction */
3294 } else /* simSKIPNEXT check */
3295 STATE
&= ~simSKIPNEXT
;
3297 /* If the delay slot was active before the instruction is
3298 executed, then update the PC to its new value: */
3301 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3307 if (MIPSISA
< 4) { /* The following is only required on pre MIPS IV processors: */
3308 /* Deal with pending register updates: */
3310 printf("DBG: EMPTY BEFORE pending_in = %d, pending_out = %d, pending_total = %d\n",pending_in
,pending_out
,pending_total
);
3312 if (PENDING_OUT
!= PENDING_IN
) {
3314 int index
= PENDING_OUT
;
3315 int total
= PENDING_TOTAL
;
3316 if (PENDING_TOTAL
== 0) {
3317 fprintf(stderr
,"FATAL: Mis-match on pending update pointers\n");
3320 for (loop
= 0; (loop
< total
); loop
++) {
3322 printf("DBG: BEFORE index = %d, loop = %d\n",index
,loop
);
3324 if (PENDING_SLOT_REG
[index
] != (LAST_EMBED_REGNUM
+ 1)) {
3326 printf("pending_slot_count[%d] = %d\n",index
,PENDING_SLOT_COUNT
[index
]);
3328 if (--(PENDING_SLOT_COUNT
[index
]) == 0) {
3330 printf("pending_slot_reg[%d] = %d\n",index
,PENDING_SLOT_REG
[index
]);
3331 printf("pending_slot_value[%d] = 0x%s\n",index
,pr_addr(PENDING_SLOT_VALUE
[index
]));
3333 if (PENDING_SLOT_REG
[index
] == COCIDX
) {
3335 SETFCC(0,((FCR31
& (1 << 23)) ? 1 : 0));
3340 REGISTERS
[PENDING_SLOT_REG
[index
]] = PENDING_SLOT_VALUE
[index
];
3342 /* The only time we have PENDING updates to FPU
3343 registers, is when performing binary transfers. This
3344 means we should update the register type field. */
3345 if ((PENDING_SLOT_REG
[index
] >= FGRIDX
) && (PENDING_SLOT_REG
[index
] < (FGRIDX
+ 32)))
3346 FPR_STATE
[PENDING_SLOT_REG
[index
] - FGRIDX
] = fmt_uninterpreted
;
3350 printf("registers[%d] = 0x%s\n",PENDING_SLOT_REG
[index
],pr_addr(REGISTERS
[PENDING_SLOT_REG
[index
]]));
3352 PENDING_SLOT_REG
[index
] = (LAST_EMBED_REGNUM
+ 1);
3354 if (PENDING_OUT
== PSLOTS
)
3360 printf("DBG: AFTER index = %d, loop = %d\n",index
,loop
);
3363 if (index
== PSLOTS
)
3368 printf("DBG: EMPTY AFTER pending_in = %d, pending_out = %d, pending_total = %d\n",PENDING_IN
,PENDING_OUT
,PENDING_TOTAL
);
3372 #if !defined(FASTSIM)
3373 if (sim_events_tickn (sd
, pipeline_count
))
3375 /* cpu->cia = cia; */
3376 sim_events_process (sd
);
3379 if (sim_events_tick (sd
))
3381 /* cpu->cia = cia; */
3382 sim_events_process (sd
);
3384 #endif /* FASTSIM */
3390 /* This code copied from gdb's utils.c. Would like to share this code,
3391 but don't know of a common place where both could get to it. */
3393 /* Temporary storage using circular buffer */
3399 static char buf
[NUMCELLS
][CELLSIZE
];
3401 if (++cell
>=NUMCELLS
) cell
=0;
3405 /* Print routines to handle variable size regs, etc */
3407 /* Eliminate warning from compiler on 32-bit systems */
3408 static int thirty_two
= 32;
3414 char *paddr_str
=get_cell();
3415 switch (sizeof(addr
))
3418 sprintf(paddr_str
,"%08lx%08lx",
3419 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3422 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3425 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3428 sprintf(paddr_str
,"%x",addr
);
3437 char *paddr_str
=get_cell();
3438 sprintf(paddr_str
,"%08lx%08lx",
3439 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3444 /*---------------------------------------------------------------------------*/
3445 /*> EOF interp.c <*/