2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
41 /* start-sanitize-sky */
45 #include "sky-libvpe.h"
47 /* end-sanitize-sky */
69 #include "libiberty.h"
71 #include "callback.h" /* GDB simulator callback interface */
72 #include "remote-sim.h" /* GDB simulator interface */
76 /* start-sanitize-sky */
80 /* end-sanitize-sky */
86 char* pr_addr
PARAMS ((SIM_ADDR addr
));
87 char* pr_uword64
PARAMS ((uword64 addr
));
90 /* Get the simulator engine description, without including the code: */
92 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
99 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
104 /* The following reserved instruction value is used when a simulator
105 trap is required. NOTE: Care must be taken, since this value may be
106 used in later revisions of the MIPS ISA. */
107 #define RSVD_INSTRUCTION (0x00000005)
108 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
110 #define RSVD_INSTRUCTION_ARG_SHIFT 6
111 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
114 /* Bits in the Debug register */
115 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
116 #define Debug_DM 0x40000000 /* Debug Mode */
117 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
123 /*---------------------------------------------------------------------------*/
124 /*-- GDB simulator interface ------------------------------------------------*/
125 /*---------------------------------------------------------------------------*/
127 static void ColdReset
PARAMS((SIM_DESC sd
));
129 /*---------------------------------------------------------------------------*/
133 #define DELAYSLOT() {\
134 if (STATE & simDELAYSLOT)\
135 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
136 STATE |= simDELAYSLOT;\
139 #define JALDELAYSLOT() {\
141 STATE |= simJALDELAYSLOT;\
145 STATE &= ~simDELAYSLOT;\
146 STATE |= simSKIPNEXT;\
149 #define CANCELDELAYSLOT() {\
151 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
154 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
155 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
157 #define K0BASE (0x80000000)
158 #define K0SIZE (0x20000000)
159 #define K1BASE (0xA0000000)
160 #define K1SIZE (0x20000000)
161 #define MONITOR_BASE (0xBFC00000)
162 #define MONITOR_SIZE (1 << 11)
163 #define MEM_SIZE (2 << 20)
165 /* start-sanitize-sky */
168 #define MEM_SIZE (16 << 20) /* 16 MB */
170 /* end-sanitize-sky */
173 static char *tracefile
= "trace.din"; /* default filename for trace log */
174 FILE *tracefh
= NULL
;
175 static void open_trace
PARAMS((SIM_DESC sd
));
178 static DECLARE_OPTION_HANDLER (mips_option_handler
);
180 #define OPTION_DINERO_TRACE 200
181 #define OPTION_DINERO_FILE 201
184 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
194 case OPTION_DINERO_TRACE
: /* ??? */
196 /* Eventually the simTRACE flag could be treated as a toggle, to
197 allow external control of the program points being traced
198 (i.e. only from main onwards, excluding the run-time setup,
200 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
202 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
205 else if (strcmp (arg
, "yes") == 0)
207 else if (strcmp (arg
, "no") == 0)
209 else if (strcmp (arg
, "on") == 0)
211 else if (strcmp (arg
, "off") == 0)
215 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
222 Simulator constructed without dinero tracing support (for performance).\n\
223 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
227 case OPTION_DINERO_FILE
:
229 if (optarg
!= NULL
) {
231 tmp
= (char *)malloc(strlen(optarg
) + 1);
234 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
240 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
251 static const OPTION mips_options
[] =
253 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
254 '\0', "on|off", "Enable dinero tracing",
255 mips_option_handler
},
256 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
257 '\0', "FILE", "Write dinero trace to FILE",
258 mips_option_handler
},
259 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
263 int interrupt_pending
;
266 interrupt_event (SIM_DESC sd
, void *data
)
268 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
271 interrupt_pending
= 0;
272 SignalExceptionInterrupt ();
274 else if (!interrupt_pending
)
275 sim_events_schedule (sd
, 1, interrupt_event
, data
);
279 /*---------------------------------------------------------------------------*/
280 /*-- Device registration hook -----------------------------------------------*/
281 /*---------------------------------------------------------------------------*/
282 static void device_init(SIM_DESC sd
) {
284 extern void register_devices(SIM_DESC
);
285 register_devices(sd
);
289 /* start-sanitize-sky */
292 short i
[NUM_VU_INTEGER_REGS
];
293 int f
[NUM_VU_REGS
- NUM_VU_INTEGER_REGS
];
296 /* end-sanitize-sky */
298 /*---------------------------------------------------------------------------*/
299 /*-- GDB simulator interface ------------------------------------------------*/
300 /*---------------------------------------------------------------------------*/
303 sim_open (kind
, cb
, abfd
, argv
)
309 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
310 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
312 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
314 /* FIXME: watchpoints code shouldn't need this */
315 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
316 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
317 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
321 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
323 sim_add_option_table (sd
, NULL
, mips_options
);
325 /* Allocate core managed memory */
328 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
329 /* For compatibility with the old code - under this (at level one)
330 are the kernel spaces K0 & K1. Both of these map to a single
331 smaller sub region */
332 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
333 /* start-sanitize-sky */
335 /* end-sanitize-sky */
336 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
338 MEM_SIZE
, /* actual size */
340 /* start-sanitize-sky */
342 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
344 MEM_SIZE
, /* actual size */
346 0); /* add alias at 0x0000 */
348 /* end-sanitize-sky */
352 /* getopt will print the error message so we just have to exit if this fails.
353 FIXME: Hmmm... in the case of gdb we need getopt to call
355 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
357 /* Uninstall the modules to avoid memory leaks,
358 file descriptor leaks, etc. */
359 sim_module_uninstall (sd
);
363 /* check for/establish the a reference program image */
364 if (sim_analyze_program (sd
,
365 (STATE_PROG_ARGV (sd
) != NULL
366 ? *STATE_PROG_ARGV (sd
)
370 sim_module_uninstall (sd
);
374 /* Configure/verify the target byte order and other runtime
375 configuration options */
376 if (sim_config (sd
) != SIM_RC_OK
)
378 sim_module_uninstall (sd
);
382 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
384 /* Uninstall the modules to avoid memory leaks,
385 file descriptor leaks, etc. */
386 sim_module_uninstall (sd
);
390 /* verify assumptions the simulator made about the host type system.
391 This macro does not return if there is a problem */
392 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
393 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
395 /* This is NASTY, in that we are assuming the size of specific
399 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
402 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
403 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
404 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
405 else if ((rn
>= 33) && (rn
<= 37))
406 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
407 else if ((rn
== SRIDX
)
410 || ((rn
>= 72) && (rn
<= 89)))
411 cpu
->register_widths
[rn
] = 32;
413 cpu
->register_widths
[rn
] = 0;
415 /* start-sanitize-r5900 */
417 /* set the 5900 "upper" registers to 64 bits */
418 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
419 cpu
->register_widths
[rn
] = 64;
420 /* end-sanitize-r5900 */
422 /* start-sanitize-sky */
424 /* Now the VU registers */
425 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
426 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
427 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
429 /* Hack for now - to test gdb interface */
430 vu_regs
[0].i
[rn
] = rn
+ 0x100;
431 vu_regs
[1].i
[rn
] = rn
+ 0x200;
434 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
436 int first_vec_reg
= NUM_VU_INTEGER_REGS
+ 8;
438 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
439 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
441 /* Hack for now - to test gdb interface */
442 if( rn
< first_vec_reg
) {
443 f
= rn
- NUM_VU_INTEGER_REGS
+ 100.0;
444 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
445 f
= rn
- NUM_VU_INTEGER_REGS
+ 200.0;
446 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
449 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 1000.0;
450 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
451 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 2000.0;
452 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
456 /* end-sanitize-sky */
460 if (STATE
& simTRACE
)
464 /* Write the monitor trap address handlers into the monitor (eeprom)
465 address space. This can only be done once the target endianness
466 has been determined. */
469 /* Entry into the IDT monitor is via fixed address vectors, and
470 not using machine instructions. To avoid clashing with use of
471 the MIPS TRAP system, we place our own (simulator specific)
472 "undefined" instructions into the relevant vector slots. */
473 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
475 address_word vaddr
= (MONITOR_BASE
+ loop
);
476 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
478 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
480 /* The PMON monitor uses the same address space, but rather than
481 branching into it the address of a routine is loaded. We can
482 cheat for the moment, and direct the PMON routine to IDT style
483 instructions within the monitor space. This relies on the IDT
484 monitor not using the locations from 0xBFC00500 onwards as its
486 for (loop
= 0; (loop
< 24); loop
++)
488 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
489 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
505 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
507 case 8: /* cliexit */
510 case 11: /* flush_cache */
514 /* FIXME - should monitor_base be SIM_ADDR?? */
515 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
517 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
519 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
521 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
533 tracefh
= fopen(tracefile
,"wb+");
536 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
543 sim_close (sd
, quitting
)
548 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
551 /* "quitting" is non-zero if we cannot hang on errors */
553 /* Ensure that any resources allocated through the callback
554 mechanism are released: */
555 sim_io_shutdown (sd
);
558 if (tracefh
!= NULL
&& tracefh
!= stderr
)
563 /* FIXME - free SD */
570 sim_write (sd
,addr
,buffer
,size
)
573 unsigned char *buffer
;
577 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
579 /* Return the number of bytes written, or zero if error. */
581 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
584 /* We use raw read and write routines, since we do not want to count
585 the GDB memory accesses in our statistics gathering. */
587 for (index
= 0; index
< size
; index
++)
589 address_word vaddr
= (address_word
)addr
+ index
;
592 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
594 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
602 sim_read (sd
,addr
,buffer
,size
)
605 unsigned char *buffer
;
609 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
611 /* Return the number of bytes read, or zero if error. */
613 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
616 for (index
= 0; (index
< size
); index
++)
618 address_word vaddr
= (address_word
)addr
+ index
;
621 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
623 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
631 sim_store_register (sd
,rn
,memory
,length
)
634 unsigned char *memory
;
637 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
638 /* NOTE: gdb (the client) stores registers in target byte order
639 while the simulator uses host byte order */
641 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
644 /* Unfortunately this suffers from the same problem as the register
645 numbering one. We need to know what the width of each logical
646 register number is for the architecture being simulated. */
648 if (cpu
->register_widths
[rn
] == 0)
650 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
654 /* start-sanitize-r5900 */
655 if (rn
>= 90 && rn
< 90 + 32)
657 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
663 SA
= T2H_8(*(unsigned64
*)memory
);
665 case 122: /* FIXME */
666 LO1
= T2H_8(*(unsigned64
*)memory
);
668 case 123: /* FIXME */
669 HI1
= T2H_8(*(unsigned64
*)memory
);
672 /* end-sanitize-r5900 */
674 /* start-sanitize-sky */
676 if (rn
>= NUM_R5900_REGS
)
678 int size
= 4; /* Default register size */
680 rn
= rn
- NUM_R5900_REGS
;
682 if (rn
< NUM_VU_INTEGER_REGS
)
683 size
= write_vu_int_reg (& vu0_device
.state
->regs
, rn
, memory
);
684 else if( rn
< NUM_VU_REGS
)
685 vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
]
686 = T2H_4( *(unsigned int *) memory
);
688 rn
= rn
- NUM_VU_REGS
;
690 if( rn
< NUM_VU_INTEGER_REGS
)
691 size
= write_vu_int_reg (& vu1_device
.state
->regs
, rn
, memory
);
692 else if( rn
< NUM_VU_REGS
)
693 vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
]
694 = T2H_4( *(unsigned int *) memory
);
696 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
702 /* end-sanitize-sky */
704 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
706 if (cpu
->register_widths
[rn
] == 32)
708 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
713 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
718 if (cpu
->register_widths
[rn
] == 32)
720 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
725 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
731 sim_fetch_register (sd
,rn
,memory
,length
)
734 unsigned char *memory
;
737 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
738 /* NOTE: gdb (the client) stores registers in target byte order
739 while the simulator uses host byte order */
741 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
744 if (cpu
->register_widths
[rn
] == 0)
746 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
750 /* start-sanitize-r5900 */
751 if (rn
>= 90 && rn
< 90 + 32)
753 *(unsigned64
*)memory
= GPR1
[rn
- 90];
759 *((unsigned64
*)memory
) = H2T_8(SA
);
761 case 122: /* FIXME */
762 *((unsigned64
*)memory
) = H2T_8(LO1
);
764 case 123: /* FIXME */
765 *((unsigned64
*)memory
) = H2T_8(HI1
);
768 /* end-sanitize-r5900 */
770 /* start-sanitize-sky */
772 if (rn
>= NUM_R5900_REGS
)
774 int size
= 4; /* default register width */
776 rn
= rn
- NUM_R5900_REGS
;
778 if (rn
< NUM_VU_INTEGER_REGS
)
779 size
= read_vu_int_reg (& vu0_device
.state
->regs
, rn
, memory
);
780 else if (rn
< NUM_VU_REGS
)
781 *((unsigned int *) memory
)
782 = H2T_4( vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
] );
785 rn
= rn
- NUM_VU_REGS
;
787 if (rn
< NUM_VU_INTEGER_REGS
)
788 size
= read_vu_int_reg (& vu1_device
.state
->regs
, rn
, memory
);
789 else if (rn
< NUM_VU_REGS
)
790 (*(unsigned int *) memory
)
791 = H2T_4( vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
] );
793 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
799 /* end-sanitize-sky */
801 /* Any floating point register */
802 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
804 if (cpu
->register_widths
[rn
] == 32)
806 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
811 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
816 if (cpu
->register_widths
[rn
] == 32)
818 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
823 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
830 sim_create_inferior (sd
, abfd
, argv
,env
)
838 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
846 /* override PC value set by ColdReset () */
848 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
850 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
851 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
855 #if 0 /* def DEBUG */
858 /* We should really place the argv slot values into the argument
859 registers, and onto the stack as required. However, this
860 assumes that we have a stack defined, which is not
861 necessarily true at the moment. */
863 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
864 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
865 printf("DBG: arg \"%s\"\n",*cptr
);
873 sim_do_command (sd
,cmd
)
877 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
878 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
882 /*---------------------------------------------------------------------------*/
883 /*-- Private simulator support interface ------------------------------------*/
884 /*---------------------------------------------------------------------------*/
886 /* Read a null terminated string from memory, return in a buffer */
895 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
897 buf
= NZALLOC (char, nr
+ 1);
898 sim_read (sd
, addr
, buf
, nr
);
902 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
904 sim_monitor (SIM_DESC sd
,
910 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
913 /* The IDT monitor actually allows two instructions per vector
914 slot. However, the simulator currently causes a trap on each
915 individual instruction. We cheat, and lose the bottom bit. */
918 /* The following callback functions are available, however the
919 monitor we are simulating does not make use of them: get_errno,
920 isatty, lseek, rename, system, time and unlink */
924 case 6: /* int open(char *path,int flags) */
926 char *path
= fetch_str (sd
, A0
);
927 V0
= sim_io_open (sd
, path
, (int)A1
);
932 case 7: /* int read(int file,char *ptr,int len) */
936 char *buf
= zalloc (nr
);
937 V0
= sim_io_read (sd
, fd
, buf
, nr
);
938 sim_write (sd
, A1
, buf
, nr
);
943 case 8: /* int write(int file,char *ptr,int len) */
947 char *buf
= zalloc (nr
);
948 sim_read (sd
, A1
, buf
, nr
);
949 V0
= sim_io_write (sd
, fd
, buf
, nr
);
954 case 10: /* int close(int file) */
956 V0
= sim_io_close (sd
, (int)A0
);
960 case 2: /* Densan monitor: char inbyte(int waitflag) */
962 if (A0
== 0) /* waitflag == NOWAIT */
963 V0
= (unsigned_word
)-1;
965 /* Drop through to case 11 */
967 case 11: /* char inbyte(void) */
970 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
972 sim_io_error(sd
,"Invalid return from character read");
973 V0
= (unsigned_word
)-1;
976 V0
= (unsigned_word
)tmp
;
980 case 3: /* Densan monitor: void co(char chr) */
981 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
983 char tmp
= (char)(A0
& 0xFF);
984 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
988 case 17: /* void _exit() */
990 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
991 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
992 (unsigned int)(A0
& 0xFFFFFFFF));
996 case 28 : /* PMON flush_cache */
999 case 55: /* void get_mem_info(unsigned int *ptr) */
1000 /* in: A0 = pointer to three word memory location */
1001 /* out: [A0 + 0] = size */
1002 /* [A0 + 4] = instruction cache size */
1003 /* [A0 + 8] = data cache size */
1005 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1007 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
1008 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1012 case 158 : /* PMON printf */
1013 /* in: A0 = pointer to format string */
1014 /* A1 = optional argument 1 */
1015 /* A2 = optional argument 2 */
1016 /* A3 = optional argument 3 */
1018 /* The following is based on the PMON printf source */
1020 address_word s
= A0
;
1022 signed_word
*ap
= &A1
; /* 1st argument */
1023 /* This isn't the quickest way, since we call the host print
1024 routine for every character almost. But it does avoid
1025 having to allocate and manage a temporary string buffer. */
1026 /* TODO: Include check that we only use three arguments (A1,
1028 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1033 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1034 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1035 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1037 if (strchr ("dobxXulscefg%", s
))
1052 else if (c
>= '1' && c
<= '9')
1056 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1059 n
= (unsigned int)strtol(tmp
,NULL
,10);
1072 sim_io_printf (sd
, "%%");
1077 address_word p
= *ap
++;
1079 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1080 sim_io_printf(sd
, "%c", ch
);
1083 sim_io_printf(sd
,"(null)");
1086 sim_io_printf (sd
, "%c", (int)*ap
++);
1091 sim_read (sd
, s
++, &c
, 1);
1095 sim_read (sd
, s
++, &c
, 1);
1098 if (strchr ("dobxXu", c
))
1100 word64 lv
= (word64
) *ap
++;
1102 sim_io_printf(sd
,"<binary not supported>");
1105 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1107 sim_io_printf(sd
, tmp
, lv
);
1109 sim_io_printf(sd
, tmp
, (int)lv
);
1112 else if (strchr ("eEfgG", c
))
1114 double dbl
= *(double*)(ap
++);
1115 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1116 sim_io_printf (sd
, tmp
, dbl
);
1122 sim_io_printf(sd
, "%c", c
);
1128 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1129 reason
, pr_addr(cia
));
1135 /* Store a word into memory. */
1138 store_word (SIM_DESC sd
,
1147 if ((vaddr
& 3) != 0)
1148 SignalExceptionAddressStore ();
1151 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1154 const uword64 mask
= 7;
1158 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1159 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1160 memval
= ((uword64
) val
) << (8 * byte
);
1161 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1167 /* Load a word from memory. */
1170 load_word (SIM_DESC sd
,
1175 if ((vaddr
& 3) != 0)
1176 SignalExceptionAddressLoad ();
1182 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1185 const uword64 mask
= 0x7;
1186 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1187 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1191 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1192 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1194 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1195 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1202 /* Simulate the mips16 entry and exit pseudo-instructions. These
1203 would normally be handled by the reserved instruction exception
1204 code, but for ease of simulation we just handle them directly. */
1207 mips16_entry (SIM_DESC sd
,
1212 int aregs
, sregs
, rreg
;
1215 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1218 aregs
= (insn
& 0x700) >> 8;
1219 sregs
= (insn
& 0x0c0) >> 6;
1220 rreg
= (insn
& 0x020) >> 5;
1222 /* This should be checked by the caller. */
1231 /* This is the entry pseudo-instruction. */
1233 for (i
= 0; i
< aregs
; i
++)
1234 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1242 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1245 for (i
= 0; i
< sregs
; i
++)
1248 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1256 /* This is the exit pseudo-instruction. */
1263 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1266 for (i
= 0; i
< sregs
; i
++)
1269 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1274 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1278 FGR
[0] = WORD64LO (GPR
[4]);
1279 FPR_STATE
[0] = fmt_uninterpreted
;
1281 else if (aregs
== 6)
1283 FGR
[0] = WORD64LO (GPR
[5]);
1284 FGR
[1] = WORD64LO (GPR
[4]);
1285 FPR_STATE
[0] = fmt_uninterpreted
;
1286 FPR_STATE
[1] = fmt_uninterpreted
;
1295 /*-- trace support ----------------------------------------------------------*/
1297 /* The TRACE support is provided (if required) in the memory accessing
1298 routines. Since we are also providing the architecture specific
1299 features, the architecture simulation code can also deal with
1300 notifying the TRACE world of cache flushes, etc. Similarly we do
1301 not need to provide profiling support in the simulator engine,
1302 since we can sample in the instruction fetch control loop. By
1303 defining the TRACE manifest, we add tracing as a run-time
1307 /* Tracing by default produces "din" format (as required by
1308 dineroIII). Each line of such a trace file *MUST* have a din label
1309 and address field. The rest of the line is ignored, so comments can
1310 be included if desired. The first field is the label which must be
1311 one of the following values:
1316 3 escape record (treated as unknown access type)
1317 4 escape record (causes cache flush)
1319 The address field is a 32bit (lower-case) hexadecimal address
1320 value. The address should *NOT* be preceded by "0x".
1322 The size of the memory transfer is not important when dealing with
1323 cache lines (as long as no more than a cache line can be
1324 transferred in a single operation :-), however more information
1325 could be given following the dineroIII requirement to allow more
1326 complete memory and cache simulators to provide better
1327 results. i.e. the University of Pisa has a cache simulator that can
1328 also take bus size and speed as (variable) inputs to calculate
1329 complete system performance (a much more useful ability when trying
1330 to construct an end product, rather than a processor). They
1331 currently have an ARM version of their tool called ChARM. */
1335 dotrace (SIM_DESC sd
,
1343 if (STATE
& simTRACE
) {
1345 fprintf(tracefh
,"%d %s ; width %d ; ",
1349 va_start(ap
,comment
);
1350 vfprintf(tracefh
,comment
,ap
);
1352 fprintf(tracefh
,"\n");
1354 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1355 we may be generating 64bit ones, we should put the hi-32bits of the
1356 address into the comment field. */
1358 /* TODO: Provide a buffer for the trace lines. We can then avoid
1359 performing writes until the buffer is filled, or the file is
1362 /* NOTE: We could consider adding a comment field to the "din" file
1363 produced using type 3 markers (unknown access). This would then
1364 allow information about the program that the "din" is for, and
1365 the MIPs world that was being simulated, to be placed into the
1372 /*---------------------------------------------------------------------------*/
1373 /*-- simulator engine -------------------------------------------------------*/
1374 /*---------------------------------------------------------------------------*/
1377 ColdReset (SIM_DESC sd
)
1380 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1382 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1383 /* RESET: Fixed PC address: */
1384 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1385 /* The reset vector address is in the unmapped, uncached memory space. */
1387 SR
&= ~(status_SR
| status_TS
| status_RP
);
1388 SR
|= (status_ERL
| status_BEV
);
1390 /* Cheat and allow access to the complete register set immediately */
1391 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1392 && WITH_TARGET_WORD_BITSIZE
== 64)
1393 SR
|= status_FR
; /* 64bit registers */
1395 /* Ensure that any instructions with pending register updates are
1397 PENDING_INVALIDATE();
1399 /* Initialise the FPU registers to the unknown state */
1400 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1403 for (rn
= 0; (rn
< 32); rn
++)
1404 FPR_STATE
[rn
] = fmt_uninterpreted
;
1410 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1412 /* Translate a virtual address to a physical address and cache
1413 coherence algorithm describing the mechanism used to resolve the
1414 memory reference. Given the virtual address vAddr, and whether the
1415 reference is to Instructions ot Data (IorD), find the corresponding
1416 physical address (pAddr) and the cache coherence algorithm (CCA)
1417 used to resolve the reference. If the virtual address is in one of
1418 the unmapped address spaces the physical address and the CCA are
1419 determined directly by the virtual address. If the virtual address
1420 is in one of the mapped address spaces then the TLB is used to
1421 determine the physical address and access type; if the required
1422 translation is not present in the TLB or the desired access is not
1423 permitted the function fails and an exception is taken.
1425 NOTE: Normally (RAW == 0), when address translation fails, this
1426 function raises an exception and does not return. */
1429 address_translation (SIM_DESC sd
,
1435 address_word
*pAddr
,
1439 int res
= -1; /* TRUE : Assume good return */
1442 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1445 /* Check that the address is valid for this memory model */
1447 /* For a simple (flat) memory model, we simply pass virtual
1448 addressess through (mostly) unchanged. */
1449 vAddr
&= 0xFFFFFFFF;
1451 *pAddr
= vAddr
; /* default for isTARGET */
1452 *CCA
= Uncached
; /* not used for isHOST */
1457 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1459 /* Prefetch data from memory. Prefetch is an advisory instruction for
1460 which an implementation specific action is taken. The action taken
1461 may increase performance, but must not change the meaning of the
1462 program, or alter architecturally-visible state. */
1465 prefetch (SIM_DESC sd
,
1475 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1478 /* For our simple memory model we do nothing */
1482 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1484 /* Load a value from memory. Use the cache and main memory as
1485 specified in the Cache Coherence Algorithm (CCA) and the sort of
1486 access (IorD) to find the contents of AccessLength memory bytes
1487 starting at physical location pAddr. The data is returned in the
1488 fixed width naturally-aligned memory element (MemElem). The
1489 low-order two (or three) bits of the address and the AccessLength
1490 indicate which of the bytes within MemElem needs to be given to the
1491 processor. If the memory access type of the reference is uncached
1492 then only the referenced bytes are read from memory and valid
1493 within the memory element. If the access type is cached, and the
1494 data is not present in cache, an implementation specific size and
1495 alignment block of memory is read and loaded into the cache to
1496 satisfy a load reference. At a minimum, the block is the entire
1499 load_memory (SIM_DESC sd
,
1514 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1517 #if defined(WARN_MEM)
1518 if (CCA
!= uncached
)
1519 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1520 #endif /* WARN_MEM */
1522 /* If instruction fetch then we need to check that the two lo-order
1523 bits are zero, otherwise raise a InstructionFetch exception: */
1524 if ((IorD
== isINSTRUCTION
)
1525 && ((pAddr
& 0x3) != 0)
1526 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1527 SignalExceptionInstructionFetch ();
1529 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1531 /* In reality this should be a Bus Error */
1532 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1534 (LOADDRMASK
+ 1) << 2,
1539 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1542 /* Read the specified number of bytes from memory. Adjust for
1543 host/target byte ordering/ Align the least significant byte
1546 switch (AccessLength
)
1548 case AccessLength_QUADWORD
:
1550 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
, read_map
, pAddr
);
1551 value1
= VH8_16 (val
);
1552 value
= VL8_16 (val
);
1555 case AccessLength_DOUBLEWORD
:
1556 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1559 case AccessLength_SEPTIBYTE
:
1560 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1563 case AccessLength_SEXTIBYTE
:
1564 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1567 case AccessLength_QUINTIBYTE
:
1568 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1571 case AccessLength_WORD
:
1572 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1575 case AccessLength_TRIPLEBYTE
:
1576 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1579 case AccessLength_HALFWORD
:
1580 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1583 case AccessLength_BYTE
:
1584 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1592 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1593 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1596 /* See also store_memory. */
1597 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1600 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1601 shifted to the most significant byte position. */
1602 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1604 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1605 is already in the correct postition. */
1606 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1610 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1611 pr_uword64(value1
),pr_uword64(value
));
1615 if (memval1p
) *memval1p
= value1
;
1619 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1621 /* Store a value to memory. The specified data is stored into the
1622 physical location pAddr using the memory hierarchy (data caches and
1623 main memory) as specified by the Cache Coherence Algorithm
1624 (CCA). The MemElem contains the data for an aligned, fixed-width
1625 memory element (word for 32-bit processors, doubleword for 64-bit
1626 processors), though only the bytes that will actually be stored to
1627 memory need to be valid. The low-order two (or three) bits of pAddr
1628 and the AccessLength field indicates which of the bytes within the
1629 MemElem data should actually be stored; only these bytes in memory
1633 store_memory (SIM_DESC sd
,
1639 uword64 MemElem1
, /* High order 64 bits */
1644 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1647 #if defined(WARN_MEM)
1648 if (CCA
!= uncached
)
1649 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1650 #endif /* WARN_MEM */
1652 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1653 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1656 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1660 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1663 /* See also load_memory */
1664 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1667 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1668 shifted to the most significant byte position. */
1669 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1671 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1672 is already in the correct postition. */
1673 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1677 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1680 switch (AccessLength
)
1682 case AccessLength_QUADWORD
:
1684 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1685 sim_core_write_aligned_16 (cpu
, NULL_CIA
, write_map
, pAddr
, val
);
1688 case AccessLength_DOUBLEWORD
:
1689 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1690 write_map
, pAddr
, MemElem
);
1692 case AccessLength_SEPTIBYTE
:
1693 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1694 write_map
, pAddr
, MemElem
);
1696 case AccessLength_SEXTIBYTE
:
1697 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1698 write_map
, pAddr
, MemElem
);
1700 case AccessLength_QUINTIBYTE
:
1701 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1702 write_map
, pAddr
, MemElem
);
1704 case AccessLength_WORD
:
1705 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1706 write_map
, pAddr
, MemElem
);
1708 case AccessLength_TRIPLEBYTE
:
1709 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1710 write_map
, pAddr
, MemElem
);
1712 case AccessLength_HALFWORD
:
1713 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1714 write_map
, pAddr
, MemElem
);
1716 case AccessLength_BYTE
:
1717 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1718 write_map
, pAddr
, MemElem
);
1729 ifetch32 (SIM_DESC sd
,
1734 /* Copy the action of the LW instruction */
1735 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1736 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1739 unsigned32 instruction
;
1742 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1743 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1744 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1745 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1746 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1752 ifetch16 (SIM_DESC sd
,
1757 /* Copy the action of the LW instruction */
1758 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1759 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1762 unsigned16 instruction
;
1765 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1766 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1767 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1768 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1769 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1774 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1775 /* Order loads and stores to synchronise shared memory. Perform the
1776 action necessary to make the effects of groups of synchronizable
1777 loads and stores indicated by stype occur in the same order for all
1780 sync_operation (SIM_DESC sd
,
1786 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1791 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1792 /* Signal an exception condition. This will result in an exception
1793 that aborts the instruction. The instruction operation pseudocode
1794 will never see a return from this function call. */
1797 signal_exception (SIM_DESC sd
,
1805 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1808 /* Ensure that any active atomic read/modify/write operation will fail: */
1811 switch (exception
) {
1812 /* TODO: For testing purposes I have been ignoring TRAPs. In
1813 reality we should either simulate them, or allow the user to
1814 ignore them at run-time.
1817 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1823 unsigned int instruction
;
1826 va_start(ap
,exception
);
1827 instruction
= va_arg(ap
,unsigned int);
1830 code
= (instruction
>> 6) & 0xFFFFF;
1832 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1833 code
, pr_addr(cia
));
1837 case DebugBreakPoint
:
1838 if (! (Debug
& Debug_DM
))
1844 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1845 DEPC
= cia
- 4; /* reference the branch instruction */
1849 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1853 Debug
|= Debug_DM
; /* in debugging mode */
1854 Debug
|= Debug_DBp
; /* raising a DBp exception */
1856 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1860 case ReservedInstruction
:
1863 unsigned int instruction
;
1864 va_start(ap
,exception
);
1865 instruction
= va_arg(ap
,unsigned int);
1867 /* Provide simple monitor support using ReservedInstruction
1868 exceptions. The following code simulates the fixed vector
1869 entry points into the IDT monitor by causing a simulator
1870 trap, performing the monitor operation, and returning to
1871 the address held in the $ra register (standard PCS return
1872 address). This means we only need to pre-load the vector
1873 space with suitable instruction values. For systems were
1874 actual trap instructions are used, we would not need to
1875 perform this magic. */
1876 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1878 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1879 /* NOTE: This assumes that a branch-and-link style
1880 instruction was used to enter the vector (which is the
1881 case with the current IDT monitor). */
1882 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1884 /* Look for the mips16 entry and exit instructions, and
1885 simulate a handler for them. */
1886 else if ((cia
& 1) != 0
1887 && (instruction
& 0xf81f) == 0xe809
1888 && (instruction
& 0x0c0) != 0x0c0)
1890 mips16_entry (SD
, CPU
, cia
, instruction
);
1891 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1893 /* else fall through to normal exception processing */
1894 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1899 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1901 /* Keep a copy of the current A0 in-case this is the program exit
1905 unsigned int instruction
;
1906 va_start(ap
,exception
);
1907 instruction
= va_arg(ap
,unsigned int);
1909 /* Check for our special terminating BREAK: */
1910 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1911 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1912 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1915 if (STATE
& simDELAYSLOT
)
1916 PC
= cia
- 4; /* reference the branch instruction */
1919 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1920 sim_stopped
, SIM_SIGTRAP
);
1923 /* Store exception code into current exception id variable (used
1926 /* TODO: If not simulating exceptions then stop the simulator
1927 execution. At the moment we always stop the simulation. */
1929 /* See figure 5-17 for an outline of the code below */
1930 if (! (SR
& status_EXL
))
1932 CAUSE
= (exception
<< 2);
1933 if (STATE
& simDELAYSLOT
)
1935 STATE
&= ~simDELAYSLOT
;
1937 EPC
= (cia
- 4); /* reference the branch instruction */
1941 /* FIXME: TLB et.al. */
1946 CAUSE
= (exception
<< 2);
1950 /* Store exception code into current exception id variable (used
1952 if (SR
& status_BEV
)
1953 PC
= (signed)0xBFC00200 + 0x180;
1955 PC
= (signed)0x80000000 + 0x180;
1957 switch ((CAUSE
>> 2) & 0x1F)
1960 /* Interrupts arrive during event processing, no need to
1964 case TLBModification
:
1969 case InstructionFetch
:
1971 /* The following is so that the simulator will continue from the
1972 exception address on breakpoint operations. */
1974 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1975 sim_stopped
, SIM_SIGBUS
);
1977 case ReservedInstruction
:
1978 case CoProcessorUnusable
:
1980 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1981 sim_stopped
, SIM_SIGILL
);
1983 case IntegerOverflow
:
1985 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1986 sim_stopped
, SIM_SIGFPE
);
1992 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1993 sim_stopped
, SIM_SIGTRAP
);
1997 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1998 "FATAL: Should not encounter a breakpoint\n");
2000 default : /* Unknown internal exception */
2002 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2003 sim_stopped
, SIM_SIGABRT
);
2007 case SimulatorFault
:
2011 va_start(ap
,exception
);
2012 msg
= va_arg(ap
,char *);
2014 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2015 "FATAL: Simulator error \"%s\"\n",msg
);
2022 #if defined(WARN_RESULT)
2023 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2024 /* This function indicates that the result of the operation is
2025 undefined. However, this should not affect the instruction
2026 stream. All that is meant to happen is that the destination
2027 register is set to an undefined result. To keep the simulator
2028 simple, we just don't bother updating the destination register, so
2029 the overall result will be undefined. If desired we can stop the
2030 simulator by raising a pseudo-exception. */
2031 #define UndefinedResult() undefined_result (sd,cia)
2033 undefined_result(sd
,cia
)
2037 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
2038 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2043 #endif /* WARN_RESULT */
2046 cache_op (SIM_DESC sd
,
2052 unsigned int instruction
)
2054 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2055 static int icache_warning
= 1;
2056 static int dcache_warning
= 1;
2058 static int icache_warning
= 0;
2059 static int dcache_warning
= 0;
2062 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2063 enable bit in the Status Register is clear - a coprocessor
2064 unusable exception is taken. */
2066 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
2070 case 0: /* instruction cache */
2072 case 0: /* Index Invalidate */
2073 case 1: /* Index Load Tag */
2074 case 2: /* Index Store Tag */
2075 case 4: /* Hit Invalidate */
2077 case 6: /* Hit Writeback */
2078 if (!icache_warning
)
2080 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2086 SignalException(ReservedInstruction
,instruction
);
2091 case 1: /* data cache */
2093 case 0: /* Index Writeback Invalidate */
2094 case 1: /* Index Load Tag */
2095 case 2: /* Index Store Tag */
2096 case 3: /* Create Dirty */
2097 case 4: /* Hit Invalidate */
2098 case 5: /* Hit Writeback Invalidate */
2099 case 6: /* Hit Writeback */
2100 if (!dcache_warning
)
2102 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2108 SignalException(ReservedInstruction
,instruction
);
2113 default: /* unrecognised cache ID */
2114 SignalException(ReservedInstruction
,instruction
);
2121 /*-- FPU support routines ---------------------------------------------------*/
2123 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2124 formats conform to ANSI/IEEE Std 754-1985. */
2125 /* SINGLE precision floating:
2126 * seeeeeeeefffffffffffffffffffffff
2128 * e = 8bits = exponent
2129 * f = 23bits = fraction
2131 /* SINGLE precision fixed:
2132 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2134 * i = 31bits = integer
2136 /* DOUBLE precision floating:
2137 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2139 * e = 11bits = exponent
2140 * f = 52bits = fraction
2142 /* DOUBLE precision fixed:
2143 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2145 * i = 63bits = integer
2148 /* Extract sign-bit: */
2149 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2150 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2151 /* Extract biased exponent: */
2152 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2153 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2154 /* Extract unbiased Exponent: */
2155 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2156 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2157 /* Extract complete fraction field: */
2158 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2159 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2160 /* Extract numbered fraction bit: */
2161 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2162 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2164 /* Explicit QNaN values used when value required: */
2165 #define FPQNaN_SINGLE (0x7FBFFFFF)
2166 #define FPQNaN_WORD (0x7FFFFFFF)
2167 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2168 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2170 /* Explicit Infinity values used when required: */
2171 #define FPINF_SINGLE (0x7F800000)
2172 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2174 #if 1 /* def DEBUG */
2175 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2176 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2180 value_fpr (SIM_DESC sd
,
2189 /* Treat unused register values, as fixed-point 64bit values: */
2190 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2192 /* If request to read data as "uninterpreted", then use the current
2194 fmt
= FPR_STATE
[fpr
];
2199 /* For values not yet accessed, set to the desired format: */
2200 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2201 FPR_STATE
[fpr
] = fmt
;
2203 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2206 if (fmt
!= FPR_STATE
[fpr
]) {
2207 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2208 FPR_STATE
[fpr
] = fmt_unknown
;
2211 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2212 /* Set QNaN value: */
2215 value
= FPQNaN_SINGLE
;
2219 value
= FPQNaN_DOUBLE
;
2223 value
= FPQNaN_WORD
;
2227 value
= FPQNaN_LONG
;
2234 } else if (SizeFGR() == 64) {
2238 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2241 case fmt_uninterpreted
:
2255 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2258 case fmt_uninterpreted
:
2261 if ((fpr
& 1) == 0) { /* even registers only */
2262 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2264 SignalException(ReservedInstruction
,0);
2275 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2278 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2285 store_fpr (SIM_DESC sd
,
2295 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2298 if (SizeFGR() == 64) {
2300 case fmt_uninterpreted_32
:
2301 fmt
= fmt_uninterpreted
;
2304 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2305 FPR_STATE
[fpr
] = fmt
;
2308 case fmt_uninterpreted_64
:
2309 fmt
= fmt_uninterpreted
;
2310 case fmt_uninterpreted
:
2314 FPR_STATE
[fpr
] = fmt
;
2318 FPR_STATE
[fpr
] = fmt_unknown
;
2324 case fmt_uninterpreted_32
:
2325 fmt
= fmt_uninterpreted
;
2328 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2329 FPR_STATE
[fpr
] = fmt
;
2332 case fmt_uninterpreted_64
:
2333 fmt
= fmt_uninterpreted
;
2334 case fmt_uninterpreted
:
2337 if ((fpr
& 1) == 0) { /* even register number only */
2338 FGR
[fpr
+1] = (value
>> 32);
2339 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2340 FPR_STATE
[fpr
+ 1] = fmt
;
2341 FPR_STATE
[fpr
] = fmt
;
2343 FPR_STATE
[fpr
] = fmt_unknown
;
2344 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2345 SignalException(ReservedInstruction
,0);
2350 FPR_STATE
[fpr
] = fmt_unknown
;
2355 #if defined(WARN_RESULT)
2358 #endif /* WARN_RESULT */
2361 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2364 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2381 sim_fpu_32to (&wop
, op
);
2382 boolean
= sim_fpu_is_nan (&wop
);
2389 sim_fpu_64to (&wop
, op
);
2390 boolean
= sim_fpu_is_nan (&wop
);
2394 fprintf (stderr
, "Bad switch\n");
2399 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2413 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2420 sim_fpu_32to (&wop
, op
);
2421 boolean
= sim_fpu_is_infinity (&wop
);
2427 sim_fpu_64to (&wop
, op
);
2428 boolean
= sim_fpu_is_infinity (&wop
);
2432 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2437 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2451 /* Argument checking already performed by the FPCOMPARE code */
2454 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2457 /* The format type should already have been checked: */
2463 sim_fpu_32to (&wop1
, op1
);
2464 sim_fpu_32to (&wop2
, op2
);
2465 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2472 sim_fpu_64to (&wop1
, op1
);
2473 sim_fpu_64to (&wop2
, op2
);
2474 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2478 fprintf (stderr
, "Bad switch\n");
2483 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2497 /* Argument checking already performed by the FPCOMPARE code */
2500 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2503 /* The format type should already have been checked: */
2509 sim_fpu_32to (&wop1
, op1
);
2510 sim_fpu_32to (&wop2
, op2
);
2511 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2518 sim_fpu_64to (&wop1
, op1
);
2519 sim_fpu_64to (&wop2
, op2
);
2520 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2524 fprintf (stderr
, "Bad switch\n");
2529 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2536 AbsoluteValue(op
,fmt
)
2543 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2546 /* The format type should already have been checked: */
2552 sim_fpu_32to (&wop
, op
);
2553 sim_fpu_abs (&wop
, &wop
);
2554 sim_fpu_to32 (&ans
, &wop
);
2562 sim_fpu_64to (&wop
, op
);
2563 sim_fpu_abs (&wop
, &wop
);
2564 sim_fpu_to64 (&ans
, &wop
);
2569 fprintf (stderr
, "Bad switch\n");
2584 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2587 /* The format type should already have been checked: */
2593 sim_fpu_32to (&wop
, op
);
2594 sim_fpu_neg (&wop
, &wop
);
2595 sim_fpu_to32 (&ans
, &wop
);
2603 sim_fpu_64to (&wop
, op
);
2604 sim_fpu_neg (&wop
, &wop
);
2605 sim_fpu_to64 (&ans
, &wop
);
2610 fprintf (stderr
, "Bad switch\n");
2626 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2629 /* The registers must specify FPRs valid for operands of type
2630 "fmt". If they are not valid, the result is undefined. */
2632 /* The format type should already have been checked: */
2640 sim_fpu_32to (&wop1
, op1
);
2641 sim_fpu_32to (&wop2
, op2
);
2642 sim_fpu_add (&ans
, &wop1
, &wop2
);
2643 sim_fpu_to32 (&res
, &ans
);
2653 sim_fpu_64to (&wop1
, op1
);
2654 sim_fpu_64to (&wop2
, op2
);
2655 sim_fpu_add (&ans
, &wop1
, &wop2
);
2656 sim_fpu_to64 (&res
, &ans
);
2661 fprintf (stderr
, "Bad switch\n");
2666 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2681 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2684 /* The registers must specify FPRs valid for operands of type
2685 "fmt". If they are not valid, the result is undefined. */
2687 /* The format type should already have been checked: */
2695 sim_fpu_32to (&wop1
, op1
);
2696 sim_fpu_32to (&wop2
, op2
);
2697 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2698 sim_fpu_to32 (&res
, &ans
);
2708 sim_fpu_64to (&wop1
, op1
);
2709 sim_fpu_64to (&wop2
, op2
);
2710 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2711 sim_fpu_to64 (&res
, &ans
);
2716 fprintf (stderr
, "Bad switch\n");
2721 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2728 Multiply(op1
,op2
,fmt
)
2736 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2739 /* The registers must specify FPRs valid for operands of type
2740 "fmt". If they are not valid, the result is undefined. */
2742 /* The format type should already have been checked: */
2750 sim_fpu_32to (&wop1
, op1
);
2751 sim_fpu_32to (&wop2
, op2
);
2752 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2753 sim_fpu_to32 (&res
, &ans
);
2763 sim_fpu_64to (&wop1
, op1
);
2764 sim_fpu_64to (&wop2
, op2
);
2765 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2766 sim_fpu_to64 (&res
, &ans
);
2771 fprintf (stderr
, "Bad switch\n");
2776 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2791 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2794 /* The registers must specify FPRs valid for operands of type
2795 "fmt". If they are not valid, the result is undefined. */
2797 /* The format type should already have been checked: */
2805 sim_fpu_32to (&wop1
, op1
);
2806 sim_fpu_32to (&wop2
, op2
);
2807 sim_fpu_div (&ans
, &wop1
, &wop2
);
2808 sim_fpu_to32 (&res
, &ans
);
2818 sim_fpu_64to (&wop1
, op1
);
2819 sim_fpu_64to (&wop2
, op2
);
2820 sim_fpu_div (&ans
, &wop1
, &wop2
);
2821 sim_fpu_to64 (&res
, &ans
);
2826 fprintf (stderr
, "Bad switch\n");
2831 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2845 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2848 /* The registers must specify FPRs valid for operands of type
2849 "fmt". If they are not valid, the result is undefined. */
2851 /* The format type should already have been checked: */
2858 sim_fpu_32to (&wop
, op
);
2859 sim_fpu_inv (&ans
, &wop
);
2860 sim_fpu_to32 (&res
, &ans
);
2869 sim_fpu_64to (&wop
, op
);
2870 sim_fpu_inv (&ans
, &wop
);
2871 sim_fpu_to64 (&res
, &ans
);
2876 fprintf (stderr
, "Bad switch\n");
2881 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2895 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2898 /* The registers must specify FPRs valid for operands of type
2899 "fmt". If they are not valid, the result is undefined. */
2901 /* The format type should already have been checked: */
2908 sim_fpu_32to (&wop
, op
);
2909 sim_fpu_sqrt (&ans
, &wop
);
2910 sim_fpu_to32 (&res
, &ans
);
2919 sim_fpu_64to (&wop
, op
);
2920 sim_fpu_sqrt (&ans
, &wop
);
2921 sim_fpu_to64 (&res
, &ans
);
2926 fprintf (stderr
, "Bad switch\n");
2931 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2947 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2950 /* The registers must specify FPRs valid for operands of type
2951 "fmt". If they are not valid, the result is undefined. */
2953 /* The format type should already have been checked: */
2960 sim_fpu_32to (&wop1
, op1
);
2961 sim_fpu_32to (&wop2
, op2
);
2962 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2969 sim_fpu_64to (&wop1
, op1
);
2970 sim_fpu_64to (&wop2
, op2
);
2971 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2975 fprintf (stderr
, "Bad switch\n");
2981 case SIM_FPU_IS_SNAN
:
2982 case SIM_FPU_IS_QNAN
:
2984 case SIM_FPU_IS_NINF
:
2985 case SIM_FPU_IS_NNUMBER
:
2986 case SIM_FPU_IS_NDENORM
:
2987 case SIM_FPU_IS_NZERO
:
2988 result
= op2
; /* op1 - op2 < 0 */
2989 case SIM_FPU_IS_PINF
:
2990 case SIM_FPU_IS_PNUMBER
:
2991 case SIM_FPU_IS_PDENORM
:
2992 case SIM_FPU_IS_PZERO
:
2993 result
= op1
; /* op1 - op2 > 0 */
2995 fprintf (stderr
, "Bad switch\n");
3000 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3017 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3020 /* The registers must specify FPRs valid for operands of type
3021 "fmt". If they are not valid, the result is undefined. */
3023 /* The format type should already have been checked: */
3030 sim_fpu_32to (&wop1
, op1
);
3031 sim_fpu_32to (&wop2
, op2
);
3032 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3039 sim_fpu_64to (&wop1
, op1
);
3040 sim_fpu_64to (&wop2
, op2
);
3041 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3045 fprintf (stderr
, "Bad switch\n");
3051 case SIM_FPU_IS_SNAN
:
3052 case SIM_FPU_IS_QNAN
:
3054 case SIM_FPU_IS_NINF
:
3055 case SIM_FPU_IS_NNUMBER
:
3056 case SIM_FPU_IS_NDENORM
:
3057 case SIM_FPU_IS_NZERO
:
3058 result
= op1
; /* op1 - op2 < 0 */
3059 case SIM_FPU_IS_PINF
:
3060 case SIM_FPU_IS_PNUMBER
:
3061 case SIM_FPU_IS_PDENORM
:
3062 case SIM_FPU_IS_PZERO
:
3063 result
= op2
; /* op1 - op2 > 0 */
3065 fprintf (stderr
, "Bad switch\n");
3070 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3078 convert (SIM_DESC sd
,
3087 sim_fpu_round round
;
3088 unsigned32 result32
;
3089 unsigned64 result64
;
3092 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3098 /* Round result to nearest representable value. When two
3099 representable values are equally near, round to the value
3100 that has a least significant bit of zero (i.e. is even). */
3101 round
= sim_fpu_round_near
;
3104 /* Round result to the value closest to, and not greater in
3105 magnitude than, the result. */
3106 round
= sim_fpu_round_zero
;
3109 /* Round result to the value closest to, and not less than,
3111 round
= sim_fpu_round_up
;
3115 /* Round result to the value closest to, and not greater than,
3117 round
= sim_fpu_round_down
;
3121 fprintf (stderr
, "Bad switch\n");
3125 /* Convert the input to sim_fpu internal format */
3129 sim_fpu_64to (&wop
, op
);
3132 sim_fpu_32to (&wop
, op
);
3135 sim_fpu_i32to (&wop
, op
, round
);
3138 sim_fpu_i64to (&wop
, op
, round
);
3141 fprintf (stderr
, "Bad switch\n");
3145 /* Convert sim_fpu format into the output */
3146 /* The value WOP is converted to the destination format, rounding
3147 using mode RM. When the destination is a fixed-point format, then
3148 a source value of Infinity, NaN or one which would round to an
3149 integer outside the fixed point range then an IEEE Invalid
3150 Operation condition is raised. */
3154 sim_fpu_round_32 (&wop
, round
, 0);
3155 sim_fpu_to32 (&result32
, &wop
);
3156 result64
= result32
;
3159 sim_fpu_round_64 (&wop
, round
, 0);
3160 sim_fpu_to64 (&result64
, &wop
);
3163 sim_fpu_to32i (&result32
, &wop
, round
);
3164 result64
= result32
;
3167 sim_fpu_to64i (&result64
, &wop
, round
);
3171 fprintf (stderr
, "Bad switch\n");
3176 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
3183 /*-- co-processor support routines ------------------------------------------*/
3186 CoProcPresent(coproc_number
)
3187 unsigned int coproc_number
;
3189 /* Return TRUE if simulator provides a model for the given co-processor number */
3194 cop_lw (SIM_DESC sd
,
3199 unsigned int memword
)
3204 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3207 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3209 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3210 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3215 #if 0 /* this should be controlled by a configuration option */
3216 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3225 cop_ld (SIM_DESC sd
,
3232 switch (coproc_num
) {
3234 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3236 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3241 #if 0 /* this message should be controlled by a configuration option */
3242 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3252 cop_lq (SIM_DESC sd
,
3257 unsigned128 memword
)
3261 /* start-sanitize-sky */
3265 /* end-sanitize-sky */
3268 sim_io_printf(sd
,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3269 coproc_num
,coproc_reg
,pr_addr(cia
));
3278 cop_sw (SIM_DESC sd
,
3284 unsigned int value
= 0;
3289 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3292 hold
= FPR_STATE
[coproc_reg
];
3293 FPR_STATE
[coproc_reg
] = fmt_word
;
3294 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3295 FPR_STATE
[coproc_reg
] = hold
;
3300 #if 0 /* should be controlled by configuration option */
3301 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3310 cop_sd (SIM_DESC sd
,
3320 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3322 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3327 #if 0 /* should be controlled by configuration option */
3328 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3338 cop_sq (SIM_DESC sd
,
3344 unsigned128 value
= {0, 0};
3347 /* start-sanitize-sky */
3351 /* end-sanitize-sky */
3354 sim_io_printf(sd
,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3355 coproc_num
,coproc_reg
,pr_addr(cia
));
3364 decode_coproc (SIM_DESC sd
,
3367 unsigned int instruction
)
3369 int coprocnum
= ((instruction
>> 26) & 3);
3373 case 0: /* standard CPU control and cache registers */
3375 int code
= ((instruction
>> 21) & 0x1F);
3376 /* R4000 Users Manual (second edition) lists the following CP0
3378 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3379 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3380 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3381 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3382 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3383 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3384 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3385 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3386 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3387 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3389 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3391 int rt
= ((instruction
>> 16) & 0x1F);
3392 int rd
= ((instruction
>> 11) & 0x1F);
3394 switch (rd
) /* NOTEs: Standard CP0 registers */
3396 /* 0 = Index R4000 VR4100 VR4300 */
3397 /* 1 = Random R4000 VR4100 VR4300 */
3398 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3399 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3400 /* 4 = Context R4000 VR4100 VR4300 */
3401 /* 5 = PageMask R4000 VR4100 VR4300 */
3402 /* 6 = Wired R4000 VR4100 VR4300 */
3403 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3404 /* 9 = Count R4000 VR4100 VR4300 */
3405 /* 10 = EntryHi R4000 VR4100 VR4300 */
3406 /* 11 = Compare R4000 VR4100 VR4300 */
3407 /* 12 = SR R4000 VR4100 VR4300 */
3414 /* 13 = Cause R4000 VR4100 VR4300 */
3421 /* 14 = EPC R4000 VR4100 VR4300 */
3422 /* 15 = PRId R4000 VR4100 VR4300 */
3423 #ifdef SUBTARGET_R3900
3432 /* 16 = Config R4000 VR4100 VR4300 */
3435 GPR
[rt
] = C0_CONFIG
;
3437 C0_CONFIG
= GPR
[rt
];
3440 #ifdef SUBTARGET_R3900
3449 /* 17 = LLAddr R4000 VR4100 VR4300 */
3451 /* 18 = WatchLo R4000 VR4100 VR4300 */
3452 /* 19 = WatchHi R4000 VR4100 VR4300 */
3453 /* 20 = XContext R4000 VR4100 VR4300 */
3454 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3455 /* 27 = CacheErr R4000 VR4100 */
3456 /* 28 = TagLo R4000 VR4100 VR4300 */
3457 /* 29 = TagHi R4000 VR4100 VR4300 */
3458 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3459 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3460 /* CPR[0,rd] = GPR[rt]; */
3463 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3465 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3468 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3471 if (SR
& status_ERL
)
3473 /* Oops, not yet available */
3474 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3484 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3488 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3496 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3497 /* TODO: When executing an ERET or RFE instruction we should
3498 clear LLBIT, to ensure that any out-standing atomic
3499 read/modify/write sequence fails. */
3503 case 2: /* undefined co-processor */
3507 /* start-sanitize-sky */
3509 /* On the R5900, this refers to a "VU" vector co-processor. */
3511 int i_25_21
= (instruction
>> 21) & 0x1f;
3512 int i_20_16
= (instruction
>> 16) & 0x1f;
3513 int i_15_11
= (instruction
>> 11) & 0x1f;
3514 int i_15_0
= instruction
& 0xffff;
3515 int i_10_1
= (instruction
>> 1) & 0x3ff;
3516 int interlock
= instruction
& 0x01;
3517 unsigned_4 vpe_status
= sim_core_read_aligned_4 (cpu
, cia
, read_map
, VPE0_STAT
);
3518 int vpe_busy
= (vpe_status
& 0x00000001);
3519 /* setup for semantic.c-like actions below */
3520 typedef unsigned_4 instruction_word
;
3523 sim_cpu
* CPU_
= cpu
;
3527 /* test COP2 usability */
3528 if(! (SR
& status_CU2
))
3530 SignalException(CoProcessorUnusable
,instruction
);
3534 /* classify & execute basic COP2 instructions */
3535 if(i_25_21
== 0x08 && i_20_16
== 0x00) /* BC2F */
3537 address_word offset
= EXTEND16(i_15_0
) << 2;
3538 if(! vpe_busy
) DELAY_SLOT(cia
+ 4 + offset
);
3540 else if(i_25_21
== 0x08 && i_20_16
==0x02) /* BC2FL */
3542 address_word offset
= EXTEND16(i_15_0
) << 2;
3543 if(! vpe_busy
) DELAY_SLOT(cia
+ 4 + offset
);
3544 else NULLIFY_NEXT_INSTRUCTION();
3546 else if(i_25_21
== 0x08 && i_20_16
== 0x01) /* BC2T */
3548 address_word offset
= EXTEND16(i_15_0
) << 2;
3549 if(vpe_busy
) DELAY_SLOT(cia
+ 4 + offset
);
3551 else if(i_25_21
== 0x08 && i_20_16
== 0x03) /* BC2TL */
3553 address_word offset
= EXTEND16(i_15_0
) << 2;
3554 if(vpe_busy
) DELAY_SLOT(cia
+ 4 + offset
);
3555 else NULLIFY_NEXT_INSTRUCTION();
3557 else if((i_25_21
== 0x02 && i_10_1
== 0x000) || /* CFC2 */
3558 (i_25_21
== 0x06 && i_10_1
== 0x000)) /* CTC2 */
3562 int to_vu
= (i_25_21
== 0x06); /* transfer direction */
3563 address_word vu_cr_addr
; /* VU control register address */
3568 vu0_issue(sd
); /* advance one clock cycle */
3569 vpe_status
= sim_core_read_aligned_4 (cpu
, cia
, read_map
, VPE0_STAT
);
3570 vpe_busy
= vpe_status
& 0x00000001;
3573 /* compute VU register address */
3574 vu_cr_addr
= VU0_MST
+ (id
* 16);
3576 /* read or write word */
3577 if(to_vu
) /* CTC2 */
3579 unsigned_4 data
= GPR
[rt
];
3580 sim_core_write_aligned_4(cpu
, cia
, write_map
, vu_cr_addr
, data
);
3584 unsigned_4 data
= sim_core_read_aligned_4(cpu
, cia
, read_map
, vu_cr_addr
);
3585 GPR
[rt
] = EXTEND64(data
);
3588 else if((i_25_21
== 0x01) || /* QMFC2 */
3589 (i_25_21
== 0x05)) /* QMTC2 */
3593 int to_vu
= (i_25_21
== 0x05); /* transfer direction */
3594 address_word vu_cr_addr
; /* VU control register address */
3599 vu0_issue(sd
); /* advance one clock cycle */
3600 vpe_status
= sim_core_read_aligned_4 (cpu
, cia
, read_map
, VPE0_STAT
);
3601 vpe_busy
= vpe_status
& 0x00000001;
3604 /* compute VU register address */
3605 vu_cr_addr
= VU0_VF00
+ (id
* 16);
3607 /* read or write word */
3608 if(to_vu
) /* CTC2 */
3610 unsigned_4 data
= GPR
[rt
];
3611 sim_core_write_aligned_4(cpu
, cia
, write_map
, vu_cr_addr
, data
);
3615 unsigned_4 data
= sim_core_read_aligned_4(cpu
, cia
, read_map
, vu_cr_addr
);
3616 GPR
[rt
] = EXTEND64(data
);
3619 /* other COP2 instructions */
3622 SignalException(ReservedInstruction
,instruction
);
3626 /* cleanup for semantic.c-like actions above */
3629 #endif /* TARGET_SKY */
3630 /* end-sanitize-sky */
3634 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3635 instruction
,pr_addr(cia
));
3640 case 1: /* should not occur (FPU co-processor) */
3641 case 3: /* should not occur (FPU co-processor) */
3642 SignalException(ReservedInstruction
,instruction
);
3650 /*-- instruction simulation -------------------------------------------------*/
3652 /* When the IGEN simulator is being built, the function below is be
3653 replaced by a generated version. However, WITH_IGEN == 2 indicates
3654 that the fubction below should be compiled but under a different
3655 name (to allow backward compatibility) */
3657 #if (WITH_IGEN != 1)
3659 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3661 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3664 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3667 int next_cpu_nr
; /* ignore */
3668 int nr_cpus
; /* ignore */
3669 int siggnal
; /* ignore */
3671 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3672 #if !defined(FASTSIM)
3673 unsigned int pipeline_count
= 1;
3677 if (STATE_MEMORY (sd
) == NULL
) {
3678 printf("DBG: simulate() entered with no memory\n");
3683 #if 0 /* Disabled to check that everything works OK */
3684 /* The VR4300 seems to sign-extend the PC on its first
3685 access. However, this may just be because it is currently
3686 configured in 32bit mode. However... */
3687 PC
= SIGNEXTEND(PC
,32);
3690 /* main controlling loop */
3692 /* vaddr is slowly being replaced with cia - current instruction
3694 address_word cia
= (uword64
)PC
;
3695 address_word vaddr
= cia
;
3698 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3702 printf("DBG: state = 0x%08X :",state
);
3703 if (state
& simHALTEX
) printf(" simHALTEX");
3704 if (state
& simHALTIN
) printf(" simHALTIN");
3709 DSSTATE
= (STATE
& simDELAYSLOT
);
3712 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3715 /* Fetch the next instruction from the simulator memory: */
3716 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3717 if ((vaddr
& 1) == 0) {
3718 /* Copy the action of the LW instruction */
3719 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3720 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3723 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3724 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3725 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3726 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3728 /* Copy the action of the LH instruction */
3729 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3730 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3733 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3734 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3735 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3736 paddr
& ~ (uword64
) 1,
3737 vaddr
, isINSTRUCTION
, isREAL
);
3738 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3739 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3742 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3747 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3750 /* This is required by exception processing, to ensure that we can
3751 cope with exceptions in the delay slots of branches that may
3752 already have changed the PC. */
3753 if ((vaddr
& 1) == 0)
3754 PC
+= 4; /* increment ready for the next fetch */
3757 /* NOTE: If we perform a delay slot change to the PC, this
3758 increment is not requuired. However, it would make the
3759 simulator more complicated to try and avoid this small hit. */
3761 /* Currently this code provides a simple model. For more
3762 complicated models we could perform exception status checks at
3763 this point, and set the simSTOP state as required. This could
3764 also include processing any hardware interrupts raised by any
3765 I/O model attached to the simulator context.
3767 Support for "asynchronous" I/O events within the simulated world
3768 could be providing by managing a counter, and calling a I/O
3769 specific handler when a particular threshold is reached. On most
3770 architectures a decrement and check for zero operation is
3771 usually quicker than an increment and compare. However, the
3772 process of managing a known value decrement to zero, is higher
3773 than the cost of using an explicit value UINT_MAX into the
3774 future. Which system is used will depend on how complicated the
3775 I/O model is, and how much it is likely to affect the simulator
3778 If events need to be scheduled further in the future than
3779 UINT_MAX event ticks, then the I/O model should just provide its
3780 own counter, triggered from the event system. */
3782 /* MIPS pipeline ticks. To allow for future support where the
3783 pipeline hit of individual instructions is known, this control
3784 loop manages a "pipeline_count" variable. It is initialised to
3785 1 (one), and will only be changed by the simulator engine when
3786 executing an instruction. If the engine does not have access to
3787 pipeline cycle count information then all instructions will be
3788 treated as using a single cycle. NOTE: A standard system is not
3789 provided by the default simulator because different MIPS
3790 architectures have different cycle counts for the same
3793 [NOTE: pipeline_count has been replaced the event queue] */
3795 /* shuffle the floating point status pipeline state */
3796 ENGINE_ISSUE_PREFIX_HOOK();
3798 /* NOTE: For multi-context simulation environments the "instruction"
3799 variable should be local to this routine. */
3801 /* Shorthand accesses for engine. Note: If we wanted to use global
3802 variables (and a single-threaded simulator engine), then we can
3803 create the actual variables with these names. */
3805 if (!(STATE
& simSKIPNEXT
)) {
3806 /* Include the simulator engine */
3807 #include "oengine.c"
3808 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3809 #error "Mismatch between run-time simulator code and simulation engine"
3811 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3812 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3814 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3815 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3818 #if defined(WARN_LOHI)
3819 /* Decrement the HI/LO validity ticks */
3824 /* start-sanitize-r5900 */
3829 /* end-sanitize-r5900 */
3830 #endif /* WARN_LOHI */
3832 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3833 should check for it being changed. It is better doing it here,
3834 than within the simulator, since it will help keep the simulator
3837 #if defined(WARN_ZERO)
3838 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3839 #endif /* WARN_ZERO */
3840 ZERO
= 0; /* reset back to zero before next instruction */
3842 } else /* simSKIPNEXT check */
3843 STATE
&= ~simSKIPNEXT
;
3845 /* If the delay slot was active before the instruction is
3846 executed, then update the PC to its new value: */
3849 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3858 #if !defined(FASTSIM)
3859 if (sim_events_tickn (sd
, pipeline_count
))
3861 /* cpu->cia = cia; */
3862 sim_events_process (sd
);
3865 if (sim_events_tick (sd
))
3867 /* cpu->cia = cia; */
3868 sim_events_process (sd
);
3870 #endif /* FASTSIM */
3876 /* This code copied from gdb's utils.c. Would like to share this code,
3877 but don't know of a common place where both could get to it. */
3879 /* Temporary storage using circular buffer */
3885 static char buf
[NUMCELLS
][CELLSIZE
];
3887 if (++cell
>=NUMCELLS
) cell
=0;
3891 /* Print routines to handle variable size regs, etc */
3893 /* Eliminate warning from compiler on 32-bit systems */
3894 static int thirty_two
= 32;
3900 char *paddr_str
=get_cell();
3901 switch (sizeof(addr
))
3904 sprintf(paddr_str
,"%08lx%08lx",
3905 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3908 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3911 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3914 sprintf(paddr_str
,"%x",addr
);
3923 char *paddr_str
=get_cell();
3924 sprintf(paddr_str
,"%08lx%08lx",
3925 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3931 pending_tick (SIM_DESC sd
,
3936 sim_io_printf (sd
, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN
, PENDING_OUT
, PENDING_TOTAL
);
3937 if (PENDING_OUT
!= PENDING_IN
)
3940 int index
= PENDING_OUT
;
3941 int total
= PENDING_TOTAL
;
3942 if (PENDING_TOTAL
== 0)
3943 sim_engine_abort (SD
, CPU
, cia
, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3944 for (loop
= 0; (loop
< total
); loop
++)
3946 if (PENDING_SLOT_DEST
[index
] != NULL
)
3948 PENDING_SLOT_DELAY
[index
] -= 1;
3949 if (PENDING_SLOT_DELAY
[index
] == 0)
3951 if (PENDING_SLOT_BIT
[index
] >= 0)
3952 switch (PENDING_SLOT_SIZE
[index
])
3955 if (PENDING_SLOT_VALUE
[index
])
3956 *(unsigned32
*)PENDING_SLOT_DEST
[index
] |=
3957 BIT32 (PENDING_SLOT_BIT
[index
]);
3959 *(unsigned32
*)PENDING_SLOT_DEST
[index
] &=
3960 BIT32 (PENDING_SLOT_BIT
[index
]);
3963 if (PENDING_SLOT_VALUE
[index
])
3964 *(unsigned64
*)PENDING_SLOT_DEST
[index
] |=
3965 BIT64 (PENDING_SLOT_BIT
[index
]);
3967 *(unsigned64
*)PENDING_SLOT_DEST
[index
] &=
3968 BIT64 (PENDING_SLOT_BIT
[index
]);
3973 switch (PENDING_SLOT_SIZE
[index
])
3976 *(unsigned32
*)PENDING_SLOT_DEST
[index
] =
3977 PENDING_SLOT_VALUE
[index
];
3980 *(unsigned64
*)PENDING_SLOT_DEST
[index
] =
3981 PENDING_SLOT_VALUE
[index
];
3985 if (PENDING_OUT
== index
)
3987 PENDING_SLOT_DEST
[index
] = NULL
;
3988 PENDING_OUT
= (PENDING_OUT
+ 1) % PSLOTS
;
3993 index
= (index
+ 1) % PSLOTS
;
3997 /*---------------------------------------------------------------------------*/
3998 /*> EOF interp.c <*/