2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
114 static void ColdReset
PARAMS((SIM_DESC sd
));
116 /*---------------------------------------------------------------------------*/
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
126 #define JALDELAYSLOT() {\
128 STATE |= simJALDELAYSLOT;\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
136 #define CANCELDELAYSLOT() {\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
151 /* start-sanitize-sky */
154 #define MEM_SIZE (16 << 20) /* 16 MB */
156 /* end-sanitize-sky */
159 static char *tracefile
= "trace.din"; /* default filename for trace log */
160 FILE *tracefh
= NULL
;
161 static void open_trace
PARAMS((SIM_DESC sd
));
164 static DECLARE_OPTION_HANDLER (mips_option_handler
);
166 #define OPTION_DINERO_TRACE 200
167 #define OPTION_DINERO_FILE 201
170 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
180 case OPTION_DINERO_TRACE
: /* ??? */
182 /* Eventually the simTRACE flag could be treated as a toggle, to
183 allow external control of the program points being traced
184 (i.e. only from main onwards, excluding the run-time setup,
186 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
188 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
191 else if (strcmp (arg
, "yes") == 0)
193 else if (strcmp (arg
, "no") == 0)
195 else if (strcmp (arg
, "on") == 0)
197 else if (strcmp (arg
, "off") == 0)
201 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
208 Simulator constructed without dinero tracing support (for performance).\n\
209 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
213 case OPTION_DINERO_FILE
:
215 if (optarg
!= NULL
) {
217 tmp
= (char *)malloc(strlen(optarg
) + 1);
220 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
226 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
237 static const OPTION mips_options
[] =
239 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
240 '\0', "on|off", "Enable dinero tracing",
241 mips_option_handler
},
242 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
243 '\0', "FILE", "Write dinero trace to FILE",
244 mips_option_handler
},
245 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
249 int interrupt_pending
;
252 interrupt_event (SIM_DESC sd
, void *data
)
254 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
257 interrupt_pending
= 0;
258 SignalExceptionInterrupt ();
260 else if (!interrupt_pending
)
261 sim_events_schedule (sd
, 1, interrupt_event
, data
);
265 /*---------------------------------------------------------------------------*/
266 /*-- Device registration hook -----------------------------------------------*/
267 /*---------------------------------------------------------------------------*/
268 static void device_init(SIM_DESC sd
) {
270 extern void register_devices(SIM_DESC
);
271 register_devices(sd
);
275 /* start-sanitize-sky */
278 short i
[NUM_VU_INTEGER_REGS
];
279 int f
[NUM_VU_REGS
- NUM_VU_INTEGER_REGS
];
282 /* end-sanitize-sky */
284 /*---------------------------------------------------------------------------*/
285 /*-- GDB simulator interface ------------------------------------------------*/
286 /*---------------------------------------------------------------------------*/
289 sim_open (kind
, cb
, abfd
, argv
)
295 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
296 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
298 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
300 /* FIXME: watchpoints code shouldn't need this */
301 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
302 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
303 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
307 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
309 sim_add_option_table (sd
, NULL
, mips_options
);
311 /* Allocate core managed memory */
314 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
315 /* For compatibility with the old code - under this (at level one)
316 are the kernel spaces K0 & K1. Both of these map to a single
317 smaller sub region */
318 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
319 /* start-sanitize-sky */
321 /* end-sanitize-sky */
322 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
324 MEM_SIZE
, /* actual size */
326 /* start-sanitize-sky */
328 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
330 MEM_SIZE
, /* actual size */
332 0); /* add alias at 0x0000 */
334 /* end-sanitize-sky */
338 /* getopt will print the error message so we just have to exit if this fails.
339 FIXME: Hmmm... in the case of gdb we need getopt to call
341 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
343 /* Uninstall the modules to avoid memory leaks,
344 file descriptor leaks, etc. */
345 sim_module_uninstall (sd
);
349 /* check for/establish the a reference program image */
350 if (sim_analyze_program (sd
,
351 (STATE_PROG_ARGV (sd
) != NULL
352 ? *STATE_PROG_ARGV (sd
)
356 sim_module_uninstall (sd
);
360 /* Configure/verify the target byte order and other runtime
361 configuration options */
362 if (sim_config (sd
) != SIM_RC_OK
)
364 sim_module_uninstall (sd
);
368 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
370 /* Uninstall the modules to avoid memory leaks,
371 file descriptor leaks, etc. */
372 sim_module_uninstall (sd
);
376 /* verify assumptions the simulator made about the host type system.
377 This macro does not return if there is a problem */
378 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
379 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
381 /* This is NASTY, in that we are assuming the size of specific
385 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
388 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
389 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
390 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
391 else if ((rn
>= 33) && (rn
<= 37))
392 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
393 else if ((rn
== SRIDX
)
396 || ((rn
>= 72) && (rn
<= 89)))
397 cpu
->register_widths
[rn
] = 32;
399 cpu
->register_widths
[rn
] = 0;
401 /* start-sanitize-r5900 */
403 /* set the 5900 "upper" registers to 64 bits */
404 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
405 cpu
->register_widths
[rn
] = 64;
406 /* end-sanitize-r5900 */
408 /* start-sanitize-sky */
410 /* Now the VU registers */
411 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
412 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
413 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
415 /* Hack for now - to test gdb interface */
416 vu_regs
[0].i
[rn
] = rn
+ 0x100;
417 vu_regs
[1].i
[rn
] = rn
+ 0x200;
420 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
422 int first_vec_reg
= NUM_VU_INTEGER_REGS
+ 8;
424 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
425 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
427 /* Hack for now - to test gdb interface */
428 if( rn
< first_vec_reg
) {
429 f
= rn
- NUM_VU_INTEGER_REGS
+ 100.0;
430 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
431 f
= rn
- NUM_VU_INTEGER_REGS
+ 200.0;
432 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
435 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 1000.0;
436 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
437 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 2000.0;
438 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
442 /* end-sanitize-sky */
446 if (STATE
& simTRACE
)
450 /* Write the monitor trap address handlers into the monitor (eeprom)
451 address space. This can only be done once the target endianness
452 has been determined. */
455 /* Entry into the IDT monitor is via fixed address vectors, and
456 not using machine instructions. To avoid clashing with use of
457 the MIPS TRAP system, we place our own (simulator specific)
458 "undefined" instructions into the relevant vector slots. */
459 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
461 address_word vaddr
= (MONITOR_BASE
+ loop
);
462 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
464 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
466 /* The PMON monitor uses the same address space, but rather than
467 branching into it the address of a routine is loaded. We can
468 cheat for the moment, and direct the PMON routine to IDT style
469 instructions within the monitor space. This relies on the IDT
470 monitor not using the locations from 0xBFC00500 onwards as its
472 for (loop
= 0; (loop
< 24); loop
++)
474 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
475 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
491 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
493 case 8: /* cliexit */
496 case 11: /* flush_cache */
500 /* FIXME - should monitor_base be SIM_ADDR?? */
501 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
503 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
505 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
507 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
519 tracefh
= fopen(tracefile
,"wb+");
522 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
529 sim_close (sd
, quitting
)
534 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
537 /* "quitting" is non-zero if we cannot hang on errors */
539 /* Ensure that any resources allocated through the callback
540 mechanism are released: */
541 sim_io_shutdown (sd
);
544 if (tracefh
!= NULL
&& tracefh
!= stderr
)
549 /* FIXME - free SD */
556 sim_write (sd
,addr
,buffer
,size
)
559 unsigned char *buffer
;
563 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
565 /* Return the number of bytes written, or zero if error. */
567 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
570 /* We use raw read and write routines, since we do not want to count
571 the GDB memory accesses in our statistics gathering. */
573 for (index
= 0; index
< size
; index
++)
575 address_word vaddr
= (address_word
)addr
+ index
;
578 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
580 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
588 sim_read (sd
,addr
,buffer
,size
)
591 unsigned char *buffer
;
595 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
597 /* Return the number of bytes read, or zero if error. */
599 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
602 for (index
= 0; (index
< size
); index
++)
604 address_word vaddr
= (address_word
)addr
+ index
;
607 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
609 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
617 sim_store_register (sd
,rn
,memory
,length
)
620 unsigned char *memory
;
623 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
624 /* NOTE: gdb (the client) stores registers in target byte order
625 while the simulator uses host byte order */
627 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
630 /* Unfortunately this suffers from the same problem as the register
631 numbering one. We need to know what the width of each logical
632 register number is for the architecture being simulated. */
634 if (cpu
->register_widths
[rn
] == 0)
636 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
640 /* start-sanitize-r5900 */
641 if (rn
>= 90 && rn
< 90 + 32)
643 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
649 SA
= T2H_8(*(unsigned64
*)memory
);
651 case 122: /* FIXME */
652 LO1
= T2H_8(*(unsigned64
*)memory
);
654 case 123: /* FIXME */
655 HI1
= T2H_8(*(unsigned64
*)memory
);
658 /* end-sanitize-r5900 */
660 /* start-sanitize-sky */
662 if (rn
>= NUM_R5900_REGS
)
664 int size
= 4; /* Default register size */
666 rn
= rn
- NUM_R5900_REGS
;
668 if (rn
< NUM_VU_INTEGER_REGS
)
670 vu_regs
[0].i
[rn
] = T2H_2( *(unsigned short *) memory
);
673 else if( rn
< NUM_VU_REGS
)
674 vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
]
675 = T2H_4( *(unsigned int *) memory
);
677 rn
= rn
- NUM_VU_REGS
;
679 if( rn
< NUM_VU_INTEGER_REGS
)
681 vu_regs
[1].i
[rn
] = T2H_2( *(unsigned short *) memory
);
684 else if( rn
< NUM_VU_REGS
)
685 vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
]
686 = T2H_4( *(unsigned int *) memory
);
688 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
694 /* end-sanitize-sky */
696 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
698 if (cpu
->register_widths
[rn
] == 32)
700 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
705 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
710 if (cpu
->register_widths
[rn
] == 32)
712 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
717 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
723 sim_fetch_register (sd
,rn
,memory
,length
)
726 unsigned char *memory
;
729 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
730 /* NOTE: gdb (the client) stores registers in target byte order
731 while the simulator uses host byte order */
733 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
736 if (cpu
->register_widths
[rn
] == 0)
738 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
742 /* start-sanitize-r5900 */
743 if (rn
>= 90 && rn
< 90 + 32)
745 *(unsigned64
*)memory
= GPR1
[rn
- 90];
751 *((unsigned64
*)memory
) = H2T_8(SA
);
753 case 122: /* FIXME */
754 *((unsigned64
*)memory
) = H2T_8(LO1
);
756 case 123: /* FIXME */
757 *((unsigned64
*)memory
) = H2T_8(HI1
);
760 /* end-sanitize-r5900 */
762 /* start-sanitize-sky */
764 if (rn
>= NUM_R5900_REGS
)
766 int size
= 4; /* default register width */
768 rn
= rn
- NUM_R5900_REGS
;
770 if (rn
< NUM_VU_INTEGER_REGS
)
772 *((unsigned short *) memory
) = H2T_2( vu_regs
[0].i
[rn
] );
775 else if (rn
< NUM_VU_REGS
)
776 *((unsigned int *) memory
)
777 = H2T_4( vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
] );
780 rn
= rn
- NUM_VU_REGS
;
782 if (rn
< NUM_VU_INTEGER_REGS
)
784 (*(unsigned short *) memory
) = H2T_2( vu_regs
[1].i
[rn
] );
787 else if (rn
< NUM_VU_REGS
)
788 (*(unsigned int *) memory
)
789 = H2T_4( vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
] );
791 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
797 /* end-sanitize-sky */
799 /* Any floating point register */
800 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
802 if (cpu
->register_widths
[rn
] == 32)
804 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
809 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
814 if (cpu
->register_widths
[rn
] == 32)
816 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
821 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
828 sim_create_inferior (sd
, abfd
, argv
,env
)
836 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
844 /* override PC value set by ColdReset () */
846 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
848 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
849 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
853 #if 0 /* def DEBUG */
856 /* We should really place the argv slot values into the argument
857 registers, and onto the stack as required. However, this
858 assumes that we have a stack defined, which is not
859 necessarily true at the moment. */
861 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
862 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
863 printf("DBG: arg \"%s\"\n",*cptr
);
871 sim_do_command (sd
,cmd
)
875 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
876 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
880 /*---------------------------------------------------------------------------*/
881 /*-- Private simulator support interface ------------------------------------*/
882 /*---------------------------------------------------------------------------*/
884 /* Read a null terminated string from memory, return in a buffer */
893 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
895 buf
= NZALLOC (char, nr
+ 1);
896 sim_read (sd
, addr
, buf
, nr
);
900 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
902 sim_monitor (SIM_DESC sd
,
908 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
911 /* The IDT monitor actually allows two instructions per vector
912 slot. However, the simulator currently causes a trap on each
913 individual instruction. We cheat, and lose the bottom bit. */
916 /* The following callback functions are available, however the
917 monitor we are simulating does not make use of them: get_errno,
918 isatty, lseek, rename, system, time and unlink */
922 case 6: /* int open(char *path,int flags) */
924 char *path
= fetch_str (sd
, A0
);
925 V0
= sim_io_open (sd
, path
, (int)A1
);
930 case 7: /* int read(int file,char *ptr,int len) */
934 char *buf
= zalloc (nr
);
935 V0
= sim_io_read (sd
, fd
, buf
, nr
);
936 sim_write (sd
, A1
, buf
, nr
);
941 case 8: /* int write(int file,char *ptr,int len) */
945 char *buf
= zalloc (nr
);
946 sim_read (sd
, A1
, buf
, nr
);
947 V0
= sim_io_write (sd
, fd
, buf
, nr
);
952 case 10: /* int close(int file) */
954 V0
= sim_io_close (sd
, (int)A0
);
958 case 2: /* Densan monitor: char inbyte(int waitflag) */
960 if (A0
== 0) /* waitflag == NOWAIT */
961 V0
= (unsigned_word
)-1;
963 /* Drop through to case 11 */
965 case 11: /* char inbyte(void) */
968 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
970 sim_io_error(sd
,"Invalid return from character read");
971 V0
= (unsigned_word
)-1;
974 V0
= (unsigned_word
)tmp
;
978 case 3: /* Densan monitor: void co(char chr) */
979 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
981 char tmp
= (char)(A0
& 0xFF);
982 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
986 case 17: /* void _exit() */
988 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
989 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
990 (unsigned int)(A0
& 0xFFFFFFFF));
994 case 28 : /* PMON flush_cache */
997 case 55: /* void get_mem_info(unsigned int *ptr) */
998 /* in: A0 = pointer to three word memory location */
999 /* out: [A0 + 0] = size */
1000 /* [A0 + 4] = instruction cache size */
1001 /* [A0 + 8] = data cache size */
1003 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
1005 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
1006 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1010 case 158 : /* PMON printf */
1011 /* in: A0 = pointer to format string */
1012 /* A1 = optional argument 1 */
1013 /* A2 = optional argument 2 */
1014 /* A3 = optional argument 3 */
1016 /* The following is based on the PMON printf source */
1018 address_word s
= A0
;
1020 signed_word
*ap
= &A1
; /* 1st argument */
1021 /* This isn't the quickest way, since we call the host print
1022 routine for every character almost. But it does avoid
1023 having to allocate and manage a temporary string buffer. */
1024 /* TODO: Include check that we only use three arguments (A1,
1026 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1031 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1032 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1033 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1035 if (strchr ("dobxXulscefg%", s
))
1050 else if (c
>= '1' && c
<= '9')
1054 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1057 n
= (unsigned int)strtol(tmp
,NULL
,10);
1070 sim_io_printf (sd
, "%%");
1075 address_word p
= *ap
++;
1077 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1078 sim_io_printf(sd
, "%c", ch
);
1081 sim_io_printf(sd
,"(null)");
1084 sim_io_printf (sd
, "%c", (int)*ap
++);
1089 sim_read (sd
, s
++, &c
, 1);
1093 sim_read (sd
, s
++, &c
, 1);
1096 if (strchr ("dobxXu", c
))
1098 word64 lv
= (word64
) *ap
++;
1100 sim_io_printf(sd
,"<binary not supported>");
1103 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1105 sim_io_printf(sd
, tmp
, lv
);
1107 sim_io_printf(sd
, tmp
, (int)lv
);
1110 else if (strchr ("eEfgG", c
))
1112 double dbl
= *(double*)(ap
++);
1113 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1114 sim_io_printf (sd
, tmp
, dbl
);
1120 sim_io_printf(sd
, "%c", c
);
1126 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1127 reason
, pr_addr(cia
));
1133 /* Store a word into memory. */
1136 store_word (SIM_DESC sd
,
1145 if ((vaddr
& 3) != 0)
1146 SignalExceptionAddressStore ();
1149 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1152 const uword64 mask
= 7;
1156 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1157 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1158 memval
= ((uword64
) val
) << (8 * byte
);
1159 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1165 /* Load a word from memory. */
1168 load_word (SIM_DESC sd
,
1173 if ((vaddr
& 3) != 0)
1174 SignalExceptionAddressLoad ();
1180 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1183 const uword64 mask
= 0x7;
1184 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1185 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1189 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1190 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1192 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1193 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1200 /* Simulate the mips16 entry and exit pseudo-instructions. These
1201 would normally be handled by the reserved instruction exception
1202 code, but for ease of simulation we just handle them directly. */
1205 mips16_entry (SIM_DESC sd
,
1210 int aregs
, sregs
, rreg
;
1213 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1216 aregs
= (insn
& 0x700) >> 8;
1217 sregs
= (insn
& 0x0c0) >> 6;
1218 rreg
= (insn
& 0x020) >> 5;
1220 /* This should be checked by the caller. */
1229 /* This is the entry pseudo-instruction. */
1231 for (i
= 0; i
< aregs
; i
++)
1232 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1240 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1243 for (i
= 0; i
< sregs
; i
++)
1246 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1254 /* This is the exit pseudo-instruction. */
1261 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1264 for (i
= 0; i
< sregs
; i
++)
1267 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1272 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1276 FGR
[0] = WORD64LO (GPR
[4]);
1277 FPR_STATE
[0] = fmt_uninterpreted
;
1279 else if (aregs
== 6)
1281 FGR
[0] = WORD64LO (GPR
[5]);
1282 FGR
[1] = WORD64LO (GPR
[4]);
1283 FPR_STATE
[0] = fmt_uninterpreted
;
1284 FPR_STATE
[1] = fmt_uninterpreted
;
1293 /*-- trace support ----------------------------------------------------------*/
1295 /* The TRACE support is provided (if required) in the memory accessing
1296 routines. Since we are also providing the architecture specific
1297 features, the architecture simulation code can also deal with
1298 notifying the TRACE world of cache flushes, etc. Similarly we do
1299 not need to provide profiling support in the simulator engine,
1300 since we can sample in the instruction fetch control loop. By
1301 defining the TRACE manifest, we add tracing as a run-time
1305 /* Tracing by default produces "din" format (as required by
1306 dineroIII). Each line of such a trace file *MUST* have a din label
1307 and address field. The rest of the line is ignored, so comments can
1308 be included if desired. The first field is the label which must be
1309 one of the following values:
1314 3 escape record (treated as unknown access type)
1315 4 escape record (causes cache flush)
1317 The address field is a 32bit (lower-case) hexadecimal address
1318 value. The address should *NOT* be preceded by "0x".
1320 The size of the memory transfer is not important when dealing with
1321 cache lines (as long as no more than a cache line can be
1322 transferred in a single operation :-), however more information
1323 could be given following the dineroIII requirement to allow more
1324 complete memory and cache simulators to provide better
1325 results. i.e. the University of Pisa has a cache simulator that can
1326 also take bus size and speed as (variable) inputs to calculate
1327 complete system performance (a much more useful ability when trying
1328 to construct an end product, rather than a processor). They
1329 currently have an ARM version of their tool called ChARM. */
1333 dotrace (SIM_DESC sd
,
1341 if (STATE
& simTRACE
) {
1343 fprintf(tracefh
,"%d %s ; width %d ; ",
1347 va_start(ap
,comment
);
1348 vfprintf(tracefh
,comment
,ap
);
1350 fprintf(tracefh
,"\n");
1352 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1353 we may be generating 64bit ones, we should put the hi-32bits of the
1354 address into the comment field. */
1356 /* TODO: Provide a buffer for the trace lines. We can then avoid
1357 performing writes until the buffer is filled, or the file is
1360 /* NOTE: We could consider adding a comment field to the "din" file
1361 produced using type 3 markers (unknown access). This would then
1362 allow information about the program that the "din" is for, and
1363 the MIPs world that was being simulated, to be placed into the
1370 /*---------------------------------------------------------------------------*/
1371 /*-- simulator engine -------------------------------------------------------*/
1372 /*---------------------------------------------------------------------------*/
1375 ColdReset (SIM_DESC sd
)
1378 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1380 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1381 /* RESET: Fixed PC address: */
1382 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1383 /* The reset vector address is in the unmapped, uncached memory space. */
1385 SR
&= ~(status_SR
| status_TS
| status_RP
);
1386 SR
|= (status_ERL
| status_BEV
);
1388 /* Cheat and allow access to the complete register set immediately */
1389 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1390 && WITH_TARGET_WORD_BITSIZE
== 64)
1391 SR
|= status_FR
; /* 64bit registers */
1393 /* Ensure that any instructions with pending register updates are
1395 PENDING_INVALIDATE();
1397 /* Initialise the FPU registers to the unknown state */
1398 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1401 for (rn
= 0; (rn
< 32); rn
++)
1402 FPR_STATE
[rn
] = fmt_uninterpreted
;
1408 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1410 /* Translate a virtual address to a physical address and cache
1411 coherence algorithm describing the mechanism used to resolve the
1412 memory reference. Given the virtual address vAddr, and whether the
1413 reference is to Instructions ot Data (IorD), find the corresponding
1414 physical address (pAddr) and the cache coherence algorithm (CCA)
1415 used to resolve the reference. If the virtual address is in one of
1416 the unmapped address spaces the physical address and the CCA are
1417 determined directly by the virtual address. If the virtual address
1418 is in one of the mapped address spaces then the TLB is used to
1419 determine the physical address and access type; if the required
1420 translation is not present in the TLB or the desired access is not
1421 permitted the function fails and an exception is taken.
1423 NOTE: Normally (RAW == 0), when address translation fails, this
1424 function raises an exception and does not return. */
1427 address_translation (SIM_DESC sd
,
1433 address_word
*pAddr
,
1437 int res
= -1; /* TRUE : Assume good return */
1440 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1443 /* Check that the address is valid for this memory model */
1445 /* For a simple (flat) memory model, we simply pass virtual
1446 addressess through (mostly) unchanged. */
1447 vAddr
&= 0xFFFFFFFF;
1449 *pAddr
= vAddr
; /* default for isTARGET */
1450 *CCA
= Uncached
; /* not used for isHOST */
1455 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1457 /* Prefetch data from memory. Prefetch is an advisory instruction for
1458 which an implementation specific action is taken. The action taken
1459 may increase performance, but must not change the meaning of the
1460 program, or alter architecturally-visible state. */
1463 prefetch (SIM_DESC sd
,
1473 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1476 /* For our simple memory model we do nothing */
1480 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1482 /* Load a value from memory. Use the cache and main memory as
1483 specified in the Cache Coherence Algorithm (CCA) and the sort of
1484 access (IorD) to find the contents of AccessLength memory bytes
1485 starting at physical location pAddr. The data is returned in the
1486 fixed width naturally-aligned memory element (MemElem). The
1487 low-order two (or three) bits of the address and the AccessLength
1488 indicate which of the bytes within MemElem needs to be given to the
1489 processor. If the memory access type of the reference is uncached
1490 then only the referenced bytes are read from memory and valid
1491 within the memory element. If the access type is cached, and the
1492 data is not present in cache, an implementation specific size and
1493 alignment block of memory is read and loaded into the cache to
1494 satisfy a load reference. At a minimum, the block is the entire
1497 load_memory (SIM_DESC sd
,
1512 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1515 #if defined(WARN_MEM)
1516 if (CCA
!= uncached
)
1517 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1518 #endif /* WARN_MEM */
1520 /* If instruction fetch then we need to check that the two lo-order
1521 bits are zero, otherwise raise a InstructionFetch exception: */
1522 if ((IorD
== isINSTRUCTION
)
1523 && ((pAddr
& 0x3) != 0)
1524 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1525 SignalExceptionInstructionFetch ();
1527 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1529 /* In reality this should be a Bus Error */
1530 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1532 (LOADDRMASK
+ 1) << 2,
1537 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1540 /* Read the specified number of bytes from memory. Adjust for
1541 host/target byte ordering/ Align the least significant byte
1544 switch (AccessLength
)
1546 case AccessLength_QUADWORD
:
1548 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
, read_map
, pAddr
);
1549 value1
= VH8_16 (val
);
1550 value
= VL8_16 (val
);
1553 case AccessLength_DOUBLEWORD
:
1554 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1557 case AccessLength_SEPTIBYTE
:
1558 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1561 case AccessLength_SEXTIBYTE
:
1562 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1565 case AccessLength_QUINTIBYTE
:
1566 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1569 case AccessLength_WORD
:
1570 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1573 case AccessLength_TRIPLEBYTE
:
1574 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1577 case AccessLength_HALFWORD
:
1578 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1581 case AccessLength_BYTE
:
1582 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1590 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1591 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1594 /* See also store_memory. */
1595 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1598 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1599 shifted to the most significant byte position. */
1600 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1602 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1603 is already in the correct postition. */
1604 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1608 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1609 pr_uword64(value1
),pr_uword64(value
));
1613 if (memval1p
) *memval1p
= value1
;
1617 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1619 /* Store a value to memory. The specified data is stored into the
1620 physical location pAddr using the memory hierarchy (data caches and
1621 main memory) as specified by the Cache Coherence Algorithm
1622 (CCA). The MemElem contains the data for an aligned, fixed-width
1623 memory element (word for 32-bit processors, doubleword for 64-bit
1624 processors), though only the bytes that will actually be stored to
1625 memory need to be valid. The low-order two (or three) bits of pAddr
1626 and the AccessLength field indicates which of the bytes within the
1627 MemElem data should actually be stored; only these bytes in memory
1631 store_memory (SIM_DESC sd
,
1637 uword64 MemElem1
, /* High order 64 bits */
1642 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1645 #if defined(WARN_MEM)
1646 if (CCA
!= uncached
)
1647 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1648 #endif /* WARN_MEM */
1650 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1651 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1654 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1658 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1661 /* See also load_memory */
1662 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1665 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1666 shifted to the most significant byte position. */
1667 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1669 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1670 is already in the correct postition. */
1671 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1675 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1678 switch (AccessLength
)
1680 case AccessLength_QUADWORD
:
1682 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1683 sim_core_write_aligned_16 (cpu
, NULL_CIA
, write_map
, pAddr
, val
);
1686 case AccessLength_DOUBLEWORD
:
1687 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1688 write_map
, pAddr
, MemElem
);
1690 case AccessLength_SEPTIBYTE
:
1691 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1692 write_map
, pAddr
, MemElem
);
1694 case AccessLength_SEXTIBYTE
:
1695 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1696 write_map
, pAddr
, MemElem
);
1698 case AccessLength_QUINTIBYTE
:
1699 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1700 write_map
, pAddr
, MemElem
);
1702 case AccessLength_WORD
:
1703 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1704 write_map
, pAddr
, MemElem
);
1706 case AccessLength_TRIPLEBYTE
:
1707 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1708 write_map
, pAddr
, MemElem
);
1710 case AccessLength_HALFWORD
:
1711 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1712 write_map
, pAddr
, MemElem
);
1714 case AccessLength_BYTE
:
1715 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1716 write_map
, pAddr
, MemElem
);
1727 ifetch32 (SIM_DESC sd
,
1732 /* Copy the action of the LW instruction */
1733 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1734 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1737 unsigned32 instruction
;
1740 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1741 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1742 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1743 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1744 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1750 ifetch16 (SIM_DESC sd
,
1755 /* Copy the action of the LW instruction */
1756 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1757 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1760 unsigned16 instruction
;
1763 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1764 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1765 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1766 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1767 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1772 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1773 /* Order loads and stores to synchronise shared memory. Perform the
1774 action necessary to make the effects of groups of synchronizable
1775 loads and stores indicated by stype occur in the same order for all
1778 sync_operation (SIM_DESC sd
,
1784 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1789 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790 /* Signal an exception condition. This will result in an exception
1791 that aborts the instruction. The instruction operation pseudocode
1792 will never see a return from this function call. */
1795 signal_exception (SIM_DESC sd
,
1803 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1806 /* Ensure that any active atomic read/modify/write operation will fail: */
1809 switch (exception
) {
1810 /* TODO: For testing purposes I have been ignoring TRAPs. In
1811 reality we should either simulate them, or allow the user to
1812 ignore them at run-time.
1815 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1821 unsigned int instruction
;
1824 va_start(ap
,exception
);
1825 instruction
= va_arg(ap
,unsigned int);
1828 code
= (instruction
>> 6) & 0xFFFFF;
1830 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1831 code
, pr_addr(cia
));
1835 case DebugBreakPoint
:
1836 if (! (Debug
& Debug_DM
))
1842 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1843 DEPC
= cia
- 4; /* reference the branch instruction */
1847 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1851 Debug
|= Debug_DM
; /* in debugging mode */
1852 Debug
|= Debug_DBp
; /* raising a DBp exception */
1854 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1858 case ReservedInstruction
:
1861 unsigned int instruction
;
1862 va_start(ap
,exception
);
1863 instruction
= va_arg(ap
,unsigned int);
1865 /* Provide simple monitor support using ReservedInstruction
1866 exceptions. The following code simulates the fixed vector
1867 entry points into the IDT monitor by causing a simulator
1868 trap, performing the monitor operation, and returning to
1869 the address held in the $ra register (standard PCS return
1870 address). This means we only need to pre-load the vector
1871 space with suitable instruction values. For systems were
1872 actual trap instructions are used, we would not need to
1873 perform this magic. */
1874 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1876 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1877 /* NOTE: This assumes that a branch-and-link style
1878 instruction was used to enter the vector (which is the
1879 case with the current IDT monitor). */
1880 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1882 /* Look for the mips16 entry and exit instructions, and
1883 simulate a handler for them. */
1884 else if ((cia
& 1) != 0
1885 && (instruction
& 0xf81f) == 0xe809
1886 && (instruction
& 0x0c0) != 0x0c0)
1888 mips16_entry (SD
, CPU
, cia
, instruction
);
1889 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1891 /* else fall through to normal exception processing */
1892 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1897 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1899 /* Keep a copy of the current A0 in-case this is the program exit
1903 unsigned int instruction
;
1904 va_start(ap
,exception
);
1905 instruction
= va_arg(ap
,unsigned int);
1907 /* Check for our special terminating BREAK: */
1908 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1909 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1910 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1913 if (STATE
& simDELAYSLOT
)
1914 PC
= cia
- 4; /* reference the branch instruction */
1917 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1918 sim_stopped
, SIM_SIGTRAP
);
1921 /* Store exception code into current exception id variable (used
1924 /* TODO: If not simulating exceptions then stop the simulator
1925 execution. At the moment we always stop the simulation. */
1927 /* See figure 5-17 for an outline of the code below */
1928 if (! (SR
& status_EXL
))
1930 CAUSE
= (exception
<< 2);
1931 if (STATE
& simDELAYSLOT
)
1933 STATE
&= ~simDELAYSLOT
;
1935 EPC
= (cia
- 4); /* reference the branch instruction */
1939 /* FIXME: TLB et.al. */
1944 CAUSE
= (exception
<< 2);
1948 /* Store exception code into current exception id variable (used
1950 if (SR
& status_BEV
)
1951 PC
= (signed)0xBFC00200 + 0x180;
1953 PC
= (signed)0x80000000 + 0x180;
1955 switch ((CAUSE
>> 2) & 0x1F)
1958 /* Interrupts arrive during event processing, no need to
1962 case TLBModification
:
1967 case InstructionFetch
:
1969 /* The following is so that the simulator will continue from the
1970 exception address on breakpoint operations. */
1972 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1973 sim_stopped
, SIM_SIGBUS
);
1975 case ReservedInstruction
:
1976 case CoProcessorUnusable
:
1978 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1979 sim_stopped
, SIM_SIGILL
);
1981 case IntegerOverflow
:
1983 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1984 sim_stopped
, SIM_SIGFPE
);
1990 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1991 sim_stopped
, SIM_SIGTRAP
);
1995 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1996 "FATAL: Should not encounter a breakpoint\n");
1998 default : /* Unknown internal exception */
2000 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
2001 sim_stopped
, SIM_SIGABRT
);
2005 case SimulatorFault
:
2009 va_start(ap
,exception
);
2010 msg
= va_arg(ap
,char *);
2012 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2013 "FATAL: Simulator error \"%s\"\n",msg
);
2020 #if defined(WARN_RESULT)
2021 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2022 /* This function indicates that the result of the operation is
2023 undefined. However, this should not affect the instruction
2024 stream. All that is meant to happen is that the destination
2025 register is set to an undefined result. To keep the simulator
2026 simple, we just don't bother updating the destination register, so
2027 the overall result will be undefined. If desired we can stop the
2028 simulator by raising a pseudo-exception. */
2029 #define UndefinedResult() undefined_result (sd,cia)
2031 undefined_result(sd
,cia
)
2035 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
2036 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2041 #endif /* WARN_RESULT */
2044 cache_op (SIM_DESC sd
,
2050 unsigned int instruction
)
2052 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2053 static int icache_warning
= 1;
2054 static int dcache_warning
= 1;
2056 static int icache_warning
= 0;
2057 static int dcache_warning
= 0;
2060 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2061 enable bit in the Status Register is clear - a coprocessor
2062 unusable exception is taken. */
2064 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
2068 case 0: /* instruction cache */
2070 case 0: /* Index Invalidate */
2071 case 1: /* Index Load Tag */
2072 case 2: /* Index Store Tag */
2073 case 4: /* Hit Invalidate */
2075 case 6: /* Hit Writeback */
2076 if (!icache_warning
)
2078 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2084 SignalException(ReservedInstruction
,instruction
);
2089 case 1: /* data cache */
2091 case 0: /* Index Writeback Invalidate */
2092 case 1: /* Index Load Tag */
2093 case 2: /* Index Store Tag */
2094 case 3: /* Create Dirty */
2095 case 4: /* Hit Invalidate */
2096 case 5: /* Hit Writeback Invalidate */
2097 case 6: /* Hit Writeback */
2098 if (!dcache_warning
)
2100 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2106 SignalException(ReservedInstruction
,instruction
);
2111 default: /* unrecognised cache ID */
2112 SignalException(ReservedInstruction
,instruction
);
2119 /*-- FPU support routines ---------------------------------------------------*/
2121 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2122 formats conform to ANSI/IEEE Std 754-1985. */
2123 /* SINGLE precision floating:
2124 * seeeeeeeefffffffffffffffffffffff
2126 * e = 8bits = exponent
2127 * f = 23bits = fraction
2129 /* SINGLE precision fixed:
2130 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2132 * i = 31bits = integer
2134 /* DOUBLE precision floating:
2135 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2137 * e = 11bits = exponent
2138 * f = 52bits = fraction
2140 /* DOUBLE precision fixed:
2141 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2143 * i = 63bits = integer
2146 /* Extract sign-bit: */
2147 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2148 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2149 /* Extract biased exponent: */
2150 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2151 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2152 /* Extract unbiased Exponent: */
2153 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2154 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2155 /* Extract complete fraction field: */
2156 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2157 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2158 /* Extract numbered fraction bit: */
2159 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2160 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2162 /* Explicit QNaN values used when value required: */
2163 #define FPQNaN_SINGLE (0x7FBFFFFF)
2164 #define FPQNaN_WORD (0x7FFFFFFF)
2165 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2166 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2168 /* Explicit Infinity values used when required: */
2169 #define FPINF_SINGLE (0x7F800000)
2170 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2172 #if 1 /* def DEBUG */
2173 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2174 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2178 value_fpr (SIM_DESC sd
,
2187 /* Treat unused register values, as fixed-point 64bit values: */
2188 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2190 /* If request to read data as "uninterpreted", then use the current
2192 fmt
= FPR_STATE
[fpr
];
2197 /* For values not yet accessed, set to the desired format: */
2198 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2199 FPR_STATE
[fpr
] = fmt
;
2201 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2204 if (fmt
!= FPR_STATE
[fpr
]) {
2205 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2206 FPR_STATE
[fpr
] = fmt_unknown
;
2209 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2210 /* Set QNaN value: */
2213 value
= FPQNaN_SINGLE
;
2217 value
= FPQNaN_DOUBLE
;
2221 value
= FPQNaN_WORD
;
2225 value
= FPQNaN_LONG
;
2232 } else if (SizeFGR() == 64) {
2236 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2239 case fmt_uninterpreted
:
2253 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2256 case fmt_uninterpreted
:
2259 if ((fpr
& 1) == 0) { /* even registers only */
2260 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2262 SignalException(ReservedInstruction
,0);
2273 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2276 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2283 store_fpr (SIM_DESC sd
,
2293 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2296 if (SizeFGR() == 64) {
2298 case fmt_uninterpreted_32
:
2299 fmt
= fmt_uninterpreted
;
2302 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2303 FPR_STATE
[fpr
] = fmt
;
2306 case fmt_uninterpreted_64
:
2307 fmt
= fmt_uninterpreted
;
2308 case fmt_uninterpreted
:
2312 FPR_STATE
[fpr
] = fmt
;
2316 FPR_STATE
[fpr
] = fmt_unknown
;
2322 case fmt_uninterpreted_32
:
2323 fmt
= fmt_uninterpreted
;
2326 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2327 FPR_STATE
[fpr
] = fmt
;
2330 case fmt_uninterpreted_64
:
2331 fmt
= fmt_uninterpreted
;
2332 case fmt_uninterpreted
:
2335 if ((fpr
& 1) == 0) { /* even register number only */
2336 FGR
[fpr
+1] = (value
>> 32);
2337 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2338 FPR_STATE
[fpr
+ 1] = fmt
;
2339 FPR_STATE
[fpr
] = fmt
;
2341 FPR_STATE
[fpr
] = fmt_unknown
;
2342 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2343 SignalException(ReservedInstruction
,0);
2348 FPR_STATE
[fpr
] = fmt_unknown
;
2353 #if defined(WARN_RESULT)
2356 #endif /* WARN_RESULT */
2359 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2362 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2379 sim_fpu_32to (&wop
, op
);
2380 boolean
= sim_fpu_is_nan (&wop
);
2387 sim_fpu_64to (&wop
, op
);
2388 boolean
= sim_fpu_is_nan (&wop
);
2392 fprintf (stderr
, "Bad switch\n");
2397 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2411 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2418 sim_fpu_32to (&wop
, op
);
2419 boolean
= sim_fpu_is_infinity (&wop
);
2425 sim_fpu_64to (&wop
, op
);
2426 boolean
= sim_fpu_is_infinity (&wop
);
2430 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2435 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2449 /* Argument checking already performed by the FPCOMPARE code */
2452 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2455 /* The format type should already have been checked: */
2461 sim_fpu_32to (&wop1
, op1
);
2462 sim_fpu_32to (&wop2
, op2
);
2463 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2470 sim_fpu_64to (&wop1
, op1
);
2471 sim_fpu_64to (&wop2
, op2
);
2472 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2476 fprintf (stderr
, "Bad switch\n");
2481 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2495 /* Argument checking already performed by the FPCOMPARE code */
2498 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2501 /* The format type should already have been checked: */
2507 sim_fpu_32to (&wop1
, op1
);
2508 sim_fpu_32to (&wop2
, op2
);
2509 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2516 sim_fpu_64to (&wop1
, op1
);
2517 sim_fpu_64to (&wop2
, op2
);
2518 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2522 fprintf (stderr
, "Bad switch\n");
2527 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2534 AbsoluteValue(op
,fmt
)
2541 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2544 /* The format type should already have been checked: */
2550 sim_fpu_32to (&wop
, op
);
2551 sim_fpu_abs (&wop
, &wop
);
2552 sim_fpu_to32 (&ans
, &wop
);
2560 sim_fpu_64to (&wop
, op
);
2561 sim_fpu_abs (&wop
, &wop
);
2562 sim_fpu_to64 (&ans
, &wop
);
2567 fprintf (stderr
, "Bad switch\n");
2582 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2585 /* The format type should already have been checked: */
2591 sim_fpu_32to (&wop
, op
);
2592 sim_fpu_neg (&wop
, &wop
);
2593 sim_fpu_to32 (&ans
, &wop
);
2601 sim_fpu_64to (&wop
, op
);
2602 sim_fpu_neg (&wop
, &wop
);
2603 sim_fpu_to64 (&ans
, &wop
);
2608 fprintf (stderr
, "Bad switch\n");
2624 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2627 /* The registers must specify FPRs valid for operands of type
2628 "fmt". If they are not valid, the result is undefined. */
2630 /* The format type should already have been checked: */
2638 sim_fpu_32to (&wop1
, op1
);
2639 sim_fpu_32to (&wop2
, op2
);
2640 sim_fpu_add (&ans
, &wop1
, &wop2
);
2641 sim_fpu_to32 (&res
, &ans
);
2651 sim_fpu_64to (&wop1
, op1
);
2652 sim_fpu_64to (&wop2
, op2
);
2653 sim_fpu_add (&ans
, &wop1
, &wop2
);
2654 sim_fpu_to64 (&res
, &ans
);
2659 fprintf (stderr
, "Bad switch\n");
2664 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2679 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2682 /* The registers must specify FPRs valid for operands of type
2683 "fmt". If they are not valid, the result is undefined. */
2685 /* The format type should already have been checked: */
2693 sim_fpu_32to (&wop1
, op1
);
2694 sim_fpu_32to (&wop2
, op2
);
2695 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2696 sim_fpu_to32 (&res
, &ans
);
2706 sim_fpu_64to (&wop1
, op1
);
2707 sim_fpu_64to (&wop2
, op2
);
2708 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2709 sim_fpu_to64 (&res
, &ans
);
2714 fprintf (stderr
, "Bad switch\n");
2719 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2726 Multiply(op1
,op2
,fmt
)
2734 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2737 /* The registers must specify FPRs valid for operands of type
2738 "fmt". If they are not valid, the result is undefined. */
2740 /* The format type should already have been checked: */
2748 sim_fpu_32to (&wop1
, op1
);
2749 sim_fpu_32to (&wop2
, op2
);
2750 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2751 sim_fpu_to32 (&res
, &ans
);
2761 sim_fpu_64to (&wop1
, op1
);
2762 sim_fpu_64to (&wop2
, op2
);
2763 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2764 sim_fpu_to64 (&res
, &ans
);
2769 fprintf (stderr
, "Bad switch\n");
2774 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2789 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2792 /* The registers must specify FPRs valid for operands of type
2793 "fmt". If they are not valid, the result is undefined. */
2795 /* The format type should already have been checked: */
2803 sim_fpu_32to (&wop1
, op1
);
2804 sim_fpu_32to (&wop2
, op2
);
2805 sim_fpu_div (&ans
, &wop1
, &wop2
);
2806 sim_fpu_to32 (&res
, &ans
);
2816 sim_fpu_64to (&wop1
, op1
);
2817 sim_fpu_64to (&wop2
, op2
);
2818 sim_fpu_div (&ans
, &wop1
, &wop2
);
2819 sim_fpu_to64 (&res
, &ans
);
2824 fprintf (stderr
, "Bad switch\n");
2829 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2843 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2846 /* The registers must specify FPRs valid for operands of type
2847 "fmt". If they are not valid, the result is undefined. */
2849 /* The format type should already have been checked: */
2856 sim_fpu_32to (&wop
, op
);
2857 sim_fpu_inv (&ans
, &wop
);
2858 sim_fpu_to32 (&res
, &ans
);
2867 sim_fpu_64to (&wop
, op
);
2868 sim_fpu_inv (&ans
, &wop
);
2869 sim_fpu_to64 (&res
, &ans
);
2874 fprintf (stderr
, "Bad switch\n");
2879 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2893 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2896 /* The registers must specify FPRs valid for operands of type
2897 "fmt". If they are not valid, the result is undefined. */
2899 /* The format type should already have been checked: */
2906 sim_fpu_32to (&wop
, op
);
2907 sim_fpu_sqrt (&ans
, &wop
);
2908 sim_fpu_to32 (&res
, &ans
);
2917 sim_fpu_64to (&wop
, op
);
2918 sim_fpu_sqrt (&ans
, &wop
);
2919 sim_fpu_to64 (&res
, &ans
);
2924 fprintf (stderr
, "Bad switch\n");
2929 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2945 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2948 /* The registers must specify FPRs valid for operands of type
2949 "fmt". If they are not valid, the result is undefined. */
2951 /* The format type should already have been checked: */
2958 sim_fpu_32to (&wop1
, op1
);
2959 sim_fpu_32to (&wop2
, op2
);
2960 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2967 sim_fpu_64to (&wop1
, op1
);
2968 sim_fpu_64to (&wop2
, op2
);
2969 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2973 fprintf (stderr
, "Bad switch\n");
2979 case SIM_FPU_IS_SNAN
:
2980 case SIM_FPU_IS_QNAN
:
2982 case SIM_FPU_IS_NINF
:
2983 case SIM_FPU_IS_NNUMBER
:
2984 case SIM_FPU_IS_NDENORM
:
2985 case SIM_FPU_IS_NZERO
:
2986 result
= op2
; /* op1 - op2 < 0 */
2987 case SIM_FPU_IS_PINF
:
2988 case SIM_FPU_IS_PNUMBER
:
2989 case SIM_FPU_IS_PDENORM
:
2990 case SIM_FPU_IS_PZERO
:
2991 result
= op1
; /* op1 - op2 > 0 */
2993 fprintf (stderr
, "Bad switch\n");
2998 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3015 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3018 /* The registers must specify FPRs valid for operands of type
3019 "fmt". If they are not valid, the result is undefined. */
3021 /* The format type should already have been checked: */
3028 sim_fpu_32to (&wop1
, op1
);
3029 sim_fpu_32to (&wop2
, op2
);
3030 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3037 sim_fpu_64to (&wop1
, op1
);
3038 sim_fpu_64to (&wop2
, op2
);
3039 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3043 fprintf (stderr
, "Bad switch\n");
3049 case SIM_FPU_IS_SNAN
:
3050 case SIM_FPU_IS_QNAN
:
3052 case SIM_FPU_IS_NINF
:
3053 case SIM_FPU_IS_NNUMBER
:
3054 case SIM_FPU_IS_NDENORM
:
3055 case SIM_FPU_IS_NZERO
:
3056 result
= op1
; /* op1 - op2 < 0 */
3057 case SIM_FPU_IS_PINF
:
3058 case SIM_FPU_IS_PNUMBER
:
3059 case SIM_FPU_IS_PDENORM
:
3060 case SIM_FPU_IS_PZERO
:
3061 result
= op2
; /* op1 - op2 > 0 */
3063 fprintf (stderr
, "Bad switch\n");
3068 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3076 convert (SIM_DESC sd
,
3085 sim_fpu_round round
;
3086 unsigned32 result32
;
3087 unsigned64 result64
;
3090 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3096 /* Round result to nearest representable value. When two
3097 representable values are equally near, round to the value
3098 that has a least significant bit of zero (i.e. is even). */
3099 round
= sim_fpu_round_near
;
3102 /* Round result to the value closest to, and not greater in
3103 magnitude than, the result. */
3104 round
= sim_fpu_round_zero
;
3107 /* Round result to the value closest to, and not less than,
3109 round
= sim_fpu_round_up
;
3113 /* Round result to the value closest to, and not greater than,
3115 round
= sim_fpu_round_down
;
3119 fprintf (stderr
, "Bad switch\n");
3123 /* Convert the input to sim_fpu internal format */
3127 sim_fpu_64to (&wop
, op
);
3130 sim_fpu_32to (&wop
, op
);
3133 sim_fpu_i32to (&wop
, op
, round
);
3136 sim_fpu_i64to (&wop
, op
, round
);
3139 fprintf (stderr
, "Bad switch\n");
3143 /* Convert sim_fpu format into the output */
3144 /* The value WOP is converted to the destination format, rounding
3145 using mode RM. When the destination is a fixed-point format, then
3146 a source value of Infinity, NaN or one which would round to an
3147 integer outside the fixed point range then an IEEE Invalid
3148 Operation condition is raised. */
3152 sim_fpu_round_32 (&wop
, round
, 0);
3153 sim_fpu_to32 (&result32
, &wop
);
3154 result64
= result32
;
3157 sim_fpu_round_64 (&wop
, round
, 0);
3158 sim_fpu_to64 (&result64
, &wop
);
3161 sim_fpu_to32i (&result32
, &wop
, round
);
3162 result64
= result32
;
3165 sim_fpu_to64i (&result64
, &wop
, round
);
3169 fprintf (stderr
, "Bad switch\n");
3174 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
3181 /*-- co-processor support routines ------------------------------------------*/
3184 CoProcPresent(coproc_number
)
3185 unsigned int coproc_number
;
3187 /* Return TRUE if simulator provides a model for the given co-processor number */
3192 cop_lw (SIM_DESC sd
,
3197 unsigned int memword
)
3202 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3205 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3207 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3208 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3213 #if 0 /* this should be controlled by a configuration option */
3214 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3223 cop_ld (SIM_DESC sd
,
3230 switch (coproc_num
) {
3232 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3234 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3239 #if 0 /* this message should be controlled by a configuration option */
3240 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3249 cop_sw (SIM_DESC sd
,
3255 unsigned int value
= 0;
3260 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3263 hold
= FPR_STATE
[coproc_reg
];
3264 FPR_STATE
[coproc_reg
] = fmt_word
;
3265 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3266 FPR_STATE
[coproc_reg
] = hold
;
3271 #if 0 /* should be controlled by configuration option */
3272 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3281 cop_sd (SIM_DESC sd
,
3291 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3293 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3298 #if 0 /* should be controlled by configuration option */
3299 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3308 decode_coproc (SIM_DESC sd
,
3311 unsigned int instruction
)
3313 int coprocnum
= ((instruction
>> 26) & 3);
3317 case 0: /* standard CPU control and cache registers */
3319 int code
= ((instruction
>> 21) & 0x1F);
3320 /* R4000 Users Manual (second edition) lists the following CP0
3322 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3323 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3324 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3325 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3326 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3327 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3328 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3329 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3330 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3331 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3333 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3335 int rt
= ((instruction
>> 16) & 0x1F);
3336 int rd
= ((instruction
>> 11) & 0x1F);
3338 switch (rd
) /* NOTEs: Standard CP0 registers */
3340 /* 0 = Index R4000 VR4100 VR4300 */
3341 /* 1 = Random R4000 VR4100 VR4300 */
3342 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3343 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3344 /* 4 = Context R4000 VR4100 VR4300 */
3345 /* 5 = PageMask R4000 VR4100 VR4300 */
3346 /* 6 = Wired R4000 VR4100 VR4300 */
3347 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3348 /* 9 = Count R4000 VR4100 VR4300 */
3349 /* 10 = EntryHi R4000 VR4100 VR4300 */
3350 /* 11 = Compare R4000 VR4100 VR4300 */
3351 /* 12 = SR R4000 VR4100 VR4300 */
3358 /* 13 = Cause R4000 VR4100 VR4300 */
3365 /* 14 = EPC R4000 VR4100 VR4300 */
3366 /* 15 = PRId R4000 VR4100 VR4300 */
3367 #ifdef SUBTARGET_R3900
3376 /* 16 = Config R4000 VR4100 VR4300 */
3379 GPR
[rt
] = C0_CONFIG
;
3381 C0_CONFIG
= GPR
[rt
];
3384 #ifdef SUBTARGET_R3900
3393 /* 17 = LLAddr R4000 VR4100 VR4300 */
3395 /* 18 = WatchLo R4000 VR4100 VR4300 */
3396 /* 19 = WatchHi R4000 VR4100 VR4300 */
3397 /* 20 = XContext R4000 VR4100 VR4300 */
3398 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3399 /* 27 = CacheErr R4000 VR4100 */
3400 /* 28 = TagLo R4000 VR4100 VR4300 */
3401 /* 29 = TagHi R4000 VR4100 VR4300 */
3402 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3403 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3404 /* CPR[0,rd] = GPR[rt]; */
3407 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3409 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3412 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3415 if (SR
& status_ERL
)
3417 /* Oops, not yet available */
3418 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3428 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3432 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3440 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3441 /* TODO: When executing an ERET or RFE instruction we should
3442 clear LLBIT, to ensure that any out-standing atomic
3443 read/modify/write sequence fails. */
3447 case 2: /* undefined co-processor */
3448 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3451 case 1: /* should not occur (FPU co-processor) */
3452 case 3: /* should not occur (FPU co-processor) */
3453 SignalException(ReservedInstruction
,instruction
);
3460 /*-- instruction simulation -------------------------------------------------*/
3462 /* When the IGEN simulator is being built, the function below is be
3463 replaced by a generated version. However, WITH_IGEN == 2 indicates
3464 that the fubction below should be compiled but under a different
3465 name (to allow backward compatibility) */
3467 #if (WITH_IGEN != 1)
3469 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3471 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3474 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3477 int next_cpu_nr
; /* ignore */
3478 int nr_cpus
; /* ignore */
3479 int siggnal
; /* ignore */
3481 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3482 #if !defined(FASTSIM)
3483 unsigned int pipeline_count
= 1;
3487 if (STATE_MEMORY (sd
) == NULL
) {
3488 printf("DBG: simulate() entered with no memory\n");
3493 #if 0 /* Disabled to check that everything works OK */
3494 /* The VR4300 seems to sign-extend the PC on its first
3495 access. However, this may just be because it is currently
3496 configured in 32bit mode. However... */
3497 PC
= SIGNEXTEND(PC
,32);
3500 /* main controlling loop */
3502 /* vaddr is slowly being replaced with cia - current instruction
3504 address_word cia
= (uword64
)PC
;
3505 address_word vaddr
= cia
;
3508 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3512 printf("DBG: state = 0x%08X :",state
);
3513 if (state
& simHALTEX
) printf(" simHALTEX");
3514 if (state
& simHALTIN
) printf(" simHALTIN");
3519 DSSTATE
= (STATE
& simDELAYSLOT
);
3522 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3525 /* Fetch the next instruction from the simulator memory: */
3526 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3527 if ((vaddr
& 1) == 0) {
3528 /* Copy the action of the LW instruction */
3529 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3530 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3533 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3534 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3535 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3536 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3538 /* Copy the action of the LH instruction */
3539 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3540 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3543 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3544 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3545 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3546 paddr
& ~ (uword64
) 1,
3547 vaddr
, isINSTRUCTION
, isREAL
);
3548 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3549 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3552 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3557 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3560 /* This is required by exception processing, to ensure that we can
3561 cope with exceptions in the delay slots of branches that may
3562 already have changed the PC. */
3563 if ((vaddr
& 1) == 0)
3564 PC
+= 4; /* increment ready for the next fetch */
3567 /* NOTE: If we perform a delay slot change to the PC, this
3568 increment is not requuired. However, it would make the
3569 simulator more complicated to try and avoid this small hit. */
3571 /* Currently this code provides a simple model. For more
3572 complicated models we could perform exception status checks at
3573 this point, and set the simSTOP state as required. This could
3574 also include processing any hardware interrupts raised by any
3575 I/O model attached to the simulator context.
3577 Support for "asynchronous" I/O events within the simulated world
3578 could be providing by managing a counter, and calling a I/O
3579 specific handler when a particular threshold is reached. On most
3580 architectures a decrement and check for zero operation is
3581 usually quicker than an increment and compare. However, the
3582 process of managing a known value decrement to zero, is higher
3583 than the cost of using an explicit value UINT_MAX into the
3584 future. Which system is used will depend on how complicated the
3585 I/O model is, and how much it is likely to affect the simulator
3588 If events need to be scheduled further in the future than
3589 UINT_MAX event ticks, then the I/O model should just provide its
3590 own counter, triggered from the event system. */
3592 /* MIPS pipeline ticks. To allow for future support where the
3593 pipeline hit of individual instructions is known, this control
3594 loop manages a "pipeline_count" variable. It is initialised to
3595 1 (one), and will only be changed by the simulator engine when
3596 executing an instruction. If the engine does not have access to
3597 pipeline cycle count information then all instructions will be
3598 treated as using a single cycle. NOTE: A standard system is not
3599 provided by the default simulator because different MIPS
3600 architectures have different cycle counts for the same
3603 [NOTE: pipeline_count has been replaced the event queue] */
3605 /* shuffle the floating point status pipeline state */
3606 ENGINE_ISSUE_PREFIX_HOOK();
3608 /* NOTE: For multi-context simulation environments the "instruction"
3609 variable should be local to this routine. */
3611 /* Shorthand accesses for engine. Note: If we wanted to use global
3612 variables (and a single-threaded simulator engine), then we can
3613 create the actual variables with these names. */
3615 if (!(STATE
& simSKIPNEXT
)) {
3616 /* Include the simulator engine */
3617 #include "oengine.c"
3618 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3619 #error "Mismatch between run-time simulator code and simulation engine"
3621 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3622 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3624 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3625 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3628 #if defined(WARN_LOHI)
3629 /* Decrement the HI/LO validity ticks */
3634 /* start-sanitize-r5900 */
3639 /* end-sanitize-r5900 */
3640 #endif /* WARN_LOHI */
3642 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3643 should check for it being changed. It is better doing it here,
3644 than within the simulator, since it will help keep the simulator
3647 #if defined(WARN_ZERO)
3648 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3649 #endif /* WARN_ZERO */
3650 ZERO
= 0; /* reset back to zero before next instruction */
3652 } else /* simSKIPNEXT check */
3653 STATE
&= ~simSKIPNEXT
;
3655 /* If the delay slot was active before the instruction is
3656 executed, then update the PC to its new value: */
3659 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3668 #if !defined(FASTSIM)
3669 if (sim_events_tickn (sd
, pipeline_count
))
3671 /* cpu->cia = cia; */
3672 sim_events_process (sd
);
3675 if (sim_events_tick (sd
))
3677 /* cpu->cia = cia; */
3678 sim_events_process (sd
);
3680 #endif /* FASTSIM */
3686 /* This code copied from gdb's utils.c. Would like to share this code,
3687 but don't know of a common place where both could get to it. */
3689 /* Temporary storage using circular buffer */
3695 static char buf
[NUMCELLS
][CELLSIZE
];
3697 if (++cell
>=NUMCELLS
) cell
=0;
3701 /* Print routines to handle variable size regs, etc */
3703 /* Eliminate warning from compiler on 32-bit systems */
3704 static int thirty_two
= 32;
3710 char *paddr_str
=get_cell();
3711 switch (sizeof(addr
))
3714 sprintf(paddr_str
,"%08lx%08lx",
3715 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3718 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3721 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3724 sprintf(paddr_str
,"%x",addr
);
3733 char *paddr_str
=get_cell();
3734 sprintf(paddr_str
,"%08lx%08lx",
3735 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3741 pending_tick (SIM_DESC sd
,
3746 sim_io_printf (sd
, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN
, PENDING_OUT
, PENDING_TOTAL
);
3747 if (PENDING_OUT
!= PENDING_IN
)
3750 int index
= PENDING_OUT
;
3751 int total
= PENDING_TOTAL
;
3752 if (PENDING_TOTAL
== 0)
3753 sim_engine_abort (SD
, CPU
, cia
, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3754 for (loop
= 0; (loop
< total
); loop
++)
3756 if (PENDING_SLOT_DEST
[index
] != NULL
)
3758 PENDING_SLOT_DELAY
[index
] -= 1;
3759 if (PENDING_SLOT_DELAY
[index
] == 0)
3761 if (PENDING_SLOT_BIT
[index
] >= 0)
3762 switch (PENDING_SLOT_SIZE
[index
])
3765 if (PENDING_SLOT_VALUE
[index
])
3766 *(unsigned32
*)PENDING_SLOT_DEST
[index
] |=
3767 BIT32 (PENDING_SLOT_BIT
[index
]);
3769 *(unsigned32
*)PENDING_SLOT_DEST
[index
] &=
3770 BIT32 (PENDING_SLOT_BIT
[index
]);
3773 if (PENDING_SLOT_VALUE
[index
])
3774 *(unsigned64
*)PENDING_SLOT_DEST
[index
] |=
3775 BIT64 (PENDING_SLOT_BIT
[index
]);
3777 *(unsigned64
*)PENDING_SLOT_DEST
[index
] &=
3778 BIT64 (PENDING_SLOT_BIT
[index
]);
3783 switch (PENDING_SLOT_SIZE
[index
])
3786 *(unsigned32
*)PENDING_SLOT_DEST
[index
] =
3787 PENDING_SLOT_VALUE
[index
];
3790 *(unsigned64
*)PENDING_SLOT_DEST
[index
] =
3791 PENDING_SLOT_VALUE
[index
];
3795 if (PENDING_OUT
== index
)
3797 PENDING_SLOT_DEST
[index
] = NULL
;
3798 PENDING_OUT
= (PENDING_OUT
+ 1) % PSLOTS
;
3803 index
= (index
+ 1) % PSLOTS
;
3807 /*---------------------------------------------------------------------------*/
3808 /*> EOF interp.c <*/