projects / binutils-gdb.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Define CPU_INDEX. Initialize.
[binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Author$
18 $Date$
19
20 NOTEs:
21
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
25 code on the hardware.
26
27 */
28
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
33 #define TRACE (1)
34 #endif
35
36 #include "bfd.h"
37 #include "sim-main.h"
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
41
42 #include "config.h"
43
44 #include <stdio.h>
45 #include <stdarg.h>
46 #include <ansidecl.h>
47 #include <ctype.h>
48 #include <limits.h>
49 #include <math.h>
50 #ifdef HAVE_STDLIB_H
51 #include <stdlib.h>
52 #endif
53 #ifdef HAVE_STRING_H
54 #include <string.h>
55 #else
56 #ifdef HAVE_STRINGS_H
57 #include <strings.h>
58 #endif
59 #endif
60
61 #include "getopt.h"
62 #include "libiberty.h"
63 #include "bfd.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
66
67 #include "sysdep.h"
68
69 #ifndef PARAMS
70 #define PARAMS(x)
71 #endif
72
73 char* pr_addr PARAMS ((SIM_ADDR addr));
74 char* pr_uword64 PARAMS ((uword64 addr));
75
76
77 /* Get the simulator engine description, without including the code: */
78 #if (WITH_IGEN)
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
80 #else
81 #define SIM_MANIFESTS
82 #include "oengine.c"
83 #undef SIM_MANIFESTS
84 #endif
85
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
87 #define SD sd
88 #define CPU cpu
89
90
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
96
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
99
100
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
105
106
107
108
109
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
113
114 static void ColdReset PARAMS((SIM_DESC sd));
115
116 /*---------------------------------------------------------------------------*/
117
118
119
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
124 }
125
126 #define JALDELAYSLOT() {\
127 DELAYSLOT ();\
128 STATE |= simJALDELAYSLOT;\
129 }
130
131 #define NULLIFY() {\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
134 }
135
136 #define CANCELDELAYSLOT() {\
137 DSSTATE = 0;\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
139 }
140
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
143
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
151 /* start-sanitize-sky */
152 #ifdef TARGET_SKY
153 #undef MEM_SIZE
154 #define MEM_SIZE (16 << 20) /* 16 MB */
155 #endif
156 /* end-sanitize-sky */
157
158 #if defined(TRACE)
159 static char *tracefile = "trace.din"; /* default filename for trace log */
160 FILE *tracefh = NULL;
161 static void open_trace PARAMS((SIM_DESC sd));
162 #endif /* TRACE */
163
164 static DECLARE_OPTION_HANDLER (mips_option_handler);
165
166 #define OPTION_DINERO_TRACE 200
167 #define OPTION_DINERO_FILE 201
168
169 static SIM_RC
170 mips_option_handler (sd, cpu, opt, arg, is_command)
171 SIM_DESC sd;
172 sim_cpu *cpu;
173 int opt;
174 char *arg;
175 int is_command;
176 {
177 int cpu_nr;
178 switch (opt)
179 {
180 case OPTION_DINERO_TRACE: /* ??? */
181 #if defined(TRACE)
182 /* Eventually the simTRACE flag could be treated as a toggle, to
183 allow external control of the program points being traced
184 (i.e. only from main onwards, excluding the run-time setup,
185 etc.). */
186 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
187 {
188 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
189 if (arg == NULL)
190 STATE |= simTRACE;
191 else if (strcmp (arg, "yes") == 0)
192 STATE |= simTRACE;
193 else if (strcmp (arg, "no") == 0)
194 STATE &= ~simTRACE;
195 else if (strcmp (arg, "on") == 0)
196 STATE |= simTRACE;
197 else if (strcmp (arg, "off") == 0)
198 STATE &= ~simTRACE;
199 else
200 {
201 fprintf (stderr, "Unreconized dinero-trace option `%s'\n", arg);
202 return SIM_RC_FAIL;
203 }
204 }
205 return SIM_RC_OK;
206 #else /* !TRACE */
207 fprintf(stderr,"\
208 Simulator constructed without dinero tracing support (for performance).\n\
209 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
210 return SIM_RC_FAIL;
211 #endif /* !TRACE */
212
213 case OPTION_DINERO_FILE:
214 #if defined(TRACE)
215 if (optarg != NULL) {
216 char *tmp;
217 tmp = (char *)malloc(strlen(optarg) + 1);
218 if (tmp == NULL)
219 {
220 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
221 return SIM_RC_FAIL;
222 }
223 else {
224 strcpy(tmp,optarg);
225 tracefile = tmp;
226 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
227 }
228 }
229 #endif /* TRACE */
230 return SIM_RC_OK;
231
232 }
233
234 return SIM_RC_OK;
235 }
236
237 static const OPTION mips_options[] =
238 {
239 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
240 '\0', "on|off", "Enable dinero tracing",
241 mips_option_handler },
242 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
243 '\0', "FILE", "Write dinero trace to FILE",
244 mips_option_handler },
245 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
246 };
247
248
249 int interrupt_pending;
250
251 static void
252 interrupt_event (SIM_DESC sd, void *data)
253 {
254 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
255 if (SR & status_IE)
256 {
257 interrupt_pending = 0;
258 SignalExceptionInterrupt ();
259 }
260 else if (!interrupt_pending)
261 sim_events_schedule (sd, 1, interrupt_event, data);
262 }
263
264
265 /*---------------------------------------------------------------------------*/
266 /*-- Device registration hook -----------------------------------------------*/
267 /*---------------------------------------------------------------------------*/
268 static void device_init(SIM_DESC sd) {
269 #ifdef DEVICE_INIT
270 extern void register_devices(SIM_DESC);
271 register_devices(sd);
272 #endif
273 }
274
275 /* start-sanitize-sky */
276 #ifdef TARGET_SKY
277 static struct {
278 short i[NUM_VU_INTEGER_REGS];
279 int f[NUM_VU_REGS - NUM_VU_INTEGER_REGS];
280 } vu_regs[2];
281 #endif
282 /* end-sanitize-sky */
283
284 /*---------------------------------------------------------------------------*/
285 /*-- GDB simulator interface ------------------------------------------------*/
286 /*---------------------------------------------------------------------------*/
287
288 SIM_DESC
289 sim_open (kind, cb, abfd, argv)
290 SIM_OPEN_KIND kind;
291 host_callback *cb;
292 struct _bfd *abfd;
293 char **argv;
294 {
295 SIM_DESC sd = sim_state_alloc (kind, cb);
296 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
297
298 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
299
300 /* FIXME: watchpoints code shouldn't need this */
301 STATE_WATCHPOINTS (sd)->pc = &(PC);
302 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
303 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
304
305 STATE = 0;
306
307 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
308 return 0;
309 sim_add_option_table (sd, NULL, mips_options);
310
311 /* Allocate core managed memory */
312
313 /* the monitor */
314 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
315 /* For compatibility with the old code - under this (at level one)
316 are the kernel spaces K0 & K1. Both of these map to a single
317 smaller sub region */
318 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
319 /* start-sanitize-sky */
320 #ifndef TARGET_SKY
321 /* end-sanitize-sky */
322 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
323 K1BASE, K0SIZE,
324 MEM_SIZE, /* actual size */
325 K0BASE);
326 /* start-sanitize-sky */
327 #else
328 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
329 K1BASE, K0SIZE,
330 MEM_SIZE, /* actual size */
331 K0BASE,
332 0); /* add alias at 0x0000 */
333 #endif
334 /* end-sanitize-sky */
335
336 device_init(sd);
337
338 /* getopt will print the error message so we just have to exit if this fails.
339 FIXME: Hmmm... in the case of gdb we need getopt to call
340 print_filtered. */
341 if (sim_parse_args (sd, argv) != SIM_RC_OK)
342 {
343 /* Uninstall the modules to avoid memory leaks,
344 file descriptor leaks, etc. */
345 sim_module_uninstall (sd);
346 return 0;
347 }
348
349 /* check for/establish the a reference program image */
350 if (sim_analyze_program (sd,
351 (STATE_PROG_ARGV (sd) != NULL
352 ? *STATE_PROG_ARGV (sd)
353 : NULL),
354 abfd) != SIM_RC_OK)
355 {
356 sim_module_uninstall (sd);
357 return 0;
358 }
359
360 /* Configure/verify the target byte order and other runtime
361 configuration options */
362 if (sim_config (sd) != SIM_RC_OK)
363 {
364 sim_module_uninstall (sd);
365 return 0;
366 }
367
368 if (sim_post_argv_init (sd) != SIM_RC_OK)
369 {
370 /* Uninstall the modules to avoid memory leaks,
371 file descriptor leaks, etc. */
372 sim_module_uninstall (sd);
373 return 0;
374 }
375
376 /* verify assumptions the simulator made about the host type system.
377 This macro does not return if there is a problem */
378 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
379 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
380
381 /* This is NASTY, in that we are assuming the size of specific
382 registers: */
383 {
384 int rn;
385 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
386 {
387 if (rn < 32)
388 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
389 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
390 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
391 else if ((rn >= 33) && (rn <= 37))
392 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
393 else if ((rn == SRIDX)
394 || (rn == FCR0IDX)
395 || (rn == FCR31IDX)
396 || ((rn >= 72) && (rn <= 89)))
397 cpu->register_widths[rn] = 32;
398 else
399 cpu->register_widths[rn] = 0;
400 }
401 /* start-sanitize-r5900 */
402
403 /* set the 5900 "upper" registers to 64 bits */
404 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
405 cpu->register_widths[rn] = 64;
406 /* end-sanitize-r5900 */
407
408 /* start-sanitize-sky */
409 #ifdef TARGET_SKY
410 /* Now the VU registers */
411 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
412 cpu->register_widths[rn + NUM_R5900_REGS] = 16;
413 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
414
415 /* Hack for now - to test gdb interface */
416 vu_regs[0].i[rn] = rn + 0x100;
417 vu_regs[1].i[rn] = rn + 0x200;
418 }
419
420 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
421 float f;
422 int first_vec_reg = NUM_VU_INTEGER_REGS + 8;
423
424 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
425 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
426
427 /* Hack for now - to test gdb interface */
428 if( rn < first_vec_reg ) {
429 f = rn - NUM_VU_INTEGER_REGS + 100.0;
430 vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
431 f = rn - NUM_VU_INTEGER_REGS + 200.0;
432 vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
433 }
434 else {
435 f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 1000.0;
436 vu_regs[0].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
437 f = (rn - first_vec_reg)/4 + (rn - first_vec_reg)%4 + 2000.0;
438 vu_regs[1].f[rn-NUM_VU_INTEGER_REGS] = *((unsigned *) &f);
439 }
440 }
441 #endif
442 /* end-sanitize-sky */
443 }
444
445 #if defined(TRACE)
446 if (STATE & simTRACE)
447 open_trace(sd);
448 #endif /* TRACE */
449
450 /* Write the monitor trap address handlers into the monitor (eeprom)
451 address space. This can only be done once the target endianness
452 has been determined. */
453 {
454 unsigned loop;
455 /* Entry into the IDT monitor is via fixed address vectors, and
456 not using machine instructions. To avoid clashing with use of
457 the MIPS TRAP system, we place our own (simulator specific)
458 "undefined" instructions into the relevant vector slots. */
459 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
460 {
461 address_word vaddr = (MONITOR_BASE + loop);
462 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
463 H2T (insn);
464 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
465 }
466 /* The PMON monitor uses the same address space, but rather than
467 branching into it the address of a routine is loaded. We can
468 cheat for the moment, and direct the PMON routine to IDT style
469 instructions within the monitor space. This relies on the IDT
470 monitor not using the locations from 0xBFC00500 onwards as its
471 entry points.*/
472 for (loop = 0; (loop < 24); loop++)
473 {
474 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
475 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
476 switch (loop)
477 {
478 case 0: /* read */
479 value = 7;
480 break;
481 case 1: /* write */
482 value = 8;
483 break;
484 case 2: /* open */
485 value = 6;
486 break;
487 case 3: /* close */
488 value = 10;
489 break;
490 case 5: /* printf */
491 value = ((0x500 - 16) / 8); /* not an IDT reason code */
492 break;
493 case 8: /* cliexit */
494 value = 17;
495 break;
496 case 11: /* flush_cache */
497 value = 28;
498 break;
499 }
500 /* FIXME - should monitor_base be SIM_ADDR?? */
501 value = ((unsigned int)MONITOR_BASE + (value * 8));
502 H2T (value);
503 sim_write (sd, vaddr, (char *)&value, sizeof (value));
504
505 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
506 vaddr -= 0x300;
507 sim_write (sd, vaddr, (char *)&value, sizeof (value));
508 }
509 }
510
511 return sd;
512 }
513
514 #if defined(TRACE)
515 static void
516 open_trace(sd)
517 SIM_DESC sd;
518 {
519 tracefh = fopen(tracefile,"wb+");
520 if (tracefh == NULL)
521 {
522 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
523 tracefh = stderr;
524 }
525 }
526 #endif /* TRACE */
527
528 void
529 sim_close (sd, quitting)
530 SIM_DESC sd;
531 int quitting;
532 {
533 #ifdef DEBUG
534 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
535 #endif
536
537 /* "quitting" is non-zero if we cannot hang on errors */
538
539 /* Ensure that any resources allocated through the callback
540 mechanism are released: */
541 sim_io_shutdown (sd);
542
543 #if defined(TRACE)
544 if (tracefh != NULL && tracefh != stderr)
545 fclose(tracefh);
546 tracefh = NULL;
547 #endif /* TRACE */
548
549 /* FIXME - free SD */
550
551 return;
552 }
553
554
555 int
556 sim_write (sd,addr,buffer,size)
557 SIM_DESC sd;
558 SIM_ADDR addr;
559 unsigned char *buffer;
560 int size;
561 {
562 int index;
563 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
564
565 /* Return the number of bytes written, or zero if error. */
566 #ifdef DEBUG
567 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
568 #endif
569
570 /* We use raw read and write routines, since we do not want to count
571 the GDB memory accesses in our statistics gathering. */
572
573 for (index = 0; index < size; index++)
574 {
575 address_word vaddr = (address_word)addr + index;
576 address_word paddr;
577 int cca;
578 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
579 break;
580 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
581 break;
582 }
583
584 return(index);
585 }
586
587 int
588 sim_read (sd,addr,buffer,size)
589 SIM_DESC sd;
590 SIM_ADDR addr;
591 unsigned char *buffer;
592 int size;
593 {
594 int index;
595 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
596
597 /* Return the number of bytes read, or zero if error. */
598 #ifdef DEBUG
599 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
600 #endif /* DEBUG */
601
602 for (index = 0; (index < size); index++)
603 {
604 address_word vaddr = (address_word)addr + index;
605 address_word paddr;
606 int cca;
607 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
608 break;
609 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
610 break;
611 }
612
613 return(index);
614 }
615
616 int
617 sim_store_register (sd,rn,memory,length)
618 SIM_DESC sd;
619 int rn;
620 unsigned char *memory;
621 int length;
622 {
623 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
624 /* NOTE: gdb (the client) stores registers in target byte order
625 while the simulator uses host byte order */
626 #ifdef DEBUG
627 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
628 #endif /* DEBUG */
629
630 /* Unfortunately this suffers from the same problem as the register
631 numbering one. We need to know what the width of each logical
632 register number is for the architecture being simulated. */
633
634 if (cpu->register_widths[rn] == 0)
635 {
636 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
637 return 0;
638 }
639
640 /* start-sanitize-r5900 */
641 if (rn >= 90 && rn < 90 + 32)
642 {
643 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
644 return 8;
645 }
646 switch (rn)
647 {
648 case REGISTER_SA:
649 SA = T2H_8(*(unsigned64*)memory);
650 return 8;
651 case 122: /* FIXME */
652 LO1 = T2H_8(*(unsigned64*)memory);
653 return 8;
654 case 123: /* FIXME */
655 HI1 = T2H_8(*(unsigned64*)memory);
656 return 8;
657 }
658 /* end-sanitize-r5900 */
659
660 /* start-sanitize-sky */
661 #ifdef TARGET_SKY
662 if (rn >= NUM_R5900_REGS)
663 {
664 int size = 4; /* Default register size */
665
666 rn = rn - NUM_R5900_REGS;
667
668 if (rn < NUM_VU_INTEGER_REGS)
669 {
670 vu_regs[0].i[rn] = T2H_2( *(unsigned short *) memory );
671 size = 2;
672 }
673 else if( rn < NUM_VU_REGS )
674 vu_regs[0].f[rn - NUM_VU_INTEGER_REGS]
675 = T2H_4( *(unsigned int *) memory );
676 else {
677 rn = rn - NUM_VU_REGS;
678
679 if( rn < NUM_VU_INTEGER_REGS )
680 {
681 vu_regs[1].i[rn] = T2H_2( *(unsigned short *) memory );
682 size = 2;
683 }
684 else if( rn < NUM_VU_REGS )
685 vu_regs[1].f[rn - NUM_VU_INTEGER_REGS]
686 = T2H_4( *(unsigned int *) memory );
687 else
688 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
689 }
690
691 return size;
692 }
693 #endif
694 /* end-sanitize-sky */
695
696 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
697 {
698 if (cpu->register_widths[rn] == 32)
699 {
700 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
701 return 4;
702 }
703 else
704 {
705 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
706 return 8;
707 }
708 }
709
710 if (cpu->register_widths[rn] == 32)
711 {
712 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
713 return 4;
714 }
715 else
716 {
717 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
718 return 8;
719 }
720 }
721
722 int
723 sim_fetch_register (sd,rn,memory,length)
724 SIM_DESC sd;
725 int rn;
726 unsigned char *memory;
727 int length;
728 {
729 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
730 /* NOTE: gdb (the client) stores registers in target byte order
731 while the simulator uses host byte order */
732 #ifdef DEBUG
733 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
734 #endif /* DEBUG */
735
736 if (cpu->register_widths[rn] == 0)
737 {
738 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
739 return 0;
740 }
741
742 /* start-sanitize-r5900 */
743 if (rn >= 90 && rn < 90 + 32)
744 {
745 *(unsigned64*)memory = GPR1[rn - 90];
746 return 8;
747 }
748 switch (rn)
749 {
750 case REGISTER_SA:
751 *((unsigned64*)memory) = H2T_8(SA);
752 return 8;
753 case 122: /* FIXME */
754 *((unsigned64*)memory) = H2T_8(LO1);
755 return 8;
756 case 123: /* FIXME */
757 *((unsigned64*)memory) = H2T_8(HI1);
758 return 8;
759 }
760 /* end-sanitize-r5900 */
761
762 /* start-sanitize-sky */
763 #ifdef TARGET_SKY
764 if (rn >= NUM_R5900_REGS)
765 {
766 int size = 4; /* default register width */
767
768 rn = rn - NUM_R5900_REGS;
769
770 if (rn < NUM_VU_INTEGER_REGS)
771 {
772 *((unsigned short *) memory) = H2T_2( vu_regs[0].i[rn] );
773 size = 2;
774 }
775 else if (rn < NUM_VU_REGS)
776 *((unsigned int *) memory)
777 = H2T_4( vu_regs[0].f[rn - NUM_VU_INTEGER_REGS] );
778 else
779 {
780 rn = rn - NUM_VU_REGS;
781
782 if (rn < NUM_VU_INTEGER_REGS)
783 {
784 (*(unsigned short *) memory) = H2T_2( vu_regs[1].i[rn] );
785 size = 2;
786 }
787 else if (rn < NUM_VU_REGS)
788 (*(unsigned int *) memory)
789 = H2T_4( vu_regs[1].f[rn - NUM_VU_INTEGER_REGS] );
790 else
791 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
792 }
793
794 return size;
795 }
796 #endif
797 /* end-sanitize-sky */
798
799 /* Any floating point register */
800 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
801 {
802 if (cpu->register_widths[rn] == 32)
803 {
804 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
805 return 4;
806 }
807 else
808 {
809 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
810 return 8;
811 }
812 }
813
814 if (cpu->register_widths[rn] == 32)
815 {
816 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
817 return 4;
818 }
819 else
820 {
821 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
822 return 8;
823 }
824 }
825
826
827 SIM_RC
828 sim_create_inferior (sd, abfd, argv,env)
829 SIM_DESC sd;
830 struct _bfd *abfd;
831 char **argv;
832 char **env;
833 {
834
835 #ifdef DEBUG
836 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
837 pr_addr(PC));
838 #endif /* DEBUG */
839
840 ColdReset(sd);
841
842 if (abfd != NULL)
843 {
844 /* override PC value set by ColdReset () */
845 int cpu_nr;
846 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
847 {
848 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
849 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
850 }
851 }
852
853 #if 0 /* def DEBUG */
854 if (argv || env)
855 {
856 /* We should really place the argv slot values into the argument
857 registers, and onto the stack as required. However, this
858 assumes that we have a stack defined, which is not
859 necessarily true at the moment. */
860 char **cptr;
861 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
862 for (cptr = argv; (cptr && *cptr); cptr++)
863 printf("DBG: arg \"%s\"\n",*cptr);
864 }
865 #endif /* DEBUG */
866
867 return SIM_RC_OK;
868 }
869
870 void
871 sim_do_command (sd,cmd)
872 SIM_DESC sd;
873 char *cmd;
874 {
875 if (sim_args_command (sd, cmd) != SIM_RC_OK)
876 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
877 cmd);
878 }
879
880 /*---------------------------------------------------------------------------*/
881 /*-- Private simulator support interface ------------------------------------*/
882 /*---------------------------------------------------------------------------*/
883
884 /* Read a null terminated string from memory, return in a buffer */
885 static char *
886 fetch_str (sd, addr)
887 SIM_DESC sd;
888 address_word addr;
889 {
890 char *buf;
891 int nr = 0;
892 char null;
893 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
894 nr++;
895 buf = NZALLOC (char, nr + 1);
896 sim_read (sd, addr, buf, nr);
897 return buf;
898 }
899
900 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
901 static void
902 sim_monitor (SIM_DESC sd,
903 sim_cpu *cpu,
904 address_word cia,
905 unsigned int reason)
906 {
907 #ifdef DEBUG
908 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
909 #endif /* DEBUG */
910
911 /* The IDT monitor actually allows two instructions per vector
912 slot. However, the simulator currently causes a trap on each
913 individual instruction. We cheat, and lose the bottom bit. */
914 reason >>= 1;
915
916 /* The following callback functions are available, however the
917 monitor we are simulating does not make use of them: get_errno,
918 isatty, lseek, rename, system, time and unlink */
919 switch (reason)
920 {
921
922 case 6: /* int open(char *path,int flags) */
923 {
924 char *path = fetch_str (sd, A0);
925 V0 = sim_io_open (sd, path, (int)A1);
926 zfree (path);
927 break;
928 }
929
930 case 7: /* int read(int file,char *ptr,int len) */
931 {
932 int fd = A0;
933 int nr = A2;
934 char *buf = zalloc (nr);
935 V0 = sim_io_read (sd, fd, buf, nr);
936 sim_write (sd, A1, buf, nr);
937 zfree (buf);
938 }
939 break;
940
941 case 8: /* int write(int file,char *ptr,int len) */
942 {
943 int fd = A0;
944 int nr = A2;
945 char *buf = zalloc (nr);
946 sim_read (sd, A1, buf, nr);
947 V0 = sim_io_write (sd, fd, buf, nr);
948 zfree (buf);
949 break;
950 }
951
952 case 10: /* int close(int file) */
953 {
954 V0 = sim_io_close (sd, (int)A0);
955 break;
956 }
957
958 case 2: /* Densan monitor: char inbyte(int waitflag) */
959 {
960 if (A0 == 0) /* waitflag == NOWAIT */
961 V0 = (unsigned_word)-1;
962 }
963 /* Drop through to case 11 */
964
965 case 11: /* char inbyte(void) */
966 {
967 char tmp;
968 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
969 {
970 sim_io_error(sd,"Invalid return from character read");
971 V0 = (unsigned_word)-1;
972 }
973 else
974 V0 = (unsigned_word)tmp;
975 break;
976 }
977
978 case 3: /* Densan monitor: void co(char chr) */
979 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
980 {
981 char tmp = (char)(A0 & 0xFF);
982 sim_io_write_stdout (sd, &tmp, sizeof(char));
983 break;
984 }
985
986 case 17: /* void _exit() */
987 {
988 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
989 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
990 (unsigned int)(A0 & 0xFFFFFFFF));
991 break;
992 }
993
994 case 28 : /* PMON flush_cache */
995 break;
996
997 case 55: /* void get_mem_info(unsigned int *ptr) */
998 /* in: A0 = pointer to three word memory location */
999 /* out: [A0 + 0] = size */
1000 /* [A0 + 4] = instruction cache size */
1001 /* [A0 + 8] = data cache size */
1002 {
1003 address_word value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
1004 H2T (value);
1005 sim_write (sd, A0, (char *)&value, sizeof (value));
1006 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1007 break;
1008 }
1009
1010 case 158 : /* PMON printf */
1011 /* in: A0 = pointer to format string */
1012 /* A1 = optional argument 1 */
1013 /* A2 = optional argument 2 */
1014 /* A3 = optional argument 3 */
1015 /* out: void */
1016 /* The following is based on the PMON printf source */
1017 {
1018 address_word s = A0;
1019 char c;
1020 signed_word *ap = &A1; /* 1st argument */
1021 /* This isn't the quickest way, since we call the host print
1022 routine for every character almost. But it does avoid
1023 having to allocate and manage a temporary string buffer. */
1024 /* TODO: Include check that we only use three arguments (A1,
1025 A2 and A3) */
1026 while (sim_read (sd, s++, &c, 1) && c != '\0')
1027 {
1028 if (c == '%')
1029 {
1030 char tmp[40];
1031 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1032 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1033 while (sim_read (sd, s++, &c, 1) && c != '\0')
1034 {
1035 if (strchr ("dobxXulscefg%", s))
1036 break;
1037 else if (c == '-')
1038 fmt = FMT_LJUST;
1039 else if (c == '0')
1040 fmt = FMT_RJUST0;
1041 else if (c == '~')
1042 fmt = FMT_CENTER;
1043 else if (c == '*')
1044 {
1045 if (haddot)
1046 trunc = (int)*ap++;
1047 else
1048 width = (int)*ap++;
1049 }
1050 else if (c >= '1' && c <= '9')
1051 {
1052 address_word t = s;
1053 unsigned int n;
1054 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1055 tmp[s - t] = c;
1056 tmp[s - t] = '\0';
1057 n = (unsigned int)strtol(tmp,NULL,10);
1058 if (haddot)
1059 trunc = n;
1060 else
1061 width = n;
1062 s--;
1063 }
1064 else if (c == '.')
1065 haddot = 1;
1066 }
1067 switch (c)
1068 {
1069 case '%':
1070 sim_io_printf (sd, "%%");
1071 break;
1072 case 's':
1073 if ((int)*ap != 0)
1074 {
1075 address_word p = *ap++;
1076 char ch;
1077 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1078 sim_io_printf(sd, "%c", ch);
1079 }
1080 else
1081 sim_io_printf(sd,"(null)");
1082 break;
1083 case 'c':
1084 sim_io_printf (sd, "%c", (int)*ap++);
1085 break;
1086 default:
1087 if (c == 'l')
1088 {
1089 sim_read (sd, s++, &c, 1);
1090 if (c == 'l')
1091 {
1092 longlong = 1;
1093 sim_read (sd, s++, &c, 1);
1094 }
1095 }
1096 if (strchr ("dobxXu", c))
1097 {
1098 word64 lv = (word64) *ap++;
1099 if (c == 'b')
1100 sim_io_printf(sd,"<binary not supported>");
1101 else
1102 {
1103 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1104 if (longlong)
1105 sim_io_printf(sd, tmp, lv);
1106 else
1107 sim_io_printf(sd, tmp, (int)lv);
1108 }
1109 }
1110 else if (strchr ("eEfgG", c))
1111 {
1112 double dbl = *(double*)(ap++);
1113 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1114 sim_io_printf (sd, tmp, dbl);
1115 trunc = 0;
1116 }
1117 }
1118 }
1119 else
1120 sim_io_printf(sd, "%c", c);
1121 }
1122 break;
1123 }
1124
1125 default:
1126 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1127 reason, pr_addr(cia));
1128 break;
1129 }
1130 return;
1131 }
1132
1133 /* Store a word into memory. */
1134
1135 static void
1136 store_word (SIM_DESC sd,
1137 sim_cpu *cpu,
1138 address_word cia,
1139 uword64 vaddr,
1140 signed_word val)
1141 {
1142 address_word paddr;
1143 int uncached;
1144
1145 if ((vaddr & 3) != 0)
1146 SignalExceptionAddressStore ();
1147 else
1148 {
1149 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1150 isTARGET, isREAL))
1151 {
1152 const uword64 mask = 7;
1153 uword64 memval;
1154 unsigned int byte;
1155
1156 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1157 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1158 memval = ((uword64) val) << (8 * byte);
1159 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1160 isREAL);
1161 }
1162 }
1163 }
1164
1165 /* Load a word from memory. */
1166
1167 static signed_word
1168 load_word (SIM_DESC sd,
1169 sim_cpu *cpu,
1170 address_word cia,
1171 uword64 vaddr)
1172 {
1173 if ((vaddr & 3) != 0)
1174 SignalExceptionAddressLoad ();
1175 else
1176 {
1177 address_word paddr;
1178 int uncached;
1179
1180 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1181 isTARGET, isREAL))
1182 {
1183 const uword64 mask = 0x7;
1184 const unsigned int reverse = ReverseEndian ? 1 : 0;
1185 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1186 uword64 memval;
1187 unsigned int byte;
1188
1189 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1190 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1191 isDATA, isREAL);
1192 byte = (vaddr & mask) ^ (bigend << 2);
1193 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1194 }
1195 }
1196
1197 return 0;
1198 }
1199
1200 /* Simulate the mips16 entry and exit pseudo-instructions. These
1201 would normally be handled by the reserved instruction exception
1202 code, but for ease of simulation we just handle them directly. */
1203
1204 static void
1205 mips16_entry (SIM_DESC sd,
1206 sim_cpu *cpu,
1207 address_word cia,
1208 unsigned int insn)
1209 {
1210 int aregs, sregs, rreg;
1211
1212 #ifdef DEBUG
1213 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1214 #endif /* DEBUG */
1215
1216 aregs = (insn & 0x700) >> 8;
1217 sregs = (insn & 0x0c0) >> 6;
1218 rreg = (insn & 0x020) >> 5;
1219
1220 /* This should be checked by the caller. */
1221 if (sregs == 3)
1222 abort ();
1223
1224 if (aregs < 5)
1225 {
1226 int i;
1227 signed_word tsp;
1228
1229 /* This is the entry pseudo-instruction. */
1230
1231 for (i = 0; i < aregs; i++)
1232 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1233
1234 tsp = SP;
1235 SP -= 32;
1236
1237 if (rreg)
1238 {
1239 tsp -= 4;
1240 store_word (SD, CPU, cia, (uword64) tsp, RA);
1241 }
1242
1243 for (i = 0; i < sregs; i++)
1244 {
1245 tsp -= 4;
1246 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1247 }
1248 }
1249 else
1250 {
1251 int i;
1252 signed_word tsp;
1253
1254 /* This is the exit pseudo-instruction. */
1255
1256 tsp = SP + 32;
1257
1258 if (rreg)
1259 {
1260 tsp -= 4;
1261 RA = load_word (SD, CPU, cia, (uword64) tsp);
1262 }
1263
1264 for (i = 0; i < sregs; i++)
1265 {
1266 tsp -= 4;
1267 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1268 }
1269
1270 SP += 32;
1271
1272 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1273 {
1274 if (aregs == 5)
1275 {
1276 FGR[0] = WORD64LO (GPR[4]);
1277 FPR_STATE[0] = fmt_uninterpreted;
1278 }
1279 else if (aregs == 6)
1280 {
1281 FGR[0] = WORD64LO (GPR[5]);
1282 FGR[1] = WORD64LO (GPR[4]);
1283 FPR_STATE[0] = fmt_uninterpreted;
1284 FPR_STATE[1] = fmt_uninterpreted;
1285 }
1286 }
1287
1288 PC = RA;
1289 }
1290
1291 }
1292
1293 /*-- trace support ----------------------------------------------------------*/
1294
1295 /* The TRACE support is provided (if required) in the memory accessing
1296 routines. Since we are also providing the architecture specific
1297 features, the architecture simulation code can also deal with
1298 notifying the TRACE world of cache flushes, etc. Similarly we do
1299 not need to provide profiling support in the simulator engine,
1300 since we can sample in the instruction fetch control loop. By
1301 defining the TRACE manifest, we add tracing as a run-time
1302 option. */
1303
1304 #if defined(TRACE)
1305 /* Tracing by default produces "din" format (as required by
1306 dineroIII). Each line of such a trace file *MUST* have a din label
1307 and address field. The rest of the line is ignored, so comments can
1308 be included if desired. The first field is the label which must be
1309 one of the following values:
1310
1311 0 read data
1312 1 write data
1313 2 instruction fetch
1314 3 escape record (treated as unknown access type)
1315 4 escape record (causes cache flush)
1316
1317 The address field is a 32bit (lower-case) hexadecimal address
1318 value. The address should *NOT* be preceded by "0x".
1319
1320 The size of the memory transfer is not important when dealing with
1321 cache lines (as long as no more than a cache line can be
1322 transferred in a single operation :-), however more information
1323 could be given following the dineroIII requirement to allow more
1324 complete memory and cache simulators to provide better
1325 results. i.e. the University of Pisa has a cache simulator that can
1326 also take bus size and speed as (variable) inputs to calculate
1327 complete system performance (a much more useful ability when trying
1328 to construct an end product, rather than a processor). They
1329 currently have an ARM version of their tool called ChARM. */
1330
1331
1332 void
1333 dotrace (SIM_DESC sd,
1334 sim_cpu *cpu,
1335 FILE *tracefh,
1336 int type,
1337 SIM_ADDR address,
1338 int width,
1339 char *comment,...)
1340 {
1341 if (STATE & simTRACE) {
1342 va_list ap;
1343 fprintf(tracefh,"%d %s ; width %d ; ",
1344 type,
1345 pr_addr(address),
1346 width);
1347 va_start(ap,comment);
1348 vfprintf(tracefh,comment,ap);
1349 va_end(ap);
1350 fprintf(tracefh,"\n");
1351 }
1352 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1353 we may be generating 64bit ones, we should put the hi-32bits of the
1354 address into the comment field. */
1355
1356 /* TODO: Provide a buffer for the trace lines. We can then avoid
1357 performing writes until the buffer is filled, or the file is
1358 being closed. */
1359
1360 /* NOTE: We could consider adding a comment field to the "din" file
1361 produced using type 3 markers (unknown access). This would then
1362 allow information about the program that the "din" is for, and
1363 the MIPs world that was being simulated, to be placed into the
1364 trace file. */
1365
1366 return;
1367 }
1368 #endif /* TRACE */
1369
1370 /*---------------------------------------------------------------------------*/
1371 /*-- simulator engine -------------------------------------------------------*/
1372 /*---------------------------------------------------------------------------*/
1373
1374 static void
1375 ColdReset (SIM_DESC sd)
1376 {
1377 int cpu_nr;
1378 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1379 {
1380 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1381 /* RESET: Fixed PC address: */
1382 PC = UNSIGNED64 (0xFFFFFFFFBFC00000);
1383 /* The reset vector address is in the unmapped, uncached memory space. */
1384
1385 SR &= ~(status_SR | status_TS | status_RP);
1386 SR |= (status_ERL | status_BEV);
1387
1388 /* Cheat and allow access to the complete register set immediately */
1389 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1390 && WITH_TARGET_WORD_BITSIZE == 64)
1391 SR |= status_FR; /* 64bit registers */
1392
1393 /* Ensure that any instructions with pending register updates are
1394 cleared: */
1395 PENDING_INVALIDATE();
1396
1397 /* Initialise the FPU registers to the unknown state */
1398 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1399 {
1400 int rn;
1401 for (rn = 0; (rn < 32); rn++)
1402 FPR_STATE[rn] = fmt_uninterpreted;
1403 }
1404
1405 }
1406 }
1407
1408 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1409 (revision 3.1) */
1410 /* Translate a virtual address to a physical address and cache
1411 coherence algorithm describing the mechanism used to resolve the
1412 memory reference. Given the virtual address vAddr, and whether the
1413 reference is to Instructions ot Data (IorD), find the corresponding
1414 physical address (pAddr) and the cache coherence algorithm (CCA)
1415 used to resolve the reference. If the virtual address is in one of
1416 the unmapped address spaces the physical address and the CCA are
1417 determined directly by the virtual address. If the virtual address
1418 is in one of the mapped address spaces then the TLB is used to
1419 determine the physical address and access type; if the required
1420 translation is not present in the TLB or the desired access is not
1421 permitted the function fails and an exception is taken.
1422
1423 NOTE: Normally (RAW == 0), when address translation fails, this
1424 function raises an exception and does not return. */
1425
1426 int
1427 address_translation (SIM_DESC sd,
1428 sim_cpu *cpu,
1429 address_word cia,
1430 address_word vAddr,
1431 int IorD,
1432 int LorS,
1433 address_word *pAddr,
1434 int *CCA,
1435 int raw)
1436 {
1437 int res = -1; /* TRUE : Assume good return */
1438
1439 #ifdef DEBUG
1440 sim_io_printf(sd,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"),(LorS ? "iSTORE" : "isLOAD"));
1441 #endif
1442
1443 /* Check that the address is valid for this memory model */
1444
1445 /* For a simple (flat) memory model, we simply pass virtual
1446 addressess through (mostly) unchanged. */
1447 vAddr &= 0xFFFFFFFF;
1448
1449 *pAddr = vAddr; /* default for isTARGET */
1450 *CCA = Uncached; /* not used for isHOST */
1451
1452 return(res);
1453 }
1454
1455 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1456 (revision 3.1) */
1457 /* Prefetch data from memory. Prefetch is an advisory instruction for
1458 which an implementation specific action is taken. The action taken
1459 may increase performance, but must not change the meaning of the
1460 program, or alter architecturally-visible state. */
1461
1462 void
1463 prefetch (SIM_DESC sd,
1464 sim_cpu *cpu,
1465 address_word cia,
1466 int CCA,
1467 address_word pAddr,
1468 address_word vAddr,
1469 int DATA,
1470 int hint)
1471 {
1472 #ifdef DEBUG
1473 sim_io_printf(sd,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA,pr_addr(pAddr),pr_addr(vAddr),DATA,hint);
1474 #endif /* DEBUG */
1475
1476 /* For our simple memory model we do nothing */
1477 return;
1478 }
1479
1480 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1481 (revision 3.1) */
1482 /* Load a value from memory. Use the cache and main memory as
1483 specified in the Cache Coherence Algorithm (CCA) and the sort of
1484 access (IorD) to find the contents of AccessLength memory bytes
1485 starting at physical location pAddr. The data is returned in the
1486 fixed width naturally-aligned memory element (MemElem). The
1487 low-order two (or three) bits of the address and the AccessLength
1488 indicate which of the bytes within MemElem needs to be given to the
1489 processor. If the memory access type of the reference is uncached
1490 then only the referenced bytes are read from memory and valid
1491 within the memory element. If the access type is cached, and the
1492 data is not present in cache, an implementation specific size and
1493 alignment block of memory is read and loaded into the cache to
1494 satisfy a load reference. At a minimum, the block is the entire
1495 memory element. */
1496 void
1497 load_memory (SIM_DESC sd,
1498 sim_cpu *cpu,
1499 address_word cia,
1500 uword64* memvalp,
1501 uword64* memval1p,
1502 int CCA,
1503 int AccessLength,
1504 address_word pAddr,
1505 address_word vAddr,
1506 int IorD)
1507 {
1508 uword64 value = 0;
1509 uword64 value1 = 0;
1510
1511 #ifdef DEBUG
1512 sim_io_printf(sd,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp,memval1p,CCA,AccessLength,pr_addr(pAddr),pr_addr(vAddr),(IorD ? "isDATA" : "isINSTRUCTION"));
1513 #endif /* DEBUG */
1514
1515 #if defined(WARN_MEM)
1516 if (CCA != uncached)
1517 sim_io_eprintf(sd,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1518 #endif /* WARN_MEM */
1519
1520 /* If instruction fetch then we need to check that the two lo-order
1521 bits are zero, otherwise raise a InstructionFetch exception: */
1522 if ((IorD == isINSTRUCTION)
1523 && ((pAddr & 0x3) != 0)
1524 && (((pAddr & 0x1) != 0) || ((vAddr & 0x1) == 0)))
1525 SignalExceptionInstructionFetch ();
1526
1527 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1528 {
1529 /* In reality this should be a Bus Error */
1530 sim_io_error (sd, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1531 AccessLength,
1532 (LOADDRMASK + 1) << 2,
1533 pr_addr (pAddr));
1534 }
1535
1536 #if defined(TRACE)
1537 dotrace (SD, CPU, tracefh,((IorD == isDATA) ? 0 : 2),(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"load%s",((IorD == isDATA) ? "" : " instruction"));
1538 #endif /* TRACE */
1539
1540 /* Read the specified number of bytes from memory. Adjust for
1541 host/target byte ordering/ Align the least significant byte
1542 read. */
1543
1544 switch (AccessLength)
1545 {
1546 case AccessLength_QUADWORD :
1547 {
1548 unsigned_16 val = sim_core_read_aligned_16 (cpu, NULL_CIA, read_map, pAddr);
1549 value1 = VH8_16 (val);
1550 value = VL8_16 (val);
1551 break;
1552 }
1553 case AccessLength_DOUBLEWORD :
1554 value = sim_core_read_aligned_8 (cpu, NULL_CIA,
1555 read_map, pAddr);
1556 break;
1557 case AccessLength_SEPTIBYTE :
1558 value = sim_core_read_misaligned_7 (cpu, NULL_CIA,
1559 read_map, pAddr);
1560 break;
1561 case AccessLength_SEXTIBYTE :
1562 value = sim_core_read_misaligned_6 (cpu, NULL_CIA,
1563 read_map, pAddr);
1564 break;
1565 case AccessLength_QUINTIBYTE :
1566 value = sim_core_read_misaligned_5 (cpu, NULL_CIA,
1567 read_map, pAddr);
1568 break;
1569 case AccessLength_WORD :
1570 value = sim_core_read_aligned_4 (cpu, NULL_CIA,
1571 read_map, pAddr);
1572 break;
1573 case AccessLength_TRIPLEBYTE :
1574 value = sim_core_read_misaligned_3 (cpu, NULL_CIA,
1575 read_map, pAddr);
1576 break;
1577 case AccessLength_HALFWORD :
1578 value = sim_core_read_aligned_2 (cpu, NULL_CIA,
1579 read_map, pAddr);
1580 break;
1581 case AccessLength_BYTE :
1582 value = sim_core_read_aligned_1 (cpu, NULL_CIA,
1583 read_map, pAddr);
1584 break;
1585 default:
1586 abort ();
1587 }
1588
1589 #ifdef DEBUG
1590 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1591 (int)(pAddr & LOADDRMASK),pr_uword64(value1),pr_uword64(value));
1592 #endif /* DEBUG */
1593
1594 /* See also store_memory. */
1595 if (AccessLength <= AccessLength_DOUBLEWORD)
1596 {
1597 if (BigEndianMem)
1598 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1599 shifted to the most significant byte position. */
1600 value <<= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1601 else
1602 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1603 is already in the correct postition. */
1604 value <<= ((pAddr & LOADDRMASK) * 8);
1605 }
1606
1607 #ifdef DEBUG
1608 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1609 pr_uword64(value1),pr_uword64(value));
1610 #endif /* DEBUG */
1611
1612 *memvalp = value;
1613 if (memval1p) *memval1p = value1;
1614 }
1615
1616
1617 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1618 (revision 3.1) */
1619 /* Store a value to memory. The specified data is stored into the
1620 physical location pAddr using the memory hierarchy (data caches and
1621 main memory) as specified by the Cache Coherence Algorithm
1622 (CCA). The MemElem contains the data for an aligned, fixed-width
1623 memory element (word for 32-bit processors, doubleword for 64-bit
1624 processors), though only the bytes that will actually be stored to
1625 memory need to be valid. The low-order two (or three) bits of pAddr
1626 and the AccessLength field indicates which of the bytes within the
1627 MemElem data should actually be stored; only these bytes in memory
1628 will be changed. */
1629
1630 void
1631 store_memory (SIM_DESC sd,
1632 sim_cpu *cpu,
1633 address_word cia,
1634 int CCA,
1635 int AccessLength,
1636 uword64 MemElem,
1637 uword64 MemElem1, /* High order 64 bits */
1638 address_word pAddr,
1639 address_word vAddr)
1640 {
1641 #ifdef DEBUG
1642 sim_io_printf(sd,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA,AccessLength,pr_uword64(MemElem),pr_uword64(MemElem1),pr_addr(pAddr),pr_addr(vAddr));
1643 #endif /* DEBUG */
1644
1645 #if defined(WARN_MEM)
1646 if (CCA != uncached)
1647 sim_io_eprintf(sd,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA);
1648 #endif /* WARN_MEM */
1649
1650 if (((pAddr & LOADDRMASK) + AccessLength) > LOADDRMASK)
1651 sim_io_error(sd,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength,(LOADDRMASK + 1)<<2,pr_addr(pAddr));
1652
1653 #if defined(TRACE)
1654 dotrace (SD, CPU, tracefh,1,(unsigned int)(pAddr&0xFFFFFFFF),(AccessLength + 1),"store");
1655 #endif /* TRACE */
1656
1657 #ifdef DEBUG
1658 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr & LOADDRMASK),pr_uword64(MemElem1),pr_uword64(MemElem));
1659 #endif /* DEBUG */
1660
1661 /* See also load_memory */
1662 if (AccessLength <= AccessLength_DOUBLEWORD)
1663 {
1664 if (BigEndianMem)
1665 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1666 shifted to the most significant byte position. */
1667 MemElem >>= (((7 - (pAddr & LOADDRMASK)) - AccessLength) * 8);
1668 else
1669 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1670 is already in the correct postition. */
1671 MemElem >>= ((pAddr & LOADDRMASK) * 8);
1672 }
1673
1674 #ifdef DEBUG
1675 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift,pr_uword64(MemElem1),pr_uword64(MemElem));
1676 #endif /* DEBUG */
1677
1678 switch (AccessLength)
1679 {
1680 case AccessLength_QUADWORD :
1681 {
1682 unsigned_16 val = U16_8 (MemElem1, MemElem);
1683 sim_core_write_aligned_16 (cpu, NULL_CIA, write_map, pAddr, val);
1684 break;
1685 }
1686 case AccessLength_DOUBLEWORD :
1687 sim_core_write_aligned_8 (cpu, NULL_CIA,
1688 write_map, pAddr, MemElem);
1689 break;
1690 case AccessLength_SEPTIBYTE :
1691 sim_core_write_misaligned_7 (cpu, NULL_CIA,
1692 write_map, pAddr, MemElem);
1693 break;
1694 case AccessLength_SEXTIBYTE :
1695 sim_core_write_misaligned_6 (cpu, NULL_CIA,
1696 write_map, pAddr, MemElem);
1697 break;
1698 case AccessLength_QUINTIBYTE :
1699 sim_core_write_misaligned_5 (cpu, NULL_CIA,
1700 write_map, pAddr, MemElem);
1701 break;
1702 case AccessLength_WORD :
1703 sim_core_write_aligned_4 (cpu, NULL_CIA,
1704 write_map, pAddr, MemElem);
1705 break;
1706 case AccessLength_TRIPLEBYTE :
1707 sim_core_write_misaligned_3 (cpu, NULL_CIA,
1708 write_map, pAddr, MemElem);
1709 break;
1710 case AccessLength_HALFWORD :
1711 sim_core_write_aligned_2 (cpu, NULL_CIA,
1712 write_map, pAddr, MemElem);
1713 break;
1714 case AccessLength_BYTE :
1715 sim_core_write_aligned_1 (cpu, NULL_CIA,
1716 write_map, pAddr, MemElem);
1717 break;
1718 default:
1719 abort ();
1720 }
1721
1722 return;
1723 }
1724
1725
1726 unsigned32
1727 ifetch32 (SIM_DESC sd,
1728 sim_cpu *cpu,
1729 address_word cia,
1730 address_word vaddr)
1731 {
1732 /* Copy the action of the LW instruction */
1733 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1734 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1735 unsigned64 value;
1736 address_word paddr;
1737 unsigned32 instruction;
1738 unsigned byte;
1739 int cca;
1740 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1741 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1742 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1743 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1744 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1745 return instruction;
1746 }
1747
1748
1749 unsigned16
1750 ifetch16 (SIM_DESC sd,
1751 sim_cpu *cpu,
1752 address_word cia,
1753 address_word vaddr)
1754 {
1755 /* Copy the action of the LW instruction */
1756 address_word reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
1757 address_word bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
1758 unsigned64 value;
1759 address_word paddr;
1760 unsigned16 instruction;
1761 unsigned byte;
1762 int cca;
1763 AddressTranslation (vaddr, isINSTRUCTION, isLOAD, &paddr, &cca, isTARGET, isREAL);
1764 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
1765 LoadMemory (&value, NULL, cca, AccessLength_WORD, paddr, vaddr, isINSTRUCTION, isREAL);
1766 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
1767 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
1768 return instruction;
1769 }
1770
1771
1772 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1773 /* Order loads and stores to synchronise shared memory. Perform the
1774 action necessary to make the effects of groups of synchronizable
1775 loads and stores indicated by stype occur in the same order for all
1776 processors. */
1777 void
1778 sync_operation (SIM_DESC sd,
1779 sim_cpu *cpu,
1780 address_word cia,
1781 int stype)
1782 {
1783 #ifdef DEBUG
1784 sim_io_printf(sd,"SyncOperation(%d) : TODO\n",stype);
1785 #endif /* DEBUG */
1786 return;
1787 }
1788
1789 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1790 /* Signal an exception condition. This will result in an exception
1791 that aborts the instruction. The instruction operation pseudocode
1792 will never see a return from this function call. */
1793
1794 void
1795 signal_exception (SIM_DESC sd,
1796 sim_cpu *cpu,
1797 address_word cia,
1798 int exception,...)
1799 {
1800 int vector;
1801
1802 #ifdef DEBUG
1803 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1804 #endif /* DEBUG */
1805
1806 /* Ensure that any active atomic read/modify/write operation will fail: */
1807 LLBIT = 0;
1808
1809 switch (exception) {
1810 /* TODO: For testing purposes I have been ignoring TRAPs. In
1811 reality we should either simulate them, or allow the user to
1812 ignore them at run-time.
1813 Same for SYSCALL */
1814 case Trap :
1815 sim_io_eprintf(sd,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia));
1816 break;
1817
1818 case SystemCall :
1819 {
1820 va_list ap;
1821 unsigned int instruction;
1822 unsigned int code;
1823
1824 va_start(ap,exception);
1825 instruction = va_arg(ap,unsigned int);
1826 va_end(ap);
1827
1828 code = (instruction >> 6) & 0xFFFFF;
1829
1830 sim_io_eprintf(sd,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1831 code, pr_addr(cia));
1832 }
1833 break;
1834
1835 case DebugBreakPoint :
1836 if (! (Debug & Debug_DM))
1837 {
1838 if (INDELAYSLOT())
1839 {
1840 CANCELDELAYSLOT();
1841
1842 Debug |= Debug_DBD; /* signaled from within in delay slot */
1843 DEPC = cia - 4; /* reference the branch instruction */
1844 }
1845 else
1846 {
1847 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1848 DEPC = cia;
1849 }
1850
1851 Debug |= Debug_DM; /* in debugging mode */
1852 Debug |= Debug_DBp; /* raising a DBp exception */
1853 PC = 0xBFC00200;
1854 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1855 }
1856 break;
1857
1858 case ReservedInstruction :
1859 {
1860 va_list ap;
1861 unsigned int instruction;
1862 va_start(ap,exception);
1863 instruction = va_arg(ap,unsigned int);
1864 va_end(ap);
1865 /* Provide simple monitor support using ReservedInstruction
1866 exceptions. The following code simulates the fixed vector
1867 entry points into the IDT monitor by causing a simulator
1868 trap, performing the monitor operation, and returning to
1869 the address held in the $ra register (standard PCS return
1870 address). This means we only need to pre-load the vector
1871 space with suitable instruction values. For systems were
1872 actual trap instructions are used, we would not need to
1873 perform this magic. */
1874 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1875 {
1876 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1877 /* NOTE: This assumes that a branch-and-link style
1878 instruction was used to enter the vector (which is the
1879 case with the current IDT monitor). */
1880 sim_engine_restart (SD, CPU, NULL, RA);
1881 }
1882 /* Look for the mips16 entry and exit instructions, and
1883 simulate a handler for them. */
1884 else if ((cia & 1) != 0
1885 && (instruction & 0xf81f) == 0xe809
1886 && (instruction & 0x0c0) != 0x0c0)
1887 {
1888 mips16_entry (SD, CPU, cia, instruction);
1889 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1890 }
1891 /* else fall through to normal exception processing */
1892 sim_io_eprintf(sd,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction,pr_addr(cia));
1893 }
1894
1895 case BreakPoint:
1896 #ifdef DEBUG
1897 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1898 #endif /* DEBUG */
1899 /* Keep a copy of the current A0 in-case this is the program exit
1900 breakpoint: */
1901 {
1902 va_list ap;
1903 unsigned int instruction;
1904 va_start(ap,exception);
1905 instruction = va_arg(ap,unsigned int);
1906 va_end(ap);
1907 /* Check for our special terminating BREAK: */
1908 if ((instruction & 0x03FFFFC0) == 0x03ff0000) {
1909 sim_engine_halt (SD, CPU, NULL, cia,
1910 sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1911 }
1912 }
1913 if (STATE & simDELAYSLOT)
1914 PC = cia - 4; /* reference the branch instruction */
1915 else
1916 PC = cia;
1917 sim_engine_halt (SD, CPU, NULL, cia,
1918 sim_stopped, SIM_SIGTRAP);
1919
1920 default:
1921 /* Store exception code into current exception id variable (used
1922 by exit code): */
1923
1924 /* TODO: If not simulating exceptions then stop the simulator
1925 execution. At the moment we always stop the simulation. */
1926
1927 /* See figure 5-17 for an outline of the code below */
1928 if (! (SR & status_EXL))
1929 {
1930 CAUSE = (exception << 2);
1931 if (STATE & simDELAYSLOT)
1932 {
1933 STATE &= ~simDELAYSLOT;
1934 CAUSE |= cause_BD;
1935 EPC = (cia - 4); /* reference the branch instruction */
1936 }
1937 else
1938 EPC = cia;
1939 /* FIXME: TLB et.al. */
1940 vector = 0x180;
1941 }
1942 else
1943 {
1944 CAUSE = (exception << 2);
1945 vector = 0x180;
1946 }
1947 SR |= status_EXL;
1948 /* Store exception code into current exception id variable (used
1949 by exit code): */
1950 if (SR & status_BEV)
1951 PC = (signed)0xBFC00200 + 0x180;
1952 else
1953 PC = (signed)0x80000000 + 0x180;
1954
1955 switch ((CAUSE >> 2) & 0x1F)
1956 {
1957 case Interrupt:
1958 /* Interrupts arrive during event processing, no need to
1959 restart */
1960 return;
1961
1962 case TLBModification:
1963 case TLBLoad:
1964 case TLBStore:
1965 case AddressLoad:
1966 case AddressStore:
1967 case InstructionFetch:
1968 case DataReference:
1969 /* The following is so that the simulator will continue from the
1970 exception address on breakpoint operations. */
1971 PC = EPC;
1972 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1973 sim_stopped, SIM_SIGBUS);
1974
1975 case ReservedInstruction:
1976 case CoProcessorUnusable:
1977 PC = EPC;
1978 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1979 sim_stopped, SIM_SIGILL);
1980
1981 case IntegerOverflow:
1982 case FPE:
1983 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1984 sim_stopped, SIM_SIGFPE);
1985
1986 case Trap:
1987 case Watch:
1988 case SystemCall:
1989 PC = EPC;
1990 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1991 sim_stopped, SIM_SIGTRAP);
1992
1993 case BreakPoint:
1994 PC = EPC;
1995 sim_engine_abort (SD, CPU, NULL_CIA,
1996 "FATAL: Should not encounter a breakpoint\n");
1997
1998 default : /* Unknown internal exception */
1999 PC = EPC;
2000 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
2001 sim_stopped, SIM_SIGABRT);
2002
2003 }
2004
2005 case SimulatorFault:
2006 {
2007 va_list ap;
2008 char *msg;
2009 va_start(ap,exception);
2010 msg = va_arg(ap,char *);
2011 va_end(ap);
2012 sim_engine_abort (SD, CPU, NULL_CIA,
2013 "FATAL: Simulator error \"%s\"\n",msg);
2014 }
2015 }
2016
2017 return;
2018 }
2019
2020 #if defined(WARN_RESULT)
2021 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2022 /* This function indicates that the result of the operation is
2023 undefined. However, this should not affect the instruction
2024 stream. All that is meant to happen is that the destination
2025 register is set to an undefined result. To keep the simulator
2026 simple, we just don't bother updating the destination register, so
2027 the overall result will be undefined. If desired we can stop the
2028 simulator by raising a pseudo-exception. */
2029 #define UndefinedResult() undefined_result (sd,cia)
2030 static void
2031 undefined_result(sd,cia)
2032 SIM_DESC sd;
2033 address_word cia;
2034 {
2035 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
2036 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2037 state |= simSTOP;
2038 #endif
2039 return;
2040 }
2041 #endif /* WARN_RESULT */
2042
2043 void
2044 cache_op (SIM_DESC sd,
2045 sim_cpu *cpu,
2046 address_word cia,
2047 int op,
2048 address_word pAddr,
2049 address_word vAddr,
2050 unsigned int instruction)
2051 {
2052 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2053 static int icache_warning = 1;
2054 static int dcache_warning = 1;
2055 #else
2056 static int icache_warning = 0;
2057 static int dcache_warning = 0;
2058 #endif
2059
2060 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2061 enable bit in the Status Register is clear - a coprocessor
2062 unusable exception is taken. */
2063 #if 0
2064 sim_io_printf(sd,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia));
2065 #endif
2066
2067 switch (op & 0x3) {
2068 case 0: /* instruction cache */
2069 switch (op >> 2) {
2070 case 0: /* Index Invalidate */
2071 case 1: /* Index Load Tag */
2072 case 2: /* Index Store Tag */
2073 case 4: /* Hit Invalidate */
2074 case 5: /* Fill */
2075 case 6: /* Hit Writeback */
2076 if (!icache_warning)
2077 {
2078 sim_io_eprintf(sd,"Instruction CACHE operation %d to be coded\n",(op >> 2));
2079 icache_warning = 1;
2080 }
2081 break;
2082
2083 default:
2084 SignalException(ReservedInstruction,instruction);
2085 break;
2086 }
2087 break;
2088
2089 case 1: /* data cache */
2090 switch (op >> 2) {
2091 case 0: /* Index Writeback Invalidate */
2092 case 1: /* Index Load Tag */
2093 case 2: /* Index Store Tag */
2094 case 3: /* Create Dirty */
2095 case 4: /* Hit Invalidate */
2096 case 5: /* Hit Writeback Invalidate */
2097 case 6: /* Hit Writeback */
2098 if (!dcache_warning)
2099 {
2100 sim_io_eprintf(sd,"Data CACHE operation %d to be coded\n",(op >> 2));
2101 dcache_warning = 1;
2102 }
2103 break;
2104
2105 default:
2106 SignalException(ReservedInstruction,instruction);
2107 break;
2108 }
2109 break;
2110
2111 default: /* unrecognised cache ID */
2112 SignalException(ReservedInstruction,instruction);
2113 break;
2114 }
2115
2116 return;
2117 }
2118
2119 /*-- FPU support routines ---------------------------------------------------*/
2120
2121 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2122 formats conform to ANSI/IEEE Std 754-1985. */
2123 /* SINGLE precision floating:
2124 * seeeeeeeefffffffffffffffffffffff
2125 * s = 1bit = sign
2126 * e = 8bits = exponent
2127 * f = 23bits = fraction
2128 */
2129 /* SINGLE precision fixed:
2130 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2131 * s = 1bit = sign
2132 * i = 31bits = integer
2133 */
2134 /* DOUBLE precision floating:
2135 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2136 * s = 1bit = sign
2137 * e = 11bits = exponent
2138 * f = 52bits = fraction
2139 */
2140 /* DOUBLE precision fixed:
2141 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2142 * s = 1bit = sign
2143 * i = 63bits = integer
2144 */
2145
2146 /* Extract sign-bit: */
2147 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2148 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2149 /* Extract biased exponent: */
2150 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2151 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2152 /* Extract unbiased Exponent: */
2153 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2154 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2155 /* Extract complete fraction field: */
2156 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2157 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2158 /* Extract numbered fraction bit: */
2159 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2160 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2161
2162 /* Explicit QNaN values used when value required: */
2163 #define FPQNaN_SINGLE (0x7FBFFFFF)
2164 #define FPQNaN_WORD (0x7FFFFFFF)
2165 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2166 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2167
2168 /* Explicit Infinity values used when required: */
2169 #define FPINF_SINGLE (0x7F800000)
2170 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2171
2172 #if 1 /* def DEBUG */
2173 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2174 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2175 #endif /* DEBUG */
2176
2177 uword64
2178 value_fpr (SIM_DESC sd,
2179 sim_cpu *cpu,
2180 address_word cia,
2181 int fpr,
2182 FP_formats fmt)
2183 {
2184 uword64 value = 0;
2185 int err = 0;
2186
2187 /* Treat unused register values, as fixed-point 64bit values: */
2188 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2189 #if 1
2190 /* If request to read data as "uninterpreted", then use the current
2191 encoding: */
2192 fmt = FPR_STATE[fpr];
2193 #else
2194 fmt = fmt_long;
2195 #endif
2196
2197 /* For values not yet accessed, set to the desired format: */
2198 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2199 FPR_STATE[fpr] = fmt;
2200 #ifdef DEBUG
2201 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2202 #endif /* DEBUG */
2203 }
2204 if (fmt != FPR_STATE[fpr]) {
2205 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2206 FPR_STATE[fpr] = fmt_unknown;
2207 }
2208
2209 if (FPR_STATE[fpr] == fmt_unknown) {
2210 /* Set QNaN value: */
2211 switch (fmt) {
2212 case fmt_single:
2213 value = FPQNaN_SINGLE;
2214 break;
2215
2216 case fmt_double:
2217 value = FPQNaN_DOUBLE;
2218 break;
2219
2220 case fmt_word:
2221 value = FPQNaN_WORD;
2222 break;
2223
2224 case fmt_long:
2225 value = FPQNaN_LONG;
2226 break;
2227
2228 default:
2229 err = -1;
2230 break;
2231 }
2232 } else if (SizeFGR() == 64) {
2233 switch (fmt) {
2234 case fmt_single:
2235 case fmt_word:
2236 value = (FGR[fpr] & 0xFFFFFFFF);
2237 break;
2238
2239 case fmt_uninterpreted:
2240 case fmt_double:
2241 case fmt_long:
2242 value = FGR[fpr];
2243 break;
2244
2245 default :
2246 err = -1;
2247 break;
2248 }
2249 } else {
2250 switch (fmt) {
2251 case fmt_single:
2252 case fmt_word:
2253 value = (FGR[fpr] & 0xFFFFFFFF);
2254 break;
2255
2256 case fmt_uninterpreted:
2257 case fmt_double:
2258 case fmt_long:
2259 if ((fpr & 1) == 0) { /* even registers only */
2260 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2261 } else {
2262 SignalException(ReservedInstruction,0);
2263 }
2264 break;
2265
2266 default :
2267 err = -1;
2268 break;
2269 }
2270 }
2271
2272 if (err)
2273 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2274
2275 #ifdef DEBUG
2276 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2277 #endif /* DEBUG */
2278
2279 return(value);
2280 }
2281
2282 void
2283 store_fpr (SIM_DESC sd,
2284 sim_cpu *cpu,
2285 address_word cia,
2286 int fpr,
2287 FP_formats fmt,
2288 uword64 value)
2289 {
2290 int err = 0;
2291
2292 #ifdef DEBUG
2293 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2294 #endif /* DEBUG */
2295
2296 if (SizeFGR() == 64) {
2297 switch (fmt) {
2298 case fmt_uninterpreted_32:
2299 fmt = fmt_uninterpreted;
2300 case fmt_single :
2301 case fmt_word :
2302 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2303 FPR_STATE[fpr] = fmt;
2304 break;
2305
2306 case fmt_uninterpreted_64:
2307 fmt = fmt_uninterpreted;
2308 case fmt_uninterpreted:
2309 case fmt_double :
2310 case fmt_long :
2311 FGR[fpr] = value;
2312 FPR_STATE[fpr] = fmt;
2313 break;
2314
2315 default :
2316 FPR_STATE[fpr] = fmt_unknown;
2317 err = -1;
2318 break;
2319 }
2320 } else {
2321 switch (fmt) {
2322 case fmt_uninterpreted_32:
2323 fmt = fmt_uninterpreted;
2324 case fmt_single :
2325 case fmt_word :
2326 FGR[fpr] = (value & 0xFFFFFFFF);
2327 FPR_STATE[fpr] = fmt;
2328 break;
2329
2330 case fmt_uninterpreted_64:
2331 fmt = fmt_uninterpreted;
2332 case fmt_uninterpreted:
2333 case fmt_double :
2334 case fmt_long :
2335 if ((fpr & 1) == 0) { /* even register number only */
2336 FGR[fpr+1] = (value >> 32);
2337 FGR[fpr] = (value & 0xFFFFFFFF);
2338 FPR_STATE[fpr + 1] = fmt;
2339 FPR_STATE[fpr] = fmt;
2340 } else {
2341 FPR_STATE[fpr] = fmt_unknown;
2342 FPR_STATE[fpr + 1] = fmt_unknown;
2343 SignalException(ReservedInstruction,0);
2344 }
2345 break;
2346
2347 default :
2348 FPR_STATE[fpr] = fmt_unknown;
2349 err = -1;
2350 break;
2351 }
2352 }
2353 #if defined(WARN_RESULT)
2354 else
2355 UndefinedResult();
2356 #endif /* WARN_RESULT */
2357
2358 if (err)
2359 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2360
2361 #ifdef DEBUG
2362 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2363 #endif /* DEBUG */
2364
2365 return;
2366 }
2367
2368 int
2369 NaN(op,fmt)
2370 uword64 op;
2371 FP_formats fmt;
2372 {
2373 int boolean = 0;
2374 switch (fmt) {
2375 case fmt_single:
2376 case fmt_word:
2377 {
2378 sim_fpu wop;
2379 sim_fpu_32to (&wop, op);
2380 boolean = sim_fpu_is_nan (&wop);
2381 break;
2382 }
2383 case fmt_double:
2384 case fmt_long:
2385 {
2386 sim_fpu wop;
2387 sim_fpu_64to (&wop, op);
2388 boolean = sim_fpu_is_nan (&wop);
2389 break;
2390 }
2391 default:
2392 fprintf (stderr, "Bad switch\n");
2393 abort ();
2394 }
2395
2396 #ifdef DEBUG
2397 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2398 #endif /* DEBUG */
2399
2400 return(boolean);
2401 }
2402
2403 int
2404 Infinity(op,fmt)
2405 uword64 op;
2406 FP_formats fmt;
2407 {
2408 int boolean = 0;
2409
2410 #ifdef DEBUG
2411 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2412 #endif /* DEBUG */
2413
2414 switch (fmt) {
2415 case fmt_single:
2416 {
2417 sim_fpu wop;
2418 sim_fpu_32to (&wop, op);
2419 boolean = sim_fpu_is_infinity (&wop);
2420 break;
2421 }
2422 case fmt_double:
2423 {
2424 sim_fpu wop;
2425 sim_fpu_64to (&wop, op);
2426 boolean = sim_fpu_is_infinity (&wop);
2427 break;
2428 }
2429 default:
2430 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2431 break;
2432 }
2433
2434 #ifdef DEBUG
2435 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2436 #endif /* DEBUG */
2437
2438 return(boolean);
2439 }
2440
2441 int
2442 Less(op1,op2,fmt)
2443 uword64 op1;
2444 uword64 op2;
2445 FP_formats fmt;
2446 {
2447 int boolean = 0;
2448
2449 /* Argument checking already performed by the FPCOMPARE code */
2450
2451 #ifdef DEBUG
2452 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2453 #endif /* DEBUG */
2454
2455 /* The format type should already have been checked: */
2456 switch (fmt) {
2457 case fmt_single:
2458 {
2459 sim_fpu wop1;
2460 sim_fpu wop2;
2461 sim_fpu_32to (&wop1, op1);
2462 sim_fpu_32to (&wop2, op2);
2463 boolean = sim_fpu_is_lt (&wop1, &wop2);
2464 break;
2465 }
2466 case fmt_double:
2467 {
2468 sim_fpu wop1;
2469 sim_fpu wop2;
2470 sim_fpu_64to (&wop1, op1);
2471 sim_fpu_64to (&wop2, op2);
2472 boolean = sim_fpu_is_lt (&wop1, &wop2);
2473 break;
2474 }
2475 default:
2476 fprintf (stderr, "Bad switch\n");
2477 abort ();
2478 }
2479
2480 #ifdef DEBUG
2481 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2482 #endif /* DEBUG */
2483
2484 return(boolean);
2485 }
2486
2487 int
2488 Equal(op1,op2,fmt)
2489 uword64 op1;
2490 uword64 op2;
2491 FP_formats fmt;
2492 {
2493 int boolean = 0;
2494
2495 /* Argument checking already performed by the FPCOMPARE code */
2496
2497 #ifdef DEBUG
2498 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2499 #endif /* DEBUG */
2500
2501 /* The format type should already have been checked: */
2502 switch (fmt) {
2503 case fmt_single:
2504 {
2505 sim_fpu wop1;
2506 sim_fpu wop2;
2507 sim_fpu_32to (&wop1, op1);
2508 sim_fpu_32to (&wop2, op2);
2509 boolean = sim_fpu_is_eq (&wop1, &wop2);
2510 break;
2511 }
2512 case fmt_double:
2513 {
2514 sim_fpu wop1;
2515 sim_fpu wop2;
2516 sim_fpu_64to (&wop1, op1);
2517 sim_fpu_64to (&wop2, op2);
2518 boolean = sim_fpu_is_eq (&wop1, &wop2);
2519 break;
2520 }
2521 default:
2522 fprintf (stderr, "Bad switch\n");
2523 abort ();
2524 }
2525
2526 #ifdef DEBUG
2527 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2528 #endif /* DEBUG */
2529
2530 return(boolean);
2531 }
2532
2533 uword64
2534 AbsoluteValue(op,fmt)
2535 uword64 op;
2536 FP_formats fmt;
2537 {
2538 uword64 result = 0;
2539
2540 #ifdef DEBUG
2541 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2542 #endif /* DEBUG */
2543
2544 /* The format type should already have been checked: */
2545 switch (fmt) {
2546 case fmt_single:
2547 {
2548 sim_fpu wop;
2549 unsigned32 ans;
2550 sim_fpu_32to (&wop, op);
2551 sim_fpu_abs (&wop, &wop);
2552 sim_fpu_to32 (&ans, &wop);
2553 result = ans;
2554 break;
2555 }
2556 case fmt_double:
2557 {
2558 sim_fpu wop;
2559 unsigned64 ans;
2560 sim_fpu_64to (&wop, op);
2561 sim_fpu_abs (&wop, &wop);
2562 sim_fpu_to64 (&ans, &wop);
2563 result = ans;
2564 break;
2565 }
2566 default:
2567 fprintf (stderr, "Bad switch\n");
2568 abort ();
2569 }
2570
2571 return(result);
2572 }
2573
2574 uword64
2575 Negate(op,fmt)
2576 uword64 op;
2577 FP_formats fmt;
2578 {
2579 uword64 result = 0;
2580
2581 #ifdef DEBUG
2582 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2583 #endif /* DEBUG */
2584
2585 /* The format type should already have been checked: */
2586 switch (fmt) {
2587 case fmt_single:
2588 {
2589 sim_fpu wop;
2590 unsigned32 ans;
2591 sim_fpu_32to (&wop, op);
2592 sim_fpu_neg (&wop, &wop);
2593 sim_fpu_to32 (&ans, &wop);
2594 result = ans;
2595 break;
2596 }
2597 case fmt_double:
2598 {
2599 sim_fpu wop;
2600 unsigned64 ans;
2601 sim_fpu_64to (&wop, op);
2602 sim_fpu_neg (&wop, &wop);
2603 sim_fpu_to64 (&ans, &wop);
2604 result = ans;
2605 break;
2606 }
2607 default:
2608 fprintf (stderr, "Bad switch\n");
2609 abort ();
2610 }
2611
2612 return(result);
2613 }
2614
2615 uword64
2616 Add(op1,op2,fmt)
2617 uword64 op1;
2618 uword64 op2;
2619 FP_formats fmt;
2620 {
2621 uword64 result = 0;
2622
2623 #ifdef DEBUG
2624 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2625 #endif /* DEBUG */
2626
2627 /* The registers must specify FPRs valid for operands of type
2628 "fmt". If they are not valid, the result is undefined. */
2629
2630 /* The format type should already have been checked: */
2631 switch (fmt) {
2632 case fmt_single:
2633 {
2634 sim_fpu wop1;
2635 sim_fpu wop2;
2636 sim_fpu ans;
2637 unsigned32 res;
2638 sim_fpu_32to (&wop1, op1);
2639 sim_fpu_32to (&wop2, op2);
2640 sim_fpu_add (&ans, &wop1, &wop2);
2641 sim_fpu_to32 (&res, &ans);
2642 result = res;
2643 break;
2644 }
2645 case fmt_double:
2646 {
2647 sim_fpu wop1;
2648 sim_fpu wop2;
2649 sim_fpu ans;
2650 unsigned64 res;
2651 sim_fpu_64to (&wop1, op1);
2652 sim_fpu_64to (&wop2, op2);
2653 sim_fpu_add (&ans, &wop1, &wop2);
2654 sim_fpu_to64 (&res, &ans);
2655 result = res;
2656 break;
2657 }
2658 default:
2659 fprintf (stderr, "Bad switch\n");
2660 abort ();
2661 }
2662
2663 #ifdef DEBUG
2664 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2665 #endif /* DEBUG */
2666
2667 return(result);
2668 }
2669
2670 uword64
2671 Sub(op1,op2,fmt)
2672 uword64 op1;
2673 uword64 op2;
2674 FP_formats fmt;
2675 {
2676 uword64 result = 0;
2677
2678 #ifdef DEBUG
2679 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2680 #endif /* DEBUG */
2681
2682 /* The registers must specify FPRs valid for operands of type
2683 "fmt". If they are not valid, the result is undefined. */
2684
2685 /* The format type should already have been checked: */
2686 switch (fmt) {
2687 case fmt_single:
2688 {
2689 sim_fpu wop1;
2690 sim_fpu wop2;
2691 sim_fpu ans;
2692 unsigned32 res;
2693 sim_fpu_32to (&wop1, op1);
2694 sim_fpu_32to (&wop2, op2);
2695 sim_fpu_sub (&ans, &wop1, &wop2);
2696 sim_fpu_to32 (&res, &ans);
2697 result = res;
2698 }
2699 break;
2700 case fmt_double:
2701 {
2702 sim_fpu wop1;
2703 sim_fpu wop2;
2704 sim_fpu ans;
2705 unsigned64 res;
2706 sim_fpu_64to (&wop1, op1);
2707 sim_fpu_64to (&wop2, op2);
2708 sim_fpu_sub (&ans, &wop1, &wop2);
2709 sim_fpu_to64 (&res, &ans);
2710 result = res;
2711 }
2712 break;
2713 default:
2714 fprintf (stderr, "Bad switch\n");
2715 abort ();
2716 }
2717
2718 #ifdef DEBUG
2719 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2720 #endif /* DEBUG */
2721
2722 return(result);
2723 }
2724
2725 uword64
2726 Multiply(op1,op2,fmt)
2727 uword64 op1;
2728 uword64 op2;
2729 FP_formats fmt;
2730 {
2731 uword64 result = 0;
2732
2733 #ifdef DEBUG
2734 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2735 #endif /* DEBUG */
2736
2737 /* The registers must specify FPRs valid for operands of type
2738 "fmt". If they are not valid, the result is undefined. */
2739
2740 /* The format type should already have been checked: */
2741 switch (fmt) {
2742 case fmt_single:
2743 {
2744 sim_fpu wop1;
2745 sim_fpu wop2;
2746 sim_fpu ans;
2747 unsigned32 res;
2748 sim_fpu_32to (&wop1, op1);
2749 sim_fpu_32to (&wop2, op2);
2750 sim_fpu_mul (&ans, &wop1, &wop2);
2751 sim_fpu_to32 (&res, &ans);
2752 result = res;
2753 break;
2754 }
2755 case fmt_double:
2756 {
2757 sim_fpu wop1;
2758 sim_fpu wop2;
2759 sim_fpu ans;
2760 unsigned64 res;
2761 sim_fpu_64to (&wop1, op1);
2762 sim_fpu_64to (&wop2, op2);
2763 sim_fpu_mul (&ans, &wop1, &wop2);
2764 sim_fpu_to64 (&res, &ans);
2765 result = res;
2766 break;
2767 }
2768 default:
2769 fprintf (stderr, "Bad switch\n");
2770 abort ();
2771 }
2772
2773 #ifdef DEBUG
2774 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2775 #endif /* DEBUG */
2776
2777 return(result);
2778 }
2779
2780 uword64
2781 Divide(op1,op2,fmt)
2782 uword64 op1;
2783 uword64 op2;
2784 FP_formats fmt;
2785 {
2786 uword64 result = 0;
2787
2788 #ifdef DEBUG
2789 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2790 #endif /* DEBUG */
2791
2792 /* The registers must specify FPRs valid for operands of type
2793 "fmt". If they are not valid, the result is undefined. */
2794
2795 /* The format type should already have been checked: */
2796 switch (fmt) {
2797 case fmt_single:
2798 {
2799 sim_fpu wop1;
2800 sim_fpu wop2;
2801 sim_fpu ans;
2802 unsigned32 res;
2803 sim_fpu_32to (&wop1, op1);
2804 sim_fpu_32to (&wop2, op2);
2805 sim_fpu_div (&ans, &wop1, &wop2);
2806 sim_fpu_to32 (&res, &ans);
2807 result = res;
2808 break;
2809 }
2810 case fmt_double:
2811 {
2812 sim_fpu wop1;
2813 sim_fpu wop2;
2814 sim_fpu ans;
2815 unsigned64 res;
2816 sim_fpu_64to (&wop1, op1);
2817 sim_fpu_64to (&wop2, op2);
2818 sim_fpu_div (&ans, &wop1, &wop2);
2819 sim_fpu_to64 (&res, &ans);
2820 result = res;
2821 break;
2822 }
2823 default:
2824 fprintf (stderr, "Bad switch\n");
2825 abort ();
2826 }
2827
2828 #ifdef DEBUG
2829 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2830 #endif /* DEBUG */
2831
2832 return(result);
2833 }
2834
2835 uword64 UNUSED
2836 Recip(op,fmt)
2837 uword64 op;
2838 FP_formats fmt;
2839 {
2840 uword64 result = 0;
2841
2842 #ifdef DEBUG
2843 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2844 #endif /* DEBUG */
2845
2846 /* The registers must specify FPRs valid for operands of type
2847 "fmt". If they are not valid, the result is undefined. */
2848
2849 /* The format type should already have been checked: */
2850 switch (fmt) {
2851 case fmt_single:
2852 {
2853 sim_fpu wop;
2854 sim_fpu ans;
2855 unsigned32 res;
2856 sim_fpu_32to (&wop, op);
2857 sim_fpu_inv (&ans, &wop);
2858 sim_fpu_to32 (&res, &ans);
2859 result = res;
2860 break;
2861 }
2862 case fmt_double:
2863 {
2864 sim_fpu wop;
2865 sim_fpu ans;
2866 unsigned64 res;
2867 sim_fpu_64to (&wop, op);
2868 sim_fpu_inv (&ans, &wop);
2869 sim_fpu_to64 (&res, &ans);
2870 result = res;
2871 break;
2872 }
2873 default:
2874 fprintf (stderr, "Bad switch\n");
2875 abort ();
2876 }
2877
2878 #ifdef DEBUG
2879 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2880 #endif /* DEBUG */
2881
2882 return(result);
2883 }
2884
2885 uword64
2886 SquareRoot(op,fmt)
2887 uword64 op;
2888 FP_formats fmt;
2889 {
2890 uword64 result = 0;
2891
2892 #ifdef DEBUG
2893 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2894 #endif /* DEBUG */
2895
2896 /* The registers must specify FPRs valid for operands of type
2897 "fmt". If they are not valid, the result is undefined. */
2898
2899 /* The format type should already have been checked: */
2900 switch (fmt) {
2901 case fmt_single:
2902 {
2903 sim_fpu wop;
2904 sim_fpu ans;
2905 unsigned32 res;
2906 sim_fpu_32to (&wop, op);
2907 sim_fpu_sqrt (&ans, &wop);
2908 sim_fpu_to32 (&res, &ans);
2909 result = res;
2910 break;
2911 }
2912 case fmt_double:
2913 {
2914 sim_fpu wop;
2915 sim_fpu ans;
2916 unsigned64 res;
2917 sim_fpu_64to (&wop, op);
2918 sim_fpu_sqrt (&ans, &wop);
2919 sim_fpu_to64 (&res, &ans);
2920 result = res;
2921 break;
2922 }
2923 default:
2924 fprintf (stderr, "Bad switch\n");
2925 abort ();
2926 }
2927
2928 #ifdef DEBUG
2929 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2930 #endif /* DEBUG */
2931
2932 return(result);
2933 }
2934
2935 #if 0
2936 uword64
2937 Max (uword64 op1,
2938 uword64 op2,
2939 FP_formats fmt)
2940 {
2941 int cmp;
2942 unsigned64 result;
2943
2944 #ifdef DEBUG
2945 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2946 #endif /* DEBUG */
2947
2948 /* The registers must specify FPRs valid for operands of type
2949 "fmt". If they are not valid, the result is undefined. */
2950
2951 /* The format type should already have been checked: */
2952 switch (fmt)
2953 {
2954 case fmt_single:
2955 {
2956 sim_fpu wop1;
2957 sim_fpu wop2;
2958 sim_fpu_32to (&wop1, op1);
2959 sim_fpu_32to (&wop2, op2);
2960 cmp = sim_fpu_cmp (&wop1, &wop2);
2961 break;
2962 }
2963 case fmt_double:
2964 {
2965 sim_fpu wop1;
2966 sim_fpu wop2;
2967 sim_fpu_64to (&wop1, op1);
2968 sim_fpu_64to (&wop2, op2);
2969 cmp = sim_fpu_cmp (&wop1, &wop2);
2970 break;
2971 }
2972 default:
2973 fprintf (stderr, "Bad switch\n");
2974 abort ();
2975 }
2976
2977 switch (cmp)
2978 {
2979 case SIM_FPU_IS_SNAN:
2980 case SIM_FPU_IS_QNAN:
2981 result = op1;
2982 case SIM_FPU_IS_NINF:
2983 case SIM_FPU_IS_NNUMBER:
2984 case SIM_FPU_IS_NDENORM:
2985 case SIM_FPU_IS_NZERO:
2986 result = op2; /* op1 - op2 < 0 */
2987 case SIM_FPU_IS_PINF:
2988 case SIM_FPU_IS_PNUMBER:
2989 case SIM_FPU_IS_PDENORM:
2990 case SIM_FPU_IS_PZERO:
2991 result = op1; /* op1 - op2 > 0 */
2992 default:
2993 fprintf (stderr, "Bad switch\n");
2994 abort ();
2995 }
2996
2997 #ifdef DEBUG
2998 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2999 #endif /* DEBUG */
3000
3001 return(result);
3002 }
3003 #endif
3004
3005 #if 0
3006 uword64
3007 Min (uword64 op1,
3008 uword64 op2,
3009 FP_formats fmt)
3010 {
3011 int cmp;
3012 unsigned64 result;
3013
3014 #ifdef DEBUG
3015 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
3016 #endif /* DEBUG */
3017
3018 /* The registers must specify FPRs valid for operands of type
3019 "fmt". If they are not valid, the result is undefined. */
3020
3021 /* The format type should already have been checked: */
3022 switch (fmt)
3023 {
3024 case fmt_single:
3025 {
3026 sim_fpu wop1;
3027 sim_fpu wop2;
3028 sim_fpu_32to (&wop1, op1);
3029 sim_fpu_32to (&wop2, op2);
3030 cmp = sim_fpu_cmp (&wop1, &wop2);
3031 break;
3032 }
3033 case fmt_double:
3034 {
3035 sim_fpu wop1;
3036 sim_fpu wop2;
3037 sim_fpu_64to (&wop1, op1);
3038 sim_fpu_64to (&wop2, op2);
3039 cmp = sim_fpu_cmp (&wop1, &wop2);
3040 break;
3041 }
3042 default:
3043 fprintf (stderr, "Bad switch\n");
3044 abort ();
3045 }
3046
3047 switch (cmp)
3048 {
3049 case SIM_FPU_IS_SNAN:
3050 case SIM_FPU_IS_QNAN:
3051 result = op1;
3052 case SIM_FPU_IS_NINF:
3053 case SIM_FPU_IS_NNUMBER:
3054 case SIM_FPU_IS_NDENORM:
3055 case SIM_FPU_IS_NZERO:
3056 result = op1; /* op1 - op2 < 0 */
3057 case SIM_FPU_IS_PINF:
3058 case SIM_FPU_IS_PNUMBER:
3059 case SIM_FPU_IS_PDENORM:
3060 case SIM_FPU_IS_PZERO:
3061 result = op2; /* op1 - op2 > 0 */
3062 default:
3063 fprintf (stderr, "Bad switch\n");
3064 abort ();
3065 }
3066
3067 #ifdef DEBUG
3068 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
3069 #endif /* DEBUG */
3070
3071 return(result);
3072 }
3073 #endif
3074
3075 uword64
3076 convert (SIM_DESC sd,
3077 sim_cpu *cpu,
3078 address_word cia,
3079 int rm,
3080 uword64 op,
3081 FP_formats from,
3082 FP_formats to)
3083 {
3084 sim_fpu wop;
3085 sim_fpu_round round;
3086 unsigned32 result32;
3087 unsigned64 result64;
3088
3089 #ifdef DEBUG
3090 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
3091 #endif /* DEBUG */
3092
3093 switch (rm)
3094 {
3095 case FP_RM_NEAREST:
3096 /* Round result to nearest representable value. When two
3097 representable values are equally near, round to the value
3098 that has a least significant bit of zero (i.e. is even). */
3099 round = sim_fpu_round_near;
3100 break;
3101 case FP_RM_TOZERO:
3102 /* Round result to the value closest to, and not greater in
3103 magnitude than, the result. */
3104 round = sim_fpu_round_zero;
3105 break;
3106 case FP_RM_TOPINF:
3107 /* Round result to the value closest to, and not less than,
3108 the result. */
3109 round = sim_fpu_round_up;
3110 break;
3111
3112 case FP_RM_TOMINF:
3113 /* Round result to the value closest to, and not greater than,
3114 the result. */
3115 round = sim_fpu_round_down;
3116 break;
3117 default:
3118 round = 0;
3119 fprintf (stderr, "Bad switch\n");
3120 abort ();
3121 }
3122
3123 /* Convert the input to sim_fpu internal format */
3124 switch (from)
3125 {
3126 case fmt_double:
3127 sim_fpu_64to (&wop, op);
3128 break;
3129 case fmt_single:
3130 sim_fpu_32to (&wop, op);
3131 break;
3132 case fmt_word:
3133 sim_fpu_i32to (&wop, op, round);
3134 break;
3135 case fmt_long:
3136 sim_fpu_i64to (&wop, op, round);
3137 break;
3138 default:
3139 fprintf (stderr, "Bad switch\n");
3140 abort ();
3141 }
3142
3143 /* Convert sim_fpu format into the output */
3144 /* The value WOP is converted to the destination format, rounding
3145 using mode RM. When the destination is a fixed-point format, then
3146 a source value of Infinity, NaN or one which would round to an
3147 integer outside the fixed point range then an IEEE Invalid
3148 Operation condition is raised. */
3149 switch (to)
3150 {
3151 case fmt_single:
3152 sim_fpu_round_32 (&wop, round, 0);
3153 sim_fpu_to32 (&result32, &wop);
3154 result64 = result32;
3155 break;
3156 case fmt_double:
3157 sim_fpu_round_64 (&wop, round, 0);
3158 sim_fpu_to64 (&result64, &wop);
3159 break;
3160 case fmt_word:
3161 sim_fpu_to32i (&result32, &wop, round);
3162 result64 = result32;
3163 break;
3164 case fmt_long:
3165 sim_fpu_to64i (&result64, &wop, round);
3166 break;
3167 default:
3168 result64 = 0;
3169 fprintf (stderr, "Bad switch\n");
3170 abort ();
3171 }
3172
3173 #ifdef DEBUG
3174 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
3175 #endif /* DEBUG */
3176
3177 return(result64);
3178 }
3179
3180
3181 /*-- co-processor support routines ------------------------------------------*/
3182
3183 static int UNUSED
3184 CoProcPresent(coproc_number)
3185 unsigned int coproc_number;
3186 {
3187 /* Return TRUE if simulator provides a model for the given co-processor number */
3188 return(0);
3189 }
3190
3191 void
3192 cop_lw (SIM_DESC sd,
3193 sim_cpu *cpu,
3194 address_word cia,
3195 int coproc_num,
3196 int coproc_reg,
3197 unsigned int memword)
3198 {
3199 switch (coproc_num)
3200 {
3201 case 1:
3202 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3203 {
3204 #ifdef DEBUG
3205 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3206 #endif
3207 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3208 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3209 break;
3210 }
3211
3212 default:
3213 #if 0 /* this should be controlled by a configuration option */
3214 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3215 #endif
3216 break;
3217 }
3218
3219 return;
3220 }
3221
3222 void
3223 cop_ld (SIM_DESC sd,
3224 sim_cpu *cpu,
3225 address_word cia,
3226 int coproc_num,
3227 int coproc_reg,
3228 uword64 memword)
3229 {
3230 switch (coproc_num) {
3231 case 1:
3232 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3233 {
3234 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3235 break;
3236 }
3237
3238 default:
3239 #if 0 /* this message should be controlled by a configuration option */
3240 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3241 #endif
3242 break;
3243 }
3244
3245 return;
3246 }
3247
3248 unsigned int
3249 cop_sw (SIM_DESC sd,
3250 sim_cpu *cpu,
3251 address_word cia,
3252 int coproc_num,
3253 int coproc_reg)
3254 {
3255 unsigned int value = 0;
3256
3257 switch (coproc_num)
3258 {
3259 case 1:
3260 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3261 {
3262 FP_formats hold;
3263 hold = FPR_STATE[coproc_reg];
3264 FPR_STATE[coproc_reg] = fmt_word;
3265 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3266 FPR_STATE[coproc_reg] = hold;
3267 break;
3268 }
3269
3270 default:
3271 #if 0 /* should be controlled by configuration option */
3272 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3273 #endif
3274 break;
3275 }
3276
3277 return(value);
3278 }
3279
3280 uword64
3281 cop_sd (SIM_DESC sd,
3282 sim_cpu *cpu,
3283 address_word cia,
3284 int coproc_num,
3285 int coproc_reg)
3286 {
3287 uword64 value = 0;
3288 switch (coproc_num)
3289 {
3290 case 1:
3291 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3292 {
3293 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3294 break;
3295 }
3296
3297 default:
3298 #if 0 /* should be controlled by configuration option */
3299 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3300 #endif
3301 break;
3302 }
3303
3304 return(value);
3305 }
3306
3307 void
3308 decode_coproc (SIM_DESC sd,
3309 sim_cpu *cpu,
3310 address_word cia,
3311 unsigned int instruction)
3312 {
3313 int coprocnum = ((instruction >> 26) & 3);
3314
3315 switch (coprocnum)
3316 {
3317 case 0: /* standard CPU control and cache registers */
3318 {
3319 int code = ((instruction >> 21) & 0x1F);
3320 /* R4000 Users Manual (second edition) lists the following CP0
3321 instructions:
3322 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3323 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3324 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3325 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3326 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3327 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3328 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3329 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3330 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3331 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3332 */
3333 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
3334 {
3335 int rt = ((instruction >> 16) & 0x1F);
3336 int rd = ((instruction >> 11) & 0x1F);
3337
3338 switch (rd) /* NOTEs: Standard CP0 registers */
3339 {
3340 /* 0 = Index R4000 VR4100 VR4300 */
3341 /* 1 = Random R4000 VR4100 VR4300 */
3342 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3343 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3344 /* 4 = Context R4000 VR4100 VR4300 */
3345 /* 5 = PageMask R4000 VR4100 VR4300 */
3346 /* 6 = Wired R4000 VR4100 VR4300 */
3347 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3348 /* 9 = Count R4000 VR4100 VR4300 */
3349 /* 10 = EntryHi R4000 VR4100 VR4300 */
3350 /* 11 = Compare R4000 VR4100 VR4300 */
3351 /* 12 = SR R4000 VR4100 VR4300 */
3352 case 12:
3353 if (code == 0x00)
3354 GPR[rt] = SR;
3355 else
3356 SR = GPR[rt];
3357 break;
3358 /* 13 = Cause R4000 VR4100 VR4300 */
3359 case 13:
3360 if (code == 0x00)
3361 GPR[rt] = CAUSE;
3362 else
3363 CAUSE = GPR[rt];
3364 break;
3365 /* 14 = EPC R4000 VR4100 VR4300 */
3366 /* 15 = PRId R4000 VR4100 VR4300 */
3367 #ifdef SUBTARGET_R3900
3368 /* 16 = Debug */
3369 case 16:
3370 if (code == 0x00)
3371 GPR[rt] = Debug;
3372 else
3373 Debug = GPR[rt];
3374 break;
3375 #else
3376 /* 16 = Config R4000 VR4100 VR4300 */
3377 case 16:
3378 if (code == 0x00)
3379 GPR[rt] = C0_CONFIG;
3380 else
3381 C0_CONFIG = GPR[rt];
3382 break;
3383 #endif
3384 #ifdef SUBTARGET_R3900
3385 /* 17 = Debug */
3386 case 17:
3387 if (code == 0x00)
3388 GPR[rt] = DEPC;
3389 else
3390 DEPC = GPR[rt];
3391 break;
3392 #else
3393 /* 17 = LLAddr R4000 VR4100 VR4300 */
3394 #endif
3395 /* 18 = WatchLo R4000 VR4100 VR4300 */
3396 /* 19 = WatchHi R4000 VR4100 VR4300 */
3397 /* 20 = XContext R4000 VR4100 VR4300 */
3398 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3399 /* 27 = CacheErr R4000 VR4100 */
3400 /* 28 = TagLo R4000 VR4100 VR4300 */
3401 /* 29 = TagHi R4000 VR4100 VR4300 */
3402 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3403 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3404 /* CPR[0,rd] = GPR[rt]; */
3405 default:
3406 if (code == 0x00)
3407 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3408 else
3409 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3410 }
3411 }
3412 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3413 {
3414 /* ERET */
3415 if (SR & status_ERL)
3416 {
3417 /* Oops, not yet available */
3418 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3419 PC = EPC;
3420 SR &= ~status_ERL;
3421 }
3422 else
3423 {
3424 PC = EPC;
3425 SR &= ~status_EXL;
3426 }
3427 }
3428 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3429 {
3430 /* RFE */
3431 }
3432 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3433 {
3434 /* DERET */
3435 Debug &= ~Debug_DM;
3436 DELAYSLOT();
3437 DSPC = DEPC;
3438 }
3439 else
3440 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3441 /* TODO: When executing an ERET or RFE instruction we should
3442 clear LLBIT, to ensure that any out-standing atomic
3443 read/modify/write sequence fails. */
3444 }
3445 break;
3446
3447 case 2: /* undefined co-processor */
3448 sim_io_eprintf(sd,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3449 break;
3450
3451 case 1: /* should not occur (FPU co-processor) */
3452 case 3: /* should not occur (FPU co-processor) */
3453 SignalException(ReservedInstruction,instruction);
3454 break;
3455 }
3456
3457 return;
3458 }
3459
3460 /*-- instruction simulation -------------------------------------------------*/
3461
3462 /* When the IGEN simulator is being built, the function below is be
3463 replaced by a generated version. However, WITH_IGEN == 2 indicates
3464 that the fubction below should be compiled but under a different
3465 name (to allow backward compatibility) */
3466
3467 #if (WITH_IGEN != 1)
3468 #if (WITH_IGEN > 1)
3469 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3470 void
3471 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3472 #else
3473 void
3474 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3475 #endif
3476 SIM_DESC sd;
3477 int next_cpu_nr; /* ignore */
3478 int nr_cpus; /* ignore */
3479 int siggnal; /* ignore */
3480 {
3481 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3482 #if !defined(FASTSIM)
3483 unsigned int pipeline_count = 1;
3484 #endif
3485
3486 #ifdef DEBUG
3487 if (STATE_MEMORY (sd) == NULL) {
3488 printf("DBG: simulate() entered with no memory\n");
3489 exit(1);
3490 }
3491 #endif /* DEBUG */
3492
3493 #if 0 /* Disabled to check that everything works OK */
3494 /* The VR4300 seems to sign-extend the PC on its first
3495 access. However, this may just be because it is currently
3496 configured in 32bit mode. However... */
3497 PC = SIGNEXTEND(PC,32);
3498 #endif
3499
3500 /* main controlling loop */
3501 while (1) {
3502 /* vaddr is slowly being replaced with cia - current instruction
3503 address */
3504 address_word cia = (uword64)PC;
3505 address_word vaddr = cia;
3506 address_word paddr;
3507 int cca;
3508 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3509
3510 #ifdef DEBUG
3511 {
3512 printf("DBG: state = 0x%08X :",state);
3513 if (state & simHALTEX) printf(" simHALTEX");
3514 if (state & simHALTIN) printf(" simHALTIN");
3515 printf("\n");
3516 }
3517 #endif /* DEBUG */
3518
3519 DSSTATE = (STATE & simDELAYSLOT);
3520 #ifdef DEBUG
3521 if (dsstate)
3522 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3523 #endif /* DEBUG */
3524
3525 /* Fetch the next instruction from the simulator memory: */
3526 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3527 if ((vaddr & 1) == 0) {
3528 /* Copy the action of the LW instruction */
3529 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3530 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3531 uword64 value;
3532 unsigned int byte;
3533 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3534 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3535 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3536 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3537 } else {
3538 /* Copy the action of the LH instruction */
3539 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3540 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3541 uword64 value;
3542 unsigned int byte;
3543 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3544 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3545 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3546 paddr & ~ (uword64) 1,
3547 vaddr, isINSTRUCTION, isREAL);
3548 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3549 instruction = ((value >> (8 * byte)) & 0xFFFF);
3550 }
3551 } else {
3552 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3553 exit(1);
3554 }
3555
3556 #ifdef DEBUG
3557 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3558 #endif /* DEBUG */
3559
3560 /* This is required by exception processing, to ensure that we can
3561 cope with exceptions in the delay slots of branches that may
3562 already have changed the PC. */
3563 if ((vaddr & 1) == 0)
3564 PC += 4; /* increment ready for the next fetch */
3565 else
3566 PC += 2;
3567 /* NOTE: If we perform a delay slot change to the PC, this
3568 increment is not requuired. However, it would make the
3569 simulator more complicated to try and avoid this small hit. */
3570
3571 /* Currently this code provides a simple model. For more
3572 complicated models we could perform exception status checks at
3573 this point, and set the simSTOP state as required. This could
3574 also include processing any hardware interrupts raised by any
3575 I/O model attached to the simulator context.
3576
3577 Support for "asynchronous" I/O events within the simulated world
3578 could be providing by managing a counter, and calling a I/O
3579 specific handler when a particular threshold is reached. On most
3580 architectures a decrement and check for zero operation is
3581 usually quicker than an increment and compare. However, the
3582 process of managing a known value decrement to zero, is higher
3583 than the cost of using an explicit value UINT_MAX into the
3584 future. Which system is used will depend on how complicated the
3585 I/O model is, and how much it is likely to affect the simulator
3586 bandwidth.
3587
3588 If events need to be scheduled further in the future than
3589 UINT_MAX event ticks, then the I/O model should just provide its
3590 own counter, triggered from the event system. */
3591
3592 /* MIPS pipeline ticks. To allow for future support where the
3593 pipeline hit of individual instructions is known, this control
3594 loop manages a "pipeline_count" variable. It is initialised to
3595 1 (one), and will only be changed by the simulator engine when
3596 executing an instruction. If the engine does not have access to
3597 pipeline cycle count information then all instructions will be
3598 treated as using a single cycle. NOTE: A standard system is not
3599 provided by the default simulator because different MIPS
3600 architectures have different cycle counts for the same
3601 instructions.
3602
3603 [NOTE: pipeline_count has been replaced the event queue] */
3604
3605 /* shuffle the floating point status pipeline state */
3606 ENGINE_ISSUE_PREFIX_HOOK();
3607
3608 /* NOTE: For multi-context simulation environments the "instruction"
3609 variable should be local to this routine. */
3610
3611 /* Shorthand accesses for engine. Note: If we wanted to use global
3612 variables (and a single-threaded simulator engine), then we can
3613 create the actual variables with these names. */
3614
3615 if (!(STATE & simSKIPNEXT)) {
3616 /* Include the simulator engine */
3617 #include "oengine.c"
3618 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3619 #error "Mismatch between run-time simulator code and simulation engine"
3620 #endif
3621 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3622 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3623 #endif
3624 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3625 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3626 #endif
3627
3628 #if defined(WARN_LOHI)
3629 /* Decrement the HI/LO validity ticks */
3630 if (HIACCESS > 0)
3631 HIACCESS--;
3632 if (LOACCESS > 0)
3633 LOACCESS--;
3634 /* start-sanitize-r5900 */
3635 if (HI1ACCESS > 0)
3636 HI1ACCESS--;
3637 if (LO1ACCESS > 0)
3638 LO1ACCESS--;
3639 /* end-sanitize-r5900 */
3640 #endif /* WARN_LOHI */
3641
3642 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3643 should check for it being changed. It is better doing it here,
3644 than within the simulator, since it will help keep the simulator
3645 small. */
3646 if (ZERO != 0) {
3647 #if defined(WARN_ZERO)
3648 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3649 #endif /* WARN_ZERO */
3650 ZERO = 0; /* reset back to zero before next instruction */
3651 }
3652 } else /* simSKIPNEXT check */
3653 STATE &= ~simSKIPNEXT;
3654
3655 /* If the delay slot was active before the instruction is
3656 executed, then update the PC to its new value: */
3657 if (DSSTATE) {
3658 #ifdef DEBUG
3659 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3660 #endif /* DEBUG */
3661 PC = DSPC;
3662 CANCELDELAYSLOT();
3663 }
3664
3665 if (MIPSISA < 4)
3666 PENDING_TICK();
3667
3668 #if !defined(FASTSIM)
3669 if (sim_events_tickn (sd, pipeline_count))
3670 {
3671 /* cpu->cia = cia; */
3672 sim_events_process (sd);
3673 }
3674 #else
3675 if (sim_events_tick (sd))
3676 {
3677 /* cpu->cia = cia; */
3678 sim_events_process (sd);
3679 }
3680 #endif /* FASTSIM */
3681 }
3682 }
3683 #endif
3684
3685
3686 /* This code copied from gdb's utils.c. Would like to share this code,
3687 but don't know of a common place where both could get to it. */
3688
3689 /* Temporary storage using circular buffer */
3690 #define NUMCELLS 16
3691 #define CELLSIZE 32
3692 static char*
3693 get_cell()
3694 {
3695 static char buf[NUMCELLS][CELLSIZE];
3696 static int cell=0;
3697 if (++cell>=NUMCELLS) cell=0;
3698 return buf[cell];
3699 }
3700
3701 /* Print routines to handle variable size regs, etc */
3702
3703 /* Eliminate warning from compiler on 32-bit systems */
3704 static int thirty_two = 32;
3705
3706 char*
3707 pr_addr(addr)
3708 SIM_ADDR addr;
3709 {
3710 char *paddr_str=get_cell();
3711 switch (sizeof(addr))
3712 {
3713 case 8:
3714 sprintf(paddr_str,"%08lx%08lx",
3715 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3716 break;
3717 case 4:
3718 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3719 break;
3720 case 2:
3721 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3722 break;
3723 default:
3724 sprintf(paddr_str,"%x",addr);
3725 }
3726 return paddr_str;
3727 }
3728
3729 char*
3730 pr_uword64(addr)
3731 uword64 addr;
3732 {
3733 char *paddr_str=get_cell();
3734 sprintf(paddr_str,"%08lx%08lx",
3735 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3736 return paddr_str;
3737 }
3738
3739
3740 void
3741 pending_tick (SIM_DESC sd,
3742 sim_cpu *cpu,
3743 address_word cia)
3744 {
3745 if (PENDING_TRACE)
3746 sim_io_printf (sd, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN, PENDING_OUT, PENDING_TOTAL);
3747 if (PENDING_OUT != PENDING_IN)
3748 {
3749 int loop;
3750 int index = PENDING_OUT;
3751 int total = PENDING_TOTAL;
3752 if (PENDING_TOTAL == 0)
3753 sim_engine_abort (SD, CPU, cia, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3754 for (loop = 0; (loop < total); loop++)
3755 {
3756 if (PENDING_SLOT_DEST[index] != NULL)
3757 {
3758 PENDING_SLOT_DELAY[index] -= 1;
3759 if (PENDING_SLOT_DELAY[index] == 0)
3760 {
3761 if (PENDING_SLOT_BIT[index] >= 0)
3762 switch (PENDING_SLOT_SIZE[index])
3763 {
3764 case 32:
3765 if (PENDING_SLOT_VALUE[index])
3766 *(unsigned32*)PENDING_SLOT_DEST[index] |=
3767 BIT32 (PENDING_SLOT_BIT[index]);
3768 else
3769 *(unsigned32*)PENDING_SLOT_DEST[index] &=
3770 BIT32 (PENDING_SLOT_BIT[index]);
3771 break;
3772 case 64:
3773 if (PENDING_SLOT_VALUE[index])
3774 *(unsigned64*)PENDING_SLOT_DEST[index] |=
3775 BIT64 (PENDING_SLOT_BIT[index]);
3776 else
3777 *(unsigned64*)PENDING_SLOT_DEST[index] &=
3778 BIT64 (PENDING_SLOT_BIT[index]);
3779 break;
3780 break;
3781 }
3782 else
3783 switch (PENDING_SLOT_SIZE[index])
3784 {
3785 case 32:
3786 *(unsigned32*)PENDING_SLOT_DEST[index] =
3787 PENDING_SLOT_VALUE[index];
3788 break;
3789 case 64:
3790 *(unsigned64*)PENDING_SLOT_DEST[index] =
3791 PENDING_SLOT_VALUE[index];
3792 break;
3793 }
3794 }
3795 if (PENDING_OUT == index)
3796 {
3797 PENDING_SLOT_DEST[index] = NULL;
3798 PENDING_OUT = (PENDING_OUT + 1) % PSLOTS;
3799 PENDING_TOTAL--;
3800 }
3801 }
3802 }
3803 index = (index + 1) % PSLOTS;
3804 }
3805 }
3806
3807 /*---------------------------------------------------------------------------*/
3808 /*> EOF interp.c <*/