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* Handle 10 and 20-bit versions of Break instruction. Move handling
[binutils-gdb.git] / sim / mips / interp.c
1 /*> interp.c <*/
2 /* Simulator for the MIPS architecture.
3
4 This file is part of the MIPS sim
5
6 THIS SOFTWARE IS NOT COPYRIGHTED
7
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
11
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
15
16 $Revision$
17 $Date$
18
19 NOTEs:
20
21 The IDT monitor (found on the VR4300 board), seems to lie about
22 register contents. It seems to treat the registers as sign-extended
23 32-bit values. This cause *REAL* problems when single-stepping 64-bit
24 code on the hardware.
25
26 */
27
28 /* The TRACE manifests enable the provision of extra features. If they
29 are not defined then a simpler (quicker) simulator is constructed
30 without the required run-time checks, etc. */
31 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
32 #define TRACE (1)
33 #endif
34
35 #include "bfd.h"
36 #include "sim-main.h"
37 #include "sim-utils.h"
38 #include "sim-options.h"
39 #include "sim-assert.h"
40 #include "sim-hw.h"
41
42 /* start-sanitize-sky */
43 #ifdef TARGET_SKY
44 #include "sky-vu.h"
45 #include "sky-vpe.h"
46 #include "sky-libvpe.h"
47 #include "sky-pke.h"
48 #include "sky-gpuif.h"
49 #include "idecode.h"
50 #include "support.h"
51 #undef SD
52 #endif
53 /* end-sanitize-sky */
54
55 #include "config.h"
56
57 #include <stdio.h>
58 #include <stdarg.h>
59 #include <ansidecl.h>
60 #include <ctype.h>
61 #include <limits.h>
62 #include <math.h>
63 #ifdef HAVE_STDLIB_H
64 #include <stdlib.h>
65 #endif
66 #ifdef HAVE_STRING_H
67 #include <string.h>
68 #else
69 #ifdef HAVE_STRINGS_H
70 #include <strings.h>
71 #endif
72 #endif
73
74 #include "getopt.h"
75 #include "libiberty.h"
76 #include "bfd.h"
77 #include "callback.h" /* GDB simulator callback interface */
78 #include "remote-sim.h" /* GDB simulator interface */
79
80 #include "sysdep.h"
81
82 #ifndef PARAMS
83 #define PARAMS(x)
84 #endif
85
86 char* pr_addr PARAMS ((SIM_ADDR addr));
87 char* pr_uword64 PARAMS ((uword64 addr));
88
89
90 /* Get the simulator engine description, without including the code: */
91 #if !(WITH_IGEN)
92 #define SIM_MANIFESTS
93 #include "oengine.c"
94 #undef SIM_MANIFESTS
95 #endif
96
97 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
98 #define CPU cpu
99 #define SD sd
100
101
102 /* The following reserved instruction value is used when a simulator
103 trap is required. NOTE: Care must be taken, since this value may be
104 used in later revisions of the MIPS ISA. */
105
106 #define RSVD_INSTRUCTION (0x00000005)
107 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
108
109 #define RSVD_INSTRUCTION_ARG_SHIFT 6
110 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
111
112
113 /* Bits in the Debug register */
114 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
115 #define Debug_DM 0x40000000 /* Debug Mode */
116 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
117
118 /*---------------------------------------------------------------------------*/
119 /*-- GDB simulator interface ------------------------------------------------*/
120 /*---------------------------------------------------------------------------*/
121
122 static void ColdReset PARAMS((SIM_DESC sd));
123
124 /*---------------------------------------------------------------------------*/
125
126
127
128 #define DELAYSLOT() {\
129 if (STATE & simDELAYSLOT)\
130 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
131 STATE |= simDELAYSLOT;\
132 }
133
134 #define JALDELAYSLOT() {\
135 DELAYSLOT ();\
136 STATE |= simJALDELAYSLOT;\
137 }
138
139 #define NULLIFY() {\
140 STATE &= ~simDELAYSLOT;\
141 STATE |= simSKIPNEXT;\
142 }
143
144 #define CANCELDELAYSLOT() {\
145 DSSTATE = 0;\
146 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
147 }
148
149 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
150 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
151
152 #define K0BASE (0x80000000)
153 #define K0SIZE (0x20000000)
154 #define K1BASE (0xA0000000)
155 #define K1SIZE (0x20000000)
156 #define MONITOR_BASE (0xBFC00000)
157 #define MONITOR_SIZE (1 << 11)
158 #define MEM_SIZE (2 << 20)
159
160 /* start-sanitize-sky */
161 #ifdef TARGET_SKY
162 #undef MEM_SIZE
163 #define MEM_SIZE (16 << 20) /* 16 MB */
164 #endif
165 /* end-sanitize-sky */
166
167 #if defined(TRACE)
168 static char *tracefile = "trace.din"; /* default filename for trace log */
169 FILE *tracefh = NULL;
170 static void open_trace PARAMS((SIM_DESC sd));
171 #endif /* TRACE */
172
173 /* simulation target board. NULL=canonical */
174 static char* board = NULL;
175
176
177 static DECLARE_OPTION_HANDLER (mips_option_handler);
178
179 enum {
180 OPTION_DINERO_TRACE = OPTION_START,
181 OPTION_DINERO_FILE
182 /* start-sanitize-sky */
183 #ifdef TARGET_SKY
184 #ifdef SKY_FUNIT
185 ,OPTION_FLOAT_TYPE
186 #endif
187 ,OPTION_GS_ENABLE
188 ,OPTION_GS_REFRESH1
189 ,OPTION_GS_REFRESH2
190 #endif
191 /* end-sanitize-sky */
192 ,OPTION_BOARD
193 };
194
195
196 static SIM_RC
197 mips_option_handler (sd, cpu, opt, arg, is_command)
198 SIM_DESC sd;
199 sim_cpu *cpu;
200 int opt;
201 char *arg;
202 int is_command;
203 {
204 int cpu_nr;
205 switch (opt)
206 {
207 case OPTION_DINERO_TRACE: /* ??? */
208 #if defined(TRACE)
209 /* Eventually the simTRACE flag could be treated as a toggle, to
210 allow external control of the program points being traced
211 (i.e. only from main onwards, excluding the run-time setup,
212 etc.). */
213 for (cpu_nr = 0; cpu_nr < MAX_NR_PROCESSORS; cpu_nr++)
214 {
215 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
216 if (arg == NULL)
217 STATE |= simTRACE;
218 else if (strcmp (arg, "yes") == 0)
219 STATE |= simTRACE;
220 else if (strcmp (arg, "no") == 0)
221 STATE &= ~simTRACE;
222 else if (strcmp (arg, "on") == 0)
223 STATE |= simTRACE;
224 else if (strcmp (arg, "off") == 0)
225 STATE &= ~simTRACE;
226 else
227 {
228 fprintf (stderr, "Unrecognized dinero-trace option `%s'\n", arg);
229 return SIM_RC_FAIL;
230 }
231 }
232 return SIM_RC_OK;
233 #else /* !TRACE */
234 fprintf(stderr,"\
235 Simulator constructed without dinero tracing support (for performance).\n\
236 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
237 return SIM_RC_FAIL;
238 #endif /* !TRACE */
239
240 case OPTION_DINERO_FILE:
241 #if defined(TRACE)
242 if (optarg != NULL) {
243 char *tmp;
244 tmp = (char *)malloc(strlen(optarg) + 1);
245 if (tmp == NULL)
246 {
247 sim_io_printf(sd,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg);
248 return SIM_RC_FAIL;
249 }
250 else {
251 strcpy(tmp,optarg);
252 tracefile = tmp;
253 sim_io_printf(sd,"Placing trace information into file \"%s\"\n",tracefile);
254 }
255 }
256 #endif /* TRACE */
257 return SIM_RC_OK;
258
259 /* start-sanitize-sky */
260 #ifdef TARGET_SKY
261 #ifdef SKY_FUNIT
262 case OPTION_FLOAT_TYPE:
263 /* Use host (fast) or target (accurate) floating point implementation. */
264 if (arg && strcmp (arg, "fast") == 0)
265 STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_ACCURATE;
266 else if (arg && strcmp (arg, "accurate") == 0)
267 STATE_FP_TYPE_OPT (sd) |= STATE_FP_TYPE_OPT_ACCURATE;
268 else
269 {
270 fprintf (stderr, "Unrecognized float-type option `%s'\n", arg);
271 return SIM_RC_FAIL;
272 }
273 /*printf ("float-type=0x%08x\n", STATE_FP_TYPE_OPT (sd));*/
274 return SIM_RC_OK;
275 #endif
276
277 case OPTION_GS_ENABLE:
278 /* Enable GS libraries. */
279 if ( arg && strcmp (arg, "on") == 0 )
280 gif_options (&GIF_full,GIF_OPT_GS_ENABLE,1,0,0);
281 else if ( arg && strcmp (arg, "off") == 0 )
282 gif_options (&GIF_full,GIF_OPT_GS_ENABLE,0,0,0);
283 else
284 {
285 fprintf (stderr, "Unrecognized enable-gs option `%s'\n", arg);
286 return SIM_RC_FAIL;
287 }
288 return SIM_RC_OK;
289
290 case OPTION_GS_REFRESH1:
291 case OPTION_GS_REFRESH2:
292 {
293 /* The GS has defineable register and register values. */
294 unsigned_4 address[2];
295 long long value[2];
296 char c[3];
297
298 if ( arg && strlen (arg) == 59 && arg[10] == '=' &&
299 arg[29] == ':' && arg[40] == '=' &&
300 ( sscanf (arg,"%lx%c%Lx%c%lx%c%Lx", &address[0],&c[0],&value[0],
301 &c[1],&address[1],&c[2],&value[1]) == 7 ))
302 {
303 gif_options (&GIF_full, ( opt == OPTION_GS_REFRESH1 ) ?
304 GIF_OPT_GS_REFRESH1:GIF_OPT_GS_REFRESH2,
305 0,&address[0],&value[0]);
306 }
307 else
308 {
309 fprintf (stderr, "Unrecognized gs-refresh option `%s'\n", arg);
310 return SIM_RC_FAIL;
311 }
312 }
313 return SIM_RC_OK;
314
315 #endif
316 /* end-sanitize-sky */
317
318 case OPTION_BOARD:
319 {
320 if (arg)
321 {
322 board = zalloc(strlen(arg) + 1);
323 strcpy(board, arg);
324 }
325 return SIM_RC_OK;
326 }
327 }
328
329 return SIM_RC_OK;
330 }
331
332
333 static const OPTION mips_options[] =
334 {
335 { {"dinero-trace", optional_argument, NULL, OPTION_DINERO_TRACE},
336 '\0', "on|off", "Enable dinero tracing",
337 mips_option_handler },
338 { {"dinero-file", required_argument, NULL, OPTION_DINERO_FILE},
339 '\0', "FILE", "Write dinero trace to FILE",
340 mips_option_handler },
341 /* start-sanitize-sky */
342 #ifdef TARGET_SKY
343 #ifdef SKY_FUNIT
344 { {"float-type", required_argument, NULL, OPTION_FLOAT_TYPE},
345 '\0', "fast|accurate", "Use fast (host) or accurate (target) floating point",
346 mips_option_handler },
347 #endif
348 { {"enable-gs", required_argument, NULL, OPTION_GS_ENABLE},
349 '\0', "on|off", "Enable GS library routines",
350 mips_option_handler },
351 { {"gs-refresh1", required_argument, NULL, OPTION_GS_REFRESH1},
352 '\0', "0xaddress0=0xvalue0:0xaddress1=0xvalue1", "GS refresh buffer 1 addresses and values",
353 mips_option_handler },
354 { {"gs-refresh2", required_argument, NULL, OPTION_GS_REFRESH2},
355 '\0', "0xaddress0=0xvalue0:0xaddress1=0xvalue1", "GS refresh buffer 2 addresses and values",
356 mips_option_handler },
357 #endif
358 /* end-sanitize-sky */
359
360 { {"board", required_argument, NULL, OPTION_BOARD},
361 '\0', "none" /* rely on compile-time string concatenation for other options */
362
363 /* start-sanitize-tx3904 */
364 #define BOARD_JMR3904 "jmr3904"
365 "|" BOARD_JMR3904
366 #define BOARD_JMR3904_DEBUG "jmr3904debug"
367 "|" BOARD_JMR3904_DEBUG
368 /* end-sanitize-tx3904 */
369
370 , "Customize simulation for a particular board.", mips_option_handler },
371
372 { {NULL, no_argument, NULL, 0}, '\0', NULL, NULL, NULL }
373 };
374
375
376 int interrupt_pending;
377
378 static void
379 interrupt_event (SIM_DESC sd, void *data)
380 {
381 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
382 address_word cia = CIA_GET (cpu);
383 if (SR & status_IE)
384 {
385 interrupt_pending = 0;
386 SignalExceptionInterrupt ();
387 }
388 else if (!interrupt_pending)
389 sim_events_schedule (sd, 1, interrupt_event, data);
390 }
391
392
393 /*---------------------------------------------------------------------------*/
394 /*-- Device registration hook -----------------------------------------------*/
395 /*---------------------------------------------------------------------------*/
396 static void device_init(SIM_DESC sd) {
397 #ifdef DEVICE_INIT
398 extern void register_devices(SIM_DESC);
399 register_devices(sd);
400 #endif
401 }
402
403 /*---------------------------------------------------------------------------*/
404 /*-- GDB simulator interface ------------------------------------------------*/
405 /*---------------------------------------------------------------------------*/
406
407 SIM_DESC
408 sim_open (kind, cb, abfd, argv)
409 SIM_OPEN_KIND kind;
410 host_callback *cb;
411 struct _bfd *abfd;
412 char **argv;
413 {
414 SIM_DESC sd = sim_state_alloc (kind, cb);
415 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
416
417 SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
418 /* start-sanitize-sky */
419
420 #if defined(TARGET_SKY) && defined(SKY_FUNIT)
421 /* Set "--float-type fast" as the default. */
422 STATE_FP_TYPE_OPT (sd) &= ~STATE_FP_TYPE_OPT_ACCURATE;
423 #endif
424 /* end-sanitize-sky */
425
426 /* FIXME: watchpoints code shouldn't need this */
427 STATE_WATCHPOINTS (sd)->pc = &(PC);
428 STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
429 STATE_WATCHPOINTS (sd)->interrupt_handler = interrupt_event;
430
431 STATE = 0;
432
433 if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
434 return 0;
435 sim_add_option_table (sd, NULL, mips_options);
436
437 /* getopt will print the error message so we just have to exit if this fails.
438 FIXME: Hmmm... in the case of gdb we need getopt to call
439 print_filtered. */
440 if (sim_parse_args (sd, argv) != SIM_RC_OK)
441 {
442 /* Uninstall the modules to avoid memory leaks,
443 file descriptor leaks, etc. */
444 sim_module_uninstall (sd);
445 return 0;
446 }
447
448 /* handle board-specific memory maps */
449 if (board == NULL)
450 {
451 /* Allocate core managed memory */
452
453 /* start-sanitize-sky */
454 #ifndef TARGET_SKY
455 /* end-sanitize-sky */
456 /* the monitor */
457 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE, MONITOR_SIZE);
458 /* For compatibility with the old code - under this (at level one)
459 are the kernel spaces K0 & K1. Both of these map to a single
460 smaller sub region */
461 sim_do_command(sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
462 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
463 K1BASE, K0SIZE,
464 MEM_SIZE, /* actual size */
465 K0BASE);
466 /* start-sanitize-sky */
467 #else
468 /* the monitor */
469 sim_do_commandf (sd, "memory region 0x%lx,0x%lx", MONITOR_BASE - K1BASE, MONITOR_SIZE);
470 sim_do_command (sd," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
471 /* 16M @ 0x0. Aliases at 0x80000000 and 0xA0000000 are handled by
472 address_translation() */
473 sim_do_commandf (sd, "memory size 0x%lx", MEM_SIZE);
474 #endif
475 /* end-sanitize-sky */
476
477 device_init(sd);
478 }
479
480 /* start-sanitize-tx3904 */
481 #if (WITH_HW)
482 if (board != NULL
483 && (strcmp(board, BOARD_JMR3904) == 0 ||
484 strcmp(board, BOARD_JMR3904_DEBUG) == 0))
485 {
486 /* match VIRTUAL memory layout of JMR-TX3904 board */
487
488 /* --- memory --- */
489
490 /* ROM: 0x9FC0_0000 - 0x9FFF_FFFF and 0xBFC0_0000 - 0xBFFF_FFFF */
491 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
492 0x9FC00000,
493 4 * 1024 * 1024, /* 4 MB */
494 0xBFC00000);
495
496 /* SRAM: 0x8000_0000 - 0x803F_FFFF and 0xA000_0000 - 0xA03F_FFFF */
497 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
498 0x80000000,
499 4 * 1024 * 1024, /* 4 MB */
500 0xA0000000);
501
502 /* DRAM: 0x8800_0000 - 0x89FF_FFFF and 0xA800_0000 - 0xA9FF_FFFF */
503 sim_do_commandf (sd, "memory alias 0x%lx@1,0x%lx,0x%0x",
504 0x88000000,
505 32 * 1024 * 1024, /* 32 MB */
506 0xA8000000);
507
508 /* --- simulated devices --- */
509 sim_hw_parse (sd, "/tx3904irc@0xffffc000/reg 0xffffc000 0x20");
510 sim_hw_parse (sd, "/tx3904cpu");
511 sim_hw_parse (sd, "/tx3904tmr@0xfffff000/reg 0xfffff000 0x100");
512 sim_hw_parse (sd, "/tx3904tmr@0xfffff100/reg 0xfffff100 0x100");
513 sim_hw_parse (sd, "/tx3904tmr@0xfffff200/reg 0xfffff200 0x100");
514
515 /* -- device connections --- */
516 sim_hw_parse (sd, "/tx3904irc > ip level /tx3904cpu");
517 sim_hw_parse (sd, "/tx3904tmr@0xfffff000 > int tmr0 /tx3904irc");
518 sim_hw_parse (sd, "/tx3904tmr@0xfffff100 > int tmr1 /tx3904irc");
519 sim_hw_parse (sd, "/tx3904tmr@0xfffff200 > int tmr2 /tx3904irc");
520
521 if(! strcmp(board, BOARD_JMR3904_DEBUG))
522 {
523 /* -- DEBUG: glue interrupt generators --- */
524 sim_hw_parse (sd, "/glue@0xffff0000/reg 0xffff0000 0x50");
525 sim_hw_parse (sd, "/glue@0xffff0000 > int0 int0 /tx3904irc");
526 sim_hw_parse (sd, "/glue@0xffff0000 > int1 int1 /tx3904irc");
527 sim_hw_parse (sd, "/glue@0xffff0000 > int2 int2 /tx3904irc");
528 sim_hw_parse (sd, "/glue@0xffff0000 > int3 int3 /tx3904irc");
529 sim_hw_parse (sd, "/glue@0xffff0000 > int4 int4 /tx3904irc");
530 sim_hw_parse (sd, "/glue@0xffff0000 > int5 int5 /tx3904irc");
531 sim_hw_parse (sd, "/glue@0xffff0000 > int6 int6 /tx3904irc");
532 sim_hw_parse (sd, "/glue@0xffff0000 > int7 int7 /tx3904irc");
533 sim_hw_parse (sd, "/glue@0xffff0000 > int8 dmac0 /tx3904irc");
534 sim_hw_parse (sd, "/glue@0xffff0000 > int9 dmac1 /tx3904irc");
535 sim_hw_parse (sd, "/glue@0xffff0000 > int10 dmac2 /tx3904irc");
536 sim_hw_parse (sd, "/glue@0xffff0000 > int11 dmac3 /tx3904irc");
537 sim_hw_parse (sd, "/glue@0xffff0000 > int12 sio0 /tx3904irc");
538 sim_hw_parse (sd, "/glue@0xffff0000 > int13 sio1 /tx3904irc");
539 sim_hw_parse (sd, "/glue@0xffff0000 > int14 tmr0 /tx3904irc");
540 sim_hw_parse (sd, "/glue@0xffff0000 > int15 tmr1 /tx3904irc");
541 sim_hw_parse (sd, "/glue@0xffff0000 > int16 tmr2 /tx3904irc");
542 sim_hw_parse (sd, "/glue@0xffff0000 > int17 nmi /tx3904cpu");
543 }
544
545 device_init(sd);
546 }
547 #endif
548 /* end-sanitize-tx3904 */
549
550
551 /* check for/establish the a reference program image */
552 if (sim_analyze_program (sd,
553 (STATE_PROG_ARGV (sd) != NULL
554 ? *STATE_PROG_ARGV (sd)
555 : NULL),
556 abfd) != SIM_RC_OK)
557 {
558 sim_module_uninstall (sd);
559 return 0;
560 }
561
562 /* Configure/verify the target byte order and other runtime
563 configuration options */
564 if (sim_config (sd) != SIM_RC_OK)
565 {
566 sim_module_uninstall (sd);
567 return 0;
568 }
569
570 if (sim_post_argv_init (sd) != SIM_RC_OK)
571 {
572 /* Uninstall the modules to avoid memory leaks,
573 file descriptor leaks, etc. */
574 sim_module_uninstall (sd);
575 return 0;
576 }
577
578 /* verify assumptions the simulator made about the host type system.
579 This macro does not return if there is a problem */
580 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
581 SIM_ASSERT (sizeof(word64) == (8 * sizeof(char)));
582
583 /* This is NASTY, in that we are assuming the size of specific
584 registers: */
585 {
586 int rn;
587 for (rn = 0; (rn < (LAST_EMBED_REGNUM + 1)); rn++)
588 {
589 if (rn < 32)
590 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
591 else if ((rn >= FGRIDX) && (rn < (FGRIDX + NR_FGR)))
592 cpu->register_widths[rn] = WITH_TARGET_FLOATING_POINT_BITSIZE;
593 else if ((rn >= 33) && (rn <= 37))
594 cpu->register_widths[rn] = WITH_TARGET_WORD_BITSIZE;
595 else if ((rn == SRIDX)
596 || (rn == FCR0IDX)
597 || (rn == FCR31IDX)
598 || ((rn >= 72) && (rn <= 89)))
599 cpu->register_widths[rn] = 32;
600 else
601 cpu->register_widths[rn] = 0;
602 }
603 /* start-sanitize-r5900 */
604
605 /* set the 5900 "upper" registers to 64 bits */
606 for( rn = LAST_EMBED_REGNUM+1; rn < NUM_REGS; rn++)
607 cpu->register_widths[rn] = 64;
608 /* end-sanitize-r5900 */
609
610 /* start-sanitize-sky */
611 #ifdef TARGET_SKY
612 /* Now the VU registers */
613 for( rn = 0; rn < NUM_VU_INTEGER_REGS; rn++ ) {
614 cpu->register_widths[rn + NUM_R5900_REGS] = 16;
615 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 16;
616 }
617
618 for( rn = NUM_VU_INTEGER_REGS; rn < NUM_VU_REGS; rn++ ) {
619 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
620 cpu->register_widths[rn + NUM_R5900_REGS + NUM_VU_REGS] = 32;
621 }
622
623 /* Finally the VIF registers */
624 for( rn = 2*NUM_VU_REGS; rn < 2*NUM_VU_REGS + 2*NUM_VIF_REGS; rn++ )
625 cpu->register_widths[rn + NUM_R5900_REGS] = 32;
626
627 cpu->cur_device = 0;
628 #endif
629 /* end-sanitize-sky */
630 }
631
632 #if defined(TRACE)
633 if (STATE & simTRACE)
634 open_trace(sd);
635 #endif /* TRACE */
636
637 /* Write an abort sequence into the TRAP (common) exception vector
638 addresses. This is to catch code executing a TRAP (et.al.)
639 instruction without installing a trap handler. */
640 {
641 unsigned32 halt[2] = { 0x2404002f /* addiu r4, r0, 47 */,
642 HALT_INSTRUCTION /* BREAK */ };
643 H2T (halt[0]);
644 H2T (halt[1]);
645 sim_write (sd, 0x80000180, (char *) halt, sizeof (halt));
646 sim_write (sd, 0xBFC00380, (char *) halt, sizeof (halt));
647 }
648
649
650 /* Write the monitor trap address handlers into the monitor (eeprom)
651 address space. This can only be done once the target endianness
652 has been determined. */
653 {
654 unsigned loop;
655 /* Entry into the IDT monitor is via fixed address vectors, and
656 not using machine instructions. To avoid clashing with use of
657 the MIPS TRAP system, we place our own (simulator specific)
658 "undefined" instructions into the relevant vector slots. */
659 for (loop = 0; (loop < MONITOR_SIZE); loop += 4)
660 {
661 address_word vaddr = (MONITOR_BASE + loop);
662 unsigned32 insn = (RSVD_INSTRUCTION | (((loop >> 2) & RSVD_INSTRUCTION_ARG_MASK) << RSVD_INSTRUCTION_ARG_SHIFT));
663 H2T (insn);
664 sim_write (sd, vaddr, (char *)&insn, sizeof (insn));
665 }
666 /* The PMON monitor uses the same address space, but rather than
667 branching into it the address of a routine is loaded. We can
668 cheat for the moment, and direct the PMON routine to IDT style
669 instructions within the monitor space. This relies on the IDT
670 monitor not using the locations from 0xBFC00500 onwards as its
671 entry points.*/
672 for (loop = 0; (loop < 24); loop++)
673 {
674 address_word vaddr = (MONITOR_BASE + 0x500 + (loop * 4));
675 unsigned32 value = ((0x500 - 8) / 8); /* default UNDEFINED reason code */
676 switch (loop)
677 {
678 case 0: /* read */
679 value = 7;
680 break;
681 case 1: /* write */
682 value = 8;
683 break;
684 case 2: /* open */
685 value = 6;
686 break;
687 case 3: /* close */
688 value = 10;
689 break;
690 case 5: /* printf */
691 value = ((0x500 - 16) / 8); /* not an IDT reason code */
692 break;
693 case 8: /* cliexit */
694 value = 17;
695 break;
696 case 11: /* flush_cache */
697 value = 28;
698 break;
699 }
700 /* FIXME - should monitor_base be SIM_ADDR?? */
701 value = ((unsigned int)MONITOR_BASE + (value * 8));
702 H2T (value);
703 sim_write (sd, vaddr, (char *)&value, sizeof (value));
704
705 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
706 vaddr -= 0x300;
707 sim_write (sd, vaddr, (char *)&value, sizeof (value));
708 }
709 }
710
711 return sd;
712 }
713
714 #if defined(TRACE)
715 static void
716 open_trace(sd)
717 SIM_DESC sd;
718 {
719 tracefh = fopen(tracefile,"wb+");
720 if (tracefh == NULL)
721 {
722 sim_io_eprintf(sd,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile);
723 tracefh = stderr;
724 }
725 }
726 #endif /* TRACE */
727
728 void
729 sim_close (sd, quitting)
730 SIM_DESC sd;
731 int quitting;
732 {
733 #ifdef DEBUG
734 printf("DBG: sim_close: entered (quitting = %d)\n",quitting);
735 #endif
736
737 /* "quitting" is non-zero if we cannot hang on errors */
738
739 /* Ensure that any resources allocated through the callback
740 mechanism are released: */
741 sim_io_shutdown (sd);
742
743 #if defined(TRACE)
744 if (tracefh != NULL && tracefh != stderr)
745 fclose(tracefh);
746 tracefh = NULL;
747 #endif /* TRACE */
748
749 /* FIXME - free SD */
750
751 return;
752 }
753
754
755 int
756 sim_write (sd,addr,buffer,size)
757 SIM_DESC sd;
758 SIM_ADDR addr;
759 unsigned char *buffer;
760 int size;
761 {
762 int index;
763 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
764
765 /* Return the number of bytes written, or zero if error. */
766 #ifdef DEBUG
767 sim_io_printf(sd,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr),size);
768 #endif
769
770 /* We use raw read and write routines, since we do not want to count
771 the GDB memory accesses in our statistics gathering. */
772
773 for (index = 0; index < size; index++)
774 {
775 address_word vaddr = (address_word)addr + index;
776 address_word paddr;
777 int cca;
778 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isSTORE, &paddr, &cca, isRAW))
779 break;
780 if (sim_core_write_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
781 break;
782 }
783
784 return(index);
785 }
786
787 int
788 sim_read (sd,addr,buffer,size)
789 SIM_DESC sd;
790 SIM_ADDR addr;
791 unsigned char *buffer;
792 int size;
793 {
794 int index;
795 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
796
797 /* Return the number of bytes read, or zero if error. */
798 #ifdef DEBUG
799 sim_io_printf(sd,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr),size);
800 #endif /* DEBUG */
801
802 for (index = 0; (index < size); index++)
803 {
804 address_word vaddr = (address_word)addr + index;
805 address_word paddr;
806 int cca;
807 if (!address_translation (SD, CPU, NULL_CIA, vaddr, isDATA, isLOAD, &paddr, &cca, isRAW))
808 break;
809 if (sim_core_read_buffer (SD, CPU, read_map, buffer + index, paddr, 1) != 1)
810 break;
811 }
812
813 return(index);
814 }
815
816 int
817 sim_store_register (sd,rn,memory,length)
818 SIM_DESC sd;
819 int rn;
820 unsigned char *memory;
821 int length;
822 {
823 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
824 /* NOTE: gdb (the client) stores registers in target byte order
825 while the simulator uses host byte order */
826 #ifdef DEBUG
827 sim_io_printf(sd,"sim_store_register(%d,*memory=0x%s);\n",rn,pr_addr(*((SIM_ADDR *)memory)));
828 #endif /* DEBUG */
829
830 /* Unfortunately this suffers from the same problem as the register
831 numbering one. We need to know what the width of each logical
832 register number is for the architecture being simulated. */
833
834 if (cpu->register_widths[rn] == 0)
835 {
836 sim_io_eprintf(sd,"Invalid register width for %d (register store ignored)\n",rn);
837 return 0;
838 }
839
840 /* start-sanitize-r5900 */
841 if (rn >= 90 && rn < 90 + 32)
842 {
843 GPR1[rn - 90] = T2H_8 (*(unsigned64*)memory);
844 return 8;
845 }
846 switch (rn)
847 {
848 case REGISTER_SA:
849 SA = T2H_8(*(unsigned64*)memory);
850 return 8;
851 case 122: /* FIXME */
852 LO1 = T2H_8(*(unsigned64*)memory);
853 return 8;
854 case 123: /* FIXME */
855 HI1 = T2H_8(*(unsigned64*)memory);
856 return 8;
857 }
858 /* end-sanitize-r5900 */
859
860 /* start-sanitize-sky */
861 #ifdef TARGET_SKY
862 if (rn >= NUM_R5900_REGS)
863 {
864 rn = rn - NUM_R5900_REGS;
865
866 if( rn < NUM_VU_REGS )
867 {
868 if (rn < NUM_VU_INTEGER_REGS)
869 return write_vu_int_reg (&(vu0_device.regs), rn, memory);
870 else if (rn >= FIRST_VEC_REG)
871 {
872 rn -= FIRST_VEC_REG;
873 return write_vu_vec_reg (&(vu0_device.regs), rn>>2, rn&3,
874 memory);
875 }
876 else switch (rn - NUM_VU_INTEGER_REGS)
877 {
878 case 0:
879 return write_vu_special_reg (&vu0_device, VU_REG_CIA,
880 memory);
881 case 1:
882 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
883 memory);
884 case 2: /* VU0 has no P register */
885 return 4;
886 case 3:
887 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
888 memory);
889 case 4:
890 return write_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
891 memory);
892 default:
893 return write_vu_acc_reg (&(vu0_device.regs),
894 rn - (NUM_VU_INTEGER_REGS + 5),
895 memory);
896 }
897 }
898
899 rn = rn - NUM_VU_REGS;
900
901 if (rn < NUM_VU_REGS)
902 {
903 if (rn < NUM_VU_INTEGER_REGS)
904 return write_vu_int_reg (&(vu1_device.regs), rn, memory);
905 else if (rn >= FIRST_VEC_REG)
906 {
907 rn -= FIRST_VEC_REG;
908 return write_vu_vec_reg (&(vu1_device.regs),
909 rn >> 2, rn & 3, memory);
910 }
911 else switch (rn - NUM_VU_INTEGER_REGS)
912 {
913 case 0:
914 return write_vu_special_reg (&vu1_device, VU_REG_CIA,
915 memory);
916 case 1:
917 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MR,
918 memory);
919 case 2:
920 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MP,
921 memory);
922 case 3:
923 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MI,
924 memory);
925 case 4:
926 return write_vu_misc_reg (&(vu1_device.regs), VU_REG_MQ,
927 memory);
928 default:
929 return write_vu_acc_reg (&(vu1_device.regs),
930 rn - (NUM_VU_INTEGER_REGS + 5),
931 memory);
932 }
933 }
934
935 rn -= NUM_VU_REGS; /* VIF0 registers are next */
936
937 if (rn < NUM_VIF_REGS)
938 {
939 if (rn < NUM_VIF_REGS-1)
940 return write_pke_reg (&pke0_device, rn, memory);
941 else
942 {
943 sim_io_eprintf( sd, "Can't write vif0_pc (store ignored)\n" );
944 return 0;
945 }
946 }
947
948 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
949
950 if (rn < NUM_VIF_REGS)
951 {
952 if (rn < NUM_VIF_REGS-1)
953 return write_pke_reg (&pke1_device, rn, memory);
954 else
955 {
956 sim_io_eprintf( sd, "Can't write vif1_pc (store ignored)\n" );
957 return 0;
958 }
959 }
960
961 sim_io_eprintf( sd, "Invalid VU register (register store ignored)\n" );
962 return 0;
963 }
964 #endif
965 /* end-sanitize-sky */
966
967 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
968 {
969 if (cpu->register_widths[rn] == 32)
970 {
971 cpu->fgr[rn - FGRIDX] = T2H_4 (*(unsigned32*)memory);
972 return 4;
973 }
974 else
975 {
976 cpu->fgr[rn - FGRIDX] = T2H_8 (*(unsigned64*)memory);
977 return 8;
978 }
979 }
980
981 if (cpu->register_widths[rn] == 32)
982 {
983 cpu->registers[rn] = T2H_4 (*(unsigned32*)memory);
984 return 4;
985 }
986 else
987 {
988 cpu->registers[rn] = T2H_8 (*(unsigned64*)memory);
989 return 8;
990 }
991
992 return 0;
993 }
994
995 int
996 sim_fetch_register (sd,rn,memory,length)
997 SIM_DESC sd;
998 int rn;
999 unsigned char *memory;
1000 int length;
1001 {
1002 sim_cpu *cpu = STATE_CPU (sd, 0); /* FIXME */
1003 /* NOTE: gdb (the client) stores registers in target byte order
1004 while the simulator uses host byte order */
1005 #ifdef DEBUG
1006 sim_io_printf(sd,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn,pr_addr(registers[rn]));
1007 #endif /* DEBUG */
1008
1009 if (cpu->register_widths[rn] == 0)
1010 {
1011 sim_io_eprintf (sd, "Invalid register width for %d (register fetch ignored)\n",rn);
1012 return 0;
1013 }
1014
1015 /* start-sanitize-r5900 */
1016 if (rn >= 90 && rn < 90 + 32)
1017 {
1018 *((unsigned64*)memory) = H2T_8 (GPR1[rn - 90]);
1019 return 8;
1020 }
1021 switch (rn)
1022 {
1023 case REGISTER_SA:
1024 *((unsigned64*)memory) = H2T_8(SA);
1025 return 8;
1026 case 122: /* FIXME */
1027 *((unsigned64*)memory) = H2T_8(LO1);
1028 return 8;
1029 case 123: /* FIXME */
1030 *((unsigned64*)memory) = H2T_8(HI1);
1031 return 8;
1032 }
1033 /* end-sanitize-r5900 */
1034
1035 /* start-sanitize-sky */
1036 #ifdef TARGET_SKY
1037 if (rn >= NUM_R5900_REGS)
1038 {
1039 rn = rn - NUM_R5900_REGS;
1040
1041 if (rn < NUM_VU_REGS)
1042 {
1043 if (rn < NUM_VU_INTEGER_REGS)
1044 return read_vu_int_reg (&(vu0_device.regs), rn, memory);
1045 else if (rn >= FIRST_VEC_REG)
1046 {
1047 rn -= FIRST_VEC_REG;
1048 return read_vu_vec_reg (&(vu0_device.regs), rn>>2, rn & 3,
1049 memory);
1050 }
1051 else switch (rn - NUM_VU_INTEGER_REGS)
1052 {
1053 case 0:
1054 return read_vu_special_reg(&vu0_device, VU_REG_CIA, memory);
1055 case 1:
1056 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MR,
1057 memory);
1058 case 2: /* VU0 has no P register */
1059 *((int *) memory) = 0;
1060 return 4;
1061 case 3:
1062 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MI,
1063 memory);
1064 case 4:
1065 return read_vu_misc_reg (&(vu0_device.regs), VU_REG_MQ,
1066 memory);
1067 default:
1068 return read_vu_acc_reg (&(vu0_device.regs),
1069 rn - (NUM_VU_INTEGER_REGS + 5),
1070 memory);
1071 }
1072 }
1073
1074 rn -= NUM_VU_REGS; /* VU1 registers are next */
1075
1076 if (rn < NUM_VU_REGS)
1077 {
1078 if (rn < NUM_VU_INTEGER_REGS)
1079 return read_vu_int_reg (&(vu1_device.regs), rn, memory);
1080 else if (rn >= FIRST_VEC_REG)
1081 {
1082 rn -= FIRST_VEC_REG;
1083 return read_vu_vec_reg (&(vu1_device.regs),
1084 rn >> 2, rn & 3, memory);
1085 }
1086 else switch (rn - NUM_VU_INTEGER_REGS)
1087 {
1088 case 0:
1089 return read_vu_special_reg(&vu1_device, VU_REG_CIA, memory);
1090 case 1:
1091 return read_vu_misc_reg (&(vu1_device.regs),
1092 VU_REG_MR, memory);
1093 case 2:
1094 return read_vu_misc_reg (&(vu1_device.regs),
1095 VU_REG_MP, memory);
1096 case 3:
1097 return read_vu_misc_reg (&(vu1_device.regs),
1098 VU_REG_MI, memory);
1099 case 4:
1100 return read_vu_misc_reg (&(vu1_device.regs),
1101 VU_REG_MQ, memory);
1102 default:
1103 return read_vu_acc_reg (&(vu1_device.regs),
1104 rn - (NUM_VU_INTEGER_REGS + 5),
1105 memory);
1106 }
1107 }
1108
1109 rn -= NUM_VU_REGS; /* VIF0 registers are next */
1110
1111 if (rn < NUM_VIF_REGS)
1112 {
1113 if (rn < NUM_VIF_REGS-1)
1114 return read_pke_reg (&pke0_device, rn, memory);
1115 else
1116 return read_pke_pc (&pke0_device, memory);
1117 }
1118
1119 rn -= NUM_VIF_REGS; /* VIF1 registers are last */
1120
1121 if (rn < NUM_VIF_REGS)
1122 {
1123 if (rn < NUM_VIF_REGS-1)
1124 return read_pke_reg (&pke1_device, rn, memory);
1125 else
1126 return read_pke_pc (&pke1_device, memory);
1127 }
1128
1129 sim_io_eprintf( sd, "Invalid VU register (register fetch ignored)\n" );
1130 }
1131 #endif
1132 /* end-sanitize-sky */
1133
1134 /* Any floating point register */
1135 if (rn >= FGRIDX && rn < FGRIDX + NR_FGR)
1136 {
1137 if (cpu->register_widths[rn] == 32)
1138 {
1139 *(unsigned32*)memory = H2T_4 (cpu->fgr[rn - FGRIDX]);
1140 return 4;
1141 }
1142 else
1143 {
1144 *(unsigned64*)memory = H2T_8 (cpu->fgr[rn - FGRIDX]);
1145 return 8;
1146 }
1147 }
1148
1149 if (cpu->register_widths[rn] == 32)
1150 {
1151 *(unsigned32*)memory = H2T_4 ((unsigned32)(cpu->registers[rn]));
1152 return 4;
1153 }
1154 else
1155 {
1156 *(unsigned64*)memory = H2T_8 ((unsigned64)(cpu->registers[rn]));
1157 return 8;
1158 }
1159
1160 return 0;
1161 }
1162
1163
1164 SIM_RC
1165 sim_create_inferior (sd, abfd, argv,env)
1166 SIM_DESC sd;
1167 struct _bfd *abfd;
1168 char **argv;
1169 char **env;
1170 {
1171
1172 #ifdef DEBUG
1173 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
1174 pr_addr(PC));
1175 #endif /* DEBUG */
1176
1177 ColdReset(sd);
1178
1179 if (abfd != NULL)
1180 {
1181 /* override PC value set by ColdReset () */
1182 int cpu_nr;
1183 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1184 {
1185 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1186 CIA_SET (cpu, (unsigned64) bfd_get_start_address (abfd));
1187 }
1188 }
1189
1190 #if 0 /* def DEBUG */
1191 if (argv || env)
1192 {
1193 /* We should really place the argv slot values into the argument
1194 registers, and onto the stack as required. However, this
1195 assumes that we have a stack defined, which is not
1196 necessarily true at the moment. */
1197 char **cptr;
1198 sim_io_printf(sd,"sim_create_inferior() : passed arguments ignored\n");
1199 for (cptr = argv; (cptr && *cptr); cptr++)
1200 printf("DBG: arg \"%s\"\n",*cptr);
1201 }
1202 #endif /* DEBUG */
1203
1204 return SIM_RC_OK;
1205 }
1206
1207 void
1208 sim_do_command (sd,cmd)
1209 SIM_DESC sd;
1210 char *cmd;
1211 {
1212 if (sim_args_command (sd, cmd) != SIM_RC_OK)
1213 sim_io_printf (sd, "Error: \"%s\" is not a valid MIPS simulator command.\n",
1214 cmd);
1215 }
1216
1217 /*---------------------------------------------------------------------------*/
1218 /*-- Private simulator support interface ------------------------------------*/
1219 /*---------------------------------------------------------------------------*/
1220
1221 /* Read a null terminated string from memory, return in a buffer */
1222 static char *
1223 fetch_str (sd, addr)
1224 SIM_DESC sd;
1225 address_word addr;
1226 {
1227 char *buf;
1228 int nr = 0;
1229 char null;
1230 while (sim_read (sd, addr + nr, &null, 1) == 1 && null != 0)
1231 nr++;
1232 buf = NZALLOC (char, nr + 1);
1233 sim_read (sd, addr, buf, nr);
1234 return buf;
1235 }
1236
1237 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
1238 static void
1239 sim_monitor (SIM_DESC sd,
1240 sim_cpu *cpu,
1241 address_word cia,
1242 unsigned int reason)
1243 {
1244 #ifdef DEBUG
1245 printf("DBG: sim_monitor: entered (reason = %d)\n",reason);
1246 #endif /* DEBUG */
1247
1248 /* The IDT monitor actually allows two instructions per vector
1249 slot. However, the simulator currently causes a trap on each
1250 individual instruction. We cheat, and lose the bottom bit. */
1251 reason >>= 1;
1252
1253 /* The following callback functions are available, however the
1254 monitor we are simulating does not make use of them: get_errno,
1255 isatty, lseek, rename, system, time and unlink */
1256 switch (reason)
1257 {
1258
1259 case 6: /* int open(char *path,int flags) */
1260 {
1261 char *path = fetch_str (sd, A0);
1262 V0 = sim_io_open (sd, path, (int)A1);
1263 zfree (path);
1264 break;
1265 }
1266
1267 case 7: /* int read(int file,char *ptr,int len) */
1268 {
1269 int fd = A0;
1270 int nr = A2;
1271 char *buf = zalloc (nr);
1272 V0 = sim_io_read (sd, fd, buf, nr);
1273 sim_write (sd, A1, buf, nr);
1274 zfree (buf);
1275 }
1276 break;
1277
1278 case 8: /* int write(int file,char *ptr,int len) */
1279 {
1280 int fd = A0;
1281 int nr = A2;
1282 char *buf = zalloc (nr);
1283 sim_read (sd, A1, buf, nr);
1284 V0 = sim_io_write (sd, fd, buf, nr);
1285 zfree (buf);
1286 break;
1287 }
1288
1289 case 10: /* int close(int file) */
1290 {
1291 V0 = sim_io_close (sd, (int)A0);
1292 break;
1293 }
1294
1295 case 2: /* Densan monitor: char inbyte(int waitflag) */
1296 {
1297 if (A0 == 0) /* waitflag == NOWAIT */
1298 V0 = (unsigned_word)-1;
1299 }
1300 /* Drop through to case 11 */
1301
1302 case 11: /* char inbyte(void) */
1303 {
1304 char tmp;
1305 if (sim_io_read_stdin (sd, &tmp, sizeof(char)) != sizeof(char))
1306 {
1307 sim_io_error(sd,"Invalid return from character read");
1308 V0 = (unsigned_word)-1;
1309 }
1310 else
1311 V0 = (unsigned_word)tmp;
1312 break;
1313 }
1314
1315 case 3: /* Densan monitor: void co(char chr) */
1316 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
1317 {
1318 char tmp = (char)(A0 & 0xFF);
1319 sim_io_write_stdout (sd, &tmp, sizeof(char));
1320 break;
1321 }
1322
1323 case 17: /* void _exit() */
1324 {
1325 sim_io_eprintf (sd, "sim_monitor(17): _exit(int reason) to be coded\n");
1326 sim_engine_halt (SD, CPU, NULL, NULL_CIA, sim_exited,
1327 (unsigned int)(A0 & 0xFFFFFFFF));
1328 break;
1329 }
1330
1331 case 28 : /* PMON flush_cache */
1332 break;
1333
1334 case 55: /* void get_mem_info(unsigned int *ptr) */
1335 /* in: A0 = pointer to three word memory location */
1336 /* out: [A0 + 0] = size */
1337 /* [A0 + 4] = instruction cache size */
1338 /* [A0 + 8] = data cache size */
1339 {
1340 unsigned_4 value = MEM_SIZE /* FIXME STATE_MEM_SIZE (sd) */;
1341 unsigned_4 zero = 0;
1342 H2T (value);
1343 sim_write (sd, A0 + 0, (char *)&value, 4);
1344 sim_write (sd, A0 + 4, (char *)&zero, 4);
1345 sim_write (sd, A0 + 8, (char *)&zero, 4);
1346 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1347 break;
1348 }
1349
1350 case 158 : /* PMON printf */
1351 /* in: A0 = pointer to format string */
1352 /* A1 = optional argument 1 */
1353 /* A2 = optional argument 2 */
1354 /* A3 = optional argument 3 */
1355 /* out: void */
1356 /* The following is based on the PMON printf source */
1357 {
1358 address_word s = A0;
1359 char c;
1360 signed_word *ap = &A1; /* 1st argument */
1361 /* This isn't the quickest way, since we call the host print
1362 routine for every character almost. But it does avoid
1363 having to allocate and manage a temporary string buffer. */
1364 /* TODO: Include check that we only use three arguments (A1,
1365 A2 and A3) */
1366 while (sim_read (sd, s++, &c, 1) && c != '\0')
1367 {
1368 if (c == '%')
1369 {
1370 char tmp[40];
1371 enum {FMT_RJUST, FMT_LJUST, FMT_RJUST0, FMT_CENTER} fmt = FMT_RJUST;
1372 int width = 0, trunc = 0, haddot = 0, longlong = 0;
1373 while (sim_read (sd, s++, &c, 1) && c != '\0')
1374 {
1375 if (strchr ("dobxXulscefg%", c))
1376 break;
1377 else if (c == '-')
1378 fmt = FMT_LJUST;
1379 else if (c == '0')
1380 fmt = FMT_RJUST0;
1381 else if (c == '~')
1382 fmt = FMT_CENTER;
1383 else if (c == '*')
1384 {
1385 if (haddot)
1386 trunc = (int)*ap++;
1387 else
1388 width = (int)*ap++;
1389 }
1390 else if (c >= '1' && c <= '9')
1391 {
1392 address_word t = s;
1393 unsigned int n;
1394 while (sim_read (sd, s++, &c, 1) == 1 && isdigit (c))
1395 tmp[s - t] = c;
1396 tmp[s - t] = '\0';
1397 n = (unsigned int)strtol(tmp,NULL,10);
1398 if (haddot)
1399 trunc = n;
1400 else
1401 width = n;
1402 s--;
1403 }
1404 else if (c == '.')
1405 haddot = 1;
1406 }
1407 switch (c)
1408 {
1409 case '%':
1410 sim_io_printf (sd, "%%");
1411 break;
1412 case 's':
1413 if ((int)*ap != 0)
1414 {
1415 address_word p = *ap++;
1416 char ch;
1417 while (sim_read (sd, p++, &ch, 1) == 1 && ch != '\0')
1418 sim_io_printf(sd, "%c", ch);
1419 }
1420 else
1421 sim_io_printf(sd,"(null)");
1422 break;
1423 case 'c':
1424 sim_io_printf (sd, "%c", (int)*ap++);
1425 break;
1426 default:
1427 if (c == 'l')
1428 {
1429 sim_read (sd, s++, &c, 1);
1430 if (c == 'l')
1431 {
1432 longlong = 1;
1433 sim_read (sd, s++, &c, 1);
1434 }
1435 }
1436 if (strchr ("dobxXu", c))
1437 {
1438 word64 lv = (word64) *ap++;
1439 if (c == 'b')
1440 sim_io_printf(sd,"<binary not supported>");
1441 else
1442 {
1443 sprintf (tmp, "%%%s%c", longlong ? "ll" : "", c);
1444 if (longlong)
1445 sim_io_printf(sd, tmp, lv);
1446 else
1447 sim_io_printf(sd, tmp, (int)lv);
1448 }
1449 }
1450 else if (strchr ("eEfgG", c))
1451 {
1452 double dbl = *(double*)(ap++);
1453 sprintf (tmp, "%%%d.%d%c", width, trunc, c);
1454 sim_io_printf (sd, tmp, dbl);
1455 trunc = 0;
1456 }
1457 }
1458 }
1459 else
1460 sim_io_printf(sd, "%c", c);
1461 }
1462 break;
1463 }
1464
1465 default:
1466 sim_io_error (sd, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1467 reason, pr_addr(cia));
1468 break;
1469 }
1470 return;
1471 }
1472
1473 /* Store a word into memory. */
1474
1475 static void
1476 store_word (SIM_DESC sd,
1477 sim_cpu *cpu,
1478 address_word cia,
1479 uword64 vaddr,
1480 signed_word val)
1481 {
1482 address_word paddr;
1483 int uncached;
1484
1485 if ((vaddr & 3) != 0)
1486 SignalExceptionAddressStore ();
1487 else
1488 {
1489 if (AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached,
1490 isTARGET, isREAL))
1491 {
1492 const uword64 mask = 7;
1493 uword64 memval;
1494 unsigned int byte;
1495
1496 paddr = (paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2));
1497 byte = (vaddr & mask) ^ (BigEndianCPU << 2);
1498 memval = ((uword64) val) << (8 * byte);
1499 StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
1500 isREAL);
1501 }
1502 }
1503 }
1504
1505 /* Load a word from memory. */
1506
1507 static signed_word
1508 load_word (SIM_DESC sd,
1509 sim_cpu *cpu,
1510 address_word cia,
1511 uword64 vaddr)
1512 {
1513 if ((vaddr & 3) != 0)
1514 SignalExceptionAddressLoad ();
1515 else
1516 {
1517 address_word paddr;
1518 int uncached;
1519
1520 if (AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached,
1521 isTARGET, isREAL))
1522 {
1523 const uword64 mask = 0x7;
1524 const unsigned int reverse = ReverseEndian ? 1 : 0;
1525 const unsigned int bigend = BigEndianCPU ? 1 : 0;
1526 uword64 memval;
1527 unsigned int byte;
1528
1529 paddr = (paddr & ~mask) | ((paddr & mask) ^ (reverse << 2));
1530 LoadMemory (&memval,NULL,uncached, AccessLength_WORD, paddr, vaddr,
1531 isDATA, isREAL);
1532 byte = (vaddr & mask) ^ (bigend << 2);
1533 return SIGNEXTEND (((memval >> (8 * byte)) & 0xffffffff), 32);
1534 }
1535 }
1536
1537 return 0;
1538 }
1539
1540 /* Simulate the mips16 entry and exit pseudo-instructions. These
1541 would normally be handled by the reserved instruction exception
1542 code, but for ease of simulation we just handle them directly. */
1543
1544 static void
1545 mips16_entry (SIM_DESC sd,
1546 sim_cpu *cpu,
1547 address_word cia,
1548 unsigned int insn)
1549 {
1550 int aregs, sregs, rreg;
1551
1552 #ifdef DEBUG
1553 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn);
1554 #endif /* DEBUG */
1555
1556 aregs = (insn & 0x700) >> 8;
1557 sregs = (insn & 0x0c0) >> 6;
1558 rreg = (insn & 0x020) >> 5;
1559
1560 /* This should be checked by the caller. */
1561 if (sregs == 3)
1562 abort ();
1563
1564 if (aregs < 5)
1565 {
1566 int i;
1567 signed_word tsp;
1568
1569 /* This is the entry pseudo-instruction. */
1570
1571 for (i = 0; i < aregs; i++)
1572 store_word (SD, CPU, cia, (uword64) (SP + 4 * i), GPR[i + 4]);
1573
1574 tsp = SP;
1575 SP -= 32;
1576
1577 if (rreg)
1578 {
1579 tsp -= 4;
1580 store_word (SD, CPU, cia, (uword64) tsp, RA);
1581 }
1582
1583 for (i = 0; i < sregs; i++)
1584 {
1585 tsp -= 4;
1586 store_word (SD, CPU, cia, (uword64) tsp, GPR[16 + i]);
1587 }
1588 }
1589 else
1590 {
1591 int i;
1592 signed_word tsp;
1593
1594 /* This is the exit pseudo-instruction. */
1595
1596 tsp = SP + 32;
1597
1598 if (rreg)
1599 {
1600 tsp -= 4;
1601 RA = load_word (SD, CPU, cia, (uword64) tsp);
1602 }
1603
1604 for (i = 0; i < sregs; i++)
1605 {
1606 tsp -= 4;
1607 GPR[i + 16] = load_word (SD, CPU, cia, (uword64) tsp);
1608 }
1609
1610 SP += 32;
1611
1612 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1613 {
1614 if (aregs == 5)
1615 {
1616 FGR[0] = WORD64LO (GPR[4]);
1617 FPR_STATE[0] = fmt_uninterpreted;
1618 }
1619 else if (aregs == 6)
1620 {
1621 FGR[0] = WORD64LO (GPR[5]);
1622 FGR[1] = WORD64LO (GPR[4]);
1623 FPR_STATE[0] = fmt_uninterpreted;
1624 FPR_STATE[1] = fmt_uninterpreted;
1625 }
1626 }
1627
1628 PC = RA;
1629 }
1630
1631 }
1632
1633 /*-- trace support ----------------------------------------------------------*/
1634
1635 /* The TRACE support is provided (if required) in the memory accessing
1636 routines. Since we are also providing the architecture specific
1637 features, the architecture simulation code can also deal with
1638 notifying the TRACE world of cache flushes, etc. Similarly we do
1639 not need to provide profiling support in the simulator engine,
1640 since we can sample in the instruction fetch control loop. By
1641 defining the TRACE manifest, we add tracing as a run-time
1642 option. */
1643
1644 #if defined(TRACE)
1645 /* Tracing by default produces "din" format (as required by
1646 dineroIII). Each line of such a trace file *MUST* have a din label
1647 and address field. The rest of the line is ignored, so comments can
1648 be included if desired. The first field is the label which must be
1649 one of the following values:
1650
1651 0 read data
1652 1 write data
1653 2 instruction fetch
1654 3 escape record (treated as unknown access type)
1655 4 escape record (causes cache flush)
1656
1657 The address field is a 32bit (lower-case) hexadecimal address
1658 value. The address should *NOT* be preceded by "0x".
1659
1660 The size of the memory transfer is not important when dealing with
1661 cache lines (as long as no more than a cache line can be
1662 transferred in a single operation :-), however more information
1663 could be given following the dineroIII requirement to allow more
1664 complete memory and cache simulators to provide better
1665 results. i.e. the University of Pisa has a cache simulator that can
1666 also take bus size and speed as (variable) inputs to calculate
1667 complete system performance (a much more useful ability when trying
1668 to construct an end product, rather than a processor). They
1669 currently have an ARM version of their tool called ChARM. */
1670
1671
1672 void
1673 dotrace (SIM_DESC sd,
1674 sim_cpu *cpu,
1675 FILE *tracefh,
1676 int type,
1677 SIM_ADDR address,
1678 int width,
1679 char *comment,...)
1680 {
1681 if (STATE & simTRACE) {
1682 va_list ap;
1683 fprintf(tracefh,"%d %s ; width %d ; ",
1684 type,
1685 pr_addr(address),
1686 width);
1687 va_start(ap,comment);
1688 vfprintf(tracefh,comment,ap);
1689 va_end(ap);
1690 fprintf(tracefh,"\n");
1691 }
1692 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1693 we may be generating 64bit ones, we should put the hi-32bits of the
1694 address into the comment field. */
1695
1696 /* TODO: Provide a buffer for the trace lines. We can then avoid
1697 performing writes until the buffer is filled, or the file is
1698 being closed. */
1699
1700 /* NOTE: We could consider adding a comment field to the "din" file
1701 produced using type 3 markers (unknown access). This would then
1702 allow information about the program that the "din" is for, and
1703 the MIPs world that was being simulated, to be placed into the
1704 trace file. */
1705
1706 return;
1707 }
1708 #endif /* TRACE */
1709
1710 /*---------------------------------------------------------------------------*/
1711 /*-- simulator engine -------------------------------------------------------*/
1712 /*---------------------------------------------------------------------------*/
1713
1714 static void
1715 ColdReset (SIM_DESC sd)
1716 {
1717 int cpu_nr;
1718 for (cpu_nr = 0; cpu_nr < sim_engine_nr_cpus (sd); cpu_nr++)
1719 {
1720 sim_cpu *cpu = STATE_CPU (sd, cpu_nr);
1721 /* RESET: Fixed PC address: */
1722 PC = (unsigned_word) UNSIGNED64 (0xFFFFFFFFBFC00000);
1723 /* The reset vector address is in the unmapped, uncached memory space. */
1724
1725 SR &= ~(status_SR | status_TS | status_RP);
1726 SR |= (status_ERL | status_BEV);
1727
1728 /* Cheat and allow access to the complete register set immediately */
1729 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT
1730 && WITH_TARGET_WORD_BITSIZE == 64)
1731 SR |= status_FR; /* 64bit registers */
1732
1733 /* Ensure that any instructions with pending register updates are
1734 cleared: */
1735 PENDING_INVALIDATE();
1736
1737 /* Initialise the FPU registers to the unknown state */
1738 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
1739 {
1740 int rn;
1741 for (rn = 0; (rn < 32); rn++)
1742 FPR_STATE[rn] = fmt_uninterpreted;
1743 }
1744
1745 }
1746 }
1747
1748 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1749 /* Signal an exception condition. This will result in an exception
1750 that aborts the instruction. The instruction operation pseudocode
1751 will never see a return from this function call. */
1752
1753 void
1754 signal_exception (SIM_DESC sd,
1755 sim_cpu *cpu,
1756 address_word cia,
1757 int exception,...)
1758 {
1759 /* int vector; */
1760
1761 #ifdef DEBUG
1762 sim_io_printf(sd,"DBG: SignalException(%d) PC = 0x%s\n",exception,pr_addr(cia));
1763 #endif /* DEBUG */
1764
1765 /* Ensure that any active atomic read/modify/write operation will fail: */
1766 LLBIT = 0;
1767
1768 switch (exception) {
1769
1770 case DebugBreakPoint :
1771 if (! (Debug & Debug_DM))
1772 {
1773 if (INDELAYSLOT())
1774 {
1775 CANCELDELAYSLOT();
1776
1777 Debug |= Debug_DBD; /* signaled from within in delay slot */
1778 DEPC = cia - 4; /* reference the branch instruction */
1779 }
1780 else
1781 {
1782 Debug &= ~Debug_DBD; /* not signaled from within a delay slot */
1783 DEPC = cia;
1784 }
1785
1786 Debug |= Debug_DM; /* in debugging mode */
1787 Debug |= Debug_DBp; /* raising a DBp exception */
1788 PC = 0xBFC00200;
1789 sim_engine_restart (SD, CPU, NULL, NULL_CIA);
1790 }
1791 break;
1792
1793 case ReservedInstruction :
1794 {
1795 va_list ap;
1796 unsigned int instruction;
1797 va_start(ap,exception);
1798 instruction = va_arg(ap,unsigned int);
1799 va_end(ap);
1800 /* Provide simple monitor support using ReservedInstruction
1801 exceptions. The following code simulates the fixed vector
1802 entry points into the IDT monitor by causing a simulator
1803 trap, performing the monitor operation, and returning to
1804 the address held in the $ra register (standard PCS return
1805 address). This means we only need to pre-load the vector
1806 space with suitable instruction values. For systems were
1807 actual trap instructions are used, we would not need to
1808 perform this magic. */
1809 if ((instruction & RSVD_INSTRUCTION_MASK) == RSVD_INSTRUCTION)
1810 {
1811 sim_monitor (SD, CPU, cia, ((instruction >> RSVD_INSTRUCTION_ARG_SHIFT) & RSVD_INSTRUCTION_ARG_MASK) );
1812 /* NOTE: This assumes that a branch-and-link style
1813 instruction was used to enter the vector (which is the
1814 case with the current IDT monitor). */
1815 sim_engine_restart (SD, CPU, NULL, RA);
1816 }
1817 /* Look for the mips16 entry and exit instructions, and
1818 simulate a handler for them. */
1819 else if ((cia & 1) != 0
1820 && (instruction & 0xf81f) == 0xe809
1821 && (instruction & 0x0c0) != 0x0c0)
1822 {
1823 mips16_entry (SD, CPU, cia, instruction);
1824 sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1825 }
1826 /* else fall through to normal exception processing */
1827 sim_io_eprintf(sd,"ReservedInstruction at PC = 0x%s\n", pr_addr (cia));
1828 }
1829
1830 default:
1831 /* Store exception code into current exception id variable (used
1832 by exit code): */
1833
1834 /* TODO: If not simulating exceptions then stop the simulator
1835 execution. At the moment we always stop the simulation. */
1836
1837 #ifdef SUBTARGET_R3900
1838 /* update interrupt-related registers */
1839
1840 /* insert exception code in bits 6:2 */
1841 CAUSE = LSMASKED32(CAUSE, 31, 7) | LSINSERTED32(exception, 6, 2);
1842 /* shift IE/KU history bits left */
1843 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 3, 0), 5, 2);
1844
1845 if (STATE & simDELAYSLOT)
1846 {
1847 STATE &= ~simDELAYSLOT;
1848 CAUSE |= cause_BD;
1849 EPC = (cia - 4); /* reference the branch instruction */
1850 }
1851 else
1852 EPC = cia;
1853
1854 if (SR & status_BEV)
1855 PC = (signed)0xBFC00000 + 0x180;
1856 else
1857 PC = (signed)0x80000000 + 0x080;
1858 #else
1859 /* See figure 5-17 for an outline of the code below */
1860 if (! (SR & status_EXL))
1861 {
1862 CAUSE = (exception << 2);
1863 if (STATE & simDELAYSLOT)
1864 {
1865 STATE &= ~simDELAYSLOT;
1866 CAUSE |= cause_BD;
1867 EPC = (cia - 4); /* reference the branch instruction */
1868 }
1869 else
1870 EPC = cia;
1871 /* FIXME: TLB et.al. */
1872 /* vector = 0x180; */
1873 }
1874 else
1875 {
1876 CAUSE = (exception << 2);
1877 /* vector = 0x180; */
1878 }
1879 SR |= status_EXL;
1880 /* Store exception code into current exception id variable (used
1881 by exit code): */
1882
1883 if (SR & status_BEV)
1884 PC = (signed)0xBFC00200 + 0x180;
1885 else
1886 PC = (signed)0x80000000 + 0x180;
1887 #endif
1888
1889 switch ((CAUSE >> 2) & 0x1F)
1890 {
1891 case Interrupt:
1892 /* Interrupts arrive during event processing, no need to
1893 restart */
1894 return;
1895
1896 case NMIReset:
1897 /* Ditto */
1898 #ifdef SUBTARGET_3900
1899 /* Exception vector: BEV=0 BFC00000 / BEF=1 BFC00000 */
1900 PC = (signed)0xBFC00000;
1901 #endif SUBTARGET_3900
1902 return;
1903
1904 case TLBModification:
1905 case TLBLoad:
1906 case TLBStore:
1907 case AddressLoad:
1908 case AddressStore:
1909 case InstructionFetch:
1910 case DataReference:
1911 /* The following is so that the simulator will continue from the
1912 exception address on breakpoint operations. */
1913 PC = EPC;
1914 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1915 sim_stopped, SIM_SIGBUS);
1916
1917 case ReservedInstruction:
1918 case CoProcessorUnusable:
1919 PC = EPC;
1920 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1921 sim_stopped, SIM_SIGILL);
1922
1923 case IntegerOverflow:
1924 case FPE:
1925 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1926 sim_stopped, SIM_SIGFPE);
1927
1928 case BreakPoint:
1929 case SystemCall:
1930 case Trap:
1931 sim_engine_restart (SD, CPU, NULL, PC);
1932 break;
1933
1934 case Watch:
1935 PC = EPC;
1936 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1937 sim_stopped, SIM_SIGTRAP);
1938
1939 default : /* Unknown internal exception */
1940 PC = EPC;
1941 sim_engine_halt (SD, CPU, NULL, NULL_CIA,
1942 sim_stopped, SIM_SIGABRT);
1943
1944 }
1945
1946 case SimulatorFault:
1947 {
1948 va_list ap;
1949 char *msg;
1950 va_start(ap,exception);
1951 msg = va_arg(ap,char *);
1952 va_end(ap);
1953 sim_engine_abort (SD, CPU, NULL_CIA,
1954 "FATAL: Simulator error \"%s\"\n",msg);
1955 }
1956 }
1957
1958 return;
1959 }
1960
1961 #if defined(WARN_RESULT)
1962 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1963 /* This function indicates that the result of the operation is
1964 undefined. However, this should not affect the instruction
1965 stream. All that is meant to happen is that the destination
1966 register is set to an undefined result. To keep the simulator
1967 simple, we just don't bother updating the destination register, so
1968 the overall result will be undefined. If desired we can stop the
1969 simulator by raising a pseudo-exception. */
1970 #define UndefinedResult() undefined_result (sd,cia)
1971 static void
1972 undefined_result(sd,cia)
1973 SIM_DESC sd;
1974 address_word cia;
1975 {
1976 sim_io_eprintf(sd,"UndefinedResult: PC = 0x%s\n",pr_addr(cia));
1977 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
1978 state |= simSTOP;
1979 #endif
1980 return;
1981 }
1982 #endif /* WARN_RESULT */
1983
1984 /*-- FPU support routines ---------------------------------------------------*/
1985
1986 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
1987 formats conform to ANSI/IEEE Std 754-1985. */
1988 /* SINGLE precision floating:
1989 * seeeeeeeefffffffffffffffffffffff
1990 * s = 1bit = sign
1991 * e = 8bits = exponent
1992 * f = 23bits = fraction
1993 */
1994 /* SINGLE precision fixed:
1995 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
1996 * s = 1bit = sign
1997 * i = 31bits = integer
1998 */
1999 /* DOUBLE precision floating:
2000 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2001 * s = 1bit = sign
2002 * e = 11bits = exponent
2003 * f = 52bits = fraction
2004 */
2005 /* DOUBLE precision fixed:
2006 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2007 * s = 1bit = sign
2008 * i = 63bits = integer
2009 */
2010
2011 /* Extract sign-bit: */
2012 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2013 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2014 /* Extract biased exponent: */
2015 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2016 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2017 /* Extract unbiased Exponent: */
2018 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2019 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2020 /* Extract complete fraction field: */
2021 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2022 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2023 /* Extract numbered fraction bit: */
2024 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2025 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2026
2027 /* Explicit QNaN values used when value required: */
2028 #define FPQNaN_SINGLE (0x7FBFFFFF)
2029 #define FPQNaN_WORD (0x7FFFFFFF)
2030 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2031 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2032
2033 /* Explicit Infinity values used when required: */
2034 #define FPINF_SINGLE (0x7F800000)
2035 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2036
2037 #if 1 /* def DEBUG */
2038 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2039 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2040 #endif /* DEBUG */
2041
2042 uword64
2043 value_fpr (SIM_DESC sd,
2044 sim_cpu *cpu,
2045 address_word cia,
2046 int fpr,
2047 FP_formats fmt)
2048 {
2049 uword64 value = 0;
2050 int err = 0;
2051
2052 /* Treat unused register values, as fixed-point 64bit values: */
2053 if ((fmt == fmt_uninterpreted) || (fmt == fmt_unknown))
2054 #if 1
2055 /* If request to read data as "uninterpreted", then use the current
2056 encoding: */
2057 fmt = FPR_STATE[fpr];
2058 #else
2059 fmt = fmt_long;
2060 #endif
2061
2062 /* For values not yet accessed, set to the desired format: */
2063 if (FPR_STATE[fpr] == fmt_uninterpreted) {
2064 FPR_STATE[fpr] = fmt;
2065 #ifdef DEBUG
2066 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr,DOFMT(fmt));
2067 #endif /* DEBUG */
2068 }
2069 if (fmt != FPR_STATE[fpr]) {
2070 sim_io_eprintf(sd,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr,DOFMT(FPR_STATE[fpr]),DOFMT(fmt),pr_addr(cia));
2071 FPR_STATE[fpr] = fmt_unknown;
2072 }
2073
2074 if (FPR_STATE[fpr] == fmt_unknown) {
2075 /* Set QNaN value: */
2076 switch (fmt) {
2077 case fmt_single:
2078 value = FPQNaN_SINGLE;
2079 break;
2080
2081 case fmt_double:
2082 value = FPQNaN_DOUBLE;
2083 break;
2084
2085 case fmt_word:
2086 value = FPQNaN_WORD;
2087 break;
2088
2089 case fmt_long:
2090 value = FPQNaN_LONG;
2091 break;
2092
2093 default:
2094 err = -1;
2095 break;
2096 }
2097 } else if (SizeFGR() == 64) {
2098 switch (fmt) {
2099 case fmt_single:
2100 case fmt_word:
2101 value = (FGR[fpr] & 0xFFFFFFFF);
2102 break;
2103
2104 case fmt_uninterpreted:
2105 case fmt_double:
2106 case fmt_long:
2107 value = FGR[fpr];
2108 break;
2109
2110 default :
2111 err = -1;
2112 break;
2113 }
2114 } else {
2115 switch (fmt) {
2116 case fmt_single:
2117 case fmt_word:
2118 value = (FGR[fpr] & 0xFFFFFFFF);
2119 break;
2120
2121 case fmt_uninterpreted:
2122 case fmt_double:
2123 case fmt_long:
2124 if ((fpr & 1) == 0) { /* even registers only */
2125 value = ((((uword64)FGR[fpr+1]) << 32) | (FGR[fpr] & 0xFFFFFFFF));
2126 } else {
2127 SignalException(ReservedInstruction,0);
2128 }
2129 break;
2130
2131 default :
2132 err = -1;
2133 break;
2134 }
2135 }
2136
2137 if (err)
2138 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2139
2140 #ifdef DEBUG
2141 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2142 #endif /* DEBUG */
2143
2144 return(value);
2145 }
2146
2147 void
2148 store_fpr (SIM_DESC sd,
2149 sim_cpu *cpu,
2150 address_word cia,
2151 int fpr,
2152 FP_formats fmt,
2153 uword64 value)
2154 {
2155 int err = 0;
2156
2157 #ifdef DEBUG
2158 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr,DOFMT(fmt),pr_addr(value),pr_addr(cia),SizeFGR());
2159 #endif /* DEBUG */
2160
2161 if (SizeFGR() == 64) {
2162 switch (fmt) {
2163 case fmt_uninterpreted_32:
2164 fmt = fmt_uninterpreted;
2165 case fmt_single :
2166 case fmt_word :
2167 FGR[fpr] = (((uword64)0xDEADC0DE << 32) | (value & 0xFFFFFFFF));
2168 FPR_STATE[fpr] = fmt;
2169 break;
2170
2171 case fmt_uninterpreted_64:
2172 fmt = fmt_uninterpreted;
2173 case fmt_uninterpreted:
2174 case fmt_double :
2175 case fmt_long :
2176 FGR[fpr] = value;
2177 FPR_STATE[fpr] = fmt;
2178 break;
2179
2180 default :
2181 FPR_STATE[fpr] = fmt_unknown;
2182 err = -1;
2183 break;
2184 }
2185 } else {
2186 switch (fmt) {
2187 case fmt_uninterpreted_32:
2188 fmt = fmt_uninterpreted;
2189 case fmt_single :
2190 case fmt_word :
2191 FGR[fpr] = (value & 0xFFFFFFFF);
2192 FPR_STATE[fpr] = fmt;
2193 break;
2194
2195 case fmt_uninterpreted_64:
2196 fmt = fmt_uninterpreted;
2197 case fmt_uninterpreted:
2198 case fmt_double :
2199 case fmt_long :
2200 if ((fpr & 1) == 0) { /* even register number only */
2201 FGR[fpr+1] = (value >> 32);
2202 FGR[fpr] = (value & 0xFFFFFFFF);
2203 FPR_STATE[fpr + 1] = fmt;
2204 FPR_STATE[fpr] = fmt;
2205 } else {
2206 FPR_STATE[fpr] = fmt_unknown;
2207 FPR_STATE[fpr + 1] = fmt_unknown;
2208 SignalException(ReservedInstruction,0);
2209 }
2210 break;
2211
2212 default :
2213 FPR_STATE[fpr] = fmt_unknown;
2214 err = -1;
2215 break;
2216 }
2217 }
2218 #if defined(WARN_RESULT)
2219 else
2220 UndefinedResult();
2221 #endif /* WARN_RESULT */
2222
2223 if (err)
2224 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2225
2226 #ifdef DEBUG
2227 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr,pr_addr(FGR[fpr]),DOFMT(fmt));
2228 #endif /* DEBUG */
2229
2230 return;
2231 }
2232
2233 int
2234 NaN(op,fmt)
2235 uword64 op;
2236 FP_formats fmt;
2237 {
2238 int boolean = 0;
2239 switch (fmt) {
2240 case fmt_single:
2241 case fmt_word:
2242 {
2243 sim_fpu wop;
2244 sim_fpu_32to (&wop, op);
2245 boolean = sim_fpu_is_nan (&wop);
2246 break;
2247 }
2248 case fmt_double:
2249 case fmt_long:
2250 {
2251 sim_fpu wop;
2252 sim_fpu_64to (&wop, op);
2253 boolean = sim_fpu_is_nan (&wop);
2254 break;
2255 }
2256 default:
2257 fprintf (stderr, "Bad switch\n");
2258 abort ();
2259 }
2260
2261 #ifdef DEBUG
2262 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2263 #endif /* DEBUG */
2264
2265 return(boolean);
2266 }
2267
2268 int
2269 Infinity(op,fmt)
2270 uword64 op;
2271 FP_formats fmt;
2272 {
2273 int boolean = 0;
2274
2275 #ifdef DEBUG
2276 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt),pr_addr(op));
2277 #endif /* DEBUG */
2278
2279 switch (fmt) {
2280 case fmt_single:
2281 {
2282 sim_fpu wop;
2283 sim_fpu_32to (&wop, op);
2284 boolean = sim_fpu_is_infinity (&wop);
2285 break;
2286 }
2287 case fmt_double:
2288 {
2289 sim_fpu wop;
2290 sim_fpu_64to (&wop, op);
2291 boolean = sim_fpu_is_infinity (&wop);
2292 break;
2293 }
2294 default:
2295 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt));
2296 break;
2297 }
2298
2299 #ifdef DEBUG
2300 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean,pr_addr(op),DOFMT(fmt));
2301 #endif /* DEBUG */
2302
2303 return(boolean);
2304 }
2305
2306 int
2307 Less(op1,op2,fmt)
2308 uword64 op1;
2309 uword64 op2;
2310 FP_formats fmt;
2311 {
2312 int boolean = 0;
2313
2314 /* Argument checking already performed by the FPCOMPARE code */
2315
2316 #ifdef DEBUG
2317 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2318 #endif /* DEBUG */
2319
2320 /* The format type should already have been checked: */
2321 switch (fmt) {
2322 case fmt_single:
2323 {
2324 sim_fpu wop1;
2325 sim_fpu wop2;
2326 sim_fpu_32to (&wop1, op1);
2327 sim_fpu_32to (&wop2, op2);
2328 boolean = sim_fpu_is_lt (&wop1, &wop2);
2329 break;
2330 }
2331 case fmt_double:
2332 {
2333 sim_fpu wop1;
2334 sim_fpu wop2;
2335 sim_fpu_64to (&wop1, op1);
2336 sim_fpu_64to (&wop2, op2);
2337 boolean = sim_fpu_is_lt (&wop1, &wop2);
2338 break;
2339 }
2340 default:
2341 fprintf (stderr, "Bad switch\n");
2342 abort ();
2343 }
2344
2345 #ifdef DEBUG
2346 printf("DBG: Less: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2347 #endif /* DEBUG */
2348
2349 return(boolean);
2350 }
2351
2352 int
2353 Equal(op1,op2,fmt)
2354 uword64 op1;
2355 uword64 op2;
2356 FP_formats fmt;
2357 {
2358 int boolean = 0;
2359
2360 /* Argument checking already performed by the FPCOMPARE code */
2361
2362 #ifdef DEBUG
2363 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2364 #endif /* DEBUG */
2365
2366 /* The format type should already have been checked: */
2367 switch (fmt) {
2368 case fmt_single:
2369 {
2370 sim_fpu wop1;
2371 sim_fpu wop2;
2372 sim_fpu_32to (&wop1, op1);
2373 sim_fpu_32to (&wop2, op2);
2374 boolean = sim_fpu_is_eq (&wop1, &wop2);
2375 break;
2376 }
2377 case fmt_double:
2378 {
2379 sim_fpu wop1;
2380 sim_fpu wop2;
2381 sim_fpu_64to (&wop1, op1);
2382 sim_fpu_64to (&wop2, op2);
2383 boolean = sim_fpu_is_eq (&wop1, &wop2);
2384 break;
2385 }
2386 default:
2387 fprintf (stderr, "Bad switch\n");
2388 abort ();
2389 }
2390
2391 #ifdef DEBUG
2392 printf("DBG: Equal: returning %d (format = %s)\n",boolean,DOFMT(fmt));
2393 #endif /* DEBUG */
2394
2395 return(boolean);
2396 }
2397
2398 uword64
2399 AbsoluteValue(op,fmt)
2400 uword64 op;
2401 FP_formats fmt;
2402 {
2403 uword64 result = 0;
2404
2405 #ifdef DEBUG
2406 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2407 #endif /* DEBUG */
2408
2409 /* The format type should already have been checked: */
2410 switch (fmt) {
2411 case fmt_single:
2412 {
2413 sim_fpu wop;
2414 unsigned32 ans;
2415 sim_fpu_32to (&wop, op);
2416 sim_fpu_abs (&wop, &wop);
2417 sim_fpu_to32 (&ans, &wop);
2418 result = ans;
2419 break;
2420 }
2421 case fmt_double:
2422 {
2423 sim_fpu wop;
2424 unsigned64 ans;
2425 sim_fpu_64to (&wop, op);
2426 sim_fpu_abs (&wop, &wop);
2427 sim_fpu_to64 (&ans, &wop);
2428 result = ans;
2429 break;
2430 }
2431 default:
2432 fprintf (stderr, "Bad switch\n");
2433 abort ();
2434 }
2435
2436 return(result);
2437 }
2438
2439 uword64
2440 Negate(op,fmt)
2441 uword64 op;
2442 FP_formats fmt;
2443 {
2444 uword64 result = 0;
2445
2446 #ifdef DEBUG
2447 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2448 #endif /* DEBUG */
2449
2450 /* The format type should already have been checked: */
2451 switch (fmt) {
2452 case fmt_single:
2453 {
2454 sim_fpu wop;
2455 unsigned32 ans;
2456 sim_fpu_32to (&wop, op);
2457 sim_fpu_neg (&wop, &wop);
2458 sim_fpu_to32 (&ans, &wop);
2459 result = ans;
2460 break;
2461 }
2462 case fmt_double:
2463 {
2464 sim_fpu wop;
2465 unsigned64 ans;
2466 sim_fpu_64to (&wop, op);
2467 sim_fpu_neg (&wop, &wop);
2468 sim_fpu_to64 (&ans, &wop);
2469 result = ans;
2470 break;
2471 }
2472 default:
2473 fprintf (stderr, "Bad switch\n");
2474 abort ();
2475 }
2476
2477 return(result);
2478 }
2479
2480 uword64
2481 Add(op1,op2,fmt)
2482 uword64 op1;
2483 uword64 op2;
2484 FP_formats fmt;
2485 {
2486 uword64 result = 0;
2487
2488 #ifdef DEBUG
2489 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2490 #endif /* DEBUG */
2491
2492 /* The registers must specify FPRs valid for operands of type
2493 "fmt". If they are not valid, the result is undefined. */
2494
2495 /* The format type should already have been checked: */
2496 switch (fmt) {
2497 case fmt_single:
2498 {
2499 sim_fpu wop1;
2500 sim_fpu wop2;
2501 sim_fpu ans;
2502 unsigned32 res;
2503 sim_fpu_32to (&wop1, op1);
2504 sim_fpu_32to (&wop2, op2);
2505 sim_fpu_add (&ans, &wop1, &wop2);
2506 sim_fpu_to32 (&res, &ans);
2507 result = res;
2508 break;
2509 }
2510 case fmt_double:
2511 {
2512 sim_fpu wop1;
2513 sim_fpu wop2;
2514 sim_fpu ans;
2515 unsigned64 res;
2516 sim_fpu_64to (&wop1, op1);
2517 sim_fpu_64to (&wop2, op2);
2518 sim_fpu_add (&ans, &wop1, &wop2);
2519 sim_fpu_to64 (&res, &ans);
2520 result = res;
2521 break;
2522 }
2523 default:
2524 fprintf (stderr, "Bad switch\n");
2525 abort ();
2526 }
2527
2528 #ifdef DEBUG
2529 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2530 #endif /* DEBUG */
2531
2532 return(result);
2533 }
2534
2535 uword64
2536 Sub(op1,op2,fmt)
2537 uword64 op1;
2538 uword64 op2;
2539 FP_formats fmt;
2540 {
2541 uword64 result = 0;
2542
2543 #ifdef DEBUG
2544 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2545 #endif /* DEBUG */
2546
2547 /* The registers must specify FPRs valid for operands of type
2548 "fmt". If they are not valid, the result is undefined. */
2549
2550 /* The format type should already have been checked: */
2551 switch (fmt) {
2552 case fmt_single:
2553 {
2554 sim_fpu wop1;
2555 sim_fpu wop2;
2556 sim_fpu ans;
2557 unsigned32 res;
2558 sim_fpu_32to (&wop1, op1);
2559 sim_fpu_32to (&wop2, op2);
2560 sim_fpu_sub (&ans, &wop1, &wop2);
2561 sim_fpu_to32 (&res, &ans);
2562 result = res;
2563 }
2564 break;
2565 case fmt_double:
2566 {
2567 sim_fpu wop1;
2568 sim_fpu wop2;
2569 sim_fpu ans;
2570 unsigned64 res;
2571 sim_fpu_64to (&wop1, op1);
2572 sim_fpu_64to (&wop2, op2);
2573 sim_fpu_sub (&ans, &wop1, &wop2);
2574 sim_fpu_to64 (&res, &ans);
2575 result = res;
2576 }
2577 break;
2578 default:
2579 fprintf (stderr, "Bad switch\n");
2580 abort ();
2581 }
2582
2583 #ifdef DEBUG
2584 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2585 #endif /* DEBUG */
2586
2587 return(result);
2588 }
2589
2590 uword64
2591 Multiply(op1,op2,fmt)
2592 uword64 op1;
2593 uword64 op2;
2594 FP_formats fmt;
2595 {
2596 uword64 result = 0;
2597
2598 #ifdef DEBUG
2599 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2600 #endif /* DEBUG */
2601
2602 /* The registers must specify FPRs valid for operands of type
2603 "fmt". If they are not valid, the result is undefined. */
2604
2605 /* The format type should already have been checked: */
2606 switch (fmt) {
2607 case fmt_single:
2608 {
2609 sim_fpu wop1;
2610 sim_fpu wop2;
2611 sim_fpu ans;
2612 unsigned32 res;
2613 sim_fpu_32to (&wop1, op1);
2614 sim_fpu_32to (&wop2, op2);
2615 sim_fpu_mul (&ans, &wop1, &wop2);
2616 sim_fpu_to32 (&res, &ans);
2617 result = res;
2618 break;
2619 }
2620 case fmt_double:
2621 {
2622 sim_fpu wop1;
2623 sim_fpu wop2;
2624 sim_fpu ans;
2625 unsigned64 res;
2626 sim_fpu_64to (&wop1, op1);
2627 sim_fpu_64to (&wop2, op2);
2628 sim_fpu_mul (&ans, &wop1, &wop2);
2629 sim_fpu_to64 (&res, &ans);
2630 result = res;
2631 break;
2632 }
2633 default:
2634 fprintf (stderr, "Bad switch\n");
2635 abort ();
2636 }
2637
2638 #ifdef DEBUG
2639 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2640 #endif /* DEBUG */
2641
2642 return(result);
2643 }
2644
2645 uword64
2646 Divide(op1,op2,fmt)
2647 uword64 op1;
2648 uword64 op2;
2649 FP_formats fmt;
2650 {
2651 uword64 result = 0;
2652
2653 #ifdef DEBUG
2654 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2655 #endif /* DEBUG */
2656
2657 /* The registers must specify FPRs valid for operands of type
2658 "fmt". If they are not valid, the result is undefined. */
2659
2660 /* The format type should already have been checked: */
2661 switch (fmt) {
2662 case fmt_single:
2663 {
2664 sim_fpu wop1;
2665 sim_fpu wop2;
2666 sim_fpu ans;
2667 unsigned32 res;
2668 sim_fpu_32to (&wop1, op1);
2669 sim_fpu_32to (&wop2, op2);
2670 sim_fpu_div (&ans, &wop1, &wop2);
2671 sim_fpu_to32 (&res, &ans);
2672 result = res;
2673 break;
2674 }
2675 case fmt_double:
2676 {
2677 sim_fpu wop1;
2678 sim_fpu wop2;
2679 sim_fpu ans;
2680 unsigned64 res;
2681 sim_fpu_64to (&wop1, op1);
2682 sim_fpu_64to (&wop2, op2);
2683 sim_fpu_div (&ans, &wop1, &wop2);
2684 sim_fpu_to64 (&res, &ans);
2685 result = res;
2686 break;
2687 }
2688 default:
2689 fprintf (stderr, "Bad switch\n");
2690 abort ();
2691 }
2692
2693 #ifdef DEBUG
2694 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2695 #endif /* DEBUG */
2696
2697 return(result);
2698 }
2699
2700 uword64 UNUSED
2701 Recip(op,fmt)
2702 uword64 op;
2703 FP_formats fmt;
2704 {
2705 uword64 result = 0;
2706
2707 #ifdef DEBUG
2708 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2709 #endif /* DEBUG */
2710
2711 /* The registers must specify FPRs valid for operands of type
2712 "fmt". If they are not valid, the result is undefined. */
2713
2714 /* The format type should already have been checked: */
2715 switch (fmt) {
2716 case fmt_single:
2717 {
2718 sim_fpu wop;
2719 sim_fpu ans;
2720 unsigned32 res;
2721 sim_fpu_32to (&wop, op);
2722 sim_fpu_inv (&ans, &wop);
2723 sim_fpu_to32 (&res, &ans);
2724 result = res;
2725 break;
2726 }
2727 case fmt_double:
2728 {
2729 sim_fpu wop;
2730 sim_fpu ans;
2731 unsigned64 res;
2732 sim_fpu_64to (&wop, op);
2733 sim_fpu_inv (&ans, &wop);
2734 sim_fpu_to64 (&res, &ans);
2735 result = res;
2736 break;
2737 }
2738 default:
2739 fprintf (stderr, "Bad switch\n");
2740 abort ();
2741 }
2742
2743 #ifdef DEBUG
2744 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2745 #endif /* DEBUG */
2746
2747 return(result);
2748 }
2749
2750 uword64
2751 SquareRoot(op,fmt)
2752 uword64 op;
2753 FP_formats fmt;
2754 {
2755 uword64 result = 0;
2756
2757 #ifdef DEBUG
2758 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt),pr_addr(op));
2759 #endif /* DEBUG */
2760
2761 /* The registers must specify FPRs valid for operands of type
2762 "fmt". If they are not valid, the result is undefined. */
2763
2764 /* The format type should already have been checked: */
2765 switch (fmt) {
2766 case fmt_single:
2767 {
2768 sim_fpu wop;
2769 sim_fpu ans;
2770 unsigned32 res;
2771 sim_fpu_32to (&wop, op);
2772 sim_fpu_sqrt (&ans, &wop);
2773 sim_fpu_to32 (&res, &ans);
2774 result = res;
2775 break;
2776 }
2777 case fmt_double:
2778 {
2779 sim_fpu wop;
2780 sim_fpu ans;
2781 unsigned64 res;
2782 sim_fpu_64to (&wop, op);
2783 sim_fpu_sqrt (&ans, &wop);
2784 sim_fpu_to64 (&res, &ans);
2785 result = res;
2786 break;
2787 }
2788 default:
2789 fprintf (stderr, "Bad switch\n");
2790 abort ();
2791 }
2792
2793 #ifdef DEBUG
2794 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2795 #endif /* DEBUG */
2796
2797 return(result);
2798 }
2799
2800 #if 0
2801 uword64
2802 Max (uword64 op1,
2803 uword64 op2,
2804 FP_formats fmt)
2805 {
2806 int cmp;
2807 unsigned64 result;
2808
2809 #ifdef DEBUG
2810 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2811 #endif /* DEBUG */
2812
2813 /* The registers must specify FPRs valid for operands of type
2814 "fmt". If they are not valid, the result is undefined. */
2815
2816 /* The format type should already have been checked: */
2817 switch (fmt)
2818 {
2819 case fmt_single:
2820 {
2821 sim_fpu wop1;
2822 sim_fpu wop2;
2823 sim_fpu_32to (&wop1, op1);
2824 sim_fpu_32to (&wop2, op2);
2825 cmp = sim_fpu_cmp (&wop1, &wop2);
2826 break;
2827 }
2828 case fmt_double:
2829 {
2830 sim_fpu wop1;
2831 sim_fpu wop2;
2832 sim_fpu_64to (&wop1, op1);
2833 sim_fpu_64to (&wop2, op2);
2834 cmp = sim_fpu_cmp (&wop1, &wop2);
2835 break;
2836 }
2837 default:
2838 fprintf (stderr, "Bad switch\n");
2839 abort ();
2840 }
2841
2842 switch (cmp)
2843 {
2844 case SIM_FPU_IS_SNAN:
2845 case SIM_FPU_IS_QNAN:
2846 result = op1;
2847 case SIM_FPU_IS_NINF:
2848 case SIM_FPU_IS_NNUMBER:
2849 case SIM_FPU_IS_NDENORM:
2850 case SIM_FPU_IS_NZERO:
2851 result = op2; /* op1 - op2 < 0 */
2852 case SIM_FPU_IS_PINF:
2853 case SIM_FPU_IS_PNUMBER:
2854 case SIM_FPU_IS_PDENORM:
2855 case SIM_FPU_IS_PZERO:
2856 result = op1; /* op1 - op2 > 0 */
2857 default:
2858 fprintf (stderr, "Bad switch\n");
2859 abort ();
2860 }
2861
2862 #ifdef DEBUG
2863 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2864 #endif /* DEBUG */
2865
2866 return(result);
2867 }
2868 #endif
2869
2870 #if 0
2871 uword64
2872 Min (uword64 op1,
2873 uword64 op2,
2874 FP_formats fmt)
2875 {
2876 int cmp;
2877 unsigned64 result;
2878
2879 #ifdef DEBUG
2880 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt),pr_addr(op1),pr_addr(op2));
2881 #endif /* DEBUG */
2882
2883 /* The registers must specify FPRs valid for operands of type
2884 "fmt". If they are not valid, the result is undefined. */
2885
2886 /* The format type should already have been checked: */
2887 switch (fmt)
2888 {
2889 case fmt_single:
2890 {
2891 sim_fpu wop1;
2892 sim_fpu wop2;
2893 sim_fpu_32to (&wop1, op1);
2894 sim_fpu_32to (&wop2, op2);
2895 cmp = sim_fpu_cmp (&wop1, &wop2);
2896 break;
2897 }
2898 case fmt_double:
2899 {
2900 sim_fpu wop1;
2901 sim_fpu wop2;
2902 sim_fpu_64to (&wop1, op1);
2903 sim_fpu_64to (&wop2, op2);
2904 cmp = sim_fpu_cmp (&wop1, &wop2);
2905 break;
2906 }
2907 default:
2908 fprintf (stderr, "Bad switch\n");
2909 abort ();
2910 }
2911
2912 switch (cmp)
2913 {
2914 case SIM_FPU_IS_SNAN:
2915 case SIM_FPU_IS_QNAN:
2916 result = op1;
2917 case SIM_FPU_IS_NINF:
2918 case SIM_FPU_IS_NNUMBER:
2919 case SIM_FPU_IS_NDENORM:
2920 case SIM_FPU_IS_NZERO:
2921 result = op1; /* op1 - op2 < 0 */
2922 case SIM_FPU_IS_PINF:
2923 case SIM_FPU_IS_PNUMBER:
2924 case SIM_FPU_IS_PDENORM:
2925 case SIM_FPU_IS_PZERO:
2926 result = op2; /* op1 - op2 > 0 */
2927 default:
2928 fprintf (stderr, "Bad switch\n");
2929 abort ();
2930 }
2931
2932 #ifdef DEBUG
2933 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result),DOFMT(fmt));
2934 #endif /* DEBUG */
2935
2936 return(result);
2937 }
2938 #endif
2939
2940 uword64
2941 convert (SIM_DESC sd,
2942 sim_cpu *cpu,
2943 address_word cia,
2944 int rm,
2945 uword64 op,
2946 FP_formats from,
2947 FP_formats to)
2948 {
2949 sim_fpu wop;
2950 sim_fpu_round round;
2951 unsigned32 result32;
2952 unsigned64 result64;
2953
2954 #ifdef DEBUG
2955 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm),pr_addr(op),DOFMT(from),DOFMT(to),pr_addr(IPC));
2956 #endif /* DEBUG */
2957
2958 switch (rm)
2959 {
2960 case FP_RM_NEAREST:
2961 /* Round result to nearest representable value. When two
2962 representable values are equally near, round to the value
2963 that has a least significant bit of zero (i.e. is even). */
2964 round = sim_fpu_round_near;
2965 break;
2966 case FP_RM_TOZERO:
2967 /* Round result to the value closest to, and not greater in
2968 magnitude than, the result. */
2969 round = sim_fpu_round_zero;
2970 break;
2971 case FP_RM_TOPINF:
2972 /* Round result to the value closest to, and not less than,
2973 the result. */
2974 round = sim_fpu_round_up;
2975 break;
2976
2977 case FP_RM_TOMINF:
2978 /* Round result to the value closest to, and not greater than,
2979 the result. */
2980 round = sim_fpu_round_down;
2981 break;
2982 default:
2983 round = 0;
2984 fprintf (stderr, "Bad switch\n");
2985 abort ();
2986 }
2987
2988 /* Convert the input to sim_fpu internal format */
2989 switch (from)
2990 {
2991 case fmt_double:
2992 sim_fpu_64to (&wop, op);
2993 break;
2994 case fmt_single:
2995 sim_fpu_32to (&wop, op);
2996 break;
2997 case fmt_word:
2998 sim_fpu_i32to (&wop, op, round);
2999 break;
3000 case fmt_long:
3001 sim_fpu_i64to (&wop, op, round);
3002 break;
3003 default:
3004 fprintf (stderr, "Bad switch\n");
3005 abort ();
3006 }
3007
3008 /* Convert sim_fpu format into the output */
3009 /* The value WOP is converted to the destination format, rounding
3010 using mode RM. When the destination is a fixed-point format, then
3011 a source value of Infinity, NaN or one which would round to an
3012 integer outside the fixed point range then an IEEE Invalid
3013 Operation condition is raised. */
3014 switch (to)
3015 {
3016 case fmt_single:
3017 sim_fpu_round_32 (&wop, round, 0);
3018 sim_fpu_to32 (&result32, &wop);
3019 result64 = result32;
3020 break;
3021 case fmt_double:
3022 sim_fpu_round_64 (&wop, round, 0);
3023 sim_fpu_to64 (&result64, &wop);
3024 break;
3025 case fmt_word:
3026 sim_fpu_to32i (&result32, &wop, round);
3027 result64 = result32;
3028 break;
3029 case fmt_long:
3030 sim_fpu_to64i (&result64, &wop, round);
3031 break;
3032 default:
3033 result64 = 0;
3034 fprintf (stderr, "Bad switch\n");
3035 abort ();
3036 }
3037
3038 #ifdef DEBUG
3039 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64),DOFMT(to));
3040 #endif /* DEBUG */
3041
3042 return(result64);
3043 }
3044
3045
3046 /*-- co-processor support routines ------------------------------------------*/
3047
3048 static int UNUSED
3049 CoProcPresent(coproc_number)
3050 unsigned int coproc_number;
3051 {
3052 /* Return TRUE if simulator provides a model for the given co-processor number */
3053 return(0);
3054 }
3055
3056 void
3057 cop_lw (SIM_DESC sd,
3058 sim_cpu *cpu,
3059 address_word cia,
3060 int coproc_num,
3061 int coproc_reg,
3062 unsigned int memword)
3063 {
3064 switch (coproc_num)
3065 {
3066 case 1:
3067 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3068 {
3069 #ifdef DEBUG
3070 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword,pr_addr(memword));
3071 #endif
3072 StoreFPR(coproc_reg,fmt_word,(uword64)memword);
3073 FPR_STATE[coproc_reg] = fmt_uninterpreted;
3074 break;
3075 }
3076
3077 default:
3078 #if 0 /* this should be controlled by a configuration option */
3079 sim_io_printf(sd,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,memword,pr_addr(cia));
3080 #endif
3081 break;
3082 }
3083
3084 return;
3085 }
3086
3087 void
3088 cop_ld (SIM_DESC sd,
3089 sim_cpu *cpu,
3090 address_word cia,
3091 int coproc_num,
3092 int coproc_reg,
3093 uword64 memword)
3094 {
3095 switch (coproc_num) {
3096 case 1:
3097 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3098 {
3099 StoreFPR(coproc_reg,fmt_uninterpreted,memword);
3100 break;
3101 }
3102
3103 default:
3104 #if 0 /* this message should be controlled by a configuration option */
3105 sim_io_printf(sd,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(memword),pr_addr(cia));
3106 #endif
3107 break;
3108 }
3109
3110 return;
3111 }
3112
3113
3114 /* start-sanitize-sky */
3115 #ifdef TARGET_SKY
3116 void
3117 cop_lq (SIM_DESC sd,
3118 sim_cpu *cpu,
3119 address_word cia,
3120 int coproc_num,
3121 int coproc_reg,
3122 unsigned128 memword)
3123 {
3124 switch (coproc_num)
3125 {
3126 case 2:
3127 {
3128 int i;
3129
3130 while(vu0_busy())
3131 vu0_issue(sd);
3132
3133 /* one word at a time, argh! */
3134 for(i=0; i<4; i++)
3135 {
3136 unsigned_4 value;
3137 value = H2T_4(*A4_16(& memword, 3-i));
3138 write_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3139 }
3140 }
3141 break;
3142
3143 default:
3144 sim_io_printf(sd,"COP_LQ(%d,%d,??) at PC = 0x%s : TODO (architecture specific)\n",
3145 coproc_num,coproc_reg,pr_addr(cia));
3146 break;
3147 }
3148
3149 return;
3150 }
3151 #endif /* TARGET_SKY */
3152 /* end-sanitize-sky */
3153
3154
3155 unsigned int
3156 cop_sw (SIM_DESC sd,
3157 sim_cpu *cpu,
3158 address_word cia,
3159 int coproc_num,
3160 int coproc_reg)
3161 {
3162 unsigned int value = 0;
3163
3164 switch (coproc_num)
3165 {
3166 case 1:
3167 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3168 {
3169 FP_formats hold;
3170 hold = FPR_STATE[coproc_reg];
3171 FPR_STATE[coproc_reg] = fmt_word;
3172 value = (unsigned int)ValueFPR(coproc_reg,fmt_uninterpreted);
3173 FPR_STATE[coproc_reg] = hold;
3174 break;
3175 }
3176
3177 default:
3178 #if 0 /* should be controlled by configuration option */
3179 sim_io_printf(sd,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3180 #endif
3181 break;
3182 }
3183
3184 return(value);
3185 }
3186
3187 uword64
3188 cop_sd (SIM_DESC sd,
3189 sim_cpu *cpu,
3190 address_word cia,
3191 int coproc_num,
3192 int coproc_reg)
3193 {
3194 uword64 value = 0;
3195 switch (coproc_num)
3196 {
3197 case 1:
3198 if (CURRENT_FLOATING_POINT == HARD_FLOATING_POINT)
3199 {
3200 value = ValueFPR(coproc_reg,fmt_uninterpreted);
3201 break;
3202 }
3203
3204 default:
3205 #if 0 /* should be controlled by configuration option */
3206 sim_io_printf(sd,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num,coproc_reg,pr_addr(cia));
3207 #endif
3208 break;
3209 }
3210
3211 return(value);
3212 }
3213
3214
3215 /* start-sanitize-sky */
3216 #ifdef TARGET_SKY
3217 unsigned128
3218 cop_sq (SIM_DESC sd,
3219 sim_cpu *cpu,
3220 address_word cia,
3221 int coproc_num,
3222 int coproc_reg)
3223 {
3224 unsigned128 value = U16_8(0, 0);
3225 switch (coproc_num)
3226 {
3227 case 2:
3228 {
3229 unsigned_16 xyzw;
3230 int i;
3231
3232 while(vu0_busy())
3233 vu0_issue(sd);
3234
3235 /* one word at a time, argh! */
3236 for(i=0; i<4; i++)
3237 {
3238 unsigned_4 value;
3239 read_vu_vec_reg(&(vu0_device.regs), coproc_reg, i, & value);
3240 *A4_16(& xyzw, 3-i) = T2H_4(value);
3241 }
3242 return xyzw;
3243 }
3244 break;
3245
3246 default:
3247 sim_io_printf(sd,"COP_SQ(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",
3248 coproc_num,coproc_reg,pr_addr(cia));
3249 break;
3250 }
3251
3252 return(value);
3253 }
3254 #endif /* TARGET_SKY */
3255 /* end-sanitize-sky */
3256
3257
3258 void
3259 decode_coproc (SIM_DESC sd,
3260 sim_cpu *cpu,
3261 address_word cia,
3262 unsigned int instruction)
3263 {
3264 int coprocnum = ((instruction >> 26) & 3);
3265
3266 switch (coprocnum)
3267 {
3268 case 0: /* standard CPU control and cache registers */
3269 {
3270 int code = ((instruction >> 21) & 0x1F);
3271 /* R4000 Users Manual (second edition) lists the following CP0
3272 instructions:
3273 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3274 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3275 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3276 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3277 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3278 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3279 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3280 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3281 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3282 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3283 */
3284 if (((code == 0x00) || (code == 0x04)) && ((instruction & 0x7FF) == 0))
3285 {
3286 int rt = ((instruction >> 16) & 0x1F);
3287 int rd = ((instruction >> 11) & 0x1F);
3288
3289 switch (rd) /* NOTEs: Standard CP0 registers */
3290 {
3291 /* 0 = Index R4000 VR4100 VR4300 */
3292 /* 1 = Random R4000 VR4100 VR4300 */
3293 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3294 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3295 /* 4 = Context R4000 VR4100 VR4300 */
3296 /* 5 = PageMask R4000 VR4100 VR4300 */
3297 /* 6 = Wired R4000 VR4100 VR4300 */
3298 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3299 /* 9 = Count R4000 VR4100 VR4300 */
3300 /* 10 = EntryHi R4000 VR4100 VR4300 */
3301 /* 11 = Compare R4000 VR4100 VR4300 */
3302 /* 12 = SR R4000 VR4100 VR4300 */
3303 #ifdef SUBTARGET_R3900
3304 case 3:
3305 /* ignore */
3306 break;
3307 /* 3 = Config R3900 */
3308 #endif /* SUBTARGET_R3900 */
3309 case 12:
3310 if (code == 0x00)
3311 GPR[rt] = SR;
3312 else
3313 SR = GPR[rt];
3314 break;
3315 /* 13 = Cause R4000 VR4100 VR4300 */
3316 case 13:
3317 if (code == 0x00)
3318 GPR[rt] = CAUSE;
3319 else
3320 CAUSE = GPR[rt];
3321 break;
3322 /* 14 = EPC R4000 VR4100 VR4300 */
3323 case 14:
3324 if (code == 0x00)
3325 GPR[rt] = (signed_word) (signed_address) EPC;
3326 else
3327 EPC = GPR[rt];
3328 break;
3329 /* 15 = PRId R4000 VR4100 VR4300 */
3330 #ifdef SUBTARGET_R3900
3331 /* 16 = Debug */
3332 case 16:
3333 if (code == 0x00)
3334 GPR[rt] = Debug;
3335 else
3336 Debug = GPR[rt];
3337 break;
3338 #else
3339 /* 16 = Config R4000 VR4100 VR4300 */
3340 case 16:
3341 if (code == 0x00)
3342 GPR[rt] = C0_CONFIG;
3343 else
3344 C0_CONFIG = GPR[rt];
3345 break;
3346 #endif
3347 #ifdef SUBTARGET_R3900
3348 /* 17 = Debug */
3349 case 17:
3350 if (code == 0x00)
3351 GPR[rt] = DEPC;
3352 else
3353 DEPC = GPR[rt];
3354 break;
3355 #else
3356 /* 17 = LLAddr R4000 VR4100 VR4300 */
3357 #endif
3358 /* 18 = WatchLo R4000 VR4100 VR4300 */
3359 /* 19 = WatchHi R4000 VR4100 VR4300 */
3360 /* 20 = XContext R4000 VR4100 VR4300 */
3361 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3362 /* 27 = CacheErr R4000 VR4100 */
3363 /* 28 = TagLo R4000 VR4100 VR4300 */
3364 /* 29 = TagHi R4000 VR4100 VR4300 */
3365 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3366 GPR[rt] = 0xDEADC0DE; /* CPR[0,rd] */
3367 /* CPR[0,rd] = GPR[rt]; */
3368 default:
3369 if (code == 0x00)
3370 sim_io_printf(sd,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt,rd);
3371 else
3372 sim_io_printf(sd,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt,rd);
3373 }
3374 }
3375 else if (code == 0x10 && (instruction & 0x3f) == 0x18)
3376 {
3377 /* ERET */
3378 if (SR & status_ERL)
3379 {
3380 /* Oops, not yet available */
3381 sim_io_printf(sd,"Warning: ERET when SR[ERL] set not handled yet");
3382 PC = EPC;
3383 SR &= ~status_ERL;
3384 }
3385 else
3386 {
3387 PC = EPC;
3388 SR &= ~status_EXL;
3389 }
3390 }
3391 else if (code == 0x10 && (instruction & 0x3f) == 0x10)
3392 {
3393 /* RFE */
3394 #ifdef SUBTARGET_R3900
3395 /* TX39: Copy IEp/KUp -> IEc/KUc, and IEo/KUo -> IEp/KUp */
3396
3397 /* shift IE/KU history bits right */
3398 SR = LSMASKED32(SR, 31, 4) | LSINSERTED32(LSEXTRACTED32(SR, 5, 2), 3, 0);
3399
3400 /* TODO: CACHE register */
3401 #endif /* SUBTARGET_R3900 */
3402 }
3403 else if (code == 0x10 && (instruction & 0x3f) == 0x1F)
3404 {
3405 /* DERET */
3406 Debug &= ~Debug_DM;
3407 DELAYSLOT();
3408 DSPC = DEPC;
3409 }
3410 else
3411 sim_io_eprintf(sd,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction,pr_addr(cia));
3412 /* TODO: When executing an ERET or RFE instruction we should
3413 clear LLBIT, to ensure that any out-standing atomic
3414 read/modify/write sequence fails. */
3415 }
3416 break;
3417
3418 case 2: /* co-processor 2 */
3419 {
3420 int handle = 0;
3421
3422 /* start-sanitize-sky */
3423 #ifdef TARGET_SKY
3424 /* On the R5900, this refers to a "VU" vector co-processor. */
3425
3426 int i_25_21 = (instruction >> 21) & 0x1f;
3427 int i_20_16 = (instruction >> 16) & 0x1f;
3428 int i_20_6 = (instruction >> 6) & 0x7fff;
3429 int i_15_11 = (instruction >> 11) & 0x1f;
3430 int i_15_0 = instruction & 0xffff;
3431 int i_10_1 = (instruction >> 1) & 0x3ff;
3432 int i_10_0 = instruction & 0x7ff;
3433 int i_10_6 = (instruction >> 6) & 0x1f;
3434 int i_5_0 = instruction & 0x03f;
3435 int interlock = instruction & 0x01;
3436 /* setup for semantic.c-like actions below */
3437 typedef unsigned_4 instruction_word;
3438 int CIA = cia;
3439 int NIA = cia + 4;
3440
3441 handle = 1;
3442
3443 /* test COP2 usability */
3444 if(! (SR & status_CU2))
3445 {
3446 SignalException(CoProcessorUnusable,instruction);
3447 /* NOTREACHED */
3448 }
3449
3450 #define MY_INDEX itable_COPz_NORMAL
3451 #define MY_PREFIX COPz_NORMAL
3452 #define MY_NAME "COPz_NORMAL"
3453
3454 /* classify & execute basic COP2 instructions */
3455 if(i_25_21 == 0x08 && i_20_16 == 0x00) /* BC2F */
3456 {
3457 address_word offset = EXTEND16(i_15_0) << 2;
3458 if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3459 }
3460 else if(i_25_21 == 0x08 && i_20_16==0x02) /* BC2FL */
3461 {
3462 address_word offset = EXTEND16(i_15_0) << 2;
3463 if(! vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3464 else NULLIFY_NEXT_INSTRUCTION();
3465 }
3466 else if(i_25_21 == 0x08 && i_20_16 == 0x01) /* BC2T */
3467 {
3468 address_word offset = EXTEND16(i_15_0) << 2;
3469 if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3470 }
3471 else if(i_25_21 == 0x08 && i_20_16 == 0x03) /* BC2TL */
3472 {
3473 address_word offset = EXTEND16(i_15_0) << 2;
3474 if(vu0_busy()) DELAY_SLOT(cia + 4 + offset);
3475 else NULLIFY_NEXT_INSTRUCTION();
3476 }
3477 else if((i_25_21 == 0x02 && i_10_1 == 0x000) || /* CFC2 */
3478 (i_25_21 == 0x01)) /* QMFC2 */
3479 {
3480 int rt = i_20_16;
3481 int id = i_15_11;
3482
3483 /* interlock checking */
3484 /* POLICY: never busy in macro mode */
3485 while(vu0_busy() && interlock)
3486 vu0_issue(sd);
3487
3488 /* perform VU register address */
3489 if(i_25_21 == 0x01) /* QMFC2 */
3490 {
3491 unsigned_16 xyzw;
3492 /* one word at a time, argh! */
3493 read_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
3494 read_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
3495 read_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
3496 read_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
3497 GPR[rt] = T2H_8(* A8_16(& xyzw, 1));
3498 GPR1[rt] = T2H_8(* A8_16(& xyzw, 0));
3499 }
3500 else /* CFC2 */
3501 {
3502 unsigned_4 data;
3503 /* enum + int calculation, argh! */
3504 id = VU_REG_MST + 16 * id;
3505 if (id >= VU_REG_CMSAR0)
3506 read_vu_special_reg(&vu0_device, id, & data);
3507 else
3508 read_vu_misc_reg(&(vu0_device.regs), id, & data);
3509 GPR[rt] = EXTEND32(T2H_4(data));
3510 }
3511 }
3512 else if((i_25_21 == 0x06 && i_10_1 == 0x000) || /* CTC2 */
3513 (i_25_21 == 0x05)) /* QMTC2 */
3514 {
3515 int rt = i_20_16;
3516 int id = i_15_11;
3517
3518 /* interlock checking: wait until M or E bits set */
3519 /* POLICY: never busy in macro mode */
3520 while(vu0_busy() && interlock)
3521 {
3522 if(vu0_micro_interlock_released())
3523 {
3524 vu0_micro_interlock_clear();
3525 break;
3526 }
3527
3528 vu0_issue(sd);
3529 }
3530
3531 /* perform VU register address */
3532 if(i_25_21 == 0x05) /* QMTC2 */
3533 {
3534 unsigned_16 xyzw = U16_8(GPR1[rt], GPR[rt]);
3535
3536 xyzw = H2T_16(xyzw);
3537 /* one word at a time, argh! */
3538 write_vu_vec_reg(&(vu0_device.regs), id, 0, A4_16(& xyzw, 3));
3539 write_vu_vec_reg(&(vu0_device.regs), id, 1, A4_16(& xyzw, 2));
3540 write_vu_vec_reg(&(vu0_device.regs), id, 2, A4_16(& xyzw, 1));
3541 write_vu_vec_reg(&(vu0_device.regs), id, 3, A4_16(& xyzw, 0));
3542 }
3543 else /* CTC2 */
3544 {
3545 unsigned_4 data = H2T_4(GPR[rt]);
3546 /* enum + int calculation, argh! */
3547 id = VU_REG_VI + 16 * id;
3548 if (id >= VU_REG_CMSAR0)
3549 write_vu_special_reg(&vu0_device, id, & data);
3550 else
3551 write_vu_misc_reg(&(vu0_device.regs), id, & data);
3552 }
3553 }
3554 else if(i_10_0 == 0x3bf) /* VWAITQ */
3555 {
3556 while(vu0_q_busy())
3557 vu0_issue(sd);
3558 }
3559 else if(i_5_0 == 0x38) /* VCALLMS */
3560 {
3561 unsigned_4 data = H2T_2(i_20_6);
3562
3563 while(vu0_busy())
3564 vu0_issue(sd);
3565
3566 /* write to reserved CIA register to get VU0 moving */
3567 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3568
3569 ASSERT(vu0_busy());
3570 }
3571 else if(i_5_0 == 0x39) /* VCALLMSR */
3572 {
3573 unsigned_4 data;
3574
3575 while(vu0_busy())
3576 vu0_issue(sd);
3577
3578 read_vu_special_reg(& vu0_device, VU_REG_CMSAR0, & data);
3579 /* write to reserved CIA register to get VU0 moving */
3580 write_vu_special_reg(& vu0_device, VU_REG_CIA, & data);
3581
3582 ASSERT(vu0_busy());
3583 }
3584 /* handle all remaining UPPER VU instructions in one block */
3585 else if((i_5_0 < 0x30) || /* VADDx .. VMINI */
3586 (i_5_0 >= 0x3c && i_10_6 < 0x0c)) /* VADDAx .. VNOP */
3587 {
3588 unsigned_4 vu_upper, vu_lower;
3589 vu_upper =
3590 0x00000000 | /* bits 31 .. 25 */
3591 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3592 vu_lower = 0x8000033c; /* NOP */
3593
3594 /* POLICY: never busy in macro mode */
3595 while(vu0_busy())
3596 vu0_issue(sd);
3597
3598 vu0_macro_issue(vu_upper, vu_lower);
3599
3600 /* POLICY: wait for completion of macro-instruction */
3601 while(vu0_busy())
3602 vu0_issue(sd);
3603 }
3604 /* handle all remaining LOWER VU instructions in one block */
3605 else if((i_5_0 >= 0x30 && i_5_0 <= 0x35) || /* VIADD .. VIOR */
3606 (i_5_0 >= 0x3c && i_10_6 >= 0x0c)) /* VMOVE .. VRXOR */
3607 { /* N.B.: VWAITQ already covered by prior case */
3608 unsigned_4 vu_upper, vu_lower;
3609 vu_upper = 0x000002ff; /* NOP/NOP */
3610 vu_lower =
3611 0x80000000 | /* bits 31 .. 25 */
3612 (instruction & 0x01ffffff); /* bits 24 .. 0 */
3613
3614 /* POLICY: never busy in macro mode */
3615 while(vu0_busy())
3616 vu0_issue(sd);
3617
3618 vu0_macro_issue(vu_upper, vu_lower);
3619
3620 /* POLICY: wait for completion of macro-instruction */
3621 while(vu0_busy())
3622 vu0_issue(sd);
3623 }
3624 /* ... no other COP2 instructions ... */
3625 else
3626 {
3627 SignalException(ReservedInstruction, instruction);
3628 /* NOTREACHED */
3629 }
3630
3631 /* cleanup for semantic.c-like actions above */
3632 PC = NIA;
3633
3634 #undef MY_INDEX
3635 #undef MY_PREFIX
3636 #undef MY_NAME
3637
3638 #endif /* TARGET_SKY */
3639 /* end-sanitize-sky */
3640
3641 if(! handle)
3642 {
3643 sim_io_eprintf(sd, "COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",
3644 instruction,pr_addr(cia));
3645 }
3646 }
3647 break;
3648
3649 case 1: /* should not occur (FPU co-processor) */
3650 case 3: /* should not occur (FPU co-processor) */
3651 SignalException(ReservedInstruction,instruction);
3652 break;
3653 }
3654
3655 return;
3656 }
3657
3658
3659 /*-- instruction simulation -------------------------------------------------*/
3660
3661 /* When the IGEN simulator is being built, the function below is be
3662 replaced by a generated version. However, WITH_IGEN == 2 indicates
3663 that the fubction below should be compiled but under a different
3664 name (to allow backward compatibility) */
3665
3666 #if (WITH_IGEN != 1)
3667 #if (WITH_IGEN > 1)
3668 void old_engine_run PARAMS ((SIM_DESC sd, int next_cpu_nr, int siggnal));
3669 void
3670 old_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3671 #else
3672 void
3673 sim_engine_run (sd, next_cpu_nr, nr_cpus, siggnal)
3674 #endif
3675 SIM_DESC sd;
3676 int next_cpu_nr; /* ignore */
3677 int nr_cpus; /* ignore */
3678 int siggnal; /* ignore */
3679 {
3680 sim_cpu *cpu = STATE_CPU (sd, 0); /* hardwire to cpu 0 */
3681 #if !defined(FASTSIM)
3682 unsigned int pipeline_count = 1;
3683 #endif
3684
3685 #ifdef DEBUG
3686 if (STATE_MEMORY (sd) == NULL) {
3687 printf("DBG: simulate() entered with no memory\n");
3688 exit(1);
3689 }
3690 #endif /* DEBUG */
3691
3692 #if 0 /* Disabled to check that everything works OK */
3693 /* The VR4300 seems to sign-extend the PC on its first
3694 access. However, this may just be because it is currently
3695 configured in 32bit mode. However... */
3696 PC = SIGNEXTEND(PC,32);
3697 #endif
3698
3699 /* main controlling loop */
3700 while (1) {
3701 /* vaddr is slowly being replaced with cia - current instruction
3702 address */
3703 address_word cia = (uword64)PC;
3704 address_word vaddr = cia;
3705 address_word paddr;
3706 int cca;
3707 unsigned int instruction; /* uword64? what's this used for? FIXME! */
3708
3709 #ifdef DEBUG
3710 {
3711 printf("DBG: state = 0x%08X :",state);
3712 if (state & simHALTEX) printf(" simHALTEX");
3713 if (state & simHALTIN) printf(" simHALTIN");
3714 printf("\n");
3715 }
3716 #endif /* DEBUG */
3717
3718 DSSTATE = (STATE & simDELAYSLOT);
3719 #ifdef DEBUG
3720 if (dsstate)
3721 sim_io_printf(sd,"DBG: DSPC = 0x%s\n",pr_addr(DSPC));
3722 #endif /* DEBUG */
3723
3724 /* Fetch the next instruction from the simulator memory: */
3725 if (AddressTranslation(cia,isINSTRUCTION,isLOAD,&paddr,&cca,isTARGET,isREAL)) {
3726 if ((vaddr & 1) == 0) {
3727 /* Copy the action of the LW instruction */
3728 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 2) : 0);
3729 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 2) : 0);
3730 uword64 value;
3731 unsigned int byte;
3732 paddr = ((paddr & ~LOADDRMASK) | ((paddr & LOADDRMASK) ^ (reverse << 2)));
3733 LoadMemory(&value,NULL,cca,AccessLength_WORD,paddr,vaddr,isINSTRUCTION,isREAL);
3734 byte = ((vaddr & LOADDRMASK) ^ (bigend << 2));
3735 instruction = ((value >> (8 * byte)) & 0xFFFFFFFF);
3736 } else {
3737 /* Copy the action of the LH instruction */
3738 unsigned int reverse = (ReverseEndian ? (LOADDRMASK >> 1) : 0);
3739 unsigned int bigend = (BigEndianCPU ? (LOADDRMASK >> 1) : 0);
3740 uword64 value;
3741 unsigned int byte;
3742 paddr = (((paddr & ~ (uword64) 1) & ~LOADDRMASK)
3743 | (((paddr & ~ (uword64) 1) & LOADDRMASK) ^ (reverse << 1)));
3744 LoadMemory(&value,NULL,cca, AccessLength_HALFWORD,
3745 paddr & ~ (uword64) 1,
3746 vaddr, isINSTRUCTION, isREAL);
3747 byte = (((vaddr &~ (uword64) 1) & LOADDRMASK) ^ (bigend << 1));
3748 instruction = ((value >> (8 * byte)) & 0xFFFF);
3749 }
3750 } else {
3751 fprintf(stderr,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC));
3752 exit(1);
3753 }
3754
3755 #ifdef DEBUG
3756 sim_io_printf(sd,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction,pr_addr(PC));
3757 #endif /* DEBUG */
3758
3759 /* This is required by exception processing, to ensure that we can
3760 cope with exceptions in the delay slots of branches that may
3761 already have changed the PC. */
3762 if ((vaddr & 1) == 0)
3763 PC += 4; /* increment ready for the next fetch */
3764 else
3765 PC += 2;
3766 /* NOTE: If we perform a delay slot change to the PC, this
3767 increment is not requuired. However, it would make the
3768 simulator more complicated to try and avoid this small hit. */
3769
3770 /* Currently this code provides a simple model. For more
3771 complicated models we could perform exception status checks at
3772 this point, and set the simSTOP state as required. This could
3773 also include processing any hardware interrupts raised by any
3774 I/O model attached to the simulator context.
3775
3776 Support for "asynchronous" I/O events within the simulated world
3777 could be providing by managing a counter, and calling a I/O
3778 specific handler when a particular threshold is reached. On most
3779 architectures a decrement and check for zero operation is
3780 usually quicker than an increment and compare. However, the
3781 process of managing a known value decrement to zero, is higher
3782 than the cost of using an explicit value UINT_MAX into the
3783 future. Which system is used will depend on how complicated the
3784 I/O model is, and how much it is likely to affect the simulator
3785 bandwidth.
3786
3787 If events need to be scheduled further in the future than
3788 UINT_MAX event ticks, then the I/O model should just provide its
3789 own counter, triggered from the event system. */
3790
3791 /* MIPS pipeline ticks. To allow for future support where the
3792 pipeline hit of individual instructions is known, this control
3793 loop manages a "pipeline_count" variable. It is initialised to
3794 1 (one), and will only be changed by the simulator engine when
3795 executing an instruction. If the engine does not have access to
3796 pipeline cycle count information then all instructions will be
3797 treated as using a single cycle. NOTE: A standard system is not
3798 provided by the default simulator because different MIPS
3799 architectures have different cycle counts for the same
3800 instructions.
3801
3802 [NOTE: pipeline_count has been replaced the event queue] */
3803
3804 /* shuffle the floating point status pipeline state */
3805 ENGINE_ISSUE_PREFIX_HOOK();
3806
3807 /* NOTE: For multi-context simulation environments the "instruction"
3808 variable should be local to this routine. */
3809
3810 /* Shorthand accesses for engine. Note: If we wanted to use global
3811 variables (and a single-threaded simulator engine), then we can
3812 create the actual variables with these names. */
3813
3814 if (!(STATE & simSKIPNEXT)) {
3815 /* Include the simulator engine */
3816 #include "oengine.c"
3817 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3818 #error "Mismatch between run-time simulator code and simulation engine"
3819 #endif
3820 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3821 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3822 #endif
3823 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3824 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3825 #endif
3826
3827 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3828 should check for it being changed. It is better doing it here,
3829 than within the simulator, since it will help keep the simulator
3830 small. */
3831 if (ZERO != 0) {
3832 #if defined(WARN_ZERO)
3833 sim_io_eprintf(sd,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO),pr_addr(cia));
3834 #endif /* WARN_ZERO */
3835 ZERO = 0; /* reset back to zero before next instruction */
3836 }
3837 } else /* simSKIPNEXT check */
3838 STATE &= ~simSKIPNEXT;
3839
3840 /* If the delay slot was active before the instruction is
3841 executed, then update the PC to its new value: */
3842 if (DSSTATE) {
3843 #ifdef DEBUG
3844 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC));
3845 #endif /* DEBUG */
3846 PC = DSPC;
3847 CANCELDELAYSLOT();
3848 }
3849
3850 if (MIPSISA < 4)
3851 PENDING_TICK();
3852
3853 #if !defined(FASTSIM)
3854 if (sim_events_tickn (sd, pipeline_count))
3855 {
3856 /* cpu->cia = cia; */
3857 sim_events_process (sd);
3858 }
3859 #else
3860 if (sim_events_tick (sd))
3861 {
3862 /* cpu->cia = cia; */
3863 sim_events_process (sd);
3864 }
3865 #endif /* FASTSIM */
3866 }
3867 }
3868 #endif
3869
3870
3871 /* This code copied from gdb's utils.c. Would like to share this code,
3872 but don't know of a common place where both could get to it. */
3873
3874 /* Temporary storage using circular buffer */
3875 #define NUMCELLS 16
3876 #define CELLSIZE 32
3877 static char*
3878 get_cell()
3879 {
3880 static char buf[NUMCELLS][CELLSIZE];
3881 static int cell=0;
3882 if (++cell>=NUMCELLS) cell=0;
3883 return buf[cell];
3884 }
3885
3886 /* Print routines to handle variable size regs, etc */
3887
3888 /* Eliminate warning from compiler on 32-bit systems */
3889 static int thirty_two = 32;
3890
3891 char*
3892 pr_addr(addr)
3893 SIM_ADDR addr;
3894 {
3895 char *paddr_str=get_cell();
3896 switch (sizeof(addr))
3897 {
3898 case 8:
3899 sprintf(paddr_str,"%08lx%08lx",
3900 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3901 break;
3902 case 4:
3903 sprintf(paddr_str,"%08lx",(unsigned long)addr);
3904 break;
3905 case 2:
3906 sprintf(paddr_str,"%04x",(unsigned short)(addr&0xffff));
3907 break;
3908 default:
3909 sprintf(paddr_str,"%x",addr);
3910 }
3911 return paddr_str;
3912 }
3913
3914 char*
3915 pr_uword64(addr)
3916 uword64 addr;
3917 {
3918 char *paddr_str=get_cell();
3919 sprintf(paddr_str,"%08lx%08lx",
3920 (unsigned long)(addr>>thirty_two),(unsigned long)(addr&0xffffffff));
3921 return paddr_str;
3922 }
3923
3924
3925
3926 /*---------------------------------------------------------------------------*/
3927 /*> EOF interp.c <*/