2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
73 char* pr_addr
PARAMS ((SIM_ADDR addr
));
74 char* pr_uword64
PARAMS ((uword64 addr
));
77 /* Get the simulator engine description, without including the code: */
79 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
86 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
91 /* The following reserved instruction value is used when a simulator
92 trap is required. NOTE: Care must be taken, since this value may be
93 used in later revisions of the MIPS ISA. */
94 #define RSVD_INSTRUCTION (0x00000005)
95 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
97 #define RSVD_INSTRUCTION_ARG_SHIFT 6
98 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
101 /* Bits in the Debug register */
102 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
103 #define Debug_DM 0x40000000 /* Debug Mode */
104 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
110 /*---------------------------------------------------------------------------*/
111 /*-- GDB simulator interface ------------------------------------------------*/
112 /*---------------------------------------------------------------------------*/
114 static void ColdReset
PARAMS((SIM_DESC sd
));
116 /*---------------------------------------------------------------------------*/
120 #define DELAYSLOT() {\
121 if (STATE & simDELAYSLOT)\
122 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
123 STATE |= simDELAYSLOT;\
126 #define JALDELAYSLOT() {\
128 STATE |= simJALDELAYSLOT;\
132 STATE &= ~simDELAYSLOT;\
133 STATE |= simSKIPNEXT;\
136 #define CANCELDELAYSLOT() {\
138 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
141 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
142 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
144 #define K0BASE (0x80000000)
145 #define K0SIZE (0x20000000)
146 #define K1BASE (0xA0000000)
147 #define K1SIZE (0x20000000)
148 #define MONITOR_BASE (0xBFC00000)
149 #define MONITOR_SIZE (1 << 11)
150 #define MEM_SIZE (2 << 20)
153 static char *tracefile
= "trace.din"; /* default filename for trace log */
154 FILE *tracefh
= NULL
;
155 static void open_trace
PARAMS((SIM_DESC sd
));
158 #define OPTION_DINERO_TRACE 200
159 #define OPTION_DINERO_FILE 201
162 mips_option_handler (sd
, opt
, arg
)
170 case OPTION_DINERO_TRACE
: /* ??? */
172 /* Eventually the simTRACE flag could be treated as a toggle, to
173 allow external control of the program points being traced
174 (i.e. only from main onwards, excluding the run-time setup,
176 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
178 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
181 else if (strcmp (arg
, "yes") == 0)
183 else if (strcmp (arg
, "no") == 0)
185 else if (strcmp (arg
, "on") == 0)
187 else if (strcmp (arg
, "off") == 0)
191 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
198 Simulator constructed without dinero tracing support (for performance).\n\
199 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
203 case OPTION_DINERO_FILE
:
205 if (optarg
!= NULL
) {
207 tmp
= (char *)malloc(strlen(optarg
) + 1);
210 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
216 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
227 static const OPTION mips_options
[] =
229 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
230 '\0', "on|off", "Enable dinero tracing",
231 mips_option_handler
},
232 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
233 '\0', "FILE", "Write dinero trace to FILE",
234 mips_option_handler
},
235 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
239 int interrupt_pending
;
242 interrupt_event (SIM_DESC sd
, void *data
)
244 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
247 interrupt_pending
= 0;
248 SignalExceptionInterrupt ();
250 else if (!interrupt_pending
)
251 sim_events_schedule (sd
, 1, interrupt_event
, data
);
255 /*---------------------------------------------------------------------------*/
256 /*-- Device registration hook -----------------------------------------------*/
257 /*---------------------------------------------------------------------------*/
258 static void device_init(SIM_DESC sd
) {
260 extern void register_devices(SIM_DESC
);
261 register_devices(sd
);
265 /* start-sanitize-sky */
269 int f
[NUM_VU_REGS
- 16];
272 /* end-sanitize-sky */
274 /*---------------------------------------------------------------------------*/
275 /*-- GDB simulator interface ------------------------------------------------*/
276 /*---------------------------------------------------------------------------*/
279 sim_open (kind
, cb
, abfd
, argv
)
285 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
286 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
288 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
290 /* FIXME: watchpoints code shouldn't need this */
291 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
292 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
293 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
297 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
299 sim_add_option_table (sd
, mips_options
);
301 /* Allocate core managed memory */
304 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
305 /* For compatibility with the old code - under this (at level one)
306 are the kernel spaces K0 & K1. Both of these map to a single
307 smaller sub region */
308 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
309 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
311 MEM_SIZE
, /* actual size */
316 /* getopt will print the error message so we just have to exit if this fails.
317 FIXME: Hmmm... in the case of gdb we need getopt to call
319 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
321 /* Uninstall the modules to avoid memory leaks,
322 file descriptor leaks, etc. */
323 sim_module_uninstall (sd
);
327 /* check for/establish the a reference program image */
328 if (sim_analyze_program (sd
,
329 (STATE_PROG_ARGV (sd
) != NULL
330 ? *STATE_PROG_ARGV (sd
)
334 sim_module_uninstall (sd
);
338 /* Configure/verify the target byte order and other runtime
339 configuration options */
340 if (sim_config (sd
) != SIM_RC_OK
)
342 sim_module_uninstall (sd
);
346 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
348 /* Uninstall the modules to avoid memory leaks,
349 file descriptor leaks, etc. */
350 sim_module_uninstall (sd
);
354 /* verify assumptions the simulator made about the host type system.
355 This macro does not return if there is a problem */
356 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
357 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
359 /* This is NASTY, in that we are assuming the size of specific
363 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
366 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
367 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
368 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
369 else if ((rn
>= 33) && (rn
<= 37))
370 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
371 else if ((rn
== SRIDX
)
374 || ((rn
>= 72) && (rn
<= 89)))
375 cpu
->register_widths
[rn
] = 32;
377 cpu
->register_widths
[rn
] = 0;
379 /* start-sanitize-r5900 */
381 /* set the 5900 "upper" registers to 64 bits */
382 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
383 cpu
->register_widths
[rn
] = 64;
384 /* end-sanitize-r5900 */
386 /* start-sanitize-sky */
388 /* Now the VU registers */
389 for( rn
= 0; rn
< 16; rn
++ ) { /* first the integer registers */
390 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
391 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
393 /* Hack for now - to test gdb interface */
394 vu_regs
[0].i
[rn
] = rn
+ 0x100;
395 vu_regs
[1].i
[rn
] = rn
+ 0x200;
398 for( rn
= 16; rn
< NUM_VU_REGS
; rn
++ ) { /* then the FP registers */
401 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
402 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
404 /* Hack for now - to test gdb interface */
407 vu_regs
[0].f
[rn
-16] = *((unsigned *) &f
);
409 vu_regs
[1].f
[rn
-16] = *((unsigned *) &f
);
412 f
= (rn
- 24)/4 + (rn
- 24)%4 + 1000.0;
413 vu_regs
[0].f
[rn
-16] = *((unsigned *) &f
);
414 f
= (rn
- 24)/4 + (rn
- 24)%4 + 2000.0;
415 vu_regs
[1].f
[rn
-16] = *((unsigned *) &f
);
419 /* end-sanitize-sky */
423 if (STATE
& simTRACE
)
427 /* Write the monitor trap address handlers into the monitor (eeprom)
428 address space. This can only be done once the target endianness
429 has been determined. */
432 /* Entry into the IDT monitor is via fixed address vectors, and
433 not using machine instructions. To avoid clashing with use of
434 the MIPS TRAP system, we place our own (simulator specific)
435 "undefined" instructions into the relevant vector slots. */
436 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
438 address_word vaddr
= (MONITOR_BASE
+ loop
);
439 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
441 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
443 /* The PMON monitor uses the same address space, but rather than
444 branching into it the address of a routine is loaded. We can
445 cheat for the moment, and direct the PMON routine to IDT style
446 instructions within the monitor space. This relies on the IDT
447 monitor not using the locations from 0xBFC00500 onwards as its
449 for (loop
= 0; (loop
< 24); loop
++)
451 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
452 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
468 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
470 case 8: /* cliexit */
473 case 11: /* flush_cache */
477 /* FIXME - should monitor_base be SIM_ADDR?? */
478 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
480 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
482 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
484 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
496 tracefh
= fopen(tracefile
,"wb+");
499 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
506 sim_close (sd
, quitting
)
511 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
514 /* "quitting" is non-zero if we cannot hang on errors */
516 /* Ensure that any resources allocated through the callback
517 mechanism are released: */
518 sim_io_shutdown (sd
);
521 if (tracefh
!= NULL
&& tracefh
!= stderr
)
526 /* FIXME - free SD */
533 sim_write (sd
,addr
,buffer
,size
)
536 unsigned char *buffer
;
540 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
542 /* Return the number of bytes written, or zero if error. */
544 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
547 /* We use raw read and write routines, since we do not want to count
548 the GDB memory accesses in our statistics gathering. */
550 for (index
= 0; index
< size
; index
++)
552 address_word vaddr
= (address_word
)addr
+ index
;
555 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
557 if (sim_core_write_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
565 sim_read (sd
,addr
,buffer
,size
)
568 unsigned char *buffer
;
572 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
574 /* Return the number of bytes read, or zero if error. */
576 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
579 for (index
= 0; (index
< size
); index
++)
581 address_word vaddr
= (address_word
)addr
+ index
;
584 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
586 if (sim_core_read_buffer (SD
, CPU
, sim_core_read_map
, buffer
+ index
, paddr
, 1) != 1)
594 sim_store_register (sd
,rn
,memory
,length
)
597 unsigned char *memory
;
600 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
601 /* NOTE: gdb (the client) stores registers in target byte order
602 while the simulator uses host byte order */
604 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
607 /* Unfortunately this suffers from the same problem as the register
608 numbering one. We need to know what the width of each logical
609 register number is for the architecture being simulated. */
611 if (cpu
->register_widths
[rn
] == 0)
613 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
617 /* start-sanitize-r5900 */
618 if (rn
>= 90 && rn
< 90 + 32)
620 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
626 SA
= T2H_8(*(unsigned64
*)memory
);
628 case 122: /* FIXME */
629 LO1
= T2H_8(*(unsigned64
*)memory
);
631 case 123: /* FIXME */
632 HI1
= T2H_8(*(unsigned64
*)memory
);
636 /* end-sanitize-r5900 */
637 /* start-sanitize-sky */
639 else if( rn
> NUM_R5900_REGS
) {
640 rn
= rn
- NUM_R5900_REGS
;
643 vu_regs
[0].i
[rn
] = T2H_2( *(unsigned short *) memory
);
644 else if( rn
< NUM_VU_REGS
)
645 vu_regs
[0].f
[rn
- 16] = T2H_4( *(unsigned int *) memory
);
647 rn
= rn
- NUM_VU_REGS
;
650 vu_regs
[1].i
[rn
] = T2H_2( *(unsigned short *) memory
);
651 else if( rn
< NUM_VU_REGS
)
652 vu_regs
[1].f
[rn
- 16] = T2H_4( *(unsigned int *) memory
);
654 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
658 /* end-sanitize-sky */
660 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
662 if (cpu
->register_widths
[rn
] == 32)
664 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
669 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
674 if (cpu
->register_widths
[rn
] == 32)
676 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
681 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
687 sim_fetch_register (sd
,rn
,memory
,length
)
690 unsigned char *memory
;
693 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
694 /* NOTE: gdb (the client) stores registers in target byte order
695 while the simulator uses host byte order */
697 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
700 if (cpu
->register_widths
[rn
] == 0)
702 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
706 /* start-sanitize-r5900 */
707 if (rn
>= 90 && rn
< 90 + 32)
709 *(unsigned64
*)memory
= GPR1
[rn
- 90];
715 *((unsigned64
*)memory
) = H2T_8(SA
);
717 case 122: /* FIXME */
718 *((unsigned64
*)memory
) = H2T_8(LO1
);
720 case 123: /* FIXME */
721 *((unsigned64
*)memory
) = H2T_8(HI1
);
725 /* end-sanitize-r5900 */
726 /* start-sanitize-sky */
728 if( rn
> NUM_R5900_REGS
) {
729 rn
= rn
- NUM_R5900_REGS
;
732 *((unsigned short *) memory
) = H2T_2( vu_regs
[0].i
[rn
] );
733 else if( rn
< NUM_VU_REGS
)
734 *((unsigned int *) memory
) = H2T_4( vu_regs
[0].f
[rn
- 16] );
736 rn
= rn
- NUM_VU_REGS
;
739 (*(unsigned short *) memory
) = H2T_2( vu_regs
[1].i
[rn
] );
740 else if( rn
< NUM_VU_REGS
)
741 (*(unsigned int *) memory
) = H2T_4( vu_regs
[1].f
[rn
- 16] );
743 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
749 /* end-sanitize-sky */
751 /* Any floating point register */
752 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
754 if (cpu
->register_widths
[rn
] == 32)
756 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
761 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
766 if (cpu
->register_widths
[rn
] == 32)
768 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
773 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
780 sim_info (sd
,verbose
)
784 /* Accessed from the GDB "info files" command: */
785 if (STATE_VERBOSE_P (sd
) || verbose
)
788 sim_io_printf (sd
, "MIPS %d-bit %s endian simulator\n",
789 WITH_TARGET_WORD_BITSIZE
,
790 (CURRENT_TARGET_BYTE_ORDER
== BIG_ENDIAN
? "Big" : "Little"));
792 #if !defined(FASTSIM)
793 /* It would be a useful feature, if when performing multi-cycle
794 simulations (rather than single-stepping) we keep the start and
795 end times of the execution, so that we can give a performance
796 figure for the simulator. */
797 #endif /* !FASTSIM */
798 sim_io_printf (sd
, "Number of execution cycles = %ld\n",
799 (long) sim_events_time (sd
));
801 /* print information pertaining to MIPS ISA and architecture being simulated */
802 /* things that may be interesting */
803 /* instructions executed - if available */
804 /* cycles executed - if available */
805 /* pipeline stalls - if available */
806 /* virtual time taken */
808 /* profiling frequency */
812 profile_print (sd
, STATE_VERBOSE_P (sd
), NULL
, NULL
);
817 sim_create_inferior (sd
, abfd
, argv
,env
)
825 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
833 /* override PC value set by ColdReset () */
835 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
837 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
838 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
842 #if 0 /* def DEBUG */
845 /* We should really place the argv slot values into the argument
846 registers, and onto the stack as required. However, this
847 assumes that we have a stack defined, which is not
848 necessarily true at the moment. */
850 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
851 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
852 printf("DBG: arg \"%s\"\n",*cptr
);
860 sim_do_command (sd
,cmd
)
864 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
865 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
869 /*---------------------------------------------------------------------------*/
870 /*-- Private simulator support interface ------------------------------------*/
871 /*---------------------------------------------------------------------------*/
873 /* Read a null terminated string from memory, return in a buffer */
882 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
884 buf
= NZALLOC (char, nr
+ 1);
885 sim_read (sd
, addr
, buf
, nr
);
889 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
891 sim_monitor (SIM_DESC sd
,
897 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
900 /* The IDT monitor actually allows two instructions per vector
901 slot. However, the simulator currently causes a trap on each
902 individual instruction. We cheat, and lose the bottom bit. */
905 /* The following callback functions are available, however the
906 monitor we are simulating does not make use of them: get_errno,
907 isatty, lseek, rename, system, time and unlink */
911 case 6: /* int open(char *path,int flags) */
913 char *path
= fetch_str (sd
, A0
);
914 V0
= sim_io_open (sd
, path
, (int)A1
);
919 case 7: /* int read(int file,char *ptr,int len) */
923 char *buf
= zalloc (nr
);
924 V0
= sim_io_read (sd
, fd
, buf
, nr
);
925 sim_write (sd
, A1
, buf
, nr
);
930 case 8: /* int write(int file,char *ptr,int len) */
934 char *buf
= zalloc (nr
);
935 sim_read (sd
, A1
, buf
, nr
);
936 V0
= sim_io_write (sd
, fd
, buf
, nr
);
941 case 10: /* int close(int file) */
943 V0
= sim_io_close (sd
, (int)A0
);
947 case 2: /* Densan monitor: char inbyte(int waitflag) */
949 if (A0
== 0) /* waitflag == NOWAIT */
950 V0
= (unsigned_word
)-1;
952 /* Drop through to case 11 */
954 case 11: /* char inbyte(void) */
957 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
959 sim_io_error(sd
,"Invalid return from character read");
960 V0
= (unsigned_word
)-1;
963 V0
= (unsigned_word
)tmp
;
967 case 3: /* Densan monitor: void co(char chr) */
968 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
970 char tmp
= (char)(A0
& 0xFF);
971 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
975 case 17: /* void _exit() */
977 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
978 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
979 (unsigned int)(A0
& 0xFFFFFFFF));
983 case 28 : /* PMON flush_cache */
986 case 55: /* void get_mem_info(unsigned int *ptr) */
987 /* in: A0 = pointer to three word memory location */
988 /* out: [A0 + 0] = size */
989 /* [A0 + 4] = instruction cache size */
990 /* [A0 + 8] = data cache size */
992 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
994 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
995 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
999 case 158 : /* PMON printf */
1000 /* in: A0 = pointer to format string */
1001 /* A1 = optional argument 1 */
1002 /* A2 = optional argument 2 */
1003 /* A3 = optional argument 3 */
1005 /* The following is based on the PMON printf source */
1007 address_word s
= A0
;
1009 signed_word
*ap
= &A1
; /* 1st argument */
1010 /* This isn't the quickest way, since we call the host print
1011 routine for every character almost. But it does avoid
1012 having to allocate and manage a temporary string buffer. */
1013 /* TODO: Include check that we only use three arguments (A1,
1015 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1020 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1021 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1022 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1024 if (strchr ("dobxXulscefg%", s
))
1039 else if (c
>= '1' && c
<= '9')
1043 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1046 n
= (unsigned int)strtol(tmp
,NULL
,10);
1059 sim_io_printf (sd
, "%%");
1064 address_word p
= *ap
++;
1066 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1067 sim_io_printf(sd
, "%c", ch
);
1070 sim_io_printf(sd
,"(null)");
1073 sim_io_printf (sd
, "%c", (int)*ap
++);
1078 sim_read (sd
, s
++, &c
, 1);
1082 sim_read (sd
, s
++, &c
, 1);
1085 if (strchr ("dobxXu", c
))
1087 word64 lv
= (word64
) *ap
++;
1089 sim_io_printf(sd
,"<binary not supported>");
1092 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1094 sim_io_printf(sd
, tmp
, lv
);
1096 sim_io_printf(sd
, tmp
, (int)lv
);
1099 else if (strchr ("eEfgG", c
))
1101 double dbl
= *(double*)(ap
++);
1102 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1103 sim_io_printf (sd
, tmp
, dbl
);
1109 sim_io_printf(sd
, "%c", c
);
1115 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1116 reason
, pr_addr(cia
));
1122 /* Store a word into memory. */
1125 store_word (SIM_DESC sd
,
1134 if ((vaddr
& 3) != 0)
1135 SignalExceptionAddressStore ();
1138 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1141 const uword64 mask
= 7;
1145 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1146 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1147 memval
= ((uword64
) val
) << (8 * byte
);
1148 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1154 /* Load a word from memory. */
1157 load_word (SIM_DESC sd
,
1162 if ((vaddr
& 3) != 0)
1163 SignalExceptionAddressLoad ();
1169 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1172 const uword64 mask
= 0x7;
1173 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1174 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1178 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1179 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1181 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1182 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1189 /* Simulate the mips16 entry and exit pseudo-instructions. These
1190 would normally be handled by the reserved instruction exception
1191 code, but for ease of simulation we just handle them directly. */
1194 mips16_entry (SIM_DESC sd
,
1199 int aregs
, sregs
, rreg
;
1202 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1205 aregs
= (insn
& 0x700) >> 8;
1206 sregs
= (insn
& 0x0c0) >> 6;
1207 rreg
= (insn
& 0x020) >> 5;
1209 /* This should be checked by the caller. */
1218 /* This is the entry pseudo-instruction. */
1220 for (i
= 0; i
< aregs
; i
++)
1221 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1229 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1232 for (i
= 0; i
< sregs
; i
++)
1235 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1243 /* This is the exit pseudo-instruction. */
1250 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1253 for (i
= 0; i
< sregs
; i
++)
1256 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1261 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1265 FGR
[0] = WORD64LO (GPR
[4]);
1266 FPR_STATE
[0] = fmt_uninterpreted
;
1268 else if (aregs
== 6)
1270 FGR
[0] = WORD64LO (GPR
[5]);
1271 FGR
[1] = WORD64LO (GPR
[4]);
1272 FPR_STATE
[0] = fmt_uninterpreted
;
1273 FPR_STATE
[1] = fmt_uninterpreted
;
1282 /*-- trace support ----------------------------------------------------------*/
1284 /* The TRACE support is provided (if required) in the memory accessing
1285 routines. Since we are also providing the architecture specific
1286 features, the architecture simulation code can also deal with
1287 notifying the TRACE world of cache flushes, etc. Similarly we do
1288 not need to provide profiling support in the simulator engine,
1289 since we can sample in the instruction fetch control loop. By
1290 defining the TRACE manifest, we add tracing as a run-time
1294 /* Tracing by default produces "din" format (as required by
1295 dineroIII). Each line of such a trace file *MUST* have a din label
1296 and address field. The rest of the line is ignored, so comments can
1297 be included if desired. The first field is the label which must be
1298 one of the following values:
1303 3 escape record (treated as unknown access type)
1304 4 escape record (causes cache flush)
1306 The address field is a 32bit (lower-case) hexadecimal address
1307 value. The address should *NOT* be preceded by "0x".
1309 The size of the memory transfer is not important when dealing with
1310 cache lines (as long as no more than a cache line can be
1311 transferred in a single operation :-), however more information
1312 could be given following the dineroIII requirement to allow more
1313 complete memory and cache simulators to provide better
1314 results. i.e. the University of Pisa has a cache simulator that can
1315 also take bus size and speed as (variable) inputs to calculate
1316 complete system performance (a much more useful ability when trying
1317 to construct an end product, rather than a processor). They
1318 currently have an ARM version of their tool called ChARM. */
1322 dotrace (SIM_DESC sd
,
1330 if (STATE
& simTRACE
) {
1332 fprintf(tracefh
,"%d %s ; width %d ; ",
1336 va_start(ap
,comment
);
1337 vfprintf(tracefh
,comment
,ap
);
1339 fprintf(tracefh
,"\n");
1341 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1342 we may be generating 64bit ones, we should put the hi-32bits of the
1343 address into the comment field. */
1345 /* TODO: Provide a buffer for the trace lines. We can then avoid
1346 performing writes until the buffer is filled, or the file is
1349 /* NOTE: We could consider adding a comment field to the "din" file
1350 produced using type 3 markers (unknown access). This would then
1351 allow information about the program that the "din" is for, and
1352 the MIPs world that was being simulated, to be placed into the
1359 /*---------------------------------------------------------------------------*/
1360 /*-- simulator engine -------------------------------------------------------*/
1361 /*---------------------------------------------------------------------------*/
1364 ColdReset (SIM_DESC sd
)
1367 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1369 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1370 /* RESET: Fixed PC address: */
1371 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1372 /* The reset vector address is in the unmapped, uncached memory space. */
1374 SR
&= ~(status_SR
| status_TS
| status_RP
);
1375 SR
|= (status_ERL
| status_BEV
);
1377 /* Cheat and allow access to the complete register set immediately */
1378 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1379 && WITH_TARGET_WORD_BITSIZE
== 64)
1380 SR
|= status_FR
; /* 64bit registers */
1382 /* Ensure that any instructions with pending register updates are
1384 PENDING_INVALIDATE();
1386 /* Initialise the FPU registers to the unknown state */
1387 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1390 for (rn
= 0; (rn
< 32); rn
++)
1391 FPR_STATE
[rn
] = fmt_uninterpreted
;
1397 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1399 /* Translate a virtual address to a physical address and cache
1400 coherence algorithm describing the mechanism used to resolve the
1401 memory reference. Given the virtual address vAddr, and whether the
1402 reference is to Instructions ot Data (IorD), find the corresponding
1403 physical address (pAddr) and the cache coherence algorithm (CCA)
1404 used to resolve the reference. If the virtual address is in one of
1405 the unmapped address spaces the physical address and the CCA are
1406 determined directly by the virtual address. If the virtual address
1407 is in one of the mapped address spaces then the TLB is used to
1408 determine the physical address and access type; if the required
1409 translation is not present in the TLB or the desired access is not
1410 permitted the function fails and an exception is taken.
1412 NOTE: Normally (RAW == 0), when address translation fails, this
1413 function raises an exception and does not return. */
1416 address_translation (SIM_DESC sd
,
1422 address_word
*pAddr
,
1426 int res
= -1; /* TRUE : Assume good return */
1429 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1432 /* Check that the address is valid for this memory model */
1434 /* For a simple (flat) memory model, we simply pass virtual
1435 addressess through (mostly) unchanged. */
1436 vAddr
&= 0xFFFFFFFF;
1438 *pAddr
= vAddr
; /* default for isTARGET */
1439 *CCA
= Uncached
; /* not used for isHOST */
1444 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1446 /* Prefetch data from memory. Prefetch is an advisory instruction for
1447 which an implementation specific action is taken. The action taken
1448 may increase performance, but must not change the meaning of the
1449 program, or alter architecturally-visible state. */
1452 prefetch (SIM_DESC sd
,
1462 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1465 /* For our simple memory model we do nothing */
1469 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1471 /* Load a value from memory. Use the cache and main memory as
1472 specified in the Cache Coherence Algorithm (CCA) and the sort of
1473 access (IorD) to find the contents of AccessLength memory bytes
1474 starting at physical location pAddr. The data is returned in the
1475 fixed width naturally-aligned memory element (MemElem). The
1476 low-order two (or three) bits of the address and the AccessLength
1477 indicate which of the bytes within MemElem needs to be given to the
1478 processor. If the memory access type of the reference is uncached
1479 then only the referenced bytes are read from memory and valid
1480 within the memory element. If the access type is cached, and the
1481 data is not present in cache, an implementation specific size and
1482 alignment block of memory is read and loaded into the cache to
1483 satisfy a load reference. At a minimum, the block is the entire
1486 load_memory (SIM_DESC sd
,
1501 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1504 #if defined(WARN_MEM)
1505 if (CCA
!= uncached
)
1506 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1507 #endif /* WARN_MEM */
1509 /* If instruction fetch then we need to check that the two lo-order
1510 bits are zero, otherwise raise a InstructionFetch exception: */
1511 if ((IorD
== isINSTRUCTION
)
1512 && ((pAddr
& 0x3) != 0)
1513 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1514 SignalExceptionInstructionFetch ();
1516 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1518 /* In reality this should be a Bus Error */
1519 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1521 (LOADDRMASK
+ 1) << 2,
1526 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1529 /* Read the specified number of bytes from memory. Adjust for
1530 host/target byte ordering/ Align the least significant byte
1533 switch (AccessLength
)
1535 case AccessLength_QUADWORD
:
1537 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
,
1538 sim_core_read_map
, pAddr
);
1539 value1
= VH8_16 (val
);
1540 value
= VL8_16 (val
);
1543 case AccessLength_DOUBLEWORD
:
1544 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1545 sim_core_read_map
, pAddr
);
1547 case AccessLength_SEPTIBYTE
:
1548 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1549 sim_core_read_map
, pAddr
);
1551 case AccessLength_SEXTIBYTE
:
1552 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1553 sim_core_read_map
, pAddr
);
1555 case AccessLength_QUINTIBYTE
:
1556 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1557 sim_core_read_map
, pAddr
);
1559 case AccessLength_WORD
:
1560 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1561 sim_core_read_map
, pAddr
);
1563 case AccessLength_TRIPLEBYTE
:
1564 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1565 sim_core_read_map
, pAddr
);
1567 case AccessLength_HALFWORD
:
1568 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1569 sim_core_read_map
, pAddr
);
1571 case AccessLength_BYTE
:
1572 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1573 sim_core_read_map
, pAddr
);
1580 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1581 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1584 /* See also store_memory. */
1585 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1588 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1589 shifted to the most significant byte position. */
1590 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1592 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1593 is already in the correct postition. */
1594 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1598 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1599 pr_uword64(value1
),pr_uword64(value
));
1603 if (memval1p
) *memval1p
= value1
;
1607 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1609 /* Store a value to memory. The specified data is stored into the
1610 physical location pAddr using the memory hierarchy (data caches and
1611 main memory) as specified by the Cache Coherence Algorithm
1612 (CCA). The MemElem contains the data for an aligned, fixed-width
1613 memory element (word for 32-bit processors, doubleword for 64-bit
1614 processors), though only the bytes that will actually be stored to
1615 memory need to be valid. The low-order two (or three) bits of pAddr
1616 and the AccessLength field indicates which of the bytes within the
1617 MemElem data should actually be stored; only these bytes in memory
1621 store_memory (SIM_DESC sd
,
1627 uword64 MemElem1
, /* High order 64 bits */
1632 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1635 #if defined(WARN_MEM)
1636 if (CCA
!= uncached
)
1637 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1638 #endif /* WARN_MEM */
1640 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1641 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1644 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1648 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1651 /* See also load_memory */
1652 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1655 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1656 shifted to the most significant byte position. */
1657 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1659 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1660 is already in the correct postition. */
1661 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1665 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1668 switch (AccessLength
)
1670 case AccessLength_QUADWORD
:
1672 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1673 sim_core_write_aligned_16 (cpu
, NULL_CIA
,
1674 sim_core_write_map
, pAddr
, val
);
1677 case AccessLength_DOUBLEWORD
:
1678 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1679 sim_core_write_map
, pAddr
, MemElem
);
1681 case AccessLength_SEPTIBYTE
:
1682 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1683 sim_core_write_map
, pAddr
, MemElem
);
1685 case AccessLength_SEXTIBYTE
:
1686 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1687 sim_core_write_map
, pAddr
, MemElem
);
1689 case AccessLength_QUINTIBYTE
:
1690 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1691 sim_core_write_map
, pAddr
, MemElem
);
1693 case AccessLength_WORD
:
1694 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1695 sim_core_write_map
, pAddr
, MemElem
);
1697 case AccessLength_TRIPLEBYTE
:
1698 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1699 sim_core_write_map
, pAddr
, MemElem
);
1701 case AccessLength_HALFWORD
:
1702 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1703 sim_core_write_map
, pAddr
, MemElem
);
1705 case AccessLength_BYTE
:
1706 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1707 sim_core_write_map
, pAddr
, MemElem
);
1718 ifetch32 (SIM_DESC sd
,
1723 /* Copy the action of the LW instruction */
1724 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1725 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1728 unsigned32 instruction
;
1731 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1732 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1733 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1734 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1735 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1741 ifetch16 (SIM_DESC sd
,
1746 /* Copy the action of the LW instruction */
1747 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1748 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1751 unsigned16 instruction
;
1754 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1755 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1756 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1757 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1758 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1763 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1764 /* Order loads and stores to synchronise shared memory. Perform the
1765 action necessary to make the effects of groups of synchronizable
1766 loads and stores indicated by stype occur in the same order for all
1769 sync_operation (SIM_DESC sd
,
1775 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1780 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1781 /* Signal an exception condition. This will result in an exception
1782 that aborts the instruction. The instruction operation pseudocode
1783 will never see a return from this function call. */
1786 signal_exception (SIM_DESC sd
,
1794 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1797 /* Ensure that any active atomic read/modify/write operation will fail: */
1800 switch (exception
) {
1801 /* TODO: For testing purposes I have been ignoring TRAPs. In
1802 reality we should either simulate them, or allow the user to
1803 ignore them at run-time.
1806 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1812 unsigned int instruction
;
1815 va_start(ap
,exception
);
1816 instruction
= va_arg(ap
,unsigned int);
1819 code
= (instruction
>> 6) & 0xFFFFF;
1821 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1822 code
, pr_addr(cia
));
1826 case DebugBreakPoint
:
1827 if (! (Debug
& Debug_DM
))
1833 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1834 DEPC
= cia
- 4; /* reference the branch instruction */
1838 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1842 Debug
|= Debug_DM
; /* in debugging mode */
1843 Debug
|= Debug_DBp
; /* raising a DBp exception */
1845 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1849 case ReservedInstruction
:
1852 unsigned int instruction
;
1853 va_start(ap
,exception
);
1854 instruction
= va_arg(ap
,unsigned int);
1856 /* Provide simple monitor support using ReservedInstruction
1857 exceptions. The following code simulates the fixed vector
1858 entry points into the IDT monitor by causing a simulator
1859 trap, performing the monitor operation, and returning to
1860 the address held in the $ra register (standard PCS return
1861 address). This means we only need to pre-load the vector
1862 space with suitable instruction values. For systems were
1863 actual trap instructions are used, we would not need to
1864 perform this magic. */
1865 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1867 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1868 /* NOTE: This assumes that a branch-and-link style
1869 instruction was used to enter the vector (which is the
1870 case with the current IDT monitor). */
1871 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1873 /* Look for the mips16 entry and exit instructions, and
1874 simulate a handler for them. */
1875 else if ((cia
& 1) != 0
1876 && (instruction
& 0xf81f) == 0xe809
1877 && (instruction
& 0x0c0) != 0x0c0)
1879 mips16_entry (SD
, CPU
, cia
, instruction
);
1880 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1882 /* else fall through to normal exception processing */
1883 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1888 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1890 /* Keep a copy of the current A0 in-case this is the program exit
1894 unsigned int instruction
;
1895 va_start(ap
,exception
);
1896 instruction
= va_arg(ap
,unsigned int);
1898 /* Check for our special terminating BREAK: */
1899 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1900 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1901 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1904 if (STATE
& simDELAYSLOT
)
1905 PC
= cia
- 4; /* reference the branch instruction */
1908 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1909 sim_stopped
, SIM_SIGTRAP
);
1912 /* Store exception code into current exception id variable (used
1915 /* TODO: If not simulating exceptions then stop the simulator
1916 execution. At the moment we always stop the simulation. */
1918 /* See figure 5-17 for an outline of the code below */
1919 if (! (SR
& status_EXL
))
1921 CAUSE
= (exception
<< 2);
1922 if (STATE
& simDELAYSLOT
)
1924 STATE
&= ~simDELAYSLOT
;
1926 EPC
= (cia
- 4); /* reference the branch instruction */
1930 /* FIXME: TLB et.al. */
1935 CAUSE
= (exception
<< 2);
1939 /* Store exception code into current exception id variable (used
1941 if (SR
& status_BEV
)
1942 PC
= (signed)0xBFC00200 + 0x180;
1944 PC
= (signed)0x80000000 + 0x180;
1946 switch ((CAUSE
>> 2) & 0x1F)
1949 /* Interrupts arrive during event processing, no need to
1953 case TLBModification
:
1958 case InstructionFetch
:
1960 /* The following is so that the simulator will continue from the
1961 exception address on breakpoint operations. */
1963 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1964 sim_stopped
, SIM_SIGBUS
);
1966 case ReservedInstruction
:
1967 case CoProcessorUnusable
:
1969 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1970 sim_stopped
, SIM_SIGILL
);
1972 case IntegerOverflow
:
1974 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1975 sim_stopped
, SIM_SIGFPE
);
1981 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1982 sim_stopped
, SIM_SIGTRAP
);
1986 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1987 "FATAL: Should not encounter a breakpoint\n");
1989 default : /* Unknown internal exception */
1991 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1992 sim_stopped
, SIM_SIGABRT
);
1996 case SimulatorFault
:
2000 va_start(ap
,exception
);
2001 msg
= va_arg(ap
,char *);
2003 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2004 "FATAL: Simulator error \"%s\"\n",msg
);
2011 #if defined(WARN_RESULT)
2012 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2013 /* This function indicates that the result of the operation is
2014 undefined. However, this should not affect the instruction
2015 stream. All that is meant to happen is that the destination
2016 register is set to an undefined result. To keep the simulator
2017 simple, we just don't bother updating the destination register, so
2018 the overall result will be undefined. If desired we can stop the
2019 simulator by raising a pseudo-exception. */
2020 #define UndefinedResult() undefined_result (sd,cia)
2022 undefined_result(sd
,cia
)
2026 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
2027 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2032 #endif /* WARN_RESULT */
2035 cache_op (SIM_DESC sd
,
2041 unsigned int instruction
)
2043 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2044 static int icache_warning
= 1;
2045 static int dcache_warning
= 1;
2047 static int icache_warning
= 0;
2048 static int dcache_warning
= 0;
2051 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2052 enable bit in the Status Register is clear - a coprocessor
2053 unusable exception is taken. */
2055 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
2059 case 0: /* instruction cache */
2061 case 0: /* Index Invalidate */
2062 case 1: /* Index Load Tag */
2063 case 2: /* Index Store Tag */
2064 case 4: /* Hit Invalidate */
2066 case 6: /* Hit Writeback */
2067 if (!icache_warning
)
2069 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2075 SignalException(ReservedInstruction
,instruction
);
2080 case 1: /* data cache */
2082 case 0: /* Index Writeback Invalidate */
2083 case 1: /* Index Load Tag */
2084 case 2: /* Index Store Tag */
2085 case 3: /* Create Dirty */
2086 case 4: /* Hit Invalidate */
2087 case 5: /* Hit Writeback Invalidate */
2088 case 6: /* Hit Writeback */
2089 if (!dcache_warning
)
2091 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2097 SignalException(ReservedInstruction
,instruction
);
2102 default: /* unrecognised cache ID */
2103 SignalException(ReservedInstruction
,instruction
);
2110 /*-- FPU support routines ---------------------------------------------------*/
2112 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2113 formats conform to ANSI/IEEE Std 754-1985. */
2114 /* SINGLE precision floating:
2115 * seeeeeeeefffffffffffffffffffffff
2117 * e = 8bits = exponent
2118 * f = 23bits = fraction
2120 /* SINGLE precision fixed:
2121 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2123 * i = 31bits = integer
2125 /* DOUBLE precision floating:
2126 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2128 * e = 11bits = exponent
2129 * f = 52bits = fraction
2131 /* DOUBLE precision fixed:
2132 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2134 * i = 63bits = integer
2137 /* Extract sign-bit: */
2138 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2139 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2140 /* Extract biased exponent: */
2141 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2142 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2143 /* Extract unbiased Exponent: */
2144 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2145 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2146 /* Extract complete fraction field: */
2147 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2148 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2149 /* Extract numbered fraction bit: */
2150 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2151 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2153 /* Explicit QNaN values used when value required: */
2154 #define FPQNaN_SINGLE (0x7FBFFFFF)
2155 #define FPQNaN_WORD (0x7FFFFFFF)
2156 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2157 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2159 /* Explicit Infinity values used when required: */
2160 #define FPINF_SINGLE (0x7F800000)
2161 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2163 #if 1 /* def DEBUG */
2164 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2165 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2169 value_fpr (SIM_DESC sd
,
2178 /* Treat unused register values, as fixed-point 64bit values: */
2179 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2181 /* If request to read data as "uninterpreted", then use the current
2183 fmt
= FPR_STATE
[fpr
];
2188 /* For values not yet accessed, set to the desired format: */
2189 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2190 FPR_STATE
[fpr
] = fmt
;
2192 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2195 if (fmt
!= FPR_STATE
[fpr
]) {
2196 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2197 FPR_STATE
[fpr
] = fmt_unknown
;
2200 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2201 /* Set QNaN value: */
2204 value
= FPQNaN_SINGLE
;
2208 value
= FPQNaN_DOUBLE
;
2212 value
= FPQNaN_WORD
;
2216 value
= FPQNaN_LONG
;
2223 } else if (SizeFGR() == 64) {
2227 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2230 case fmt_uninterpreted
:
2244 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2247 case fmt_uninterpreted
:
2250 if ((fpr
& 1) == 0) { /* even registers only */
2251 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2253 SignalException(ReservedInstruction
,0);
2264 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2267 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2274 store_fpr (SIM_DESC sd
,
2284 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2287 if (SizeFGR() == 64) {
2289 case fmt_uninterpreted_32
:
2290 fmt
= fmt_uninterpreted
;
2293 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2294 FPR_STATE
[fpr
] = fmt
;
2297 case fmt_uninterpreted_64
:
2298 fmt
= fmt_uninterpreted
;
2299 case fmt_uninterpreted
:
2303 FPR_STATE
[fpr
] = fmt
;
2307 FPR_STATE
[fpr
] = fmt_unknown
;
2313 case fmt_uninterpreted_32
:
2314 fmt
= fmt_uninterpreted
;
2317 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2318 FPR_STATE
[fpr
] = fmt
;
2321 case fmt_uninterpreted_64
:
2322 fmt
= fmt_uninterpreted
;
2323 case fmt_uninterpreted
:
2326 if ((fpr
& 1) == 0) { /* even register number only */
2327 FGR
[fpr
+1] = (value
>> 32);
2328 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2329 FPR_STATE
[fpr
+ 1] = fmt
;
2330 FPR_STATE
[fpr
] = fmt
;
2332 FPR_STATE
[fpr
] = fmt_unknown
;
2333 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2334 SignalException(ReservedInstruction
,0);
2339 FPR_STATE
[fpr
] = fmt_unknown
;
2344 #if defined(WARN_RESULT)
2347 #endif /* WARN_RESULT */
2350 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2353 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2370 sim_fpu_32to (&wop
, op
);
2371 boolean
= sim_fpu_is_nan (&wop
);
2378 sim_fpu_64to (&wop
, op
);
2379 boolean
= sim_fpu_is_nan (&wop
);
2383 fprintf (stderr
, "Bad switch\n");
2388 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2402 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2409 sim_fpu_32to (&wop
, op
);
2410 boolean
= sim_fpu_is_infinity (&wop
);
2416 sim_fpu_64to (&wop
, op
);
2417 boolean
= sim_fpu_is_infinity (&wop
);
2421 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2426 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2440 /* Argument checking already performed by the FPCOMPARE code */
2443 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2446 /* The format type should already have been checked: */
2452 sim_fpu_32to (&wop1
, op1
);
2453 sim_fpu_32to (&wop2
, op2
);
2454 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2461 sim_fpu_64to (&wop1
, op1
);
2462 sim_fpu_64to (&wop2
, op2
);
2463 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2467 fprintf (stderr
, "Bad switch\n");
2472 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2486 /* Argument checking already performed by the FPCOMPARE code */
2489 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2492 /* The format type should already have been checked: */
2498 sim_fpu_32to (&wop1
, op1
);
2499 sim_fpu_32to (&wop2
, op2
);
2500 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2507 sim_fpu_64to (&wop1
, op1
);
2508 sim_fpu_64to (&wop2
, op2
);
2509 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2513 fprintf (stderr
, "Bad switch\n");
2518 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2525 AbsoluteValue(op
,fmt
)
2532 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2535 /* The format type should already have been checked: */
2541 sim_fpu_32to (&wop
, op
);
2542 sim_fpu_abs (&wop
, &wop
);
2543 sim_fpu_to32 (&ans
, &wop
);
2551 sim_fpu_64to (&wop
, op
);
2552 sim_fpu_abs (&wop
, &wop
);
2553 sim_fpu_to64 (&ans
, &wop
);
2558 fprintf (stderr
, "Bad switch\n");
2573 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2576 /* The format type should already have been checked: */
2582 sim_fpu_32to (&wop
, op
);
2583 sim_fpu_neg (&wop
, &wop
);
2584 sim_fpu_to32 (&ans
, &wop
);
2592 sim_fpu_64to (&wop
, op
);
2593 sim_fpu_neg (&wop
, &wop
);
2594 sim_fpu_to64 (&ans
, &wop
);
2599 fprintf (stderr
, "Bad switch\n");
2615 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2618 /* The registers must specify FPRs valid for operands of type
2619 "fmt". If they are not valid, the result is undefined. */
2621 /* The format type should already have been checked: */
2629 sim_fpu_32to (&wop1
, op1
);
2630 sim_fpu_32to (&wop2
, op2
);
2631 sim_fpu_add (&ans
, &wop1
, &wop2
);
2632 sim_fpu_to32 (&res
, &ans
);
2642 sim_fpu_64to (&wop1
, op1
);
2643 sim_fpu_64to (&wop2
, op2
);
2644 sim_fpu_add (&ans
, &wop1
, &wop2
);
2645 sim_fpu_to64 (&res
, &ans
);
2650 fprintf (stderr
, "Bad switch\n");
2655 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2670 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2673 /* The registers must specify FPRs valid for operands of type
2674 "fmt". If they are not valid, the result is undefined. */
2676 /* The format type should already have been checked: */
2684 sim_fpu_32to (&wop1
, op1
);
2685 sim_fpu_32to (&wop2
, op2
);
2686 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2687 sim_fpu_to32 (&res
, &ans
);
2697 sim_fpu_64to (&wop1
, op1
);
2698 sim_fpu_64to (&wop2
, op2
);
2699 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2700 sim_fpu_to64 (&res
, &ans
);
2705 fprintf (stderr
, "Bad switch\n");
2710 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2717 Multiply(op1
,op2
,fmt
)
2725 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2728 /* The registers must specify FPRs valid for operands of type
2729 "fmt". If they are not valid, the result is undefined. */
2731 /* The format type should already have been checked: */
2739 sim_fpu_32to (&wop1
, op1
);
2740 sim_fpu_32to (&wop2
, op2
);
2741 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2742 sim_fpu_to32 (&res
, &ans
);
2752 sim_fpu_64to (&wop1
, op1
);
2753 sim_fpu_64to (&wop2
, op2
);
2754 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2755 sim_fpu_to64 (&res
, &ans
);
2760 fprintf (stderr
, "Bad switch\n");
2765 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2780 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2783 /* The registers must specify FPRs valid for operands of type
2784 "fmt". If they are not valid, the result is undefined. */
2786 /* The format type should already have been checked: */
2794 sim_fpu_32to (&wop1
, op1
);
2795 sim_fpu_32to (&wop2
, op2
);
2796 sim_fpu_div (&ans
, &wop1
, &wop2
);
2797 sim_fpu_to32 (&res
, &ans
);
2807 sim_fpu_64to (&wop1
, op1
);
2808 sim_fpu_64to (&wop2
, op2
);
2809 sim_fpu_div (&ans
, &wop1
, &wop2
);
2810 sim_fpu_to64 (&res
, &ans
);
2815 fprintf (stderr
, "Bad switch\n");
2820 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2834 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2837 /* The registers must specify FPRs valid for operands of type
2838 "fmt". If they are not valid, the result is undefined. */
2840 /* The format type should already have been checked: */
2847 sim_fpu_32to (&wop
, op
);
2848 sim_fpu_inv (&ans
, &wop
);
2849 sim_fpu_to32 (&res
, &ans
);
2858 sim_fpu_64to (&wop
, op
);
2859 sim_fpu_inv (&ans
, &wop
);
2860 sim_fpu_to64 (&res
, &ans
);
2865 fprintf (stderr
, "Bad switch\n");
2870 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2884 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2887 /* The registers must specify FPRs valid for operands of type
2888 "fmt". If they are not valid, the result is undefined. */
2890 /* The format type should already have been checked: */
2897 sim_fpu_32to (&wop
, op
);
2898 sim_fpu_sqrt (&ans
, &wop
);
2899 sim_fpu_to32 (&res
, &ans
);
2908 sim_fpu_64to (&wop
, op
);
2909 sim_fpu_sqrt (&ans
, &wop
);
2910 sim_fpu_to64 (&res
, &ans
);
2915 fprintf (stderr
, "Bad switch\n");
2920 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2935 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2938 /* The registers must specify FPRs valid for operands of type
2939 "fmt". If they are not valid, the result is undefined. */
2941 /* The format type should already have been checked: */
2948 sim_fpu_32to (&wop1
, op1
);
2949 sim_fpu_32to (&wop2
, op2
);
2950 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2957 sim_fpu_64to (&wop1
, op1
);
2958 sim_fpu_64to (&wop2
, op2
);
2959 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2963 fprintf (stderr
, "Bad switch\n");
2969 case SIM_FPU_IS_SNAN
:
2970 case SIM_FPU_IS_QNAN
:
2972 case SIM_FPU_IS_NINF
:
2973 case SIM_FPU_IS_NNUMBER
:
2974 case SIM_FPU_IS_NDENORM
:
2975 case SIM_FPU_IS_NZERO
:
2976 result
= op2
; /* op1 - op2 < 0 */
2977 case SIM_FPU_IS_PINF
:
2978 case SIM_FPU_IS_PNUMBER
:
2979 case SIM_FPU_IS_PDENORM
:
2980 case SIM_FPU_IS_PZERO
:
2981 result
= op1
; /* op1 - op2 > 0 */
2983 fprintf (stderr
, "Bad switch\n");
2988 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3003 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3006 /* The registers must specify FPRs valid for operands of type
3007 "fmt". If they are not valid, the result is undefined. */
3009 /* The format type should already have been checked: */
3016 sim_fpu_32to (&wop1
, op1
);
3017 sim_fpu_32to (&wop2
, op2
);
3018 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3025 sim_fpu_64to (&wop1
, op1
);
3026 sim_fpu_64to (&wop2
, op2
);
3027 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3031 fprintf (stderr
, "Bad switch\n");
3037 case SIM_FPU_IS_SNAN
:
3038 case SIM_FPU_IS_QNAN
:
3040 case SIM_FPU_IS_NINF
:
3041 case SIM_FPU_IS_NNUMBER
:
3042 case SIM_FPU_IS_NDENORM
:
3043 case SIM_FPU_IS_NZERO
:
3044 result
= op1
; /* op1 - op2 < 0 */
3045 case SIM_FPU_IS_PINF
:
3046 case SIM_FPU_IS_PNUMBER
:
3047 case SIM_FPU_IS_PDENORM
:
3048 case SIM_FPU_IS_PZERO
:
3049 result
= op2
; /* op1 - op2 > 0 */
3051 fprintf (stderr
, "Bad switch\n");
3056 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3063 convert (SIM_DESC sd
,
3072 sim_fpu_round round
;
3073 unsigned32 result32
;
3074 unsigned64 result64
;
3077 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3083 /* Round result to nearest representable value. When two
3084 representable values are equally near, round to the value
3085 that has a least significant bit of zero (i.e. is even). */
3086 round
= sim_fpu_round_near
;
3089 /* Round result to the value closest to, and not greater in
3090 magnitude than, the result. */
3091 round
= sim_fpu_round_zero
;
3094 /* Round result to the value closest to, and not less than,
3096 round
= sim_fpu_round_up
;
3100 /* Round result to the value closest to, and not greater than,
3102 round
= sim_fpu_round_down
;
3106 fprintf (stderr
, "Bad switch\n");
3110 /* Convert the input to sim_fpu internal format */
3114 sim_fpu_64to (&wop
, op
);
3117 sim_fpu_32to (&wop
, op
);
3120 sim_fpu_i32to (&wop
, op
, round
);
3123 sim_fpu_i64to (&wop
, op
, round
);
3126 fprintf (stderr
, "Bad switch\n");
3130 /* Convert sim_fpu format into the output */
3131 /* The value WOP is converted to the destination format, rounding
3132 using mode RM. When the destination is a fixed-point format, then
3133 a source value of Infinity, NaN or one which would round to an
3134 integer outside the fixed point range then an IEEE Invalid
3135 Operation condition is raised. */
3139 sim_fpu_round_32 (&wop
, round
, 0);
3140 sim_fpu_to32 (&result32
, &wop
);
3141 result64
= result32
;
3144 sim_fpu_round_64 (&wop
, round
, 0);
3145 sim_fpu_to64 (&result64
, &wop
);
3148 sim_fpu_to32i (&result32
, &wop
, round
);
3149 result64
= result32
;
3152 sim_fpu_to64i (&result64
, &wop
, round
);
3156 fprintf (stderr
, "Bad switch\n");
3161 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
3168 /*-- co-processor support routines ------------------------------------------*/
3171 CoProcPresent(coproc_number
)
3172 unsigned int coproc_number
;
3174 /* Return TRUE if simulator provides a model for the given co-processor number */
3179 cop_lw (SIM_DESC sd
,
3184 unsigned int memword
)
3189 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3192 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3194 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3195 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3200 #if 0 /* this should be controlled by a configuration option */
3201 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3210 cop_ld (SIM_DESC sd
,
3217 switch (coproc_num
) {
3219 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3221 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3226 #if 0 /* this message should be controlled by a configuration option */
3227 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3236 cop_sw (SIM_DESC sd
,
3242 unsigned int value
= 0;
3247 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3250 hold
= FPR_STATE
[coproc_reg
];
3251 FPR_STATE
[coproc_reg
] = fmt_word
;
3252 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3253 FPR_STATE
[coproc_reg
] = hold
;
3258 #if 0 /* should be controlled by configuration option */
3259 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3268 cop_sd (SIM_DESC sd
,
3278 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3280 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3285 #if 0 /* should be controlled by configuration option */
3286 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3295 decode_coproc (SIM_DESC sd
,
3298 unsigned int instruction
)
3300 int coprocnum
= ((instruction
>> 26) & 3);
3304 case 0: /* standard CPU control and cache registers */
3306 int code
= ((instruction
>> 21) & 0x1F);
3307 /* R4000 Users Manual (second edition) lists the following CP0
3309 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3310 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3311 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3312 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3313 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3314 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3315 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3316 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3317 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3318 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3320 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3322 int rt
= ((instruction
>> 16) & 0x1F);
3323 int rd
= ((instruction
>> 11) & 0x1F);
3325 switch (rd
) /* NOTEs: Standard CP0 registers */
3327 /* 0 = Index R4000 VR4100 VR4300 */
3328 /* 1 = Random R4000 VR4100 VR4300 */
3329 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3330 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3331 /* 4 = Context R4000 VR4100 VR4300 */
3332 /* 5 = PageMask R4000 VR4100 VR4300 */
3333 /* 6 = Wired R4000 VR4100 VR4300 */
3334 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3335 /* 9 = Count R4000 VR4100 VR4300 */
3336 /* 10 = EntryHi R4000 VR4100 VR4300 */
3337 /* 11 = Compare R4000 VR4100 VR4300 */
3338 /* 12 = SR R4000 VR4100 VR4300 */
3345 /* 13 = Cause R4000 VR4100 VR4300 */
3352 /* 14 = EPC R4000 VR4100 VR4300 */
3353 /* 15 = PRId R4000 VR4100 VR4300 */
3354 #ifdef SUBTARGET_R3900
3363 /* 16 = Config R4000 VR4100 VR4300 */
3366 GPR
[rt
] = C0_CONFIG
;
3368 C0_CONFIG
= GPR
[rt
];
3371 #ifdef SUBTARGET_R3900
3380 /* 17 = LLAddr R4000 VR4100 VR4300 */
3382 /* 18 = WatchLo R4000 VR4100 VR4300 */
3383 /* 19 = WatchHi R4000 VR4100 VR4300 */
3384 /* 20 = XContext R4000 VR4100 VR4300 */
3385 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3386 /* 27 = CacheErr R4000 VR4100 */
3387 /* 28 = TagLo R4000 VR4100 VR4300 */
3388 /* 29 = TagHi R4000 VR4100 VR4300 */
3389 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3390 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3391 /* CPR[0,rd] = GPR[rt]; */
3394 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3396 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3399 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3402 if (SR
& status_ERL
)
3404 /* Oops, not yet available */
3405 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3415 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3419 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3427 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3428 /* TODO: When executing an ERET or RFE instruction we should
3429 clear LLBIT, to ensure that any out-standing atomic
3430 read/modify/write sequence fails. */
3434 case 2: /* undefined co-processor */
3435 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3438 case 1: /* should not occur (FPU co-processor) */
3439 case 3: /* should not occur (FPU co-processor) */
3440 SignalException(ReservedInstruction
,instruction
);
3447 /*-- instruction simulation -------------------------------------------------*/
3449 /* When the IGEN simulator is being built, the function below is be
3450 replaced by a generated version. However, WITH_IGEN == 2 indicates
3451 that the fubction below should be compiled but under a different
3452 name (to allow backward compatibility) */
3454 #if (WITH_IGEN != 1)
3456 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3458 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3461 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3464 int next_cpu_nr
; /* ignore */
3465 int nr_cpus
; /* ignore */
3466 int siggnal
; /* ignore */
3468 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3469 #if !defined(FASTSIM)
3470 unsigned int pipeline_count
= 1;
3474 if (STATE_MEMORY (sd
) == NULL
) {
3475 printf("DBG: simulate() entered with no memory\n");
3480 #if 0 /* Disabled to check that everything works OK */
3481 /* The VR4300 seems to sign-extend the PC on its first
3482 access. However, this may just be because it is currently
3483 configured in 32bit mode. However... */
3484 PC
= SIGNEXTEND(PC
,32);
3487 /* main controlling loop */
3489 /* vaddr is slowly being replaced with cia - current instruction
3491 address_word cia
= (uword64
)PC
;
3492 address_word vaddr
= cia
;
3495 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3499 printf("DBG: state = 0x%08X :",state
);
3500 if (state
& simHALTEX
) printf(" simHALTEX");
3501 if (state
& simHALTIN
) printf(" simHALTIN");
3506 DSSTATE
= (STATE
& simDELAYSLOT
);
3509 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3512 /* Fetch the next instruction from the simulator memory: */
3513 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3514 if ((vaddr
& 1) == 0) {
3515 /* Copy the action of the LW instruction */
3516 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3517 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3520 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3521 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3522 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3523 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3525 /* Copy the action of the LH instruction */
3526 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3527 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3530 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3531 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3532 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3533 paddr
& ~ (uword64
) 1,
3534 vaddr
, isINSTRUCTION
, isREAL
);
3535 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3536 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3539 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3544 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3547 /* This is required by exception processing, to ensure that we can
3548 cope with exceptions in the delay slots of branches that may
3549 already have changed the PC. */
3550 if ((vaddr
& 1) == 0)
3551 PC
+= 4; /* increment ready for the next fetch */
3554 /* NOTE: If we perform a delay slot change to the PC, this
3555 increment is not requuired. However, it would make the
3556 simulator more complicated to try and avoid this small hit. */
3558 /* Currently this code provides a simple model. For more
3559 complicated models we could perform exception status checks at
3560 this point, and set the simSTOP state as required. This could
3561 also include processing any hardware interrupts raised by any
3562 I/O model attached to the simulator context.
3564 Support for "asynchronous" I/O events within the simulated world
3565 could be providing by managing a counter, and calling a I/O
3566 specific handler when a particular threshold is reached. On most
3567 architectures a decrement and check for zero operation is
3568 usually quicker than an increment and compare. However, the
3569 process of managing a known value decrement to zero, is higher
3570 than the cost of using an explicit value UINT_MAX into the
3571 future. Which system is used will depend on how complicated the
3572 I/O model is, and how much it is likely to affect the simulator
3575 If events need to be scheduled further in the future than
3576 UINT_MAX event ticks, then the I/O model should just provide its
3577 own counter, triggered from the event system. */
3579 /* MIPS pipeline ticks. To allow for future support where the
3580 pipeline hit of individual instructions is known, this control
3581 loop manages a "pipeline_count" variable. It is initialised to
3582 1 (one), and will only be changed by the simulator engine when
3583 executing an instruction. If the engine does not have access to
3584 pipeline cycle count information then all instructions will be
3585 treated as using a single cycle. NOTE: A standard system is not
3586 provided by the default simulator because different MIPS
3587 architectures have different cycle counts for the same
3590 [NOTE: pipeline_count has been replaced the event queue] */
3592 /* shuffle the floating point status pipeline state */
3593 ENGINE_ISSUE_PREFIX_HOOK();
3595 /* NOTE: For multi-context simulation environments the "instruction"
3596 variable should be local to this routine. */
3598 /* Shorthand accesses for engine. Note: If we wanted to use global
3599 variables (and a single-threaded simulator engine), then we can
3600 create the actual variables with these names. */
3602 if (!(STATE
& simSKIPNEXT
)) {
3603 /* Include the simulator engine */
3604 #include "oengine.c"
3605 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3606 #error "Mismatch between run-time simulator code and simulation engine"
3608 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3609 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3611 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3612 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3615 #if defined(WARN_LOHI)
3616 /* Decrement the HI/LO validity ticks */
3621 /* start-sanitize-r5900 */
3626 /* end-sanitize-r5900 */
3627 #endif /* WARN_LOHI */
3629 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3630 should check for it being changed. It is better doing it here,
3631 than within the simulator, since it will help keep the simulator
3634 #if defined(WARN_ZERO)
3635 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3636 #endif /* WARN_ZERO */
3637 ZERO
= 0; /* reset back to zero before next instruction */
3639 } else /* simSKIPNEXT check */
3640 STATE
&= ~simSKIPNEXT
;
3642 /* If the delay slot was active before the instruction is
3643 executed, then update the PC to its new value: */
3646 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3655 #if !defined(FASTSIM)
3656 if (sim_events_tickn (sd
, pipeline_count
))
3658 /* cpu->cia = cia; */
3659 sim_events_process (sd
);
3662 if (sim_events_tick (sd
))
3664 /* cpu->cia = cia; */
3665 sim_events_process (sd
);
3667 #endif /* FASTSIM */
3673 /* This code copied from gdb's utils.c. Would like to share this code,
3674 but don't know of a common place where both could get to it. */
3676 /* Temporary storage using circular buffer */
3682 static char buf
[NUMCELLS
][CELLSIZE
];
3684 if (++cell
>=NUMCELLS
) cell
=0;
3688 /* Print routines to handle variable size regs, etc */
3690 /* Eliminate warning from compiler on 32-bit systems */
3691 static int thirty_two
= 32;
3697 char *paddr_str
=get_cell();
3698 switch (sizeof(addr
))
3701 sprintf(paddr_str
,"%08lx%08lx",
3702 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3705 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3708 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3711 sprintf(paddr_str
,"%x",addr
);
3720 char *paddr_str
=get_cell();
3721 sprintf(paddr_str
,"%08lx%08lx",
3722 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3728 pending_tick (SIM_DESC sd
,
3733 sim_io_printf (sd
, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN
, PENDING_OUT
, PENDING_TOTAL
);
3734 if (PENDING_OUT
!= PENDING_IN
)
3737 int index
= PENDING_OUT
;
3738 int total
= PENDING_TOTAL
;
3739 if (PENDING_TOTAL
== 0)
3740 sim_engine_abort (SD
, CPU
, cia
, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3741 for (loop
= 0; (loop
< total
); loop
++)
3743 if (PENDING_SLOT_DEST
[index
] != NULL
)
3745 PENDING_SLOT_DELAY
[index
] -= 1;
3746 if (PENDING_SLOT_DELAY
[index
] == 0)
3748 if (PENDING_SLOT_BIT
[index
] >= 0)
3749 switch (PENDING_SLOT_SIZE
[index
])
3752 if (PENDING_SLOT_VALUE
[index
])
3753 *(unsigned32
*)PENDING_SLOT_DEST
[index
] |=
3754 BIT32 (PENDING_SLOT_BIT
[index
]);
3756 *(unsigned32
*)PENDING_SLOT_DEST
[index
] &=
3757 BIT32 (PENDING_SLOT_BIT
[index
]);
3760 if (PENDING_SLOT_VALUE
[index
])
3761 *(unsigned64
*)PENDING_SLOT_DEST
[index
] |=
3762 BIT64 (PENDING_SLOT_BIT
[index
]);
3764 *(unsigned64
*)PENDING_SLOT_DEST
[index
] &=
3765 BIT64 (PENDING_SLOT_BIT
[index
]);
3770 switch (PENDING_SLOT_SIZE
[index
])
3773 *(unsigned32
*)PENDING_SLOT_DEST
[index
] =
3774 PENDING_SLOT_VALUE
[index
];
3777 *(unsigned64
*)PENDING_SLOT_DEST
[index
] =
3778 PENDING_SLOT_VALUE
[index
];
3782 if (PENDING_OUT
== index
)
3784 PENDING_SLOT_DEST
[index
] = NULL
;
3785 PENDING_OUT
= (PENDING_OUT
+ 1) % PSLOTS
;
3790 index
= (index
+ 1) % PSLOTS
;
3794 /*---------------------------------------------------------------------------*/
3795 /*> EOF interp.c <*/