2 /* Simulator for the MIPS architecture.
4 This file is part of the MIPS sim
6 THIS SOFTWARE IS NOT COPYRIGHTED
8 Cygnus offers the following for use in the public domain. Cygnus
9 makes no warranty with regard to the software or it's performance
10 and the user accepts the software "AS IS" with all faults.
12 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
13 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
14 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
22 The IDT monitor (found on the VR4300 board), seems to lie about
23 register contents. It seems to treat the registers as sign-extended
24 32-bit values. This cause *REAL* problems when single-stepping 64-bit
29 /* The TRACE manifests enable the provision of extra features. If they
30 are not defined then a simpler (quicker) simulator is constructed
31 without the required run-time checks, etc. */
32 #if 1 /* 0 to allow user build selection, 1 to force inclusion */
38 #include "sim-utils.h"
39 #include "sim-options.h"
40 #include "sim-assert.h"
62 #include "libiberty.h"
64 #include "callback.h" /* GDB simulator callback interface */
65 #include "remote-sim.h" /* GDB simulator interface */
69 /* start-sanitize-sky */
73 /* end-sanitize-sky */
79 char* pr_addr
PARAMS ((SIM_ADDR addr
));
80 char* pr_uword64
PARAMS ((uword64 addr
));
83 /* Get the simulator engine description, without including the code: */
85 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3)
92 /* Within interp.c we refer to the sim_state and sim_cpu directly. */
97 /* The following reserved instruction value is used when a simulator
98 trap is required. NOTE: Care must be taken, since this value may be
99 used in later revisions of the MIPS ISA. */
100 #define RSVD_INSTRUCTION (0x00000005)
101 #define RSVD_INSTRUCTION_MASK (0xFC00003F)
103 #define RSVD_INSTRUCTION_ARG_SHIFT 6
104 #define RSVD_INSTRUCTION_ARG_MASK 0xFFFFF
107 /* Bits in the Debug register */
108 #define Debug_DBD 0x80000000 /* Debug Branch Delay */
109 #define Debug_DM 0x40000000 /* Debug Mode */
110 #define Debug_DBp 0x00000002 /* Debug Breakpoint indicator */
116 /*---------------------------------------------------------------------------*/
117 /*-- GDB simulator interface ------------------------------------------------*/
118 /*---------------------------------------------------------------------------*/
120 static void ColdReset
PARAMS((SIM_DESC sd
));
122 /*---------------------------------------------------------------------------*/
126 #define DELAYSLOT() {\
127 if (STATE & simDELAYSLOT)\
128 sim_io_eprintf(sd,"Delay slot already activated (branch in delay slot?)\n");\
129 STATE |= simDELAYSLOT;\
132 #define JALDELAYSLOT() {\
134 STATE |= simJALDELAYSLOT;\
138 STATE &= ~simDELAYSLOT;\
139 STATE |= simSKIPNEXT;\
142 #define CANCELDELAYSLOT() {\
144 STATE &= ~(simDELAYSLOT | simJALDELAYSLOT);\
147 #define INDELAYSLOT() ((STATE & simDELAYSLOT) != 0)
148 #define INJALDELAYSLOT() ((STATE & simJALDELAYSLOT) != 0)
150 #define K0BASE (0x80000000)
151 #define K0SIZE (0x20000000)
152 #define K1BASE (0xA0000000)
153 #define K1SIZE (0x20000000)
154 #define MONITOR_BASE (0xBFC00000)
155 #define MONITOR_SIZE (1 << 11)
156 #define MEM_SIZE (2 << 20)
157 /* start-sanitize-sky */
160 #define MEM_SIZE (16 << 20) /* 16 MB */
162 /* end-sanitize-sky */
165 static char *tracefile
= "trace.din"; /* default filename for trace log */
166 FILE *tracefh
= NULL
;
167 static void open_trace
PARAMS((SIM_DESC sd
));
170 static DECLARE_OPTION_HANDLER (mips_option_handler
);
172 #define OPTION_DINERO_TRACE 200
173 #define OPTION_DINERO_FILE 201
176 mips_option_handler (sd
, cpu
, opt
, arg
, is_command
)
186 case OPTION_DINERO_TRACE
: /* ??? */
188 /* Eventually the simTRACE flag could be treated as a toggle, to
189 allow external control of the program points being traced
190 (i.e. only from main onwards, excluding the run-time setup,
192 for (cpu_nr
= 0; cpu_nr
< MAX_NR_PROCESSORS
; cpu_nr
++)
194 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
197 else if (strcmp (arg
, "yes") == 0)
199 else if (strcmp (arg
, "no") == 0)
201 else if (strcmp (arg
, "on") == 0)
203 else if (strcmp (arg
, "off") == 0)
207 fprintf (stderr
, "Unreconized dinero-trace option `%s'\n", arg
);
214 Simulator constructed without dinero tracing support (for performance).\n\
215 Re-compile simulator with \"-DTRACE\" to enable this option.\n");
219 case OPTION_DINERO_FILE
:
221 if (optarg
!= NULL
) {
223 tmp
= (char *)malloc(strlen(optarg
) + 1);
226 sim_io_printf(sd
,"Failed to allocate buffer for tracefile name \"%s\"\n",optarg
);
232 sim_io_printf(sd
,"Placing trace information into file \"%s\"\n",tracefile
);
243 static const OPTION mips_options
[] =
245 { {"dinero-trace", optional_argument
, NULL
, OPTION_DINERO_TRACE
},
246 '\0', "on|off", "Enable dinero tracing",
247 mips_option_handler
},
248 { {"dinero-file", required_argument
, NULL
, OPTION_DINERO_FILE
},
249 '\0', "FILE", "Write dinero trace to FILE",
250 mips_option_handler
},
251 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
255 int interrupt_pending
;
258 interrupt_event (SIM_DESC sd
, void *data
)
260 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
263 interrupt_pending
= 0;
264 SignalExceptionInterrupt ();
266 else if (!interrupt_pending
)
267 sim_events_schedule (sd
, 1, interrupt_event
, data
);
271 /*---------------------------------------------------------------------------*/
272 /*-- Device registration hook -----------------------------------------------*/
273 /*---------------------------------------------------------------------------*/
274 static void device_init(SIM_DESC sd
) {
276 extern void register_devices(SIM_DESC
);
277 register_devices(sd
);
281 /* start-sanitize-sky */
284 short i
[NUM_VU_INTEGER_REGS
];
285 int f
[NUM_VU_REGS
- NUM_VU_INTEGER_REGS
];
288 /* end-sanitize-sky */
290 /*---------------------------------------------------------------------------*/
291 /*-- GDB simulator interface ------------------------------------------------*/
292 /*---------------------------------------------------------------------------*/
295 sim_open (kind
, cb
, abfd
, argv
)
301 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
302 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
304 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
306 /* FIXME: watchpoints code shouldn't need this */
307 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
308 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
309 STATE_WATCHPOINTS (sd
)->interrupt_handler
= interrupt_event
;
313 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
315 sim_add_option_table (sd
, NULL
, mips_options
);
317 /* Allocate core managed memory */
320 sim_do_commandf (sd
, "memory region 0x%lx,0x%lx", MONITOR_BASE
, MONITOR_SIZE
);
321 /* For compatibility with the old code - under this (at level one)
322 are the kernel spaces K0 & K1. Both of these map to a single
323 smaller sub region */
324 sim_do_command(sd
," memory region 0x7fff8000,0x8000") ; /* MTZ- 32 k stack */
325 /* start-sanitize-sky */
327 /* end-sanitize-sky */
328 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x",
330 MEM_SIZE
, /* actual size */
332 /* start-sanitize-sky */
334 sim_do_commandf (sd
, "memory alias 0x%lx@1,0x%lx%%0x%lx,0x%0x,0x%0x",
336 MEM_SIZE
, /* actual size */
338 0); /* add alias at 0x0000 */
340 /* end-sanitize-sky */
344 /* getopt will print the error message so we just have to exit if this fails.
345 FIXME: Hmmm... in the case of gdb we need getopt to call
347 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
349 /* Uninstall the modules to avoid memory leaks,
350 file descriptor leaks, etc. */
351 sim_module_uninstall (sd
);
355 /* check for/establish the a reference program image */
356 if (sim_analyze_program (sd
,
357 (STATE_PROG_ARGV (sd
) != NULL
358 ? *STATE_PROG_ARGV (sd
)
362 sim_module_uninstall (sd
);
366 /* Configure/verify the target byte order and other runtime
367 configuration options */
368 if (sim_config (sd
) != SIM_RC_OK
)
370 sim_module_uninstall (sd
);
374 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
376 /* Uninstall the modules to avoid memory leaks,
377 file descriptor leaks, etc. */
378 sim_module_uninstall (sd
);
382 /* verify assumptions the simulator made about the host type system.
383 This macro does not return if there is a problem */
384 SIM_ASSERT (sizeof(int) == (4 * sizeof(char)));
385 SIM_ASSERT (sizeof(word64
) == (8 * sizeof(char)));
387 /* This is NASTY, in that we are assuming the size of specific
391 for (rn
= 0; (rn
< (LAST_EMBED_REGNUM
+ 1)); rn
++)
394 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
395 else if ((rn
>= FGRIDX
) && (rn
< (FGRIDX
+ NR_FGR
)))
396 cpu
->register_widths
[rn
] = WITH_TARGET_FLOATING_POINT_BITSIZE
;
397 else if ((rn
>= 33) && (rn
<= 37))
398 cpu
->register_widths
[rn
] = WITH_TARGET_WORD_BITSIZE
;
399 else if ((rn
== SRIDX
)
402 || ((rn
>= 72) && (rn
<= 89)))
403 cpu
->register_widths
[rn
] = 32;
405 cpu
->register_widths
[rn
] = 0;
407 /* start-sanitize-r5900 */
409 /* set the 5900 "upper" registers to 64 bits */
410 for( rn
= LAST_EMBED_REGNUM
+1; rn
< NUM_REGS
; rn
++)
411 cpu
->register_widths
[rn
] = 64;
412 /* end-sanitize-r5900 */
414 /* start-sanitize-sky */
416 /* Now the VU registers */
417 for( rn
= 0; rn
< NUM_VU_INTEGER_REGS
; rn
++ ) {
418 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 16;
419 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 16;
421 /* Hack for now - to test gdb interface */
422 vu_regs
[0].i
[rn
] = rn
+ 0x100;
423 vu_regs
[1].i
[rn
] = rn
+ 0x200;
426 for( rn
= NUM_VU_INTEGER_REGS
; rn
< NUM_VU_REGS
; rn
++ ) {
428 int first_vec_reg
= NUM_VU_INTEGER_REGS
+ 8;
430 cpu
->register_widths
[rn
+ NUM_R5900_REGS
] = 32;
431 cpu
->register_widths
[rn
+ NUM_R5900_REGS
+ NUM_VU_REGS
] = 32;
433 /* Hack for now - to test gdb interface */
434 if( rn
< first_vec_reg
) {
435 f
= rn
- NUM_VU_INTEGER_REGS
+ 100.0;
436 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
437 f
= rn
- NUM_VU_INTEGER_REGS
+ 200.0;
438 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
441 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 1000.0;
442 vu_regs
[0].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
443 f
= (rn
- first_vec_reg
)/4 + (rn
- first_vec_reg
)%4 + 2000.0;
444 vu_regs
[1].f
[rn
-NUM_VU_INTEGER_REGS
] = *((unsigned *) &f
);
448 /* end-sanitize-sky */
452 if (STATE
& simTRACE
)
456 /* Write the monitor trap address handlers into the monitor (eeprom)
457 address space. This can only be done once the target endianness
458 has been determined. */
461 /* Entry into the IDT monitor is via fixed address vectors, and
462 not using machine instructions. To avoid clashing with use of
463 the MIPS TRAP system, we place our own (simulator specific)
464 "undefined" instructions into the relevant vector slots. */
465 for (loop
= 0; (loop
< MONITOR_SIZE
); loop
+= 4)
467 address_word vaddr
= (MONITOR_BASE
+ loop
);
468 unsigned32 insn
= (RSVD_INSTRUCTION
| (((loop
>> 2) & RSVD_INSTRUCTION_ARG_MASK
) << RSVD_INSTRUCTION_ARG_SHIFT
));
470 sim_write (sd
, vaddr
, (char *)&insn
, sizeof (insn
));
472 /* The PMON monitor uses the same address space, but rather than
473 branching into it the address of a routine is loaded. We can
474 cheat for the moment, and direct the PMON routine to IDT style
475 instructions within the monitor space. This relies on the IDT
476 monitor not using the locations from 0xBFC00500 onwards as its
478 for (loop
= 0; (loop
< 24); loop
++)
480 address_word vaddr
= (MONITOR_BASE
+ 0x500 + (loop
* 4));
481 unsigned32 value
= ((0x500 - 8) / 8); /* default UNDEFINED reason code */
497 value
= ((0x500 - 16) / 8); /* not an IDT reason code */
499 case 8: /* cliexit */
502 case 11: /* flush_cache */
506 /* FIXME - should monitor_base be SIM_ADDR?? */
507 value
= ((unsigned int)MONITOR_BASE
+ (value
* 8));
509 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
511 /* The LSI MiniRISC PMON has its vectors at 0x200, not 0x500. */
513 sim_write (sd
, vaddr
, (char *)&value
, sizeof (value
));
525 tracefh
= fopen(tracefile
,"wb+");
528 sim_io_eprintf(sd
,"Failed to create file \"%s\", writing trace information to stderr.\n",tracefile
);
535 sim_close (sd
, quitting
)
540 printf("DBG: sim_close: entered (quitting = %d)\n",quitting
);
543 /* "quitting" is non-zero if we cannot hang on errors */
545 /* Ensure that any resources allocated through the callback
546 mechanism are released: */
547 sim_io_shutdown (sd
);
550 if (tracefh
!= NULL
&& tracefh
!= stderr
)
555 /* FIXME - free SD */
562 sim_write (sd
,addr
,buffer
,size
)
565 unsigned char *buffer
;
569 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
571 /* Return the number of bytes written, or zero if error. */
573 sim_io_printf(sd
,"sim_write(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
576 /* We use raw read and write routines, since we do not want to count
577 the GDB memory accesses in our statistics gathering. */
579 for (index
= 0; index
< size
; index
++)
581 address_word vaddr
= (address_word
)addr
+ index
;
584 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isSTORE
, &paddr
, &cca
, isRAW
))
586 if (sim_core_write_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
594 sim_read (sd
,addr
,buffer
,size
)
597 unsigned char *buffer
;
601 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
603 /* Return the number of bytes read, or zero if error. */
605 sim_io_printf(sd
,"sim_read(0x%s,buffer,%d);\n",pr_addr(addr
),size
);
608 for (index
= 0; (index
< size
); index
++)
610 address_word vaddr
= (address_word
)addr
+ index
;
613 if (!address_translation (SD
, CPU
, NULL_CIA
, vaddr
, isDATA
, isLOAD
, &paddr
, &cca
, isRAW
))
615 if (sim_core_read_buffer (SD
, CPU
, read_map
, buffer
+ index
, paddr
, 1) != 1)
623 sim_store_register (sd
,rn
,memory
,length
)
626 unsigned char *memory
;
629 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
630 /* NOTE: gdb (the client) stores registers in target byte order
631 while the simulator uses host byte order */
633 sim_io_printf(sd
,"sim_store_register(%d,*memory=0x%s);\n",rn
,pr_addr(*((SIM_ADDR
*)memory
)));
636 /* Unfortunately this suffers from the same problem as the register
637 numbering one. We need to know what the width of each logical
638 register number is for the architecture being simulated. */
640 if (cpu
->register_widths
[rn
] == 0)
642 sim_io_eprintf(sd
,"Invalid register width for %d (register store ignored)\n",rn
);
646 /* start-sanitize-r5900 */
647 if (rn
>= 90 && rn
< 90 + 32)
649 GPR1
[rn
- 90] = T2H_8 (*(unsigned64
*)memory
);
655 SA
= T2H_8(*(unsigned64
*)memory
);
657 case 122: /* FIXME */
658 LO1
= T2H_8(*(unsigned64
*)memory
);
660 case 123: /* FIXME */
661 HI1
= T2H_8(*(unsigned64
*)memory
);
664 /* end-sanitize-r5900 */
666 /* start-sanitize-sky */
668 if (rn
>= NUM_R5900_REGS
)
670 int size
= 4; /* Default register size */
672 rn
= rn
- NUM_R5900_REGS
;
674 if (rn
< NUM_VU_INTEGER_REGS
)
675 size
= write_vu_int_reg (&(vu0_state
.regs
), rn
, memory
);
676 else if( rn
< NUM_VU_REGS
)
677 vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
]
678 = T2H_4( *(unsigned int *) memory
);
680 rn
= rn
- NUM_VU_REGS
;
682 if( rn
< NUM_VU_INTEGER_REGS
)
683 size
= write_vu_int_reg (&(vu1_state
.regs
), rn
, memory
);
684 else if( rn
< NUM_VU_REGS
)
685 vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
]
686 = T2H_4( *(unsigned int *) memory
);
688 sim_io_eprintf( sd
, "Invalid VU register (register store ignored)\n" );
694 /* end-sanitize-sky */
696 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
698 if (cpu
->register_widths
[rn
] == 32)
700 cpu
->fgr
[rn
- FGRIDX
] = T2H_4 (*(unsigned32
*)memory
);
705 cpu
->fgr
[rn
- FGRIDX
] = T2H_8 (*(unsigned64
*)memory
);
710 if (cpu
->register_widths
[rn
] == 32)
712 cpu
->registers
[rn
] = T2H_4 (*(unsigned32
*)memory
);
717 cpu
->registers
[rn
] = T2H_8 (*(unsigned64
*)memory
);
723 sim_fetch_register (sd
,rn
,memory
,length
)
726 unsigned char *memory
;
729 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* FIXME */
730 /* NOTE: gdb (the client) stores registers in target byte order
731 while the simulator uses host byte order */
733 sim_io_printf(sd
,"sim_fetch_register(%d=0x%s,mem) : place simulator registers into memory\n",rn
,pr_addr(registers
[rn
]));
736 if (cpu
->register_widths
[rn
] == 0)
738 sim_io_eprintf (sd
, "Invalid register width for %d (register fetch ignored)\n",rn
);
742 /* start-sanitize-r5900 */
743 if (rn
>= 90 && rn
< 90 + 32)
745 *(unsigned64
*)memory
= GPR1
[rn
- 90];
751 *((unsigned64
*)memory
) = H2T_8(SA
);
753 case 122: /* FIXME */
754 *((unsigned64
*)memory
) = H2T_8(LO1
);
756 case 123: /* FIXME */
757 *((unsigned64
*)memory
) = H2T_8(HI1
);
760 /* end-sanitize-r5900 */
762 /* start-sanitize-sky */
764 if (rn
>= NUM_R5900_REGS
)
766 int size
= 4; /* default register width */
768 rn
= rn
- NUM_R5900_REGS
;
770 if (rn
< NUM_VU_INTEGER_REGS
)
771 size
= read_vu_int_reg (&(vu0_state
.regs
), rn
, memory
);
772 else if (rn
< NUM_VU_REGS
)
773 *((unsigned int *) memory
)
774 = H2T_4( vu_regs
[0].f
[rn
- NUM_VU_INTEGER_REGS
] );
777 rn
= rn
- NUM_VU_REGS
;
779 if (rn
< NUM_VU_INTEGER_REGS
)
780 size
= read_vu_int_reg (&(vu1_state
.regs
), rn
, memory
);
781 else if (rn
< NUM_VU_REGS
)
782 (*(unsigned int *) memory
)
783 = H2T_4( vu_regs
[1].f
[rn
- NUM_VU_INTEGER_REGS
] );
785 sim_io_eprintf( sd
, "Invalid VU register (register fetch ignored)\n" );
791 /* end-sanitize-sky */
793 /* Any floating point register */
794 if (rn
>= FGRIDX
&& rn
< FGRIDX
+ NR_FGR
)
796 if (cpu
->register_widths
[rn
] == 32)
798 *(unsigned32
*)memory
= H2T_4 (cpu
->fgr
[rn
- FGRIDX
]);
803 *(unsigned64
*)memory
= H2T_8 (cpu
->fgr
[rn
- FGRIDX
]);
808 if (cpu
->register_widths
[rn
] == 32)
810 *(unsigned32
*)memory
= H2T_4 ((unsigned32
)(cpu
->registers
[rn
]));
815 *(unsigned64
*)memory
= H2T_8 ((unsigned64
)(cpu
->registers
[rn
]));
822 sim_create_inferior (sd
, abfd
, argv
,env
)
830 printf("DBG: sim_create_inferior entered: start_address = 0x%s\n",
838 /* override PC value set by ColdReset () */
840 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
842 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
843 CIA_SET (cpu
, (unsigned64
) bfd_get_start_address (abfd
));
847 #if 0 /* def DEBUG */
850 /* We should really place the argv slot values into the argument
851 registers, and onto the stack as required. However, this
852 assumes that we have a stack defined, which is not
853 necessarily true at the moment. */
855 sim_io_printf(sd
,"sim_create_inferior() : passed arguments ignored\n");
856 for (cptr
= argv
; (cptr
&& *cptr
); cptr
++)
857 printf("DBG: arg \"%s\"\n",*cptr
);
865 sim_do_command (sd
,cmd
)
869 if (sim_args_command (sd
, cmd
) != SIM_RC_OK
)
870 sim_io_printf (sd
, "Error: \"%s\" is not a valid MIPS simulator command.\n",
874 /*---------------------------------------------------------------------------*/
875 /*-- Private simulator support interface ------------------------------------*/
876 /*---------------------------------------------------------------------------*/
878 /* Read a null terminated string from memory, return in a buffer */
887 while (sim_read (sd
, addr
+ nr
, &null
, 1) == 1 && null
!= 0)
889 buf
= NZALLOC (char, nr
+ 1);
890 sim_read (sd
, addr
, buf
, nr
);
894 /* Simple monitor interface (currently setup for the IDT and PMON monitors) */
896 sim_monitor (SIM_DESC sd
,
902 printf("DBG: sim_monitor: entered (reason = %d)\n",reason
);
905 /* The IDT monitor actually allows two instructions per vector
906 slot. However, the simulator currently causes a trap on each
907 individual instruction. We cheat, and lose the bottom bit. */
910 /* The following callback functions are available, however the
911 monitor we are simulating does not make use of them: get_errno,
912 isatty, lseek, rename, system, time and unlink */
916 case 6: /* int open(char *path,int flags) */
918 char *path
= fetch_str (sd
, A0
);
919 V0
= sim_io_open (sd
, path
, (int)A1
);
924 case 7: /* int read(int file,char *ptr,int len) */
928 char *buf
= zalloc (nr
);
929 V0
= sim_io_read (sd
, fd
, buf
, nr
);
930 sim_write (sd
, A1
, buf
, nr
);
935 case 8: /* int write(int file,char *ptr,int len) */
939 char *buf
= zalloc (nr
);
940 sim_read (sd
, A1
, buf
, nr
);
941 V0
= sim_io_write (sd
, fd
, buf
, nr
);
946 case 10: /* int close(int file) */
948 V0
= sim_io_close (sd
, (int)A0
);
952 case 2: /* Densan monitor: char inbyte(int waitflag) */
954 if (A0
== 0) /* waitflag == NOWAIT */
955 V0
= (unsigned_word
)-1;
957 /* Drop through to case 11 */
959 case 11: /* char inbyte(void) */
962 if (sim_io_read_stdin (sd
, &tmp
, sizeof(char)) != sizeof(char))
964 sim_io_error(sd
,"Invalid return from character read");
965 V0
= (unsigned_word
)-1;
968 V0
= (unsigned_word
)tmp
;
972 case 3: /* Densan monitor: void co(char chr) */
973 case 12: /* void outbyte(char chr) : write a byte to "stdout" */
975 char tmp
= (char)(A0
& 0xFF);
976 sim_io_write_stdout (sd
, &tmp
, sizeof(char));
980 case 17: /* void _exit() */
982 sim_io_eprintf (sd
, "sim_monitor(17): _exit(int reason) to be coded\n");
983 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
, sim_exited
,
984 (unsigned int)(A0
& 0xFFFFFFFF));
988 case 28 : /* PMON flush_cache */
991 case 55: /* void get_mem_info(unsigned int *ptr) */
992 /* in: A0 = pointer to three word memory location */
993 /* out: [A0 + 0] = size */
994 /* [A0 + 4] = instruction cache size */
995 /* [A0 + 8] = data cache size */
997 address_word value
= MEM_SIZE
/* FIXME STATE_MEM_SIZE (sd) */;
999 sim_write (sd
, A0
, (char *)&value
, sizeof (value
));
1000 /* sim_io_eprintf (sd, "sim: get_mem_info() depreciated\n"); */
1004 case 158 : /* PMON printf */
1005 /* in: A0 = pointer to format string */
1006 /* A1 = optional argument 1 */
1007 /* A2 = optional argument 2 */
1008 /* A3 = optional argument 3 */
1010 /* The following is based on the PMON printf source */
1012 address_word s
= A0
;
1014 signed_word
*ap
= &A1
; /* 1st argument */
1015 /* This isn't the quickest way, since we call the host print
1016 routine for every character almost. But it does avoid
1017 having to allocate and manage a temporary string buffer. */
1018 /* TODO: Include check that we only use three arguments (A1,
1020 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1025 enum {FMT_RJUST
, FMT_LJUST
, FMT_RJUST0
, FMT_CENTER
} fmt
= FMT_RJUST
;
1026 int width
= 0, trunc
= 0, haddot
= 0, longlong
= 0;
1027 while (sim_read (sd
, s
++, &c
, 1) && c
!= '\0')
1029 if (strchr ("dobxXulscefg%", s
))
1044 else if (c
>= '1' && c
<= '9')
1048 while (sim_read (sd
, s
++, &c
, 1) == 1 && isdigit (c
))
1051 n
= (unsigned int)strtol(tmp
,NULL
,10);
1064 sim_io_printf (sd
, "%%");
1069 address_word p
= *ap
++;
1071 while (sim_read (sd
, p
++, &ch
, 1) == 1 && ch
!= '\0')
1072 sim_io_printf(sd
, "%c", ch
);
1075 sim_io_printf(sd
,"(null)");
1078 sim_io_printf (sd
, "%c", (int)*ap
++);
1083 sim_read (sd
, s
++, &c
, 1);
1087 sim_read (sd
, s
++, &c
, 1);
1090 if (strchr ("dobxXu", c
))
1092 word64 lv
= (word64
) *ap
++;
1094 sim_io_printf(sd
,"<binary not supported>");
1097 sprintf (tmp
, "%%%s%c", longlong
? "ll" : "", c
);
1099 sim_io_printf(sd
, tmp
, lv
);
1101 sim_io_printf(sd
, tmp
, (int)lv
);
1104 else if (strchr ("eEfgG", c
))
1106 double dbl
= *(double*)(ap
++);
1107 sprintf (tmp
, "%%%d.%d%c", width
, trunc
, c
);
1108 sim_io_printf (sd
, tmp
, dbl
);
1114 sim_io_printf(sd
, "%c", c
);
1120 sim_io_error (sd
, "TODO: sim_monitor(%d) : PC = 0x%s\n",
1121 reason
, pr_addr(cia
));
1127 /* Store a word into memory. */
1130 store_word (SIM_DESC sd
,
1139 if ((vaddr
& 3) != 0)
1140 SignalExceptionAddressStore ();
1143 if (AddressTranslation (vaddr
, isDATA
, isSTORE
, &paddr
, &uncached
,
1146 const uword64 mask
= 7;
1150 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (ReverseEndian
<< 2));
1151 byte
= (vaddr
& mask
) ^ (BigEndianCPU
<< 2);
1152 memval
= ((uword64
) val
) << (8 * byte
);
1153 StoreMemory (uncached
, AccessLength_WORD
, memval
, 0, paddr
, vaddr
,
1159 /* Load a word from memory. */
1162 load_word (SIM_DESC sd
,
1167 if ((vaddr
& 3) != 0)
1168 SignalExceptionAddressLoad ();
1174 if (AddressTranslation (vaddr
, isDATA
, isLOAD
, &paddr
, &uncached
,
1177 const uword64 mask
= 0x7;
1178 const unsigned int reverse
= ReverseEndian
? 1 : 0;
1179 const unsigned int bigend
= BigEndianCPU
? 1 : 0;
1183 paddr
= (paddr
& ~mask
) | ((paddr
& mask
) ^ (reverse
<< 2));
1184 LoadMemory (&memval
,NULL
,uncached
, AccessLength_WORD
, paddr
, vaddr
,
1186 byte
= (vaddr
& mask
) ^ (bigend
<< 2);
1187 return SIGNEXTEND (((memval
>> (8 * byte
)) & 0xffffffff), 32);
1194 /* Simulate the mips16 entry and exit pseudo-instructions. These
1195 would normally be handled by the reserved instruction exception
1196 code, but for ease of simulation we just handle them directly. */
1199 mips16_entry (SIM_DESC sd
,
1204 int aregs
, sregs
, rreg
;
1207 printf("DBG: mips16_entry: entered (insn = 0x%08X)\n",insn
);
1210 aregs
= (insn
& 0x700) >> 8;
1211 sregs
= (insn
& 0x0c0) >> 6;
1212 rreg
= (insn
& 0x020) >> 5;
1214 /* This should be checked by the caller. */
1223 /* This is the entry pseudo-instruction. */
1225 for (i
= 0; i
< aregs
; i
++)
1226 store_word (SD
, CPU
, cia
, (uword64
) (SP
+ 4 * i
), GPR
[i
+ 4]);
1234 store_word (SD
, CPU
, cia
, (uword64
) tsp
, RA
);
1237 for (i
= 0; i
< sregs
; i
++)
1240 store_word (SD
, CPU
, cia
, (uword64
) tsp
, GPR
[16 + i
]);
1248 /* This is the exit pseudo-instruction. */
1255 RA
= load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1258 for (i
= 0; i
< sregs
; i
++)
1261 GPR
[i
+ 16] = load_word (SD
, CPU
, cia
, (uword64
) tsp
);
1266 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1270 FGR
[0] = WORD64LO (GPR
[4]);
1271 FPR_STATE
[0] = fmt_uninterpreted
;
1273 else if (aregs
== 6)
1275 FGR
[0] = WORD64LO (GPR
[5]);
1276 FGR
[1] = WORD64LO (GPR
[4]);
1277 FPR_STATE
[0] = fmt_uninterpreted
;
1278 FPR_STATE
[1] = fmt_uninterpreted
;
1287 /*-- trace support ----------------------------------------------------------*/
1289 /* The TRACE support is provided (if required) in the memory accessing
1290 routines. Since we are also providing the architecture specific
1291 features, the architecture simulation code can also deal with
1292 notifying the TRACE world of cache flushes, etc. Similarly we do
1293 not need to provide profiling support in the simulator engine,
1294 since we can sample in the instruction fetch control loop. By
1295 defining the TRACE manifest, we add tracing as a run-time
1299 /* Tracing by default produces "din" format (as required by
1300 dineroIII). Each line of such a trace file *MUST* have a din label
1301 and address field. The rest of the line is ignored, so comments can
1302 be included if desired. The first field is the label which must be
1303 one of the following values:
1308 3 escape record (treated as unknown access type)
1309 4 escape record (causes cache flush)
1311 The address field is a 32bit (lower-case) hexadecimal address
1312 value. The address should *NOT* be preceded by "0x".
1314 The size of the memory transfer is not important when dealing with
1315 cache lines (as long as no more than a cache line can be
1316 transferred in a single operation :-), however more information
1317 could be given following the dineroIII requirement to allow more
1318 complete memory and cache simulators to provide better
1319 results. i.e. the University of Pisa has a cache simulator that can
1320 also take bus size and speed as (variable) inputs to calculate
1321 complete system performance (a much more useful ability when trying
1322 to construct an end product, rather than a processor). They
1323 currently have an ARM version of their tool called ChARM. */
1327 dotrace (SIM_DESC sd
,
1335 if (STATE
& simTRACE
) {
1337 fprintf(tracefh
,"%d %s ; width %d ; ",
1341 va_start(ap
,comment
);
1342 vfprintf(tracefh
,comment
,ap
);
1344 fprintf(tracefh
,"\n");
1346 /* NOTE: Since the "din" format will only accept 32bit addresses, and
1347 we may be generating 64bit ones, we should put the hi-32bits of the
1348 address into the comment field. */
1350 /* TODO: Provide a buffer for the trace lines. We can then avoid
1351 performing writes until the buffer is filled, or the file is
1354 /* NOTE: We could consider adding a comment field to the "din" file
1355 produced using type 3 markers (unknown access). This would then
1356 allow information about the program that the "din" is for, and
1357 the MIPs world that was being simulated, to be placed into the
1364 /*---------------------------------------------------------------------------*/
1365 /*-- simulator engine -------------------------------------------------------*/
1366 /*---------------------------------------------------------------------------*/
1369 ColdReset (SIM_DESC sd
)
1372 for (cpu_nr
= 0; cpu_nr
< sim_engine_nr_cpus (sd
); cpu_nr
++)
1374 sim_cpu
*cpu
= STATE_CPU (sd
, cpu_nr
);
1375 /* RESET: Fixed PC address: */
1376 PC
= UNSIGNED64 (0xFFFFFFFFBFC00000);
1377 /* The reset vector address is in the unmapped, uncached memory space. */
1379 SR
&= ~(status_SR
| status_TS
| status_RP
);
1380 SR
|= (status_ERL
| status_BEV
);
1382 /* Cheat and allow access to the complete register set immediately */
1383 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
1384 && WITH_TARGET_WORD_BITSIZE
== 64)
1385 SR
|= status_FR
; /* 64bit registers */
1387 /* Ensure that any instructions with pending register updates are
1389 PENDING_INVALIDATE();
1391 /* Initialise the FPU registers to the unknown state */
1392 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
1395 for (rn
= 0; (rn
< 32); rn
++)
1396 FPR_STATE
[rn
] = fmt_uninterpreted
;
1402 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1404 /* Translate a virtual address to a physical address and cache
1405 coherence algorithm describing the mechanism used to resolve the
1406 memory reference. Given the virtual address vAddr, and whether the
1407 reference is to Instructions ot Data (IorD), find the corresponding
1408 physical address (pAddr) and the cache coherence algorithm (CCA)
1409 used to resolve the reference. If the virtual address is in one of
1410 the unmapped address spaces the physical address and the CCA are
1411 determined directly by the virtual address. If the virtual address
1412 is in one of the mapped address spaces then the TLB is used to
1413 determine the physical address and access type; if the required
1414 translation is not present in the TLB or the desired access is not
1415 permitted the function fails and an exception is taken.
1417 NOTE: Normally (RAW == 0), when address translation fails, this
1418 function raises an exception and does not return. */
1421 address_translation (SIM_DESC sd
,
1427 address_word
*pAddr
,
1431 int res
= -1; /* TRUE : Assume good return */
1434 sim_io_printf(sd
,"AddressTranslation(0x%s,%s,%s,...);\n",pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"),(LorS
? "iSTORE" : "isLOAD"));
1437 /* Check that the address is valid for this memory model */
1439 /* For a simple (flat) memory model, we simply pass virtual
1440 addressess through (mostly) unchanged. */
1441 vAddr
&= 0xFFFFFFFF;
1443 *pAddr
= vAddr
; /* default for isTARGET */
1444 *CCA
= Uncached
; /* not used for isHOST */
1449 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1451 /* Prefetch data from memory. Prefetch is an advisory instruction for
1452 which an implementation specific action is taken. The action taken
1453 may increase performance, but must not change the meaning of the
1454 program, or alter architecturally-visible state. */
1457 prefetch (SIM_DESC sd
,
1467 sim_io_printf(sd
,"Prefetch(%d,0x%s,0x%s,%d,%d);\n",CCA
,pr_addr(pAddr
),pr_addr(vAddr
),DATA
,hint
);
1470 /* For our simple memory model we do nothing */
1474 /* Description from page A-22 of the "MIPS IV Instruction Set" manual
1476 /* Load a value from memory. Use the cache and main memory as
1477 specified in the Cache Coherence Algorithm (CCA) and the sort of
1478 access (IorD) to find the contents of AccessLength memory bytes
1479 starting at physical location pAddr. The data is returned in the
1480 fixed width naturally-aligned memory element (MemElem). The
1481 low-order two (or three) bits of the address and the AccessLength
1482 indicate which of the bytes within MemElem needs to be given to the
1483 processor. If the memory access type of the reference is uncached
1484 then only the referenced bytes are read from memory and valid
1485 within the memory element. If the access type is cached, and the
1486 data is not present in cache, an implementation specific size and
1487 alignment block of memory is read and loaded into the cache to
1488 satisfy a load reference. At a minimum, the block is the entire
1491 load_memory (SIM_DESC sd
,
1506 sim_io_printf(sd
,"DBG: LoadMemory(%p,%p,%d,%d,0x%s,0x%s,%s)\n",memvalp
,memval1p
,CCA
,AccessLength
,pr_addr(pAddr
),pr_addr(vAddr
),(IorD
? "isDATA" : "isINSTRUCTION"));
1509 #if defined(WARN_MEM)
1510 if (CCA
!= uncached
)
1511 sim_io_eprintf(sd
,"LoadMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1512 #endif /* WARN_MEM */
1514 /* If instruction fetch then we need to check that the two lo-order
1515 bits are zero, otherwise raise a InstructionFetch exception: */
1516 if ((IorD
== isINSTRUCTION
)
1517 && ((pAddr
& 0x3) != 0)
1518 && (((pAddr
& 0x1) != 0) || ((vAddr
& 0x1) == 0)))
1519 SignalExceptionInstructionFetch ();
1521 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1523 /* In reality this should be a Bus Error */
1524 sim_io_error (sd
, "AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",
1526 (LOADDRMASK
+ 1) << 2,
1531 dotrace (SD
, CPU
, tracefh
,((IorD
== isDATA
) ? 0 : 2),(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"load%s",((IorD
== isDATA
) ? "" : " instruction"));
1534 /* Read the specified number of bytes from memory. Adjust for
1535 host/target byte ordering/ Align the least significant byte
1538 switch (AccessLength
)
1540 case AccessLength_QUADWORD
:
1542 unsigned_16 val
= sim_core_read_aligned_16 (cpu
, NULL_CIA
, read_map
, pAddr
);
1543 value1
= VH8_16 (val
);
1544 value
= VL8_16 (val
);
1547 case AccessLength_DOUBLEWORD
:
1548 value
= sim_core_read_aligned_8 (cpu
, NULL_CIA
,
1551 case AccessLength_SEPTIBYTE
:
1552 value
= sim_core_read_misaligned_7 (cpu
, NULL_CIA
,
1555 case AccessLength_SEXTIBYTE
:
1556 value
= sim_core_read_misaligned_6 (cpu
, NULL_CIA
,
1559 case AccessLength_QUINTIBYTE
:
1560 value
= sim_core_read_misaligned_5 (cpu
, NULL_CIA
,
1563 case AccessLength_WORD
:
1564 value
= sim_core_read_aligned_4 (cpu
, NULL_CIA
,
1567 case AccessLength_TRIPLEBYTE
:
1568 value
= sim_core_read_misaligned_3 (cpu
, NULL_CIA
,
1571 case AccessLength_HALFWORD
:
1572 value
= sim_core_read_aligned_2 (cpu
, NULL_CIA
,
1575 case AccessLength_BYTE
:
1576 value
= sim_core_read_aligned_1 (cpu
, NULL_CIA
,
1584 printf("DBG: LoadMemory() : (offset %d) : value = 0x%s%s\n",
1585 (int)(pAddr
& LOADDRMASK
),pr_uword64(value1
),pr_uword64(value
));
1588 /* See also store_memory. */
1589 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1592 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1593 shifted to the most significant byte position. */
1594 value
<<= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1596 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1597 is already in the correct postition. */
1598 value
<<= ((pAddr
& LOADDRMASK
) * 8);
1602 printf("DBG: LoadMemory() : shifted value = 0x%s%s\n",
1603 pr_uword64(value1
),pr_uword64(value
));
1607 if (memval1p
) *memval1p
= value1
;
1611 /* Description from page A-23 of the "MIPS IV Instruction Set" manual
1613 /* Store a value to memory. The specified data is stored into the
1614 physical location pAddr using the memory hierarchy (data caches and
1615 main memory) as specified by the Cache Coherence Algorithm
1616 (CCA). The MemElem contains the data for an aligned, fixed-width
1617 memory element (word for 32-bit processors, doubleword for 64-bit
1618 processors), though only the bytes that will actually be stored to
1619 memory need to be valid. The low-order two (or three) bits of pAddr
1620 and the AccessLength field indicates which of the bytes within the
1621 MemElem data should actually be stored; only these bytes in memory
1625 store_memory (SIM_DESC sd
,
1631 uword64 MemElem1
, /* High order 64 bits */
1636 sim_io_printf(sd
,"DBG: StoreMemory(%d,%d,0x%s,0x%s,0x%s,0x%s)\n",CCA
,AccessLength
,pr_uword64(MemElem
),pr_uword64(MemElem1
),pr_addr(pAddr
),pr_addr(vAddr
));
1639 #if defined(WARN_MEM)
1640 if (CCA
!= uncached
)
1641 sim_io_eprintf(sd
,"StoreMemory CCA (%d) is not uncached (currently all accesses treated as cached)\n",CCA
);
1642 #endif /* WARN_MEM */
1644 if (((pAddr
& LOADDRMASK
) + AccessLength
) > LOADDRMASK
)
1645 sim_io_error(sd
,"AccessLength of %d would extend over %dbit aligned boundary for physical address 0x%s\n",AccessLength
,(LOADDRMASK
+ 1)<<2,pr_addr(pAddr
));
1648 dotrace (SD
, CPU
, tracefh
,1,(unsigned int)(pAddr
&0xFFFFFFFF),(AccessLength
+ 1),"store");
1652 printf("DBG: StoreMemory: offset = %d MemElem = 0x%s%s\n",(unsigned int)(pAddr
& LOADDRMASK
),pr_uword64(MemElem1
),pr_uword64(MemElem
));
1655 /* See also load_memory */
1656 if (AccessLength
<= AccessLength_DOUBLEWORD
)
1659 /* for big endian target, byte (pAddr&LOADDRMASK == 0) is
1660 shifted to the most significant byte position. */
1661 MemElem
>>= (((7 - (pAddr
& LOADDRMASK
)) - AccessLength
) * 8);
1663 /* For little endian target, byte (pAddr&LOADDRMASK == 0)
1664 is already in the correct postition. */
1665 MemElem
>>= ((pAddr
& LOADDRMASK
) * 8);
1669 printf("DBG: StoreMemory: shift = %d MemElem = 0x%s%s\n",shift
,pr_uword64(MemElem1
),pr_uword64(MemElem
));
1672 switch (AccessLength
)
1674 case AccessLength_QUADWORD
:
1676 unsigned_16 val
= U16_8 (MemElem1
, MemElem
);
1677 sim_core_write_aligned_16 (cpu
, NULL_CIA
, write_map
, pAddr
, val
);
1680 case AccessLength_DOUBLEWORD
:
1681 sim_core_write_aligned_8 (cpu
, NULL_CIA
,
1682 write_map
, pAddr
, MemElem
);
1684 case AccessLength_SEPTIBYTE
:
1685 sim_core_write_misaligned_7 (cpu
, NULL_CIA
,
1686 write_map
, pAddr
, MemElem
);
1688 case AccessLength_SEXTIBYTE
:
1689 sim_core_write_misaligned_6 (cpu
, NULL_CIA
,
1690 write_map
, pAddr
, MemElem
);
1692 case AccessLength_QUINTIBYTE
:
1693 sim_core_write_misaligned_5 (cpu
, NULL_CIA
,
1694 write_map
, pAddr
, MemElem
);
1696 case AccessLength_WORD
:
1697 sim_core_write_aligned_4 (cpu
, NULL_CIA
,
1698 write_map
, pAddr
, MemElem
);
1700 case AccessLength_TRIPLEBYTE
:
1701 sim_core_write_misaligned_3 (cpu
, NULL_CIA
,
1702 write_map
, pAddr
, MemElem
);
1704 case AccessLength_HALFWORD
:
1705 sim_core_write_aligned_2 (cpu
, NULL_CIA
,
1706 write_map
, pAddr
, MemElem
);
1708 case AccessLength_BYTE
:
1709 sim_core_write_aligned_1 (cpu
, NULL_CIA
,
1710 write_map
, pAddr
, MemElem
);
1721 ifetch32 (SIM_DESC sd
,
1726 /* Copy the action of the LW instruction */
1727 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1728 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1731 unsigned32 instruction
;
1734 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1735 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1736 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1737 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1738 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1744 ifetch16 (SIM_DESC sd
,
1749 /* Copy the action of the LW instruction */
1750 address_word reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
1751 address_word bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
1754 unsigned16 instruction
;
1757 AddressTranslation (vaddr
, isINSTRUCTION
, isLOAD
, &paddr
, &cca
, isTARGET
, isREAL
);
1758 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
1759 LoadMemory (&value
, NULL
, cca
, AccessLength_WORD
, paddr
, vaddr
, isINSTRUCTION
, isREAL
);
1760 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
1761 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
1766 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1767 /* Order loads and stores to synchronise shared memory. Perform the
1768 action necessary to make the effects of groups of synchronizable
1769 loads and stores indicated by stype occur in the same order for all
1772 sync_operation (SIM_DESC sd
,
1778 sim_io_printf(sd
,"SyncOperation(%d) : TODO\n",stype
);
1783 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
1784 /* Signal an exception condition. This will result in an exception
1785 that aborts the instruction. The instruction operation pseudocode
1786 will never see a return from this function call. */
1789 signal_exception (SIM_DESC sd
,
1797 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1800 /* Ensure that any active atomic read/modify/write operation will fail: */
1803 switch (exception
) {
1804 /* TODO: For testing purposes I have been ignoring TRAPs. In
1805 reality we should either simulate them, or allow the user to
1806 ignore them at run-time.
1809 sim_io_eprintf(sd
,"Ignoring instruction TRAP (PC 0x%s)\n",pr_addr(cia
));
1815 unsigned int instruction
;
1818 va_start(ap
,exception
);
1819 instruction
= va_arg(ap
,unsigned int);
1822 code
= (instruction
>> 6) & 0xFFFFF;
1824 sim_io_eprintf(sd
,"Ignoring instruction `syscall %d' (PC 0x%s)\n",
1825 code
, pr_addr(cia
));
1829 case DebugBreakPoint
:
1830 if (! (Debug
& Debug_DM
))
1836 Debug
|= Debug_DBD
; /* signaled from within in delay slot */
1837 DEPC
= cia
- 4; /* reference the branch instruction */
1841 Debug
&= ~Debug_DBD
; /* not signaled from within a delay slot */
1845 Debug
|= Debug_DM
; /* in debugging mode */
1846 Debug
|= Debug_DBp
; /* raising a DBp exception */
1848 sim_engine_restart (SD
, CPU
, NULL
, NULL_CIA
);
1852 case ReservedInstruction
:
1855 unsigned int instruction
;
1856 va_start(ap
,exception
);
1857 instruction
= va_arg(ap
,unsigned int);
1859 /* Provide simple monitor support using ReservedInstruction
1860 exceptions. The following code simulates the fixed vector
1861 entry points into the IDT monitor by causing a simulator
1862 trap, performing the monitor operation, and returning to
1863 the address held in the $ra register (standard PCS return
1864 address). This means we only need to pre-load the vector
1865 space with suitable instruction values. For systems were
1866 actual trap instructions are used, we would not need to
1867 perform this magic. */
1868 if ((instruction
& RSVD_INSTRUCTION_MASK
) == RSVD_INSTRUCTION
)
1870 sim_monitor (SD
, CPU
, cia
, ((instruction
>> RSVD_INSTRUCTION_ARG_SHIFT
) & RSVD_INSTRUCTION_ARG_MASK
) );
1871 /* NOTE: This assumes that a branch-and-link style
1872 instruction was used to enter the vector (which is the
1873 case with the current IDT monitor). */
1874 sim_engine_restart (SD
, CPU
, NULL
, RA
);
1876 /* Look for the mips16 entry and exit instructions, and
1877 simulate a handler for them. */
1878 else if ((cia
& 1) != 0
1879 && (instruction
& 0xf81f) == 0xe809
1880 && (instruction
& 0x0c0) != 0x0c0)
1882 mips16_entry (SD
, CPU
, cia
, instruction
);
1883 sim_engine_restart (sd
, NULL
, NULL
, NULL_CIA
);
1885 /* else fall through to normal exception processing */
1886 sim_io_eprintf(sd
,"ReservedInstruction 0x%08X at PC = 0x%s\n",instruction
,pr_addr(cia
));
1891 sim_io_printf(sd
,"DBG: SignalException(%d) PC = 0x%s\n",exception
,pr_addr(cia
));
1893 /* Keep a copy of the current A0 in-case this is the program exit
1897 unsigned int instruction
;
1898 va_start(ap
,exception
);
1899 instruction
= va_arg(ap
,unsigned int);
1901 /* Check for our special terminating BREAK: */
1902 if ((instruction
& 0x03FFFFC0) == 0x03ff0000) {
1903 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1904 sim_exited
, (unsigned int)(A0
& 0xFFFFFFFF));
1907 if (STATE
& simDELAYSLOT
)
1908 PC
= cia
- 4; /* reference the branch instruction */
1911 sim_engine_halt (SD
, CPU
, NULL
, cia
,
1912 sim_stopped
, SIM_SIGTRAP
);
1915 /* Store exception code into current exception id variable (used
1918 /* TODO: If not simulating exceptions then stop the simulator
1919 execution. At the moment we always stop the simulation. */
1921 /* See figure 5-17 for an outline of the code below */
1922 if (! (SR
& status_EXL
))
1924 CAUSE
= (exception
<< 2);
1925 if (STATE
& simDELAYSLOT
)
1927 STATE
&= ~simDELAYSLOT
;
1929 EPC
= (cia
- 4); /* reference the branch instruction */
1933 /* FIXME: TLB et.al. */
1938 CAUSE
= (exception
<< 2);
1942 /* Store exception code into current exception id variable (used
1944 if (SR
& status_BEV
)
1945 PC
= (signed)0xBFC00200 + 0x180;
1947 PC
= (signed)0x80000000 + 0x180;
1949 switch ((CAUSE
>> 2) & 0x1F)
1952 /* Interrupts arrive during event processing, no need to
1956 case TLBModification
:
1961 case InstructionFetch
:
1963 /* The following is so that the simulator will continue from the
1964 exception address on breakpoint operations. */
1966 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1967 sim_stopped
, SIM_SIGBUS
);
1969 case ReservedInstruction
:
1970 case CoProcessorUnusable
:
1972 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1973 sim_stopped
, SIM_SIGILL
);
1975 case IntegerOverflow
:
1977 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1978 sim_stopped
, SIM_SIGFPE
);
1984 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1985 sim_stopped
, SIM_SIGTRAP
);
1989 sim_engine_abort (SD
, CPU
, NULL_CIA
,
1990 "FATAL: Should not encounter a breakpoint\n");
1992 default : /* Unknown internal exception */
1994 sim_engine_halt (SD
, CPU
, NULL
, NULL_CIA
,
1995 sim_stopped
, SIM_SIGABRT
);
1999 case SimulatorFault
:
2003 va_start(ap
,exception
);
2004 msg
= va_arg(ap
,char *);
2006 sim_engine_abort (SD
, CPU
, NULL_CIA
,
2007 "FATAL: Simulator error \"%s\"\n",msg
);
2014 #if defined(WARN_RESULT)
2015 /* Description from page A-26 of the "MIPS IV Instruction Set" manual (revision 3.1) */
2016 /* This function indicates that the result of the operation is
2017 undefined. However, this should not affect the instruction
2018 stream. All that is meant to happen is that the destination
2019 register is set to an undefined result. To keep the simulator
2020 simple, we just don't bother updating the destination register, so
2021 the overall result will be undefined. If desired we can stop the
2022 simulator by raising a pseudo-exception. */
2023 #define UndefinedResult() undefined_result (sd,cia)
2025 undefined_result(sd
,cia
)
2029 sim_io_eprintf(sd
,"UndefinedResult: PC = 0x%s\n",pr_addr(cia
));
2030 #if 0 /* Disabled for the moment, since it actually happens a lot at the moment. */
2035 #endif /* WARN_RESULT */
2038 cache_op (SIM_DESC sd
,
2044 unsigned int instruction
)
2046 #if 1 /* stop warning message being displayed (we should really just remove the code) */
2047 static int icache_warning
= 1;
2048 static int dcache_warning
= 1;
2050 static int icache_warning
= 0;
2051 static int dcache_warning
= 0;
2054 /* If CP0 is not useable (User or Supervisor mode) and the CP0
2055 enable bit in the Status Register is clear - a coprocessor
2056 unusable exception is taken. */
2058 sim_io_printf(sd
,"TODO: Cache availability checking (PC = 0x%s)\n",pr_addr(cia
));
2062 case 0: /* instruction cache */
2064 case 0: /* Index Invalidate */
2065 case 1: /* Index Load Tag */
2066 case 2: /* Index Store Tag */
2067 case 4: /* Hit Invalidate */
2069 case 6: /* Hit Writeback */
2070 if (!icache_warning
)
2072 sim_io_eprintf(sd
,"Instruction CACHE operation %d to be coded\n",(op
>> 2));
2078 SignalException(ReservedInstruction
,instruction
);
2083 case 1: /* data cache */
2085 case 0: /* Index Writeback Invalidate */
2086 case 1: /* Index Load Tag */
2087 case 2: /* Index Store Tag */
2088 case 3: /* Create Dirty */
2089 case 4: /* Hit Invalidate */
2090 case 5: /* Hit Writeback Invalidate */
2091 case 6: /* Hit Writeback */
2092 if (!dcache_warning
)
2094 sim_io_eprintf(sd
,"Data CACHE operation %d to be coded\n",(op
>> 2));
2100 SignalException(ReservedInstruction
,instruction
);
2105 default: /* unrecognised cache ID */
2106 SignalException(ReservedInstruction
,instruction
);
2113 /*-- FPU support routines ---------------------------------------------------*/
2115 /* Numbers are held in normalized form. The SINGLE and DOUBLE binary
2116 formats conform to ANSI/IEEE Std 754-1985. */
2117 /* SINGLE precision floating:
2118 * seeeeeeeefffffffffffffffffffffff
2120 * e = 8bits = exponent
2121 * f = 23bits = fraction
2123 /* SINGLE precision fixed:
2124 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2126 * i = 31bits = integer
2128 /* DOUBLE precision floating:
2129 * seeeeeeeeeeeffffffffffffffffffffffffffffffffffffffffffffffffffff
2131 * e = 11bits = exponent
2132 * f = 52bits = fraction
2134 /* DOUBLE precision fixed:
2135 * siiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiiii
2137 * i = 63bits = integer
2140 /* Extract sign-bit: */
2141 #define FP_S_s(v) (((v) & ((unsigned)1 << 31)) ? 1 : 0)
2142 #define FP_D_s(v) (((v) & ((uword64)1 << 63)) ? 1 : 0)
2143 /* Extract biased exponent: */
2144 #define FP_S_be(v) (((v) >> 23) & 0xFF)
2145 #define FP_D_be(v) (((v) >> 52) & 0x7FF)
2146 /* Extract unbiased Exponent: */
2147 #define FP_S_e(v) (FP_S_be(v) - 0x7F)
2148 #define FP_D_e(v) (FP_D_be(v) - 0x3FF)
2149 /* Extract complete fraction field: */
2150 #define FP_S_f(v) ((v) & ~((unsigned)0x1FF << 23))
2151 #define FP_D_f(v) ((v) & ~((uword64)0xFFF << 52))
2152 /* Extract numbered fraction bit: */
2153 #define FP_S_fb(b,v) (((v) & (1 << (23 - (b)))) ? 1 : 0)
2154 #define FP_D_fb(b,v) (((v) & (1 << (52 - (b)))) ? 1 : 0)
2156 /* Explicit QNaN values used when value required: */
2157 #define FPQNaN_SINGLE (0x7FBFFFFF)
2158 #define FPQNaN_WORD (0x7FFFFFFF)
2159 #define FPQNaN_DOUBLE (((uword64)0x7FF7FFFF << 32) | 0xFFFFFFFF)
2160 #define FPQNaN_LONG (((uword64)0x7FFFFFFF << 32) | 0xFFFFFFFF)
2162 /* Explicit Infinity values used when required: */
2163 #define FPINF_SINGLE (0x7F800000)
2164 #define FPINF_DOUBLE (((uword64)0x7FF00000 << 32) | 0x00000000)
2166 #if 1 /* def DEBUG */
2167 #define RMMODE(v) (((v) == FP_RM_NEAREST) ? "Round" : (((v) == FP_RM_TOZERO) ? "Trunc" : (((v) == FP_RM_TOPINF) ? "Ceil" : "Floor")))
2168 #define DOFMT(v) (((v) == fmt_single) ? "single" : (((v) == fmt_double) ? "double" : (((v) == fmt_word) ? "word" : (((v) == fmt_long) ? "long" : (((v) == fmt_unknown) ? "<unknown>" : (((v) == fmt_uninterpreted) ? "<uninterpreted>" : "<format error>"))))))
2172 value_fpr (SIM_DESC sd
,
2181 /* Treat unused register values, as fixed-point 64bit values: */
2182 if ((fmt
== fmt_uninterpreted
) || (fmt
== fmt_unknown
))
2184 /* If request to read data as "uninterpreted", then use the current
2186 fmt
= FPR_STATE
[fpr
];
2191 /* For values not yet accessed, set to the desired format: */
2192 if (FPR_STATE
[fpr
] == fmt_uninterpreted
) {
2193 FPR_STATE
[fpr
] = fmt
;
2195 printf("DBG: Register %d was fmt_uninterpreted. Now %s\n",fpr
,DOFMT(fmt
));
2198 if (fmt
!= FPR_STATE
[fpr
]) {
2199 sim_io_eprintf(sd
,"FPR %d (format %s) being accessed with format %s - setting to unknown (PC = 0x%s)\n",fpr
,DOFMT(FPR_STATE
[fpr
]),DOFMT(fmt
),pr_addr(cia
));
2200 FPR_STATE
[fpr
] = fmt_unknown
;
2203 if (FPR_STATE
[fpr
] == fmt_unknown
) {
2204 /* Set QNaN value: */
2207 value
= FPQNaN_SINGLE
;
2211 value
= FPQNaN_DOUBLE
;
2215 value
= FPQNaN_WORD
;
2219 value
= FPQNaN_LONG
;
2226 } else if (SizeFGR() == 64) {
2230 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2233 case fmt_uninterpreted
:
2247 value
= (FGR
[fpr
] & 0xFFFFFFFF);
2250 case fmt_uninterpreted
:
2253 if ((fpr
& 1) == 0) { /* even registers only */
2254 value
= ((((uword64
)FGR
[fpr
+1]) << 32) | (FGR
[fpr
] & 0xFFFFFFFF));
2256 SignalException(ReservedInstruction
,0);
2267 SignalExceptionSimulatorFault ("Unrecognised FP format in ValueFPR()");
2270 printf("DBG: ValueFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2277 store_fpr (SIM_DESC sd
,
2287 printf("DBG: StoreFPR: fpr = %d, fmt = %s, value = 0x%s : PC = 0x%s : SizeFGR() = %d\n",fpr
,DOFMT(fmt
),pr_addr(value
),pr_addr(cia
),SizeFGR());
2290 if (SizeFGR() == 64) {
2292 case fmt_uninterpreted_32
:
2293 fmt
= fmt_uninterpreted
;
2296 FGR
[fpr
] = (((uword64
)0xDEADC0DE << 32) | (value
& 0xFFFFFFFF));
2297 FPR_STATE
[fpr
] = fmt
;
2300 case fmt_uninterpreted_64
:
2301 fmt
= fmt_uninterpreted
;
2302 case fmt_uninterpreted
:
2306 FPR_STATE
[fpr
] = fmt
;
2310 FPR_STATE
[fpr
] = fmt_unknown
;
2316 case fmt_uninterpreted_32
:
2317 fmt
= fmt_uninterpreted
;
2320 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2321 FPR_STATE
[fpr
] = fmt
;
2324 case fmt_uninterpreted_64
:
2325 fmt
= fmt_uninterpreted
;
2326 case fmt_uninterpreted
:
2329 if ((fpr
& 1) == 0) { /* even register number only */
2330 FGR
[fpr
+1] = (value
>> 32);
2331 FGR
[fpr
] = (value
& 0xFFFFFFFF);
2332 FPR_STATE
[fpr
+ 1] = fmt
;
2333 FPR_STATE
[fpr
] = fmt
;
2335 FPR_STATE
[fpr
] = fmt_unknown
;
2336 FPR_STATE
[fpr
+ 1] = fmt_unknown
;
2337 SignalException(ReservedInstruction
,0);
2342 FPR_STATE
[fpr
] = fmt_unknown
;
2347 #if defined(WARN_RESULT)
2350 #endif /* WARN_RESULT */
2353 SignalExceptionSimulatorFault ("Unrecognised FP format in StoreFPR()");
2356 printf("DBG: StoreFPR: fpr[%d] = 0x%s (format %s)\n",fpr
,pr_addr(FGR
[fpr
]),DOFMT(fmt
));
2373 sim_fpu_32to (&wop
, op
);
2374 boolean
= sim_fpu_is_nan (&wop
);
2381 sim_fpu_64to (&wop
, op
);
2382 boolean
= sim_fpu_is_nan (&wop
);
2386 fprintf (stderr
, "Bad switch\n");
2391 printf("DBG: NaN: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2405 printf("DBG: Infinity: format %s 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2412 sim_fpu_32to (&wop
, op
);
2413 boolean
= sim_fpu_is_infinity (&wop
);
2419 sim_fpu_64to (&wop
, op
);
2420 boolean
= sim_fpu_is_infinity (&wop
);
2424 printf("DBG: TODO: unrecognised format (%s) for Infinity check\n",DOFMT(fmt
));
2429 printf("DBG: Infinity: returning %d for 0x%s (format = %s)\n",boolean
,pr_addr(op
),DOFMT(fmt
));
2443 /* Argument checking already performed by the FPCOMPARE code */
2446 printf("DBG: Less: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2449 /* The format type should already have been checked: */
2455 sim_fpu_32to (&wop1
, op1
);
2456 sim_fpu_32to (&wop2
, op2
);
2457 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2464 sim_fpu_64to (&wop1
, op1
);
2465 sim_fpu_64to (&wop2
, op2
);
2466 boolean
= sim_fpu_is_lt (&wop1
, &wop2
);
2470 fprintf (stderr
, "Bad switch\n");
2475 printf("DBG: Less: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2489 /* Argument checking already performed by the FPCOMPARE code */
2492 printf("DBG: Equal: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2495 /* The format type should already have been checked: */
2501 sim_fpu_32to (&wop1
, op1
);
2502 sim_fpu_32to (&wop2
, op2
);
2503 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2510 sim_fpu_64to (&wop1
, op1
);
2511 sim_fpu_64to (&wop2
, op2
);
2512 boolean
= sim_fpu_is_eq (&wop1
, &wop2
);
2516 fprintf (stderr
, "Bad switch\n");
2521 printf("DBG: Equal: returning %d (format = %s)\n",boolean
,DOFMT(fmt
));
2528 AbsoluteValue(op
,fmt
)
2535 printf("DBG: AbsoluteValue: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2538 /* The format type should already have been checked: */
2544 sim_fpu_32to (&wop
, op
);
2545 sim_fpu_abs (&wop
, &wop
);
2546 sim_fpu_to32 (&ans
, &wop
);
2554 sim_fpu_64to (&wop
, op
);
2555 sim_fpu_abs (&wop
, &wop
);
2556 sim_fpu_to64 (&ans
, &wop
);
2561 fprintf (stderr
, "Bad switch\n");
2576 printf("DBG: Negate: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2579 /* The format type should already have been checked: */
2585 sim_fpu_32to (&wop
, op
);
2586 sim_fpu_neg (&wop
, &wop
);
2587 sim_fpu_to32 (&ans
, &wop
);
2595 sim_fpu_64to (&wop
, op
);
2596 sim_fpu_neg (&wop
, &wop
);
2597 sim_fpu_to64 (&ans
, &wop
);
2602 fprintf (stderr
, "Bad switch\n");
2618 printf("DBG: Add: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2621 /* The registers must specify FPRs valid for operands of type
2622 "fmt". If they are not valid, the result is undefined. */
2624 /* The format type should already have been checked: */
2632 sim_fpu_32to (&wop1
, op1
);
2633 sim_fpu_32to (&wop2
, op2
);
2634 sim_fpu_add (&ans
, &wop1
, &wop2
);
2635 sim_fpu_to32 (&res
, &ans
);
2645 sim_fpu_64to (&wop1
, op1
);
2646 sim_fpu_64to (&wop2
, op2
);
2647 sim_fpu_add (&ans
, &wop1
, &wop2
);
2648 sim_fpu_to64 (&res
, &ans
);
2653 fprintf (stderr
, "Bad switch\n");
2658 printf("DBG: Add: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2673 printf("DBG: Sub: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2676 /* The registers must specify FPRs valid for operands of type
2677 "fmt". If they are not valid, the result is undefined. */
2679 /* The format type should already have been checked: */
2687 sim_fpu_32to (&wop1
, op1
);
2688 sim_fpu_32to (&wop2
, op2
);
2689 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2690 sim_fpu_to32 (&res
, &ans
);
2700 sim_fpu_64to (&wop1
, op1
);
2701 sim_fpu_64to (&wop2
, op2
);
2702 sim_fpu_sub (&ans
, &wop1
, &wop2
);
2703 sim_fpu_to64 (&res
, &ans
);
2708 fprintf (stderr
, "Bad switch\n");
2713 printf("DBG: Sub: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2720 Multiply(op1
,op2
,fmt
)
2728 printf("DBG: Multiply: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2731 /* The registers must specify FPRs valid for operands of type
2732 "fmt". If they are not valid, the result is undefined. */
2734 /* The format type should already have been checked: */
2742 sim_fpu_32to (&wop1
, op1
);
2743 sim_fpu_32to (&wop2
, op2
);
2744 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2745 sim_fpu_to32 (&res
, &ans
);
2755 sim_fpu_64to (&wop1
, op1
);
2756 sim_fpu_64to (&wop2
, op2
);
2757 sim_fpu_mul (&ans
, &wop1
, &wop2
);
2758 sim_fpu_to64 (&res
, &ans
);
2763 fprintf (stderr
, "Bad switch\n");
2768 printf("DBG: Multiply: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2783 printf("DBG: Divide: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2786 /* The registers must specify FPRs valid for operands of type
2787 "fmt". If they are not valid, the result is undefined. */
2789 /* The format type should already have been checked: */
2797 sim_fpu_32to (&wop1
, op1
);
2798 sim_fpu_32to (&wop2
, op2
);
2799 sim_fpu_div (&ans
, &wop1
, &wop2
);
2800 sim_fpu_to32 (&res
, &ans
);
2810 sim_fpu_64to (&wop1
, op1
);
2811 sim_fpu_64to (&wop2
, op2
);
2812 sim_fpu_div (&ans
, &wop1
, &wop2
);
2813 sim_fpu_to64 (&res
, &ans
);
2818 fprintf (stderr
, "Bad switch\n");
2823 printf("DBG: Divide: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2837 printf("DBG: Recip: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2840 /* The registers must specify FPRs valid for operands of type
2841 "fmt". If they are not valid, the result is undefined. */
2843 /* The format type should already have been checked: */
2850 sim_fpu_32to (&wop
, op
);
2851 sim_fpu_inv (&ans
, &wop
);
2852 sim_fpu_to32 (&res
, &ans
);
2861 sim_fpu_64to (&wop
, op
);
2862 sim_fpu_inv (&ans
, &wop
);
2863 sim_fpu_to64 (&res
, &ans
);
2868 fprintf (stderr
, "Bad switch\n");
2873 printf("DBG: Recip: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2887 printf("DBG: SquareRoot: %s: op = 0x%s\n",DOFMT(fmt
),pr_addr(op
));
2890 /* The registers must specify FPRs valid for operands of type
2891 "fmt". If they are not valid, the result is undefined. */
2893 /* The format type should already have been checked: */
2900 sim_fpu_32to (&wop
, op
);
2901 sim_fpu_sqrt (&ans
, &wop
);
2902 sim_fpu_to32 (&res
, &ans
);
2911 sim_fpu_64to (&wop
, op
);
2912 sim_fpu_sqrt (&ans
, &wop
);
2913 sim_fpu_to64 (&res
, &ans
);
2918 fprintf (stderr
, "Bad switch\n");
2923 printf("DBG: SquareRoot: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
2939 printf("DBG: Max: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
2942 /* The registers must specify FPRs valid for operands of type
2943 "fmt". If they are not valid, the result is undefined. */
2945 /* The format type should already have been checked: */
2952 sim_fpu_32to (&wop1
, op1
);
2953 sim_fpu_32to (&wop2
, op2
);
2954 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2961 sim_fpu_64to (&wop1
, op1
);
2962 sim_fpu_64to (&wop2
, op2
);
2963 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
2967 fprintf (stderr
, "Bad switch\n");
2973 case SIM_FPU_IS_SNAN
:
2974 case SIM_FPU_IS_QNAN
:
2976 case SIM_FPU_IS_NINF
:
2977 case SIM_FPU_IS_NNUMBER
:
2978 case SIM_FPU_IS_NDENORM
:
2979 case SIM_FPU_IS_NZERO
:
2980 result
= op2
; /* op1 - op2 < 0 */
2981 case SIM_FPU_IS_PINF
:
2982 case SIM_FPU_IS_PNUMBER
:
2983 case SIM_FPU_IS_PDENORM
:
2984 case SIM_FPU_IS_PZERO
:
2985 result
= op1
; /* op1 - op2 > 0 */
2987 fprintf (stderr
, "Bad switch\n");
2992 printf("DBG: Max: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3009 printf("DBG: Min: %s: op1 = 0x%s : op2 = 0x%s\n",DOFMT(fmt
),pr_addr(op1
),pr_addr(op2
));
3012 /* The registers must specify FPRs valid for operands of type
3013 "fmt". If they are not valid, the result is undefined. */
3015 /* The format type should already have been checked: */
3022 sim_fpu_32to (&wop1
, op1
);
3023 sim_fpu_32to (&wop2
, op2
);
3024 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3031 sim_fpu_64to (&wop1
, op1
);
3032 sim_fpu_64to (&wop2
, op2
);
3033 cmp
= sim_fpu_cmp (&wop1
, &wop2
);
3037 fprintf (stderr
, "Bad switch\n");
3043 case SIM_FPU_IS_SNAN
:
3044 case SIM_FPU_IS_QNAN
:
3046 case SIM_FPU_IS_NINF
:
3047 case SIM_FPU_IS_NNUMBER
:
3048 case SIM_FPU_IS_NDENORM
:
3049 case SIM_FPU_IS_NZERO
:
3050 result
= op1
; /* op1 - op2 < 0 */
3051 case SIM_FPU_IS_PINF
:
3052 case SIM_FPU_IS_PNUMBER
:
3053 case SIM_FPU_IS_PDENORM
:
3054 case SIM_FPU_IS_PZERO
:
3055 result
= op2
; /* op1 - op2 > 0 */
3057 fprintf (stderr
, "Bad switch\n");
3062 printf("DBG: Min: returning 0x%s (format = %s)\n",pr_addr(result
),DOFMT(fmt
));
3070 convert (SIM_DESC sd
,
3079 sim_fpu_round round
;
3080 unsigned32 result32
;
3081 unsigned64 result64
;
3084 printf("DBG: Convert: mode %s : op 0x%s : from %s : to %s : (PC = 0x%s)\n",RMMODE(rm
),pr_addr(op
),DOFMT(from
),DOFMT(to
),pr_addr(IPC
));
3090 /* Round result to nearest representable value. When two
3091 representable values are equally near, round to the value
3092 that has a least significant bit of zero (i.e. is even). */
3093 round
= sim_fpu_round_near
;
3096 /* Round result to the value closest to, and not greater in
3097 magnitude than, the result. */
3098 round
= sim_fpu_round_zero
;
3101 /* Round result to the value closest to, and not less than,
3103 round
= sim_fpu_round_up
;
3107 /* Round result to the value closest to, and not greater than,
3109 round
= sim_fpu_round_down
;
3113 fprintf (stderr
, "Bad switch\n");
3117 /* Convert the input to sim_fpu internal format */
3121 sim_fpu_64to (&wop
, op
);
3124 sim_fpu_32to (&wop
, op
);
3127 sim_fpu_i32to (&wop
, op
, round
);
3130 sim_fpu_i64to (&wop
, op
, round
);
3133 fprintf (stderr
, "Bad switch\n");
3137 /* Convert sim_fpu format into the output */
3138 /* The value WOP is converted to the destination format, rounding
3139 using mode RM. When the destination is a fixed-point format, then
3140 a source value of Infinity, NaN or one which would round to an
3141 integer outside the fixed point range then an IEEE Invalid
3142 Operation condition is raised. */
3146 sim_fpu_round_32 (&wop
, round
, 0);
3147 sim_fpu_to32 (&result32
, &wop
);
3148 result64
= result32
;
3151 sim_fpu_round_64 (&wop
, round
, 0);
3152 sim_fpu_to64 (&result64
, &wop
);
3155 sim_fpu_to32i (&result32
, &wop
, round
);
3156 result64
= result32
;
3159 sim_fpu_to64i (&result64
, &wop
, round
);
3163 fprintf (stderr
, "Bad switch\n");
3168 printf("DBG: Convert: returning 0x%s (to format = %s)\n",pr_addr(result64
),DOFMT(to
));
3175 /*-- co-processor support routines ------------------------------------------*/
3178 CoProcPresent(coproc_number
)
3179 unsigned int coproc_number
;
3181 /* Return TRUE if simulator provides a model for the given co-processor number */
3186 cop_lw (SIM_DESC sd
,
3191 unsigned int memword
)
3196 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3199 printf("DBG: COP_LW: memword = 0x%08X (uword64)memword = 0x%s\n",memword
,pr_addr(memword
));
3201 StoreFPR(coproc_reg
,fmt_word
,(uword64
)memword
);
3202 FPR_STATE
[coproc_reg
] = fmt_uninterpreted
;
3207 #if 0 /* this should be controlled by a configuration option */
3208 sim_io_printf(sd
,"COP_LW(%d,%d,0x%08X) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,memword
,pr_addr(cia
));
3217 cop_ld (SIM_DESC sd
,
3224 switch (coproc_num
) {
3226 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3228 StoreFPR(coproc_reg
,fmt_uninterpreted
,memword
);
3233 #if 0 /* this message should be controlled by a configuration option */
3234 sim_io_printf(sd
,"COP_LD(%d,%d,0x%s) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(memword
),pr_addr(cia
));
3243 cop_sw (SIM_DESC sd
,
3249 unsigned int value
= 0;
3254 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3257 hold
= FPR_STATE
[coproc_reg
];
3258 FPR_STATE
[coproc_reg
] = fmt_word
;
3259 value
= (unsigned int)ValueFPR(coproc_reg
,fmt_uninterpreted
);
3260 FPR_STATE
[coproc_reg
] = hold
;
3265 #if 0 /* should be controlled by configuration option */
3266 sim_io_printf(sd
,"COP_SW(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3275 cop_sd (SIM_DESC sd
,
3285 if (CURRENT_FLOATING_POINT
== HARD_FLOATING_POINT
)
3287 value
= ValueFPR(coproc_reg
,fmt_uninterpreted
);
3292 #if 0 /* should be controlled by configuration option */
3293 sim_io_printf(sd
,"COP_SD(%d,%d) at PC = 0x%s : TODO (architecture specific)\n",coproc_num
,coproc_reg
,pr_addr(cia
));
3302 decode_coproc (SIM_DESC sd
,
3305 unsigned int instruction
)
3307 int coprocnum
= ((instruction
>> 26) & 3);
3311 case 0: /* standard CPU control and cache registers */
3313 int code
= ((instruction
>> 21) & 0x1F);
3314 /* R4000 Users Manual (second edition) lists the following CP0
3316 DMFC0 Doubleword Move From CP0 (VR4100 = 01000000001tttttddddd00000000000)
3317 DMTC0 Doubleword Move To CP0 (VR4100 = 01000000101tttttddddd00000000000)
3318 MFC0 word Move From CP0 (VR4100 = 01000000000tttttddddd00000000000)
3319 MTC0 word Move To CP0 (VR4100 = 01000000100tttttddddd00000000000)
3320 TLBR Read Indexed TLB Entry (VR4100 = 01000010000000000000000000000001)
3321 TLBWI Write Indexed TLB Entry (VR4100 = 01000010000000000000000000000010)
3322 TLBWR Write Random TLB Entry (VR4100 = 01000010000000000000000000000110)
3323 TLBP Probe TLB for Matching Entry (VR4100 = 01000010000000000000000000001000)
3324 CACHE Cache operation (VR4100 = 101111bbbbbpppppiiiiiiiiiiiiiiii)
3325 ERET Exception return (VR4100 = 01000010000000000000000000011000)
3327 if (((code
== 0x00) || (code
== 0x04)) && ((instruction
& 0x7FF) == 0))
3329 int rt
= ((instruction
>> 16) & 0x1F);
3330 int rd
= ((instruction
>> 11) & 0x1F);
3332 switch (rd
) /* NOTEs: Standard CP0 registers */
3334 /* 0 = Index R4000 VR4100 VR4300 */
3335 /* 1 = Random R4000 VR4100 VR4300 */
3336 /* 2 = EntryLo0 R4000 VR4100 VR4300 */
3337 /* 3 = EntryLo1 R4000 VR4100 VR4300 */
3338 /* 4 = Context R4000 VR4100 VR4300 */
3339 /* 5 = PageMask R4000 VR4100 VR4300 */
3340 /* 6 = Wired R4000 VR4100 VR4300 */
3341 /* 8 = BadVAddr R4000 VR4100 VR4300 */
3342 /* 9 = Count R4000 VR4100 VR4300 */
3343 /* 10 = EntryHi R4000 VR4100 VR4300 */
3344 /* 11 = Compare R4000 VR4100 VR4300 */
3345 /* 12 = SR R4000 VR4100 VR4300 */
3352 /* 13 = Cause R4000 VR4100 VR4300 */
3359 /* 14 = EPC R4000 VR4100 VR4300 */
3360 /* 15 = PRId R4000 VR4100 VR4300 */
3361 #ifdef SUBTARGET_R3900
3370 /* 16 = Config R4000 VR4100 VR4300 */
3373 GPR
[rt
] = C0_CONFIG
;
3375 C0_CONFIG
= GPR
[rt
];
3378 #ifdef SUBTARGET_R3900
3387 /* 17 = LLAddr R4000 VR4100 VR4300 */
3389 /* 18 = WatchLo R4000 VR4100 VR4300 */
3390 /* 19 = WatchHi R4000 VR4100 VR4300 */
3391 /* 20 = XContext R4000 VR4100 VR4300 */
3392 /* 26 = PErr or ECC R4000 VR4100 VR4300 */
3393 /* 27 = CacheErr R4000 VR4100 */
3394 /* 28 = TagLo R4000 VR4100 VR4300 */
3395 /* 29 = TagHi R4000 VR4100 VR4300 */
3396 /* 30 = ErrorEPC R4000 VR4100 VR4300 */
3397 GPR
[rt
] = 0xDEADC0DE; /* CPR[0,rd] */
3398 /* CPR[0,rd] = GPR[rt]; */
3401 sim_io_printf(sd
,"Warning: MFC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3403 sim_io_printf(sd
,"Warning: MTC0 %d,%d ignored (architecture specific)\n",rt
,rd
);
3406 else if (code
== 0x10 && (instruction
& 0x3f) == 0x18)
3409 if (SR
& status_ERL
)
3411 /* Oops, not yet available */
3412 sim_io_printf(sd
,"Warning: ERET when SR[ERL] set not handled yet");
3422 else if (code
== 0x10 && (instruction
& 0x3f) == 0x10)
3426 else if (code
== 0x10 && (instruction
& 0x3f) == 0x1F)
3434 sim_io_eprintf(sd
,"Unrecognised COP0 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3435 /* TODO: When executing an ERET or RFE instruction we should
3436 clear LLBIT, to ensure that any out-standing atomic
3437 read/modify/write sequence fails. */
3441 case 2: /* undefined co-processor */
3442 sim_io_eprintf(sd
,"COP2 instruction 0x%08X at PC = 0x%s : No handler present\n",instruction
,pr_addr(cia
));
3445 case 1: /* should not occur (FPU co-processor) */
3446 case 3: /* should not occur (FPU co-processor) */
3447 SignalException(ReservedInstruction
,instruction
);
3454 /*-- instruction simulation -------------------------------------------------*/
3456 /* When the IGEN simulator is being built, the function below is be
3457 replaced by a generated version. However, WITH_IGEN == 2 indicates
3458 that the fubction below should be compiled but under a different
3459 name (to allow backward compatibility) */
3461 #if (WITH_IGEN != 1)
3463 void old_engine_run
PARAMS ((SIM_DESC sd
, int next_cpu_nr
, int siggnal
));
3465 old_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3468 sim_engine_run (sd
, next_cpu_nr
, nr_cpus
, siggnal
)
3471 int next_cpu_nr
; /* ignore */
3472 int nr_cpus
; /* ignore */
3473 int siggnal
; /* ignore */
3475 sim_cpu
*cpu
= STATE_CPU (sd
, 0); /* hardwire to cpu 0 */
3476 #if !defined(FASTSIM)
3477 unsigned int pipeline_count
= 1;
3481 if (STATE_MEMORY (sd
) == NULL
) {
3482 printf("DBG: simulate() entered with no memory\n");
3487 #if 0 /* Disabled to check that everything works OK */
3488 /* The VR4300 seems to sign-extend the PC on its first
3489 access. However, this may just be because it is currently
3490 configured in 32bit mode. However... */
3491 PC
= SIGNEXTEND(PC
,32);
3494 /* main controlling loop */
3496 /* vaddr is slowly being replaced with cia - current instruction
3498 address_word cia
= (uword64
)PC
;
3499 address_word vaddr
= cia
;
3502 unsigned int instruction
; /* uword64? what's this used for? FIXME! */
3506 printf("DBG: state = 0x%08X :",state
);
3507 if (state
& simHALTEX
) printf(" simHALTEX");
3508 if (state
& simHALTIN
) printf(" simHALTIN");
3513 DSSTATE
= (STATE
& simDELAYSLOT
);
3516 sim_io_printf(sd
,"DBG: DSPC = 0x%s\n",pr_addr(DSPC
));
3519 /* Fetch the next instruction from the simulator memory: */
3520 if (AddressTranslation(cia
,isINSTRUCTION
,isLOAD
,&paddr
,&cca
,isTARGET
,isREAL
)) {
3521 if ((vaddr
& 1) == 0) {
3522 /* Copy the action of the LW instruction */
3523 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 2) : 0);
3524 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 2) : 0);
3527 paddr
= ((paddr
& ~LOADDRMASK
) | ((paddr
& LOADDRMASK
) ^ (reverse
<< 2)));
3528 LoadMemory(&value
,NULL
,cca
,AccessLength_WORD
,paddr
,vaddr
,isINSTRUCTION
,isREAL
);
3529 byte
= ((vaddr
& LOADDRMASK
) ^ (bigend
<< 2));
3530 instruction
= ((value
>> (8 * byte
)) & 0xFFFFFFFF);
3532 /* Copy the action of the LH instruction */
3533 unsigned int reverse
= (ReverseEndian
? (LOADDRMASK
>> 1) : 0);
3534 unsigned int bigend
= (BigEndianCPU
? (LOADDRMASK
>> 1) : 0);
3537 paddr
= (((paddr
& ~ (uword64
) 1) & ~LOADDRMASK
)
3538 | (((paddr
& ~ (uword64
) 1) & LOADDRMASK
) ^ (reverse
<< 1)));
3539 LoadMemory(&value
,NULL
,cca
, AccessLength_HALFWORD
,
3540 paddr
& ~ (uword64
) 1,
3541 vaddr
, isINSTRUCTION
, isREAL
);
3542 byte
= (((vaddr
&~ (uword64
) 1) & LOADDRMASK
) ^ (bigend
<< 1));
3543 instruction
= ((value
>> (8 * byte
)) & 0xFFFF);
3546 fprintf(stderr
,"Cannot translate address for PC = 0x%s failed\n",pr_addr(PC
));
3551 sim_io_printf(sd
,"DBG: fetched 0x%08X from PC = 0x%s\n",instruction
,pr_addr(PC
));
3554 /* This is required by exception processing, to ensure that we can
3555 cope with exceptions in the delay slots of branches that may
3556 already have changed the PC. */
3557 if ((vaddr
& 1) == 0)
3558 PC
+= 4; /* increment ready for the next fetch */
3561 /* NOTE: If we perform a delay slot change to the PC, this
3562 increment is not requuired. However, it would make the
3563 simulator more complicated to try and avoid this small hit. */
3565 /* Currently this code provides a simple model. For more
3566 complicated models we could perform exception status checks at
3567 this point, and set the simSTOP state as required. This could
3568 also include processing any hardware interrupts raised by any
3569 I/O model attached to the simulator context.
3571 Support for "asynchronous" I/O events within the simulated world
3572 could be providing by managing a counter, and calling a I/O
3573 specific handler when a particular threshold is reached. On most
3574 architectures a decrement and check for zero operation is
3575 usually quicker than an increment and compare. However, the
3576 process of managing a known value decrement to zero, is higher
3577 than the cost of using an explicit value UINT_MAX into the
3578 future. Which system is used will depend on how complicated the
3579 I/O model is, and how much it is likely to affect the simulator
3582 If events need to be scheduled further in the future than
3583 UINT_MAX event ticks, then the I/O model should just provide its
3584 own counter, triggered from the event system. */
3586 /* MIPS pipeline ticks. To allow for future support where the
3587 pipeline hit of individual instructions is known, this control
3588 loop manages a "pipeline_count" variable. It is initialised to
3589 1 (one), and will only be changed by the simulator engine when
3590 executing an instruction. If the engine does not have access to
3591 pipeline cycle count information then all instructions will be
3592 treated as using a single cycle. NOTE: A standard system is not
3593 provided by the default simulator because different MIPS
3594 architectures have different cycle counts for the same
3597 [NOTE: pipeline_count has been replaced the event queue] */
3599 /* shuffle the floating point status pipeline state */
3600 ENGINE_ISSUE_PREFIX_HOOK();
3602 /* NOTE: For multi-context simulation environments the "instruction"
3603 variable should be local to this routine. */
3605 /* Shorthand accesses for engine. Note: If we wanted to use global
3606 variables (and a single-threaded simulator engine), then we can
3607 create the actual variables with these names. */
3609 if (!(STATE
& simSKIPNEXT
)) {
3610 /* Include the simulator engine */
3611 #include "oengine.c"
3612 #if ((GPRLEN == 64) && !PROCESSOR_64BIT) || ((GPRLEN == 32) && PROCESSOR_64BIT)
3613 #error "Mismatch between run-time simulator code and simulation engine"
3615 #if (WITH_TARGET_WORD_BITSIZE != GPRLEN)
3616 #error "Mismatch between configure WITH_TARGET_WORD_BITSIZE and gencode GPRLEN"
3618 #if ((WITH_FLOATING_POINT == HARD_FLOATING_POINT) != defined (HASFPU))
3619 #error "Mismatch between configure WITH_FLOATING_POINT and gencode HASFPU"
3622 #if defined(WARN_LOHI)
3623 /* Decrement the HI/LO validity ticks */
3628 /* start-sanitize-r5900 */
3633 /* end-sanitize-r5900 */
3634 #endif /* WARN_LOHI */
3636 /* For certain MIPS architectures, GPR[0] is hardwired to zero. We
3637 should check for it being changed. It is better doing it here,
3638 than within the simulator, since it will help keep the simulator
3641 #if defined(WARN_ZERO)
3642 sim_io_eprintf(sd
,"The ZERO register has been updated with 0x%s (PC = 0x%s) (reset back to zero)\n",pr_addr(ZERO
),pr_addr(cia
));
3643 #endif /* WARN_ZERO */
3644 ZERO
= 0; /* reset back to zero before next instruction */
3646 } else /* simSKIPNEXT check */
3647 STATE
&= ~simSKIPNEXT
;
3649 /* If the delay slot was active before the instruction is
3650 executed, then update the PC to its new value: */
3653 printf("DBG: dsstate set before instruction execution - updating PC to 0x%s\n",pr_addr(DSPC
));
3662 #if !defined(FASTSIM)
3663 if (sim_events_tickn (sd
, pipeline_count
))
3665 /* cpu->cia = cia; */
3666 sim_events_process (sd
);
3669 if (sim_events_tick (sd
))
3671 /* cpu->cia = cia; */
3672 sim_events_process (sd
);
3674 #endif /* FASTSIM */
3680 /* This code copied from gdb's utils.c. Would like to share this code,
3681 but don't know of a common place where both could get to it. */
3683 /* Temporary storage using circular buffer */
3689 static char buf
[NUMCELLS
][CELLSIZE
];
3691 if (++cell
>=NUMCELLS
) cell
=0;
3695 /* Print routines to handle variable size regs, etc */
3697 /* Eliminate warning from compiler on 32-bit systems */
3698 static int thirty_two
= 32;
3704 char *paddr_str
=get_cell();
3705 switch (sizeof(addr
))
3708 sprintf(paddr_str
,"%08lx%08lx",
3709 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3712 sprintf(paddr_str
,"%08lx",(unsigned long)addr
);
3715 sprintf(paddr_str
,"%04x",(unsigned short)(addr
&0xffff));
3718 sprintf(paddr_str
,"%x",addr
);
3727 char *paddr_str
=get_cell();
3728 sprintf(paddr_str
,"%08lx%08lx",
3729 (unsigned long)(addr
>>thirty_two
),(unsigned long)(addr
&0xffffffff));
3735 pending_tick (SIM_DESC sd
,
3740 sim_io_printf (sd
, "PENDING_DRAIN - pending_in = %d, pending_out = %d, pending_total = %d\n", PENDING_IN
, PENDING_OUT
, PENDING_TOTAL
);
3741 if (PENDING_OUT
!= PENDING_IN
)
3744 int index
= PENDING_OUT
;
3745 int total
= PENDING_TOTAL
;
3746 if (PENDING_TOTAL
== 0)
3747 sim_engine_abort (SD
, CPU
, cia
, "PENDING_DRAIN - Mis-match on pending update pointers\n");
3748 for (loop
= 0; (loop
< total
); loop
++)
3750 if (PENDING_SLOT_DEST
[index
] != NULL
)
3752 PENDING_SLOT_DELAY
[index
] -= 1;
3753 if (PENDING_SLOT_DELAY
[index
] == 0)
3755 if (PENDING_SLOT_BIT
[index
] >= 0)
3756 switch (PENDING_SLOT_SIZE
[index
])
3759 if (PENDING_SLOT_VALUE
[index
])
3760 *(unsigned32
*)PENDING_SLOT_DEST
[index
] |=
3761 BIT32 (PENDING_SLOT_BIT
[index
]);
3763 *(unsigned32
*)PENDING_SLOT_DEST
[index
] &=
3764 BIT32 (PENDING_SLOT_BIT
[index
]);
3767 if (PENDING_SLOT_VALUE
[index
])
3768 *(unsigned64
*)PENDING_SLOT_DEST
[index
] |=
3769 BIT64 (PENDING_SLOT_BIT
[index
]);
3771 *(unsigned64
*)PENDING_SLOT_DEST
[index
] &=
3772 BIT64 (PENDING_SLOT_BIT
[index
]);
3777 switch (PENDING_SLOT_SIZE
[index
])
3780 *(unsigned32
*)PENDING_SLOT_DEST
[index
] =
3781 PENDING_SLOT_VALUE
[index
];
3784 *(unsigned64
*)PENDING_SLOT_DEST
[index
] =
3785 PENDING_SLOT_VALUE
[index
];
3789 if (PENDING_OUT
== index
)
3791 PENDING_SLOT_DEST
[index
] = NULL
;
3792 PENDING_OUT
= (PENDING_OUT
+ 1) % PSLOTS
;
3797 index
= (index
+ 1) % PSLOTS
;
3801 /*---------------------------------------------------------------------------*/
3802 /*> EOF interp.c <*/