sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips16e:mips16e:               // m16e.igen
  72 :model:::mips3d:mips3d:                 // mips3d.igen
  73 :model:::mdmx:mdmx:                     // mdmx.igen
  74
  75 //  Vendor Extensions
  76 //
  77 //  Instructions specific to these extensions are in separate .igen files.
  78 //  Extensions add instructions on to a base ISA.
  79 :model:::sb1:sb1:                       // sb1.igen
  80
  81
  82 // Pseudo instructions known by IGEN
  83 :internal::::illegal:
  84 {
  85   SignalException (ReservedInstruction, 0);
  86 }
  87
  88
  89 // Pseudo instructions known by interp.c
  90 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  91 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  92 "rsvd <OP>"
  93 {
  94   SignalException (ReservedInstruction, instruction_0);
  95 }
  96
  97
  98
  99 // Helper:
 100 //
 101 // Simulate a 32 bit delayslot instruction
 102 //
 103
 104 :function:::address_word:delayslot32:address_word target
 105 {
 106   instruction_word delay_insn;
 107   sim_events_slip (SD, 1);
 108   DSPC = CIA;
 109   CIA = CIA + 4; /* NOTE not mips16 */
 110   STATE |= simDELAYSLOT;
 111   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 112   ENGINE_ISSUE_PREFIX_HOOK();
 113   idecode_issue (CPU_, delay_insn, (CIA));
 114   STATE &= ~simDELAYSLOT;
 115   return target;
 116 }
 117
 118 :function:::address_word:nullify_next_insn32:
 119 {
 120   sim_events_slip (SD, 1);
 121   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 122   return CIA + 8;
 123 }
 124
 125
 126 // Helper:
 127 //
 128 // Calculate an effective address given a base and an offset.
 129 //
 130
 131 :function:::address_word:loadstore_ea:address_word base, address_word offset
 132 *mipsI:
 133 *mipsII:
 134 *mipsIII:
 135 *mipsIV:
 136 *mipsV:
 137 *mips32:
 138 *mips32r2:
 139 *vr4100:
 140 *vr5000:
 141 *r3900:
 142 {
 143   return base + offset;
 144 }
 145
 146 :function:::address_word:loadstore_ea:address_word base, address_word offset
 147 *mips64:
 148 *mips64r2:
 149 {
 150 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 151   /* If in user mode and UX is not set, use 32-bit compatibility effective
 152      address computations as defined in the MIPS64 Architecture for
 153      Programmers Volume III, Revision 0.95, section 4.9.  */
 154   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 155       == (ksu_user << status_KSU_shift))
 156     return (address_word)((signed32)base + (signed32)offset);
 157 #endif
 158   return base + offset;
 159 }
 160
 161
 162 // Helper:
 163 //
 164 // Check that a 32-bit register value is properly sign-extended.
 165 // (See NotWordValue in ISA spec.)
 166 //
 167
 168 :function:::int:not_word_value:unsigned_word value
 169 *mipsI:
 170 *mipsII:
 171 *mipsIII:
 172 *mipsIV:
 173 *mipsV:
 174 *vr4100:
 175 *vr5000:
 176 *r3900:
 177 {
 178   /* For historical simulator compatibility (until documentation is
 179      found that makes these operations unpredictable on some of these
 180      architectures), this check never returns true.  */
 181   return 0;
 182 }
 183
 184 :function:::int:not_word_value:unsigned_word value
 185 *mips32:
 186 *mips32r2:
 187 {
 188   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 189   return 0;
 190 }
 191
 192 :function:::int:not_word_value:unsigned_word value
 193 *mips64:
 194 *mips64r2:
 195 {
 196   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 197 }
 198
 199
 200 // Helper:
 201 //
 202 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 203 // theoretically portable code which invokes non-portable behaviour from
 204 // running with no indication of the portability issue.
 205 // (See definition of UNPREDICTABLE in ISA spec.)
 206 //
 207
 208 :function:::void:unpredictable:
 209 *mipsI:
 210 *mipsII:
 211 *mipsIII:
 212 *mipsIV:
 213 *mipsV:
 214 *vr4100:
 215 *vr5000:
 216 *r3900:
 217 {
 218 }
 219
 220 :function:::void:unpredictable:
 221 *mips32:
 222 *mips32r2:
 223 *mips64:
 224 *mips64r2:
 225 {
 226   unpredictable_action (CPU, CIA);
 227 }
 228
 229
 230 // Helpers:
 231 //
 232 // Check that an access to a HI/LO register meets timing requirements
 233 //
 234 // In all MIPS ISAs,
 235 //
 236 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 237 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 238 //
 239 // The following restrictions exist for MIPS I - MIPS III:
 240 //
 241 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 242 //      in between makes MF UNPREDICTABLE. (2)
 243 //
 244 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 245 //      in between makes MF UNPREDICTABLE. (3)
 246 //
 247 // On the r3900, restriction (2) is not present, and restriction (3) is not
 248 // present for multiplication.
 249 //
 250 // Unfortunately, there seems to be some confusion about whether the last
 251 // two restrictions should apply to "MIPS IV" as well.  One edition of
 252 // the MIPS IV ISA says they do, but references in later ISA documents
 253 // suggest they don't.
 254 //
 255 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 256 // these restrictions, while others, like the VR5500, don't.  To accomodate
 257 // such differences, the MIPS IV and MIPS V version of these helper functions
 258 // use auxillary routines to determine whether the restriction applies.
 259
 260 // check_mf_cycles:
 261 //
 262 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 263 // to check for restrictions (2) and (3) above.
 264 //
 265 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 266 {
 267   if (history->mf.timestamp + 3 > time)
 268     {
 269       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 270                         itable[MY_INDEX].name,
 271                         new, (long) CIA,
 272                         (long) history->mf.cia);
 273       return 0;
 274     }
 275   return 1;
 276 }
 277
 278
 279 // check_mt_hilo:
 280 //
 281 // Check for restriction (2) above (for ISAs/processors that have it),
 282 // and record timestamps for restriction (1) above.
 283 //
 284 :function:::int:check_mt_hilo:hilo_history *history
 285 *mipsI:
 286 *mipsII:
 287 *mipsIII:
 288 *vr4100:
 289 *vr5000:
 290 {
 291   signed64 time = sim_events_time (SD);
 292   int ok = check_mf_cycles (SD_, history, time, "MT");
 293   history->mt.timestamp = time;
 294   history->mt.cia = CIA;
 295   return ok;
 296 }
 297
 298 :function:::int:check_mt_hilo:hilo_history *history
 299 *mipsIV:
 300 *mipsV:
 301 {
 302   signed64 time = sim_events_time (SD);
 303   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 304             || check_mf_cycles (SD_, history, time, "MT"));
 305   history->mt.timestamp = time;
 306   history->mt.cia = CIA;
 307   return ok;
 308 }
 309
 310 :function:::int:check_mt_hilo:hilo_history *history
 311 *mips32:
 312 *mips32r2:
 313 *mips64:
 314 *mips64r2:
 315 *r3900:
 316 {
 317   signed64 time = sim_events_time (SD);
 318   history->mt.timestamp = time;
 319   history->mt.cia = CIA;
 320   return 1;
 321 }
 322
 323
 324 // check_mf_hilo:
 325 //
 326 // Check for restriction (1) above, and record timestamps for
 327 // restriction (2) and (3) above.
 328 //
 329 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 330 *mipsI:
 331 *mipsII:
 332 *mipsIII:
 333 *mipsIV:
 334 *mipsV:
 335 *mips32:
 336 *mips32r2:
 337 *mips64:
 338 *mips64r2:
 339 *vr4100:
 340 *vr5000:
 341 *r3900:
 342 {
 343   signed64 time = sim_events_time (SD);
 344   int ok = 1;
 345   if (peer != NULL
 346       && peer->mt.timestamp > history->op.timestamp
 347       && history->mt.timestamp < history->op.timestamp
 348       && ! (history->mf.timestamp > history->op.timestamp
 349             && history->mf.timestamp < peer->mt.timestamp)
 350       && ! (peer->mf.timestamp > history->op.timestamp
 351             && peer->mf.timestamp < peer->mt.timestamp))
 352     {
 353       /* The peer has been written to since the last OP yet we have
 354          not */
 355       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 356                         itable[MY_INDEX].name,
 357                         (long) CIA,
 358                         (long) history->op.cia,
 359                         (long) peer->mt.cia);
 360       ok = 0;
 361     }
 362   history->mf.timestamp = time;
 363   history->mf.cia = CIA;
 364   return ok;
 365 }
 366
 367
 368
 369 // check_mult_hilo:
 370 //
 371 // Check for restriction (3) above (for ISAs/processors that have it)
 372 // for MULT ops, and record timestamps for restriction (1) above.
 373 //
 374 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 375 *mipsI:
 376 *mipsII:
 377 *mipsIII:
 378 *vr4100:
 379 *vr5000:
 380 {
 381   signed64 time = sim_events_time (SD);
 382   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 383             && check_mf_cycles (SD_, lo, time, "OP"));
 384   hi->op.timestamp = time;
 385   lo->op.timestamp = time;
 386   hi->op.cia = CIA;
 387   lo->op.cia = CIA;
 388   return ok;
 389 }
 390
 391 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 392 *mipsIV:
 393 *mipsV:
 394 {
 395   signed64 time = sim_events_time (SD);
 396   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 397             || (check_mf_cycles (SD_, hi, time, "OP")
 398                 && check_mf_cycles (SD_, lo, time, "OP")));
 399   hi->op.timestamp = time;
 400   lo->op.timestamp = time;
 401   hi->op.cia = CIA;
 402   lo->op.cia = CIA;
 403   return ok;
 404 }
 405
 406 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 407 *mips32:
 408 *mips32r2:
 409 *mips64:
 410 *mips64r2:
 411 *r3900:
 412 {
 413   /* FIXME: could record the fact that a stall occured if we want */
 414   signed64 time = sim_events_time (SD);
 415   hi->op.timestamp = time;
 416   lo->op.timestamp = time;
 417   hi->op.cia = CIA;
 418   lo->op.cia = CIA;
 419   return 1;
 420 }
 421
 422
 423 // check_div_hilo:
 424 //
 425 // Check for restriction (3) above (for ISAs/processors that have it)
 426 // for DIV ops, and record timestamps for restriction (1) above.
 427 //
 428 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 429 *mipsI:
 430 *mipsII:
 431 *mipsIII:
 432 *vr4100:
 433 *vr5000:
 434 *r3900:
 435 {
 436   signed64 time = sim_events_time (SD);
 437   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 438             && check_mf_cycles (SD_, lo, time, "OP"));
 439   hi->op.timestamp = time;
 440   lo->op.timestamp = time;
 441   hi->op.cia = CIA;
 442   lo->op.cia = CIA;
 443   return ok;
 444 }
 445
 446 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 447 *mipsIV:
 448 *mipsV:
 449 {
 450   signed64 time = sim_events_time (SD);
 451   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 452             || (check_mf_cycles (SD_, hi, time, "OP")
 453                 && check_mf_cycles (SD_, lo, time, "OP")));
 454   hi->op.timestamp = time;
 455   lo->op.timestamp = time;
 456   hi->op.cia = CIA;
 457   lo->op.cia = CIA;
 458   return ok;
 459 }
 460
 461 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 462 *mips32:
 463 *mips32r2:
 464 *mips64:
 465 *mips64r2:
 466 {
 467   signed64 time = sim_events_time (SD);
 468   hi->op.timestamp = time;
 469   lo->op.timestamp = time;
 470   hi->op.cia = CIA;
 471   lo->op.cia = CIA;
 472   return 1;
 473 }
 474
 475
 476 // Helper:
 477 //
 478 // Check that the 64-bit instruction can currently be used, and signal
 479 // a ReservedInstruction exception if not.
 480 //
 481
 482 :function:::void:check_u64:instruction_word insn
 483 *mipsIII:
 484 *mipsIV:
 485 *mipsV:
 486 *vr4100:
 487 *vr5000:
 488 *vr5400:
 489 *vr5500:
 490 {
 491   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 492 }
 493
 494 :function:::void:check_u64:instruction_word insn
 495 *mips16e:
 496 *mips64:
 497 *mips64r2:
 498 {
 499 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 500   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 501     SignalException (ReservedInstruction, insn);
 502 #endif
 503 }
 504
 505
 506
 507 //
 508 // MIPS Architecture:
 509 //
 510 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 511 //
 512
 513
 514
 515 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 516 "add r<RD>, r<RS>, r<RT>"
 517 *mipsI:
 518 *mipsII:
 519 *mipsIII:
 520 *mipsIV:
 521 *mipsV:
 522 *mips32:
 523 *mips32r2:
 524 *mips64:
 525 *mips64r2:
 526 *vr4100:
 527 *vr5000:
 528 *r3900:
 529 {
 530   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 531     Unpredictable ();
 532   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 533   {
 534     ALU32_BEGIN (GPR[RS]);
 535     ALU32_ADD (GPR[RT]);
 536     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 537   }
 538   TRACE_ALU_RESULT (GPR[RD]);
 539 }
 540
 541
 542
 543 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 544 "addi r<RT>, r<RS>, <IMMEDIATE>"
 545 *mipsI:
 546 *mipsII:
 547 *mipsIII:
 548 *mipsIV:
 549 *mipsV:
 550 *mips32:
 551 *mips32r2:
 552 *mips64:
 553 *mips64r2:
 554 *vr4100:
 555 *vr5000:
 556 *r3900:
 557 {
 558   if (NotWordValue (GPR[RS]))
 559     Unpredictable ();
 560   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 561   {
 562     ALU32_BEGIN (GPR[RS]);
 563     ALU32_ADD (EXTEND16 (IMMEDIATE));
 564     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 565   }
 566   TRACE_ALU_RESULT (GPR[RT]);
 567 }
 568
 569
 570
 571 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 572 {
 573   if (NotWordValue (GPR[rs]))
 574     Unpredictable ();
 575   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 576   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 577   TRACE_ALU_RESULT (GPR[rt]);
 578 }
 579
 580 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 581 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 582 *mipsI:
 583 *mipsII:
 584 *mipsIII:
 585 *mipsIV:
 586 *mipsV:
 587 *mips32:
 588 *mips32r2:
 589 *mips64:
 590 *mips64r2:
 591 *vr4100:
 592 *vr5000:
 593 *r3900:
 594 {
 595   do_addiu (SD_, RS, RT, IMMEDIATE);
 596 }
 597
 598
 599
 600 :function:::void:do_addu:int rs, int rt, int rd
 601 {
 602   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 603     Unpredictable ();
 604   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 605   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 606   TRACE_ALU_RESULT (GPR[rd]);
 607 }
 608
 609 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 610 "addu r<RD>, r<RS>, r<RT>"
 611 *mipsI:
 612 *mipsII:
 613 *mipsIII:
 614 *mipsIV:
 615 *mipsV:
 616 *mips32:
 617 *mips32r2:
 618 *mips64:
 619 *mips64r2:
 620 *vr4100:
 621 *vr5000:
 622 *r3900:
 623 {
 624   do_addu (SD_, RS, RT, RD);
 625 }
 626
 627
 628
 629 :function:::void:do_and:int rs, int rt, int rd
 630 {
 631   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 632   GPR[rd] = GPR[rs] & GPR[rt];
 633   TRACE_ALU_RESULT (GPR[rd]);
 634 }
 635
 636 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 637 "and r<RD>, r<RS>, r<RT>"
 638 *mipsI:
 639 *mipsII:
 640 *mipsIII:
 641 *mipsIV:
 642 *mipsV:
 643 *mips32:
 644 *mips32r2:
 645 *mips64:
 646 *mips64r2:
 647 *vr4100:
 648 *vr5000:
 649 *r3900:
 650 {
 651   do_and (SD_, RS, RT, RD);
 652 }
 653
 654
 655
 656 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 657 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 658 *mipsI:
 659 *mipsII:
 660 *mipsIII:
 661 *mipsIV:
 662 *mipsV:
 663 *mips32:
 664 *mips32r2:
 665 *mips64:
 666 *mips64r2:
 667 *vr4100:
 668 *vr5000:
 669 *r3900:
 670 {
 671   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 672   GPR[RT] = GPR[RS] & IMMEDIATE;
 673   TRACE_ALU_RESULT (GPR[RT]);
 674 }
 675
 676
 677
 678 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 679 "beq r<RS>, r<RT>, <OFFSET>"
 680 *mipsI:
 681 *mipsII:
 682 *mipsIII:
 683 *mipsIV:
 684 *mipsV:
 685 *mips32:
 686 *mips32r2:
 687 *mips64:
 688 *mips64r2:
 689 *vr4100:
 690 *vr5000:
 691 *r3900:
 692 {
 693   address_word offset = EXTEND16 (OFFSET) << 2;
 694   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 695     {
 696       DELAY_SLOT (NIA + offset);
 697     }
 698 }
 699
 700
 701
 702 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 703 "beql r<RS>, r<RT>, <OFFSET>"
 704 *mipsII:
 705 *mipsIII:
 706 *mipsIV:
 707 *mipsV:
 708 *mips32:
 709 *mips32r2:
 710 *mips64:
 711 *mips64r2:
 712 *vr4100:
 713 *vr5000:
 714 *r3900:
 715 {
 716   address_word offset = EXTEND16 (OFFSET) << 2;
 717   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 718     {
 719       DELAY_SLOT (NIA + offset);
 720     }
 721   else
 722     NULLIFY_NEXT_INSTRUCTION ();
 723 }
 724
 725
 726
 727 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 728 "bgez r<RS>, <OFFSET>"
 729 *mipsI:
 730 *mipsII:
 731 *mipsIII:
 732 *mipsIV:
 733 *mipsV:
 734 *mips32:
 735 *mips32r2:
 736 *mips64:
 737 *mips64r2:
 738 *vr4100:
 739 *vr5000:
 740 *r3900:
 741 {
 742   address_word offset = EXTEND16 (OFFSET) << 2;
 743   if ((signed_word) GPR[RS] >= 0)
 744     {
 745       DELAY_SLOT (NIA + offset);
 746     }
 747 }
 748
 749
 750
 751 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 752 "bgezal r<RS>, <OFFSET>"
 753 *mipsI:
 754 *mipsII:
 755 *mipsIII:
 756 *mipsIV:
 757 *mipsV:
 758 *mips32:
 759 *mips32r2:
 760 *mips64:
 761 *mips64r2:
 762 *vr4100:
 763 *vr5000:
 764 *r3900:
 765 {
 766   address_word offset = EXTEND16 (OFFSET) << 2;
 767   if (RS == 31)
 768     Unpredictable ();
 769   RA = (CIA + 8);
 770   if ((signed_word) GPR[RS] >= 0)
 771     {
 772       DELAY_SLOT (NIA + offset);
 773     }
 774 }
 775
 776
 777
 778 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 779 "bgezall r<RS>, <OFFSET>"
 780 *mipsII:
 781 *mipsIII:
 782 *mipsIV:
 783 *mipsV:
 784 *mips32:
 785 *mips32r2:
 786 *mips64:
 787 *mips64r2:
 788 *vr4100:
 789 *vr5000:
 790 *r3900:
 791 {
 792   address_word offset = EXTEND16 (OFFSET) << 2;
 793   if (RS == 31)
 794     Unpredictable ();
 795   RA = (CIA + 8);
 796   /* NOTE: The branch occurs AFTER the next instruction has been
 797      executed */
 798   if ((signed_word) GPR[RS] >= 0)
 799     {
 800       DELAY_SLOT (NIA + offset);
 801     }
 802   else
 803     NULLIFY_NEXT_INSTRUCTION ();
 804 }
 805
 806
 807
 808 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 809 "bgezl r<RS>, <OFFSET>"
 810 *mipsII:
 811 *mipsIII:
 812 *mipsIV:
 813 *mipsV:
 814 *mips32:
 815 *mips32r2:
 816 *mips64:
 817 *mips64r2:
 818 *vr4100:
 819 *vr5000:
 820 *r3900:
 821 {
 822   address_word offset = EXTEND16 (OFFSET) << 2;
 823   if ((signed_word) GPR[RS] >= 0)
 824     {
 825       DELAY_SLOT (NIA + offset);
 826     }
 827   else
 828     NULLIFY_NEXT_INSTRUCTION ();
 829 }
 830
 831
 832
 833 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 834 "bgtz r<RS>, <OFFSET>"
 835 *mipsI:
 836 *mipsII:
 837 *mipsIII:
 838 *mipsIV:
 839 *mipsV:
 840 *mips32:
 841 *mips32r2:
 842 *mips64:
 843 *mips64r2:
 844 *vr4100:
 845 *vr5000:
 846 *r3900:
 847 {
 848   address_word offset = EXTEND16 (OFFSET) << 2;
 849   if ((signed_word) GPR[RS] > 0)
 850     {
 851       DELAY_SLOT (NIA + offset);
 852     }
 853 }
 854
 855
 856
 857 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 858 "bgtzl r<RS>, <OFFSET>"
 859 *mipsII:
 860 *mipsIII:
 861 *mipsIV:
 862 *mipsV:
 863 *mips32:
 864 *mips32r2:
 865 *mips64:
 866 *mips64r2:
 867 *vr4100:
 868 *vr5000:
 869 *r3900:
 870 {
 871   address_word offset = EXTEND16 (OFFSET) << 2;
 872   /* NOTE: The branch occurs AFTER the next instruction has been
 873      executed */
 874   if ((signed_word) GPR[RS] > 0)
 875     {
 876       DELAY_SLOT (NIA + offset);
 877     }
 878   else
 879     NULLIFY_NEXT_INSTRUCTION ();
 880 }
 881
 882
 883
 884 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 885 "blez r<RS>, <OFFSET>"
 886 *mipsI:
 887 *mipsII:
 888 *mipsIII:
 889 *mipsIV:
 890 *mipsV:
 891 *mips32:
 892 *mips32r2:
 893 *mips64:
 894 *mips64r2:
 895 *vr4100:
 896 *vr5000:
 897 *r3900:
 898 {
 899   address_word offset = EXTEND16 (OFFSET) << 2;
 900   /* NOTE: The branch occurs AFTER the next instruction has been
 901      executed */
 902   if ((signed_word) GPR[RS] <= 0)
 903     {
 904       DELAY_SLOT (NIA + offset);
 905     }
 906 }
 907
 908
 909
 910 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 911 "bgezl r<RS>, <OFFSET>"
 912 *mipsII:
 913 *mipsIII:
 914 *mipsIV:
 915 *mipsV:
 916 *mips32:
 917 *mips32r2:
 918 *mips64:
 919 *mips64r2:
 920 *vr4100:
 921 *vr5000:
 922 *r3900:
 923 {
 924   address_word offset = EXTEND16 (OFFSET) << 2;
 925   if ((signed_word) GPR[RS] <= 0)
 926     {
 927       DELAY_SLOT (NIA + offset);
 928     }
 929   else
 930     NULLIFY_NEXT_INSTRUCTION ();
 931 }
 932
 933
 934
 935 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 936 "bltz r<RS>, <OFFSET>"
 937 *mipsI:
 938 *mipsII:
 939 *mipsIII:
 940 *mipsIV:
 941 *mipsV:
 942 *mips32:
 943 *mips32r2:
 944 *mips64:
 945 *mips64r2:
 946 *vr4100:
 947 *vr5000:
 948 *r3900:
 949 {
 950   address_word offset = EXTEND16 (OFFSET) << 2;
 951   if ((signed_word) GPR[RS] < 0)
 952     {
 953       DELAY_SLOT (NIA + offset);
 954     }
 955 }
 956
 957
 958
 959 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 960 "bltzal r<RS>, <OFFSET>"
 961 *mipsI:
 962 *mipsII:
 963 *mipsIII:
 964 *mipsIV:
 965 *mipsV:
 966 *mips32:
 967 *mips32r2:
 968 *mips64:
 969 *mips64r2:
 970 *vr4100:
 971 *vr5000:
 972 *r3900:
 973 {
 974   address_word offset = EXTEND16 (OFFSET) << 2;
 975   if (RS == 31)
 976     Unpredictable ();
 977   RA = (CIA + 8);
 978   /* NOTE: The branch occurs AFTER the next instruction has been
 979      executed */
 980   if ((signed_word) GPR[RS] < 0)
 981     {
 982       DELAY_SLOT (NIA + offset);
 983     }
 984 }
 985
 986
 987
 988 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 989 "bltzall r<RS>, <OFFSET>"
 990 *mipsII:
 991 *mipsIII:
 992 *mipsIV:
 993 *mipsV:
 994 *mips32:
 995 *mips32r2:
 996 *mips64:
 997 *mips64r2:
 998 *vr4100:
 999 *vr5000:
1000 *r3900:
1001 {
1002   address_word offset = EXTEND16 (OFFSET) << 2;
1003   if (RS == 31)
1004     Unpredictable ();
1005   RA = (CIA + 8);
1006   if ((signed_word) GPR[RS] < 0)
1007     {
1008       DELAY_SLOT (NIA + offset);
1009     }
1010   else
1011     NULLIFY_NEXT_INSTRUCTION ();
1012 }
1013
1014
1015
1016 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1017 "bltzl r<RS>, <OFFSET>"
1018 *mipsII:
1019 *mipsIII:
1020 *mipsIV:
1021 *mipsV:
1022 *mips32:
1023 *mips32r2:
1024 *mips64:
1025 *mips64r2:
1026 *vr4100:
1027 *vr5000:
1028 *r3900:
1029 {
1030   address_word offset = EXTEND16 (OFFSET) << 2;
1031   /* NOTE: The branch occurs AFTER the next instruction has been
1032      executed */
1033   if ((signed_word) GPR[RS] < 0)
1034     {
1035       DELAY_SLOT (NIA + offset);
1036     }
1037   else
1038     NULLIFY_NEXT_INSTRUCTION ();
1039 }
1040
1041
1042
1043 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1044 "bne r<RS>, r<RT>, <OFFSET>"
1045 *mipsI:
1046 *mipsII:
1047 *mipsIII:
1048 *mipsIV:
1049 *mipsV:
1050 *mips32:
1051 *mips32r2:
1052 *mips64:
1053 *mips64r2:
1054 *vr4100:
1055 *vr5000:
1056 *r3900:
1057 {
1058   address_word offset = EXTEND16 (OFFSET) << 2;
1059   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1060     {
1061       DELAY_SLOT (NIA + offset);
1062     }
1063 }
1064
1065
1066
1067 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1068 "bnel r<RS>, r<RT>, <OFFSET>"
1069 *mipsII:
1070 *mipsIII:
1071 *mipsIV:
1072 *mipsV:
1073 *mips32:
1074 *mips32r2:
1075 *mips64:
1076 *mips64r2:
1077 *vr4100:
1078 *vr5000:
1079 *r3900:
1080 {
1081   address_word offset = EXTEND16 (OFFSET) << 2;
1082   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1083     {
1084       DELAY_SLOT (NIA + offset);
1085     }
1086   else
1087     NULLIFY_NEXT_INSTRUCTION ();
1088 }
1089
1090
1091
1092 000000,20.CODE,001101:SPECIAL:32::BREAK
1093 "break %#lx<CODE>"
1094 *mipsI:
1095 *mipsII:
1096 *mipsIII:
1097 *mipsIV:
1098 *mipsV:
1099 *mips32:
1100 *mips32r2:
1101 *mips64:
1102 *mips64r2:
1103 *vr4100:
1104 *vr5000:
1105 *r3900:
1106 {
1107   /* Check for some break instruction which are reserved for use by the simulator.  */
1108   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1109   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1110       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1111     {
1112       sim_engine_halt (SD, CPU, NULL, cia,
1113                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1114     }
1115   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1116            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1117     {
1118       if (STATE & simDELAYSLOT)
1119         PC = cia - 4; /* reference the branch instruction */
1120       else
1121         PC = cia;
1122       SignalException (BreakPoint, instruction_0);
1123     }
1124
1125   else
1126     {
1127       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1128          the exception. */
1129       SignalException (BreakPoint, instruction_0);
1130     }
1131 }
1132
1133
1134
1135 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1136 "clo r<RD>, r<RS>"
1137 *mips32:
1138 *mips32r2:
1139 *mips64:
1140 *mips64r2:
1141 *vr5500:
1142 {
1143   unsigned32 temp = GPR[RS];
1144   unsigned32 i, mask;
1145   if (RT != RD)
1146     Unpredictable ();
1147   if (NotWordValue (GPR[RS]))
1148     Unpredictable ();
1149   TRACE_ALU_INPUT1 (GPR[RS]);
1150   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1151     {
1152       if ((temp & mask) == 0)
1153         break;
1154       mask >>= 1;
1155     }
1156   GPR[RD] = EXTEND32 (i);
1157   TRACE_ALU_RESULT (GPR[RD]);
1158 }
1159
1160
1161
1162 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1163 "clz r<RD>, r<RS>"
1164 *mips32:
1165 *mips32r2:
1166 *mips64:
1167 *mips64r2:
1168 *vr5500:
1169 {
1170   unsigned32 temp = GPR[RS];
1171   unsigned32 i, mask;
1172   if (RT != RD)
1173     Unpredictable ();
1174   if (NotWordValue (GPR[RS]))
1175     Unpredictable ();
1176   TRACE_ALU_INPUT1 (GPR[RS]);
1177   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1178     {
1179       if ((temp & mask) != 0)
1180         break;
1181       mask >>= 1;
1182     }
1183   GPR[RD] = EXTEND32 (i);
1184   TRACE_ALU_RESULT (GPR[RD]);
1185 }
1186
1187
1188
1189 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1190 "dadd r<RD>, r<RS>, r<RT>"
1191 *mipsIII:
1192 *mipsIV:
1193 *mipsV:
1194 *mips64:
1195 *mips64r2:
1196 *vr4100:
1197 *vr5000:
1198 {
1199   check_u64 (SD_, instruction_0);
1200   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1201   {
1202     ALU64_BEGIN (GPR[RS]);
1203     ALU64_ADD (GPR[RT]);
1204     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1205   }
1206   TRACE_ALU_RESULT (GPR[RD]);
1207 }
1208
1209
1210
1211 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1212 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1213 *mipsIII:
1214 *mipsIV:
1215 *mipsV:
1216 *mips64:
1217 *mips64r2:
1218 *vr4100:
1219 *vr5000:
1220 {
1221   check_u64 (SD_, instruction_0);
1222   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1223   {
1224     ALU64_BEGIN (GPR[RS]);
1225     ALU64_ADD (EXTEND16 (IMMEDIATE));
1226     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1227   }
1228   TRACE_ALU_RESULT (GPR[RT]);
1229 }
1230
1231
1232
1233 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1234 {
1235   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1236   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1237   TRACE_ALU_RESULT (GPR[rt]);
1238 }
1239
1240 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1241 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1242 *mipsIII:
1243 *mipsIV:
1244 *mipsV:
1245 *mips64:
1246 *mips64r2:
1247 *vr4100:
1248 *vr5000:
1249 {
1250   check_u64 (SD_, instruction_0);
1251   do_daddiu (SD_, RS, RT, IMMEDIATE);
1252 }
1253
1254
1255
1256 :function:::void:do_daddu:int rs, int rt, int rd
1257 {
1258   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1259   GPR[rd] = GPR[rs] + GPR[rt];
1260   TRACE_ALU_RESULT (GPR[rd]);
1261 }
1262
1263 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1264 "daddu r<RD>, r<RS>, r<RT>"
1265 *mipsIII:
1266 *mipsIV:
1267 *mipsV:
1268 *mips64:
1269 *mips64r2:
1270 *vr4100:
1271 *vr5000:
1272 {
1273   check_u64 (SD_, instruction_0);
1274   do_daddu (SD_, RS, RT, RD);
1275 }
1276
1277
1278
1279 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1280 "dclo r<RD>, r<RS>"
1281 *mips64:
1282 *mips64r2:
1283 *vr5500:
1284 {
1285   unsigned64 temp = GPR[RS];
1286   unsigned32 i;
1287   unsigned64 mask;
1288   check_u64 (SD_, instruction_0);
1289   if (RT != RD)
1290     Unpredictable ();
1291   TRACE_ALU_INPUT1 (GPR[RS]);
1292   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1293     {
1294       if ((temp & mask) == 0)
1295         break;
1296       mask >>= 1;
1297     }
1298   GPR[RD] = EXTEND32 (i);
1299   TRACE_ALU_RESULT (GPR[RD]);
1300 }
1301
1302
1303
1304 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1305 "dclz r<RD>, r<RS>"
1306 *mips64:
1307 *mips64r2:
1308 *vr5500:
1309 {
1310   unsigned64 temp = GPR[RS];
1311   unsigned32 i;
1312   unsigned64 mask;
1313   check_u64 (SD_, instruction_0);
1314   if (RT != RD)
1315     Unpredictable ();
1316   TRACE_ALU_INPUT1 (GPR[RS]);
1317   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1318     {
1319       if ((temp & mask) != 0)
1320         break;
1321       mask >>= 1;
1322     }
1323   GPR[RD] = EXTEND32 (i);
1324   TRACE_ALU_RESULT (GPR[RD]);
1325 }
1326
1327
1328
1329 :function:::void:do_ddiv:int rs, int rt
1330 {
1331   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1332   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1333   {
1334     signed64 n = GPR[rs];
1335     signed64 d = GPR[rt];
1336     signed64 hi;
1337     signed64 lo;
1338     if (d == 0)
1339       {
1340         lo = SIGNED64 (0x8000000000000000);
1341         hi = 0;
1342       }
1343     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1344       {
1345         lo = SIGNED64 (0x8000000000000000);
1346         hi = 0;
1347       }
1348     else
1349       {
1350         lo = (n / d);
1351         hi = (n % d);
1352       }
1353     HI = hi;
1354     LO = lo;
1355   }
1356   TRACE_ALU_RESULT2 (HI, LO);
1357 }
1358
1359 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1360 "ddiv r<RS>, r<RT>"
1361 *mipsIII:
1362 *mipsIV:
1363 *mipsV:
1364 *mips64:
1365 *mips64r2:
1366 *vr4100:
1367 *vr5000:
1368 {
1369   check_u64 (SD_, instruction_0);
1370   do_ddiv (SD_, RS, RT);
1371 }
1372
1373
1374
1375 :function:::void:do_ddivu:int rs, int rt
1376 {
1377   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1378   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1379   {
1380     unsigned64 n = GPR[rs];
1381     unsigned64 d = GPR[rt];
1382     unsigned64 hi;
1383     unsigned64 lo;
1384     if (d == 0)
1385       {
1386         lo = SIGNED64 (0x8000000000000000);
1387         hi = 0;
1388       }
1389     else
1390       {
1391         lo = (n / d);
1392         hi = (n % d);
1393       }
1394     HI = hi;
1395     LO = lo;
1396   }
1397   TRACE_ALU_RESULT2 (HI, LO);
1398 }
1399
1400 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1401 "ddivu r<RS>, r<RT>"
1402 *mipsIII:
1403 *mipsIV:
1404 *mipsV:
1405 *mips64:
1406 *mips64r2:
1407 *vr4100:
1408 *vr5000:
1409 {
1410   check_u64 (SD_, instruction_0);
1411   do_ddivu (SD_, RS, RT);
1412 }
1413
1414 :function:::void:do_div:int rs, int rt
1415 {
1416   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1417   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1418   {
1419     signed32 n = GPR[rs];
1420     signed32 d = GPR[rt];
1421     if (d == 0)
1422       {
1423         LO = EXTEND32 (0x80000000);
1424         HI = EXTEND32 (0);
1425       }
1426     else if (n == SIGNED32 (0x80000000) && d == -1)
1427       {
1428         LO = EXTEND32 (0x80000000);
1429         HI = EXTEND32 (0);
1430       }
1431     else
1432       {
1433         LO = EXTEND32 (n / d);
1434         HI = EXTEND32 (n % d);
1435       }
1436   }
1437   TRACE_ALU_RESULT2 (HI, LO);
1438 }
1439
1440 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1441 "div r<RS>, r<RT>"
1442 *mipsI:
1443 *mipsII:
1444 *mipsIII:
1445 *mipsIV:
1446 *mipsV:
1447 *mips32:
1448 *mips32r2:
1449 *mips64:
1450 *mips64r2:
1451 *vr4100:
1452 *vr5000:
1453 *r3900:
1454 {
1455   do_div (SD_, RS, RT);
1456 }
1457
1458
1459
1460 :function:::void:do_divu:int rs, int rt
1461 {
1462   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1463   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1464   {
1465     unsigned32 n = GPR[rs];
1466     unsigned32 d = GPR[rt];
1467     if (d == 0)
1468       {
1469         LO = EXTEND32 (0x80000000);
1470         HI = EXTEND32 (0);
1471       }
1472     else
1473       {
1474         LO = EXTEND32 (n / d);
1475         HI = EXTEND32 (n % d);
1476       }
1477   }
1478   TRACE_ALU_RESULT2 (HI, LO);
1479 }
1480
1481 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1482 "divu r<RS>, r<RT>"
1483 *mipsI:
1484 *mipsII:
1485 *mipsIII:
1486 *mipsIV:
1487 *mipsV:
1488 *mips32:
1489 *mips32r2:
1490 *mips64:
1491 *mips64r2:
1492 *vr4100:
1493 *vr5000:
1494 *r3900:
1495 {
1496   do_divu (SD_, RS, RT);
1497 }
1498
1499
1500 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1501 {
1502   unsigned64 lo;
1503   unsigned64 hi;
1504   unsigned64 m00;
1505   unsigned64 m01;
1506   unsigned64 m10;
1507   unsigned64 m11;
1508   unsigned64 mid;
1509   int sign;
1510   unsigned64 op1 = GPR[rs];
1511   unsigned64 op2 = GPR[rt];
1512   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1513   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1514   /* make signed multiply unsigned */
1515   sign = 0;
1516   if (signed_p)
1517     {
1518       if ((signed64) op1 < 0)
1519         {
1520           op1 = - op1;
1521           ++sign;
1522         }
1523       if ((signed64) op2 < 0)
1524         {
1525           op2 = - op2;
1526           ++sign;
1527         }
1528     }
1529   /* multiply out the 4 sub products */
1530   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1531   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1532   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1533   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1534   /* add the products */
1535   mid = ((unsigned64) VH4_8 (m00)
1536          + (unsigned64) VL4_8 (m10)
1537          + (unsigned64) VL4_8 (m01));
1538   lo = U8_4 (mid, m00);
1539   hi = (m11
1540         + (unsigned64) VH4_8 (mid)
1541         + (unsigned64) VH4_8 (m01)
1542         + (unsigned64) VH4_8 (m10));
1543   /* fix the sign */
1544   if (sign & 1)
1545     {
1546       lo = -lo;
1547       if (lo == 0)
1548         hi = -hi;
1549       else
1550         hi = -hi - 1;
1551     }
1552   /* save the result HI/LO (and a gpr) */
1553   LO = lo;
1554   HI = hi;
1555   if (rd != 0)
1556     GPR[rd] = lo;
1557   TRACE_ALU_RESULT2 (HI, LO);
1558 }
1559
1560 :function:::void:do_dmult:int rs, int rt, int rd
1561 {
1562   do_dmultx (SD_, rs, rt, rd, 1);
1563 }
1564
1565 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1566 "dmult r<RS>, r<RT>"
1567 *mipsIII:
1568 *mipsIV:
1569 *mipsV:
1570 *mips64:
1571 *mips64r2:
1572 *vr4100:
1573 {
1574   check_u64 (SD_, instruction_0);
1575   do_dmult (SD_, RS, RT, 0);
1576 }
1577
1578 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1579 "dmult r<RS>, r<RT>":RD == 0
1580 "dmult r<RD>, r<RS>, r<RT>"
1581 *vr5000:
1582 {
1583   check_u64 (SD_, instruction_0);
1584   do_dmult (SD_, RS, RT, RD);
1585 }
1586
1587
1588
1589 :function:::void:do_dmultu:int rs, int rt, int rd
1590 {
1591   do_dmultx (SD_, rs, rt, rd, 0);
1592 }
1593
1594 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1595 "dmultu r<RS>, r<RT>"
1596 *mipsIII:
1597 *mipsIV:
1598 *mipsV:
1599 *mips64:
1600 *mips64r2:
1601 *vr4100:
1602 {
1603   check_u64 (SD_, instruction_0);
1604   do_dmultu (SD_, RS, RT, 0);
1605 }
1606
1607 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1608 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1609 "dmultu r<RS>, r<RT>"
1610 *vr5000:
1611 {
1612   check_u64 (SD_, instruction_0);
1613   do_dmultu (SD_, RS, RT, RD);
1614 }
1615
1616
1617 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1618 {
1619   unsigned64 result;
1620
1621   y &= 63;
1622   TRACE_ALU_INPUT2 (x, y);
1623   result = ROTR64 (x, y);
1624   TRACE_ALU_RESULT (result);
1625   return result;
1626 }
1627
1628 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1629 "dror r<RD>, r<RT>, <SHIFT>"
1630 *mips64r2:
1631 *vr5400:
1632 *vr5500:
1633 {
1634   check_u64 (SD_, instruction_0);
1635   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1636 }
1637
1638 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1639 "dror32 r<RD>, r<RT>, <SHIFT>"
1640 *mips64r2:
1641 *vr5400:
1642 *vr5500:
1643 {
1644   check_u64 (SD_, instruction_0);
1645   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1646 }
1647
1648 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1649 "drorv r<RD>, r<RT>, r<RS>"
1650 *mips64r2:
1651 *vr5400:
1652 *vr5500:
1653 {
1654   check_u64 (SD_, instruction_0);
1655   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1656 }
1657
1658
1659 :function:::void:do_dsll:int rt, int rd, int shift
1660 {
1661   TRACE_ALU_INPUT2 (GPR[rt], shift);
1662   GPR[rd] = GPR[rt] << shift;
1663   TRACE_ALU_RESULT (GPR[rd]);
1664 }
1665
1666 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1667 "dsll r<RD>, r<RT>, <SHIFT>"
1668 *mipsIII:
1669 *mipsIV:
1670 *mipsV:
1671 *mips64:
1672 *mips64r2:
1673 *vr4100:
1674 *vr5000:
1675 {
1676   check_u64 (SD_, instruction_0);
1677   do_dsll (SD_, RT, RD, SHIFT);
1678 }
1679
1680
1681 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1682 "dsll32 r<RD>, r<RT>, <SHIFT>"
1683 *mipsIII:
1684 *mipsIV:
1685 *mipsV:
1686 *mips64:
1687 *mips64r2:
1688 *vr4100:
1689 *vr5000:
1690 {
1691   int s = 32 + SHIFT;
1692   check_u64 (SD_, instruction_0);
1693   TRACE_ALU_INPUT2 (GPR[RT], s);
1694   GPR[RD] = GPR[RT] << s;
1695   TRACE_ALU_RESULT (GPR[RD]);
1696 }
1697
1698 :function:::void:do_dsllv:int rs, int rt, int rd
1699 {
1700   int s = MASKED64 (GPR[rs], 5, 0);
1701   TRACE_ALU_INPUT2 (GPR[rt], s);
1702   GPR[rd] = GPR[rt] << s;
1703   TRACE_ALU_RESULT (GPR[rd]);
1704 }
1705
1706 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1707 "dsllv r<RD>, r<RT>, r<RS>"
1708 *mipsIII:
1709 *mipsIV:
1710 *mipsV:
1711 *mips64:
1712 *mips64r2:
1713 *vr4100:
1714 *vr5000:
1715 {
1716   check_u64 (SD_, instruction_0);
1717   do_dsllv (SD_, RS, RT, RD);
1718 }
1719
1720 :function:::void:do_dsra:int rt, int rd, int shift
1721 {
1722   TRACE_ALU_INPUT2 (GPR[rt], shift);
1723   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1724   TRACE_ALU_RESULT (GPR[rd]);
1725 }
1726
1727
1728 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1729 "dsra r<RD>, r<RT>, <SHIFT>"
1730 *mipsIII:
1731 *mipsIV:
1732 *mipsV:
1733 *mips64:
1734 *mips64r2:
1735 *vr4100:
1736 *vr5000:
1737 {
1738   check_u64 (SD_, instruction_0);
1739   do_dsra (SD_, RT, RD, SHIFT);
1740 }
1741
1742
1743 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1744 "dsra32 r<RD>, r<RT>, <SHIFT>"
1745 *mipsIII:
1746 *mipsIV:
1747 *mipsV:
1748 *mips64:
1749 *mips64r2:
1750 *vr4100:
1751 *vr5000:
1752 {
1753   int s = 32 + SHIFT;
1754   check_u64 (SD_, instruction_0);
1755   TRACE_ALU_INPUT2 (GPR[RT], s);
1756   GPR[RD] = ((signed64) GPR[RT]) >> s;
1757   TRACE_ALU_RESULT (GPR[RD]);
1758 }
1759
1760
1761 :function:::void:do_dsrav:int rs, int rt, int rd
1762 {
1763   int s = MASKED64 (GPR[rs], 5, 0);
1764   TRACE_ALU_INPUT2 (GPR[rt], s);
1765   GPR[rd] = ((signed64) GPR[rt]) >> s;
1766   TRACE_ALU_RESULT (GPR[rd]);
1767 }
1768
1769 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1770 "dsrav r<RD>, r<RT>, r<RS>"
1771 *mipsIII:
1772 *mipsIV:
1773 *mipsV:
1774 *mips64:
1775 *mips64r2:
1776 *vr4100:
1777 *vr5000:
1778 {
1779   check_u64 (SD_, instruction_0);
1780   do_dsrav (SD_, RS, RT, RD);
1781 }
1782
1783 :function:::void:do_dsrl:int rt, int rd, int shift
1784 {
1785   TRACE_ALU_INPUT2 (GPR[rt], shift);
1786   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1787   TRACE_ALU_RESULT (GPR[rd]);
1788 }
1789
1790
1791 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1792 "dsrl r<RD>, r<RT>, <SHIFT>"
1793 *mipsIII:
1794 *mipsIV:
1795 *mipsV:
1796 *mips64:
1797 *mips64r2:
1798 *vr4100:
1799 *vr5000:
1800 {
1801   check_u64 (SD_, instruction_0);
1802   do_dsrl (SD_, RT, RD, SHIFT);
1803 }
1804
1805
1806 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1807 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1808 *mipsIII:
1809 *mipsIV:
1810 *mipsV:
1811 *mips64:
1812 *mips64r2:
1813 *vr4100:
1814 *vr5000:
1815 {
1816   int s = 32 + SHIFT;
1817   check_u64 (SD_, instruction_0);
1818   TRACE_ALU_INPUT2 (GPR[RT], s);
1819   GPR[RD] = (unsigned64) GPR[RT] >> s;
1820   TRACE_ALU_RESULT (GPR[RD]);
1821 }
1822
1823
1824 :function:::void:do_dsrlv:int rs, int rt, int rd
1825 {
1826   int s = MASKED64 (GPR[rs], 5, 0);
1827   TRACE_ALU_INPUT2 (GPR[rt], s);
1828   GPR[rd] = (unsigned64) GPR[rt] >> s;
1829   TRACE_ALU_RESULT (GPR[rd]);
1830 }
1831
1832
1833
1834 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1835 "dsrlv r<RD>, r<RT>, r<RS>"
1836 *mipsIII:
1837 *mipsIV:
1838 *mipsV:
1839 *mips64:
1840 *mips64r2:
1841 *vr4100:
1842 *vr5000:
1843 {
1844   check_u64 (SD_, instruction_0);
1845   do_dsrlv (SD_, RS, RT, RD);
1846 }
1847
1848
1849 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1850 "dsub r<RD>, r<RS>, r<RT>"
1851 *mipsIII:
1852 *mipsIV:
1853 *mipsV:
1854 *mips64:
1855 *mips64r2:
1856 *vr4100:
1857 *vr5000:
1858 {
1859   check_u64 (SD_, instruction_0);
1860   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1861   {
1862     ALU64_BEGIN (GPR[RS]);
1863     ALU64_SUB (GPR[RT]);
1864     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1865   }
1866   TRACE_ALU_RESULT (GPR[RD]);
1867 }
1868
1869
1870 :function:::void:do_dsubu:int rs, int rt, int rd
1871 {
1872   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1873   GPR[rd] = GPR[rs] - GPR[rt];
1874   TRACE_ALU_RESULT (GPR[rd]);
1875 }
1876
1877 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1878 "dsubu r<RD>, r<RS>, r<RT>"
1879 *mipsIII:
1880 *mipsIV:
1881 *mipsV:
1882 *mips64:
1883 *mips64r2:
1884 *vr4100:
1885 *vr5000:
1886 {
1887   check_u64 (SD_, instruction_0);
1888   do_dsubu (SD_, RS, RT, RD);
1889 }
1890
1891
1892 000010,26.INSTR_INDEX:NORMAL:32::J
1893 "j <INSTR_INDEX>"
1894 *mipsI:
1895 *mipsII:
1896 *mipsIII:
1897 *mipsIV:
1898 *mipsV:
1899 *mips32:
1900 *mips32r2:
1901 *mips64:
1902 *mips64r2:
1903 *vr4100:
1904 *vr5000:
1905 *r3900:
1906 {
1907   /* NOTE: The region used is that of the delay slot NIA and NOT the
1908      current instruction */
1909   address_word region = (NIA & MASK (63, 28));
1910   DELAY_SLOT (region | (INSTR_INDEX << 2));
1911 }
1912
1913
1914 000011,26.INSTR_INDEX:NORMAL:32::JAL
1915 "jal <INSTR_INDEX>"
1916 *mipsI:
1917 *mipsII:
1918 *mipsIII:
1919 *mipsIV:
1920 *mipsV:
1921 *mips32:
1922 *mips32r2:
1923 *mips64:
1924 *mips64r2:
1925 *vr4100:
1926 *vr5000:
1927 *r3900:
1928 {
1929   /* NOTE: The region used is that of the delay slot and NOT the
1930      current instruction */
1931   address_word region = (NIA & MASK (63, 28));
1932   GPR[31] = CIA + 8;
1933   DELAY_SLOT (region | (INSTR_INDEX << 2));
1934 }
1935
1936 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1937 "jalr r<RS>":RD == 31
1938 "jalr r<RD>, r<RS>"
1939 *mipsI:
1940 *mipsII:
1941 *mipsIII:
1942 *mipsIV:
1943 *mipsV:
1944 *mips32:
1945 *mips32r2:
1946 *mips64:
1947 *mips64r2:
1948 *vr4100:
1949 *vr5000:
1950 *r3900:
1951 {
1952   address_word temp = GPR[RS];
1953   GPR[RD] = CIA + 8;
1954   DELAY_SLOT (temp);
1955 }
1956
1957
1958 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1959 "jr r<RS>"
1960 *mipsI:
1961 *mipsII:
1962 *mipsIII:
1963 *mipsIV:
1964 *mipsV:
1965 *mips32:
1966 *mips32r2:
1967 *mips64:
1968 *mips64r2:
1969 *vr4100:
1970 *vr5000:
1971 *r3900:
1972 {
1973   DELAY_SLOT (GPR[RS]);
1974 }
1975
1976
1977 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1978 {
1979   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1980   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1981   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1982   unsigned int byte;
1983   address_word paddr;
1984   int uncached;
1985   unsigned64 memval;
1986   address_word vaddr;
1987
1988   vaddr = loadstore_ea (SD_, base, offset);
1989   if ((vaddr & access) != 0)
1990     {
1991       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1992     }
1993   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1994   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1995   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1996   byte = ((vaddr & mask) ^ bigendiancpu);
1997   return (memval >> (8 * byte));
1998 }
1999
2000 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2001 {
2002   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2003   address_word reverseendian = (ReverseEndian ? -1 : 0);
2004   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2005   unsigned int byte;
2006   unsigned int word;
2007   address_word paddr;
2008   int uncached;
2009   unsigned64 memval;
2010   address_word vaddr;
2011   int nr_lhs_bits;
2012   int nr_rhs_bits;
2013   unsigned_word lhs_mask;
2014   unsigned_word temp;
2015
2016   vaddr = loadstore_ea (SD_, base, offset);
2017   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2018   paddr = (paddr ^ (reverseendian & mask));
2019   if (BigEndianMem == 0)
2020     paddr = paddr & ~access;
2021
2022   /* compute where within the word/mem we are */
2023   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2024   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2025   nr_lhs_bits = 8 * byte + 8;
2026   nr_rhs_bits = 8 * access - 8 * byte;
2027   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2028
2029   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2030            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2031            (long) ((unsigned64) paddr >> 32), (long) paddr,
2032            word, byte, nr_lhs_bits, nr_rhs_bits); */
2033
2034   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2035   if (word == 0)
2036     {
2037       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2038       temp = (memval << nr_rhs_bits);
2039     }
2040   else
2041     {
2042       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2043       temp = (memval >> nr_lhs_bits);
2044     }
2045   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2046   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2047
2048   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2049            (long) ((unsigned64) memval >> 32), (long) memval,
2050            (long) ((unsigned64) temp >> 32), (long) temp,
2051            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2052            (long) (rt >> 32), (long) rt); */
2053   return rt;
2054 }
2055
2056 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2057 {
2058   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2059   address_word reverseendian = (ReverseEndian ? -1 : 0);
2060   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2061   unsigned int byte;
2062   address_word paddr;
2063   int uncached;
2064   unsigned64 memval;
2065   address_word vaddr;
2066
2067   vaddr = loadstore_ea (SD_, base, offset);
2068   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2069   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2070   paddr = (paddr ^ (reverseendian & mask));
2071   if (BigEndianMem != 0)
2072     paddr = paddr & ~access;
2073   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2074   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2075   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2076   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2077      (long) paddr, byte, (long) paddr, (long) memval); */
2078   {
2079     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2080     rt &= ~screen;
2081     rt |= (memval >> (8 * byte)) & screen;
2082   }
2083   return rt;
2084 }
2085
2086
2087 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2088 "lb r<RT>, <OFFSET>(r<BASE>)"
2089 *mipsI:
2090 *mipsII:
2091 *mipsIII:
2092 *mipsIV:
2093 *mipsV:
2094 *mips32:
2095 *mips32r2:
2096 *mips64:
2097 *mips64r2:
2098 *vr4100:
2099 *vr5000:
2100 *r3900:
2101 {
2102   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2103 }
2104
2105
2106 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2107 "lbu r<RT>, <OFFSET>(r<BASE>)"
2108 *mipsI:
2109 *mipsII:
2110 *mipsIII:
2111 *mipsIV:
2112 *mipsV:
2113 *mips32:
2114 *mips32r2:
2115 *mips64:
2116 *mips64r2:
2117 *vr4100:
2118 *vr5000:
2119 *r3900:
2120 {
2121   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2122 }
2123
2124
2125 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2126 "ld r<RT>, <OFFSET>(r<BASE>)"
2127 *mipsIII:
2128 *mipsIV:
2129 *mipsV:
2130 *mips64:
2131 *mips64r2:
2132 *vr4100:
2133 *vr5000:
2134 {
2135   check_u64 (SD_, instruction_0);
2136   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2137 }
2138
2139
2140 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2141 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2142 *mipsII:
2143 *mipsIII:
2144 *mipsIV:
2145 *mipsV:
2146 *mips32:
2147 *mips32r2:
2148 *mips64:
2149 *mips64r2:
2150 *vr4100:
2151 *vr5000:
2152 *r3900:
2153 {
2154   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2155 }
2156
2157
2158
2159
2160 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2161 "ldl r<RT>, <OFFSET>(r<BASE>)"
2162 *mipsIII:
2163 *mipsIV:
2164 *mipsV:
2165 *mips64:
2166 *mips64r2:
2167 *vr4100:
2168 *vr5000:
2169 {
2170   check_u64 (SD_, instruction_0);
2171   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2172 }
2173
2174
2175 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2176 "ldr r<RT>, <OFFSET>(r<BASE>)"
2177 *mipsIII:
2178 *mipsIV:
2179 *mipsV:
2180 *mips64:
2181 *mips64r2:
2182 *vr4100:
2183 *vr5000:
2184 {
2185   check_u64 (SD_, instruction_0);
2186   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2187 }
2188
2189
2190 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2191 "lh r<RT>, <OFFSET>(r<BASE>)"
2192 *mipsI:
2193 *mipsII:
2194 *mipsIII:
2195 *mipsIV:
2196 *mipsV:
2197 *mips32:
2198 *mips32r2:
2199 *mips64:
2200 *mips64r2:
2201 *vr4100:
2202 *vr5000:
2203 *r3900:
2204 {
2205   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2206 }
2207
2208
2209 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2210 "lhu r<RT>, <OFFSET>(r<BASE>)"
2211 *mipsI:
2212 *mipsII:
2213 *mipsIII:
2214 *mipsIV:
2215 *mipsV:
2216 *mips32:
2217 *mips32r2:
2218 *mips64:
2219 *mips64r2:
2220 *vr4100:
2221 *vr5000:
2222 *r3900:
2223 {
2224   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2225 }
2226
2227
2228 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2229 "ll r<RT>, <OFFSET>(r<BASE>)"
2230 *mipsII:
2231 *mipsIII:
2232 *mipsIV:
2233 *mipsV:
2234 *mips32:
2235 *mips32r2:
2236 *mips64:
2237 *mips64r2:
2238 *vr4100:
2239 *vr5000:
2240 {
2241   address_word base = GPR[BASE];
2242   address_word offset = EXTEND16 (OFFSET);
2243   {
2244     address_word vaddr = loadstore_ea (SD_, base, offset);
2245     address_word paddr;
2246     int uncached;
2247     if ((vaddr & 3) != 0)
2248       {
2249         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2250       }
2251     else
2252       {
2253         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2254           {
2255             unsigned64 memval = 0;
2256             unsigned64 memval1 = 0;
2257             unsigned64 mask = 0x7;
2258             unsigned int shift = 2;
2259             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2260             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2261             unsigned int byte;
2262             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2263             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2264             byte = ((vaddr & mask) ^ (bigend << shift));
2265             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2266             LLBIT = 1;
2267           }
2268       }
2269   }
2270 }
2271
2272
2273 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2274 "lld r<RT>, <OFFSET>(r<BASE>)"
2275 *mipsIII:
2276 *mipsIV:
2277 *mipsV:
2278 *mips64:
2279 *mips64r2:
2280 *vr4100:
2281 *vr5000:
2282 {
2283   address_word base = GPR[BASE];
2284   address_word offset = EXTEND16 (OFFSET);
2285   check_u64 (SD_, instruction_0);
2286   {
2287     address_word vaddr = loadstore_ea (SD_, base, offset);
2288     address_word paddr;
2289     int uncached;
2290     if ((vaddr & 7) != 0)
2291       {
2292         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2293       }
2294     else
2295       {
2296         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2297           {
2298             unsigned64 memval = 0;
2299             unsigned64 memval1 = 0;
2300             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2301             GPR[RT] = memval;
2302             LLBIT = 1;
2303           }
2304       }
2305   }
2306 }
2307
2308
2309 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2310 "lui r<RT>, %#lx<IMMEDIATE>"
2311 *mipsI:
2312 *mipsII:
2313 *mipsIII:
2314 *mipsIV:
2315 *mipsV:
2316 *mips32:
2317 *mips32r2:
2318 *mips64:
2319 *mips64r2:
2320 *vr4100:
2321 *vr5000:
2322 *r3900:
2323 {
2324   TRACE_ALU_INPUT1 (IMMEDIATE);
2325   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2326   TRACE_ALU_RESULT (GPR[RT]);
2327 }
2328
2329
2330 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2331 "lw r<RT>, <OFFSET>(r<BASE>)"
2332 *mipsI:
2333 *mipsII:
2334 *mipsIII:
2335 *mipsIV:
2336 *mipsV:
2337 *mips32:
2338 *mips32r2:
2339 *mips64:
2340 *mips64r2:
2341 *vr4100:
2342 *vr5000:
2343 *r3900:
2344 {
2345   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2346 }
2347
2348
2349 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2350 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2351 *mipsI:
2352 *mipsII:
2353 *mipsIII:
2354 *mipsIV:
2355 *mipsV:
2356 *mips32:
2357 *mips32r2:
2358 *mips64:
2359 *mips64r2:
2360 *vr4100:
2361 *vr5000:
2362 *r3900:
2363 {
2364   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2365 }
2366
2367
2368 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2369 "lwl r<RT>, <OFFSET>(r<BASE>)"
2370 *mipsI:
2371 *mipsII:
2372 *mipsIII:
2373 *mipsIV:
2374 *mipsV:
2375 *mips32:
2376 *mips32r2:
2377 *mips64:
2378 *mips64r2:
2379 *vr4100:
2380 *vr5000:
2381 *r3900:
2382 {
2383   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2384 }
2385
2386
2387 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2388 "lwr r<RT>, <OFFSET>(r<BASE>)"
2389 *mipsI:
2390 *mipsII:
2391 *mipsIII:
2392 *mipsIV:
2393 *mipsV:
2394 *mips32:
2395 *mips32r2:
2396 *mips64:
2397 *mips64r2:
2398 *vr4100:
2399 *vr5000:
2400 *r3900:
2401 {
2402   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2403 }
2404
2405
2406 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2407 "lwu r<RT>, <OFFSET>(r<BASE>)"
2408 *mipsIII:
2409 *mipsIV:
2410 *mipsV:
2411 *mips64:
2412 *mips64r2:
2413 *vr4100:
2414 *vr5000:
2415 {
2416   check_u64 (SD_, instruction_0);
2417   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2418 }
2419
2420
2421
2422 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2423 "madd r<RS>, r<RT>"
2424 *mips32:
2425 *mips32r2:
2426 *mips64:
2427 *mips64r2:
2428 *vr5500:
2429 {
2430   signed64 temp;
2431   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2432   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2433     Unpredictable ();
2434   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2435   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2436           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2437   LO = EXTEND32 (temp);
2438   HI = EXTEND32 (VH4_8 (temp));
2439   TRACE_ALU_RESULT2 (HI, LO);
2440 }
2441
2442
2443
2444 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2445 "maddu r<RS>, r<RT>"
2446 *mips32:
2447 *mips32r2:
2448 *mips64:
2449 *mips64r2:
2450 *vr5500:
2451 {
2452   unsigned64 temp;
2453   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2454   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2455     Unpredictable ();
2456   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2457   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2458           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2459   LO = EXTEND32 (temp);
2460   HI = EXTEND32 (VH4_8 (temp));
2461   TRACE_ALU_RESULT2 (HI, LO);
2462 }
2463
2464
2465 :function:::void:do_mfhi:int rd
2466 {
2467   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2468   TRACE_ALU_INPUT1 (HI);
2469   GPR[rd] = HI;
2470   TRACE_ALU_RESULT (GPR[rd]);
2471 }
2472
2473 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2474 "mfhi r<RD>"
2475 *mipsI:
2476 *mipsII:
2477 *mipsIII:
2478 *mipsIV:
2479 *mipsV:
2480 *mips32:
2481 *mips32r2:
2482 *mips64:
2483 *mips64r2:
2484 *vr4100:
2485 *vr5000:
2486 *r3900:
2487 {
2488   do_mfhi (SD_, RD);
2489 }
2490
2491
2492
2493 :function:::void:do_mflo:int rd
2494 {
2495   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2496   TRACE_ALU_INPUT1 (LO);
2497   GPR[rd] = LO;
2498   TRACE_ALU_RESULT (GPR[rd]);
2499 }
2500
2501 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2502 "mflo r<RD>"
2503 *mipsI:
2504 *mipsII:
2505 *mipsIII:
2506 *mipsIV:
2507 *mipsV:
2508 *mips32:
2509 *mips32r2:
2510 *mips64:
2511 *mips64r2:
2512 *vr4100:
2513 *vr5000:
2514 *r3900:
2515 {
2516   do_mflo (SD_, RD);
2517 }
2518
2519
2520
2521 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2522 "movn r<RD>, r<RS>, r<RT>"
2523 *mipsIV:
2524 *mipsV:
2525 *mips32:
2526 *mips32r2:
2527 *mips64:
2528 *mips64r2:
2529 *vr5000:
2530 {
2531   if (GPR[RT] != 0)
2532     {
2533       GPR[RD] = GPR[RS];
2534       TRACE_ALU_RESULT (GPR[RD]);
2535     }
2536 }
2537
2538
2539
2540 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2541 "movz r<RD>, r<RS>, r<RT>"
2542 *mipsIV:
2543 *mipsV:
2544 *mips32:
2545 *mips32r2:
2546 *mips64:
2547 *mips64r2:
2548 *vr5000:
2549 {
2550   if (GPR[RT] == 0)
2551     {
2552       GPR[RD] = GPR[RS];
2553       TRACE_ALU_RESULT (GPR[RD]);
2554     }
2555 }
2556
2557
2558
2559 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2560 "msub r<RS>, r<RT>"
2561 *mips32:
2562 *mips32r2:
2563 *mips64:
2564 *mips64r2:
2565 *vr5500:
2566 {
2567   signed64 temp;
2568   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2569   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2570     Unpredictable ();
2571   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2572   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2573           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2574   LO = EXTEND32 (temp);
2575   HI = EXTEND32 (VH4_8 (temp));
2576   TRACE_ALU_RESULT2 (HI, LO);
2577 }
2578
2579
2580
2581 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2582 "msubu r<RS>, r<RT>"
2583 *mips32:
2584 *mips32r2:
2585 *mips64:
2586 *mips64r2:
2587 *vr5500:
2588 {
2589   unsigned64 temp;
2590   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2591   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2592     Unpredictable ();
2593   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2594   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2595           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2596   LO = EXTEND32 (temp);
2597   HI = EXTEND32 (VH4_8 (temp));
2598   TRACE_ALU_RESULT2 (HI, LO);
2599 }
2600
2601
2602
2603 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2604 "mthi r<RS>"
2605 *mipsI:
2606 *mipsII:
2607 *mipsIII:
2608 *mipsIV:
2609 *mipsV:
2610 *mips32:
2611 *mips32r2:
2612 *mips64:
2613 *mips64r2:
2614 *vr4100:
2615 *vr5000:
2616 *r3900:
2617 {
2618   check_mt_hilo (SD_, HIHISTORY);
2619   HI = GPR[RS];
2620 }
2621
2622
2623
2624 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2625 "mtlo r<RS>"
2626 *mipsI:
2627 *mipsII:
2628 *mipsIII:
2629 *mipsIV:
2630 *mipsV:
2631 *mips32:
2632 *mips32r2:
2633 *mips64:
2634 *mips64r2:
2635 *vr4100:
2636 *vr5000:
2637 *r3900:
2638 {
2639   check_mt_hilo (SD_, LOHISTORY);
2640   LO = GPR[RS];
2641 }
2642
2643
2644
2645 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2646 "mul r<RD>, r<RS>, r<RT>"
2647 *mips32:
2648 *mips32r2:
2649 *mips64:
2650 *mips64r2:
2651 *vr5500:
2652 {
2653   signed64 prod;
2654   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2655     Unpredictable ();
2656   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2657   prod = (((signed64)(signed32) GPR[RS])
2658           * ((signed64)(signed32) GPR[RT]));
2659   GPR[RD] = EXTEND32 (VL4_8 (prod));
2660   TRACE_ALU_RESULT (GPR[RD]);
2661 }
2662
2663
2664
2665 :function:::void:do_mult:int rs, int rt, int rd
2666 {
2667   signed64 prod;
2668   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2669   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2670     Unpredictable ();
2671   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2672   prod = (((signed64)(signed32) GPR[rs])
2673           * ((signed64)(signed32) GPR[rt]));
2674   LO = EXTEND32 (VL4_8 (prod));
2675   HI = EXTEND32 (VH4_8 (prod));
2676   if (rd != 0)
2677     GPR[rd] = LO;
2678   TRACE_ALU_RESULT2 (HI, LO);
2679 }
2680
2681 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2682 "mult r<RS>, r<RT>"
2683 *mipsI:
2684 *mipsII:
2685 *mipsIII:
2686 *mipsIV:
2687 *mipsV:
2688 *mips32:
2689 *mips32r2:
2690 *mips64:
2691 *mips64r2:
2692 *vr4100:
2693 {
2694   do_mult (SD_, RS, RT, 0);
2695 }
2696
2697
2698 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2699 "mult r<RS>, r<RT>":RD == 0
2700 "mult r<RD>, r<RS>, r<RT>"
2701 *vr5000:
2702 *r3900:
2703 {
2704   do_mult (SD_, RS, RT, RD);
2705 }
2706
2707
2708 :function:::void:do_multu:int rs, int rt, int rd
2709 {
2710   unsigned64 prod;
2711   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2712   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2713     Unpredictable ();
2714   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2715   prod = (((unsigned64)(unsigned32) GPR[rs])
2716           * ((unsigned64)(unsigned32) GPR[rt]));
2717   LO = EXTEND32 (VL4_8 (prod));
2718   HI = EXTEND32 (VH4_8 (prod));
2719   if (rd != 0)
2720     GPR[rd] = LO;
2721   TRACE_ALU_RESULT2 (HI, LO);
2722 }
2723
2724 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2725 "multu r<RS>, r<RT>"
2726 *mipsI:
2727 *mipsII:
2728 *mipsIII:
2729 *mipsIV:
2730 *mipsV:
2731 *mips32:
2732 *mips32r2:
2733 *mips64:
2734 *mips64r2:
2735 *vr4100:
2736 {
2737   do_multu (SD_, RS, RT, 0);
2738 }
2739
2740 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2741 "multu r<RS>, r<RT>":RD == 0
2742 "multu r<RD>, r<RS>, r<RT>"
2743 *vr5000:
2744 *r3900:
2745 {
2746   do_multu (SD_, RS, RT, RD);
2747 }
2748
2749
2750 :function:::void:do_nor:int rs, int rt, int rd
2751 {
2752   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2753   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2754   TRACE_ALU_RESULT (GPR[rd]);
2755 }
2756
2757 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2758 "nor r<RD>, r<RS>, r<RT>"
2759 *mipsI:
2760 *mipsII:
2761 *mipsIII:
2762 *mipsIV:
2763 *mipsV:
2764 *mips32:
2765 *mips32r2:
2766 *mips64:
2767 *mips64r2:
2768 *vr4100:
2769 *vr5000:
2770 *r3900:
2771 {
2772   do_nor (SD_, RS, RT, RD);
2773 }
2774
2775
2776 :function:::void:do_or:int rs, int rt, int rd
2777 {
2778   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2779   GPR[rd] = (GPR[rs] | GPR[rt]);
2780   TRACE_ALU_RESULT (GPR[rd]);
2781 }
2782
2783 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2784 "or r<RD>, r<RS>, r<RT>"
2785 *mipsI:
2786 *mipsII:
2787 *mipsIII:
2788 *mipsIV:
2789 *mipsV:
2790 *mips32:
2791 *mips32r2:
2792 *mips64:
2793 *mips64r2:
2794 *vr4100:
2795 *vr5000:
2796 *r3900:
2797 {
2798   do_or (SD_, RS, RT, RD);
2799 }
2800
2801
2802
2803 :function:::void:do_ori:int rs, int rt, unsigned immediate
2804 {
2805   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2806   GPR[rt] = (GPR[rs] | immediate);
2807   TRACE_ALU_RESULT (GPR[rt]);
2808 }
2809
2810 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2811 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2812 *mipsI:
2813 *mipsII:
2814 *mipsIII:
2815 *mipsIV:
2816 *mipsV:
2817 *mips32:
2818 *mips32r2:
2819 *mips64:
2820 *mips64r2:
2821 *vr4100:
2822 *vr5000:
2823 *r3900:
2824 {
2825   do_ori (SD_, RS, RT, IMMEDIATE);
2826 }
2827
2828
2829 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2830 "pref <HINT>, <OFFSET>(r<BASE>)"
2831 *mipsIV:
2832 *mipsV:
2833 *mips32:
2834 *mips32r2:
2835 *mips64:
2836 *mips64r2:
2837 *vr5000:
2838 {
2839   address_word base = GPR[BASE];
2840   address_word offset = EXTEND16 (OFFSET);
2841   {
2842     address_word vaddr = loadstore_ea (SD_, base, offset);
2843     address_word paddr;
2844     int uncached;
2845     {
2846       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2847         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2848     }
2849   }
2850 }
2851
2852
2853 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2854 {
2855   unsigned64 result;
2856
2857   y &= 31;
2858   TRACE_ALU_INPUT2 (x, y);
2859   result = EXTEND32 (ROTR32 (x, y));
2860   TRACE_ALU_RESULT (result);
2861   return result;
2862 }
2863
2864 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2865 "ror r<RD>, r<RT>, <SHIFT>"
2866 *mips32r2:
2867 *mips64r2:
2868 *vr5400:
2869 *vr5500:
2870 {
2871   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2872 }
2873
2874 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2875 "rorv r<RD>, r<RT>, r<RS>"
2876 *mips32r2:
2877 *mips64r2:
2878 *vr5400:
2879 *vr5500:
2880 {
2881   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2882 }
2883
2884
2885 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2886 {
2887   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2888   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2889   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2890   unsigned int byte;
2891   address_word paddr;
2892   int uncached;
2893   unsigned64 memval;
2894   address_word vaddr;
2895
2896   vaddr = loadstore_ea (SD_, base, offset);
2897   if ((vaddr & access) != 0)
2898     {
2899       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2900     }
2901   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2902   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2903   byte = ((vaddr & mask) ^ bigendiancpu);
2904   memval = (word << (8 * byte));
2905   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2906 }
2907
2908 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2909 {
2910   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2911   address_word reverseendian = (ReverseEndian ? -1 : 0);
2912   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2913   unsigned int byte;
2914   unsigned int word;
2915   address_word paddr;
2916   int uncached;
2917   unsigned64 memval;
2918   address_word vaddr;
2919   int nr_lhs_bits;
2920   int nr_rhs_bits;
2921
2922   vaddr = loadstore_ea (SD_, base, offset);
2923   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2924   paddr = (paddr ^ (reverseendian & mask));
2925   if (BigEndianMem == 0)
2926     paddr = paddr & ~access;
2927
2928   /* compute where within the word/mem we are */
2929   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2930   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2931   nr_lhs_bits = 8 * byte + 8;
2932   nr_rhs_bits = 8 * access - 8 * byte;
2933   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2934   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2935            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2936            (long) ((unsigned64) paddr >> 32), (long) paddr,
2937            word, byte, nr_lhs_bits, nr_rhs_bits); */
2938
2939   if (word == 0)
2940     {
2941       memval = (rt >> nr_rhs_bits);
2942     }
2943   else
2944     {
2945       memval = (rt << nr_lhs_bits);
2946     }
2947   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2948            (long) ((unsigned64) rt >> 32), (long) rt,
2949            (long) ((unsigned64) memval >> 32), (long) memval); */
2950   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2951 }
2952
2953 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2954 {
2955   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2956   address_word reverseendian = (ReverseEndian ? -1 : 0);
2957   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2958   unsigned int byte;
2959   address_word paddr;
2960   int uncached;
2961   unsigned64 memval;
2962   address_word vaddr;
2963
2964   vaddr = loadstore_ea (SD_, base, offset);
2965   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2966   paddr = (paddr ^ (reverseendian & mask));
2967   if (BigEndianMem != 0)
2968     paddr &= ~access;
2969   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2970   memval = (rt << (byte * 8));
2971   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2972 }
2973
2974
2975 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2976 "sb r<RT>, <OFFSET>(r<BASE>)"
2977 *mipsI:
2978 *mipsII:
2979 *mipsIII:
2980 *mipsIV:
2981 *mipsV:
2982 *mips32:
2983 *mips32r2:
2984 *mips64:
2985 *mips64r2:
2986 *vr4100:
2987 *vr5000:
2988 *r3900:
2989 {
2990   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2991 }
2992
2993
2994 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2995 "sc r<RT>, <OFFSET>(r<BASE>)"
2996 *mipsII:
2997 *mipsIII:
2998 *mipsIV:
2999 *mipsV:
3000 *mips32:
3001 *mips32r2:
3002 *mips64:
3003 *mips64r2:
3004 *vr4100:
3005 *vr5000:
3006 {
3007   unsigned32 instruction = instruction_0;
3008   address_word base = GPR[BASE];
3009   address_word offset = EXTEND16 (OFFSET);
3010   {
3011     address_word vaddr = loadstore_ea (SD_, base, offset);
3012     address_word paddr;
3013     int uncached;
3014     if ((vaddr & 3) != 0)
3015       {
3016         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3017       }
3018     else
3019       {
3020         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3021           {
3022             unsigned64 memval = 0;
3023             unsigned64 memval1 = 0;
3024             unsigned64 mask = 0x7;
3025             unsigned int byte;
3026             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3027             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3028             memval = ((unsigned64) GPR[RT] << (8 * byte));
3029             if (LLBIT)
3030               {
3031                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3032               }
3033             GPR[RT] = LLBIT;
3034           }
3035       }
3036   }
3037 }
3038
3039
3040 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3041 "scd r<RT>, <OFFSET>(r<BASE>)"
3042 *mipsIII:
3043 *mipsIV:
3044 *mipsV:
3045 *mips64:
3046 *mips64r2:
3047 *vr4100:
3048 *vr5000:
3049 {
3050   address_word base = GPR[BASE];
3051   address_word offset = EXTEND16 (OFFSET);
3052   check_u64 (SD_, instruction_0);
3053   {
3054     address_word vaddr = loadstore_ea (SD_, base, offset);
3055     address_word paddr;
3056     int uncached;
3057     if ((vaddr & 7) != 0)
3058       {
3059         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3060       }
3061     else
3062       {
3063         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3064           {
3065             unsigned64 memval = 0;
3066             unsigned64 memval1 = 0;
3067             memval = GPR[RT];
3068             if (LLBIT)
3069               {
3070                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3071               }
3072             GPR[RT] = LLBIT;
3073           }
3074       }
3075   }
3076 }
3077
3078
3079 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3080 "sd r<RT>, <OFFSET>(r<BASE>)"
3081 *mipsIII:
3082 *mipsIV:
3083 *mipsV:
3084 *mips64:
3085 *mips64r2:
3086 *vr4100:
3087 *vr5000:
3088 {
3089   check_u64 (SD_, instruction_0);
3090   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3091 }
3092
3093
3094 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3095 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3096 *mipsII:
3097 *mipsIII:
3098 *mipsIV:
3099 *mipsV:
3100 *mips32:
3101 *mips32r2:
3102 *mips64:
3103 *mips64r2:
3104 *vr4100:
3105 *vr5000:
3106 {
3107   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3108 }
3109
3110
3111 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3112 "sdl r<RT>, <OFFSET>(r<BASE>)"
3113 *mipsIII:
3114 *mipsIV:
3115 *mipsV:
3116 *mips64:
3117 *mips64r2:
3118 *vr4100:
3119 *vr5000:
3120 {
3121   check_u64 (SD_, instruction_0);
3122   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3123 }
3124
3125
3126 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3127 "sdr r<RT>, <OFFSET>(r<BASE>)"
3128 *mipsIII:
3129 *mipsIV:
3130 *mipsV:
3131 *mips64:
3132 *mips64r2:
3133 *vr4100:
3134 *vr5000:
3135 {
3136   check_u64 (SD_, instruction_0);
3137   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3138 }
3139
3140
3141
3142 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3143 "sh r<RT>, <OFFSET>(r<BASE>)"
3144 *mipsI:
3145 *mipsII:
3146 *mipsIII:
3147 *mipsIV:
3148 *mipsV:
3149 *mips32:
3150 *mips32r2:
3151 *mips64:
3152 *mips64r2:
3153 *vr4100:
3154 *vr5000:
3155 *r3900:
3156 {
3157   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3158 }
3159
3160
3161 :function:::void:do_sll:int rt, int rd, int shift
3162 {
3163   unsigned32 temp = (GPR[rt] << shift);
3164   TRACE_ALU_INPUT2 (GPR[rt], shift);
3165   GPR[rd] = EXTEND32 (temp);
3166   TRACE_ALU_RESULT (GPR[rd]);
3167 }
3168
3169 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3170 "nop":RD == 0 && RT == 0 && SHIFT == 0
3171 "sll r<RD>, r<RT>, <SHIFT>"
3172 *mipsI:
3173 *mipsII:
3174 *mipsIII:
3175 *mipsIV:
3176 *mipsV:
3177 *vr4100:
3178 *vr5000:
3179 *r3900:
3180 {
3181   /* Skip shift for NOP, so that there won't be lots of extraneous
3182      trace output.  */
3183   if (RD != 0 || RT != 0 || SHIFT != 0)
3184     do_sll (SD_, RT, RD, SHIFT);
3185 }
3186
3187 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3188 "nop":RD == 0 && RT == 0 && SHIFT == 0
3189 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3190 "sll r<RD>, r<RT>, <SHIFT>"
3191 *mips32:
3192 *mips32r2:
3193 *mips64:
3194 *mips64r2:
3195 {
3196   /* Skip shift for NOP and SSNOP, so that there won't be lots of
3197      extraneous trace output.  */
3198   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3199     do_sll (SD_, RT, RD, SHIFT);
3200 }
3201
3202
3203 :function:::void:do_sllv:int rs, int rt, int rd
3204 {
3205   int s = MASKED (GPR[rs], 4, 0);
3206   unsigned32 temp = (GPR[rt] << s);
3207   TRACE_ALU_INPUT2 (GPR[rt], s);
3208   GPR[rd] = EXTEND32 (temp);
3209   TRACE_ALU_RESULT (GPR[rd]);
3210 }
3211
3212 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3213 "sllv r<RD>, r<RT>, r<RS>"
3214 *mipsI:
3215 *mipsII:
3216 *mipsIII:
3217 *mipsIV:
3218 *mipsV:
3219 *mips32:
3220 *mips32r2:
3221 *mips64:
3222 *mips64r2:
3223 *vr4100:
3224 *vr5000:
3225 *r3900:
3226 {
3227   do_sllv (SD_, RS, RT, RD);
3228 }
3229
3230
3231 :function:::void:do_slt:int rs, int rt, int rd
3232 {
3233   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3234   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3235   TRACE_ALU_RESULT (GPR[rd]);
3236 }
3237
3238 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3239 "slt r<RD>, r<RS>, r<RT>"
3240 *mipsI:
3241 *mipsII:
3242 *mipsIII:
3243 *mipsIV:
3244 *mipsV:
3245 *mips32:
3246 *mips32r2:
3247 *mips64:
3248 *mips64r2:
3249 *vr4100:
3250 *vr5000:
3251 *r3900:
3252 {
3253   do_slt (SD_, RS, RT, RD);
3254 }
3255
3256
3257 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3258 {
3259   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3260   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3261   TRACE_ALU_RESULT (GPR[rt]);
3262 }
3263
3264 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3265 "slti r<RT>, r<RS>, <IMMEDIATE>"
3266 *mipsI:
3267 *mipsII:
3268 *mipsIII:
3269 *mipsIV:
3270 *mipsV:
3271 *mips32:
3272 *mips32r2:
3273 *mips64:
3274 *mips64r2:
3275 *vr4100:
3276 *vr5000:
3277 *r3900:
3278 {
3279   do_slti (SD_, RS, RT, IMMEDIATE);
3280 }
3281
3282
3283 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3284 {
3285   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3286   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3287   TRACE_ALU_RESULT (GPR[rt]);
3288 }
3289
3290 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3291 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3292 *mipsI:
3293 *mipsII:
3294 *mipsIII:
3295 *mipsIV:
3296 *mipsV:
3297 *mips32:
3298 *mips32r2:
3299 *mips64:
3300 *mips64r2:
3301 *vr4100:
3302 *vr5000:
3303 *r3900:
3304 {
3305   do_sltiu (SD_, RS, RT, IMMEDIATE);
3306 }
3307
3308
3309
3310 :function:::void:do_sltu:int rs, int rt, int rd
3311 {
3312   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3313   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3314   TRACE_ALU_RESULT (GPR[rd]);
3315 }
3316
3317 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3318 "sltu r<RD>, r<RS>, r<RT>"
3319 *mipsI:
3320 *mipsII:
3321 *mipsIII:
3322 *mipsIV:
3323 *mipsV:
3324 *mips32:
3325 *mips32r2:
3326 *mips64:
3327 *mips64r2:
3328 *vr4100:
3329 *vr5000:
3330 *r3900:
3331 {
3332   do_sltu (SD_, RS, RT, RD);
3333 }
3334
3335
3336 :function:::void:do_sra:int rt, int rd, int shift
3337 {
3338   signed32 temp = (signed32) GPR[rt] >> shift;
3339   if (NotWordValue (GPR[rt]))
3340     Unpredictable ();
3341   TRACE_ALU_INPUT2 (GPR[rt], shift);
3342   GPR[rd] = EXTEND32 (temp);
3343   TRACE_ALU_RESULT (GPR[rd]);
3344 }
3345
3346 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3347 "sra r<RD>, r<RT>, <SHIFT>"
3348 *mipsI:
3349 *mipsII:
3350 *mipsIII:
3351 *mipsIV:
3352 *mipsV:
3353 *mips32:
3354 *mips32r2:
3355 *mips64:
3356 *mips64r2:
3357 *vr4100:
3358 *vr5000:
3359 *r3900:
3360 {
3361   do_sra (SD_, RT, RD, SHIFT);
3362 }
3363
3364
3365
3366 :function:::void:do_srav:int rs, int rt, int rd
3367 {
3368   int s = MASKED (GPR[rs], 4, 0);
3369   signed32 temp = (signed32) GPR[rt] >> s;
3370   if (NotWordValue (GPR[rt]))
3371     Unpredictable ();
3372   TRACE_ALU_INPUT2 (GPR[rt], s);
3373   GPR[rd] = EXTEND32 (temp);
3374   TRACE_ALU_RESULT (GPR[rd]);
3375 }
3376
3377 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3378 "srav r<RD>, r<RT>, r<RS>"
3379 *mipsI:
3380 *mipsII:
3381 *mipsIII:
3382 *mipsIV:
3383 *mipsV:
3384 *mips32:
3385 *mips32r2:
3386 *mips64:
3387 *mips64r2:
3388 *vr4100:
3389 *vr5000:
3390 *r3900:
3391 {
3392   do_srav (SD_, RS, RT, RD);
3393 }
3394
3395
3396
3397 :function:::void:do_srl:int rt, int rd, int shift
3398 {
3399   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3400   if (NotWordValue (GPR[rt]))
3401     Unpredictable ();
3402   TRACE_ALU_INPUT2 (GPR[rt], shift);
3403   GPR[rd] = EXTEND32 (temp);
3404   TRACE_ALU_RESULT (GPR[rd]);
3405 }
3406
3407 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3408 "srl r<RD>, r<RT>, <SHIFT>"
3409 *mipsI:
3410 *mipsII:
3411 *mipsIII:
3412 *mipsIV:
3413 *mipsV:
3414 *mips32:
3415 *mips32r2:
3416 *mips64:
3417 *mips64r2:
3418 *vr4100:
3419 *vr5000:
3420 *r3900:
3421 {
3422   do_srl (SD_, RT, RD, SHIFT);
3423 }
3424
3425
3426 :function:::void:do_srlv:int rs, int rt, int rd
3427 {
3428   int s = MASKED (GPR[rs], 4, 0);
3429   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3430   if (NotWordValue (GPR[rt]))
3431     Unpredictable ();
3432   TRACE_ALU_INPUT2 (GPR[rt], s);
3433   GPR[rd] = EXTEND32 (temp);
3434   TRACE_ALU_RESULT (GPR[rd]);
3435 }
3436
3437 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3438 "srlv r<RD>, r<RT>, r<RS>"
3439 *mipsI:
3440 *mipsII:
3441 *mipsIII:
3442 *mipsIV:
3443 *mipsV:
3444 *mips32:
3445 *mips32r2:
3446 *mips64:
3447 *mips64r2:
3448 *vr4100:
3449 *vr5000:
3450 *r3900:
3451 {
3452   do_srlv (SD_, RS, RT, RD);
3453 }
3454
3455
3456 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3457 "sub r<RD>, r<RS>, r<RT>"
3458 *mipsI:
3459 *mipsII:
3460 *mipsIII:
3461 *mipsIV:
3462 *mipsV:
3463 *mips32:
3464 *mips32r2:
3465 *mips64:
3466 *mips64r2:
3467 *vr4100:
3468 *vr5000:
3469 *r3900:
3470 {
3471   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3472     Unpredictable ();
3473   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3474   {
3475     ALU32_BEGIN (GPR[RS]);
3476     ALU32_SUB (GPR[RT]);
3477     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3478   }
3479   TRACE_ALU_RESULT (GPR[RD]);
3480 }
3481
3482
3483 :function:::void:do_subu:int rs, int rt, int rd
3484 {
3485   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3486     Unpredictable ();
3487   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3488   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3489   TRACE_ALU_RESULT (GPR[rd]);
3490 }
3491
3492 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3493 "subu r<RD>, r<RS>, r<RT>"
3494 *mipsI:
3495 *mipsII:
3496 *mipsIII:
3497 *mipsIV:
3498 *mipsV:
3499 *mips32:
3500 *mips32r2:
3501 *mips64:
3502 *mips64r2:
3503 *vr4100:
3504 *vr5000:
3505 *r3900:
3506 {
3507   do_subu (SD_, RS, RT, RD);
3508 }
3509
3510
3511 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3512 "sw r<RT>, <OFFSET>(r<BASE>)"
3513 *mipsI:
3514 *mipsII:
3515 *mipsIII:
3516 *mipsIV:
3517 *mipsV:
3518 *mips32:
3519 *mips32r2:
3520 *mips64:
3521 *mips64r2:
3522 *vr4100:
3523 *r3900:
3524 *vr5000:
3525 {
3526   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3527 }
3528
3529
3530 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3531 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3532 *mipsI:
3533 *mipsII:
3534 *mipsIII:
3535 *mipsIV:
3536 *mipsV:
3537 *mips32:
3538 *mips32r2:
3539 *mips64:
3540 *mips64r2:
3541 *vr4100:
3542 *vr5000:
3543 *r3900:
3544 {
3545   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3546 }
3547
3548
3549 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3550 "swl r<RT>, <OFFSET>(r<BASE>)"
3551 *mipsI:
3552 *mipsII:
3553 *mipsIII:
3554 *mipsIV:
3555 *mipsV:
3556 *mips32:
3557 *mips32r2:
3558 *mips64:
3559 *mips64r2:
3560 *vr4100:
3561 *vr5000:
3562 *r3900:
3563 {
3564   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3565 }
3566
3567
3568 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3569 "swr r<RT>, <OFFSET>(r<BASE>)"
3570 *mipsI:
3571 *mipsII:
3572 *mipsIII:
3573 *mipsIV:
3574 *mipsV:
3575 *mips32:
3576 *mips32r2:
3577 *mips64:
3578 *mips64r2:
3579 *vr4100:
3580 *vr5000:
3581 *r3900:
3582 {
3583   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3584 }
3585
3586
3587 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3588 "sync":STYPE == 0
3589 "sync <STYPE>"
3590 *mipsII:
3591 *mipsIII:
3592 *mipsIV:
3593 *mipsV:
3594 *mips32:
3595 *mips32r2:
3596 *mips64:
3597 *mips64r2:
3598 *vr4100:
3599 *vr5000:
3600 *r3900:
3601 {
3602   SyncOperation (STYPE);
3603 }
3604
3605
3606 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3607 "syscall %#lx<CODE>"
3608 *mipsI:
3609 *mipsII:
3610 *mipsIII:
3611 *mipsIV:
3612 *mipsV:
3613 *mips32:
3614 *mips32r2:
3615 *mips64:
3616 *mips64r2:
3617 *vr4100:
3618 *vr5000:
3619 *r3900:
3620 {
3621   SignalException (SystemCall, instruction_0);
3622 }
3623
3624
3625 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3626 "teq r<RS>, r<RT>"
3627 *mipsII:
3628 *mipsIII:
3629 *mipsIV:
3630 *mipsV:
3631 *mips32:
3632 *mips32r2:
3633 *mips64:
3634 *mips64r2:
3635 *vr4100:
3636 *vr5000:
3637 {
3638   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3639     SignalException (Trap, instruction_0);
3640 }
3641
3642
3643 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3644 "teqi r<RS>, <IMMEDIATE>"
3645 *mipsII:
3646 *mipsIII:
3647 *mipsIV:
3648 *mipsV:
3649 *mips32:
3650 *mips32r2:
3651 *mips64:
3652 *mips64r2:
3653 *vr4100:
3654 *vr5000:
3655 {
3656   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3657     SignalException (Trap, instruction_0);
3658 }
3659
3660
3661 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3662 "tge r<RS>, r<RT>"
3663 *mipsII:
3664 *mipsIII:
3665 *mipsIV:
3666 *mipsV:
3667 *mips32:
3668 *mips32r2:
3669 *mips64:
3670 *mips64r2:
3671 *vr4100:
3672 *vr5000:
3673 {
3674   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3675     SignalException (Trap, instruction_0);
3676 }
3677
3678
3679 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3680 "tgei r<RS>, <IMMEDIATE>"
3681 *mipsII:
3682 *mipsIII:
3683 *mipsIV:
3684 *mipsV:
3685 *mips32:
3686 *mips32r2:
3687 *mips64:
3688 *mips64r2:
3689 *vr4100:
3690 *vr5000:
3691 {
3692   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3693     SignalException (Trap, instruction_0);
3694 }
3695
3696
3697 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3698 "tgeiu r<RS>, <IMMEDIATE>"
3699 *mipsII:
3700 *mipsIII:
3701 *mipsIV:
3702 *mipsV:
3703 *mips32:
3704 *mips32r2:
3705 *mips64:
3706 *mips64r2:
3707 *vr4100:
3708 *vr5000:
3709 {
3710   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3711     SignalException (Trap, instruction_0);
3712 }
3713
3714
3715 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3716 "tgeu r<RS>, r<RT>"
3717 *mipsII:
3718 *mipsIII:
3719 *mipsIV:
3720 *mipsV:
3721 *mips32:
3722 *mips32r2:
3723 *mips64:
3724 *mips64r2:
3725 *vr4100:
3726 *vr5000:
3727 {
3728   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3729     SignalException (Trap, instruction_0);
3730 }
3731
3732
3733 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3734 "tlt r<RS>, r<RT>"
3735 *mipsII:
3736 *mipsIII:
3737 *mipsIV:
3738 *mipsV:
3739 *mips32:
3740 *mips32r2:
3741 *mips64:
3742 *mips64r2:
3743 *vr4100:
3744 *vr5000:
3745 {
3746   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3747     SignalException (Trap, instruction_0);
3748 }
3749
3750
3751 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3752 "tlti r<RS>, <IMMEDIATE>"
3753 *mipsII:
3754 *mipsIII:
3755 *mipsIV:
3756 *mipsV:
3757 *mips32:
3758 *mips32r2:
3759 *mips64:
3760 *mips64r2:
3761 *vr4100:
3762 *vr5000:
3763 {
3764   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3765     SignalException (Trap, instruction_0);
3766 }
3767
3768
3769 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3770 "tltiu r<RS>, <IMMEDIATE>"
3771 *mipsII:
3772 *mipsIII:
3773 *mipsIV:
3774 *mipsV:
3775 *mips32:
3776 *mips32r2:
3777 *mips64:
3778 *mips64r2:
3779 *vr4100:
3780 *vr5000:
3781 {
3782   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3783     SignalException (Trap, instruction_0);
3784 }
3785
3786
3787 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3788 "tltu r<RS>, r<RT>"
3789 *mipsII:
3790 *mipsIII:
3791 *mipsIV:
3792 *mipsV:
3793 *mips32:
3794 *mips32r2:
3795 *mips64:
3796 *mips64r2:
3797 *vr4100:
3798 *vr5000:
3799 {
3800   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3801     SignalException (Trap, instruction_0);
3802 }
3803
3804
3805 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3806 "tne r<RS>, r<RT>"
3807 *mipsII:
3808 *mipsIII:
3809 *mipsIV:
3810 *mipsV:
3811 *mips32:
3812 *mips32r2:
3813 *mips64:
3814 *mips64r2:
3815 *vr4100:
3816 *vr5000:
3817 {
3818   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3819     SignalException (Trap, instruction_0);
3820 }
3821
3822
3823 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3824 "tnei r<RS>, <IMMEDIATE>"
3825 *mipsII:
3826 *mipsIII:
3827 *mipsIV:
3828 *mipsV:
3829 *mips32:
3830 *mips32r2:
3831 *mips64:
3832 *mips64r2:
3833 *vr4100:
3834 *vr5000:
3835 {
3836   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3837     SignalException (Trap, instruction_0);
3838 }
3839
3840
3841 :function:::void:do_xor:int rs, int rt, int rd
3842 {
3843   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3844   GPR[rd] = GPR[rs] ^ GPR[rt];
3845   TRACE_ALU_RESULT (GPR[rd]);
3846 }
3847
3848 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3849 "xor r<RD>, r<RS>, r<RT>"
3850 *mipsI:
3851 *mipsII:
3852 *mipsIII:
3853 *mipsIV:
3854 *mipsV:
3855 *mips32:
3856 *mips32r2:
3857 *mips64:
3858 *mips64r2:
3859 *vr4100:
3860 *vr5000:
3861 *r3900:
3862 {
3863   do_xor (SD_, RS, RT, RD);
3864 }
3865
3866
3867 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3868 {
3869   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3870   GPR[rt] = GPR[rs] ^ immediate;
3871   TRACE_ALU_RESULT (GPR[rt]);
3872 }
3873
3874 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3875 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3876 *mipsI:
3877 *mipsII:
3878 *mipsIII:
3879 *mipsIV:
3880 *mipsV:
3881 *mips32:
3882 *mips32r2:
3883 *mips64:
3884 *mips64r2:
3885 *vr4100:
3886 *vr5000:
3887 *r3900:
3888 {
3889   do_xori (SD_, RS, RT, IMMEDIATE);
3890 }
3891
3892 \f
3893 //
3894 // MIPS Architecture:
3895 //
3896 //        FPU Instruction Set (COP1 & COP1X)
3897 //
3898
3899
3900 :%s::::FMT:int fmt
3901 {
3902   switch (fmt)
3903     {
3904     case fmt_single: return "s";
3905     case fmt_double: return "d";
3906     case fmt_word: return "w";
3907     case fmt_long: return "l";
3908     case fmt_ps: return "ps";
3909     default: return "?";
3910     }
3911 }
3912
3913 :%s::::TF:int tf
3914 {
3915   if (tf)
3916     return "t";
3917   else
3918     return "f";
3919 }
3920
3921 :%s::::ND:int nd
3922 {
3923   if (nd)
3924     return "l";
3925   else
3926     return "";
3927 }
3928
3929 :%s::::COND:int cond
3930 {
3931   switch (cond)
3932     {
3933     case 00: return "f";
3934     case 01: return "un";
3935     case 02: return "eq";
3936     case 03: return "ueq";
3937     case 04: return "olt";
3938     case 05: return "ult";
3939     case 06: return "ole";
3940     case 07: return "ule";
3941     case 010: return "sf";
3942     case 011: return "ngle";
3943     case 012: return "seq";
3944     case 013: return "ngl";
3945     case 014: return "lt";
3946     case 015: return "nge";
3947     case 016: return "le";
3948     case 017: return "ngt";
3949     default: return "?";
3950     }
3951 }
3952
3953
3954 // Helpers:
3955 //
3956 // Check that the given FPU format is usable, and signal a
3957 // ReservedInstruction exception if not.
3958 //
3959
3960 // check_fmt_p checks that the format is single, double, or paired single.
3961 :function:::void:check_fmt_p:int fmt, instruction_word insn
3962 *mipsI:
3963 *mipsII:
3964 *mipsIII:
3965 *mipsIV:
3966 *mips32:
3967 *mips32r2:
3968 *vr4100:
3969 *vr5000:
3970 *r3900:
3971 {
3972   /* None of these ISAs support Paired Single, so just fall back to
3973      the single/double check.  */
3974   if ((fmt != fmt_single) && (fmt != fmt_double))
3975     SignalException (ReservedInstruction, insn);
3976 }
3977
3978 :function:::void:check_fmt_p:int fmt, instruction_word insn
3979 *mipsV:
3980 *mips64:
3981 *mips64r2:
3982 {
3983   if ((fmt != fmt_single) && (fmt != fmt_double)
3984       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3985     SignalException (ReservedInstruction, insn);
3986 }
3987
3988
3989 // Helper:
3990 //
3991 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3992 // exception if not.
3993 //
3994
3995 :function:::void:check_fpu:
3996 *mipsI:
3997 *mipsII:
3998 *mipsIII:
3999 *mipsIV:
4000 *mipsV:
4001 *mips32:
4002 *mips32r2:
4003 *mips64:
4004 *mips64r2:
4005 *vr4100:
4006 *vr5000:
4007 *r3900:
4008 {
4009   if (! COP_Usable (1))
4010     SignalExceptionCoProcessorUnusable (1);
4011 }
4012
4013
4014 // Helper:
4015 //
4016 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4017 // or MIPS32.  do_load cannot be used instead because it returns an
4018 // unsigned_word, which is limited to the size of the machine's registers.
4019 //
4020
4021 :function:::unsigned64:do_load_double:address_word base, address_word offset
4022 *mipsII:
4023 *mips32:
4024 *mips32r2:
4025 {
4026   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4027   address_word vaddr;
4028   address_word paddr;
4029   int uncached;
4030   unsigned64 memval;
4031   unsigned64 v;
4032
4033   vaddr = loadstore_ea (SD_, base, offset);
4034   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4035     {
4036       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4037                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4038                        sim_core_unaligned_signal);
4039     }
4040   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4041                       isREAL);
4042   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4043               isDATA, isREAL);
4044   v = (unsigned64)memval;
4045   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4046               isDATA, isREAL);
4047   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4048 }
4049
4050
4051 // Helper:
4052 //
4053 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4054 // or MIPS32.  do_load cannot be used instead because it returns an
4055 // unsigned_word, which is limited to the size of the machine's registers.
4056 //
4057
4058 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4059 *mipsII:
4060 *mips32:
4061 *mips32r2:
4062 {
4063   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4064   address_word vaddr;
4065   address_word paddr;
4066   int uncached;
4067   unsigned64 memval;
4068
4069   vaddr = loadstore_ea (SD_, base, offset);
4070   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4071     {
4072       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4073                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4074                        sim_core_unaligned_signal);
4075     }
4076   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4077                       isREAL);
4078   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4079   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4080                isREAL);
4081   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4082   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4083                isREAL);
4084 }
4085
4086
4087 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4088 "abs.%s<FMT> f<FD>, f<FS>"
4089 *mipsI:
4090 *mipsII:
4091 *mipsIII:
4092 *mipsIV:
4093 *mipsV:
4094 *mips32:
4095 *mips32r2:
4096 *mips64:
4097 *mips64r2:
4098 *vr4100:
4099 *vr5000:
4100 *r3900:
4101 {
4102   int fmt = FMT;
4103   check_fpu (SD_);
4104   check_fmt_p (SD_, fmt, instruction_0);
4105   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4106 }
4107
4108
4109
4110 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4111 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4112 *mipsI:
4113 *mipsII:
4114 *mipsIII:
4115 *mipsIV:
4116 *mipsV:
4117 *mips32:
4118 *mips32r2:
4119 *mips64:
4120 *mips64r2:
4121 *vr4100:
4122 *vr5000:
4123 *r3900:
4124 {
4125   int fmt = FMT;
4126   check_fpu (SD_);
4127   check_fmt_p (SD_, fmt, instruction_0);
4128   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4129 }
4130
4131
4132 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4133 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4134 *mipsV:
4135 *mips64:
4136 *mips64r2:
4137 {
4138   unsigned64 fs;
4139   unsigned64 ft;
4140   unsigned64 fd;
4141   check_fpu (SD_);
4142   check_u64 (SD_, instruction_0);
4143   fs = ValueFPR (FS, fmt_ps);
4144   if ((GPR[RS] & 0x3) != 0)
4145     Unpredictable ();
4146   if ((GPR[RS] & 0x4) == 0)
4147     fd = fs;
4148   else
4149     {
4150       ft = ValueFPR (FT, fmt_ps);
4151       if (BigEndianCPU)
4152         fd = PackPS (PSLower (fs), PSUpper (ft));
4153       else
4154         fd = PackPS (PSLower (ft), PSUpper (fs));
4155     }
4156   StoreFPR (FD, fmt_ps, fd);
4157 }
4158
4159
4160 // BC1F
4161 // BC1FL
4162 // BC1T
4163 // BC1TL
4164
4165 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4166 "bc1%s<TF>%s<ND> <OFFSET>"
4167 *mipsI:
4168 *mipsII:
4169 *mipsIII:
4170 {
4171   check_fpu (SD_);
4172   TRACE_BRANCH_INPUT (PREVCOC1());
4173   if (PREVCOC1() == TF)
4174     {
4175       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4176       TRACE_BRANCH_RESULT (dest);
4177       DELAY_SLOT (dest);
4178     }
4179   else if (ND)
4180     {
4181       TRACE_BRANCH_RESULT (0);
4182       NULLIFY_NEXT_INSTRUCTION ();
4183     }
4184   else
4185     {
4186       TRACE_BRANCH_RESULT (NIA);
4187     }
4188 }
4189
4190 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4191 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4192 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4193 *mipsIV:
4194 *mipsV:
4195 *mips32:
4196 *mips32r2:
4197 *mips64:
4198 *mips64r2:
4199 #*vr4100:
4200 *vr5000:
4201 *r3900:
4202 {
4203   check_fpu (SD_);
4204   if (GETFCC(CC) == TF)
4205     {
4206       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4207       DELAY_SLOT (dest);
4208     }
4209   else if (ND)
4210     {
4211       NULLIFY_NEXT_INSTRUCTION ();
4212     }
4213 }
4214
4215
4216 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4217 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4218 *mipsI:
4219 *mipsII:
4220 *mipsIII:
4221 {
4222   int fmt = FMT;
4223   check_fpu (SD_);
4224   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4225   TRACE_ALU_RESULT (ValueFCR (31));
4226 }
4227
4228 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4229 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4230 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4231 *mipsIV:
4232 *mipsV:
4233 *mips32:
4234 *mips32r2:
4235 *mips64:
4236 *mips64r2:
4237 *vr4100:
4238 *vr5000:
4239 *r3900:
4240 {
4241   int fmt = FMT;
4242   check_fpu (SD_);
4243   check_fmt_p (SD_, fmt, instruction_0);
4244   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4245   TRACE_ALU_RESULT (ValueFCR (31));
4246 }
4247
4248
4249 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4250 "ceil.l.%s<FMT> f<FD>, f<FS>"
4251 *mipsIII:
4252 *mipsIV:
4253 *mipsV:
4254 *mips64:
4255 *mips64r2:
4256 *vr4100:
4257 *vr5000:
4258 *r3900:
4259 {
4260   int fmt = FMT;
4261   check_fpu (SD_);
4262   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4263             fmt_long));
4264 }
4265
4266
4267 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4268 "ceil.w.%s<FMT> f<FD>, f<FS>"
4269 *mipsII:
4270 *mipsIII:
4271 *mipsIV:
4272 *mipsV:
4273 *mips32:
4274 *mips32r2:
4275 *mips64:
4276 *mips64r2:
4277 *vr4100:
4278 *vr5000:
4279 *r3900:
4280 {
4281   int fmt = FMT;
4282   check_fpu (SD_);
4283   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4284             fmt_word));
4285 }
4286
4287
4288 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4289 "cfc1 r<RT>, f<FS>"
4290 *mipsI:
4291 *mipsII:
4292 *mipsIII:
4293 {
4294   check_fpu (SD_);
4295   if (FS == 0)
4296     PENDING_FILL (RT, EXTEND32 (FCR0));
4297   else if (FS == 31)
4298     PENDING_FILL (RT, EXTEND32 (FCR31));
4299   /* else NOP */
4300 }
4301
4302 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4303 "cfc1 r<RT>, f<FS>"
4304 *mipsIV:
4305 *vr4100:
4306 *vr5000:
4307 *r3900:
4308 {
4309   check_fpu (SD_);
4310   if (FS == 0 || FS == 31)
4311     {
4312       unsigned_word  fcr = ValueFCR (FS);
4313       TRACE_ALU_INPUT1 (fcr);
4314       GPR[RT] = fcr;
4315     }
4316   /* else NOP */
4317   TRACE_ALU_RESULT (GPR[RT]);
4318 }
4319
4320 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4321 "cfc1 r<RT>, f<FS>"
4322 *mipsV:
4323 *mips32:
4324 *mips32r2:
4325 *mips64:
4326 *mips64r2:
4327 {
4328   check_fpu (SD_);
4329   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4330     {
4331       unsigned_word  fcr = ValueFCR (FS);
4332       TRACE_ALU_INPUT1 (fcr);
4333       GPR[RT] = fcr;
4334     }
4335   /* else NOP */
4336   TRACE_ALU_RESULT (GPR[RT]);
4337 }
4338
4339 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4340 "ctc1 r<RT>, f<FS>"
4341 *mipsI:
4342 *mipsII:
4343 *mipsIII:
4344 {
4345   check_fpu (SD_);
4346   if (FS == 31)
4347     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4348   /* else NOP */
4349 }
4350
4351 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4352 "ctc1 r<RT>, f<FS>"
4353 *mipsIV:
4354 *vr4100:
4355 *vr5000:
4356 *r3900:
4357 {
4358   check_fpu (SD_);
4359   TRACE_ALU_INPUT1 (GPR[RT]);
4360   if (FS == 31)
4361     StoreFCR (FS, GPR[RT]);
4362   /* else NOP */
4363 }
4364
4365 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4366 "ctc1 r<RT>, f<FS>"
4367 *mipsV:
4368 *mips32:
4369 *mips32r2:
4370 *mips64:
4371 *mips64r2:
4372 {
4373   check_fpu (SD_);
4374   TRACE_ALU_INPUT1 (GPR[RT]);
4375   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4376       StoreFCR (FS, GPR[RT]);
4377   /* else NOP */
4378 }
4379
4380
4381 //
4382 // FIXME: Does not correctly differentiate between mips*
4383 //
4384 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4385 "cvt.d.%s<FMT> f<FD>, f<FS>"
4386 *mipsI:
4387 *mipsII:
4388 *mipsIII:
4389 *mipsIV:
4390 *mipsV:
4391 *mips32:
4392 *mips32r2:
4393 *mips64:
4394 *mips64r2:
4395 *vr4100:
4396 *vr5000:
4397 *r3900:
4398 {
4399   int fmt = FMT;
4400   check_fpu (SD_);
4401   if ((fmt == fmt_double) | 0)
4402     SignalException (ReservedInstruction, instruction_0);
4403   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4404             fmt_double));
4405 }
4406
4407
4408 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4409 "cvt.l.%s<FMT> f<FD>, f<FS>"
4410 *mipsIII:
4411 *mipsIV:
4412 *mipsV:
4413 *mips64:
4414 *mips64r2:
4415 *vr4100:
4416 *vr5000:
4417 *r3900:
4418 {
4419   int fmt = FMT;
4420   check_fpu (SD_);
4421   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4422     SignalException (ReservedInstruction, instruction_0);
4423   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4424             fmt_long));
4425 }
4426
4427
4428 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4429 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4430 *mipsV:
4431 *mips64:
4432 *mips64r2:
4433 {
4434   check_fpu (SD_);
4435   check_u64 (SD_, instruction_0);
4436   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4437                                 ValueFPR (FT, fmt_single)));
4438 }
4439
4440
4441 //
4442 // FIXME: Does not correctly differentiate between mips*
4443 //
4444 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4445 "cvt.s.%s<FMT> f<FD>, f<FS>"
4446 *mipsI:
4447 *mipsII:
4448 *mipsIII:
4449 *mipsIV:
4450 *mipsV:
4451 *mips32:
4452 *mips32r2:
4453 *mips64:
4454 *mips64r2:
4455 *vr4100:
4456 *vr5000:
4457 *r3900:
4458 {
4459   int fmt = FMT;
4460   check_fpu (SD_);
4461   if ((fmt == fmt_single) | 0)
4462     SignalException (ReservedInstruction, instruction_0);
4463   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4464             fmt_single));
4465 }
4466
4467
4468 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4469 "cvt.s.pl f<FD>, f<FS>"
4470 *mipsV:
4471 *mips64:
4472 *mips64r2:
4473 {
4474   check_fpu (SD_);
4475   check_u64 (SD_, instruction_0);
4476   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4477 }
4478
4479
4480 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4481 "cvt.s.pu f<FD>, f<FS>"
4482 *mipsV:
4483 *mips64:
4484 *mips64r2:
4485 {
4486   check_fpu (SD_);
4487   check_u64 (SD_, instruction_0);
4488   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4489 }
4490
4491
4492 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4493 "cvt.w.%s<FMT> f<FD>, f<FS>"
4494 *mipsI:
4495 *mipsII:
4496 *mipsIII:
4497 *mipsIV:
4498 *mipsV:
4499 *mips32:
4500 *mips32r2:
4501 *mips64:
4502 *mips64r2:
4503 *vr4100:
4504 *vr5000:
4505 *r3900:
4506 {
4507   int fmt = FMT;
4508   check_fpu (SD_);
4509   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4510     SignalException (ReservedInstruction, instruction_0);
4511   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4512             fmt_word));
4513 }
4514
4515
4516 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4517 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4518 *mipsI:
4519 *mipsII:
4520 *mipsIII:
4521 *mipsIV:
4522 *mipsV:
4523 *mips32:
4524 *mips32r2:
4525 *mips64:
4526 *mips64r2:
4527 *vr4100:
4528 *vr5000:
4529 *r3900:
4530 {
4531   int fmt = FMT;
4532   check_fpu (SD_);
4533   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4534 }
4535
4536
4537 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4538 "dmfc1 r<RT>, f<FS>"
4539 *mipsIII:
4540 {
4541   unsigned64 v;
4542   check_fpu (SD_);
4543   check_u64 (SD_, instruction_0);
4544   if (SizeFGR () == 64)
4545     v = FGR[FS];
4546   else if ((FS & 0x1) == 0)
4547     v = SET64HI (FGR[FS+1]) | FGR[FS];
4548   else
4549     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4550   PENDING_FILL (RT, v);
4551   TRACE_ALU_RESULT (v);
4552 }
4553
4554 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4555 "dmfc1 r<RT>, f<FS>"
4556 *mipsIV:
4557 *mipsV:
4558 *mips64:
4559 *mips64r2:
4560 *vr4100:
4561 *vr5000:
4562 *r3900:
4563 {
4564   check_fpu (SD_);
4565   check_u64 (SD_, instruction_0);
4566   if (SizeFGR () == 64)
4567     GPR[RT] = FGR[FS];
4568   else if ((FS & 0x1) == 0)
4569     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4570   else
4571     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4572   TRACE_ALU_RESULT (GPR[RT]);
4573 }
4574
4575
4576 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4577 "dmtc1 r<RT>, f<FS>"
4578 *mipsIII:
4579 {
4580   unsigned64 v;
4581   check_fpu (SD_);
4582   check_u64 (SD_, instruction_0);
4583   if (SizeFGR () == 64)
4584     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4585   else if ((FS & 0x1) == 0)
4586     {
4587       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4588       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4589     }
4590   else
4591     Unpredictable ();
4592   TRACE_FP_RESULT (GPR[RT]);
4593 }
4594
4595 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4596 "dmtc1 r<RT>, f<FS>"
4597 *mipsIV:
4598 *mipsV:
4599 *mips64:
4600 *mips64r2:
4601 *vr4100:
4602 *vr5000:
4603 *r3900:
4604 {
4605   check_fpu (SD_);
4606   check_u64 (SD_, instruction_0);
4607   if (SizeFGR () == 64)
4608     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4609   else if ((FS & 0x1) == 0)
4610     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4611   else
4612     Unpredictable ();
4613 }
4614
4615
4616 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4617 "floor.l.%s<FMT> f<FD>, f<FS>"
4618 *mipsIII:
4619 *mipsIV:
4620 *mipsV:
4621 *mips64:
4622 *mips64r2:
4623 *vr4100:
4624 *vr5000:
4625 *r3900:
4626 {
4627   int fmt = FMT;
4628   check_fpu (SD_);
4629   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4630             fmt_long));
4631 }
4632
4633
4634 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4635 "floor.w.%s<FMT> f<FD>, f<FS>"
4636 *mipsII:
4637 *mipsIII:
4638 *mipsIV:
4639 *mipsV:
4640 *mips32:
4641 *mips32r2:
4642 *mips64:
4643 *mips64r2:
4644 *vr4100:
4645 *vr5000:
4646 *r3900:
4647 {
4648   int fmt = FMT;
4649   check_fpu (SD_);
4650   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4651             fmt_word));
4652 }
4653
4654
4655 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4656 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4657 *mipsII:
4658 *mips32:
4659 *mips32r2:
4660 {
4661   check_fpu (SD_);
4662   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4663 }
4664
4665
4666 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4667 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4668 *mipsIII:
4669 *mipsIV:
4670 *mipsV:
4671 *mips64:
4672 *mips64r2:
4673 *vr4100:
4674 *vr5000:
4675 *r3900:
4676 {
4677   check_fpu (SD_);
4678   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4679 }
4680
4681
4682 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4683 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4684 *mipsIV:
4685 *mipsV:
4686 *mips64:
4687 *mips64r2:
4688 *vr5000:
4689 {
4690   check_fpu (SD_);
4691   check_u64 (SD_, instruction_0);
4692   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4693 }
4694
4695
4696 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4697 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4698 *mipsV:
4699 *mips64:
4700 *mips64r2:
4701 {
4702   address_word base = GPR[BASE];
4703   address_word index = GPR[INDEX];
4704   address_word vaddr = base + index;
4705   check_fpu (SD_);
4706   check_u64 (SD_, instruction_0);
4707   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4708   if ((vaddr & 0x7) != 0)
4709     index -= (vaddr & 0x7);
4710   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4711 }
4712
4713
4714 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4715 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4716 *mipsI:
4717 *mipsII:
4718 *mipsIII:
4719 *mipsIV:
4720 *mipsV:
4721 *mips32:
4722 *mips32r2:
4723 *mips64:
4724 *mips64r2:
4725 *vr4100:
4726 *vr5000:
4727 *r3900:
4728 {
4729   check_fpu (SD_);
4730   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4731 }
4732
4733
4734 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4735 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4736 *mipsIV:
4737 *mipsV:
4738 *mips64:
4739 *mips64r2:
4740 *vr5000:
4741 {
4742   check_fpu (SD_);
4743   check_u64 (SD_, instruction_0);
4744   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4745 }
4746
4747
4748
4749 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4750 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4751 *mipsIV:
4752 *mipsV:
4753 *mips64:
4754 *mips64r2:
4755 *vr5000:
4756 {
4757   int fmt = FMT;
4758   check_fpu (SD_);
4759   check_u64 (SD_, instruction_0);
4760   check_fmt_p (SD_, fmt, instruction_0);
4761   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4762                                   ValueFPR (FR, fmt), fmt));
4763 }
4764
4765
4766 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4767 "mfc1 r<RT>, f<FS>"
4768 *mipsI:
4769 *mipsII:
4770 *mipsIII:
4771 {
4772   unsigned64 v;
4773   check_fpu (SD_);
4774   v = EXTEND32 (FGR[FS]);
4775   PENDING_FILL (RT, v);
4776   TRACE_ALU_RESULT (v);
4777 }
4778
4779 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4780 "mfc1 r<RT>, f<FS>"
4781 *mipsIV:
4782 *mipsV:
4783 *mips32:
4784 *mips32r2:
4785 *mips64:
4786 *mips64r2:
4787 *vr4100:
4788 *vr5000:
4789 *r3900:
4790 {
4791   check_fpu (SD_);
4792   GPR[RT] = EXTEND32 (FGR[FS]);
4793   TRACE_ALU_RESULT (GPR[RT]);
4794 }
4795
4796
4797 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4798 "mov.%s<FMT> f<FD>, f<FS>"
4799 *mipsI:
4800 *mipsII:
4801 *mipsIII:
4802 *mipsIV:
4803 *mipsV:
4804 *mips32:
4805 *mips32r2:
4806 *mips64:
4807 *mips64r2:
4808 *vr4100:
4809 *vr5000:
4810 *r3900:
4811 {
4812   int fmt = FMT;
4813   check_fpu (SD_);
4814   check_fmt_p (SD_, fmt, instruction_0);
4815   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4816 }
4817
4818
4819 // MOVF
4820 // MOVT
4821 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4822 "mov%s<TF> r<RD>, r<RS>, <CC>"
4823 *mipsIV:
4824 *mipsV:
4825 *mips32:
4826 *mips32r2:
4827 *mips64:
4828 *mips64r2:
4829 *vr5000:
4830 {
4831   check_fpu (SD_);
4832   if (GETFCC(CC) == TF)
4833     GPR[RD] = GPR[RS];
4834 }
4835
4836
4837 // MOVF.fmt
4838 // MOVT.fmt
4839 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4840 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4841 *mipsIV:
4842 *mipsV:
4843 *mips32:
4844 *mips32r2:
4845 *mips64:
4846 *mips64r2:
4847 *vr5000:
4848 {
4849   int fmt = FMT;
4850   check_fpu (SD_);
4851   if (fmt != fmt_ps)
4852     {
4853       if (GETFCC(CC) == TF)
4854         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4855       else
4856         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4857     }
4858   else
4859     {
4860       unsigned64 fd;
4861       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4862                                       fmt_ps)),
4863                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4864                                       fmt_ps)));
4865       StoreFPR (FD, fmt_ps, fd);
4866     }
4867 }
4868
4869
4870 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4871 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4872 *mipsIV:
4873 *mipsV:
4874 *mips32:
4875 *mips32r2:
4876 *mips64:
4877 *mips64r2:
4878 *vr5000:
4879 {
4880   check_fpu (SD_);
4881   if (GPR[RT] != 0)
4882     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4883   else
4884     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4885 }
4886
4887
4888 // MOVT see MOVtf
4889
4890
4891 // MOVT.fmt see MOVtf.fmt
4892
4893
4894
4895 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4896 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4897 *mipsIV:
4898 *mipsV:
4899 *mips32:
4900 *mips32r2:
4901 *mips64:
4902 *mips64r2:
4903 *vr5000:
4904 {
4905   check_fpu (SD_);
4906   if (GPR[RT] == 0)
4907     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4908   else
4909     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4910 }
4911
4912
4913 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4914 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4915 *mipsIV:
4916 *mipsV:
4917 *mips64:
4918 *mips64r2:
4919 *vr5000:
4920 {
4921   int fmt = FMT;
4922   check_fpu (SD_);
4923   check_u64 (SD_, instruction_0);
4924   check_fmt_p (SD_, fmt, instruction_0);
4925   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4926                                   ValueFPR (FR, fmt), fmt));
4927 }
4928
4929
4930 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4931 "mtc1 r<RT>, f<FS>"
4932 *mipsI:
4933 *mipsII:
4934 *mipsIII:
4935 {
4936   check_fpu (SD_);
4937   if (SizeFGR () == 64)
4938     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4939   else
4940     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4941   TRACE_FP_RESULT (GPR[RT]);
4942 }
4943
4944 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4945 "mtc1 r<RT>, f<FS>"
4946 *mipsIV:
4947 *mipsV:
4948 *mips32:
4949 *mips32r2:
4950 *mips64:
4951 *mips64r2:
4952 *vr4100:
4953 *vr5000:
4954 *r3900:
4955 {
4956   check_fpu (SD_);
4957   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4958 }
4959
4960
4961 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4962 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4963 *mipsI:
4964 *mipsII:
4965 *mipsIII:
4966 *mipsIV:
4967 *mipsV:
4968 *mips32:
4969 *mips32r2:
4970 *mips64:
4971 *mips64r2:
4972 *vr4100:
4973 *vr5000:
4974 *r3900:
4975 {
4976   int fmt = FMT;
4977   check_fpu (SD_);
4978   check_fmt_p (SD_, fmt, instruction_0);
4979   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4980 }
4981
4982
4983 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4984 "neg.%s<FMT> f<FD>, f<FS>"
4985 *mipsI:
4986 *mipsII:
4987 *mipsIII:
4988 *mipsIV:
4989 *mipsV:
4990 *mips32:
4991 *mips32r2:
4992 *mips64:
4993 *mips64r2:
4994 *vr4100:
4995 *vr5000:
4996 *r3900:
4997 {
4998   int fmt = FMT;
4999   check_fpu (SD_);
5000   check_fmt_p (SD_, fmt, instruction_0);
5001   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
5002 }
5003
5004
5005 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
5006 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5007 *mipsIV:
5008 *mipsV:
5009 *mips64:
5010 *mips64r2:
5011 *vr5000:
5012 {
5013   int fmt = FMT;
5014   check_fpu (SD_);
5015   check_u64 (SD_, instruction_0);
5016   check_fmt_p (SD_, fmt, instruction_0);
5017   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5018                                      ValueFPR (FR, fmt), fmt));
5019 }
5020
5021
5022 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5023 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5024 *mipsIV:
5025 *mipsV:
5026 *mips64:
5027 *mips64r2:
5028 *vr5000:
5029 {
5030   int fmt = FMT;
5031   check_fpu (SD_);
5032   check_u64 (SD_, instruction_0);
5033   check_fmt_p (SD_, fmt, instruction_0);
5034   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5035                                      ValueFPR (FR, fmt), fmt));
5036 }
5037
5038
5039 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5040 "pll.ps f<FD>, f<FS>, f<FT>"
5041 *mipsV:
5042 *mips64:
5043 *mips64r2:
5044 {
5045   check_fpu (SD_);
5046   check_u64 (SD_, instruction_0);
5047   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5048                                 PSLower (ValueFPR (FT, fmt_ps))));
5049 }
5050
5051
5052 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5053 "plu.ps f<FD>, f<FS>, f<FT>"
5054 *mipsV:
5055 *mips64:
5056 *mips64r2:
5057 {
5058   check_fpu (SD_);
5059   check_u64 (SD_, instruction_0);
5060   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5061                                 PSUpper (ValueFPR (FT, fmt_ps))));
5062 }
5063
5064
5065 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5066 "prefx <HINT>, r<INDEX>(r<BASE>)"
5067 *mipsIV:
5068 *mipsV:
5069 *mips64:
5070 *mips64r2:
5071 *vr5000:
5072 {
5073   address_word base = GPR[BASE];
5074   address_word index = GPR[INDEX];
5075   {
5076     address_word vaddr = loadstore_ea (SD_, base, index);
5077     address_word paddr;
5078     int uncached;
5079     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5080       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5081   }
5082 }
5083
5084
5085 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5086 "pul.ps f<FD>, f<FS>, f<FT>"
5087 *mipsV:
5088 *mips64:
5089 *mips64r2:
5090 {
5091   check_fpu (SD_);
5092   check_u64 (SD_, instruction_0);
5093   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5094                                 PSLower (ValueFPR (FT, fmt_ps))));
5095 }
5096
5097
5098 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5099 "puu.ps f<FD>, f<FS>, f<FT>"
5100 *mipsV:
5101 *mips64:
5102 *mips64r2:
5103 {
5104   check_fpu (SD_);
5105   check_u64 (SD_, instruction_0);
5106   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5107                                 PSUpper (ValueFPR (FT, fmt_ps))));
5108 }
5109
5110
5111 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5112 "recip.%s<FMT> f<FD>, f<FS>"
5113 *mipsIV:
5114 *mipsV:
5115 *mips64:
5116 *mips64r2:
5117 *vr5000:
5118 {
5119   int fmt = FMT;
5120   check_fpu (SD_);
5121   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5122 }
5123
5124
5125 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5126 "round.l.%s<FMT> f<FD>, f<FS>"
5127 *mipsIII:
5128 *mipsIV:
5129 *mipsV:
5130 *mips64:
5131 *mips64r2:
5132 *vr4100:
5133 *vr5000:
5134 *r3900:
5135 {
5136   int fmt = FMT;
5137   check_fpu (SD_);
5138   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5139             fmt_long));
5140 }
5141
5142
5143 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5144 "round.w.%s<FMT> f<FD>, f<FS>"
5145 *mipsII:
5146 *mipsIII:
5147 *mipsIV:
5148 *mipsV:
5149 *mips32:
5150 *mips32r2:
5151 *mips64:
5152 *mips64r2:
5153 *vr4100:
5154 *vr5000:
5155 *r3900:
5156 {
5157   int fmt = FMT;
5158   check_fpu (SD_);
5159   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5160             fmt_word));
5161 }
5162
5163
5164 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5165 "rsqrt.%s<FMT> f<FD>, f<FS>"
5166 *mipsIV:
5167 *mipsV:
5168 *mips64:
5169 *mips64r2:
5170 *vr5000:
5171 {
5172   int fmt = FMT;
5173   check_fpu (SD_);
5174   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5175 }
5176
5177
5178 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5179 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5180 *mipsII:
5181 *mips32:
5182 *mips32r2:
5183 {
5184   check_fpu (SD_);
5185   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5186 }
5187
5188
5189 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5190 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5191 *mipsIII:
5192 *mipsIV:
5193 *mipsV:
5194 *mips64:
5195 *mips64r2:
5196 *vr4100:
5197 *vr5000:
5198 *r3900:
5199 {
5200   check_fpu (SD_);
5201   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5202 }
5203
5204
5205 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5206 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5207 *mipsIV:
5208 *mipsV:
5209 *mips64:
5210 *mips64r2:
5211 *vr5000:
5212 {
5213   check_fpu (SD_);
5214   check_u64 (SD_, instruction_0);
5215   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5216 }
5217
5218
5219 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5220 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5221 *mipsV:
5222 *mips64:
5223 *mips64r2:
5224 {
5225   unsigned64 v;
5226   address_word base = GPR[BASE];
5227   address_word index = GPR[INDEX];
5228   address_word vaddr = base + index;
5229   check_fpu (SD_);
5230   check_u64 (SD_, instruction_0);
5231   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
5232   if ((vaddr & 0x7) != 0)
5233     index -= (vaddr & 0x7);
5234   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5235 }
5236
5237
5238 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5239 "sqrt.%s<FMT> f<FD>, f<FS>"
5240 *mipsII:
5241 *mipsIII:
5242 *mipsIV:
5243 *mipsV:
5244 *mips32:
5245 *mips32r2:
5246 *mips64:
5247 *mips64r2:
5248 *vr4100:
5249 *vr5000:
5250 *r3900:
5251 {
5252   int fmt = FMT;
5253   check_fpu (SD_);
5254   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
5255 }
5256
5257
5258 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5259 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5260 *mipsI:
5261 *mipsII:
5262 *mipsIII:
5263 *mipsIV:
5264 *mipsV:
5265 *mips32:
5266 *mips32r2:
5267 *mips64:
5268 *mips64r2:
5269 *vr4100:
5270 *vr5000:
5271 *r3900:
5272 {
5273   int fmt = FMT;
5274   check_fpu (SD_);
5275   check_fmt_p (SD_, fmt, instruction_0);
5276   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5277 }
5278
5279
5280
5281 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5282 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5283 *mipsI:
5284 *mipsII:
5285 *mipsIII:
5286 *mipsIV:
5287 *mipsV:
5288 *mips32:
5289 *mips32r2:
5290 *mips64:
5291 *mips64r2:
5292 *vr4100:
5293 *vr5000:
5294 *r3900:
5295 {
5296   address_word base = GPR[BASE];
5297   address_word offset = EXTEND16 (OFFSET);
5298   check_fpu (SD_);
5299   {
5300     address_word vaddr = loadstore_ea (SD_, base, offset);
5301     address_word paddr;
5302     int uncached;
5303     if ((vaddr & 3) != 0)
5304       {
5305         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5306       }
5307     else
5308       {
5309         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5310           {
5311             uword64 memval = 0;
5312             uword64 memval1 = 0;
5313             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5314             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5315             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5316             unsigned int byte;
5317             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5318             byte = ((vaddr & mask) ^ bigendiancpu);
5319             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5320             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5321           }
5322       }
5323   }
5324 }
5325
5326
5327 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5328 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5329 *mipsIV:
5330 *mipsV:
5331 *mips64:
5332 *mips64r2:
5333 *vr5000:
5334 {
5335
5336   address_word base = GPR[BASE];
5337   address_word index = GPR[INDEX];
5338   check_fpu (SD_);
5339   check_u64 (SD_, instruction_0);
5340   {
5341    address_word vaddr = loadstore_ea (SD_, base, index);
5342    address_word paddr;
5343    int uncached;
5344    if ((vaddr & 3) != 0)
5345      {
5346        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5347      }
5348    else
5349    {
5350     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5351     {
5352      unsigned64 memval = 0;
5353      unsigned64 memval1 = 0;
5354      unsigned64 mask = 0x7;
5355      unsigned int byte;
5356      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5357      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5358      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5359       {
5360        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5361       }
5362     }
5363    }
5364   }
5365 }
5366
5367
5368 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5369 "trunc.l.%s<FMT> f<FD>, f<FS>"
5370 *mipsIII:
5371 *mipsIV:
5372 *mipsV:
5373 *mips64:
5374 *mips64r2:
5375 *vr4100:
5376 *vr5000:
5377 *r3900:
5378 {
5379   int fmt = FMT;
5380   check_fpu (SD_);
5381   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5382             fmt_long));
5383 }
5384
5385
5386 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5387 "trunc.w.%s<FMT> f<FD>, f<FS>"
5388 *mipsII:
5389 *mipsIII:
5390 *mipsIV:
5391 *mipsV:
5392 *mips32:
5393 *mips32r2:
5394 *mips64:
5395 *mips64r2:
5396 *vr4100:
5397 *vr5000:
5398 *r3900:
5399 {
5400   int fmt = FMT;
5401   check_fpu (SD_);
5402   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5403             fmt_word));
5404 }
5405
5406 \f
5407 //
5408 // MIPS Architecture:
5409 //
5410 //        System Control Instruction Set (COP0)
5411 //
5412
5413
5414 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5415 "bc0f <OFFSET>"
5416 *mipsI:
5417 *mipsII:
5418 *mipsIII:
5419 *mipsIV:
5420 *mipsV:
5421 *mips32:
5422 *mips32r2:
5423 *mips64:
5424 *mips64r2:
5425 *vr4100:
5426 *vr5000:
5427
5428 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5429 "bc0f <OFFSET>"
5430 // stub needed for eCos as tx39 hardware bug workaround
5431 *r3900:
5432 {
5433   /* do nothing */
5434 }
5435
5436
5437 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5438 "bc0fl <OFFSET>"
5439 *mipsI:
5440 *mipsII:
5441 *mipsIII:
5442 *mipsIV:
5443 *mipsV:
5444 *mips32:
5445 *mips32r2:
5446 *mips64:
5447 *mips64r2:
5448 *vr4100:
5449 *vr5000:
5450
5451
5452 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5453 "bc0t <OFFSET>"
5454 *mipsI:
5455 *mipsII:
5456 *mipsIII:
5457 *mipsIV:
5458 *mipsV:
5459 *mips32:
5460 *mips32r2:
5461 *mips64:
5462 *mips64r2:
5463 *vr4100:
5464
5465
5466 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5467 "bc0tl <OFFSET>"
5468 *mipsI:
5469 *mipsII:
5470 *mipsIII:
5471 *mipsIV:
5472 *mipsV:
5473 *mips32:
5474 *mips32r2:
5475 *mips64:
5476 *mips64r2:
5477 *vr4100:
5478 *vr5000:
5479
5480
5481 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5482 "cache <OP>, <OFFSET>(r<BASE>)"
5483 *mipsIII:
5484 *mipsIV:
5485 *mipsV:
5486 *mips32:
5487 *mips32r2:
5488 *mips64:
5489 *mips64r2:
5490 *vr4100:
5491 *vr5000:
5492 *r3900:
5493 {
5494   address_word base = GPR[BASE];
5495   address_word offset = EXTEND16 (OFFSET);
5496   {
5497     address_word vaddr = loadstore_ea (SD_, base, offset);
5498     address_word paddr;
5499     int uncached;
5500     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5501       CacheOp(OP,vaddr,paddr,instruction_0);
5502   }
5503 }
5504
5505
5506 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5507 "dmfc0 r<RT>, r<RD>"
5508 *mipsIII:
5509 *mipsIV:
5510 *mipsV:
5511 *mips64:
5512 *mips64r2:
5513 {
5514   check_u64 (SD_, instruction_0);
5515   DecodeCoproc (instruction_0);
5516 }
5517
5518
5519 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5520 "dmtc0 r<RT>, r<RD>"
5521 *mipsIII:
5522 *mipsIV:
5523 *mipsV:
5524 *mips64:
5525 *mips64r2:
5526 {
5527   check_u64 (SD_, instruction_0);
5528   DecodeCoproc (instruction_0);
5529 }
5530
5531
5532 010000,1,0000000000000000000,011000:COP0:32::ERET
5533 "eret"
5534 *mipsIII:
5535 *mipsIV:
5536 *mipsV:
5537 *mips32:
5538 *mips32r2:
5539 *mips64:
5540 *mips64r2:
5541 *vr4100:
5542 *vr5000:
5543 {
5544   if (SR & status_ERL)
5545     {
5546       /* Oops, not yet available */
5547       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5548       NIA = EPC;
5549       SR &= ~status_ERL;
5550     }
5551   else
5552     {
5553       NIA = EPC;
5554       SR &= ~status_EXL;
5555     }
5556 }
5557
5558
5559 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5560 "mfc0 r<RT>, r<RD> # <REGX>"
5561 *mipsI:
5562 *mipsII:
5563 *mipsIII:
5564 *mipsIV:
5565 *mipsV:
5566 *mips32:
5567 *mips32r2:
5568 *mips64:
5569 *mips64r2:
5570 *vr4100:
5571 *vr5000:
5572 *r3900:
5573 {
5574   TRACE_ALU_INPUT0 ();
5575   DecodeCoproc (instruction_0);
5576   TRACE_ALU_RESULT (GPR[RT]);
5577 }
5578
5579 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5580 "mtc0 r<RT>, r<RD> # <REGX>"
5581 *mipsI:
5582 *mipsII:
5583 *mipsIII:
5584 *mipsIV:
5585 *mipsV:
5586 *mips32:
5587 *mips32r2:
5588 *mips64:
5589 *mips64r2:
5590 *vr4100:
5591 *vr5000:
5592 *r3900:
5593 {
5594   DecodeCoproc (instruction_0);
5595 }
5596
5597
5598 010000,1,0000000000000000000,010000:COP0:32::RFE
5599 "rfe"
5600 *mipsI:
5601 *mipsII:
5602 *mipsIII:
5603 *mipsIV:
5604 *mipsV:
5605 *vr4100:
5606 *vr5000:
5607 *r3900:
5608 {
5609   DecodeCoproc (instruction_0);
5610 }
5611
5612
5613 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5614 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5615 *mipsI:
5616 *mipsII:
5617 *mipsIII:
5618 *mipsIV:
5619 *mipsV:
5620 *mips32:
5621 *mips32r2:
5622 *mips64:
5623 *mips64r2:
5624 *vr4100:
5625 *r3900:
5626 {
5627   DecodeCoproc (instruction_0);
5628 }
5629
5630
5631
5632 010000,1,0000000000000000000,001000:COP0:32::TLBP
5633 "tlbp"
5634 *mipsI:
5635 *mipsII:
5636 *mipsIII:
5637 *mipsIV:
5638 *mipsV:
5639 *mips32:
5640 *mips32r2:
5641 *mips64:
5642 *mips64r2:
5643 *vr4100:
5644 *vr5000:
5645
5646
5647 010000,1,0000000000000000000,000001:COP0:32::TLBR
5648 "tlbr"
5649 *mipsI:
5650 *mipsII:
5651 *mipsIII:
5652 *mipsIV:
5653 *mipsV:
5654 *mips32:
5655 *mips32r2:
5656 *mips64:
5657 *mips64r2:
5658 *vr4100:
5659 *vr5000:
5660
5661
5662 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5663 "tlbwi"
5664 *mipsI:
5665 *mipsII:
5666 *mipsIII:
5667 *mipsIV:
5668 *mipsV:
5669 *mips32:
5670 *mips32r2:
5671 *mips64:
5672 *mips64r2:
5673 *vr4100:
5674 *vr5000:
5675
5676
5677 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5678 "tlbwr"
5679 *mipsI:
5680 *mipsII:
5681 *mipsIII:
5682 *mipsIV:
5683 *mipsV:
5684 *mips32:
5685 *mips32r2:
5686 *mips64:
5687 *mips64r2:
5688 *vr4100:
5689 *vr5000:
5690
5691
5692 :include:::mips3264r2.igen
5693 :include:::m16.igen
5694 :include:::m16e.igen
5695 :include:::mdmx.igen
5696 :include:::mips3d.igen
5697 :include:::sb1.igen
5698 :include:::tx.igen
5699 :include:::vr.igen
5700