sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator
  38 :model:::mipsI:mips3000:
  39 :model:::mipsII:mips6000:
  40 :model:::mipsIII:mips4000:
  41 :model:::mipsIV:mips8000:
  42 :model:::mips16:mips16:
  43 // start-sanitize-r5900
  44 :model:::r5900:mips5900:
  45 // end-sanitize-r5900
  46 :model:::r3900:mips3900:
  47 // start-sanitize-tx19
  48 :model:::tx19:tx19:
  49 // end-sanitize-tx19
  50 :model:::vr4100:mips4100:
  51 // start-sanitize-vr4xxx
  52 :model:::vr4121:mips4121:
  53 // end-sanitize-vr4xxx
  54 // start-sanitize-vr4320
  55 :model:::vr4320:mips4320:
  56 // end-sanitize-vr4320
  57 // start-sanitize-cygnus
  58 :model:::vr5400:mips5400:
  59 :model:::mdmx:mdmx:
  60 // end-sanitize-cygnus
  61 :model:::vr5000:mips5000:
  62
  63
  64
  65 // Pseudo instructions known by IGEN
  66 :internal::::illegal:
  67 {
  68   SignalException (ReservedInstruction, 0);
  69 }
  70
  71
  72 // Pseudo instructions known by interp.c
  73 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  74 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  75 "rsvd <OP>"
  76 {
  77   SignalException (ReservedInstruction, instruction_0);
  78 }
  79
  80
  81
  82 // Helper:
  83 //
  84 // Simulate a 32 bit delayslot instruction
  85 //
  86
  87 :function:::address_word:delayslot32:address_word target
  88 {
  89   instruction_word delay_insn;
  90   sim_events_slip (SD, 1);
  91   DSPC = CIA;
  92   CIA = CIA + 4; /* NOTE not mips16 */
  93   STATE |= simDELAYSLOT;
  94   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  95   idecode_issue (CPU_, delay_insn, (CIA));
  96   STATE &= ~simDELAYSLOT;
  97   return target;
  98 }
  99
 100 :function:::address_word:nullify_next_insn32:
 101 {
 102   sim_events_slip (SD, 1);
 103   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 104   return CIA + 8;
 105 }
 106
 107 // start-sanitize-branchbug4011
 108 :function:::void:check_4011_branch_bug:
 109 {
 110   if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
 111     sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
 112                       itable[MY_INDEX].name,
 113                       (long) CIA,
 114                       (long) BRANCHBUG4011_LAST_CIA);
 115 }
 116
 117 :function:::void:mark_4011_branch_bug:address_word target
 118 {
 119   if (BRANCHBUG4011_OPTION)
 120     {
 121       BRANCHBUG4011_OPTION = 2;
 122       BRANCHBUG4011_LAST_TARGET = target;
 123       BRANCHBUG4011_LAST_CIA = CIA;
 124     }
 125 }
 126
 127 // end-sanitize-branchbug4011
 128 // Helper:
 129 //
 130 // Check that an access to a HI/LO register meets timing requirements
 131 //
 132 // The following requirements exist:
 133 //
 134 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 135 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 136 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 137 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 138 //
 139
 140 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 141 {
 142   if (history->mf.timestamp + 3 > time)
 143     {
 144       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 145                         itable[MY_INDEX].name,
 146                         new, (long) CIA,
 147                         (long) history->mf.cia);
 148       return 0;
 149     }
 150   return 1;
 151 }
 152
 153 :function:::int:check_mt_hilo:hilo_history *history
 154 *mipsI,mipsII,mipsIII,mipsIV:
 155 *vr4100:
 156 *vr5000:
 157 // start-sanitize-vr4xxx
 158 *vr4121:
 159 // end-sanitize-vr4xxx
 160 // start-sanitize-vr4320
 161 *vr4320:
 162 // end-sanitize-vr4320
 163 // start-sanitize-cygnus
 164 *vr5400:
 165 // end-sanitize-cygnus
 166 {
 167   signed64 time = sim_events_time (SD);
 168   int ok = check_mf_cycles (SD_, history, time, "MT");
 169   history->mt.timestamp = time;
 170   history->mt.cia = CIA;
 171   return ok;
 172 }
 173
 174 :function:::int:check_mt_hilo:hilo_history *history
 175 *r3900:
 176 // start-sanitize-tx19
 177 *tx19:
 178 // end-sanitize-tx19
 179 // start-sanitize-r5900
 180 *r5900:
 181 // end-sanitize-r5900
 182 {
 183   signed64 time = sim_events_time (SD);
 184   history->mt.timestamp = time;
 185   history->mt.cia = CIA;
 186   return 1;
 187 }
 188
 189
 190 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 191 *mipsI,mipsII,mipsIII,mipsIV:
 192 *vr4100:
 193 *vr5000:
 194 // start-sanitize-vr4xxx
 195 *vr4121:
 196 // end-sanitize-vr4xxx
 197 // start-sanitize-vr4320
 198 *vr4320:
 199 // end-sanitize-vr4320
 200 // start-sanitize-cygnus
 201 *vr5400:
 202 // end-sanitize-cygnus
 203 *r3900:
 204 // start-sanitize-tx19
 205 *tx19:
 206 // end-sanitize-tx19
 207 {
 208   signed64 time = sim_events_time (SD);
 209   int ok = 1;
 210   if (peer != NULL
 211       && peer->mt.timestamp > history->op.timestamp
 212       && history->mt.timestamp < history->op.timestamp
 213       && ! (history->mf.timestamp > history->op.timestamp
 214             && history->mf.timestamp < peer->mt.timestamp)
 215       && ! (peer->mf.timestamp > history->op.timestamp
 216             && peer->mf.timestamp < peer->mt.timestamp))
 217     {
 218       /* The peer has been written to since the last OP yet we have
 219          not */
 220       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 221                         itable[MY_INDEX].name,
 222                         (long) CIA,
 223                         (long) history->op.cia,
 224                         (long) peer->mt.cia);
 225       ok = 0;
 226     }
 227   history->mf.timestamp = time;
 228   history->mf.cia = CIA;
 229   return ok;
 230 }
 231
 232 // start-sanitize-r5900
 233 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 234 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 235 // end-sanitize-r5900
 236 // start-sanitize-r5900
 237 *r5900:
 238 // end-sanitize-r5900
 239 // start-sanitize-r5900
 240 {
 241   /* FIXME: could record the fact that a stall occured if we want */
 242   signed64 time = sim_events_time (SD);
 243   history->mf.timestamp = time;
 244   history->mf.cia = CIA;
 245   return 1;
 246 }
 247 // end-sanitize-r5900
 248
 249
 250 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 251 *mipsI,mipsII,mipsIII,mipsIV:
 252 *vr4100:
 253 *vr5000:
 254 // start-sanitize-vr4xxx
 255 *vr4121:
 256 // end-sanitize-vr4xxx
 257 // start-sanitize-vr4320
 258 *vr4320:
 259 // end-sanitize-vr4320
 260 // start-sanitize-cygnus
 261 *vr5400:
 262 // end-sanitize-cygnus
 263 {
 264   signed64 time = sim_events_time (SD);
 265   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 266             && check_mf_cycles (SD_, lo, time, "OP"));
 267   hi->op.timestamp = time;
 268   lo->op.timestamp = time;
 269   hi->op.cia = CIA;
 270   lo->op.cia = CIA;
 271   return ok;
 272 }
 273
 274 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 275 // a mf{hi,lo}
 276 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 277 *r3900:
 278 // start-sanitize-tx19
 279 *tx19:
 280 // end-sanitize-tx19
 281 // start-sanitize-r5900
 282 *r5900:
 283 // end-sanitize-r5900
 284 {
 285   /* FIXME: could record the fact that a stall occured if we want */
 286   signed64 time = sim_events_time (SD);
 287   hi->op.timestamp = time;
 288   lo->op.timestamp = time;
 289   hi->op.cia = CIA;
 290   lo->op.cia = CIA;
 291   return 1;
 292 }
 293
 294
 295 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 296 *mipsI,mipsII,mipsIII,mipsIV:
 297 *vr4100:
 298 *vr5000:
 299 // start-sanitize-vr4xxx
 300 *vr4121:
 301 // end-sanitize-vr4xxx
 302 // start-sanitize-vr4320
 303 *vr4320:
 304 // end-sanitize-vr4320
 305 // start-sanitize-cygnus
 306 *vr5400:
 307 // end-sanitize-cygnus
 308 *r3900:
 309 // start-sanitize-tx19
 310 *tx19:
 311 // end-sanitize-tx19
 312 {
 313   signed64 time = sim_events_time (SD);
 314   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 315             && check_mf_cycles (SD_, lo, time, "OP"));
 316   hi->op.timestamp = time;
 317   lo->op.timestamp = time;
 318   hi->op.cia = CIA;
 319   lo->op.cia = CIA;
 320   return ok;
 321 }
 322
 323
 324 // start-sanitize-r5900
 325 // The r5900 div et.al insns _can_ be exectuted immediatly after
 326 // a mf{hi,lo}
 327 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 328 // end-sanitize-r5900
 329 // start-sanitize-r5900
 330 *r5900:
 331 // end-sanitize-r5900
 332 // start-sanitize-r5900
 333 {
 334   /* FIXME: could record the fact that a stall occured if we want */
 335   signed64 time = sim_events_time (SD);
 336   hi->op.timestamp = time;
 337   lo->op.timestamp = time;
 338   hi->op.cia = CIA;
 339   lo->op.cia = CIA;
 340   return 1;
 341 }
 342 // end-sanitize-r5900
 343
 344
 345
 346 //
 347 // Mips Architecture:
 348 //
 349 //        CPU Instruction Set (mipsI - mipsIV)
 350 //
 351
 352
 353
 354 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 355 "add r<RD>, r<RS>, r<RT>"
 356 *mipsI,mipsII,mipsIII,mipsIV:
 357 *vr4100:
 358 *vr5000:
 359 // start-sanitize-vr4xxx
 360 *vr4121:
 361 // end-sanitize-vr4xxx
 362 // start-sanitize-vr4320
 363 *vr4320:
 364 // end-sanitize-vr4320
 365 // start-sanitize-cygnus
 366 *vr5400:
 367 // end-sanitize-cygnus
 368 // start-sanitize-r5900
 369 *r5900:
 370 // end-sanitize-r5900
 371 *r3900:
 372 // start-sanitize-tx19
 373 *tx19:
 374 // end-sanitize-tx19
 375 {
 376   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 377   {
 378     ALU32_BEGIN (GPR[RS]);
 379     ALU32_ADD (GPR[RT]);
 380     ALU32_END (GPR[RD]);
 381   }
 382   TRACE_ALU_RESULT (GPR[RD]);
 383 }
 384
 385
 386
 387 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 388 "addi r<RT>, r<RS>, IMMEDIATE"
 389 *mipsI,mipsII,mipsIII,mipsIV:
 390 *vr4100:
 391 *vr5000:
 392 // start-sanitize-vr4xxx
 393 *vr4121:
 394 // end-sanitize-vr4xxx
 395 // start-sanitize-vr4320
 396 *vr4320:
 397 // end-sanitize-vr4320
 398 // start-sanitize-cygnus
 399 *vr5400:
 400 // end-sanitize-cygnus
 401 // start-sanitize-r5900
 402 *r5900:
 403 // end-sanitize-r5900
 404 *r3900:
 405 // start-sanitize-tx19
 406 *tx19:
 407 // end-sanitize-tx19
 408 {
 409   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 410   {
 411     ALU32_BEGIN (GPR[RS]);
 412     ALU32_ADD (EXTEND16 (IMMEDIATE));
 413     ALU32_END (GPR[RT]);
 414   }
 415   TRACE_ALU_RESULT (GPR[RT]);
 416 }
 417
 418
 419
 420 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 421 {
 422   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 423   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 424   TRACE_ALU_RESULT (GPR[rt]);
 425 }
 426
 427 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 428 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 429 *mipsI,mipsII,mipsIII,mipsIV:
 430 *vr4100:
 431 *vr5000:
 432 // start-sanitize-vr4xxx
 433 *vr4121:
 434 // end-sanitize-vr4xxx
 435 // start-sanitize-vr4320
 436 *vr4320:
 437 // end-sanitize-vr4320
 438 // start-sanitize-cygnus
 439 *vr5400:
 440 // end-sanitize-cygnus
 441 // start-sanitize-r5900
 442 *r5900:
 443 // end-sanitize-r5900
 444 *r3900:
 445 // start-sanitize-tx19
 446 *tx19:
 447 // end-sanitize-tx19
 448 {
 449   do_addiu (SD_, RS, RT, IMMEDIATE);
 450 }
 451
 452
 453
 454 :function:::void:do_addu:int rs, int rt, int rd
 455 {
 456   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 457   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 458   TRACE_ALU_RESULT (GPR[rd]);
 459 }
 460
 461 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 462 "addu r<RD>, r<RS>, r<RT>"
 463 *mipsI,mipsII,mipsIII,mipsIV:
 464 *vr4100:
 465 *vr5000:
 466 // start-sanitize-vr4xxx
 467 *vr4121:
 468 // end-sanitize-vr4xxx
 469 // start-sanitize-vr4320
 470 *vr4320:
 471 // end-sanitize-vr4320
 472 // start-sanitize-cygnus
 473 *vr5400:
 474 // end-sanitize-cygnus
 475 // start-sanitize-r5900
 476 *r5900:
 477 // end-sanitize-r5900
 478 *r3900:
 479 // start-sanitize-tx19
 480 *tx19:
 481 // end-sanitize-tx19
 482 {
 483   do_addu (SD_, RS, RT, RD);
 484 }
 485
 486
 487
 488 :function:::void:do_and:int rs, int rt, int rd
 489 {
 490   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 491   GPR[rd] = GPR[rs] & GPR[rt];
 492   TRACE_ALU_RESULT (GPR[rd]);
 493 }
 494
 495 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 496 "and r<RD>, r<RS>, r<RT>"
 497 *mipsI,mipsII,mipsIII,mipsIV:
 498 *vr4100:
 499 *vr5000:
 500 // start-sanitize-vr4xxx
 501 *vr4121:
 502 // end-sanitize-vr4xxx
 503 // start-sanitize-vr4320
 504 *vr4320:
 505 // end-sanitize-vr4320
 506 // start-sanitize-cygnus
 507 *vr5400:
 508 // end-sanitize-cygnus
 509 // start-sanitize-r5900
 510 *r5900:
 511 // end-sanitize-r5900
 512 *r3900:
 513 // start-sanitize-tx19
 514 *tx19:
 515 // end-sanitize-tx19
 516 {
 517   do_and (SD_, RS, RT, RD);
 518 }
 519
 520
 521
 522 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 523 "and r<RT>, r<RS>, <IMMEDIATE>"
 524 *mipsI,mipsII,mipsIII,mipsIV:
 525 *vr4100:
 526 *vr5000:
 527 // start-sanitize-vr4xxx
 528 *vr4121:
 529 // end-sanitize-vr4xxx
 530 // start-sanitize-vr4320
 531 *vr4320:
 532 // end-sanitize-vr4320
 533 // start-sanitize-cygnus
 534 *vr5400:
 535 // end-sanitize-cygnus
 536 // start-sanitize-r5900
 537 *r5900:
 538 // end-sanitize-r5900
 539 *r3900:
 540 // start-sanitize-tx19
 541 *tx19:
 542 // end-sanitize-tx19
 543 {
 544   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 545   GPR[RT] = GPR[RS] & IMMEDIATE;
 546   TRACE_ALU_RESULT (GPR[RT]);
 547 }
 548
 549
 550
 551 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 552 "beq r<RS>, r<RT>, <OFFSET>"
 553 *mipsI,mipsII,mipsIII,mipsIV:
 554 *vr4100:
 555 *vr5000:
 556 // start-sanitize-vr4xxx
 557 *vr4121:
 558 // end-sanitize-vr4xxx
 559 // start-sanitize-vr4320
 560 *vr4320:
 561 // end-sanitize-vr4320
 562 // start-sanitize-cygnus
 563 *vr5400:
 564 // end-sanitize-cygnus
 565 // start-sanitize-r5900
 566 *r5900:
 567 // end-sanitize-r5900
 568 *r3900:
 569 // start-sanitize-tx19
 570 *tx19:
 571 // end-sanitize-tx19
 572 {
 573   address_word offset = EXTEND16 (OFFSET) << 2;
 574   check_branch_bug ();
 575   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 576     {
 577       mark_branch_bug (NIA+offset);
 578       DELAY_SLOT (NIA + offset);
 579     }
 580 }
 581
 582
 583
 584 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 585 "beql r<RS>, r<RT>, <OFFSET>"
 586 *mipsII:
 587 *mipsIII:
 588 *mipsIV:
 589 *vr4100:
 590 *vr5000:
 591 // start-sanitize-vr4xxx
 592 *vr4121:
 593 // end-sanitize-vr4xxx
 594 // start-sanitize-vr4320
 595 *vr4320:
 596 // end-sanitize-vr4320
 597 // start-sanitize-cygnus
 598 *vr5400:
 599 // end-sanitize-cygnus
 600 // start-sanitize-r5900
 601 *r5900:
 602 // end-sanitize-r5900
 603 *r3900:
 604 // start-sanitize-tx19
 605 *tx19:
 606 // end-sanitize-tx19
 607 {
 608   address_word offset = EXTEND16 (OFFSET) << 2;
 609   check_branch_bug ();
 610   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 611     {
 612       mark_branch_bug (NIA+offset);
 613       DELAY_SLOT (NIA + offset);
 614     }
 615   else
 616     NULLIFY_NEXT_INSTRUCTION ();
 617 }
 618
 619
 620
 621 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 622 "bgez r<RS>, <OFFSET>"
 623 *mipsI,mipsII,mipsIII,mipsIV:
 624 *vr4100:
 625 *vr5000:
 626 // start-sanitize-vr4xxx
 627 *vr4121:
 628 // end-sanitize-vr4xxx
 629 // start-sanitize-vr4320
 630 *vr4320:
 631 // end-sanitize-vr4320
 632 // start-sanitize-cygnus
 633 *vr5400:
 634 // end-sanitize-cygnus
 635 // start-sanitize-r5900
 636 *r5900:
 637 // end-sanitize-r5900
 638 *r3900:
 639 // start-sanitize-tx19
 640 *tx19:
 641 // end-sanitize-tx19
 642 {
 643   address_word offset = EXTEND16 (OFFSET) << 2;
 644   check_branch_bug ();
 645   if ((signed_word) GPR[RS] >= 0)
 646     {
 647       mark_branch_bug (NIA+offset);
 648       DELAY_SLOT (NIA + offset);
 649     }
 650 }
 651
 652
 653
 654 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 655 "bgezal r<RS>, <OFFSET>"
 656 *mipsI,mipsII,mipsIII,mipsIV:
 657 *vr4100:
 658 *vr5000:
 659 // start-sanitize-vr4xxx
 660 *vr4121:
 661 // end-sanitize-vr4xxx
 662 // start-sanitize-vr4320
 663 *vr4320:
 664 // end-sanitize-vr4320
 665 // start-sanitize-cygnus
 666 *vr5400:
 667 // end-sanitize-cygnus
 668 // start-sanitize-r5900
 669 *r5900:
 670 // end-sanitize-r5900
 671 *r3900:
 672 // start-sanitize-tx19
 673 *tx19:
 674 // end-sanitize-tx19
 675 {
 676   address_word offset = EXTEND16 (OFFSET) << 2;
 677   check_branch_bug ();
 678   RA = (CIA + 8);
 679   if ((signed_word) GPR[RS] >= 0)
 680     {
 681       mark_branch_bug (NIA+offset);
 682       DELAY_SLOT (NIA + offset);
 683     }
 684 }
 685
 686
 687
 688 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 689 "bgezall r<RS>, <OFFSET>"
 690 *mipsII:
 691 *mipsIII:
 692 *mipsIV:
 693 *vr4100:
 694 *vr5000:
 695 // start-sanitize-vr4xxx
 696 *vr4121:
 697 // end-sanitize-vr4xxx
 698 // start-sanitize-vr4320
 699 *vr4320:
 700 // end-sanitize-vr4320
 701 // start-sanitize-cygnus
 702 *vr5400:
 703 // end-sanitize-cygnus
 704 // start-sanitize-r5900
 705 *r5900:
 706 // end-sanitize-r5900
 707 *r3900:
 708 // start-sanitize-tx19
 709 *tx19:
 710 // end-sanitize-tx19
 711 {
 712   address_word offset = EXTEND16 (OFFSET) << 2;
 713   check_branch_bug ();
 714   RA = (CIA + 8);
 715   /* NOTE: The branch occurs AFTER the next instruction has been
 716      executed */
 717   if ((signed_word) GPR[RS] >= 0)
 718     {
 719       mark_branch_bug (NIA+offset);
 720       DELAY_SLOT (NIA + offset);
 721     }
 722   else
 723     NULLIFY_NEXT_INSTRUCTION ();
 724 }
 725
 726
 727
 728 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 729 "bgezl r<RS>, <OFFSET>"
 730 *mipsII:
 731 *mipsIII:
 732 *mipsIV:
 733 *vr4100:
 734 *vr5000:
 735 // start-sanitize-vr4xxx
 736 *vr4121:
 737 // end-sanitize-vr4xxx
 738 // start-sanitize-vr4320
 739 *vr4320:
 740 // end-sanitize-vr4320
 741 // start-sanitize-cygnus
 742 *vr5400:
 743 // end-sanitize-cygnus
 744 // start-sanitize-r5900
 745 *r5900:
 746 // end-sanitize-r5900
 747 *r3900:
 748 // start-sanitize-tx19
 749 *tx19:
 750 // end-sanitize-tx19
 751 {
 752   address_word offset = EXTEND16 (OFFSET) << 2;
 753   check_branch_bug ();
 754   if ((signed_word) GPR[RS] >= 0)
 755     {
 756       mark_branch_bug (NIA+offset);
 757       DELAY_SLOT (NIA + offset);
 758     }
 759   else
 760     NULLIFY_NEXT_INSTRUCTION ();
 761 }
 762
 763
 764
 765 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 766 "bgtz r<RS>, <OFFSET>"
 767 *mipsI,mipsII,mipsIII,mipsIV:
 768 *vr4100:
 769 *vr5000:
 770 // start-sanitize-vr4xxx
 771 *vr4121:
 772 // end-sanitize-vr4xxx
 773 // start-sanitize-vr4320
 774 *vr4320:
 775 // end-sanitize-vr4320
 776 // start-sanitize-cygnus
 777 *vr5400:
 778 // end-sanitize-cygnus
 779 // start-sanitize-r5900
 780 *r5900:
 781 // end-sanitize-r5900
 782 *r3900:
 783 // start-sanitize-tx19
 784 *tx19:
 785 // end-sanitize-tx19
 786 {
 787   address_word offset = EXTEND16 (OFFSET) << 2;
 788   check_branch_bug ();
 789   if ((signed_word) GPR[RS] > 0)
 790     {
 791       mark_branch_bug (NIA+offset);
 792       DELAY_SLOT (NIA + offset);
 793     }
 794 }
 795
 796
 797
 798 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 799 "bgtzl r<RS>, <OFFSET>"
 800 *mipsII:
 801 *mipsIII:
 802 *mipsIV:
 803 *vr4100:
 804 *vr5000:
 805 // start-sanitize-vr4xxx
 806 *vr4121:
 807 // end-sanitize-vr4xxx
 808 // start-sanitize-vr4320
 809 *vr4320:
 810 // end-sanitize-vr4320
 811 // start-sanitize-cygnus
 812 *vr5400:
 813 // end-sanitize-cygnus
 814 // start-sanitize-r5900
 815 *r5900:
 816 // end-sanitize-r5900
 817 *r3900:
 818 // start-sanitize-tx19
 819 *tx19:
 820 // end-sanitize-tx19
 821 {
 822   address_word offset = EXTEND16 (OFFSET) << 2;
 823   check_branch_bug ();
 824   /* NOTE: The branch occurs AFTER the next instruction has been
 825      executed */
 826   if ((signed_word) GPR[RS] > 0)
 827     {
 828       mark_branch_bug (NIA+offset);
 829       DELAY_SLOT (NIA + offset);
 830     }
 831   else
 832     NULLIFY_NEXT_INSTRUCTION ();
 833 }
 834
 835
 836
 837 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 838 "blez r<RS>, <OFFSET>"
 839 *mipsI,mipsII,mipsIII,mipsIV:
 840 *vr4100:
 841 *vr5000:
 842 // start-sanitize-vr4xxx
 843 *vr4121:
 844 // end-sanitize-vr4xxx
 845 // start-sanitize-vr4320
 846 *vr4320:
 847 // end-sanitize-vr4320
 848 // start-sanitize-cygnus
 849 *vr5400:
 850 // end-sanitize-cygnus
 851 // start-sanitize-r5900
 852 *r5900:
 853 // end-sanitize-r5900
 854 *r3900:
 855 // start-sanitize-tx19
 856 *tx19:
 857 // end-sanitize-tx19
 858 {
 859   address_word offset = EXTEND16 (OFFSET) << 2;
 860   check_branch_bug ();
 861   /* NOTE: The branch occurs AFTER the next instruction has been
 862      executed */
 863   if ((signed_word) GPR[RS] <= 0)
 864     {
 865       mark_branch_bug (NIA+offset);
 866       DELAY_SLOT (NIA + offset);
 867     }
 868 }
 869
 870
 871
 872 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 873 "bgezl r<RS>, <OFFSET>"
 874 *mipsII:
 875 *mipsIII:
 876 *mipsIV:
 877 *vr4100:
 878 *vr5000:
 879 // start-sanitize-vr4xxx
 880 *vr4121:
 881 // end-sanitize-vr4xxx
 882 // start-sanitize-vr4320
 883 *vr4320:
 884 // end-sanitize-vr4320
 885 // start-sanitize-cygnus
 886 *vr5400:
 887 // end-sanitize-cygnus
 888 // start-sanitize-r5900
 889 *r5900:
 890 // end-sanitize-r5900
 891 *r3900:
 892 // start-sanitize-tx19
 893 *tx19:
 894 // end-sanitize-tx19
 895 {
 896   address_word offset = EXTEND16 (OFFSET) << 2;
 897   check_branch_bug ();
 898   if ((signed_word) GPR[RS] <= 0)
 899     {
 900       mark_branch_bug (NIA+offset);
 901       DELAY_SLOT (NIA + offset);
 902     }
 903   else
 904     NULLIFY_NEXT_INSTRUCTION ();
 905 }
 906
 907
 908
 909 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 910 "bltz r<RS>, <OFFSET>"
 911 *mipsI,mipsII,mipsIII,mipsIV:
 912 *vr4100:
 913 *vr5000:
 914 // start-sanitize-vr4xxx
 915 *vr4121:
 916 // end-sanitize-vr4xxx
 917 // start-sanitize-vr4320
 918 *vr4320:
 919 // end-sanitize-vr4320
 920 // start-sanitize-cygnus
 921 *vr5400:
 922 // end-sanitize-cygnus
 923 // start-sanitize-r5900
 924 *r5900:
 925 // end-sanitize-r5900
 926 *r3900:
 927 // start-sanitize-tx19
 928 *tx19:
 929 // end-sanitize-tx19
 930 {
 931   address_word offset = EXTEND16 (OFFSET) << 2;
 932   check_branch_bug ();
 933   if ((signed_word) GPR[RS] < 0)
 934     {
 935       mark_branch_bug (NIA+offset);
 936       DELAY_SLOT (NIA + offset);
 937     }
 938 }
 939
 940
 941
 942 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 943 "bltzal r<RS>, <OFFSET>"
 944 *mipsI,mipsII,mipsIII,mipsIV:
 945 *vr4100:
 946 *vr5000:
 947 // start-sanitize-vr4xxx
 948 *vr4121:
 949 // end-sanitize-vr4xxx
 950 // start-sanitize-vr4320
 951 *vr4320:
 952 // end-sanitize-vr4320
 953 // start-sanitize-cygnus
 954 *vr5400:
 955 // end-sanitize-cygnus
 956 // start-sanitize-r5900
 957 *r5900:
 958 // end-sanitize-r5900
 959 *r3900:
 960 // start-sanitize-tx19
 961 *tx19:
 962 // end-sanitize-tx19
 963 {
 964   address_word offset = EXTEND16 (OFFSET) << 2;
 965   check_branch_bug ();
 966   RA = (CIA + 8);
 967   /* NOTE: The branch occurs AFTER the next instruction has been
 968      executed */
 969   if ((signed_word) GPR[RS] < 0)
 970     {
 971       mark_branch_bug (NIA+offset);
 972       DELAY_SLOT (NIA + offset);
 973     }
 974 }
 975
 976
 977
 978 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 979 "bltzall r<RS>, <OFFSET>"
 980 *mipsII:
 981 *mipsIII:
 982 *mipsIV:
 983 *vr4100:
 984 *vr5000:
 985 // start-sanitize-vr4xxx
 986 *vr4121:
 987 // end-sanitize-vr4xxx
 988 // start-sanitize-vr4320
 989 *vr4320:
 990 // end-sanitize-vr4320
 991 // start-sanitize-cygnus
 992 *vr5400:
 993 // end-sanitize-cygnus
 994 // start-sanitize-r5900
 995 *r5900:
 996 // end-sanitize-r5900
 997 *r3900:
 998 // start-sanitize-tx19
 999 *tx19:
1000 // end-sanitize-tx19
1001 {
1002   address_word offset = EXTEND16 (OFFSET) << 2;
1003   check_branch_bug ();
1004   RA = (CIA + 8);
1005   if ((signed_word) GPR[RS] < 0)
1006     {
1007       mark_branch_bug (NIA+offset);
1008       DELAY_SLOT (NIA + offset);
1009     }
1010   else
1011     NULLIFY_NEXT_INSTRUCTION ();
1012 }
1013
1014
1015
1016 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1017 "bltzl r<RS>, <OFFSET>"
1018 *mipsII:
1019 *mipsIII:
1020 *mipsIV:
1021 *vr4100:
1022 *vr5000:
1023 // start-sanitize-vr4xxx
1024 *vr4121:
1025 // end-sanitize-vr4xxx
1026 // start-sanitize-vr4320
1027 *vr4320:
1028 // end-sanitize-vr4320
1029 // start-sanitize-cygnus
1030 *vr5400:
1031 // end-sanitize-cygnus
1032 // start-sanitize-r5900
1033 *r5900:
1034 // end-sanitize-r5900
1035 *r3900:
1036 // start-sanitize-tx19
1037 *tx19:
1038 // end-sanitize-tx19
1039 {
1040   address_word offset = EXTEND16 (OFFSET) << 2;
1041   check_branch_bug ();
1042   /* NOTE: The branch occurs AFTER the next instruction has been
1043      executed */
1044   if ((signed_word) GPR[RS] < 0)
1045     {
1046       mark_branch_bug (NIA+offset);
1047       DELAY_SLOT (NIA + offset);
1048     }
1049   else
1050     NULLIFY_NEXT_INSTRUCTION ();
1051 }
1052
1053
1054
1055 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1056 "bne r<RS>, r<RT>, <OFFSET>"
1057 *mipsI,mipsII,mipsIII,mipsIV:
1058 *vr4100:
1059 *vr5000:
1060 // start-sanitize-vr4xxx
1061 *vr4121:
1062 // end-sanitize-vr4xxx
1063 // start-sanitize-vr4320
1064 *vr4320:
1065 // end-sanitize-vr4320
1066 // start-sanitize-cygnus
1067 *vr5400:
1068 // end-sanitize-cygnus
1069 // start-sanitize-r5900
1070 *r5900:
1071 // end-sanitize-r5900
1072 *r3900:
1073 // start-sanitize-tx19
1074 *tx19:
1075 // end-sanitize-tx19
1076 {
1077   address_word offset = EXTEND16 (OFFSET) << 2;
1078   check_branch_bug ();
1079   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1080     {
1081       mark_branch_bug (NIA+offset);
1082       DELAY_SLOT (NIA + offset);
1083     }
1084 }
1085
1086
1087
1088 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1089 "bnel r<RS>, r<RT>, <OFFSET>"
1090 *mipsII:
1091 *mipsIII:
1092 *mipsIV:
1093 *vr4100:
1094 *vr5000:
1095 // start-sanitize-vr4xxx
1096 *vr4121:
1097 // end-sanitize-vr4xxx
1098 // start-sanitize-vr4320
1099 *vr4320:
1100 // end-sanitize-vr4320
1101 // start-sanitize-cygnus
1102 *vr5400:
1103 // end-sanitize-cygnus
1104 // start-sanitize-r5900
1105 *r5900:
1106 // end-sanitize-r5900
1107 *r3900:
1108 // start-sanitize-tx19
1109 *tx19:
1110 // end-sanitize-tx19
1111 {
1112   address_word offset = EXTEND16 (OFFSET) << 2;
1113   check_branch_bug ();
1114   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1115     {
1116       mark_branch_bug (NIA+offset);
1117       DELAY_SLOT (NIA + offset);
1118     }
1119   else
1120     NULLIFY_NEXT_INSTRUCTION ();
1121 }
1122
1123
1124
1125 000000,20.CODE,001101:SPECIAL:32::BREAK
1126 "break"
1127 *mipsI,mipsII,mipsIII,mipsIV:
1128 *vr4100:
1129 *vr5000:
1130 // start-sanitize-vr4xxx
1131 *vr4121:
1132 // end-sanitize-vr4xxx
1133 // start-sanitize-vr4320
1134 *vr4320:
1135 // end-sanitize-vr4320
1136 // start-sanitize-cygnus
1137 *vr5400:
1138 // end-sanitize-cygnus
1139 // start-sanitize-r5900
1140 *r5900:
1141 // end-sanitize-r5900
1142 *r3900:
1143 // start-sanitize-tx19
1144 *tx19:
1145 // end-sanitize-tx19
1146 {
1147   /* Check for some break instruction which are reserved for use by the simulator.  */
1148   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1149   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1150       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1151     {
1152       sim_engine_halt (SD, CPU, NULL, cia,
1153                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1154     }
1155   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1156            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1157     {
1158       if (STATE & simDELAYSLOT)
1159         PC = cia - 4; /* reference the branch instruction */
1160       else
1161         PC = cia;
1162       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1163     }
1164 // start-sanitize-sky
1165 #ifdef TARGET_SKY
1166   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1167     {
1168       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1169     }
1170   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1171     {
1172       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1173     }
1174   else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
1175     {
1176       sim_monitor(SD, CPU, cia, 316);   /* Magic number for idt printf routine. */
1177     }
1178   else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
1179     {
1180       /* This is a multi-phase load instruction.  Load next configured
1181          executable and return its starting PC in A0 ($4). */
1182
1183       if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
1184         {
1185           sim_io_eprintf (SD, "Cannot load program %d.  Not enough load-next options.\n",
1186                           STATE_MLOAD_COUNT (SD));
1187           A0 = 0;
1188         }
1189       else
1190         {
1191           char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
1192           SIM_RC rc;
1193
1194           STATE_MLOAD_INDEX (SD) ++;
1195
1196           /* call sim_load_file, preserving most previous state */
1197           rc = sim_load (SD, next, NULL, 0);
1198           if(rc != SIM_RC_OK)
1199             {
1200               sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
1201                               STATE_MLOAD_INDEX (SD));
1202               A0 = 0;
1203             }
1204           else
1205             A0 = STATE_START_ADDR (SD);
1206         }
1207     }
1208 #endif TARGET_SKY
1209 // end-sanitize-sky
1210
1211   else
1212     {
1213       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1214          the exception. */
1215       SignalException(BreakPoint, instruction_0);
1216     }
1217 }
1218
1219
1220
1221
1222
1223
1224 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1225 "dadd r<RD>, r<RS>, r<RT>"
1226 *mipsIII:
1227 *mipsIV:
1228 *vr4100:
1229 *vr5000:
1230 // start-sanitize-vr4xxx
1231 *vr4121:
1232 // end-sanitize-vr4xxx
1233 // start-sanitize-vr4320
1234 *vr4320:
1235 // end-sanitize-vr4320
1236 // start-sanitize-cygnus
1237 *vr5400:
1238 // end-sanitize-cygnus
1239 // start-sanitize-r5900
1240 *r5900:
1241 // end-sanitize-r5900
1242 // start-sanitize-tx19
1243 *tx19:
1244 // end-sanitize-tx19
1245 {
1246   /* this check's for overflow */
1247   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1248   {
1249     ALU64_BEGIN (GPR[RS]);
1250     ALU64_ADD (GPR[RT]);
1251     ALU64_END (GPR[RD]);
1252   }
1253   TRACE_ALU_RESULT (GPR[RD]);
1254 }
1255
1256
1257
1258 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1259 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1260 *mipsIII:
1261 *mipsIV:
1262 *vr4100:
1263 *vr5000:
1264 // start-sanitize-vr4xxx
1265 *vr4121:
1266 // end-sanitize-vr4xxx
1267 // start-sanitize-vr4320
1268 *vr4320:
1269 // end-sanitize-vr4320
1270 // start-sanitize-cygnus
1271 *vr5400:
1272 // end-sanitize-cygnus
1273 // start-sanitize-r5900
1274 *r5900:
1275 // end-sanitize-r5900
1276 // start-sanitize-tx19
1277 *tx19:
1278 // end-sanitize-tx19
1279 {
1280   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1281   {
1282     ALU64_BEGIN (GPR[RS]);
1283     ALU64_ADD (EXTEND16 (IMMEDIATE));
1284     ALU64_END (GPR[RT]);
1285   }
1286   TRACE_ALU_RESULT (GPR[RT]);
1287 }
1288
1289
1290
1291 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1292 {
1293   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1294   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1295   TRACE_ALU_RESULT (GPR[rt]);
1296 }
1297
1298 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1299 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1300 *mipsIII:
1301 *mipsIV:
1302 *vr4100:
1303 *vr5000:
1304 // start-sanitize-vr4xxx
1305 *vr4121:
1306 // end-sanitize-vr4xxx
1307 // start-sanitize-vr4320
1308 *vr4320:
1309 // end-sanitize-vr4320
1310 // start-sanitize-cygnus
1311 *vr5400:
1312 // end-sanitize-cygnus
1313 // start-sanitize-r5900
1314 *r5900:
1315 // end-sanitize-r5900
1316 // start-sanitize-tx19
1317 *tx19:
1318 // end-sanitize-tx19
1319 {
1320   do_daddiu (SD_, RS, RT, IMMEDIATE);
1321 }
1322
1323
1324
1325 :function:::void:do_daddu:int rs, int rt, int rd
1326 {
1327   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1328   GPR[rd] = GPR[rs] + GPR[rt];
1329   TRACE_ALU_RESULT (GPR[rd]);
1330 }
1331
1332 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1333 "daddu r<RD>, r<RS>, r<RT>"
1334 *mipsIII:
1335 *mipsIV:
1336 *vr4100:
1337 *vr5000:
1338 // start-sanitize-vr4xxx
1339 *vr4121:
1340 // end-sanitize-vr4xxx
1341 // start-sanitize-vr4320
1342 *vr4320:
1343 // end-sanitize-vr4320
1344 // start-sanitize-cygnus
1345 *vr5400:
1346 // end-sanitize-cygnus
1347 // start-sanitize-r5900
1348 *r5900:
1349 // end-sanitize-r5900
1350 // start-sanitize-tx19
1351 *tx19:
1352 // end-sanitize-tx19
1353 {
1354   do_daddu (SD_, RS, RT, RD);
1355 }
1356
1357
1358
1359 :function:64::void:do_ddiv:int rs, int rt
1360 {
1361   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1362   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1363   {
1364     signed64 n = GPR[rs];
1365     signed64 d = GPR[rt];
1366     if (d == 0)
1367       {
1368         LO = SIGNED64 (0x8000000000000000);
1369         HI = 0;
1370       }
1371     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1372       {
1373         LO = SIGNED64 (0x8000000000000000);
1374         HI = 0;
1375       }
1376     else
1377       {
1378         LO = (n / d);
1379         HI = (n % d);
1380       }
1381   }
1382   TRACE_ALU_RESULT2 (HI, LO);
1383 }
1384
1385 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1386 "ddiv r<RS>, r<RT>"
1387 *mipsIII:
1388 *mipsIV:
1389 *vr4100:
1390 *vr5000:
1391 // start-sanitize-vr4xxx
1392 *vr4121:
1393 // end-sanitize-vr4xxx
1394 // start-sanitize-vr4320
1395 *vr4320:
1396 // end-sanitize-vr4320
1397 // start-sanitize-cygnus
1398 *vr5400:
1399 // end-sanitize-cygnus
1400 // start-sanitize-r5900
1401 *r5900:
1402 // end-sanitize-r5900
1403 // start-sanitize-tx19
1404 *tx19:
1405 // end-sanitize-tx19
1406 {
1407   do_ddiv (SD_, RS, RT);
1408 }
1409
1410
1411
1412 :function:64::void:do_ddivu:int rs, int rt
1413 {
1414   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1415   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1416   {
1417     unsigned64 n = GPR[rs];
1418     unsigned64 d = GPR[rt];
1419     if (d == 0)
1420       {
1421         LO = SIGNED64 (0x8000000000000000);
1422         HI = 0;
1423       }
1424     else
1425       {
1426         LO = (n / d);
1427         HI = (n % d);
1428       }
1429   }
1430   TRACE_ALU_RESULT2 (HI, LO);
1431 }
1432
1433 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1434 "ddivu r<RS>, r<RT>"
1435 *mipsIII:
1436 *mipsIV:
1437 *vr4100:
1438 *vr5000:
1439 // start-sanitize-vr4xxx
1440 *vr4121:
1441 // end-sanitize-vr4xxx
1442 // start-sanitize-vr4320
1443 *vr4320:
1444 // end-sanitize-vr4320
1445 // start-sanitize-cygnus
1446 *vr5400:
1447 // end-sanitize-cygnus
1448 // start-sanitize-tx19
1449 *tx19:
1450 // end-sanitize-tx19
1451 {
1452   do_ddivu (SD_, RS, RT);
1453 }
1454
1455
1456
1457 :function:::void:do_div:int rs, int rt
1458 {
1459   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1460   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1461   {
1462     signed32 n = GPR[rs];
1463     signed32 d = GPR[rt];
1464     if (d == 0)
1465       {
1466         LO = EXTEND32 (0x80000000);
1467         HI = EXTEND32 (0);
1468       }
1469     else if (n == SIGNED32 (0x80000000) && d == -1)
1470       {
1471         LO = EXTEND32 (0x80000000);
1472         HI = EXTEND32 (0);
1473       }
1474     else
1475       {
1476         LO = EXTEND32 (n / d);
1477         HI = EXTEND32 (n % d);
1478       }
1479   }
1480   TRACE_ALU_RESULT2 (HI, LO);
1481 }
1482
1483 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1484 "div r<RS>, r<RT>"
1485 *mipsI,mipsII,mipsIII,mipsIV:
1486 *vr4100:
1487 *vr5000:
1488 // start-sanitize-vr4xxx
1489 *vr4121:
1490 // end-sanitize-vr4xxx
1491 // start-sanitize-vr4320
1492 *vr4320:
1493 // end-sanitize-vr4320
1494 // start-sanitize-cygnus
1495 *vr5400:
1496 // end-sanitize-cygnus
1497 // start-sanitize-r5900
1498 *r5900:
1499 // end-sanitize-r5900
1500 *r3900:
1501 // start-sanitize-tx19
1502 *tx19:
1503 // end-sanitize-tx19
1504 {
1505   do_div (SD_, RS, RT);
1506 }
1507
1508
1509
1510 :function:::void:do_divu:int rs, int rt
1511 {
1512   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1513   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1514   {
1515     unsigned32 n = GPR[rs];
1516     unsigned32 d = GPR[rt];
1517     if (d == 0)
1518       {
1519         LO = EXTEND32 (0x80000000);
1520         HI = EXTEND32 (0);
1521       }
1522    else
1523      {
1524        LO = EXTEND32 (n / d);
1525        HI = EXTEND32 (n % d);
1526      }
1527   }
1528   TRACE_ALU_RESULT2 (HI, LO);
1529 }
1530
1531 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1532 "divu r<RS>, r<RT>"
1533 *mipsI,mipsII,mipsIII,mipsIV:
1534 *vr4100:
1535 *vr5000:
1536 // start-sanitize-vr4xxx
1537 *vr4121:
1538 // end-sanitize-vr4xxx
1539 // start-sanitize-vr4320
1540 *vr4320:
1541 // end-sanitize-vr4320
1542 // start-sanitize-cygnus
1543 *vr5400:
1544 // end-sanitize-cygnus
1545 // start-sanitize-r5900
1546 *r5900:
1547 // end-sanitize-r5900
1548 *r3900:
1549 // start-sanitize-tx19
1550 *tx19:
1551 // end-sanitize-tx19
1552 {
1553   do_divu (SD_, RS, RT);
1554 }
1555
1556
1557
1558 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1559 {
1560   unsigned64 lo;
1561   unsigned64 hi;
1562   unsigned64 m00;
1563   unsigned64 m01;
1564   unsigned64 m10;
1565   unsigned64 m11;
1566   unsigned64 mid;
1567   int sign;
1568   unsigned64 op1 = GPR[rs];
1569   unsigned64 op2 = GPR[rt];
1570   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1571   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1572   /* make signed multiply unsigned */
1573   sign = 0;
1574   if (signed_p)
1575     {
1576       if (op1 < 0)
1577         {
1578           op1 = - op1;
1579           ++sign;
1580         }
1581       if (op2 < 0)
1582         {
1583           op2 = - op2;
1584           ++sign;
1585         }
1586     }
1587   /* multuply out the 4 sub products */
1588   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1589   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1590   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1591   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1592   /* add the products */
1593   mid = ((unsigned64) VH4_8 (m00)
1594          + (unsigned64) VL4_8 (m10)
1595          + (unsigned64) VL4_8 (m01));
1596   lo = U8_4 (mid, m00);
1597   hi = (m11
1598         + (unsigned64) VH4_8 (mid)
1599         + (unsigned64) VH4_8 (m01)
1600         + (unsigned64) VH4_8 (m10));
1601   /* fix the sign */
1602   if (sign & 1)
1603     {
1604       lo = -lo;
1605       if (lo == 0)
1606         hi = -hi;
1607       else
1608         hi = -hi - 1;
1609     }
1610   /* save the result HI/LO (and a gpr) */
1611   LO = lo;
1612   HI = hi;
1613   if (rd != 0)
1614     GPR[rd] = lo;
1615   TRACE_ALU_RESULT2 (HI, LO);
1616 }
1617
1618 :function:::void:do_dmult:int rs, int rt, int rd
1619 {
1620   do_dmultx (SD_, rs, rt, rd, 1);
1621 }
1622
1623 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1624 "dmult r<RS>, r<RT>"
1625 *mipsIII,mipsIV:
1626 *vr4100:
1627 // start-sanitize-vr4xxx
1628 *vr4121:
1629 // end-sanitize-vr4xxx
1630 // start-sanitize-tx19
1631 *tx19:
1632 // end-sanitize-tx19
1633 // start-sanitize-vr4320
1634 *vr4320:
1635 // end-sanitize-vr4320
1636 {
1637   do_dmult (SD_, RS, RT, 0);
1638 }
1639
1640 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1641 "dmult r<RS>, r<RT>":RD == 0
1642 "dmult r<RD>, r<RS>, r<RT>"
1643 *vr5000:
1644 // start-sanitize-cygnus
1645 *vr5400:
1646 // end-sanitize-cygnus
1647 {
1648   do_dmult (SD_, RS, RT, RD);
1649 }
1650
1651
1652
1653 :function:::void:do_dmultu:int rs, int rt, int rd
1654 {
1655   do_dmultx (SD_, rs, rt, rd, 0);
1656 }
1657
1658 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1659 "dmultu r<RS>, r<RT>"
1660 *mipsIII,mipsIV:
1661 *vr4100:
1662 // start-sanitize-vr4xxx
1663 *vr4121:
1664 // end-sanitize-vr4xxx
1665 // start-sanitize-tx19
1666 *tx19:
1667 // end-sanitize-tx19
1668 // start-sanitize-vr4320
1669 *vr4320:
1670 // end-sanitize-vr4320
1671 {
1672   do_dmultu (SD_, RS, RT, 0);
1673 }
1674
1675 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1676 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1677 "dmultu r<RS>, r<RT>"
1678 *vr5000:
1679 // start-sanitize-cygnus
1680 *vr5400:
1681 // end-sanitize-cygnus
1682 {
1683   do_dmultu (SD_, RS, RT, RD);
1684 }
1685
1686
1687
1688 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1689 "dsll r<RD>, r<RT>, <SHIFT>"
1690 *mipsIII:
1691 *mipsIV:
1692 *vr4100:
1693 *vr5000:
1694 // start-sanitize-vr4xxx
1695 *vr4121:
1696 // end-sanitize-vr4xxx
1697 // start-sanitize-vr4320
1698 *vr4320:
1699 // end-sanitize-vr4320
1700 // start-sanitize-cygnus
1701 *vr5400:
1702 // end-sanitize-cygnus
1703 // start-sanitize-r5900
1704 *r5900:
1705 // end-sanitize-r5900
1706 // start-sanitize-tx19
1707 *tx19:
1708 // end-sanitize-tx19
1709 {
1710   int s = SHIFT;
1711   GPR[RD] = GPR[RT] << s;
1712 }
1713
1714
1715 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1716 "dsll32 r<RD>, r<RT>, <SHIFT>"
1717 *mipsIII:
1718 *mipsIV:
1719 *vr4100:
1720 *vr5000:
1721 // start-sanitize-vr4xxx
1722 *vr4121:
1723 // end-sanitize-vr4xxx
1724 // start-sanitize-vr4320
1725 *vr4320:
1726 // end-sanitize-vr4320
1727 // start-sanitize-cygnus
1728 *vr5400:
1729 // end-sanitize-cygnus
1730 // start-sanitize-r5900
1731 *r5900:
1732 // end-sanitize-r5900
1733 // start-sanitize-tx19
1734 *tx19:
1735 // end-sanitize-tx19
1736 {
1737   int s = 32 + SHIFT;
1738   GPR[RD] = GPR[RT] << s;
1739 }
1740
1741
1742
1743 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1744 "dsllv r<RD>, r<RT>, r<RS>"
1745 *mipsIII:
1746 *mipsIV:
1747 *vr4100:
1748 *vr5000:
1749 // start-sanitize-vr4xxx
1750 *vr4121:
1751 // end-sanitize-vr4xxx
1752 // start-sanitize-vr4320
1753 *vr4320:
1754 // end-sanitize-vr4320
1755 // start-sanitize-cygnus
1756 *vr5400:
1757 // end-sanitize-cygnus
1758 // start-sanitize-r5900
1759 *r5900:
1760 // end-sanitize-r5900
1761 // start-sanitize-tx19
1762 *tx19:
1763 // end-sanitize-tx19
1764 {
1765   int s = MASKED64 (GPR[RS], 5, 0);
1766   GPR[RD] = GPR[RT] << s;
1767 }
1768
1769
1770
1771 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1772 "dsra r<RD>, r<RT>, <SHIFT>"
1773 *mipsIII:
1774 *mipsIV:
1775 *vr4100:
1776 *vr5000:
1777 // start-sanitize-vr4xxx
1778 *vr4121:
1779 // end-sanitize-vr4xxx
1780 // start-sanitize-vr4320
1781 *vr4320:
1782 // end-sanitize-vr4320
1783 // start-sanitize-cygnus
1784 *vr5400:
1785 // end-sanitize-cygnus
1786 // start-sanitize-r5900
1787 *r5900:
1788 // end-sanitize-r5900
1789 // start-sanitize-tx19
1790 *tx19:
1791 // end-sanitize-tx19
1792 {
1793   int s = SHIFT;
1794   GPR[RD] = ((signed64) GPR[RT]) >> s;
1795 }
1796
1797
1798 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1799 "dsra32 r<RT>, r<RD>, <SHIFT>"
1800 *mipsIII:
1801 *mipsIV:
1802 *vr4100:
1803 *vr5000:
1804 // start-sanitize-vr4xxx
1805 *vr4121:
1806 // end-sanitize-vr4xxx
1807 // start-sanitize-vr4320
1808 *vr4320:
1809 // end-sanitize-vr4320
1810 // start-sanitize-cygnus
1811 *vr5400:
1812 // end-sanitize-cygnus
1813 // start-sanitize-r5900
1814 *r5900:
1815 // end-sanitize-r5900
1816 // start-sanitize-tx19
1817 *tx19:
1818 // end-sanitize-tx19
1819 {
1820   int s = 32 + SHIFT;
1821   GPR[RD] = ((signed64) GPR[RT]) >> s;
1822 }
1823
1824
1825 :function:::void:do_dsrav:int rs, int rt, int rd
1826 {
1827   int s = MASKED64 (GPR[rs], 5, 0);
1828   TRACE_ALU_INPUT2 (GPR[rt], s);
1829   GPR[rd] = ((signed64) GPR[rt]) >> s;
1830   TRACE_ALU_RESULT (GPR[rd]);
1831 }
1832
1833 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1834 "dsra32 r<RT>, r<RD>, r<RS>"
1835 *mipsIII:
1836 *mipsIV:
1837 *vr4100:
1838 *vr5000:
1839 // start-sanitize-vr4xxx
1840 *vr4121:
1841 // end-sanitize-vr4xxx
1842 // start-sanitize-vr4320
1843 *vr4320:
1844 // end-sanitize-vr4320
1845 // start-sanitize-cygnus
1846 *vr5400:
1847 // end-sanitize-cygnus
1848 // start-sanitize-r5900
1849 *r5900:
1850 // end-sanitize-r5900
1851 // start-sanitize-tx19
1852 *tx19:
1853 // end-sanitize-tx19
1854 {
1855   do_dsrav (SD_, RS, RT, RD);
1856 }
1857
1858
1859 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1860 "dsrl r<RD>, r<RT>, <SHIFT>"
1861 *mipsIII:
1862 *mipsIV:
1863 *vr4100:
1864 *vr5000:
1865 // start-sanitize-vr4xxx
1866 *vr4121:
1867 // end-sanitize-vr4xxx
1868 // start-sanitize-vr4320
1869 *vr4320:
1870 // end-sanitize-vr4320
1871 // start-sanitize-cygnus
1872 *vr5400:
1873 // end-sanitize-cygnus
1874 // start-sanitize-r5900
1875 *r5900:
1876 // end-sanitize-r5900
1877 // start-sanitize-tx19
1878 *tx19:
1879 // end-sanitize-tx19
1880 {
1881   int s = SHIFT;
1882   GPR[RD] = (unsigned64) GPR[RT] >> s;
1883 }
1884
1885
1886 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1887 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1888 *mipsIII:
1889 *mipsIV:
1890 *vr4100:
1891 *vr5000:
1892 // start-sanitize-vr4xxx
1893 *vr4121:
1894 // end-sanitize-vr4xxx
1895 // start-sanitize-vr4320
1896 *vr4320:
1897 // end-sanitize-vr4320
1898 // start-sanitize-cygnus
1899 *vr5400:
1900 // end-sanitize-cygnus
1901 // start-sanitize-r5900
1902 *r5900:
1903 // end-sanitize-r5900
1904 // start-sanitize-tx19
1905 *tx19:
1906 // end-sanitize-tx19
1907 {
1908   int s = 32 + SHIFT;
1909   GPR[RD] = (unsigned64) GPR[RT] >> s;
1910 }
1911
1912
1913 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1914 "dsrl32 r<RD>, r<RT>, r<RS>"
1915 *mipsIII:
1916 *mipsIV:
1917 *vr4100:
1918 *vr5000:
1919 // start-sanitize-vr4xxx
1920 *vr4121:
1921 // end-sanitize-vr4xxx
1922 // start-sanitize-vr4320
1923 *vr4320:
1924 // end-sanitize-vr4320
1925 // start-sanitize-cygnus
1926 *vr5400:
1927 // end-sanitize-cygnus
1928 // start-sanitize-r5900
1929 *r5900:
1930 // end-sanitize-r5900
1931 // start-sanitize-tx19
1932 *tx19:
1933 // end-sanitize-tx19
1934 {
1935   int s = MASKED64 (GPR[RS], 5, 0);
1936   GPR[RD] = (unsigned64) GPR[RT] >> s;
1937 }
1938
1939
1940 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1941 "dsub r<RD>, r<RS>, r<RT>"
1942 *mipsIII:
1943 *mipsIV:
1944 *vr4100:
1945 *vr5000:
1946 // start-sanitize-vr4xxx
1947 *vr4121:
1948 // end-sanitize-vr4xxx
1949 // start-sanitize-vr4320
1950 *vr4320:
1951 // end-sanitize-vr4320
1952 // start-sanitize-cygnus
1953 *vr5400:
1954 // end-sanitize-cygnus
1955 // start-sanitize-r5900
1956 *r5900:
1957 // end-sanitize-r5900
1958 // start-sanitize-tx19
1959 *tx19:
1960 // end-sanitize-tx19
1961 {
1962   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1963   {
1964     ALU64_BEGIN (GPR[RS]);
1965     ALU64_SUB (GPR[RT]);
1966     ALU64_END (GPR[RD]);
1967   }
1968   TRACE_ALU_RESULT (GPR[RD]);
1969 }
1970
1971
1972 :function:::void:do_dsubu:int rs, int rt, int rd
1973 {
1974   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1975   GPR[rd] = GPR[rs] - GPR[rt];
1976   TRACE_ALU_RESULT (GPR[rd]);
1977 }
1978
1979 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1980 "dsubu r<RD>, r<RS>, r<RT>"
1981 *mipsIII:
1982 *mipsIV:
1983 *vr4100:
1984 *vr5000:
1985 // start-sanitize-vr4xxx
1986 *vr4121:
1987 // end-sanitize-vr4xxx
1988 // start-sanitize-vr4320
1989 *vr4320:
1990 // end-sanitize-vr4320
1991 // start-sanitize-cygnus
1992 *vr5400:
1993 // end-sanitize-cygnus
1994 // start-sanitize-r5900
1995 *r5900:
1996 // end-sanitize-r5900
1997 // start-sanitize-tx19
1998 *tx19:
1999 // end-sanitize-tx19
2000 {
2001   do_dsubu (SD_, RS, RT, RD);
2002 }
2003
2004
2005 000010,26.INSTR_INDEX:NORMAL:32::J
2006 "j <INSTR_INDEX>"
2007 *mipsI,mipsII,mipsIII,mipsIV:
2008 *vr4100:
2009 *vr5000:
2010 // start-sanitize-vr4xxx
2011 *vr4121:
2012 // end-sanitize-vr4xxx
2013 // start-sanitize-vr4320
2014 *vr4320:
2015 // end-sanitize-vr4320
2016 // start-sanitize-cygnus
2017 *vr5400:
2018 // end-sanitize-cygnus
2019 // start-sanitize-r5900
2020 *r5900:
2021 // end-sanitize-r5900
2022 *r3900:
2023 // start-sanitize-tx19
2024 *tx19:
2025 // end-sanitize-tx19
2026 {
2027   /* NOTE: The region used is that of the delay slot NIA and NOT the
2028      current instruction */
2029   address_word region = (NIA & MASK (63, 28));
2030   DELAY_SLOT (region | (INSTR_INDEX << 2));
2031 }
2032
2033
2034 000011,26.INSTR_INDEX:NORMAL:32::JAL
2035 "jal <INSTR_INDEX>"
2036 *mipsI,mipsII,mipsIII,mipsIV:
2037 *vr4100:
2038 *vr5000:
2039 // start-sanitize-vr4xxx
2040 *vr4121:
2041 // end-sanitize-vr4xxx
2042 // start-sanitize-vr4320
2043 *vr4320:
2044 // end-sanitize-vr4320
2045 // start-sanitize-cygnus
2046 *vr5400:
2047 // end-sanitize-cygnus
2048 // start-sanitize-r5900
2049 *r5900:
2050 // end-sanitize-r5900
2051 *r3900:
2052 // start-sanitize-tx19
2053 *tx19:
2054 // end-sanitize-tx19
2055 {
2056   /* NOTE: The region used is that of the delay slot and NOT the
2057      current instruction */
2058   address_word region = (NIA & MASK (63, 28));
2059   GPR[31] = CIA + 8;
2060   DELAY_SLOT (region | (INSTR_INDEX << 2));
2061 }
2062
2063
2064 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
2065 "jalr r<RS>":RD == 31
2066 "jalr r<RD>, r<RS>"
2067 *mipsI,mipsII,mipsIII,mipsIV:
2068 *vr4100:
2069 *vr5000:
2070 // start-sanitize-vr4xxx
2071 *vr4121:
2072 // end-sanitize-vr4xxx
2073 // start-sanitize-vr4320
2074 *vr4320:
2075 // end-sanitize-vr4320
2076 // start-sanitize-cygnus
2077 *vr5400:
2078 // end-sanitize-cygnus
2079 // start-sanitize-r5900
2080 *r5900:
2081 // end-sanitize-r5900
2082 *r3900:
2083 // start-sanitize-tx19
2084 *tx19:
2085 // end-sanitize-tx19
2086 {
2087   address_word temp = GPR[RS];
2088   GPR[RD] = CIA + 8;
2089   DELAY_SLOT (temp);
2090 }
2091
2092
2093 000000,5.RS,000000000000000001000:SPECIAL:32::JR
2094 "jr r<RS>"
2095 *mipsI,mipsII,mipsIII,mipsIV:
2096 *vr4100:
2097 *vr5000:
2098 // start-sanitize-vr4xxx
2099 *vr4121:
2100 // end-sanitize-vr4xxx
2101 // start-sanitize-vr4320
2102 *vr4320:
2103 // end-sanitize-vr4320
2104 // start-sanitize-cygnus
2105 *vr5400:
2106 // end-sanitize-cygnus
2107 // start-sanitize-r5900
2108 *r5900:
2109 // end-sanitize-r5900
2110 *r3900:
2111 // start-sanitize-tx19
2112 *tx19:
2113 // end-sanitize-tx19
2114 {
2115   DELAY_SLOT (GPR[RS]);
2116 }
2117
2118
2119 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
2120 {
2121   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2122   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2123   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2124   unsigned int byte;
2125   address_word paddr;
2126   int uncached;
2127   unsigned64 memval;
2128   address_word vaddr;
2129
2130   vaddr = base + offset;
2131   if ((vaddr & access) != 0)
2132     SignalExceptionAddressLoad ();
2133   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2134   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2135   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2136   byte = ((vaddr & mask) ^ bigendiancpu);
2137   return (memval >> (8 * byte));
2138 }
2139
2140
2141 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2142 "lb r<RT>, <OFFSET>(r<BASE>)"
2143 *mipsI,mipsII,mipsIII,mipsIV:
2144 *vr4100:
2145 *vr5000:
2146 // start-sanitize-vr4xxx
2147 *vr4121:
2148 // end-sanitize-vr4xxx
2149 // start-sanitize-vr4320
2150 *vr4320:
2151 // end-sanitize-vr4320
2152 // start-sanitize-cygnus
2153 *vr5400:
2154 // end-sanitize-cygnus
2155 // start-sanitize-r5900
2156 *r5900:
2157 // end-sanitize-r5900
2158 *r3900:
2159 // start-sanitize-tx19
2160 *tx19:
2161 // end-sanitize-tx19
2162 {
2163   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2164 }
2165
2166
2167 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2168 "lbu r<RT>, <OFFSET>(r<BASE>)"
2169 *mipsI,mipsII,mipsIII,mipsIV:
2170 *vr4100:
2171 *vr5000:
2172 // start-sanitize-vr4xxx
2173 *vr4121:
2174 // end-sanitize-vr4xxx
2175 // start-sanitize-vr4320
2176 *vr4320:
2177 // end-sanitize-vr4320
2178 // start-sanitize-cygnus
2179 *vr5400:
2180 // end-sanitize-cygnus
2181 // start-sanitize-r5900
2182 *r5900:
2183 // end-sanitize-r5900
2184 *r3900:
2185 // start-sanitize-tx19
2186 *tx19:
2187 // end-sanitize-tx19
2188 {
2189   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2190 }
2191
2192
2193 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2194 "ld r<RT>, <OFFSET>(r<BASE>)"
2195 *mipsIII:
2196 *mipsIV:
2197 *vr4100:
2198 *vr5000:
2199 // start-sanitize-vr4xxx
2200 *vr4121:
2201 // end-sanitize-vr4xxx
2202 // start-sanitize-vr4320
2203 *vr4320:
2204 // end-sanitize-vr4320
2205 // start-sanitize-cygnus
2206 *vr5400:
2207 // end-sanitize-cygnus
2208 // start-sanitize-r5900
2209 *r5900:
2210 // end-sanitize-r5900
2211 // start-sanitize-tx19
2212 *tx19:
2213 // end-sanitize-tx19
2214 {
2215   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2216 }
2217
2218
2219 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2220 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2221 *mipsII:
2222 *mipsIII:
2223 *mipsIV:
2224 *vr4100:
2225 *vr5000:
2226 // start-sanitize-vr4xxx
2227 *vr4121:
2228 // end-sanitize-vr4xxx
2229 // start-sanitize-vr4320
2230 *vr4320:
2231 // end-sanitize-vr4320
2232 // start-sanitize-cygnus
2233 *vr5400:
2234 // end-sanitize-cygnus
2235 *r3900:
2236 // start-sanitize-tx19
2237 *tx19:
2238 // end-sanitize-tx19
2239 {
2240   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2241 }
2242
2243
2244
2245
2246 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2247 "ldl r<RT>, <OFFSET>(r<BASE>)"
2248 *mipsIII:
2249 *mipsIV:
2250 *vr4100:
2251 *vr5000:
2252 // start-sanitize-vr4xxx
2253 *vr4121:
2254 // end-sanitize-vr4xxx
2255 // start-sanitize-vr4320
2256 *vr4320:
2257 // end-sanitize-vr4320
2258 // start-sanitize-cygnus
2259 *vr5400:
2260 // end-sanitize-cygnus
2261 // start-sanitize-r5900
2262 *r5900:
2263 // end-sanitize-r5900
2264 // start-sanitize-tx19
2265 *tx19:
2266 // end-sanitize-tx19
2267 {
2268   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2269 }
2270
2271
2272 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2273 "ldr r<RT>, <OFFSET>(r<BASE>)"
2274 *mipsIII:
2275 *mipsIV:
2276 *vr4100:
2277 *vr5000:
2278 // start-sanitize-vr4xxx
2279 *vr4121:
2280 // end-sanitize-vr4xxx
2281 // start-sanitize-vr4320
2282 *vr4320:
2283 // end-sanitize-vr4320
2284 // start-sanitize-cygnus
2285 *vr5400:
2286 // end-sanitize-cygnus
2287 // start-sanitize-r5900
2288 *r5900:
2289 // end-sanitize-r5900
2290 // start-sanitize-tx19
2291 *tx19:
2292 // end-sanitize-tx19
2293 {
2294   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2295 }
2296
2297
2298 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2299 "lh r<RT>, <OFFSET>(r<BASE>)"
2300 *mipsI,mipsII,mipsIII,mipsIV:
2301 *vr4100:
2302 *vr5000:
2303 // start-sanitize-vr4xxx
2304 *vr4121:
2305 // end-sanitize-vr4xxx
2306 // start-sanitize-vr4320
2307 *vr4320:
2308 // end-sanitize-vr4320
2309 // start-sanitize-cygnus
2310 *vr5400:
2311 // end-sanitize-cygnus
2312 // start-sanitize-r5900
2313 *r5900:
2314 // end-sanitize-r5900
2315 *r3900:
2316 // start-sanitize-tx19
2317 *tx19:
2318 // end-sanitize-tx19
2319 {
2320   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2321 }
2322
2323
2324 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2325 "lhu r<RT>, <OFFSET>(r<BASE>)"
2326 *mipsI,mipsII,mipsIII,mipsIV:
2327 *vr4100:
2328 *vr5000:
2329 // start-sanitize-vr4xxx
2330 *vr4121:
2331 // end-sanitize-vr4xxx
2332 // start-sanitize-vr4320
2333 *vr4320:
2334 // end-sanitize-vr4320
2335 // start-sanitize-cygnus
2336 *vr5400:
2337 // end-sanitize-cygnus
2338 // start-sanitize-r5900
2339 *r5900:
2340 // end-sanitize-r5900
2341 *r3900:
2342 // start-sanitize-tx19
2343 *tx19:
2344 // end-sanitize-tx19
2345 {
2346   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2347 }
2348
2349
2350 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2351 "ll r<RT>, <OFFSET>(r<BASE>)"
2352 *mipsII:
2353 *mipsIII:
2354 *mipsIV:
2355 *vr4100:
2356 *vr5000:
2357 // start-sanitize-vr4xxx
2358 *vr4121:
2359 // end-sanitize-vr4xxx
2360 // start-sanitize-vr4320
2361 *vr4320:
2362 // end-sanitize-vr4320
2363 // start-sanitize-cygnus
2364 *vr5400:
2365 // end-sanitize-cygnus
2366 // start-sanitize-r5900
2367 *r5900:
2368 // end-sanitize-r5900
2369 // start-sanitize-tx19
2370 *tx19:
2371 // end-sanitize-tx19
2372 {
2373   unsigned32 instruction = instruction_0;
2374   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2375   int destreg = ((instruction >> 16) & 0x0000001F);
2376   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2377   {
2378     address_word vaddr = ((unsigned64)op1 + offset);
2379     address_word paddr;
2380     int uncached;
2381     if ((vaddr & 3) != 0)
2382       SignalExceptionAddressLoad();
2383     else
2384       {
2385         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2386           {
2387             unsigned64 memval = 0;
2388             unsigned64 memval1 = 0;
2389             unsigned64 mask = 0x7;
2390             unsigned int shift = 2;
2391             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2392             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2393             unsigned int byte;
2394             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2395             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2396             byte = ((vaddr & mask) ^ (bigend << shift));
2397             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2398             LLBIT = 1;
2399           }
2400       }
2401   }
2402 }
2403
2404
2405 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2406 "lld r<RT>, <OFFSET>(r<BASE>)"
2407 *mipsIII:
2408 *mipsIV:
2409 *vr4100:
2410 *vr5000:
2411 // start-sanitize-vr4xxx
2412 *vr4121:
2413 // end-sanitize-vr4xxx
2414 // start-sanitize-vr4320
2415 *vr4320:
2416 // end-sanitize-vr4320
2417 // start-sanitize-cygnus
2418 *vr5400:
2419 // end-sanitize-cygnus
2420 // start-sanitize-r5900
2421 *r5900:
2422 // end-sanitize-r5900
2423 // start-sanitize-tx19
2424 *tx19:
2425 // end-sanitize-tx19
2426 {
2427   unsigned32 instruction = instruction_0;
2428   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2429   int destreg = ((instruction >> 16) & 0x0000001F);
2430   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2431   {
2432     address_word vaddr = ((unsigned64)op1 + offset);
2433     address_word paddr;
2434     int uncached;
2435     if ((vaddr & 7) != 0)
2436       SignalExceptionAddressLoad();
2437     else
2438       {
2439         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2440           {
2441             unsigned64 memval = 0;
2442             unsigned64 memval1 = 0;
2443             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2444             GPR[destreg] = memval;
2445             LLBIT = 1;
2446           }
2447       }
2448   }
2449 }
2450
2451
2452 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2453 "lui r<RT>, <IMMEDIATE>"
2454 *mipsI,mipsII,mipsIII,mipsIV:
2455 *vr4100:
2456 *vr5000:
2457 // start-sanitize-vr4xxx
2458 *vr4121:
2459 // end-sanitize-vr4xxx
2460 // start-sanitize-vr4320
2461 *vr4320:
2462 // end-sanitize-vr4320
2463 // start-sanitize-cygnus
2464 *vr5400:
2465 // end-sanitize-cygnus
2466 // start-sanitize-r5900
2467 *r5900:
2468 // end-sanitize-r5900
2469 *r3900:
2470 // start-sanitize-tx19
2471 *tx19:
2472 // end-sanitize-tx19
2473 {
2474   TRACE_ALU_INPUT1 (IMMEDIATE);
2475   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2476   TRACE_ALU_RESULT (GPR[RT]);
2477 }
2478
2479
2480 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2481 "lw r<RT>, <OFFSET>(r<BASE>)"
2482 *mipsI,mipsII,mipsIII,mipsIV:
2483 *vr4100:
2484 *vr5000:
2485 // start-sanitize-vr4xxx
2486 *vr4121:
2487 // end-sanitize-vr4xxx
2488 // start-sanitize-vr4320
2489 *vr4320:
2490 // end-sanitize-vr4320
2491 // start-sanitize-cygnus
2492 *vr5400:
2493 // end-sanitize-cygnus
2494 // start-sanitize-r5900
2495 *r5900:
2496 // end-sanitize-r5900
2497 *r3900:
2498 // start-sanitize-tx19
2499 *tx19:
2500 // end-sanitize-tx19
2501 {
2502   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2503 }
2504
2505
2506 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2507 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2508 *mipsI,mipsII,mipsIII,mipsIV:
2509 *vr4100:
2510 *vr5000:
2511 // start-sanitize-vr4xxx
2512 *vr4121:
2513 // end-sanitize-vr4xxx
2514 // start-sanitize-vr4320
2515 *vr4320:
2516 // end-sanitize-vr4320
2517 // start-sanitize-cygnus
2518 *vr5400:
2519 // end-sanitize-cygnus
2520 // start-sanitize-r5900
2521 *r5900:
2522 // end-sanitize-r5900
2523 *r3900:
2524 // start-sanitize-tx19
2525 *tx19:
2526 // end-sanitize-tx19
2527 {
2528   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2529 }
2530
2531
2532 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2533 {
2534   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2535   address_word reverseendian = (ReverseEndian ? -1 : 0);
2536   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2537   unsigned int byte;
2538   unsigned int word;
2539   address_word paddr;
2540   int uncached;
2541   unsigned64 memval;
2542   address_word vaddr;
2543   int nr_lhs_bits;
2544   int nr_rhs_bits;
2545   unsigned_word lhs_mask;
2546   unsigned_word temp;
2547
2548   vaddr = base + offset;
2549   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2550   paddr = (paddr ^ (reverseendian & mask));
2551   if (BigEndianMem == 0)
2552     paddr = paddr & ~access;
2553
2554   /* compute where within the word/mem we are */
2555   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2556   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2557   nr_lhs_bits = 8 * byte + 8;
2558   nr_rhs_bits = 8 * access - 8 * byte;
2559   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2560
2561   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2562            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2563            (long) ((unsigned64) paddr >> 32), (long) paddr,
2564            word, byte, nr_lhs_bits, nr_rhs_bits); */
2565
2566   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2567   if (word == 0)
2568     {
2569       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2570       temp = (memval << nr_rhs_bits);
2571     }
2572   else
2573     {
2574       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2575       temp = (memval >> nr_lhs_bits);
2576     }
2577   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2578   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2579
2580   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2581            (long) ((unsigned64) memval >> 32), (long) memval,
2582            (long) ((unsigned64) temp >> 32), (long) temp,
2583            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2584            (long) (rt >> 32), (long) rt); */
2585   return rt;
2586 }
2587
2588
2589 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2590 "lwl r<RT>, <OFFSET>(r<BASE>)"
2591 *mipsI,mipsII,mipsIII,mipsIV:
2592 *vr4100:
2593 *vr5000:
2594 // start-sanitize-vr4xxx
2595 *vr4121:
2596 // end-sanitize-vr4xxx
2597 // start-sanitize-vr4320
2598 *vr4320:
2599 // end-sanitize-vr4320
2600 // start-sanitize-cygnus
2601 *vr5400:
2602 // end-sanitize-cygnus
2603 // start-sanitize-r5900
2604 *r5900:
2605 // end-sanitize-r5900
2606 *r3900:
2607 // start-sanitize-tx19
2608 *tx19:
2609 // end-sanitize-tx19
2610 {
2611   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2612 }
2613
2614
2615 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2616 {
2617   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2618   address_word reverseendian = (ReverseEndian ? -1 : 0);
2619   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2620   unsigned int byte;
2621   address_word paddr;
2622   int uncached;
2623   unsigned64 memval;
2624   address_word vaddr;
2625
2626   vaddr = base + offset;
2627   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2628   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2629   paddr = (paddr ^ (reverseendian & mask));
2630   if (BigEndianMem != 0)
2631     paddr = paddr & ~access;
2632   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2633   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2634   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2635   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2636      (long) paddr, byte, (long) paddr, (long) memval); */
2637   {
2638     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2639     rt &= ~screen;
2640     rt |= (memval >> (8 * byte)) & screen;
2641   }
2642   return rt;
2643 }
2644
2645
2646 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2647 "lwr r<RT>, <OFFSET>(r<BASE>)"
2648 *mipsI,mipsII,mipsIII,mipsIV:
2649 *vr4100:
2650 *vr5000:
2651 // start-sanitize-vr4xxx
2652 *vr4121:
2653 // end-sanitize-vr4xxx
2654 // start-sanitize-vr4320
2655 *vr4320:
2656 // end-sanitize-vr4320
2657 // start-sanitize-cygnus
2658 *vr5400:
2659 // end-sanitize-cygnus
2660 // start-sanitize-r5900
2661 *r5900:
2662 // end-sanitize-r5900
2663 *r3900:
2664 // start-sanitize-tx19
2665 *tx19:
2666 // end-sanitize-tx19
2667 {
2668   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2669 }
2670
2671
2672 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2673 "lwu r<RT>, <OFFSET>(r<BASE>)"
2674 *mipsIII:
2675 *mipsIV:
2676 *vr4100:
2677 *vr5000:
2678 // start-sanitize-vr4xxx
2679 *vr4121:
2680 // end-sanitize-vr4xxx
2681 // start-sanitize-vr4320
2682 *vr4320:
2683 // end-sanitize-vr4320
2684 // start-sanitize-cygnus
2685 *vr5400:
2686 // end-sanitize-cygnus
2687 // start-sanitize-r5900
2688 *r5900:
2689 // end-sanitize-r5900
2690 // start-sanitize-tx19
2691 *tx19:
2692 // end-sanitize-tx19
2693 {
2694   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2695 }
2696
2697
2698 :function:::void:do_mfhi:int rd
2699 {
2700   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2701   TRACE_ALU_INPUT1 (HI);
2702   GPR[rd] = HI;
2703   TRACE_ALU_RESULT (GPR[rd]);
2704 }
2705
2706 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2707 "mfhi r<RD>"
2708 *mipsI,mipsII,mipsIII,mipsIV:
2709 *vr4100:
2710 *vr5000:
2711 // start-sanitize-vr4xxx
2712 *vr4121:
2713 // end-sanitize-vr4xxx
2714 // start-sanitize-vr4320
2715 *vr4320:
2716 // end-sanitize-vr4320
2717 // start-sanitize-cygnus
2718 *vr5400:
2719 // end-sanitize-cygnus
2720 // start-sanitize-r5900
2721 *r5900:
2722 // end-sanitize-r5900
2723 *r3900:
2724 // start-sanitize-tx19
2725 *tx19:
2726 // end-sanitize-tx19
2727 {
2728   do_mfhi (SD_, RD);
2729 }
2730
2731
2732
2733 :function:::void:do_mflo:int rd
2734 {
2735   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2736   TRACE_ALU_INPUT1 (LO);
2737   GPR[rd] = LO;
2738   TRACE_ALU_RESULT (GPR[rd]);
2739 }
2740
2741 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2742 "mflo r<RD>"
2743 *mipsI,mipsII,mipsIII,mipsIV:
2744 *vr4100:
2745 *vr5000:
2746 // start-sanitize-vr4xxx
2747 *vr4121:
2748 // end-sanitize-vr4xxx
2749 // start-sanitize-vr4320
2750 *vr4320:
2751 // end-sanitize-vr4320
2752 // start-sanitize-cygnus
2753 *vr5400:
2754 // end-sanitize-cygnus
2755 // start-sanitize-r5900
2756 *r5900:
2757 // end-sanitize-r5900
2758 *r3900:
2759 // start-sanitize-tx19
2760 *tx19:
2761 // end-sanitize-tx19
2762 {
2763   do_mflo (SD_, RD);
2764 }
2765
2766
2767
2768 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2769 "movn r<RD>, r<RS>, r<RT>"
2770 *mipsIV:
2771 *vr5000:
2772 // start-sanitize-vr4xxx
2773 *vr4121:
2774 // end-sanitize-vr4xxx
2775 // start-sanitize-vr4320
2776 *vr4320:
2777 // end-sanitize-vr4320
2778 // start-sanitize-cygnus
2779 *vr5400:
2780 // end-sanitize-cygnus
2781 // start-sanitize-r5900
2782 *r5900:
2783 // end-sanitize-r5900
2784 {
2785   if (GPR[RT] != 0)
2786     GPR[RD] = GPR[RS];
2787 }
2788
2789
2790
2791 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2792 "movz r<RD>, r<RS>, r<RT>"
2793 *mipsIV:
2794 *vr5000:
2795 // start-sanitize-vr4320
2796 *vr4320:
2797 // end-sanitize-vr4320
2798 // start-sanitize-cygnus
2799 *vr5400:
2800 // end-sanitize-cygnus
2801 // start-sanitize-r5900
2802 *r5900:
2803 // end-sanitize-r5900
2804 {
2805   if (GPR[RT] == 0)
2806     GPR[RD] = GPR[RS];
2807 }
2808
2809
2810
2811 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2812 "mthi r<RS>"
2813 *mipsI,mipsII,mipsIII,mipsIV:
2814 *vr4100:
2815 *vr5000:
2816 // start-sanitize-vr4xxx
2817 *vr4121:
2818 // end-sanitize-vr4xxx
2819 // start-sanitize-vr4320
2820 *vr4320:
2821 // end-sanitize-vr4320
2822 // start-sanitize-cygnus
2823 *vr5400:
2824 // end-sanitize-cygnus
2825 // start-sanitize-r5900
2826 *r5900:
2827 // end-sanitize-r5900
2828 *r3900:
2829 // start-sanitize-tx19
2830 *tx19:
2831 // end-sanitize-tx19
2832 {
2833   check_mt_hilo (SD_, HIHISTORY);
2834   HI = GPR[RS];
2835 }
2836
2837
2838
2839 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2840 "mtlo r<RS>"
2841 *mipsI,mipsII,mipsIII,mipsIV:
2842 *vr4100:
2843 *vr5000:
2844 // start-sanitize-vr4xxx
2845 *vr4121:
2846 // end-sanitize-vr4xxx
2847 // start-sanitize-vr4320
2848 *vr4320:
2849 // end-sanitize-vr4320
2850 // start-sanitize-cygnus
2851 *vr5400:
2852 // end-sanitize-cygnus
2853 // start-sanitize-r5900
2854 *r5900:
2855 // end-sanitize-r5900
2856 *r3900:
2857 // start-sanitize-tx19
2858 *tx19:
2859 // end-sanitize-tx19
2860 {
2861   check_mt_hilo (SD_, LOHISTORY);
2862   LO = GPR[RS];
2863 }
2864
2865
2866
2867 :function:::void:do_mult:int rs, int rt, int rd
2868 {
2869   signed64 prod;
2870   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2871   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2872   prod = (((signed64)(signed32) GPR[rs])
2873           * ((signed64)(signed32) GPR[rt]));
2874   LO = EXTEND32 (VL4_8 (prod));
2875   HI = EXTEND32 (VH4_8 (prod));
2876   if (rd != 0)
2877     GPR[rd] = LO;
2878   TRACE_ALU_RESULT2 (HI, LO);
2879 }
2880
2881 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2882 "mult r<RS>, r<RT>"
2883 *mipsI,mipsII,mipsIII,mipsIV:
2884 *vr4100:
2885 // start-sanitize-vr4xxx
2886 *vr4121:
2887 // end-sanitize-vr4xxx
2888 // start-sanitize-vr4320
2889 *vr4320:
2890 // end-sanitize-vr4320
2891 {
2892   do_mult (SD_, RS, RT, 0);
2893 }
2894
2895
2896 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2897 "mult r<RD>, r<RS>, r<RT>"
2898 *vr5000:
2899 // start-sanitize-cygnus
2900 *vr5400:
2901 // end-sanitize-cygnus
2902 // start-sanitize-r5900
2903 *r5900:
2904 // end-sanitize-r5900
2905 *r3900:
2906 // start-sanitize-tx19
2907 *tx19:
2908 // end-sanitize-tx19
2909 {
2910   do_mult (SD_, RS, RT, RD);
2911 }
2912
2913
2914 :function:::void:do_multu:int rs, int rt, int rd
2915 {
2916   unsigned64 prod;
2917   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2918   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2919   prod = (((unsigned64)(unsigned32) GPR[rs])
2920           * ((unsigned64)(unsigned32) GPR[rt]));
2921   LO = EXTEND32 (VL4_8 (prod));
2922   HI = EXTEND32 (VH4_8 (prod));
2923   if (rd != 0)
2924     GPR[rd] = LO;
2925   TRACE_ALU_RESULT2 (HI, LO);
2926 }
2927
2928 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2929 "multu r<RS>, r<RT>"
2930 *mipsI,mipsII,mipsIII,mipsIV:
2931 *vr4100:
2932 // start-sanitize-vr4xxx
2933 *vr4121:
2934 // end-sanitize-vr4xxx
2935 // start-sanitize-vr4320
2936 *vr4320:
2937 // end-sanitize-vr4320
2938 {
2939   do_multu (SD_, RS, RT, 0);
2940 }
2941
2942 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2943 "multu r<RD>, r<RS>, r<RT>"
2944 *vr5000:
2945 // start-sanitize-cygnus
2946 *vr5400:
2947 // end-sanitize-cygnus
2948 // start-sanitize-r5900
2949 *r5900:
2950 // end-sanitize-r5900
2951 *r3900:
2952 // start-sanitize-tx19
2953 *tx19:
2954 // end-sanitize-tx19
2955 {
2956   do_multu (SD_, RS, RT, 0);
2957 }
2958
2959
2960 :function:::void:do_nor:int rs, int rt, int rd
2961 {
2962   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2963   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2964   TRACE_ALU_RESULT (GPR[rd]);
2965 }
2966
2967 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2968 "nor r<RD>, r<RS>, r<RT>"
2969 *mipsI,mipsII,mipsIII,mipsIV:
2970 *vr4100:
2971 *vr5000:
2972 // start-sanitize-vr4xxx
2973 *vr4121:
2974 // end-sanitize-vr4xxx
2975 // start-sanitize-vr4320
2976 *vr4320:
2977 // end-sanitize-vr4320
2978 // start-sanitize-cygnus
2979 *vr5400:
2980 // end-sanitize-cygnus
2981 // start-sanitize-r5900
2982 *r5900:
2983 // end-sanitize-r5900
2984 *r3900:
2985 // start-sanitize-tx19
2986 *tx19:
2987 // end-sanitize-tx19
2988 {
2989   do_nor (SD_, RS, RT, RD);
2990 }
2991
2992
2993 :function:::void:do_or:int rs, int rt, int rd
2994 {
2995   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2996   GPR[rd] = (GPR[rs] | GPR[rt]);
2997   TRACE_ALU_RESULT (GPR[rd]);
2998 }
2999
3000 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
3001 "or r<RD>, r<RS>, r<RT>"
3002 *mipsI,mipsII,mipsIII,mipsIV:
3003 *vr4100:
3004 *vr5000:
3005 // start-sanitize-vr4xxx
3006 *vr4121:
3007 // end-sanitize-vr4xxx
3008 // start-sanitize-vr4320
3009 *vr4320:
3010 // end-sanitize-vr4320
3011 // start-sanitize-cygnus
3012 *vr5400:
3013 // end-sanitize-cygnus
3014 // start-sanitize-r5900
3015 *r5900:
3016 // end-sanitize-r5900
3017 *r3900:
3018 // start-sanitize-tx19
3019 *tx19:
3020 // end-sanitize-tx19
3021 {
3022   do_or (SD_, RS, RT, RD);
3023 }
3024
3025
3026
3027 :function:::void:do_ori:int rs, int rt, unsigned immediate
3028 {
3029   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3030   GPR[rt] = (GPR[rs] | immediate);
3031   TRACE_ALU_RESULT (GPR[rt]);
3032 }
3033
3034 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
3035 "ori r<RT>, r<RS>, <IMMEDIATE>"
3036 *mipsI,mipsII,mipsIII,mipsIV:
3037 *vr4100:
3038 *vr5000:
3039 // start-sanitize-vr4xxx
3040 *vr4121:
3041 // end-sanitize-vr4xxx
3042 // start-sanitize-vr4320
3043 *vr4320:
3044 // end-sanitize-vr4320
3045 // start-sanitize-cygnus
3046 *vr5400:
3047 // end-sanitize-cygnus
3048 // start-sanitize-r5900
3049 *r5900:
3050 // end-sanitize-r5900
3051 *r3900:
3052 // start-sanitize-tx19
3053 *tx19:
3054 // end-sanitize-tx19
3055 {
3056   do_ori (SD_, RS, RT, IMMEDIATE);
3057 }
3058
3059
3060 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
3061 *mipsIV:
3062 *vr5000:
3063 // start-sanitize-vr4320
3064 *vr4320:
3065 // end-sanitize-vr4320
3066 // start-sanitize-cygnus
3067 *vr5400:
3068 // end-sanitize-cygnus
3069 // start-sanitize-r5900
3070 *r5900:
3071 // end-sanitize-r5900
3072 {
3073   unsigned32 instruction = instruction_0;
3074   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3075   int hint = ((instruction >> 16) & 0x0000001F);
3076   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3077   {
3078     address_word vaddr = ((unsigned64)op1 + offset);
3079     address_word paddr;
3080     int uncached;
3081     {
3082       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3083         Prefetch(uncached,paddr,vaddr,isDATA,hint);
3084     }
3085   }
3086 }
3087
3088 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3089 {
3090   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3091   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3092   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3093   unsigned int byte;
3094   address_word paddr;
3095   int uncached;
3096   unsigned64 memval;
3097   address_word vaddr;
3098
3099   vaddr = base + offset;
3100   if ((vaddr & access) != 0)
3101     SignalExceptionAddressStore ();
3102   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3103   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3104   byte = ((vaddr & mask) ^ bigendiancpu);
3105   memval = (word << (8 * byte));
3106   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3107 }
3108
3109
3110 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3111 "sb r<RT>, <OFFSET>(r<BASE>)"
3112 *mipsI,mipsII,mipsIII,mipsIV:
3113 *vr4100:
3114 *vr5000:
3115 // start-sanitize-vr4xxx
3116 *vr4121:
3117 // end-sanitize-vr4xxx
3118 // start-sanitize-vr4320
3119 *vr4320:
3120 // end-sanitize-vr4320
3121 // start-sanitize-cygnus
3122 *vr5400:
3123 // end-sanitize-cygnus
3124 // start-sanitize-r5900
3125 *r5900:
3126 // end-sanitize-r5900
3127 *r3900:
3128 // start-sanitize-tx19
3129 *tx19:
3130 // end-sanitize-tx19
3131 {
3132   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3133 }
3134
3135
3136 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3137 "sc r<RT>, <OFFSET>(r<BASE>)"
3138 *mipsII:
3139 *mipsIII:
3140 *mipsIV:
3141 *vr4100:
3142 *vr5000:
3143 // start-sanitize-vr4xxx
3144 *vr4121:
3145 // end-sanitize-vr4xxx
3146 // start-sanitize-vr4320
3147 *vr4320:
3148 // end-sanitize-vr4320
3149 // start-sanitize-cygnus
3150 *vr5400:
3151 // end-sanitize-cygnus
3152 // start-sanitize-r5900
3153 *r5900:
3154 // end-sanitize-r5900
3155 // start-sanitize-tx19
3156 *tx19:
3157 // end-sanitize-tx19
3158 {
3159   unsigned32 instruction = instruction_0;
3160   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3161   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3162   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3163   {
3164     address_word vaddr = ((unsigned64)op1 + offset);
3165     address_word paddr;
3166     int uncached;
3167     if ((vaddr & 3) != 0)
3168       SignalExceptionAddressStore();
3169     else
3170       {
3171         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3172           {
3173             unsigned64 memval = 0;
3174             unsigned64 memval1 = 0;
3175             unsigned64 mask = 0x7;
3176             unsigned int byte;
3177             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3178             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3179             memval = ((unsigned64) op2 << (8 * byte));
3180             if (LLBIT)
3181               {
3182                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3183               }
3184             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3185           }
3186       }
3187   }
3188 }
3189
3190
3191 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3192 "scd r<RT>, <OFFSET>(r<BASE>)"
3193 *mipsIII:
3194 *mipsIV:
3195 *vr4100:
3196 *vr5000:
3197 // start-sanitize-vr4xxx
3198 *vr4121:
3199 // end-sanitize-vr4xxx
3200 // start-sanitize-vr4320
3201 *vr4320:
3202 // end-sanitize-vr4320
3203 // start-sanitize-cygnus
3204 *vr5400:
3205 // end-sanitize-cygnus
3206 // start-sanitize-r5900
3207 *r5900:
3208 // end-sanitize-r5900
3209 // start-sanitize-tx19
3210 *tx19:
3211 // end-sanitize-tx19
3212 {
3213   unsigned32 instruction = instruction_0;
3214   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3215   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3216   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3217   {
3218     address_word vaddr = ((unsigned64)op1 + offset);
3219     address_word paddr;
3220     int uncached;
3221     if ((vaddr & 7) != 0)
3222       SignalExceptionAddressStore();
3223     else
3224       {
3225         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3226           {
3227             unsigned64 memval = 0;
3228             unsigned64 memval1 = 0;
3229             memval = op2;
3230             if (LLBIT)
3231               {
3232                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3233               }
3234             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
3235           }
3236       }
3237   }
3238 }
3239
3240
3241 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3242 "sd r<RT>, <OFFSET>(r<BASE>)"
3243 *mipsIII:
3244 *mipsIV:
3245 *vr4100:
3246 *vr5000:
3247 // start-sanitize-vr4xxx
3248 *vr4121:
3249 // end-sanitize-vr4xxx
3250 // start-sanitize-vr4320
3251 *vr4320:
3252 // end-sanitize-vr4320
3253 // start-sanitize-cygnus
3254 *vr5400:
3255 // end-sanitize-cygnus
3256 // start-sanitize-r5900
3257 *r5900:
3258 // end-sanitize-r5900
3259 // start-sanitize-tx19
3260 *tx19:
3261 // end-sanitize-tx19
3262 {
3263   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3264 }
3265
3266
3267 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3268 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3269 *mipsII:
3270 *mipsIII:
3271 *mipsIV:
3272 *vr4100:
3273 *vr5000:
3274 // start-sanitize-vr4xxx
3275 *vr4121:
3276 // end-sanitize-vr4xxx
3277 // start-sanitize-vr4320
3278 *vr4320:
3279 // end-sanitize-vr4320
3280 // start-sanitize-cygnus
3281 *vr5400:
3282 // end-sanitize-cygnus
3283 // start-sanitize-tx19
3284 *tx19:
3285 // end-sanitize-tx19
3286 {
3287   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3288 }
3289
3290
3291 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3292 "sdl r<RT>, <OFFSET>(r<BASE>)"
3293 *mipsIII:
3294 *mipsIV:
3295 *vr4100:
3296 *vr5000:
3297 // start-sanitize-vr4xxx
3298 *vr4121:
3299 // end-sanitize-vr4xxx
3300 // start-sanitize-vr4320
3301 *vr4320:
3302 // end-sanitize-vr4320
3303 // start-sanitize-cygnus
3304 *vr5400:
3305 // end-sanitize-cygnus
3306 // start-sanitize-r5900
3307 *r5900:
3308 // end-sanitize-r5900
3309 // start-sanitize-tx19
3310 *tx19:
3311 // end-sanitize-tx19
3312 {
3313   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3314 }
3315
3316
3317 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3318 "sdr r<RT>, <OFFSET>(r<BASE>)"
3319 *mipsIII:
3320 *mipsIV:
3321 *vr4100:
3322 *vr5000:
3323 // start-sanitize-vr4xxx
3324 *vr4121:
3325 // end-sanitize-vr4xxx
3326 // start-sanitize-vr4320
3327 *vr4320:
3328 // end-sanitize-vr4320
3329 // start-sanitize-cygnus
3330 *vr5400:
3331 // end-sanitize-cygnus
3332 // start-sanitize-r5900
3333 *r5900:
3334 // end-sanitize-r5900
3335 // start-sanitize-tx19
3336 *tx19:
3337 // end-sanitize-tx19
3338 {
3339   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3340 }
3341
3342
3343 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3344 "sh r<RT>, <OFFSET>(r<BASE>)"
3345 *mipsI,mipsII,mipsIII,mipsIV:
3346 *vr4100:
3347 *vr5000:
3348 // start-sanitize-vr4xxx
3349 *vr4121:
3350 // end-sanitize-vr4xxx
3351 // start-sanitize-vr4320
3352 *vr4320:
3353 // end-sanitize-vr4320
3354 // start-sanitize-cygnus
3355 *vr5400:
3356 // end-sanitize-cygnus
3357 // start-sanitize-r5900
3358 *r5900:
3359 // end-sanitize-r5900
3360 *r3900:
3361 // start-sanitize-tx19
3362 *tx19:
3363 // end-sanitize-tx19
3364 {
3365   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3366 }
3367
3368
3369 :function:::void:do_sll:int rt, int rd, int shift
3370 {
3371   unsigned32 temp = (GPR[rt] << shift);
3372   TRACE_ALU_INPUT2 (GPR[rt], shift);
3373   GPR[rd] = EXTEND32 (temp);
3374   TRACE_ALU_RESULT (GPR[rd]);
3375 }
3376
3377 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
3378 "sll r<RD>, r<RT>, <SHIFT>"
3379 *mipsI,mipsII,mipsIII,mipsIV:
3380 *vr4100:
3381 *vr5000:
3382 // start-sanitize-vr4xxx
3383 *vr4121:
3384 // end-sanitize-vr4xxx
3385 // start-sanitize-vr4320
3386 *vr4320:
3387 // end-sanitize-vr4320
3388 // start-sanitize-cygnus
3389 *vr5400:
3390 // end-sanitize-cygnus
3391 // start-sanitize-r5900
3392 *r5900:
3393 // end-sanitize-r5900
3394 *r3900:
3395 // start-sanitize-tx19
3396 *tx19:
3397 // end-sanitize-tx19
3398 {
3399   do_sll (SD_, RT, RD, SHIFT);
3400 }
3401
3402
3403 :function:::void:do_sllv:int rs, int rt, int rd
3404 {
3405   int s = MASKED (GPR[rs], 4, 0);
3406   unsigned32 temp = (GPR[rt] << s);
3407   TRACE_ALU_INPUT2 (GPR[rt], s);
3408   GPR[rd] = EXTEND32 (temp);
3409   TRACE_ALU_RESULT (GPR[rd]);
3410 }
3411
3412 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3413 "sllv r<RD>, r<RT>, r<RS>"
3414 *mipsI,mipsII,mipsIII,mipsIV:
3415 *vr4100:
3416 *vr5000:
3417 // start-sanitize-vr4xxx
3418 *vr4121:
3419 // end-sanitize-vr4xxx
3420 // start-sanitize-vr4320
3421 *vr4320:
3422 // end-sanitize-vr4320
3423 // start-sanitize-cygnus
3424 *vr5400:
3425 // end-sanitize-cygnus
3426 // start-sanitize-r5900
3427 *r5900:
3428 // end-sanitize-r5900
3429 *r3900:
3430 // start-sanitize-tx19
3431 *tx19:
3432 // end-sanitize-tx19
3433 {
3434   do_sllv (SD_, RS, RT, RD);
3435 }
3436
3437
3438 :function:::void:do_slt:int rs, int rt, int rd
3439 {
3440   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3441   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3442   TRACE_ALU_RESULT (GPR[rd]);
3443 }
3444
3445 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3446 "slt r<RD>, r<RS>, r<RT>"
3447 *mipsI,mipsII,mipsIII,mipsIV:
3448 *vr4100:
3449 *vr5000:
3450 // start-sanitize-vr4xxx
3451 *vr4121:
3452 // end-sanitize-vr4xxx
3453 // start-sanitize-vr4320
3454 *vr4320:
3455 // end-sanitize-vr4320
3456 // start-sanitize-cygnus
3457 *vr5400:
3458 // end-sanitize-cygnus
3459 // start-sanitize-r5900
3460 *r5900:
3461 // end-sanitize-r5900
3462 *r3900:
3463 // start-sanitize-tx19
3464 *tx19:
3465 // end-sanitize-tx19
3466 {
3467   do_slt (SD_, RS, RT, RD);
3468 }
3469
3470
3471 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3472 {
3473   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3474   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3475   TRACE_ALU_RESULT (GPR[rt]);
3476 }
3477
3478 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3479 "slti r<RT>, r<RS>, <IMMEDIATE>"
3480 *mipsI,mipsII,mipsIII,mipsIV:
3481 *vr4100:
3482 *vr5000:
3483 // start-sanitize-vr4xxx
3484 *vr4121:
3485 // end-sanitize-vr4xxx
3486 // start-sanitize-vr4320
3487 *vr4320:
3488 // end-sanitize-vr4320
3489 // start-sanitize-cygnus
3490 *vr5400:
3491 // end-sanitize-cygnus
3492 // start-sanitize-r5900
3493 *r5900:
3494 // end-sanitize-r5900
3495 *r3900:
3496 // start-sanitize-tx19
3497 *tx19:
3498 // end-sanitize-tx19
3499 {
3500   do_slti (SD_, RS, RT, IMMEDIATE);
3501 }
3502
3503
3504 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3505 {
3506   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3507   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3508   TRACE_ALU_RESULT (GPR[rt]);
3509 }
3510
3511 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3512 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3513 *mipsI,mipsII,mipsIII,mipsIV:
3514 *vr4100:
3515 *vr5000:
3516 // start-sanitize-vr4xxx
3517 *vr4121:
3518 // end-sanitize-vr4xxx
3519 // start-sanitize-vr4320
3520 *vr4320:
3521 // end-sanitize-vr4320
3522 // start-sanitize-cygnus
3523 *vr5400:
3524 // end-sanitize-cygnus
3525 // start-sanitize-r5900
3526 *r5900:
3527 // end-sanitize-r5900
3528 *r3900:
3529 // start-sanitize-tx19
3530 *tx19:
3531 // end-sanitize-tx19
3532 {
3533   do_sltiu (SD_, RS, RT, IMMEDIATE);
3534 }
3535
3536
3537
3538 :function:::void:do_sltu:int rs, int rt, int rd
3539 {
3540   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3541   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3542   TRACE_ALU_RESULT (GPR[rd]);
3543 }
3544
3545 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3546 "sltu r<RD>, r<RS>, r<RT>"
3547 *mipsI,mipsII,mipsIII,mipsIV:
3548 *vr4100:
3549 *vr5000:
3550 // start-sanitize-vr4xxx
3551 *vr4121:
3552 // end-sanitize-vr4xxx
3553 // start-sanitize-vr4320
3554 *vr4320:
3555 // end-sanitize-vr4320
3556 // start-sanitize-cygnus
3557 *vr5400:
3558 // end-sanitize-cygnus
3559 // start-sanitize-r5900
3560 *r5900:
3561 // end-sanitize-r5900
3562 *r3900:
3563 // start-sanitize-tx19
3564 *tx19:
3565 // end-sanitize-tx19
3566 {
3567   do_sltu (SD_, RS, RT, RD);
3568 }
3569
3570
3571 :function:::void:do_sra:int rt, int rd, int shift
3572 {
3573   signed32 temp = (signed32) GPR[rt] >> shift;
3574   TRACE_ALU_INPUT2 (GPR[rt], shift);
3575   GPR[rd] = EXTEND32 (temp);
3576   TRACE_ALU_RESULT (GPR[rd]);
3577 }
3578
3579 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3580 "sra r<RD>, r<RT>, <SHIFT>"
3581 *mipsI,mipsII,mipsIII,mipsIV:
3582 *vr4100:
3583 *vr5000:
3584 // start-sanitize-vr4xxx
3585 *vr4121:
3586 // end-sanitize-vr4xxx
3587 // start-sanitize-vr4320
3588 *vr4320:
3589 // end-sanitize-vr4320
3590 // start-sanitize-cygnus
3591 *vr5400:
3592 // end-sanitize-cygnus
3593 // start-sanitize-r5900
3594 *r5900:
3595 // end-sanitize-r5900
3596 *r3900:
3597 // start-sanitize-tx19
3598 *tx19:
3599 // end-sanitize-tx19
3600 {
3601   do_sra (SD_, RT, RD, SHIFT);
3602 }
3603
3604
3605
3606 :function:::void:do_srav:int rs, int rt, int rd
3607 {
3608   int s = MASKED (GPR[rs], 4, 0);
3609   signed32 temp = (signed32) GPR[rt] >> s;
3610   TRACE_ALU_INPUT2 (GPR[rt], s);
3611   GPR[rd] = EXTEND32 (temp);
3612   TRACE_ALU_RESULT (GPR[rd]);
3613 }
3614
3615 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3616 "srav r<RD>, r<RT>, r<RS>"
3617 *mipsI,mipsII,mipsIII,mipsIV:
3618 *vr4100:
3619 *vr5000:
3620 // start-sanitize-vr4xxx
3621 *vr4121:
3622 // end-sanitize-vr4xxx
3623 // start-sanitize-vr4320
3624 *vr4320:
3625 // end-sanitize-vr4320
3626 // start-sanitize-cygnus
3627 *vr5400:
3628 // end-sanitize-cygnus
3629 // start-sanitize-r5900
3630 *r5900:
3631 // end-sanitize-r5900
3632 *r3900:
3633 // start-sanitize-tx19
3634 *tx19:
3635 // end-sanitize-tx19
3636 {
3637   do_srav (SD_, RS, RT, RD);
3638 }
3639
3640
3641
3642 :function:::void:do_srl:int rt, int rd, int shift
3643 {
3644   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3645   TRACE_ALU_INPUT2 (GPR[rt], shift);
3646   GPR[rd] = EXTEND32 (temp);
3647   TRACE_ALU_RESULT (GPR[rd]);
3648 }
3649
3650 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3651 "srl r<RD>, r<RT>, <SHIFT>"
3652 *mipsI,mipsII,mipsIII,mipsIV:
3653 *vr4100:
3654 *vr5000:
3655 // start-sanitize-vr4xxx
3656 *vr4121:
3657 // end-sanitize-vr4xxx
3658 // start-sanitize-vr4320
3659 *vr4320:
3660 // end-sanitize-vr4320
3661 // start-sanitize-cygnus
3662 *vr5400:
3663 // end-sanitize-cygnus
3664 // start-sanitize-r5900
3665 *r5900:
3666 // end-sanitize-r5900
3667 *r3900:
3668 // start-sanitize-tx19
3669 *tx19:
3670 // end-sanitize-tx19
3671 {
3672   do_srl (SD_, RT, RD, SHIFT);
3673 }
3674
3675
3676 :function:::void:do_srlv:int rs, int rt, int rd
3677 {
3678   int s = MASKED (GPR[rs], 4, 0);
3679   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3680   TRACE_ALU_INPUT2 (GPR[rt], s);
3681   GPR[rd] = EXTEND32 (temp);
3682   TRACE_ALU_RESULT (GPR[rd]);
3683 }
3684
3685 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3686 "srlv r<RD>, r<RT>, r<RS>"
3687 *mipsI,mipsII,mipsIII,mipsIV:
3688 *vr4100:
3689 *vr5000:
3690 // start-sanitize-vr4xxx
3691 *vr4121:
3692 // end-sanitize-vr4xxx
3693 // start-sanitize-vr4320
3694 *vr4320:
3695 // end-sanitize-vr4320
3696 // start-sanitize-cygnus
3697 *vr5400:
3698 // end-sanitize-cygnus
3699 // start-sanitize-r5900
3700 *r5900:
3701 // end-sanitize-r5900
3702 *r3900:
3703 // start-sanitize-tx19
3704 *tx19:
3705 // end-sanitize-tx19
3706 {
3707   do_srlv (SD_, RS, RT, RD);
3708 }
3709
3710
3711 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3712 "sub r<RD>, r<RS>, r<RT>"
3713 *mipsI,mipsII,mipsIII,mipsIV:
3714 *vr4100:
3715 *vr5000:
3716 // start-sanitize-vr4xxx
3717 *vr4121:
3718 // end-sanitize-vr4xxx
3719 // start-sanitize-vr4320
3720 *vr4320:
3721 // end-sanitize-vr4320
3722 // start-sanitize-cygnus
3723 *vr5400:
3724 // end-sanitize-cygnus
3725 // start-sanitize-r5900
3726 *r5900:
3727 // end-sanitize-r5900
3728 *r3900:
3729 // start-sanitize-tx19
3730 *tx19:
3731 // end-sanitize-tx19
3732 {
3733   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3734   {
3735     ALU32_BEGIN (GPR[RS]);
3736     ALU32_SUB (GPR[RT]);
3737     ALU32_END (GPR[RD]);
3738   }
3739   TRACE_ALU_RESULT (GPR[RD]);
3740 }
3741
3742
3743 :function:::void:do_subu:int rs, int rt, int rd
3744 {
3745   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3746   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3747   TRACE_ALU_RESULT (GPR[rd]);
3748 }
3749
3750 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3751 "subu r<RD>, r<RS>, r<RT>"
3752 *mipsI,mipsII,mipsIII,mipsIV:
3753 *vr4100:
3754 *vr5000:
3755 // start-sanitize-vr4xxx
3756 *vr4121:
3757 // end-sanitize-vr4xxx
3758 // start-sanitize-vr4320
3759 *vr4320:
3760 // end-sanitize-vr4320
3761 // start-sanitize-cygnus
3762 *vr5400:
3763 // end-sanitize-cygnus
3764 // start-sanitize-r5900
3765 *r5900:
3766 // end-sanitize-r5900
3767 *r3900:
3768 // start-sanitize-tx19
3769 *tx19:
3770 // end-sanitize-tx19
3771 {
3772   do_subu (SD_, RS, RT, RD);
3773 }
3774
3775
3776 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3777 "sw r<RT>, <OFFSET>(r<BASE>)"
3778 *mipsI,mipsII,mipsIII,mipsIV:
3779 *vr4100:
3780 // start-sanitize-vr4xxx
3781 *vr4121:
3782 // end-sanitize-vr4xxx
3783 // start-sanitize-tx19
3784 *tx19:
3785 // end-sanitize-tx19
3786 *r3900:
3787 // start-sanitize-vr4320
3788 *vr4320:
3789 // end-sanitize-vr4320
3790 *vr5000:
3791 // start-sanitize-cygnus
3792 *vr5400:
3793 // end-sanitize-cygnus
3794 // start-sanitize-r5900
3795 *r5900:
3796 // end-sanitize-r5900
3797 {
3798   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3799 }
3800
3801
3802 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3803 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3804 *mipsI,mipsII,mipsIII,mipsIV:
3805 *vr4100:
3806 *vr5000:
3807 // start-sanitize-vr4xxx
3808 *vr4121:
3809 // end-sanitize-vr4xxx
3810 // start-sanitize-vr4320
3811 *vr4320:
3812 // end-sanitize-vr4320
3813 // start-sanitize-cygnus
3814 *vr5400:
3815 // end-sanitize-cygnus
3816 *r3900:
3817 // start-sanitize-tx19
3818 *tx19:
3819 // end-sanitize-tx19
3820 {
3821   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3822 }
3823
3824
3825
3826 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3827 {
3828   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3829   address_word reverseendian = (ReverseEndian ? -1 : 0);
3830   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3831   unsigned int byte;
3832   unsigned int word;
3833   address_word paddr;
3834   int uncached;
3835   unsigned64 memval;
3836   address_word vaddr;
3837   int nr_lhs_bits;
3838   int nr_rhs_bits;
3839
3840   vaddr = base + offset;
3841   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3842   paddr = (paddr ^ (reverseendian & mask));
3843   if (BigEndianMem == 0)
3844     paddr = paddr & ~access;
3845
3846   /* compute where within the word/mem we are */
3847   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3848   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3849   nr_lhs_bits = 8 * byte + 8;
3850   nr_rhs_bits = 8 * access - 8 * byte;
3851   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3852   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3853            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3854            (long) ((unsigned64) paddr >> 32), (long) paddr,
3855            word, byte, nr_lhs_bits, nr_rhs_bits); */
3856
3857   if (word == 0)
3858     {
3859       memval = (rt >> nr_rhs_bits);
3860     }
3861   else
3862     {
3863       memval = (rt << nr_lhs_bits);
3864     }
3865   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3866            (long) ((unsigned64) rt >> 32), (long) rt,
3867            (long) ((unsigned64) memval >> 32), (long) memval); */
3868   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3869 }
3870
3871
3872 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3873 "swl r<RT>, <OFFSET>(r<BASE>)"
3874 *mipsI,mipsII,mipsIII,mipsIV:
3875 *vr4100:
3876 *vr5000:
3877 // start-sanitize-vr4xxx
3878 *vr4121:
3879 // end-sanitize-vr4xxx
3880 // start-sanitize-vr4320
3881 *vr4320:
3882 // end-sanitize-vr4320
3883 // start-sanitize-cygnus
3884 *vr5400:
3885 // end-sanitize-cygnus
3886 // start-sanitize-r5900
3887 *r5900:
3888 // end-sanitize-r5900
3889 *r3900:
3890 // start-sanitize-tx19
3891 *tx19:
3892 // end-sanitize-tx19
3893 {
3894   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3895 }
3896
3897
3898 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3899 {
3900   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3901   address_word reverseendian = (ReverseEndian ? -1 : 0);
3902   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3903   unsigned int byte;
3904   address_word paddr;
3905   int uncached;
3906   unsigned64 memval;
3907   address_word vaddr;
3908
3909   vaddr = base + offset;
3910   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3911   paddr = (paddr ^ (reverseendian & mask));
3912   if (BigEndianMem != 0)
3913     paddr &= ~access;
3914   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3915   memval = (rt << (byte * 8));
3916   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3917 }
3918
3919 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3920 "swr r<RT>, <OFFSET>(r<BASE>)"
3921 *mipsI,mipsII,mipsIII,mipsIV:
3922 *vr4100:
3923 *vr5000:
3924 // start-sanitize-vr4xxx
3925 *vr4121:
3926 // end-sanitize-vr4xxx
3927 // start-sanitize-vr4320
3928 *vr4320:
3929 // end-sanitize-vr4320
3930 // start-sanitize-cygnus
3931 *vr5400:
3932 // end-sanitize-cygnus
3933 // start-sanitize-r5900
3934 *r5900:
3935 // end-sanitize-r5900
3936 *r3900:
3937 // start-sanitize-tx19
3938 *tx19:
3939 // end-sanitize-tx19
3940 {
3941   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3942 }
3943
3944
3945 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3946 "sync":STYPE == 0
3947 "sync <STYPE>"
3948 *mipsII:
3949 *mipsIII:
3950 *mipsIV:
3951 *vr4100:
3952 *vr5000:
3953 // start-sanitize-vr4xxx
3954 *vr4121:
3955 // end-sanitize-vr4xxx
3956 // start-sanitize-vr4320
3957 *vr4320:
3958 // end-sanitize-vr4320
3959 // start-sanitize-cygnus
3960 *vr5400:
3961 // end-sanitize-cygnus
3962 // start-sanitize-r5900
3963 *r5900:
3964 // end-sanitize-r5900
3965 *r3900:
3966 // start-sanitize-tx19
3967 *tx19:
3968 // end-sanitize-tx19
3969 {
3970   SyncOperation (STYPE);
3971 }
3972
3973
3974 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3975 "syscall <CODE>"
3976 *mipsI,mipsII,mipsIII,mipsIV:
3977 *vr4100:
3978 *vr5000:
3979 // start-sanitize-vr4xxx
3980 *vr4121:
3981 // end-sanitize-vr4xxx
3982 // start-sanitize-vr4320
3983 *vr4320:
3984 // end-sanitize-vr4320
3985 // start-sanitize-cygnus
3986 *vr5400:
3987 // end-sanitize-cygnus
3988 // start-sanitize-r5900
3989 *r5900:
3990 // end-sanitize-r5900
3991 *r3900:
3992 // start-sanitize-tx19
3993 *tx19:
3994 // end-sanitize-tx19
3995 {
3996   SignalException(SystemCall, instruction_0);
3997 }
3998
3999
4000 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4001 "teq r<RS>, r<RT>"
4002 *mipsII:
4003 *mipsIII:
4004 *mipsIV:
4005 *vr4100:
4006 *vr5000:
4007 // start-sanitize-vr4xxx
4008 *vr4121:
4009 // end-sanitize-vr4xxx
4010 // start-sanitize-vr4320
4011 *vr4320:
4012 // end-sanitize-vr4320
4013 // start-sanitize-cygnus
4014 *vr5400:
4015 // end-sanitize-cygnus
4016 // start-sanitize-r5900
4017 *r5900:
4018 // end-sanitize-r5900
4019 // start-sanitize-tx19
4020 *tx19:
4021 // end-sanitize-tx19
4022 {
4023   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
4024     SignalException(Trap, instruction_0);
4025 }
4026
4027
4028 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4029 "teqi r<RS>, <IMMEDIATE>"
4030 *mipsII:
4031 *mipsIII:
4032 *mipsIV:
4033 *vr4100:
4034 *vr5000:
4035 // start-sanitize-vr4xxx
4036 *vr4121:
4037 // end-sanitize-vr4xxx
4038 // start-sanitize-vr4320
4039 *vr4320:
4040 // end-sanitize-vr4320
4041 // start-sanitize-cygnus
4042 *vr5400:
4043 // end-sanitize-cygnus
4044 // start-sanitize-r5900
4045 *r5900:
4046 // end-sanitize-r5900
4047 // start-sanitize-tx19
4048 *tx19:
4049 // end-sanitize-tx19
4050 {
4051   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
4052     SignalException(Trap, instruction_0);
4053 }
4054
4055
4056 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4057 "tge r<RS>, r<RT>"
4058 *mipsII:
4059 *mipsIII:
4060 *mipsIV:
4061 *vr4100:
4062 *vr5000:
4063 // start-sanitize-vr4xxx
4064 *vr4121:
4065 // end-sanitize-vr4xxx
4066 // start-sanitize-vr4320
4067 *vr4320:
4068 // end-sanitize-vr4320
4069 // start-sanitize-cygnus
4070 *vr5400:
4071 // end-sanitize-cygnus
4072 // start-sanitize-r5900
4073 *r5900:
4074 // end-sanitize-r5900
4075 // start-sanitize-tx19
4076 *tx19:
4077 // end-sanitize-tx19
4078 {
4079   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
4080     SignalException(Trap, instruction_0);
4081 }
4082
4083
4084 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4085 "tgei r<RS>, <IMMEDIATE>"
4086 *mipsII:
4087 *mipsIII:
4088 *mipsIV:
4089 *vr4100:
4090 *vr5000:
4091 // start-sanitize-vr4xxx
4092 *vr4121:
4093 // end-sanitize-vr4xxx
4094 // start-sanitize-vr4320
4095 *vr4320:
4096 // end-sanitize-vr4320
4097 // start-sanitize-cygnus
4098 *vr5400:
4099 // end-sanitize-cygnus
4100 // start-sanitize-r5900
4101 *r5900:
4102 // end-sanitize-r5900
4103 // start-sanitize-tx19
4104 *tx19:
4105 // end-sanitize-tx19
4106 {
4107   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
4108     SignalException(Trap, instruction_0);
4109 }
4110
4111
4112 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4113 "tgeiu r<RS>, <IMMEDIATE>"
4114 *mipsII:
4115 *mipsIII:
4116 *mipsIV:
4117 *vr4100:
4118 *vr5000:
4119 // start-sanitize-vr4xxx
4120 *vr4121:
4121 // end-sanitize-vr4xxx
4122 // start-sanitize-vr4320
4123 *vr4320:
4124 // end-sanitize-vr4320
4125 // start-sanitize-cygnus
4126 *vr5400:
4127 // end-sanitize-cygnus
4128 // start-sanitize-r5900
4129 *r5900:
4130 // end-sanitize-r5900
4131 // start-sanitize-tx19
4132 *tx19:
4133 // end-sanitize-tx19
4134 {
4135   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
4136     SignalException(Trap, instruction_0);
4137 }
4138
4139
4140 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4141 "tgeu r<RS>, r<RT>"
4142 *mipsII:
4143 *mipsIII:
4144 *mipsIV:
4145 *vr4100:
4146 *vr5000:
4147 // start-sanitize-vr4xxx
4148 *vr4121:
4149 // end-sanitize-vr4xxx
4150 // start-sanitize-vr4320
4151 *vr4320:
4152 // end-sanitize-vr4320
4153 // start-sanitize-cygnus
4154 *vr5400:
4155 // end-sanitize-cygnus
4156 // start-sanitize-r5900
4157 *r5900:
4158 // end-sanitize-r5900
4159 // start-sanitize-tx19
4160 *tx19:
4161 // end-sanitize-tx19
4162 {
4163   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
4164     SignalException(Trap, instruction_0);
4165 }
4166
4167
4168 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4169 "tlt r<RS>, r<RT>"
4170 *mipsII:
4171 *mipsIII:
4172 *mipsIV:
4173 *vr4100:
4174 *vr5000:
4175 // start-sanitize-vr4xxx
4176 *vr4121:
4177 // end-sanitize-vr4xxx
4178 // start-sanitize-vr4320
4179 *vr4320:
4180 // end-sanitize-vr4320
4181 // start-sanitize-cygnus
4182 *vr5400:
4183 // end-sanitize-cygnus
4184 // start-sanitize-r5900
4185 *r5900:
4186 // end-sanitize-r5900
4187 // start-sanitize-tx19
4188 *tx19:
4189 // end-sanitize-tx19
4190 {
4191   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
4192     SignalException(Trap, instruction_0);
4193 }
4194
4195
4196 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
4197 "tlti r<RS>, <IMMEDIATE>"
4198 *mipsII:
4199 *mipsIII:
4200 *mipsIV:
4201 *vr4100:
4202 *vr5000:
4203 // start-sanitize-vr4xxx
4204 *vr4121:
4205 // end-sanitize-vr4xxx
4206 // start-sanitize-vr4320
4207 *vr4320:
4208 // end-sanitize-vr4320
4209 // start-sanitize-cygnus
4210 *vr5400:
4211 // end-sanitize-cygnus
4212 // start-sanitize-r5900
4213 *r5900:
4214 // end-sanitize-r5900
4215 // start-sanitize-tx19
4216 *tx19:
4217 // end-sanitize-tx19
4218 {
4219   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
4220     SignalException(Trap, instruction_0);
4221 }
4222
4223
4224 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
4225 "tltiu r<RS>, <IMMEDIATE>"
4226 *mipsII:
4227 *mipsIII:
4228 *mipsIV:
4229 *vr4100:
4230 *vr5000:
4231 // start-sanitize-vr4xxx
4232 *vr4121:
4233 // end-sanitize-vr4xxx
4234 // start-sanitize-vr4320
4235 *vr4320:
4236 // end-sanitize-vr4320
4237 // start-sanitize-cygnus
4238 *vr5400:
4239 // end-sanitize-cygnus
4240 // start-sanitize-r5900
4241 *r5900:
4242 // end-sanitize-r5900
4243 // start-sanitize-tx19
4244 *tx19:
4245 // end-sanitize-tx19
4246 {
4247   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
4248     SignalException(Trap, instruction_0);
4249 }
4250
4251
4252 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
4253 "tltu r<RS>, r<RT>"
4254 *mipsII:
4255 *mipsIII:
4256 *mipsIV:
4257 *vr4100:
4258 *vr5000:
4259 // start-sanitize-vr4xxx
4260 *vr4121:
4261 // end-sanitize-vr4xxx
4262 // start-sanitize-vr4320
4263 *vr4320:
4264 // end-sanitize-vr4320
4265 // start-sanitize-cygnus
4266 *vr5400:
4267 // end-sanitize-cygnus
4268 // start-sanitize-r5900
4269 *r5900:
4270 // end-sanitize-r5900
4271 // start-sanitize-tx19
4272 *tx19:
4273 // end-sanitize-tx19
4274 {
4275   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
4276     SignalException(Trap, instruction_0);
4277 }
4278
4279
4280 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
4281 "tne r<RS>, r<RT>"
4282 *mipsII:
4283 *mipsIII:
4284 *mipsIV:
4285 *vr4100:
4286 *vr5000:
4287 // start-sanitize-vr4xxx
4288 *vr4121:
4289 // end-sanitize-vr4xxx
4290 // start-sanitize-vr4320
4291 *vr4320:
4292 // end-sanitize-vr4320
4293 // start-sanitize-cygnus
4294 *vr5400:
4295 // end-sanitize-cygnus
4296 // start-sanitize-r5900
4297 *r5900:
4298 // end-sanitize-r5900
4299 // start-sanitize-tx19
4300 *tx19:
4301 // end-sanitize-tx19
4302 {
4303   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
4304     SignalException(Trap, instruction_0);
4305 }
4306
4307
4308 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4309 "tne r<RS>, <IMMEDIATE>"
4310 *mipsII:
4311 *mipsIII:
4312 *mipsIV:
4313 *vr4100:
4314 *vr5000:
4315 // start-sanitize-vr4xxx
4316 *vr4121:
4317 // end-sanitize-vr4xxx
4318 // start-sanitize-vr4320
4319 *vr4320:
4320 // end-sanitize-vr4320
4321 // start-sanitize-cygnus
4322 *vr5400:
4323 // end-sanitize-cygnus
4324 // start-sanitize-r5900
4325 *r5900:
4326 // end-sanitize-r5900
4327 // start-sanitize-tx19
4328 *tx19:
4329 // end-sanitize-tx19
4330 {
4331   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
4332     SignalException(Trap, instruction_0);
4333 }
4334
4335
4336 :function:::void:do_xor:int rs, int rt, int rd
4337 {
4338   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4339   GPR[rd] = GPR[rs] ^ GPR[rt];
4340   TRACE_ALU_RESULT (GPR[rd]);
4341 }
4342
4343 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
4344 "xor r<RD>, r<RS>, r<RT>"
4345 *mipsI,mipsII,mipsIII,mipsIV:
4346 *vr4100:
4347 *vr5000:
4348 // start-sanitize-vr4xxx
4349 *vr4121:
4350 // end-sanitize-vr4xxx
4351 // start-sanitize-vr4320
4352 *vr4320:
4353 // end-sanitize-vr4320
4354 // start-sanitize-cygnus
4355 *vr5400:
4356 // end-sanitize-cygnus
4357 // start-sanitize-r5900
4358 *r5900:
4359 // end-sanitize-r5900
4360 *r3900:
4361 // start-sanitize-tx19
4362 *tx19:
4363 // end-sanitize-tx19
4364 {
4365   do_xor (SD_, RS, RT, RD);
4366 }
4367
4368
4369 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4370 {
4371   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4372   GPR[rt] = GPR[rs] ^ immediate;
4373   TRACE_ALU_RESULT (GPR[rt]);
4374 }
4375
4376 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4377 "xori r<RT>, r<RS>, <IMMEDIATE>"
4378 *mipsI,mipsII,mipsIII,mipsIV:
4379 *vr4100:
4380 *vr5000:
4381 // start-sanitize-vr4xxx
4382 *vr4121:
4383 // end-sanitize-vr4xxx
4384 // start-sanitize-vr4320
4385 *vr4320:
4386 // end-sanitize-vr4320
4387 // start-sanitize-cygnus
4388 *vr5400:
4389 // end-sanitize-cygnus
4390 // start-sanitize-r5900
4391 *r5900:
4392 // end-sanitize-r5900
4393 *r3900:
4394 // start-sanitize-tx19
4395 *tx19:
4396 // end-sanitize-tx19
4397 {
4398   do_xori (SD_, RS, RT, IMMEDIATE);
4399 }
4400
4401 \f
4402 //
4403 // MIPS Architecture:
4404 //
4405 //        FPU Instruction Set (COP1 & COP1X)
4406 //
4407
4408
4409 :%s::::FMT:int fmt
4410 {
4411   switch (fmt)
4412     {
4413     case fmt_single: return "s";
4414     case fmt_double: return "d";
4415     case fmt_word: return "w";
4416     case fmt_long: return "l";
4417     default: return "?";
4418     }
4419 }
4420
4421 :%s::::X:int x
4422 {
4423   switch (x)
4424     {
4425     case 0: return "f";
4426     case 1: return "t";
4427     default: return "?";
4428     }
4429 }
4430
4431 :%s::::TF:int tf
4432 {
4433   if (tf)
4434     return "t";
4435   else
4436     return "f";
4437 }
4438
4439 :%s::::ND:int nd
4440 {
4441   if (nd)
4442     return "l";
4443   else
4444     return "";
4445 }
4446
4447 :%s::::COND:int cond
4448 {
4449   switch (cond)
4450     {
4451     case 00: return "f";
4452     case 01: return "un";
4453     case 02: return "eq";
4454     case 03: return "ueq";
4455     case 04: return "olt";
4456     case 05: return "ult";
4457     case 06: return "ole";
4458     case 07: return "ule";
4459     case 010: return "sf";
4460     case 011: return "ngle";
4461     case 012: return "seq";
4462     case 013: return "ngl";
4463     case 014: return "lt";
4464     case 015: return "nge";
4465     case 016: return "le";
4466     case 017: return "ngt";
4467     default: return "?";
4468     }
4469 }
4470
4471
4472 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4473 "abs.%s<FMT> f<FD>, f<FS>"
4474 *mipsI,mipsII,mipsIII,mipsIV:
4475 *vr4100:
4476 *vr5000:
4477 // start-sanitize-vr4xxx
4478 *vr4121:
4479 // end-sanitize-vr4xxx
4480 // start-sanitize-vr4320
4481 *vr4320:
4482 // end-sanitize-vr4320
4483 // start-sanitize-cygnus
4484 *vr5400:
4485 // end-sanitize-cygnus
4486 *r3900:
4487 // start-sanitize-tx19
4488 *tx19:
4489 // end-sanitize-tx19
4490 {
4491   unsigned32 instruction = instruction_0;
4492   int destreg = ((instruction >> 6) & 0x0000001F);
4493   int fs = ((instruction >> 11) & 0x0000001F);
4494   int format = ((instruction >> 21) & 0x00000007);
4495   {
4496     if ((format != fmt_single) && (format != fmt_double))
4497       SignalException(ReservedInstruction,instruction);
4498     else
4499       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
4500   }
4501 }
4502
4503
4504
4505 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4506 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4507 *mipsI,mipsII,mipsIII,mipsIV:
4508 *vr4100:
4509 *vr5000:
4510 // start-sanitize-vr4xxx
4511 *vr4121:
4512 // end-sanitize-vr4xxx
4513 // start-sanitize-vr4320
4514 *vr4320:
4515 // end-sanitize-vr4320
4516 // start-sanitize-cygnus
4517 *vr5400:
4518 // end-sanitize-cygnus
4519 *r3900:
4520 // start-sanitize-tx19
4521 *tx19:
4522 // end-sanitize-tx19
4523 {
4524   unsigned32 instruction = instruction_0;
4525   int destreg = ((instruction >> 6) & 0x0000001F);
4526   int fs = ((instruction >> 11) & 0x0000001F);
4527   int ft = ((instruction >> 16) & 0x0000001F);
4528   int format = ((instruction >> 21) & 0x00000007);
4529   {
4530     if ((format != fmt_single) && (format != fmt_double))
4531       SignalException(ReservedInstruction, instruction);
4532     else
4533       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4534   }
4535 }
4536
4537
4538
4539 // BC1F
4540 // BC1FL
4541 // BC1T
4542 // BC1TL
4543
4544 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4545 "bc1%s<TF>%s<ND> <OFFSET>"
4546 *mipsI,mipsII,mipsIII:
4547 *vr4100:
4548 // start-sanitize-vr4xxx
4549 *vr4121:
4550 // end-sanitize-vr4xxx
4551 // start-sanitize-vr4320
4552 *vr4320:
4553 // end-sanitize-vr4320
4554 // start-sanitize-r5900
4555 *r5900:
4556 // end-sanitize-r5900
4557 {
4558   check_branch_bug ();
4559   TRACE_BRANCH_INPUT (PREVCOC1());
4560   if (PREVCOC1() == TF)
4561     {
4562       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4563       TRACE_BRANCH_RESULT (dest);
4564       mark_branch_bug (dest);
4565       DELAY_SLOT (dest);
4566     }
4567   else if (ND)
4568     {
4569       TRACE_BRANCH_RESULT (0);
4570       NULLIFY_NEXT_INSTRUCTION ();
4571     }
4572   else
4573     {
4574       TRACE_BRANCH_RESULT (NIA);
4575     }
4576 }
4577
4578 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4579 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4580 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4581 *mipsIV:
4582 *vr5000:
4583 // start-sanitize-cygnus
4584 *vr5400:
4585 // end-sanitize-cygnus
4586 *r3900:
4587 // start-sanitize-tx19
4588 *tx19:
4589 // end-sanitize-tx19
4590 {
4591   check_branch_bug ();
4592   if (GETFCC(CC) == TF)
4593     {
4594       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4595       mark_branch_bug (dest);
4596       DELAY_SLOT (dest);
4597     }
4598   else if (ND)
4599     {
4600       NULLIFY_NEXT_INSTRUCTION ();
4601     }
4602 }
4603
4604
4605
4606
4607
4608
4609 // C.EQ.S
4610 // C.EQ.D
4611 // ...
4612
4613 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4614 {
4615   if ((fmt != fmt_single) && (fmt != fmt_double))
4616     SignalException (ReservedInstruction, insn);
4617   else
4618     {
4619       int less;
4620       int equal;
4621       int unordered;
4622       int condition;
4623       unsigned64 ofs = ValueFPR (fs, fmt);
4624       unsigned64 oft = ValueFPR (ft, fmt);
4625       if (NaN (ofs, fmt) || NaN (oft, fmt))
4626         {
4627           if (FCSR & FP_ENABLE (IO))
4628             {
4629               FCSR |= FP_CAUSE (IO);
4630               SignalExceptionFPE ();
4631             }
4632           less = 0;
4633           equal = 0;
4634           unordered = 1;
4635         }
4636       else
4637         {
4638           less = Less (ofs, oft, fmt);
4639           equal = Equal (ofs, oft, fmt);
4640           unordered = 0;
4641         }
4642       condition = (((cond & (1 << 2)) && less)
4643                    || ((cond & (1 << 1)) && equal)
4644                    || ((cond & (1 << 0)) && unordered));
4645       SETFCC (cc, condition);
4646     }
4647 }
4648
4649 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
4650 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4651 *mipsI,mipsII,mipsIII:
4652 {
4653   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4654 }
4655
4656 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
4657 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4658 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4659 *mipsIV:
4660 *vr4100:
4661 *vr5000:
4662 // start-sanitize-vr4xxx
4663 *vr4121:
4664 // end-sanitize-vr4xxx
4665 // start-sanitize-vr4320
4666 *vr4320:
4667 // end-sanitize-vr4320
4668 // start-sanitize-cygnus
4669 *vr5400:
4670 // end-sanitize-cygnus
4671 *r3900:
4672 // start-sanitize-tx19
4673 *tx19:
4674 // end-sanitize-tx19
4675 {
4676   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4677 }
4678
4679
4680 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4681 "ceil.l.%s<FMT> f<FD>, f<FS>"
4682 *mipsIII:
4683 *mipsIV:
4684 *vr4100:
4685 *vr5000:
4686 // start-sanitize-vr4xxx
4687 *vr4121:
4688 // end-sanitize-vr4xxx
4689 // start-sanitize-vr4320
4690 *vr4320:
4691 // end-sanitize-vr4320
4692 // start-sanitize-cygnus
4693 *vr5400:
4694 // end-sanitize-cygnus
4695 // start-sanitize-r5900
4696 *r5900:
4697 // end-sanitize-r5900
4698 *r3900:
4699 // start-sanitize-tx19
4700 *tx19:
4701 // end-sanitize-tx19
4702 {
4703   unsigned32 instruction = instruction_0;
4704   int destreg = ((instruction >> 6) & 0x0000001F);
4705   int fs = ((instruction >> 11) & 0x0000001F);
4706   int format = ((instruction >> 21) & 0x00000007);
4707   {
4708     if ((format != fmt_single) && (format != fmt_double))
4709       SignalException(ReservedInstruction,instruction);
4710     else
4711       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4712   }
4713 }
4714
4715
4716 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4717 *mipsII:
4718 *mipsIII:
4719 *mipsIV:
4720 *vr4100:
4721 *vr5000:
4722 // start-sanitize-vr4xxx
4723 *vr4121:
4724 // end-sanitize-vr4xxx
4725 // start-sanitize-vr4320
4726 *vr4320:
4727 // end-sanitize-vr4320
4728 // start-sanitize-cygnus
4729 *vr5400:
4730 // end-sanitize-cygnus
4731 // start-sanitize-r5900
4732 *r5900:
4733 // end-sanitize-r5900
4734 *r3900:
4735 // start-sanitize-tx19
4736 *tx19:
4737 // end-sanitize-tx19
4738 {
4739   unsigned32 instruction = instruction_0;
4740   int destreg = ((instruction >> 6) & 0x0000001F);
4741   int fs = ((instruction >> 11) & 0x0000001F);
4742   int format = ((instruction >> 21) & 0x00000007);
4743   {
4744   if ((format != fmt_single) && (format != fmt_double))
4745    SignalException(ReservedInstruction,instruction);
4746   else
4747    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4748   }
4749 }
4750
4751
4752 // CFC1
4753 // CTC1
4754 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4755 "c%s<X>c1 r<RT>, f<FS>"
4756 *mipsI:
4757 *mipsII:
4758 *mipsIII:
4759 {
4760   if (X)
4761     {
4762       if (FS == 0)
4763         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4764       else if (FS == 31)
4765         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4766       /* else NOP */
4767       PENDING_FILL(COCIDX,0); /* special case */
4768     }
4769   else
4770     { /* control from */
4771       if (FS == 0)
4772         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4773       else if (FS == 31)
4774         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4775       /* else NOP */
4776     }
4777 }
4778 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4779 "c%s<X>c1 r<RT>, f<FS>"
4780 *mipsIV:
4781 *vr4100:
4782 *vr5000:
4783 // start-sanitize-vr4xxx
4784 *vr4121:
4785 // end-sanitize-vr4xxx
4786 // start-sanitize-vr4320
4787 *vr4320:
4788 // end-sanitize-vr4320
4789 // start-sanitize-cygnus
4790 *vr5400:
4791 // end-sanitize-cygnus
4792 *r3900:
4793 // start-sanitize-tx19
4794 *tx19:
4795 // end-sanitize-tx19
4796 {
4797   if (X)
4798     {
4799       /* control to */
4800       TRACE_ALU_INPUT1 (GPR[RT]);
4801       if (FS == 0)
4802         {
4803           FCR0 = VL4_8(GPR[RT]);
4804           TRACE_ALU_RESULT (FCR0);
4805         }
4806       else if (FS == 31)
4807         {
4808           FCR31 = VL4_8(GPR[RT]);
4809           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4810           TRACE_ALU_RESULT (FCR31);
4811         }
4812       else
4813         {
4814           TRACE_ALU_RESULT0 ();
4815         }
4816       /* else NOP */
4817     }
4818   else
4819     { /* control from */
4820       if (FS == 0)
4821         {
4822           TRACE_ALU_INPUT1 (FCR0);
4823           GPR[RT] = SIGNEXTEND (FCR0, 32);
4824         }
4825       else if (FS == 31)
4826         {
4827           TRACE_ALU_INPUT1 (FCR31);
4828           GPR[RT] = SIGNEXTEND (FCR31, 32);
4829         }
4830       TRACE_ALU_RESULT (GPR[RT]);
4831       /* else NOP */
4832     }
4833 }
4834
4835
4836 //
4837 // FIXME: Does not correctly differentiate between mips*
4838 //
4839 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4840 "cvt.d.%s<FMT> f<FD>, f<FS>"
4841 *mipsI,mipsII,mipsIII,mipsIV:
4842 *vr4100:
4843 *vr5000:
4844 // start-sanitize-vr4xxx
4845 *vr4121:
4846 // end-sanitize-vr4xxx
4847 // start-sanitize-vr4320
4848 *vr4320:
4849 // end-sanitize-vr4320
4850 // start-sanitize-cygnus
4851 *vr5400:
4852 // end-sanitize-cygnus
4853 *r3900:
4854 // start-sanitize-tx19
4855 *tx19:
4856 // end-sanitize-tx19
4857 {
4858   unsigned32 instruction = instruction_0;
4859   int destreg = ((instruction >> 6) & 0x0000001F);
4860   int fs = ((instruction >> 11) & 0x0000001F);
4861   int format = ((instruction >> 21) & 0x00000007);
4862   {
4863     if ((format == fmt_double) | 0)
4864       SignalException(ReservedInstruction,instruction);
4865     else
4866       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4867   }
4868 }
4869
4870
4871 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4872 "cvt.l.%s<FMT> f<FD>, f<FS>"
4873 *mipsIII:
4874 *mipsIV:
4875 *vr4100:
4876 *vr5000:
4877 // start-sanitize-vr4xxx
4878 *vr4121:
4879 // end-sanitize-vr4xxx
4880 // start-sanitize-vr4320
4881 *vr4320:
4882 // end-sanitize-vr4320
4883 // start-sanitize-cygnus
4884 *vr5400:
4885 // end-sanitize-cygnus
4886 *r3900:
4887 // start-sanitize-tx19
4888 *tx19:
4889 // end-sanitize-tx19
4890 {
4891   unsigned32 instruction = instruction_0;
4892   int destreg = ((instruction >> 6) & 0x0000001F);
4893   int fs = ((instruction >> 11) & 0x0000001F);
4894   int format = ((instruction >> 21) & 0x00000007);
4895   {
4896     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4897       SignalException(ReservedInstruction,instruction);
4898     else
4899       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4900   }
4901 }
4902
4903
4904 //
4905 // FIXME: Does not correctly differentiate between mips*
4906 //
4907 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4908 "cvt.s.%s<FMT> f<FD>, f<FS>"
4909 *mipsI,mipsII,mipsIII,mipsIV:
4910 *vr4100:
4911 *vr5000:
4912 // start-sanitize-vr4xxx
4913 *vr4121:
4914 // end-sanitize-vr4xxx
4915 // start-sanitize-vr4320
4916 *vr4320:
4917 // end-sanitize-vr4320
4918 // start-sanitize-cygnus
4919 *vr5400:
4920 // end-sanitize-cygnus
4921 *r3900:
4922 // start-sanitize-tx19
4923 *tx19:
4924 // end-sanitize-tx19
4925 {
4926   unsigned32 instruction = instruction_0;
4927   int destreg = ((instruction >> 6) & 0x0000001F);
4928   int fs = ((instruction >> 11) & 0x0000001F);
4929   int format = ((instruction >> 21) & 0x00000007);
4930   {
4931     if ((format == fmt_single) | 0)
4932       SignalException(ReservedInstruction,instruction);
4933     else
4934       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4935   }
4936 }
4937
4938
4939 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4940 "cvt.w.%s<FMT> f<FD>, f<FS>"
4941 *mipsI,mipsII,mipsIII,mipsIV:
4942 *vr4100:
4943 *vr5000:
4944 // start-sanitize-vr4xxx
4945 *vr4121:
4946 // end-sanitize-vr4xxx
4947 // start-sanitize-vr4320
4948 *vr4320:
4949 // end-sanitize-vr4320
4950 // start-sanitize-cygnus
4951 *vr5400:
4952 // end-sanitize-cygnus
4953 *r3900:
4954 // start-sanitize-tx19
4955 *tx19:
4956 // end-sanitize-tx19
4957 {
4958   unsigned32 instruction = instruction_0;
4959   int destreg = ((instruction >> 6) & 0x0000001F);
4960   int fs = ((instruction >> 11) & 0x0000001F);
4961   int format = ((instruction >> 21) & 0x00000007);
4962   {
4963     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4964       SignalException(ReservedInstruction,instruction);
4965     else
4966       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4967   }
4968 }
4969
4970
4971 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4972 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4973 *mipsI,mipsII,mipsIII,mipsIV:
4974 *vr4100:
4975 *vr5000:
4976 // start-sanitize-vr4xxx
4977 *vr4121:
4978 // end-sanitize-vr4xxx
4979 // start-sanitize-vr4320
4980 *vr4320:
4981 // end-sanitize-vr4320
4982 // start-sanitize-cygnus
4983 *vr5400:
4984 // end-sanitize-cygnus
4985 *r3900:
4986 // start-sanitize-tx19
4987 *tx19:
4988 // end-sanitize-tx19
4989 {
4990   unsigned32 instruction = instruction_0;
4991   int destreg = ((instruction >> 6) & 0x0000001F);
4992   int fs = ((instruction >> 11) & 0x0000001F);
4993   int ft = ((instruction >> 16) & 0x0000001F);
4994   int format = ((instruction >> 21) & 0x00000007);
4995   {
4996     if ((format != fmt_single) && (format != fmt_double))
4997       SignalException(ReservedInstruction,instruction);
4998     else
4999       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
5000   }
5001 }
5002
5003
5004 // DMFC1
5005 // DMTC1
5006 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
5007 "dm%s<X>c1 r<RT>, f<FS>"
5008 *mipsIII:
5009 {
5010   if (X)
5011     {
5012       if (SizeFGR() == 64)
5013         PENDING_FILL((FS + FGRIDX),GPR[RT]);
5014       else if ((FS & 0x1) == 0)
5015         {
5016           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
5017           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
5018         }
5019     }
5020   else
5021     {
5022       if (SizeFGR() == 64)
5023         PENDING_FILL(RT,FGR[FS]);
5024       else if ((FS & 0x1) == 0)
5025         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
5026       else
5027         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
5028     }
5029 }
5030 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
5031 "dm%s<X>c1 r<RT>, f<FS>"
5032 *mipsIV:
5033 *vr4100:
5034 *vr5000:
5035 // start-sanitize-vr4xxx
5036 *vr4121:
5037 // end-sanitize-vr4xxx
5038 // start-sanitize-vr4320
5039 *vr4320:
5040 // end-sanitize-vr4320
5041 // start-sanitize-cygnus
5042 *vr5400:
5043 // end-sanitize-cygnus
5044 // start-sanitize-r5900
5045 *r5900:
5046 // end-sanitize-r5900
5047 *r3900:
5048 // start-sanitize-tx19
5049 *tx19:
5050 // end-sanitize-tx19
5051 {
5052   if (X)
5053     {
5054       if (SizeFGR() == 64)
5055         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
5056       else if ((FS & 0x1) == 0)
5057         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
5058     }
5059   else
5060     {
5061       if (SizeFGR() == 64)
5062         GPR[RT] = FGR[FS];
5063       else if ((FS & 0x1) == 0)
5064         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
5065       else
5066         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5067     }
5068 }
5069
5070
5071 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
5072 "floor.l.%s<FMT> f<FD>, f<FS>"
5073 *mipsIII:
5074 *mipsIV:
5075 *vr4100:
5076 *vr5000:
5077 // start-sanitize-vr4xxx
5078 *vr4121:
5079 // end-sanitize-vr4xxx
5080 // start-sanitize-vr4320
5081 *vr4320:
5082 // end-sanitize-vr4320
5083 // start-sanitize-cygnus
5084 *vr5400:
5085 // end-sanitize-cygnus
5086 // start-sanitize-r5900
5087 *r5900:
5088 // end-sanitize-r5900
5089 *r3900:
5090 // start-sanitize-tx19
5091 *tx19:
5092 // end-sanitize-tx19
5093 {
5094   unsigned32 instruction = instruction_0;
5095   int destreg = ((instruction >> 6) & 0x0000001F);
5096   int fs = ((instruction >> 11) & 0x0000001F);
5097   int format = ((instruction >> 21) & 0x00000007);
5098   {
5099     if ((format != fmt_single) && (format != fmt_double))
5100       SignalException(ReservedInstruction,instruction);
5101     else
5102       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
5103   }
5104 }
5105
5106
5107 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
5108 "floor.w.%s<FMT> f<FD>, f<FS>"
5109 *mipsII:
5110 *mipsIII:
5111 *mipsIV:
5112 *vr4100:
5113 *vr5000:
5114 // start-sanitize-vr4xxx
5115 *vr4121:
5116 // end-sanitize-vr4xxx
5117 // start-sanitize-vr4320
5118 *vr4320:
5119 // end-sanitize-vr4320
5120 // start-sanitize-cygnus
5121 *vr5400:
5122 // end-sanitize-cygnus
5123 // start-sanitize-r5900
5124 *r5900:
5125 // end-sanitize-r5900
5126 *r3900:
5127 // start-sanitize-tx19
5128 *tx19:
5129 // end-sanitize-tx19
5130 {
5131   unsigned32 instruction = instruction_0;
5132   int destreg = ((instruction >> 6) & 0x0000001F);
5133   int fs = ((instruction >> 11) & 0x0000001F);
5134   int format = ((instruction >> 21) & 0x00000007);
5135   {
5136     if ((format != fmt_single) && (format != fmt_double))
5137       SignalException(ReservedInstruction,instruction);
5138     else
5139       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
5140   }
5141 }
5142
5143
5144 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
5145 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5146 *mipsII:
5147 *mipsIII:
5148 *mipsIV:
5149 *vr4100:
5150 *vr5000:
5151 // start-sanitize-vr4xxx
5152 *vr4121:
5153 // end-sanitize-vr4xxx
5154 // start-sanitize-vr4320
5155 *vr4320:
5156 // end-sanitize-vr4320
5157 // start-sanitize-cygnus
5158 *vr5400:
5159 // end-sanitize-cygnus
5160 *r3900:
5161 // start-sanitize-tx19
5162 *tx19:
5163 // end-sanitize-tx19
5164 {
5165   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
5166 }
5167
5168
5169 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
5170 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5171 *mipsIV:
5172 *vr5000:
5173 // start-sanitize-vr4320
5174 *vr4320:
5175 // end-sanitize-vr4320
5176 // start-sanitize-cygnus
5177 *vr5400:
5178 // end-sanitize-cygnus
5179 {
5180   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
5181 }
5182
5183
5184
5185 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
5186 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
5187 *mipsI,mipsII,mipsIII,mipsIV:
5188 *vr4100:
5189 *vr5000:
5190 // start-sanitize-vr4xxx
5191 *vr4121:
5192 // end-sanitize-vr4xxx
5193 // start-sanitize-vr4320
5194 *vr4320:
5195 // end-sanitize-vr4320
5196 // start-sanitize-cygnus
5197 *vr5400:
5198 // end-sanitize-cygnus
5199 // start-sanitize-r5900
5200 *r5900:
5201 // end-sanitize-r5900
5202 *r3900:
5203 // start-sanitize-tx19
5204 *tx19:
5205 // end-sanitize-tx19
5206 {
5207   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
5208 }
5209
5210
5211 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
5212 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5213 *mipsIV:
5214 *vr5000:
5215 // start-sanitize-vr4320
5216 *vr4320:
5217 // end-sanitize-vr4320
5218 // start-sanitize-cygnus
5219 *vr5400:
5220 // end-sanitize-cygnus
5221 {
5222   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
5223 }
5224
5225
5226
5227 //
5228 // FIXME: Not correct for mips*
5229 //
5230 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
5231 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
5232 *mipsIV:
5233 *vr5000:
5234 // start-sanitize-vr4320
5235 *vr4320:
5236 // end-sanitize-vr4320
5237 // start-sanitize-cygnus
5238 *vr5400:
5239 // end-sanitize-cygnus
5240 {
5241   unsigned32 instruction = instruction_0;
5242   int destreg = ((instruction >> 6) & 0x0000001F);
5243   int fs = ((instruction >> 11) & 0x0000001F);
5244   int ft = ((instruction >> 16) & 0x0000001F);
5245   int fr = ((instruction >> 21) & 0x0000001F);
5246   {
5247     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5248   }
5249 }
5250
5251
5252 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
5253 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
5254 *mipsIV:
5255 *vr5000:
5256 // start-sanitize-vr4320
5257 *vr4320:
5258 // end-sanitize-vr4320
5259 // start-sanitize-cygnus
5260 *vr5400:
5261 // end-sanitize-cygnus
5262 {
5263   unsigned32 instruction = instruction_0;
5264   int destreg = ((instruction >> 6) & 0x0000001F);
5265   int fs = ((instruction >> 11) & 0x0000001F);
5266   int ft = ((instruction >> 16) & 0x0000001F);
5267   int fr = ((instruction >> 21) & 0x0000001F);
5268   {
5269     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5270   }
5271 }
5272
5273
5274 // MFC1
5275 // MTC1
5276 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
5277 "m%s<X>c1 r<RT>, f<FS>"
5278 *mipsI:
5279 *mipsII:
5280 *mipsIII:
5281 {
5282   if (X)
5283     { /*MTC1*/
5284       if (SizeFGR() == 64)
5285         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
5286       else
5287         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
5288     }
5289   else /*MFC1*/
5290     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
5291 }
5292 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
5293 "m%s<X>c1 r<RT>, f<FS>"
5294 *mipsIV:
5295 *vr4100:
5296 *vr5000:
5297 // start-sanitize-vr4xxx
5298 *vr4121:
5299 // end-sanitize-vr4xxx
5300 // start-sanitize-vr4320
5301 *vr4320:
5302 // end-sanitize-vr4320
5303 // start-sanitize-cygnus
5304 *vr5400:
5305 // end-sanitize-cygnus
5306 *r3900:
5307 // start-sanitize-tx19
5308 *tx19:
5309 // end-sanitize-tx19
5310 {
5311   int fs = FS;
5312   if (X)
5313     /*MTC1*/
5314     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
5315   else /*MFC1*/
5316     GPR[RT] = SIGNEXTEND(FGR[FS],32);
5317 }
5318
5319
5320 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
5321 "mov.%s<FMT> f<FD>, f<FS>"
5322 *mipsI,mipsII,mipsIII,mipsIV:
5323 *vr4100:
5324 *vr5000:
5325 // start-sanitize-vr4xxx
5326 *vr4121:
5327 // end-sanitize-vr4xxx
5328 // start-sanitize-vr4320
5329 *vr4320:
5330 // end-sanitize-vr4320
5331 // start-sanitize-cygnus
5332 *vr5400:
5333 // end-sanitize-cygnus
5334 *r3900:
5335 // start-sanitize-tx19
5336 *tx19:
5337 // end-sanitize-tx19
5338 {
5339   unsigned32 instruction = instruction_0;
5340   int destreg = ((instruction >> 6) & 0x0000001F);
5341   int fs = ((instruction >> 11) & 0x0000001F);
5342   int format = ((instruction >> 21) & 0x00000007);
5343   {
5344     StoreFPR(destreg,format,ValueFPR(fs,format));
5345   }
5346 }
5347
5348
5349 // MOVF
5350 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
5351 "mov%s<TF> r<RD>, r<RS>, <CC>"
5352 *mipsIV:
5353 *vr5000:
5354 // start-sanitize-vr4320
5355 *vr4320:
5356 // end-sanitize-vr4320
5357 // start-sanitize-cygnus
5358 *vr5400:
5359 // end-sanitize-cygnus
5360 // start-sanitize-r5900
5361 *r5900:
5362 // end-sanitize-r5900
5363 {
5364   if (GETFCC(CC) == TF)
5365     GPR[RD] = GPR[RS];
5366 }
5367
5368
5369 // MOVF.fmt
5370 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
5371 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5372 *mipsIV:
5373 *vr5000:
5374 // start-sanitize-vr4320
5375 *vr4320:
5376 // end-sanitize-vr4320
5377 // start-sanitize-cygnus
5378 *vr5400:
5379 // end-sanitize-cygnus
5380 // start-sanitize-r5900
5381 *r5900:
5382 // end-sanitize-r5900
5383 {
5384   unsigned32 instruction = instruction_0;
5385   int format = ((instruction >> 21) & 0x00000007);
5386   {
5387    if (GETFCC(CC) == TF)
5388      StoreFPR (FD, format, ValueFPR (FS, format));
5389    else
5390      StoreFPR (FD, format, ValueFPR (FD, format));
5391   }
5392 }
5393
5394
5395 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
5396 *mipsIV:
5397 *vr5000:
5398 // start-sanitize-vr4320
5399 *vr4320:
5400 // end-sanitize-vr4320
5401 // start-sanitize-cygnus
5402 *vr5400:
5403 // end-sanitize-cygnus
5404 // start-sanitize-r5900
5405 *r5900:
5406 // end-sanitize-r5900
5407 {
5408   unsigned32 instruction = instruction_0;
5409   int destreg = ((instruction >> 6) & 0x0000001F);
5410   int fs = ((instruction >> 11) & 0x0000001F);
5411   int format = ((instruction >> 21) & 0x00000007);
5412   {
5413     StoreFPR(destreg,format,ValueFPR(fs,format));
5414   }
5415 }
5416
5417
5418 // MOVT see MOVtf
5419
5420
5421 // MOVT.fmt see MOVtf.fmt
5422
5423
5424
5425 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
5426 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5427 *mipsIV:
5428 *vr5000:
5429 // start-sanitize-vr4320
5430 *vr4320:
5431 // end-sanitize-vr4320
5432 // start-sanitize-cygnus
5433 *vr5400:
5434 // end-sanitize-cygnus
5435 // start-sanitize-r5900
5436 *r5900:
5437 // end-sanitize-r5900
5438 {
5439   unsigned32 instruction = instruction_0;
5440   int destreg = ((instruction >> 6) & 0x0000001F);
5441   int fs = ((instruction >> 11) & 0x0000001F);
5442   int format = ((instruction >> 21) & 0x00000007);
5443   {
5444    StoreFPR(destreg,format,ValueFPR(fs,format));
5445   }
5446 }
5447
5448
5449 // MSUB.fmt
5450 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
5451 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
5452 *mipsIV:
5453 *vr5000:
5454 // start-sanitize-vr4320
5455 *vr4320:
5456 // end-sanitize-vr4320
5457 // start-sanitize-cygnus
5458 *vr5400:
5459 // end-sanitize-cygnus
5460 // start-sanitize-r5900
5461 *r5900:
5462 // end-sanitize-r5900
5463 {
5464   unsigned32 instruction = instruction_0;
5465   int destreg = ((instruction >> 6) & 0x0000001F);
5466   int fs = ((instruction >> 11) & 0x0000001F);
5467   int ft = ((instruction >> 16) & 0x0000001F);
5468   int fr = ((instruction >> 21) & 0x0000001F);
5469   {
5470     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5471   }
5472 }
5473
5474
5475 // MSUB.fmt
5476 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
5477 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
5478 *mipsIV:
5479 *vr5000:
5480 // start-sanitize-vr4320
5481 *vr4320:
5482 // end-sanitize-vr4320
5483 // start-sanitize-cygnus
5484 *vr5400:
5485 // end-sanitize-cygnus
5486 // start-sanitize-r5900
5487 *r5900:
5488 // end-sanitize-r5900
5489 {
5490   unsigned32 instruction = instruction_0;
5491   int destreg = ((instruction >> 6) & 0x0000001F);
5492   int fs = ((instruction >> 11) & 0x0000001F);
5493   int ft = ((instruction >> 16) & 0x0000001F);
5494   int fr = ((instruction >> 21) & 0x0000001F);
5495   {
5496    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5497   }
5498 }
5499
5500
5501 // MTC1 see MxC1
5502
5503
5504 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
5505 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5506 *mipsI,mipsII,mipsIII,mipsIV:
5507 *vr4100:
5508 *vr5000:
5509 // start-sanitize-vr4xxx
5510 *vr4121:
5511 // end-sanitize-vr4xxx
5512 // start-sanitize-vr4320
5513 *vr4320:
5514 // end-sanitize-vr4320
5515 // start-sanitize-cygnus
5516 *vr5400:
5517 // end-sanitize-cygnus
5518 *r3900:
5519 // start-sanitize-tx19
5520 *tx19:
5521 // end-sanitize-tx19
5522 {
5523   unsigned32 instruction = instruction_0;
5524   int destreg = ((instruction >> 6) & 0x0000001F);
5525   int fs = ((instruction >> 11) & 0x0000001F);
5526   int ft = ((instruction >> 16) & 0x0000001F);
5527   int format = ((instruction >> 21) & 0x00000007);
5528   {
5529     if ((format != fmt_single) && (format != fmt_double))
5530       SignalException(ReservedInstruction,instruction);
5531     else
5532       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
5533   }
5534 }
5535
5536
5537 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
5538 "neg.%s<FMT> f<FD>, f<FS>"
5539 *mipsI,mipsII,mipsIII,mipsIV:
5540 *vr4100:
5541 *vr5000:
5542 // start-sanitize-vr4xxx
5543 *vr4121:
5544 // end-sanitize-vr4xxx
5545 // start-sanitize-vr4320
5546 *vr4320:
5547 // end-sanitize-vr4320
5548 // start-sanitize-cygnus
5549 *vr5400:
5550 // end-sanitize-cygnus
5551 *r3900:
5552 // start-sanitize-tx19
5553 *tx19:
5554 // end-sanitize-tx19
5555 {
5556   unsigned32 instruction = instruction_0;
5557   int destreg = ((instruction >> 6) & 0x0000001F);
5558   int fs = ((instruction >> 11) & 0x0000001F);
5559   int format = ((instruction >> 21) & 0x00000007);
5560   {
5561     if ((format != fmt_single) && (format != fmt_double))
5562       SignalException(ReservedInstruction,instruction);
5563     else
5564       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
5565   }
5566 }
5567
5568
5569 // NMADD.fmt
5570 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
5571 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
5572 *mipsIV:
5573 *vr5000:
5574 // start-sanitize-vr4320
5575 *vr4320:
5576 // end-sanitize-vr4320
5577 // start-sanitize-cygnus
5578 *vr5400:
5579 // end-sanitize-cygnus
5580 {
5581   unsigned32 instruction = instruction_0;
5582   int destreg = ((instruction >> 6) & 0x0000001F);
5583   int fs = ((instruction >> 11) & 0x0000001F);
5584   int ft = ((instruction >> 16) & 0x0000001F);
5585   int fr = ((instruction >> 21) & 0x0000001F);
5586   {
5587    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5588   }
5589 }
5590
5591
5592 // NMADD.fmt
5593 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
5594 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
5595 *mipsIV:
5596 *vr5000:
5597 // start-sanitize-vr4320
5598 *vr4320:
5599 // end-sanitize-vr4320
5600 // start-sanitize-cygnus
5601 *vr5400:
5602 // end-sanitize-cygnus
5603 {
5604   unsigned32 instruction = instruction_0;
5605   int destreg = ((instruction >> 6) & 0x0000001F);
5606   int fs = ((instruction >> 11) & 0x0000001F);
5607   int ft = ((instruction >> 16) & 0x0000001F);
5608   int fr = ((instruction >> 21) & 0x0000001F);
5609   {
5610    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5611   }
5612 }
5613
5614
5615 // NMSUB.fmt
5616 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5617 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5618 *mipsIV:
5619 *vr5000:
5620 // start-sanitize-vr4320
5621 *vr4320:
5622 // end-sanitize-vr4320
5623 // start-sanitize-cygnus
5624 *vr5400:
5625 // end-sanitize-cygnus
5626 {
5627   unsigned32 instruction = instruction_0;
5628   int destreg = ((instruction >> 6) & 0x0000001F);
5629   int fs = ((instruction >> 11) & 0x0000001F);
5630   int ft = ((instruction >> 16) & 0x0000001F);
5631   int fr = ((instruction >> 21) & 0x0000001F);
5632   {
5633    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5634   }
5635 }
5636
5637
5638 // NMSUB.fmt
5639 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5640 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5641 *mipsIV:
5642 *vr5000:
5643 // start-sanitize-vr4320
5644 *vr4320:
5645 // end-sanitize-vr4320
5646 // start-sanitize-cygnus
5647 *vr5400:
5648 // end-sanitize-cygnus
5649 {
5650   unsigned32 instruction = instruction_0;
5651   int destreg = ((instruction >> 6) & 0x0000001F);
5652   int fs = ((instruction >> 11) & 0x0000001F);
5653   int ft = ((instruction >> 16) & 0x0000001F);
5654   int fr = ((instruction >> 21) & 0x0000001F);
5655   {
5656     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5657   }
5658 }
5659
5660
5661 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5662 "prefx <HINT>, r<INDEX>(r<BASE>)"
5663 *mipsIV:
5664 *vr5000:
5665 // start-sanitize-vr4320
5666 *vr4320:
5667 // end-sanitize-vr4320
5668 // start-sanitize-cygnus
5669 *vr5400:
5670 // end-sanitize-cygnus
5671 {
5672   unsigned32 instruction = instruction_0;
5673   int fs = ((instruction >> 11) & 0x0000001F);
5674   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5675   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5676   {
5677     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5678     address_word paddr;
5679     int uncached;
5680     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5681       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5682   }
5683 }
5684
5685 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5686 *mipsIV:
5687 "recip.%s<FMT> f<FD>, f<FS>"
5688 *vr5000:
5689 // start-sanitize-vr4320
5690 *vr4320:
5691 // end-sanitize-vr4320
5692 // start-sanitize-cygnus
5693 *vr5400:
5694 // end-sanitize-cygnus
5695 {
5696   unsigned32 instruction = instruction_0;
5697   int destreg = ((instruction >> 6) & 0x0000001F);
5698   int fs = ((instruction >> 11) & 0x0000001F);
5699   int format = ((instruction >> 21) & 0x00000007);
5700   {
5701   if ((format != fmt_single) && (format != fmt_double))
5702    SignalException(ReservedInstruction,instruction);
5703   else
5704    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5705   }
5706 }
5707
5708
5709 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5710 "round.l.%s<FMT> f<FD>, f<FS>"
5711 *mipsIII:
5712 *mipsIV:
5713 *vr4100:
5714 *vr5000:
5715 // start-sanitize-vr4xxx
5716 *vr4121:
5717 // end-sanitize-vr4xxx
5718 // start-sanitize-vr4320
5719 *vr4320:
5720 // end-sanitize-vr4320
5721 // start-sanitize-cygnus
5722 *vr5400:
5723 // end-sanitize-cygnus
5724 // start-sanitize-r5900
5725 *r5900:
5726 // end-sanitize-r5900
5727 *r3900:
5728 // start-sanitize-tx19
5729 *tx19:
5730 // end-sanitize-tx19
5731 {
5732   unsigned32 instruction = instruction_0;
5733   int destreg = ((instruction >> 6) & 0x0000001F);
5734   int fs = ((instruction >> 11) & 0x0000001F);
5735   int format = ((instruction >> 21) & 0x00000007);
5736   {
5737     if ((format != fmt_single) && (format != fmt_double))
5738       SignalException(ReservedInstruction,instruction);
5739     else
5740       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5741   }
5742 }
5743
5744
5745 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5746 "round.w.%s<FMT> f<FD>, f<FS>"
5747 *mipsII:
5748 *mipsIII:
5749 *mipsIV:
5750 *vr4100:
5751 *vr5000:
5752 // start-sanitize-vr4xxx
5753 *vr4121:
5754 // end-sanitize-vr4xxx
5755 // start-sanitize-vr4320
5756 *vr4320:
5757 // end-sanitize-vr4320
5758 // start-sanitize-cygnus
5759 *vr5400:
5760 // end-sanitize-cygnus
5761 // start-sanitize-r5900
5762 *r5900:
5763 // end-sanitize-r5900
5764 *r3900:
5765 // start-sanitize-tx19
5766 *tx19:
5767 // end-sanitize-tx19
5768 {
5769   unsigned32 instruction = instruction_0;
5770   int destreg = ((instruction >> 6) & 0x0000001F);
5771   int fs = ((instruction >> 11) & 0x0000001F);
5772   int format = ((instruction >> 21) & 0x00000007);
5773   {
5774   if ((format != fmt_single) && (format != fmt_double))
5775    SignalException(ReservedInstruction,instruction);
5776   else
5777    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5778   }
5779 }
5780
5781
5782 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5783 *mipsIV:
5784 "rsqrt.%s<FMT> f<FD>, f<FS>"
5785 *vr5000:
5786 // start-sanitize-vr4320
5787 *vr4320:
5788 // end-sanitize-vr4320
5789 // start-sanitize-cygnus
5790 *vr5400:
5791 // end-sanitize-cygnus
5792 {
5793   unsigned32 instruction = instruction_0;
5794   int destreg = ((instruction >> 6) & 0x0000001F);
5795   int fs = ((instruction >> 11) & 0x0000001F);
5796   int format = ((instruction >> 21) & 0x00000007);
5797   {
5798   if ((format != fmt_single) && (format != fmt_double))
5799    SignalException(ReservedInstruction,instruction);
5800   else
5801    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5802   }
5803 }
5804
5805
5806 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5807 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5808 *mipsII:
5809 *mipsIII:
5810 *mipsIV:
5811 *vr4100:
5812 *vr5000:
5813 // start-sanitize-vr4xxx
5814 *vr4121:
5815 // end-sanitize-vr4xxx
5816 // start-sanitize-vr4320
5817 *vr4320:
5818 // end-sanitize-vr4320
5819 // start-sanitize-cygnus
5820 *vr5400:
5821 // end-sanitize-cygnus
5822 *r3900:
5823 // start-sanitize-tx19
5824 *tx19:
5825 // end-sanitize-tx19
5826 {
5827   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5828 }
5829
5830
5831 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5832 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5833 *mipsIV:
5834 *vr5000:
5835 // start-sanitize-vr4320
5836 *vr4320:
5837 // end-sanitize-vr4320
5838 // start-sanitize-cygnus
5839 *vr5400:
5840 // end-sanitize-cygnus
5841 {
5842   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5843 }
5844
5845
5846 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5847 "sqrt.%s<FMT> f<FD>, f<FS>"
5848 *mipsII:
5849 *mipsIII:
5850 *mipsIV:
5851 *vr4100:
5852 *vr5000:
5853 // start-sanitize-vr4xxx
5854 *vr4121:
5855 // end-sanitize-vr4xxx
5856 // start-sanitize-vr4320
5857 *vr4320:
5858 // end-sanitize-vr4320
5859 // start-sanitize-cygnus
5860 *vr5400:
5861 // end-sanitize-cygnus
5862 *r3900:
5863 // start-sanitize-tx19
5864 *tx19:
5865 // end-sanitize-tx19
5866 {
5867   unsigned32 instruction = instruction_0;
5868   int destreg = ((instruction >> 6) & 0x0000001F);
5869   int fs = ((instruction >> 11) & 0x0000001F);
5870   int format = ((instruction >> 21) & 0x00000007);
5871   {
5872     if ((format != fmt_single) && (format != fmt_double))
5873       SignalException(ReservedInstruction,instruction);
5874     else
5875       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5876   }
5877 }
5878
5879
5880 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5881 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5882 *mipsI,mipsII,mipsIII,mipsIV:
5883 *vr4100:
5884 *vr5000:
5885 // start-sanitize-vr4xxx
5886 *vr4121:
5887 // end-sanitize-vr4xxx
5888 // start-sanitize-vr4320
5889 *vr4320:
5890 // end-sanitize-vr4320
5891 // start-sanitize-cygnus
5892 *vr5400:
5893 // end-sanitize-cygnus
5894 *r3900:
5895 // start-sanitize-tx19
5896 *tx19:
5897 // end-sanitize-tx19
5898 {
5899   unsigned32 instruction = instruction_0;
5900   int destreg = ((instruction >> 6) & 0x0000001F);
5901   int fs = ((instruction >> 11) & 0x0000001F);
5902   int ft = ((instruction >> 16) & 0x0000001F);
5903   int format = ((instruction >> 21) & 0x00000007);
5904   {
5905     if ((format != fmt_single) && (format != fmt_double))
5906       SignalException(ReservedInstruction,instruction);
5907     else
5908       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5909   }
5910 }
5911
5912
5913
5914 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5915 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5916 *mipsI,mipsII,mipsIII,mipsIV:
5917 *vr4100:
5918 *vr5000:
5919 // start-sanitize-vr4xxx
5920 *vr4121:
5921 // end-sanitize-vr4xxx
5922 // start-sanitize-vr4320
5923 *vr4320:
5924 // end-sanitize-vr4320
5925 // start-sanitize-cygnus
5926 *vr5400:
5927 // end-sanitize-cygnus
5928 // start-sanitize-r5900
5929 *r5900:
5930 // end-sanitize-r5900
5931 *r3900:
5932 // start-sanitize-tx19
5933 *tx19:
5934 // end-sanitize-tx19
5935 {
5936   unsigned32 instruction = instruction_0;
5937   signed_word offset = EXTEND16 (OFFSET);
5938   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5939   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5940   {
5941     address_word vaddr = ((uword64)op1 + offset);
5942     address_word paddr;
5943     int uncached;
5944     if ((vaddr & 3) != 0)
5945       SignalExceptionAddressStore();
5946     else
5947       {
5948         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5949           {
5950             uword64 memval = 0;
5951             uword64 memval1 = 0;
5952             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5953             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5954             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5955             unsigned int byte;
5956             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5957             byte = ((vaddr & mask) ^ bigendiancpu);
5958             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5959             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5960           }
5961       }
5962   }
5963 }
5964
5965
5966 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5967 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5968 *mipsIV:
5969 *vr5000:
5970 // start-sanitize-vr4320
5971 *vr4320:
5972 // end-sanitize-vr4320
5973 // start-sanitize-cygnus
5974 *vr5400:
5975 // end-sanitize-cygnus
5976 {
5977   unsigned32 instruction = instruction_0;
5978   int fs = ((instruction >> 11) & 0x0000001F);
5979   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5980   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5981   {
5982    address_word vaddr = ((unsigned64)op1 + op2);
5983    address_word paddr;
5984    int uncached;
5985    if ((vaddr & 3) != 0)
5986     SignalExceptionAddressStore();
5987    else
5988    {
5989     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5990     {
5991      unsigned64 memval = 0;
5992      unsigned64 memval1 = 0;
5993      unsigned64 mask = 0x7;
5994      unsigned int byte;
5995      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5996      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5997      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5998       {
5999        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
6000       }
6001     }
6002    }
6003   }
6004 }
6005
6006
6007 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
6008 "trunc.l.%s<FMT> f<FD>, f<FS>"
6009 *mipsIII:
6010 *mipsIV:
6011 *vr4100:
6012 *vr5000:
6013 // start-sanitize-vr4xxx
6014 *vr4121:
6015 // end-sanitize-vr4xxx
6016 // start-sanitize-vr4320
6017 *vr4320:
6018 // end-sanitize-vr4320
6019 // start-sanitize-cygnus
6020 *vr5400:
6021 // end-sanitize-cygnus
6022 // start-sanitize-r5900
6023 *r5900:
6024 // end-sanitize-r5900
6025 *r3900:
6026 // start-sanitize-tx19
6027 *tx19:
6028 // end-sanitize-tx19
6029 {
6030   unsigned32 instruction = instruction_0;
6031   int destreg = ((instruction >> 6) & 0x0000001F);
6032   int fs = ((instruction >> 11) & 0x0000001F);
6033   int format = ((instruction >> 21) & 0x00000007);
6034   {
6035   if ((format != fmt_single) && (format != fmt_double))
6036    SignalException(ReservedInstruction,instruction);
6037   else
6038    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
6039   }
6040 }
6041
6042
6043 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
6044 "trunc.w.%s<FMT> f<FD>, f<FS>"
6045 *mipsII:
6046 *mipsIII:
6047 *mipsIV:
6048 *vr4100:
6049 *vr5000:
6050 // start-sanitize-vr4xxx
6051 *vr4121:
6052 // end-sanitize-vr4xxx
6053 // start-sanitize-vr4320
6054 *vr4320:
6055 // end-sanitize-vr4320
6056 // start-sanitize-cygnus
6057 *vr5400:
6058 // end-sanitize-cygnus
6059 // start-sanitize-r5900
6060 *r5900:
6061 // end-sanitize-r5900
6062 *r3900:
6063 // start-sanitize-tx19
6064 *tx19:
6065 // end-sanitize-tx19
6066 {
6067   unsigned32 instruction = instruction_0;
6068   int destreg = ((instruction >> 6) & 0x0000001F);
6069   int fs = ((instruction >> 11) & 0x0000001F);
6070   int format = ((instruction >> 21) & 0x00000007);
6071   {
6072   if ((format != fmt_single) && (format != fmt_double))
6073    SignalException(ReservedInstruction,instruction);
6074   else
6075    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
6076   }
6077 }
6078
6079 \f
6080 //
6081 // MIPS Architecture:
6082 //
6083 //        System Control Instruction Set (COP0)
6084 //
6085
6086
6087 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6088 "bc0f <OFFSET>"
6089 *mipsI,mipsII,mipsIII,mipsIV:
6090 *vr4100:
6091 *vr5000:
6092 // start-sanitize-vr4xxx
6093 *vr4121:
6094 // end-sanitize-vr4xxx
6095 // start-sanitize-vr4320
6096 *vr4320:
6097 // end-sanitize-vr4320
6098 // start-sanitize-cygnus
6099 *vr5400:
6100 // end-sanitize-cygnus
6101
6102
6103 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6104 "bc0fl <OFFSET>"
6105 *mipsI,mipsII,mipsIII,mipsIV:
6106 *vr4100:
6107 *vr5000:
6108 // start-sanitize-vr4xxx
6109 *vr4121:
6110 // end-sanitize-vr4xxx
6111 // start-sanitize-vr4320
6112 *vr4320:
6113 // end-sanitize-vr4320
6114 // start-sanitize-cygnus
6115 *vr5400:
6116 // end-sanitize-cygnus
6117
6118
6119 010000,01000,00001,16.OFFSET:COP0:32::BC0T
6120 "bc0t <OFFSET>"
6121 *mipsI,mipsII,mipsIII,mipsIV:
6122 *vr4100:
6123 // start-sanitize-vr4xxx
6124 *vr4121:
6125 // end-sanitize-vr4xxx
6126
6127
6128 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
6129 "bc0tl <OFFSET>"
6130 *mipsI,mipsII,mipsIII,mipsIV:
6131 *vr4100:
6132 *vr5000:
6133 // start-sanitize-vr4xxx
6134 *vr4121:
6135 // end-sanitize-vr4xxx
6136 // start-sanitize-vr4320
6137 *vr4320:
6138 // end-sanitize-vr4320
6139 // start-sanitize-cygnus
6140 *vr5400:
6141 // end-sanitize-cygnus
6142
6143
6144 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
6145 *mipsIII:
6146 *mipsIV:
6147 *vr4100:
6148 *vr5000:
6149 // start-sanitize-vr4xxx
6150 *vr4121:
6151 // end-sanitize-vr4xxx
6152 // start-sanitize-vr4320
6153 *vr4320:
6154 // end-sanitize-vr4320
6155 // start-sanitize-cygnus
6156 *vr5400:
6157 // end-sanitize-cygnus
6158 *r3900:
6159 // start-sanitize-tx19
6160 *tx19:
6161 // end-sanitize-tx19
6162 {
6163   unsigned32 instruction = instruction_0;
6164   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6165   int hint = ((instruction >> 16) & 0x0000001F);
6166   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6167   {
6168     address_word vaddr = (op1 + offset);
6169     address_word paddr;
6170     int uncached;
6171     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
6172       CacheOp(hint,vaddr,paddr,instruction);
6173   }
6174 }
6175
6176
6177 010000,10000,000000000000000,111001:COP0:32::DI
6178 "di"
6179 *mipsI,mipsII,mipsIII,mipsIV:
6180 *vr4100:
6181 *vr5000:
6182 // start-sanitize-vr4xxx
6183 *vr4121:
6184 // end-sanitize-vr4xxx
6185 // start-sanitize-vr4320
6186 *vr4320:
6187 // end-sanitize-vr4320
6188 // start-sanitize-cygnus
6189 *vr5400:
6190 // end-sanitize-cygnus
6191
6192
6193 010000,10000,000000000000000,111000:COP0:32::EI
6194 "ei"
6195 *mipsI,mipsII,mipsIII,mipsIV:
6196 *vr4100:
6197 *vr5000:
6198 // start-sanitize-vr4xxx
6199 *vr4121:
6200 // end-sanitize-vr4xxx
6201 // start-sanitize-vr4320
6202 *vr4320:
6203 // end-sanitize-vr4320
6204 // start-sanitize-cygnus
6205 *vr5400:
6206 // end-sanitize-cygnus
6207
6208
6209 010000,10000,000000000000000,011000:COP0:32::ERET
6210 "eret"
6211 *mipsIII:
6212 *mipsIV:
6213 *vr4100:
6214 *vr5000:
6215 // start-sanitize-vr4xxx
6216 *vr4121:
6217 // end-sanitize-vr4xxx
6218 // start-sanitize-vr4320
6219 *vr4320:
6220 // end-sanitize-vr4320
6221 // start-sanitize-cygnus
6222 *vr5400:
6223 // end-sanitize-cygnus
6224 // start-sanitize-r5900
6225 *r5900:
6226 // end-sanitize-r5900
6227 {
6228   if (SR & status_ERL)
6229     {
6230       /* Oops, not yet available */
6231       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6232       NIA = EPC;
6233       SR &= ~status_ERL;
6234     }
6235   else
6236     {
6237       NIA = EPC;
6238       SR &= ~status_EXL;
6239     }
6240 }
6241
6242
6243 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
6244 "mfc0 r<RT>, r<RD> # <REGX>"
6245 *mipsI,mipsII,mipsIII,mipsIV:
6246 *r3900:
6247 *vr4100:
6248 *vr5000:
6249 // start-sanitize-vr4xxx
6250 *vr4121:
6251 // end-sanitize-vr4xxx
6252 // start-sanitize-vr4320
6253 *vr4320:
6254 // end-sanitize-vr4320
6255 // start-sanitize-cygnus
6256 *vr5400:
6257 // end-sanitize-cygnus
6258 // start-sanitize-r5900
6259 *r5900:
6260 // end-sanitize-r5900
6261 {
6262   TRACE_ALU_INPUT0 ();
6263   DecodeCoproc (instruction_0);
6264   TRACE_ALU_RESULT (GPR[RT]);
6265 }
6266
6267 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
6268 "mtc0 r<RT>, r<RD> # <REGX>"
6269 *mipsI,mipsII,mipsIII,mipsIV:
6270 // start-sanitize-tx19
6271 *tx19:
6272 // end-sanitize-tx19
6273 *r3900:
6274 *vr4100:
6275 // start-sanitize-vr4xxx
6276 *vr4121:
6277 // end-sanitize-vr4xxx
6278 // start-sanitize-vr4320
6279 *vr4320:
6280 // end-sanitize-vr4320
6281 *vr5000:
6282 // start-sanitize-cygnus
6283 *vr5400:
6284 // end-sanitize-cygnus
6285 // start-sanitize-r5900
6286 *r5900:
6287 // end-sanitize-r5900
6288 {
6289   DecodeCoproc (instruction_0);
6290 }
6291
6292
6293 010000,10000,000000000000000,010000:COP0:32::RFE
6294 "rfe"
6295 *mipsI,mipsII,mipsIII,mipsIV:
6296 // start-sanitize-tx19
6297 *tx19:
6298 // end-sanitize-tx19
6299 *r3900:
6300 *vr4100:
6301 // start-sanitize-vr4xxx
6302 *vr4121:
6303 // end-sanitize-vr4xxx
6304 // start-sanitize-vr4320
6305 *vr4320:
6306 // end-sanitize-vr4320
6307 *vr5000:
6308 // start-sanitize-cygnus
6309 *vr5400:
6310 // end-sanitize-cygnus
6311 // start-sanitize-r5900
6312 *r5900:
6313 // end-sanitize-r5900
6314 {
6315   DecodeCoproc (instruction_0);
6316 }
6317
6318
6319 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6320 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
6321 *mipsI,mipsII,mipsIII,mipsIV:
6322 *vr4100:
6323 // start-sanitize-vr4xxx
6324 *vr4121:
6325 // end-sanitize-vr4xxx
6326 // start-sanitize-r5900
6327 *r5900:
6328 // end-sanitize-r5900
6329 *r3900:
6330 // start-sanitize-tx19
6331 *tx19:
6332 // end-sanitize-tx19
6333 {
6334   DecodeCoproc (instruction_0);
6335 }
6336
6337
6338
6339 010000,10000,000000000000000,001000:COP0:32::TLBP
6340 "tlbp"
6341 *mipsI,mipsII,mipsIII,mipsIV:
6342 *vr4100:
6343 *vr5000:
6344 // start-sanitize-vr4xxx
6345 *vr4121:
6346 // end-sanitize-vr4xxx
6347 // start-sanitize-vr4320
6348 *vr4320:
6349 // end-sanitize-vr4320
6350 // start-sanitize-cygnus
6351 *vr5400:
6352 // end-sanitize-cygnus
6353
6354
6355 010000,10000,000000000000000,000001:COP0:32::TLBR
6356 "tlbr"
6357 *mipsI,mipsII,mipsIII,mipsIV:
6358 *vr4100:
6359 *vr5000:
6360 // start-sanitize-vr4xxx
6361 *vr4121:
6362 // end-sanitize-vr4xxx
6363 // start-sanitize-vr4320
6364 *vr4320:
6365 // end-sanitize-vr4320
6366 // start-sanitize-cygnus
6367 *vr5400:
6368 // end-sanitize-cygnus
6369
6370
6371 010000,10000,000000000000000,000010:COP0:32::TLBWI
6372 "tlbwi"
6373 *mipsI,mipsII,mipsIII,mipsIV:
6374 *vr4100:
6375 *vr5000:
6376 // start-sanitize-vr4xxx
6377 *vr4121:
6378 // end-sanitize-vr4xxx
6379 // start-sanitize-vr4320
6380 *vr4320:
6381 // end-sanitize-vr4320
6382 // start-sanitize-cygnus
6383 *vr5400:
6384 // end-sanitize-cygnus
6385
6386
6387 010000,10000,000000000000000,000110:COP0:32::TLBWR
6388 "tlbwr"
6389 *mipsI,mipsII,mipsIII,mipsIV:
6390 *vr4100:
6391 *vr5000:
6392 // start-sanitize-vr4xxx
6393 *vr4121:
6394 // end-sanitize-vr4xxx
6395 // start-sanitize-vr4320
6396 *vr4320:
6397 // end-sanitize-vr4320
6398 // start-sanitize-cygnus
6399 *vr5400:
6400 // end-sanitize-cygnus
6401
6402 \f
6403 :include:::m16.igen
6404 // start-sanitize-cygnus
6405 :include:64,f::mdmx.igen
6406 // end-sanitize-cygnus
6407 // start-sanitize-r5900
6408 :include::r5900:r5900.igen
6409 // end-sanitize-r5900
6410 :include:::tx.igen
6411 :include:::vr.igen
6412 \f
6413 // start-sanitize-cygnus-never
6414
6415 // // FIXME FIXME FIXME What is this instruction?
6416 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
6417 // *mipsI:
6418 // *mipsII:
6419 // *mipsIII:
6420 // *mipsIV:
6421 // // start-sanitize-r5900
6422 // *r5900:
6423 // // end-sanitize-r5900
6424 // *r3900:
6425 // // start-sanitize-tx19
6426 // *tx19:
6427 // // end-sanitize-tx19
6428 // {
6429 //   unsigned32 instruction = instruction_0;
6430 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
6431 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
6432 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
6433 //   {
6434 //     if (CoProcPresent(3))
6435 //       SignalException(CoProcessorUnusable);
6436 //     else
6437 //       SignalException(ReservedInstruction,instruction);
6438 //   }
6439 // }
6440
6441 // end-sanitize-cygnus-never
6442 // start-sanitize-cygnus-never
6443
6444 // // FIXME FIXME FIXME What is this?
6445 // 11100,******,00001:RR:16::SDBBP
6446 // *mips16:
6447 // {
6448 //   unsigned32 instruction = instruction_0;
6449 //   if (have_extendval)
6450 //     SignalException (ReservedInstruction, instruction);
6451 //   {
6452 //     SignalException(DebugBreakPoint,instruction);
6453 //   }
6454 // }
6455
6456 // end-sanitize-cygnus-never
6457 // start-sanitize-cygnus-never
6458
6459 // // FIXME FIXME FIXME What is this?
6460 // 000000,********************,001110:SPECIAL:32::SDBBP
6461 // *r3900:
6462 // {
6463 //   unsigned32 instruction = instruction_0;
6464 //   {
6465 //     SignalException(DebugBreakPoint,instruction);
6466 //   }
6467 // }
6468
6469 // end-sanitize-cygnus-never