sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips64:mipsisa64:
  49
  50 //  Vendor ISAs:
  51 //
  52 //  Standard MIPS ISA instructions used for these models are listed here,
  53 //  as are functions needed by those standard instructions.  Instructions
  54 //  which are model-dependent and which are not in the standard MIPS ISAs
  55 //  (or which pre-date or use different encodings than the standard
  56 //  instructions) are (for the most part) in separate .igen files.
  57 :model:::vr4100:mips4100:               // vr.igen
  58 :model:::vr5000:mips5000:
  59 :model:::r3900:mips3900:                // tx.igen
  60
  61 //  MIPS Application Specific Extensions (ASEs)
  62 //
  63 //  Instructions for the ASEs are in separate .igen files.
  64 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  65
  66
  67 // Pseudo instructions known by IGEN
  68 :internal::::illegal:
  69 {
  70   SignalException (ReservedInstruction, 0);
  71 }
  72
  73
  74 // Pseudo instructions known by interp.c
  75 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  76 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  77 "rsvd <OP>"
  78 {
  79   SignalException (ReservedInstruction, instruction_0);
  80 }
  81
  82
  83
  84 // Helper:
  85 //
  86 // Simulate a 32 bit delayslot instruction
  87 //
  88
  89 :function:::address_word:delayslot32:address_word target
  90 {
  91   instruction_word delay_insn;
  92   sim_events_slip (SD, 1);
  93   DSPC = CIA;
  94   CIA = CIA + 4; /* NOTE not mips16 */
  95   STATE |= simDELAYSLOT;
  96   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  97   ENGINE_ISSUE_PREFIX_HOOK();
  98   idecode_issue (CPU_, delay_insn, (CIA));
  99   STATE &= ~simDELAYSLOT;
 100   return target;
 101 }
 102
 103 :function:::address_word:nullify_next_insn32:
 104 {
 105   sim_events_slip (SD, 1);
 106   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 107   return CIA + 8;
 108 }
 109
 110
 111 // Helper:
 112 //
 113 // Calculate an effective address given a base and an offset.
 114 //
 115
 116 :function:::address_word:loadstore_ea:address_word base, address_word offset
 117 *mipsI:
 118 *mipsII:
 119 *mipsIII:
 120 *mipsIV:
 121 *mipsV:
 122 *mips32:
 123 *vr4100:
 124 *vr5000:
 125 *r3900:
 126 {
 127   return base + offset;
 128 }
 129
 130 :function:::address_word:loadstore_ea:address_word base, address_word offset
 131 *mips64:
 132 {
 133 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 134   /* If in user mode and UX is not set, use 32-bit compatibility effective
 135      address computations as defined in the MIPS64 Architecture for
 136      Programmers Volume III, Revision 0.95, section 4.9.  */
 137   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 138       == (ksu_user << status_KSU_shift))
 139     return (address_word)((signed32)base + (signed32)offset);
 140 #endif
 141   return base + offset;
 142 }
 143
 144
 145 // Helper:
 146 //
 147 // Check that a 32-bit register value is properly sign-extended.
 148 // (See NotWordValue in ISA spec.)
 149 //
 150
 151 :function:::int:not_word_value:unsigned_word value
 152 *mipsI:
 153 *mipsII:
 154 *mipsIII:
 155 *mipsIV:
 156 *mipsV:
 157 *vr4100:
 158 *vr5000:
 159 *r3900:
 160 {
 161   /* For historical simulator compatibility (until documentation is
 162      found that makes these operations unpredictable on some of these
 163      architectures), this check never returns true.  */
 164   return 0;
 165 }
 166
 167 :function:::int:not_word_value:unsigned_word value
 168 *mips32:
 169 {
 170   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 171   return 0;
 172 }
 173
 174 :function:::int:not_word_value:unsigned_word value
 175 *mips64:
 176 {
 177   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 178 }
 179
 180
 181 // Helper:
 182 //
 183 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 184 // theoretically portable code which invokes non-portable behaviour from
 185 // running with no indication of the portability issue.
 186 // (See definition of UNPREDICTABLE in ISA spec.)
 187 //
 188
 189 :function:::void:unpredictable:
 190 *mipsI:
 191 *mipsII:
 192 *mipsIII:
 193 *mipsIV:
 194 *mipsV:
 195 *vr4100:
 196 *vr5000:
 197 *r3900:
 198 {
 199 }
 200
 201 :function:::void:unpredictable:
 202 *mips32:
 203 *mips64:
 204 {
 205   unpredictable_action (CPU, CIA);
 206 }
 207
 208
 209 // Helper:
 210 //
 211 // Check that an access to a HI/LO register meets timing requirements
 212 //
 213 // The following requirements exist:
 214 //
 215 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 216 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 217 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 218 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 219 //
 220
 221 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 222 {
 223   if (history->mf.timestamp + 3 > time)
 224     {
 225       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 226                         itable[MY_INDEX].name,
 227                         new, (long) CIA,
 228                         (long) history->mf.cia);
 229       return 0;
 230     }
 231   return 1;
 232 }
 233
 234 :function:::int:check_mt_hilo:hilo_history *history
 235 *mipsI:
 236 *mipsII:
 237 *mipsIII:
 238 *mipsIV:
 239 *mipsV:
 240 *vr4100:
 241 *vr5000:
 242 {
 243   signed64 time = sim_events_time (SD);
 244   int ok = check_mf_cycles (SD_, history, time, "MT");
 245   history->mt.timestamp = time;
 246   history->mt.cia = CIA;
 247   return ok;
 248 }
 249
 250 :function:::int:check_mt_hilo:hilo_history *history
 251 *mips32:
 252 *mips64:
 253 *r3900:
 254 {
 255   signed64 time = sim_events_time (SD);
 256   history->mt.timestamp = time;
 257   history->mt.cia = CIA;
 258   return 1;
 259 }
 260
 261
 262 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 263 *mipsI:
 264 *mipsII:
 265 *mipsIII:
 266 *mipsIV:
 267 *mipsV:
 268 *mips32:
 269 *mips64:
 270 *vr4100:
 271 *vr5000:
 272 *r3900:
 273 {
 274   signed64 time = sim_events_time (SD);
 275   int ok = 1;
 276   if (peer != NULL
 277       && peer->mt.timestamp > history->op.timestamp
 278       && history->mt.timestamp < history->op.timestamp
 279       && ! (history->mf.timestamp > history->op.timestamp
 280             && history->mf.timestamp < peer->mt.timestamp)
 281       && ! (peer->mf.timestamp > history->op.timestamp
 282             && peer->mf.timestamp < peer->mt.timestamp))
 283     {
 284       /* The peer has been written to since the last OP yet we have
 285          not */
 286       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 287                         itable[MY_INDEX].name,
 288                         (long) CIA,
 289                         (long) history->op.cia,
 290                         (long) peer->mt.cia);
 291       ok = 0;
 292     }
 293   history->mf.timestamp = time;
 294   history->mf.cia = CIA;
 295   return ok;
 296 }
 297
 298
 299
 300 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 301 *mipsI:
 302 *mipsII:
 303 *mipsIII:
 304 *mipsIV:
 305 *mipsV:
 306 *vr4100:
 307 *vr5000:
 308 {
 309   signed64 time = sim_events_time (SD);
 310   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 311             && check_mf_cycles (SD_, lo, time, "OP"));
 312   hi->op.timestamp = time;
 313   lo->op.timestamp = time;
 314   hi->op.cia = CIA;
 315   lo->op.cia = CIA;
 316   return ok;
 317 }
 318
 319 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 320 // a mf{hi,lo}
 321 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 322 *mips32:
 323 *mips64:
 324 *r3900:
 325 {
 326   /* FIXME: could record the fact that a stall occured if we want */
 327   signed64 time = sim_events_time (SD);
 328   hi->op.timestamp = time;
 329   lo->op.timestamp = time;
 330   hi->op.cia = CIA;
 331   lo->op.cia = CIA;
 332   return 1;
 333 }
 334
 335
 336 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 337 *mipsI:
 338 *mipsII:
 339 *mipsIII:
 340 *mipsIV:
 341 *mipsV:
 342 *mips32:
 343 *mips64:
 344 *vr4100:
 345 *vr5000:
 346 *r3900:
 347 {
 348   signed64 time = sim_events_time (SD);
 349   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 350             && check_mf_cycles (SD_, lo, time, "OP"));
 351   hi->op.timestamp = time;
 352   lo->op.timestamp = time;
 353   hi->op.cia = CIA;
 354   lo->op.cia = CIA;
 355   return ok;
 356 }
 357
 358
 359 // Helper:
 360 //
 361 // Check that the 64-bit instruction can currently be used, and signal
 362 // a ReservedInstruction exception if not.
 363 //
 364
 365 :function:::void:check_u64:instruction_word insn
 366 *mipsIII:
 367 *mipsIV:
 368 *mipsV:
 369 *vr4100:
 370 *vr5000:
 371 {
 372   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 373 }
 374
 375 :function:::void:check_u64:instruction_word insn
 376 *mips64:
 377 {
 378 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 379   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 380     SignalException (ReservedInstruction, insn);
 381 #endif
 382 }
 383
 384
 385
 386 //
 387 // MIPS Architecture:
 388 //
 389 //        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 390 //
 391
 392
 393
 394 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 395 "add r<RD>, r<RS>, r<RT>"
 396 *mipsI:
 397 *mipsII:
 398 *mipsIII:
 399 *mipsIV:
 400 *mipsV:
 401 *mips32:
 402 *mips64:
 403 *vr4100:
 404 *vr5000:
 405 *r3900:
 406 {
 407   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 408     Unpredictable ();
 409   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 410   {
 411     ALU32_BEGIN (GPR[RS]);
 412     ALU32_ADD (GPR[RT]);
 413     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 414   }
 415   TRACE_ALU_RESULT (GPR[RD]);
 416 }
 417
 418
 419
 420 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 421 "addi r<RT>, r<RS>, <IMMEDIATE>"
 422 *mipsI:
 423 *mipsII:
 424 *mipsIII:
 425 *mipsIV:
 426 *mipsV:
 427 *mips32:
 428 *mips64:
 429 *vr4100:
 430 *vr5000:
 431 *r3900:
 432 {
 433   if (NotWordValue (GPR[RS]))
 434     Unpredictable ();
 435   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 436   {
 437     ALU32_BEGIN (GPR[RS]);
 438     ALU32_ADD (EXTEND16 (IMMEDIATE));
 439     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 440   }
 441   TRACE_ALU_RESULT (GPR[RT]);
 442 }
 443
 444
 445
 446 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 447 {
 448   if (NotWordValue (GPR[rs]))
 449     Unpredictable ();
 450   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 451   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 452   TRACE_ALU_RESULT (GPR[rt]);
 453 }
 454
 455 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 456 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 457 *mipsI:
 458 *mipsII:
 459 *mipsIII:
 460 *mipsIV:
 461 *mipsV:
 462 *mips32:
 463 *mips64:
 464 *vr4100:
 465 *vr5000:
 466 *r3900:
 467 {
 468   do_addiu (SD_, RS, RT, IMMEDIATE);
 469 }
 470
 471
 472
 473 :function:::void:do_addu:int rs, int rt, int rd
 474 {
 475   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 476     Unpredictable ();
 477   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 478   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 479   TRACE_ALU_RESULT (GPR[rd]);
 480 }
 481
 482 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 483 "addu r<RD>, r<RS>, r<RT>"
 484 *mipsI:
 485 *mipsII:
 486 *mipsIII:
 487 *mipsIV:
 488 *mipsV:
 489 *mips32:
 490 *mips64:
 491 *vr4100:
 492 *vr5000:
 493 *r3900:
 494 {
 495   do_addu (SD_, RS, RT, RD);
 496 }
 497
 498
 499
 500 :function:::void:do_and:int rs, int rt, int rd
 501 {
 502   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 503   GPR[rd] = GPR[rs] & GPR[rt];
 504   TRACE_ALU_RESULT (GPR[rd]);
 505 }
 506
 507 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 508 "and r<RD>, r<RS>, r<RT>"
 509 *mipsI:
 510 *mipsII:
 511 *mipsIII:
 512 *mipsIV:
 513 *mipsV:
 514 *mips32:
 515 *mips64:
 516 *vr4100:
 517 *vr5000:
 518 *r3900:
 519 {
 520   do_and (SD_, RS, RT, RD);
 521 }
 522
 523
 524
 525 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 526 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 527 *mipsI:
 528 *mipsII:
 529 *mipsIII:
 530 *mipsIV:
 531 *mipsV:
 532 *mips32:
 533 *mips64:
 534 *vr4100:
 535 *vr5000:
 536 *r3900:
 537 {
 538   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 539   GPR[RT] = GPR[RS] & IMMEDIATE;
 540   TRACE_ALU_RESULT (GPR[RT]);
 541 }
 542
 543
 544
 545 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 546 "beq r<RS>, r<RT>, <OFFSET>"
 547 *mipsI:
 548 *mipsII:
 549 *mipsIII:
 550 *mipsIV:
 551 *mipsV:
 552 *mips32:
 553 *mips64:
 554 *vr4100:
 555 *vr5000:
 556 *r3900:
 557 {
 558   address_word offset = EXTEND16 (OFFSET) << 2;
 559   check_branch_bug ();
 560   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 561     {
 562       mark_branch_bug (NIA+offset);
 563       DELAY_SLOT (NIA + offset);
 564     }
 565 }
 566
 567
 568
 569 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 570 "beql r<RS>, r<RT>, <OFFSET>"
 571 *mipsII:
 572 *mipsIII:
 573 *mipsIV:
 574 *mipsV:
 575 *mips32:
 576 *mips64:
 577 *vr4100:
 578 *vr5000:
 579 *r3900:
 580 {
 581   address_word offset = EXTEND16 (OFFSET) << 2;
 582   check_branch_bug ();
 583   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 584     {
 585       mark_branch_bug (NIA+offset);
 586       DELAY_SLOT (NIA + offset);
 587     }
 588   else
 589     NULLIFY_NEXT_INSTRUCTION ();
 590 }
 591
 592
 593
 594 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 595 "bgez r<RS>, <OFFSET>"
 596 *mipsI:
 597 *mipsII:
 598 *mipsIII:
 599 *mipsIV:
 600 *mipsV:
 601 *mips32:
 602 *mips64:
 603 *vr4100:
 604 *vr5000:
 605 *r3900:
 606 {
 607   address_word offset = EXTEND16 (OFFSET) << 2;
 608   check_branch_bug ();
 609   if ((signed_word) GPR[RS] >= 0)
 610     {
 611       mark_branch_bug (NIA+offset);
 612       DELAY_SLOT (NIA + offset);
 613     }
 614 }
 615
 616
 617
 618 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 619 "bgezal r<RS>, <OFFSET>"
 620 *mipsI:
 621 *mipsII:
 622 *mipsIII:
 623 *mipsIV:
 624 *mipsV:
 625 *mips32:
 626 *mips64:
 627 *vr4100:
 628 *vr5000:
 629 *r3900:
 630 {
 631   address_word offset = EXTEND16 (OFFSET) << 2;
 632   check_branch_bug ();
 633   if (RS == 31)
 634     Unpredictable ();
 635   RA = (CIA + 8);
 636   if ((signed_word) GPR[RS] >= 0)
 637     {
 638       mark_branch_bug (NIA+offset);
 639       DELAY_SLOT (NIA + offset);
 640     }
 641 }
 642
 643
 644
 645 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 646 "bgezall r<RS>, <OFFSET>"
 647 *mipsII:
 648 *mipsIII:
 649 *mipsIV:
 650 *mipsV:
 651 *mips32:
 652 *mips64:
 653 *vr4100:
 654 *vr5000:
 655 *r3900:
 656 {
 657   address_word offset = EXTEND16 (OFFSET) << 2;
 658   check_branch_bug ();
 659   if (RS == 31)
 660     Unpredictable ();
 661   RA = (CIA + 8);
 662   /* NOTE: The branch occurs AFTER the next instruction has been
 663      executed */
 664   if ((signed_word) GPR[RS] >= 0)
 665     {
 666       mark_branch_bug (NIA+offset);
 667       DELAY_SLOT (NIA + offset);
 668     }
 669   else
 670     NULLIFY_NEXT_INSTRUCTION ();
 671 }
 672
 673
 674
 675 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 676 "bgezl r<RS>, <OFFSET>"
 677 *mipsII:
 678 *mipsIII:
 679 *mipsIV:
 680 *mipsV:
 681 *mips32:
 682 *mips64:
 683 *vr4100:
 684 *vr5000:
 685 *r3900:
 686 {
 687   address_word offset = EXTEND16 (OFFSET) << 2;
 688   check_branch_bug ();
 689   if ((signed_word) GPR[RS] >= 0)
 690     {
 691       mark_branch_bug (NIA+offset);
 692       DELAY_SLOT (NIA + offset);
 693     }
 694   else
 695     NULLIFY_NEXT_INSTRUCTION ();
 696 }
 697
 698
 699
 700 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 701 "bgtz r<RS>, <OFFSET>"
 702 *mipsI:
 703 *mipsII:
 704 *mipsIII:
 705 *mipsIV:
 706 *mipsV:
 707 *mips32:
 708 *mips64:
 709 *vr4100:
 710 *vr5000:
 711 *r3900:
 712 {
 713   address_word offset = EXTEND16 (OFFSET) << 2;
 714   check_branch_bug ();
 715   if ((signed_word) GPR[RS] > 0)
 716     {
 717       mark_branch_bug (NIA+offset);
 718       DELAY_SLOT (NIA + offset);
 719     }
 720 }
 721
 722
 723
 724 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 725 "bgtzl r<RS>, <OFFSET>"
 726 *mipsII:
 727 *mipsIII:
 728 *mipsIV:
 729 *mipsV:
 730 *mips32:
 731 *mips64:
 732 *vr4100:
 733 *vr5000:
 734 *r3900:
 735 {
 736   address_word offset = EXTEND16 (OFFSET) << 2;
 737   check_branch_bug ();
 738   /* NOTE: The branch occurs AFTER the next instruction has been
 739      executed */
 740   if ((signed_word) GPR[RS] > 0)
 741     {
 742       mark_branch_bug (NIA+offset);
 743       DELAY_SLOT (NIA + offset);
 744     }
 745   else
 746     NULLIFY_NEXT_INSTRUCTION ();
 747 }
 748
 749
 750
 751 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 752 "blez r<RS>, <OFFSET>"
 753 *mipsI:
 754 *mipsII:
 755 *mipsIII:
 756 *mipsIV:
 757 *mipsV:
 758 *mips32:
 759 *mips64:
 760 *vr4100:
 761 *vr5000:
 762 *r3900:
 763 {
 764   address_word offset = EXTEND16 (OFFSET) << 2;
 765   check_branch_bug ();
 766   /* NOTE: The branch occurs AFTER the next instruction has been
 767      executed */
 768   if ((signed_word) GPR[RS] <= 0)
 769     {
 770       mark_branch_bug (NIA+offset);
 771       DELAY_SLOT (NIA + offset);
 772     }
 773 }
 774
 775
 776
 777 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 778 "bgezl r<RS>, <OFFSET>"
 779 *mipsII:
 780 *mipsIII:
 781 *mipsIV:
 782 *mipsV:
 783 *mips32:
 784 *mips64:
 785 *vr4100:
 786 *vr5000:
 787 *r3900:
 788 {
 789   address_word offset = EXTEND16 (OFFSET) << 2;
 790   check_branch_bug ();
 791   if ((signed_word) GPR[RS] <= 0)
 792     {
 793       mark_branch_bug (NIA+offset);
 794       DELAY_SLOT (NIA + offset);
 795     }
 796   else
 797     NULLIFY_NEXT_INSTRUCTION ();
 798 }
 799
 800
 801
 802 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 803 "bltz r<RS>, <OFFSET>"
 804 *mipsI:
 805 *mipsII:
 806 *mipsIII:
 807 *mipsIV:
 808 *mipsV:
 809 *mips32:
 810 *mips64:
 811 *vr4100:
 812 *vr5000:
 813 *r3900:
 814 {
 815   address_word offset = EXTEND16 (OFFSET) << 2;
 816   check_branch_bug ();
 817   if ((signed_word) GPR[RS] < 0)
 818     {
 819       mark_branch_bug (NIA+offset);
 820       DELAY_SLOT (NIA + offset);
 821     }
 822 }
 823
 824
 825
 826 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 827 "bltzal r<RS>, <OFFSET>"
 828 *mipsI:
 829 *mipsII:
 830 *mipsIII:
 831 *mipsIV:
 832 *mipsV:
 833 *mips32:
 834 *mips64:
 835 *vr4100:
 836 *vr5000:
 837 *r3900:
 838 {
 839   address_word offset = EXTEND16 (OFFSET) << 2;
 840   check_branch_bug ();
 841   if (RS == 31)
 842     Unpredictable ();
 843   RA = (CIA + 8);
 844   /* NOTE: The branch occurs AFTER the next instruction has been
 845      executed */
 846   if ((signed_word) GPR[RS] < 0)
 847     {
 848       mark_branch_bug (NIA+offset);
 849       DELAY_SLOT (NIA + offset);
 850     }
 851 }
 852
 853
 854
 855 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 856 "bltzall r<RS>, <OFFSET>"
 857 *mipsII:
 858 *mipsIII:
 859 *mipsIV:
 860 *mipsV:
 861 *mips32:
 862 *mips64:
 863 *vr4100:
 864 *vr5000:
 865 *r3900:
 866 {
 867   address_word offset = EXTEND16 (OFFSET) << 2;
 868   check_branch_bug ();
 869   if (RS == 31)
 870     Unpredictable ();
 871   RA = (CIA + 8);
 872   if ((signed_word) GPR[RS] < 0)
 873     {
 874       mark_branch_bug (NIA+offset);
 875       DELAY_SLOT (NIA + offset);
 876     }
 877   else
 878     NULLIFY_NEXT_INSTRUCTION ();
 879 }
 880
 881
 882
 883 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 884 "bltzl r<RS>, <OFFSET>"
 885 *mipsII:
 886 *mipsIII:
 887 *mipsIV:
 888 *mipsV:
 889 *mips32:
 890 *mips64:
 891 *vr4100:
 892 *vr5000:
 893 *r3900:
 894 {
 895   address_word offset = EXTEND16 (OFFSET) << 2;
 896   check_branch_bug ();
 897   /* NOTE: The branch occurs AFTER the next instruction has been
 898      executed */
 899   if ((signed_word) GPR[RS] < 0)
 900     {
 901       mark_branch_bug (NIA+offset);
 902       DELAY_SLOT (NIA + offset);
 903     }
 904   else
 905     NULLIFY_NEXT_INSTRUCTION ();
 906 }
 907
 908
 909
 910 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 911 "bne r<RS>, r<RT>, <OFFSET>"
 912 *mipsI:
 913 *mipsII:
 914 *mipsIII:
 915 *mipsIV:
 916 *mipsV:
 917 *mips32:
 918 *mips64:
 919 *vr4100:
 920 *vr5000:
 921 *r3900:
 922 {
 923   address_word offset = EXTEND16 (OFFSET) << 2;
 924   check_branch_bug ();
 925   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 926     {
 927       mark_branch_bug (NIA+offset);
 928       DELAY_SLOT (NIA + offset);
 929     }
 930 }
 931
 932
 933
 934 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 935 "bnel r<RS>, r<RT>, <OFFSET>"
 936 *mipsII:
 937 *mipsIII:
 938 *mipsIV:
 939 *mipsV:
 940 *mips32:
 941 *mips64:
 942 *vr4100:
 943 *vr5000:
 944 *r3900:
 945 {
 946   address_word offset = EXTEND16 (OFFSET) << 2;
 947   check_branch_bug ();
 948   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 949     {
 950       mark_branch_bug (NIA+offset);
 951       DELAY_SLOT (NIA + offset);
 952     }
 953   else
 954     NULLIFY_NEXT_INSTRUCTION ();
 955 }
 956
 957
 958
 959 000000,20.CODE,001101:SPECIAL:32::BREAK
 960 "break %#lx<CODE>"
 961 *mipsI:
 962 *mipsII:
 963 *mipsIII:
 964 *mipsIV:
 965 *mipsV:
 966 *mips32:
 967 *mips64:
 968 *vr4100:
 969 *vr5000:
 970 *r3900:
 971 {
 972   /* Check for some break instruction which are reserved for use by the simulator.  */
 973   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 974   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 975       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 976     {
 977       sim_engine_halt (SD, CPU, NULL, cia,
 978                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 979     }
 980   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 981            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 982     {
 983       if (STATE & simDELAYSLOT)
 984         PC = cia - 4; /* reference the branch instruction */
 985       else
 986         PC = cia;
 987       SignalException (BreakPoint, instruction_0);
 988     }
 989
 990   else
 991     {
 992       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 993          the exception. */
 994       SignalException (BreakPoint, instruction_0);
 995     }
 996 }
 997
 998
 999
1000 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1001 "clo r<RD>, r<RS>"
1002 *mips32:
1003 *mips64:
1004 {
1005   unsigned32 temp = GPR[RS];
1006   unsigned32 i, mask;
1007   if (RT != RD)
1008     Unpredictable ();
1009   if (NotWordValue (GPR[RS]))
1010     Unpredictable ();
1011   TRACE_ALU_INPUT1 (GPR[RS]);
1012   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1013     {
1014       if ((temp & mask) == 0)
1015         break;
1016       mask >>= 1;
1017     }
1018   GPR[RD] = EXTEND32 (i);
1019   TRACE_ALU_RESULT (GPR[RD]);
1020 }
1021
1022
1023
1024 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1025 "clz r<RD>, r<RS>"
1026 *mips32:
1027 *mips64:
1028 {
1029   unsigned32 temp = GPR[RS];
1030   unsigned32 i, mask;
1031   if (RT != RD)
1032     Unpredictable ();
1033   if (NotWordValue (GPR[RS]))
1034     Unpredictable ();
1035   TRACE_ALU_INPUT1 (GPR[RS]);
1036   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1037     {
1038       if ((temp & mask) != 0)
1039         break;
1040       mask >>= 1;
1041     }
1042   GPR[RD] = EXTEND32 (i);
1043   TRACE_ALU_RESULT (GPR[RD]);
1044 }
1045
1046
1047
1048 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1049 "dadd r<RD>, r<RS>, r<RT>"
1050 *mipsIII:
1051 *mipsIV:
1052 *mipsV:
1053 *mips64:
1054 *vr4100:
1055 *vr5000:
1056 {
1057   check_u64 (SD_, instruction_0);
1058   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1059   {
1060     ALU64_BEGIN (GPR[RS]);
1061     ALU64_ADD (GPR[RT]);
1062     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1063   }
1064   TRACE_ALU_RESULT (GPR[RD]);
1065 }
1066
1067
1068
1069 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1070 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1071 *mipsIII:
1072 *mipsIV:
1073 *mipsV:
1074 *mips64:
1075 *vr4100:
1076 *vr5000:
1077 {
1078   check_u64 (SD_, instruction_0);
1079   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1080   {
1081     ALU64_BEGIN (GPR[RS]);
1082     ALU64_ADD (EXTEND16 (IMMEDIATE));
1083     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1084   }
1085   TRACE_ALU_RESULT (GPR[RT]);
1086 }
1087
1088
1089
1090 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1091 {
1092   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1093   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1094   TRACE_ALU_RESULT (GPR[rt]);
1095 }
1096
1097 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1098 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1099 *mipsIII:
1100 *mipsIV:
1101 *mipsV:
1102 *mips64:
1103 *vr4100:
1104 *vr5000:
1105 {
1106   check_u64 (SD_, instruction_0);
1107   do_daddiu (SD_, RS, RT, IMMEDIATE);
1108 }
1109
1110
1111
1112 :function:::void:do_daddu:int rs, int rt, int rd
1113 {
1114   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1115   GPR[rd] = GPR[rs] + GPR[rt];
1116   TRACE_ALU_RESULT (GPR[rd]);
1117 }
1118
1119 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1120 "daddu r<RD>, r<RS>, r<RT>"
1121 *mipsIII:
1122 *mipsIV:
1123 *mipsV:
1124 *mips64:
1125 *vr4100:
1126 *vr5000:
1127 {
1128   check_u64 (SD_, instruction_0);
1129   do_daddu (SD_, RS, RT, RD);
1130 }
1131
1132
1133
1134 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1135 "dclo r<RD>, r<RS>"
1136 *mips64:
1137 {
1138   unsigned64 temp = GPR[RS];
1139   unsigned32 i;
1140   unsigned64 mask;
1141   check_u64 (SD_, instruction_0);
1142   if (RT != RD)
1143     Unpredictable ();
1144   TRACE_ALU_INPUT1 (GPR[RS]);
1145   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1146     {
1147       if ((temp & mask) == 0)
1148         break;
1149       mask >>= 1;
1150     }
1151   GPR[RD] = EXTEND32 (i);
1152   TRACE_ALU_RESULT (GPR[RD]);
1153 }
1154
1155
1156
1157 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1158 "dclz r<RD>, r<RS>"
1159 *mips64:
1160 {
1161   unsigned64 temp = GPR[RS];
1162   unsigned32 i;
1163   unsigned64 mask;
1164   check_u64 (SD_, instruction_0);
1165   if (RT != RD)
1166     Unpredictable ();
1167   TRACE_ALU_INPUT1 (GPR[RS]);
1168   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1169     {
1170       if ((temp & mask) != 0)
1171         break;
1172       mask >>= 1;
1173     }
1174   GPR[RD] = EXTEND32 (i);
1175   TRACE_ALU_RESULT (GPR[RD]);
1176 }
1177
1178
1179
1180 :function:::void:do_ddiv:int rs, int rt
1181 {
1182   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1183   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1184   {
1185     signed64 n = GPR[rs];
1186     signed64 d = GPR[rt];
1187     signed64 hi;
1188     signed64 lo;
1189     if (d == 0)
1190       {
1191         lo = SIGNED64 (0x8000000000000000);
1192         hi = 0;
1193       }
1194     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1195       {
1196         lo = SIGNED64 (0x8000000000000000);
1197         hi = 0;
1198       }
1199     else
1200       {
1201         lo = (n / d);
1202         hi = (n % d);
1203       }
1204     HI = hi;
1205     LO = lo;
1206   }
1207   TRACE_ALU_RESULT2 (HI, LO);
1208 }
1209
1210 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1211 "ddiv r<RS>, r<RT>"
1212 *mipsIII:
1213 *mipsIV:
1214 *mipsV:
1215 *mips64:
1216 *vr4100:
1217 *vr5000:
1218 {
1219   check_u64 (SD_, instruction_0);
1220   do_ddiv (SD_, RS, RT);
1221 }
1222
1223
1224
1225 :function:::void:do_ddivu:int rs, int rt
1226 {
1227   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1228   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1229   {
1230     unsigned64 n = GPR[rs];
1231     unsigned64 d = GPR[rt];
1232     unsigned64 hi;
1233     unsigned64 lo;
1234     if (d == 0)
1235       {
1236         lo = SIGNED64 (0x8000000000000000);
1237         hi = 0;
1238       }
1239     else
1240       {
1241         lo = (n / d);
1242         hi = (n % d);
1243       }
1244     HI = hi;
1245     LO = lo;
1246   }
1247   TRACE_ALU_RESULT2 (HI, LO);
1248 }
1249
1250 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1251 "ddivu r<RS>, r<RT>"
1252 *mipsIII:
1253 *mipsIV:
1254 *mipsV:
1255 *mips64:
1256 *vr4100:
1257 *vr5000:
1258 {
1259   check_u64 (SD_, instruction_0);
1260   do_ddivu (SD_, RS, RT);
1261 }
1262
1263
1264
1265 :function:::void:do_div:int rs, int rt
1266 {
1267   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1268   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1269   {
1270     signed32 n = GPR[rs];
1271     signed32 d = GPR[rt];
1272     if (d == 0)
1273       {
1274         LO = EXTEND32 (0x80000000);
1275         HI = EXTEND32 (0);
1276       }
1277     else if (n == SIGNED32 (0x80000000) && d == -1)
1278       {
1279         LO = EXTEND32 (0x80000000);
1280         HI = EXTEND32 (0);
1281       }
1282     else
1283       {
1284         LO = EXTEND32 (n / d);
1285         HI = EXTEND32 (n % d);
1286       }
1287   }
1288   TRACE_ALU_RESULT2 (HI, LO);
1289 }
1290
1291 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1292 "div r<RS>, r<RT>"
1293 *mipsI:
1294 *mipsII:
1295 *mipsIII:
1296 *mipsIV:
1297 *mipsV:
1298 *mips32:
1299 *mips64:
1300 *vr4100:
1301 *vr5000:
1302 *r3900:
1303 {
1304   do_div (SD_, RS, RT);
1305 }
1306
1307
1308
1309 :function:::void:do_divu:int rs, int rt
1310 {
1311   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1312   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1313   {
1314     unsigned32 n = GPR[rs];
1315     unsigned32 d = GPR[rt];
1316     if (d == 0)
1317       {
1318         LO = EXTEND32 (0x80000000);
1319         HI = EXTEND32 (0);
1320       }
1321     else
1322       {
1323         LO = EXTEND32 (n / d);
1324         HI = EXTEND32 (n % d);
1325       }
1326   }
1327   TRACE_ALU_RESULT2 (HI, LO);
1328 }
1329
1330 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1331 "divu r<RS>, r<RT>"
1332 *mipsI:
1333 *mipsII:
1334 *mipsIII:
1335 *mipsIV:
1336 *mipsV:
1337 *mips32:
1338 *mips64:
1339 *vr4100:
1340 *vr5000:
1341 *r3900:
1342 {
1343   do_divu (SD_, RS, RT);
1344 }
1345
1346
1347
1348 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1349 {
1350   unsigned64 lo;
1351   unsigned64 hi;
1352   unsigned64 m00;
1353   unsigned64 m01;
1354   unsigned64 m10;
1355   unsigned64 m11;
1356   unsigned64 mid;
1357   int sign;
1358   unsigned64 op1 = GPR[rs];
1359   unsigned64 op2 = GPR[rt];
1360   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1361   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1362   /* make signed multiply unsigned */
1363   sign = 0;
1364   if (signed_p)
1365     {
1366       if (op1 < 0)
1367         {
1368           op1 = - op1;
1369           ++sign;
1370         }
1371       if (op2 < 0)
1372         {
1373           op2 = - op2;
1374           ++sign;
1375         }
1376     }
1377   /* multiply out the 4 sub products */
1378   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1379   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1380   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1381   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1382   /* add the products */
1383   mid = ((unsigned64) VH4_8 (m00)
1384          + (unsigned64) VL4_8 (m10)
1385          + (unsigned64) VL4_8 (m01));
1386   lo = U8_4 (mid, m00);
1387   hi = (m11
1388         + (unsigned64) VH4_8 (mid)
1389         + (unsigned64) VH4_8 (m01)
1390         + (unsigned64) VH4_8 (m10));
1391   /* fix the sign */
1392   if (sign & 1)
1393     {
1394       lo = -lo;
1395       if (lo == 0)
1396         hi = -hi;
1397       else
1398         hi = -hi - 1;
1399     }
1400   /* save the result HI/LO (and a gpr) */
1401   LO = lo;
1402   HI = hi;
1403   if (rd != 0)
1404     GPR[rd] = lo;
1405   TRACE_ALU_RESULT2 (HI, LO);
1406 }
1407
1408 :function:::void:do_dmult:int rs, int rt, int rd
1409 {
1410   do_dmultx (SD_, rs, rt, rd, 1);
1411 }
1412
1413 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1414 "dmult r<RS>, r<RT>"
1415 *mipsIII:
1416 *mipsIV:
1417 *mipsV:
1418 *mips64:
1419 *vr4100:
1420 {
1421   check_u64 (SD_, instruction_0);
1422   do_dmult (SD_, RS, RT, 0);
1423 }
1424
1425 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1426 "dmult r<RS>, r<RT>":RD == 0
1427 "dmult r<RD>, r<RS>, r<RT>"
1428 *vr5000:
1429 {
1430   check_u64 (SD_, instruction_0);
1431   do_dmult (SD_, RS, RT, RD);
1432 }
1433
1434
1435
1436 :function:::void:do_dmultu:int rs, int rt, int rd
1437 {
1438   do_dmultx (SD_, rs, rt, rd, 0);
1439 }
1440
1441 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1442 "dmultu r<RS>, r<RT>"
1443 *mipsIII:
1444 *mipsIV:
1445 *mipsV:
1446 *mips64:
1447 *vr4100:
1448 {
1449   check_u64 (SD_, instruction_0);
1450   do_dmultu (SD_, RS, RT, 0);
1451 }
1452
1453 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1454 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1455 "dmultu r<RS>, r<RT>"
1456 *vr5000:
1457 {
1458   check_u64 (SD_, instruction_0);
1459   do_dmultu (SD_, RS, RT, RD);
1460 }
1461
1462 :function:::void:do_dsll:int rt, int rd, int shift
1463 {
1464   TRACE_ALU_INPUT2 (GPR[rt], shift);
1465   GPR[rd] = GPR[rt] << shift;
1466   TRACE_ALU_RESULT (GPR[rd]);
1467 }
1468
1469 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1470 "dsll r<RD>, r<RT>, <SHIFT>"
1471 *mipsIII:
1472 *mipsIV:
1473 *mipsV:
1474 *mips64:
1475 *vr4100:
1476 *vr5000:
1477 {
1478   check_u64 (SD_, instruction_0);
1479   do_dsll (SD_, RT, RD, SHIFT);
1480 }
1481
1482
1483 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1484 "dsll32 r<RD>, r<RT>, <SHIFT>"
1485 *mipsIII:
1486 *mipsIV:
1487 *mipsV:
1488 *mips64:
1489 *vr4100:
1490 *vr5000:
1491 {
1492   int s = 32 + SHIFT;
1493   check_u64 (SD_, instruction_0);
1494   TRACE_ALU_INPUT2 (GPR[RT], s);
1495   GPR[RD] = GPR[RT] << s;
1496   TRACE_ALU_RESULT (GPR[RD]);
1497 }
1498
1499 :function:::void:do_dsllv:int rs, int rt, int rd
1500 {
1501   int s = MASKED64 (GPR[rs], 5, 0);
1502   TRACE_ALU_INPUT2 (GPR[rt], s);
1503   GPR[rd] = GPR[rt] << s;
1504   TRACE_ALU_RESULT (GPR[rd]);
1505 }
1506
1507 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1508 "dsllv r<RD>, r<RT>, r<RS>"
1509 *mipsIII:
1510 *mipsIV:
1511 *mipsV:
1512 *mips64:
1513 *vr4100:
1514 *vr5000:
1515 {
1516   check_u64 (SD_, instruction_0);
1517   do_dsllv (SD_, RS, RT, RD);
1518 }
1519
1520 :function:::void:do_dsra:int rt, int rd, int shift
1521 {
1522   TRACE_ALU_INPUT2 (GPR[rt], shift);
1523   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1524   TRACE_ALU_RESULT (GPR[rd]);
1525 }
1526
1527
1528 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1529 "dsra r<RD>, r<RT>, <SHIFT>"
1530 *mipsIII:
1531 *mipsIV:
1532 *mipsV:
1533 *mips64:
1534 *vr4100:
1535 *vr5000:
1536 {
1537   check_u64 (SD_, instruction_0);
1538   do_dsra (SD_, RT, RD, SHIFT);
1539 }
1540
1541
1542 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1543 "dsra32 r<RD>, r<RT>, <SHIFT>"
1544 *mipsIII:
1545 *mipsIV:
1546 *mipsV:
1547 *mips64:
1548 *vr4100:
1549 *vr5000:
1550 {
1551   int s = 32 + SHIFT;
1552   check_u64 (SD_, instruction_0);
1553   TRACE_ALU_INPUT2 (GPR[RT], s);
1554   GPR[RD] = ((signed64) GPR[RT]) >> s;
1555   TRACE_ALU_RESULT (GPR[RD]);
1556 }
1557
1558
1559 :function:::void:do_dsrav:int rs, int rt, int rd
1560 {
1561   int s = MASKED64 (GPR[rs], 5, 0);
1562   TRACE_ALU_INPUT2 (GPR[rt], s);
1563   GPR[rd] = ((signed64) GPR[rt]) >> s;
1564   TRACE_ALU_RESULT (GPR[rd]);
1565 }
1566
1567 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1568 "dsrav r<RD>, r<RT>, r<RS>"
1569 *mipsIII:
1570 *mipsIV:
1571 *mipsV:
1572 *mips64:
1573 *vr4100:
1574 *vr5000:
1575 {
1576   check_u64 (SD_, instruction_0);
1577   do_dsrav (SD_, RS, RT, RD);
1578 }
1579
1580 :function:::void:do_dsrl:int rt, int rd, int shift
1581 {
1582   TRACE_ALU_INPUT2 (GPR[rt], shift);
1583   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1584   TRACE_ALU_RESULT (GPR[rd]);
1585 }
1586
1587
1588 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1589 "dsrl r<RD>, r<RT>, <SHIFT>"
1590 *mipsIII:
1591 *mipsIV:
1592 *mipsV:
1593 *mips64:
1594 *vr4100:
1595 *vr5000:
1596 {
1597   check_u64 (SD_, instruction_0);
1598   do_dsrl (SD_, RT, RD, SHIFT);
1599 }
1600
1601
1602 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1603 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1604 *mipsIII:
1605 *mipsIV:
1606 *mipsV:
1607 *mips64:
1608 *vr4100:
1609 *vr5000:
1610 {
1611   int s = 32 + SHIFT;
1612   check_u64 (SD_, instruction_0);
1613   TRACE_ALU_INPUT2 (GPR[RT], s);
1614   GPR[RD] = (unsigned64) GPR[RT] >> s;
1615   TRACE_ALU_RESULT (GPR[RD]);
1616 }
1617
1618
1619 :function:::void:do_dsrlv:int rs, int rt, int rd
1620 {
1621   int s = MASKED64 (GPR[rs], 5, 0);
1622   TRACE_ALU_INPUT2 (GPR[rt], s);
1623   GPR[rd] = (unsigned64) GPR[rt] >> s;
1624   TRACE_ALU_RESULT (GPR[rd]);
1625 }
1626
1627
1628
1629 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1630 "dsrlv r<RD>, r<RT>, r<RS>"
1631 *mipsIII:
1632 *mipsIV:
1633 *mipsV:
1634 *mips64:
1635 *vr4100:
1636 *vr5000:
1637 {
1638   check_u64 (SD_, instruction_0);
1639   do_dsrlv (SD_, RS, RT, RD);
1640 }
1641
1642
1643 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1644 "dsub r<RD>, r<RS>, r<RT>"
1645 *mipsIII:
1646 *mipsIV:
1647 *mipsV:
1648 *mips64:
1649 *vr4100:
1650 *vr5000:
1651 {
1652   check_u64 (SD_, instruction_0);
1653   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1654   {
1655     ALU64_BEGIN (GPR[RS]);
1656     ALU64_SUB (GPR[RT]);
1657     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1658   }
1659   TRACE_ALU_RESULT (GPR[RD]);
1660 }
1661
1662
1663 :function:::void:do_dsubu:int rs, int rt, int rd
1664 {
1665   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1666   GPR[rd] = GPR[rs] - GPR[rt];
1667   TRACE_ALU_RESULT (GPR[rd]);
1668 }
1669
1670 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1671 "dsubu r<RD>, r<RS>, r<RT>"
1672 *mipsIII:
1673 *mipsIV:
1674 *mipsV:
1675 *mips64:
1676 *vr4100:
1677 *vr5000:
1678 {
1679   check_u64 (SD_, instruction_0);
1680   do_dsubu (SD_, RS, RT, RD);
1681 }
1682
1683
1684 000010,26.INSTR_INDEX:NORMAL:32::J
1685 "j <INSTR_INDEX>"
1686 *mipsI:
1687 *mipsII:
1688 *mipsIII:
1689 *mipsIV:
1690 *mipsV:
1691 *mips32:
1692 *mips64:
1693 *vr4100:
1694 *vr5000:
1695 *r3900:
1696 {
1697   /* NOTE: The region used is that of the delay slot NIA and NOT the
1698      current instruction */
1699   address_word region = (NIA & MASK (63, 28));
1700   DELAY_SLOT (region | (INSTR_INDEX << 2));
1701 }
1702
1703
1704 000011,26.INSTR_INDEX:NORMAL:32::JAL
1705 "jal <INSTR_INDEX>"
1706 *mipsI:
1707 *mipsII:
1708 *mipsIII:
1709 *mipsIV:
1710 *mipsV:
1711 *mips32:
1712 *mips64:
1713 *vr4100:
1714 *vr5000:
1715 *r3900:
1716 {
1717   /* NOTE: The region used is that of the delay slot and NOT the
1718      current instruction */
1719   address_word region = (NIA & MASK (63, 28));
1720   GPR[31] = CIA + 8;
1721   DELAY_SLOT (region | (INSTR_INDEX << 2));
1722 }
1723
1724 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1725 "jalr r<RS>":RD == 31
1726 "jalr r<RD>, r<RS>"
1727 *mipsI:
1728 *mipsII:
1729 *mipsIII:
1730 *mipsIV:
1731 *mipsV:
1732 *mips32:
1733 *mips64:
1734 *vr4100:
1735 *vr5000:
1736 *r3900:
1737 {
1738   address_word temp = GPR[RS];
1739   GPR[RD] = CIA + 8;
1740   DELAY_SLOT (temp);
1741 }
1742
1743
1744 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1745 "jr r<RS>"
1746 *mipsI:
1747 *mipsII:
1748 *mipsIII:
1749 *mipsIV:
1750 *mipsV:
1751 *mips32:
1752 *mips64:
1753 *vr4100:
1754 *vr5000:
1755 *r3900:
1756 {
1757   DELAY_SLOT (GPR[RS]);
1758 }
1759
1760
1761 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1762 {
1763   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1764   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1765   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1766   unsigned int byte;
1767   address_word paddr;
1768   int uncached;
1769   unsigned64 memval;
1770   address_word vaddr;
1771
1772   vaddr = loadstore_ea (SD_, base, offset);
1773   if ((vaddr & access) != 0)
1774     {
1775       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1776     }
1777   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1778   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1779   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1780   byte = ((vaddr & mask) ^ bigendiancpu);
1781   return (memval >> (8 * byte));
1782 }
1783
1784 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1785 {
1786   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1787   address_word reverseendian = (ReverseEndian ? -1 : 0);
1788   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1789   unsigned int byte;
1790   unsigned int word;
1791   address_word paddr;
1792   int uncached;
1793   unsigned64 memval;
1794   address_word vaddr;
1795   int nr_lhs_bits;
1796   int nr_rhs_bits;
1797   unsigned_word lhs_mask;
1798   unsigned_word temp;
1799
1800   vaddr = loadstore_ea (SD_, base, offset);
1801   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1802   paddr = (paddr ^ (reverseendian & mask));
1803   if (BigEndianMem == 0)
1804     paddr = paddr & ~access;
1805
1806   /* compute where within the word/mem we are */
1807   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1808   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1809   nr_lhs_bits = 8 * byte + 8;
1810   nr_rhs_bits = 8 * access - 8 * byte;
1811   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1812
1813   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1814            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1815            (long) ((unsigned64) paddr >> 32), (long) paddr,
1816            word, byte, nr_lhs_bits, nr_rhs_bits); */
1817
1818   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1819   if (word == 0)
1820     {
1821       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1822       temp = (memval << nr_rhs_bits);
1823     }
1824   else
1825     {
1826       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1827       temp = (memval >> nr_lhs_bits);
1828     }
1829   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1830   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1831
1832   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1833            (long) ((unsigned64) memval >> 32), (long) memval,
1834            (long) ((unsigned64) temp >> 32), (long) temp,
1835            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1836            (long) (rt >> 32), (long) rt); */
1837   return rt;
1838 }
1839
1840 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1841 {
1842   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1843   address_word reverseendian = (ReverseEndian ? -1 : 0);
1844   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1845   unsigned int byte;
1846   address_word paddr;
1847   int uncached;
1848   unsigned64 memval;
1849   address_word vaddr;
1850
1851   vaddr = loadstore_ea (SD_, base, offset);
1852   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1853   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1854   paddr = (paddr ^ (reverseendian & mask));
1855   if (BigEndianMem != 0)
1856     paddr = paddr & ~access;
1857   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1858   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1859   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1860   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1861      (long) paddr, byte, (long) paddr, (long) memval); */
1862   {
1863     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1864     rt &= ~screen;
1865     rt |= (memval >> (8 * byte)) & screen;
1866   }
1867   return rt;
1868 }
1869
1870
1871 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1872 "lb r<RT>, <OFFSET>(r<BASE>)"
1873 *mipsI:
1874 *mipsII:
1875 *mipsIII:
1876 *mipsIV:
1877 *mipsV:
1878 *mips32:
1879 *mips64:
1880 *vr4100:
1881 *vr5000:
1882 *r3900:
1883 {
1884   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1885 }
1886
1887
1888 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1889 "lbu r<RT>, <OFFSET>(r<BASE>)"
1890 *mipsI:
1891 *mipsII:
1892 *mipsIII:
1893 *mipsIV:
1894 *mipsV:
1895 *mips32:
1896 *mips64:
1897 *vr4100:
1898 *vr5000:
1899 *r3900:
1900 {
1901   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1902 }
1903
1904
1905 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1906 "ld r<RT>, <OFFSET>(r<BASE>)"
1907 *mipsIII:
1908 *mipsIV:
1909 *mipsV:
1910 *mips64:
1911 *vr4100:
1912 *vr5000:
1913 {
1914   check_u64 (SD_, instruction_0);
1915   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1916 }
1917
1918
1919 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1920 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1921 *mipsII:
1922 *mipsIII:
1923 *mipsIV:
1924 *mipsV:
1925 *mips32:
1926 *mips64:
1927 *vr4100:
1928 *vr5000:
1929 *r3900:
1930 {
1931   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1932 }
1933
1934
1935
1936
1937 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1938 "ldl r<RT>, <OFFSET>(r<BASE>)"
1939 *mipsIII:
1940 *mipsIV:
1941 *mipsV:
1942 *mips64:
1943 *vr4100:
1944 *vr5000:
1945 {
1946   check_u64 (SD_, instruction_0);
1947   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1948 }
1949
1950
1951 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1952 "ldr r<RT>, <OFFSET>(r<BASE>)"
1953 *mipsIII:
1954 *mipsIV:
1955 *mipsV:
1956 *mips64:
1957 *vr4100:
1958 *vr5000:
1959 {
1960   check_u64 (SD_, instruction_0);
1961   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1962 }
1963
1964
1965 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1966 "lh r<RT>, <OFFSET>(r<BASE>)"
1967 *mipsI:
1968 *mipsII:
1969 *mipsIII:
1970 *mipsIV:
1971 *mipsV:
1972 *mips32:
1973 *mips64:
1974 *vr4100:
1975 *vr5000:
1976 *r3900:
1977 {
1978   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1979 }
1980
1981
1982 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1983 "lhu r<RT>, <OFFSET>(r<BASE>)"
1984 *mipsI:
1985 *mipsII:
1986 *mipsIII:
1987 *mipsIV:
1988 *mipsV:
1989 *mips32:
1990 *mips64:
1991 *vr4100:
1992 *vr5000:
1993 *r3900:
1994 {
1995   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1996 }
1997
1998
1999 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2000 "ll r<RT>, <OFFSET>(r<BASE>)"
2001 *mipsII:
2002 *mipsIII:
2003 *mipsIV:
2004 *mipsV:
2005 *mips32:
2006 *mips64:
2007 *vr4100:
2008 *vr5000:
2009 {
2010   address_word base = GPR[BASE];
2011   address_word offset = EXTEND16 (OFFSET);
2012   {
2013     address_word vaddr = loadstore_ea (SD_, base, offset);
2014     address_word paddr;
2015     int uncached;
2016     if ((vaddr & 3) != 0)
2017       {
2018         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2019       }
2020     else
2021       {
2022         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2023           {
2024             unsigned64 memval = 0;
2025             unsigned64 memval1 = 0;
2026             unsigned64 mask = 0x7;
2027             unsigned int shift = 2;
2028             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2029             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2030             unsigned int byte;
2031             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2032             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2033             byte = ((vaddr & mask) ^ (bigend << shift));
2034             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2035             LLBIT = 1;
2036           }
2037       }
2038   }
2039 }
2040
2041
2042 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2043 "lld r<RT>, <OFFSET>(r<BASE>)"
2044 *mipsIII:
2045 *mipsIV:
2046 *mipsV:
2047 *mips64:
2048 *vr4100:
2049 *vr5000:
2050 {
2051   address_word base = GPR[BASE];
2052   address_word offset = EXTEND16 (OFFSET);
2053   check_u64 (SD_, instruction_0);
2054   {
2055     address_word vaddr = loadstore_ea (SD_, base, offset);
2056     address_word paddr;
2057     int uncached;
2058     if ((vaddr & 7) != 0)
2059       {
2060         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2061       }
2062     else
2063       {
2064         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2065           {
2066             unsigned64 memval = 0;
2067             unsigned64 memval1 = 0;
2068             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2069             GPR[RT] = memval;
2070             LLBIT = 1;
2071           }
2072       }
2073   }
2074 }
2075
2076
2077 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2078 "lui r<RT>, %#lx<IMMEDIATE>"
2079 *mipsI:
2080 *mipsII:
2081 *mipsIII:
2082 *mipsIV:
2083 *mipsV:
2084 *mips32:
2085 *mips64:
2086 *vr4100:
2087 *vr5000:
2088 *r3900:
2089 {
2090   TRACE_ALU_INPUT1 (IMMEDIATE);
2091   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2092   TRACE_ALU_RESULT (GPR[RT]);
2093 }
2094
2095
2096 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2097 "lw r<RT>, <OFFSET>(r<BASE>)"
2098 *mipsI:
2099 *mipsII:
2100 *mipsIII:
2101 *mipsIV:
2102 *mipsV:
2103 *mips32:
2104 *mips64:
2105 *vr4100:
2106 *vr5000:
2107 *r3900:
2108 {
2109   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2110 }
2111
2112
2113 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2114 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2115 *mipsI:
2116 *mipsII:
2117 *mipsIII:
2118 *mipsIV:
2119 *mipsV:
2120 *mips32:
2121 *mips64:
2122 *vr4100:
2123 *vr5000:
2124 *r3900:
2125 {
2126   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2127 }
2128
2129
2130 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2131 "lwl r<RT>, <OFFSET>(r<BASE>)"
2132 *mipsI:
2133 *mipsII:
2134 *mipsIII:
2135 *mipsIV:
2136 *mipsV:
2137 *mips32:
2138 *mips64:
2139 *vr4100:
2140 *vr5000:
2141 *r3900:
2142 {
2143   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2144 }
2145
2146
2147 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2148 "lwr r<RT>, <OFFSET>(r<BASE>)"
2149 *mipsI:
2150 *mipsII:
2151 *mipsIII:
2152 *mipsIV:
2153 *mipsV:
2154 *mips32:
2155 *mips64:
2156 *vr4100:
2157 *vr5000:
2158 *r3900:
2159 {
2160   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2161 }
2162
2163
2164 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2165 "lwu r<RT>, <OFFSET>(r<BASE>)"
2166 *mipsIII:
2167 *mipsIV:
2168 *mipsV:
2169 *mips64:
2170 *vr4100:
2171 *vr5000:
2172 {
2173   check_u64 (SD_, instruction_0);
2174   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2175 }
2176
2177
2178
2179 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2180 "madd r<RS>, r<RT>"
2181 *mips32:
2182 *mips64:
2183 {
2184   signed64 temp;
2185   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2186   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2187     Unpredictable ();
2188   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2189   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2190           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2191   LO = EXTEND32 (temp);
2192   HI = EXTEND32 (VH4_8 (temp));
2193   TRACE_ALU_RESULT2 (HI, LO);
2194 }
2195
2196
2197
2198 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2199 "maddu r<RS>, r<RT>"
2200 *mips32:
2201 *mips64:
2202 {
2203   unsigned64 temp;
2204   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2205   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2206     Unpredictable ();
2207   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2208   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2209           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2210   LO = EXTEND32 (temp);
2211   HI = EXTEND32 (VH4_8 (temp));
2212   TRACE_ALU_RESULT2 (HI, LO);
2213 }
2214
2215
2216 :function:::void:do_mfhi:int rd
2217 {
2218   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2219   TRACE_ALU_INPUT1 (HI);
2220   GPR[rd] = HI;
2221   TRACE_ALU_RESULT (GPR[rd]);
2222 }
2223
2224 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2225 "mfhi r<RD>"
2226 *mipsI:
2227 *mipsII:
2228 *mipsIII:
2229 *mipsIV:
2230 *mipsV:
2231 *mips32:
2232 *mips64:
2233 *vr4100:
2234 *vr5000:
2235 *r3900:
2236 {
2237   do_mfhi (SD_, RD);
2238 }
2239
2240
2241
2242 :function:::void:do_mflo:int rd
2243 {
2244   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2245   TRACE_ALU_INPUT1 (LO);
2246   GPR[rd] = LO;
2247   TRACE_ALU_RESULT (GPR[rd]);
2248 }
2249
2250 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2251 "mflo r<RD>"
2252 *mipsI:
2253 *mipsII:
2254 *mipsIII:
2255 *mipsIV:
2256 *mipsV:
2257 *mips32:
2258 *mips64:
2259 *vr4100:
2260 *vr5000:
2261 *r3900:
2262 {
2263   do_mflo (SD_, RD);
2264 }
2265
2266
2267
2268 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2269 "movn r<RD>, r<RS>, r<RT>"
2270 *mipsIV:
2271 *mipsV:
2272 *mips32:
2273 *mips64:
2274 *vr5000:
2275 {
2276   if (GPR[RT] != 0)
2277     GPR[RD] = GPR[RS];
2278 }
2279
2280
2281
2282 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2283 "movz r<RD>, r<RS>, r<RT>"
2284 *mipsIV:
2285 *mipsV:
2286 *mips32:
2287 *mips64:
2288 *vr5000:
2289 {
2290   if (GPR[RT] == 0)
2291     GPR[RD] = GPR[RS];
2292 }
2293
2294
2295
2296 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2297 "msub r<RS>, r<RT>"
2298 *mips32:
2299 *mips64:
2300 {
2301   signed64 temp;
2302   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2303   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2304     Unpredictable ();
2305   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2306   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2307           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2308   LO = EXTEND32 (temp);
2309   HI = EXTEND32 (VH4_8 (temp));
2310   TRACE_ALU_RESULT2 (HI, LO);
2311 }
2312
2313
2314
2315 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2316 "msubu r<RS>, r<RT>"
2317 *mips32:
2318 *mips64:
2319 {
2320   unsigned64 temp;
2321   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2322   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2323     Unpredictable ();
2324   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2325   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2326           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2327   LO = EXTEND32 (temp);
2328   HI = EXTEND32 (VH4_8 (temp));
2329   TRACE_ALU_RESULT2 (HI, LO);
2330 }
2331
2332
2333
2334 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2335 "mthi r<RS>"
2336 *mipsI:
2337 *mipsII:
2338 *mipsIII:
2339 *mipsIV:
2340 *mipsV:
2341 *mips32:
2342 *mips64:
2343 *vr4100:
2344 *vr5000:
2345 *r3900:
2346 {
2347   check_mt_hilo (SD_, HIHISTORY);
2348   HI = GPR[RS];
2349 }
2350
2351
2352
2353 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2354 "mtlo r<RS>"
2355 *mipsI:
2356 *mipsII:
2357 *mipsIII:
2358 *mipsIV:
2359 *mipsV:
2360 *mips32:
2361 *mips64:
2362 *vr4100:
2363 *vr5000:
2364 *r3900:
2365 {
2366   check_mt_hilo (SD_, LOHISTORY);
2367   LO = GPR[RS];
2368 }
2369
2370
2371
2372 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2373 "mul r<RD>, r<RS>, r<RT>"
2374 *mips32:
2375 *mips64:
2376 {
2377   signed64 prod;
2378   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2379     Unpredictable ();
2380   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2381   prod = (((signed64)(signed32) GPR[RS])
2382           * ((signed64)(signed32) GPR[RT]));
2383   GPR[RD] = EXTEND32 (VL4_8 (prod));
2384   TRACE_ALU_RESULT (GPR[RD]);
2385 }
2386
2387
2388
2389 :function:::void:do_mult:int rs, int rt, int rd
2390 {
2391   signed64 prod;
2392   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2393   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2394     Unpredictable ();
2395   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2396   prod = (((signed64)(signed32) GPR[rs])
2397           * ((signed64)(signed32) GPR[rt]));
2398   LO = EXTEND32 (VL4_8 (prod));
2399   HI = EXTEND32 (VH4_8 (prod));
2400   if (rd != 0)
2401     GPR[rd] = LO;
2402   TRACE_ALU_RESULT2 (HI, LO);
2403 }
2404
2405 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2406 "mult r<RS>, r<RT>"
2407 *mipsI:
2408 *mipsII:
2409 *mipsIII:
2410 *mipsIV:
2411 *mipsV:
2412 *mips32:
2413 *mips64:
2414 *vr4100:
2415 {
2416   do_mult (SD_, RS, RT, 0);
2417 }
2418
2419
2420 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2421 "mult r<RS>, r<RT>":RD == 0
2422 "mult r<RD>, r<RS>, r<RT>"
2423 *vr5000:
2424 *r3900:
2425 {
2426   do_mult (SD_, RS, RT, RD);
2427 }
2428
2429
2430 :function:::void:do_multu:int rs, int rt, int rd
2431 {
2432   unsigned64 prod;
2433   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2434   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2435     Unpredictable ();
2436   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2437   prod = (((unsigned64)(unsigned32) GPR[rs])
2438           * ((unsigned64)(unsigned32) GPR[rt]));
2439   LO = EXTEND32 (VL4_8 (prod));
2440   HI = EXTEND32 (VH4_8 (prod));
2441   if (rd != 0)
2442     GPR[rd] = LO;
2443   TRACE_ALU_RESULT2 (HI, LO);
2444 }
2445
2446 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2447 "multu r<RS>, r<RT>"
2448 *mipsI:
2449 *mipsII:
2450 *mipsIII:
2451 *mipsIV:
2452 *mipsV:
2453 *mips32:
2454 *mips64:
2455 *vr4100:
2456 {
2457   do_multu (SD_, RS, RT, 0);
2458 }
2459
2460 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2461 "multu r<RS>, r<RT>":RD == 0
2462 "multu r<RD>, r<RS>, r<RT>"
2463 *vr5000:
2464 *r3900:
2465 {
2466   do_multu (SD_, RS, RT, RD);
2467 }
2468
2469
2470 :function:::void:do_nor:int rs, int rt, int rd
2471 {
2472   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2473   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2474   TRACE_ALU_RESULT (GPR[rd]);
2475 }
2476
2477 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2478 "nor r<RD>, r<RS>, r<RT>"
2479 *mipsI:
2480 *mipsII:
2481 *mipsIII:
2482 *mipsIV:
2483 *mipsV:
2484 *mips32:
2485 *mips64:
2486 *vr4100:
2487 *vr5000:
2488 *r3900:
2489 {
2490   do_nor (SD_, RS, RT, RD);
2491 }
2492
2493
2494 :function:::void:do_or:int rs, int rt, int rd
2495 {
2496   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2497   GPR[rd] = (GPR[rs] | GPR[rt]);
2498   TRACE_ALU_RESULT (GPR[rd]);
2499 }
2500
2501 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2502 "or r<RD>, r<RS>, r<RT>"
2503 *mipsI:
2504 *mipsII:
2505 *mipsIII:
2506 *mipsIV:
2507 *mipsV:
2508 *mips32:
2509 *mips64:
2510 *vr4100:
2511 *vr5000:
2512 *r3900:
2513 {
2514   do_or (SD_, RS, RT, RD);
2515 }
2516
2517
2518
2519 :function:::void:do_ori:int rs, int rt, unsigned immediate
2520 {
2521   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2522   GPR[rt] = (GPR[rs] | immediate);
2523   TRACE_ALU_RESULT (GPR[rt]);
2524 }
2525
2526 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2527 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2528 *mipsI:
2529 *mipsII:
2530 *mipsIII:
2531 *mipsIV:
2532 *mipsV:
2533 *mips32:
2534 *mips64:
2535 *vr4100:
2536 *vr5000:
2537 *r3900:
2538 {
2539   do_ori (SD_, RS, RT, IMMEDIATE);
2540 }
2541
2542
2543 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2544 "pref <HINT>, <OFFSET>(r<BASE>)"
2545 *mipsIV:
2546 *mipsV:
2547 *mips32:
2548 *mips64:
2549 *vr5000:
2550 {
2551   address_word base = GPR[BASE];
2552   address_word offset = EXTEND16 (OFFSET);
2553   {
2554     address_word vaddr = loadstore_ea (SD_, base, offset);
2555     address_word paddr;
2556     int uncached;
2557     {
2558       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2559         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2560     }
2561   }
2562 }
2563
2564
2565 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2566 {
2567   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2568   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2569   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2570   unsigned int byte;
2571   address_word paddr;
2572   int uncached;
2573   unsigned64 memval;
2574   address_word vaddr;
2575
2576   vaddr = loadstore_ea (SD_, base, offset);
2577   if ((vaddr & access) != 0)
2578     {
2579       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2580     }
2581   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2582   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2583   byte = ((vaddr & mask) ^ bigendiancpu);
2584   memval = (word << (8 * byte));
2585   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2586 }
2587
2588 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2589 {
2590   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2591   address_word reverseendian = (ReverseEndian ? -1 : 0);
2592   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2593   unsigned int byte;
2594   unsigned int word;
2595   address_word paddr;
2596   int uncached;
2597   unsigned64 memval;
2598   address_word vaddr;
2599   int nr_lhs_bits;
2600   int nr_rhs_bits;
2601
2602   vaddr = loadstore_ea (SD_, base, offset);
2603   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2604   paddr = (paddr ^ (reverseendian & mask));
2605   if (BigEndianMem == 0)
2606     paddr = paddr & ~access;
2607
2608   /* compute where within the word/mem we are */
2609   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2610   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2611   nr_lhs_bits = 8 * byte + 8;
2612   nr_rhs_bits = 8 * access - 8 * byte;
2613   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2614   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2615            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2616            (long) ((unsigned64) paddr >> 32), (long) paddr,
2617            word, byte, nr_lhs_bits, nr_rhs_bits); */
2618
2619   if (word == 0)
2620     {
2621       memval = (rt >> nr_rhs_bits);
2622     }
2623   else
2624     {
2625       memval = (rt << nr_lhs_bits);
2626     }
2627   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2628            (long) ((unsigned64) rt >> 32), (long) rt,
2629            (long) ((unsigned64) memval >> 32), (long) memval); */
2630   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2631 }
2632
2633 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2634 {
2635   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2636   address_word reverseendian = (ReverseEndian ? -1 : 0);
2637   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2638   unsigned int byte;
2639   address_word paddr;
2640   int uncached;
2641   unsigned64 memval;
2642   address_word vaddr;
2643
2644   vaddr = loadstore_ea (SD_, base, offset);
2645   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2646   paddr = (paddr ^ (reverseendian & mask));
2647   if (BigEndianMem != 0)
2648     paddr &= ~access;
2649   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2650   memval = (rt << (byte * 8));
2651   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2652 }
2653
2654
2655 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2656 "sb r<RT>, <OFFSET>(r<BASE>)"
2657 *mipsI:
2658 *mipsII:
2659 *mipsIII:
2660 *mipsIV:
2661 *mipsV:
2662 *mips32:
2663 *mips64:
2664 *vr4100:
2665 *vr5000:
2666 *r3900:
2667 {
2668   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2669 }
2670
2671
2672 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2673 "sc r<RT>, <OFFSET>(r<BASE>)"
2674 *mipsII:
2675 *mipsIII:
2676 *mipsIV:
2677 *mipsV:
2678 *mips32:
2679 *mips64:
2680 *vr4100:
2681 *vr5000:
2682 {
2683   unsigned32 instruction = instruction_0;
2684   address_word base = GPR[BASE];
2685   address_word offset = EXTEND16 (OFFSET);
2686   {
2687     address_word vaddr = loadstore_ea (SD_, base, offset);
2688     address_word paddr;
2689     int uncached;
2690     if ((vaddr & 3) != 0)
2691       {
2692         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2693       }
2694     else
2695       {
2696         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2697           {
2698             unsigned64 memval = 0;
2699             unsigned64 memval1 = 0;
2700             unsigned64 mask = 0x7;
2701             unsigned int byte;
2702             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2703             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2704             memval = ((unsigned64) GPR[RT] << (8 * byte));
2705             if (LLBIT)
2706               {
2707                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2708               }
2709             GPR[RT] = LLBIT;
2710           }
2711       }
2712   }
2713 }
2714
2715
2716 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2717 "scd r<RT>, <OFFSET>(r<BASE>)"
2718 *mipsIII:
2719 *mipsIV:
2720 *mipsV:
2721 *mips64:
2722 *vr4100:
2723 *vr5000:
2724 {
2725   address_word base = GPR[BASE];
2726   address_word offset = EXTEND16 (OFFSET);
2727   check_u64 (SD_, instruction_0);
2728   {
2729     address_word vaddr = loadstore_ea (SD_, base, offset);
2730     address_word paddr;
2731     int uncached;
2732     if ((vaddr & 7) != 0)
2733       {
2734         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2735       }
2736     else
2737       {
2738         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2739           {
2740             unsigned64 memval = 0;
2741             unsigned64 memval1 = 0;
2742             memval = GPR[RT];
2743             if (LLBIT)
2744               {
2745                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2746               }
2747             GPR[RT] = LLBIT;
2748           }
2749       }
2750   }
2751 }
2752
2753
2754 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2755 "sd r<RT>, <OFFSET>(r<BASE>)"
2756 *mipsIII:
2757 *mipsIV:
2758 *mipsV:
2759 *mips64:
2760 *vr4100:
2761 *vr5000:
2762 {
2763   check_u64 (SD_, instruction_0);
2764   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2765 }
2766
2767
2768 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2769 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2770 *mipsII:
2771 *mipsIII:
2772 *mipsIV:
2773 *mipsV:
2774 *mips32:
2775 *mips64:
2776 *vr4100:
2777 *vr5000:
2778 {
2779   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2780 }
2781
2782
2783 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2784 "sdl r<RT>, <OFFSET>(r<BASE>)"
2785 *mipsIII:
2786 *mipsIV:
2787 *mipsV:
2788 *mips64:
2789 *vr4100:
2790 *vr5000:
2791 {
2792   check_u64 (SD_, instruction_0);
2793   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2794 }
2795
2796
2797 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2798 "sdr r<RT>, <OFFSET>(r<BASE>)"
2799 *mipsIII:
2800 *mipsIV:
2801 *mipsV:
2802 *mips64:
2803 *vr4100:
2804 *vr5000:
2805 {
2806   check_u64 (SD_, instruction_0);
2807   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2808 }
2809
2810
2811 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2812 "sh r<RT>, <OFFSET>(r<BASE>)"
2813 *mipsI:
2814 *mipsII:
2815 *mipsIII:
2816 *mipsIV:
2817 *mipsV:
2818 *mips32:
2819 *mips64:
2820 *vr4100:
2821 *vr5000:
2822 *r3900:
2823 {
2824   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2825 }
2826
2827
2828 :function:::void:do_sll:int rt, int rd, int shift
2829 {
2830   unsigned32 temp = (GPR[rt] << shift);
2831   TRACE_ALU_INPUT2 (GPR[rt], shift);
2832   GPR[rd] = EXTEND32 (temp);
2833   TRACE_ALU_RESULT (GPR[rd]);
2834 }
2835
2836 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2837 "nop":RD == 0 && RT == 0 && SHIFT == 0
2838 "sll r<RD>, r<RT>, <SHIFT>"
2839 *mipsI:
2840 *mipsII:
2841 *mipsIII:
2842 *mipsIV:
2843 *mipsV:
2844 *vr4100:
2845 *vr5000:
2846 *r3900:
2847 {
2848   /* Skip shift for NOP, so that there won't be lots of extraneous
2849      trace output.  */
2850   if (RD != 0 || RT != 0 || SHIFT != 0)
2851     do_sll (SD_, RT, RD, SHIFT);
2852 }
2853
2854 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2855 "nop":RD == 0 && RT == 0 && SHIFT == 0
2856 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2857 "sll r<RD>, r<RT>, <SHIFT>"
2858 *mips32:
2859 *mips64:
2860 {
2861   /* Skip shift for NOP and SSNOP, so that there won't be lots of
2862      extraneous trace output.  */
2863   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2864     do_sll (SD_, RT, RD, SHIFT);
2865 }
2866
2867
2868 :function:::void:do_sllv:int rs, int rt, int rd
2869 {
2870   int s = MASKED (GPR[rs], 4, 0);
2871   unsigned32 temp = (GPR[rt] << s);
2872   TRACE_ALU_INPUT2 (GPR[rt], s);
2873   GPR[rd] = EXTEND32 (temp);
2874   TRACE_ALU_RESULT (GPR[rd]);
2875 }
2876
2877 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2878 "sllv r<RD>, r<RT>, r<RS>"
2879 *mipsI:
2880 *mipsII:
2881 *mipsIII:
2882 *mipsIV:
2883 *mipsV:
2884 *mips32:
2885 *mips64:
2886 *vr4100:
2887 *vr5000:
2888 *r3900:
2889 {
2890   do_sllv (SD_, RS, RT, RD);
2891 }
2892
2893
2894 :function:::void:do_slt:int rs, int rt, int rd
2895 {
2896   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2897   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2898   TRACE_ALU_RESULT (GPR[rd]);
2899 }
2900
2901 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2902 "slt r<RD>, r<RS>, r<RT>"
2903 *mipsI:
2904 *mipsII:
2905 *mipsIII:
2906 *mipsIV:
2907 *mipsV:
2908 *mips32:
2909 *mips64:
2910 *vr4100:
2911 *vr5000:
2912 *r3900:
2913 {
2914   do_slt (SD_, RS, RT, RD);
2915 }
2916
2917
2918 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2919 {
2920   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2921   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2922   TRACE_ALU_RESULT (GPR[rt]);
2923 }
2924
2925 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2926 "slti r<RT>, r<RS>, <IMMEDIATE>"
2927 *mipsI:
2928 *mipsII:
2929 *mipsIII:
2930 *mipsIV:
2931 *mipsV:
2932 *mips32:
2933 *mips64:
2934 *vr4100:
2935 *vr5000:
2936 *r3900:
2937 {
2938   do_slti (SD_, RS, RT, IMMEDIATE);
2939 }
2940
2941
2942 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2943 {
2944   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2945   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2946   TRACE_ALU_RESULT (GPR[rt]);
2947 }
2948
2949 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2950 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2951 *mipsI:
2952 *mipsII:
2953 *mipsIII:
2954 *mipsIV:
2955 *mipsV:
2956 *mips32:
2957 *mips64:
2958 *vr4100:
2959 *vr5000:
2960 *r3900:
2961 {
2962   do_sltiu (SD_, RS, RT, IMMEDIATE);
2963 }
2964
2965
2966
2967 :function:::void:do_sltu:int rs, int rt, int rd
2968 {
2969   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2970   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2971   TRACE_ALU_RESULT (GPR[rd]);
2972 }
2973
2974 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2975 "sltu r<RD>, r<RS>, r<RT>"
2976 *mipsI:
2977 *mipsII:
2978 *mipsIII:
2979 *mipsIV:
2980 *mipsV:
2981 *mips32:
2982 *mips64:
2983 *vr4100:
2984 *vr5000:
2985 *r3900:
2986 {
2987   do_sltu (SD_, RS, RT, RD);
2988 }
2989
2990
2991 :function:::void:do_sra:int rt, int rd, int shift
2992 {
2993   signed32 temp = (signed32) GPR[rt] >> shift;
2994   if (NotWordValue (GPR[rt]))
2995     Unpredictable ();
2996   TRACE_ALU_INPUT2 (GPR[rt], shift);
2997   GPR[rd] = EXTEND32 (temp);
2998   TRACE_ALU_RESULT (GPR[rd]);
2999 }
3000
3001 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3002 "sra r<RD>, r<RT>, <SHIFT>"
3003 *mipsI:
3004 *mipsII:
3005 *mipsIII:
3006 *mipsIV:
3007 *mipsV:
3008 *mips32:
3009 *mips64:
3010 *vr4100:
3011 *vr5000:
3012 *r3900:
3013 {
3014   do_sra (SD_, RT, RD, SHIFT);
3015 }
3016
3017
3018
3019 :function:::void:do_srav:int rs, int rt, int rd
3020 {
3021   int s = MASKED (GPR[rs], 4, 0);
3022   signed32 temp = (signed32) GPR[rt] >> s;
3023   if (NotWordValue (GPR[rt]))
3024     Unpredictable ();
3025   TRACE_ALU_INPUT2 (GPR[rt], s);
3026   GPR[rd] = EXTEND32 (temp);
3027   TRACE_ALU_RESULT (GPR[rd]);
3028 }
3029
3030 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3031 "srav r<RD>, r<RT>, r<RS>"
3032 *mipsI:
3033 *mipsII:
3034 *mipsIII:
3035 *mipsIV:
3036 *mipsV:
3037 *mips32:
3038 *mips64:
3039 *vr4100:
3040 *vr5000:
3041 *r3900:
3042 {
3043   do_srav (SD_, RS, RT, RD);
3044 }
3045
3046
3047
3048 :function:::void:do_srl:int rt, int rd, int shift
3049 {
3050   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3051   if (NotWordValue (GPR[rt]))
3052     Unpredictable ();
3053   TRACE_ALU_INPUT2 (GPR[rt], shift);
3054   GPR[rd] = EXTEND32 (temp);
3055   TRACE_ALU_RESULT (GPR[rd]);
3056 }
3057
3058 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3059 "srl r<RD>, r<RT>, <SHIFT>"
3060 *mipsI:
3061 *mipsII:
3062 *mipsIII:
3063 *mipsIV:
3064 *mipsV:
3065 *mips32:
3066 *mips64:
3067 *vr4100:
3068 *vr5000:
3069 *r3900:
3070 {
3071   do_srl (SD_, RT, RD, SHIFT);
3072 }
3073
3074
3075 :function:::void:do_srlv:int rs, int rt, int rd
3076 {
3077   int s = MASKED (GPR[rs], 4, 0);
3078   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3079   if (NotWordValue (GPR[rt]))
3080     Unpredictable ();
3081   TRACE_ALU_INPUT2 (GPR[rt], s);
3082   GPR[rd] = EXTEND32 (temp);
3083   TRACE_ALU_RESULT (GPR[rd]);
3084 }
3085
3086 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3087 "srlv r<RD>, r<RT>, r<RS>"
3088 *mipsI:
3089 *mipsII:
3090 *mipsIII:
3091 *mipsIV:
3092 *mipsV:
3093 *mips32:
3094 *mips64:
3095 *vr4100:
3096 *vr5000:
3097 *r3900:
3098 {
3099   do_srlv (SD_, RS, RT, RD);
3100 }
3101
3102
3103 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3104 "sub r<RD>, r<RS>, r<RT>"
3105 *mipsI:
3106 *mipsII:
3107 *mipsIII:
3108 *mipsIV:
3109 *mipsV:
3110 *mips32:
3111 *mips64:
3112 *vr4100:
3113 *vr5000:
3114 *r3900:
3115 {
3116   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3117     Unpredictable ();
3118   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3119   {
3120     ALU32_BEGIN (GPR[RS]);
3121     ALU32_SUB (GPR[RT]);
3122     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3123   }
3124   TRACE_ALU_RESULT (GPR[RD]);
3125 }
3126
3127
3128 :function:::void:do_subu:int rs, int rt, int rd
3129 {
3130   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3131     Unpredictable ();
3132   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3133   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3134   TRACE_ALU_RESULT (GPR[rd]);
3135 }
3136
3137 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3138 "subu r<RD>, r<RS>, r<RT>"
3139 *mipsI:
3140 *mipsII:
3141 *mipsIII:
3142 *mipsIV:
3143 *mipsV:
3144 *mips32:
3145 *mips64:
3146 *vr4100:
3147 *vr5000:
3148 *r3900:
3149 {
3150   do_subu (SD_, RS, RT, RD);
3151 }
3152
3153
3154 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3155 "sw r<RT>, <OFFSET>(r<BASE>)"
3156 *mipsI:
3157 *mipsII:
3158 *mipsIII:
3159 *mipsIV:
3160 *mipsV:
3161 *mips32:
3162 *mips64:
3163 *vr4100:
3164 *r3900:
3165 *vr5000:
3166 {
3167   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3168 }
3169
3170
3171 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3172 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3173 *mipsI:
3174 *mipsII:
3175 *mipsIII:
3176 *mipsIV:
3177 *mipsV:
3178 *mips32:
3179 *mips64:
3180 *vr4100:
3181 *vr5000:
3182 *r3900:
3183 {
3184   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3185 }
3186
3187
3188 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3189 "swl r<RT>, <OFFSET>(r<BASE>)"
3190 *mipsI:
3191 *mipsII:
3192 *mipsIII:
3193 *mipsIV:
3194 *mipsV:
3195 *mips32:
3196 *mips64:
3197 *vr4100:
3198 *vr5000:
3199 *r3900:
3200 {
3201   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3202 }
3203
3204
3205 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3206 "swr r<RT>, <OFFSET>(r<BASE>)"
3207 *mipsI:
3208 *mipsII:
3209 *mipsIII:
3210 *mipsIV:
3211 *mipsV:
3212 *mips32:
3213 *mips64:
3214 *vr4100:
3215 *vr5000:
3216 *r3900:
3217 {
3218   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3219 }
3220
3221
3222 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3223 "sync":STYPE == 0
3224 "sync <STYPE>"
3225 *mipsII:
3226 *mipsIII:
3227 *mipsIV:
3228 *mipsV:
3229 *mips32:
3230 *mips64:
3231 *vr4100:
3232 *vr5000:
3233 *r3900:
3234 {
3235   SyncOperation (STYPE);
3236 }
3237
3238
3239 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3240 "syscall %#lx<CODE>"
3241 *mipsI:
3242 *mipsII:
3243 *mipsIII:
3244 *mipsIV:
3245 *mipsV:
3246 *mips32:
3247 *mips64:
3248 *vr4100:
3249 *vr5000:
3250 *r3900:
3251 {
3252   SignalException (SystemCall, instruction_0);
3253 }
3254
3255
3256 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3257 "teq r<RS>, r<RT>"
3258 *mipsII:
3259 *mipsIII:
3260 *mipsIV:
3261 *mipsV:
3262 *mips32:
3263 *mips64:
3264 *vr4100:
3265 *vr5000:
3266 {
3267   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3268     SignalException (Trap, instruction_0);
3269 }
3270
3271
3272 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3273 "teqi r<RS>, <IMMEDIATE>"
3274 *mipsII:
3275 *mipsIII:
3276 *mipsIV:
3277 *mipsV:
3278 *mips32:
3279 *mips64:
3280 *vr4100:
3281 *vr5000:
3282 {
3283   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3284     SignalException (Trap, instruction_0);
3285 }
3286
3287
3288 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3289 "tge r<RS>, r<RT>"
3290 *mipsII:
3291 *mipsIII:
3292 *mipsIV:
3293 *mipsV:
3294 *mips32:
3295 *mips64:
3296 *vr4100:
3297 *vr5000:
3298 {
3299   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3300     SignalException (Trap, instruction_0);
3301 }
3302
3303
3304 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3305 "tgei r<RS>, <IMMEDIATE>"
3306 *mipsII:
3307 *mipsIII:
3308 *mipsIV:
3309 *mipsV:
3310 *mips32:
3311 *mips64:
3312 *vr4100:
3313 *vr5000:
3314 {
3315   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3316     SignalException (Trap, instruction_0);
3317 }
3318
3319
3320 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3321 "tgeiu r<RS>, <IMMEDIATE>"
3322 *mipsII:
3323 *mipsIII:
3324 *mipsIV:
3325 *mipsV:
3326 *mips32:
3327 *mips64:
3328 *vr4100:
3329 *vr5000:
3330 {
3331   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3332     SignalException (Trap, instruction_0);
3333 }
3334
3335
3336 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3337 "tgeu r<RS>, r<RT>"
3338 *mipsII:
3339 *mipsIII:
3340 *mipsIV:
3341 *mipsV:
3342 *mips32:
3343 *mips64:
3344 *vr4100:
3345 *vr5000:
3346 {
3347   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3348     SignalException (Trap, instruction_0);
3349 }
3350
3351
3352 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3353 "tlt r<RS>, r<RT>"
3354 *mipsII:
3355 *mipsIII:
3356 *mipsIV:
3357 *mipsV:
3358 *mips32:
3359 *mips64:
3360 *vr4100:
3361 *vr5000:
3362 {
3363   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3364     SignalException (Trap, instruction_0);
3365 }
3366
3367
3368 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3369 "tlti r<RS>, <IMMEDIATE>"
3370 *mipsII:
3371 *mipsIII:
3372 *mipsIV:
3373 *mipsV:
3374 *mips32:
3375 *mips64:
3376 *vr4100:
3377 *vr5000:
3378 {
3379   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3380     SignalException (Trap, instruction_0);
3381 }
3382
3383
3384 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3385 "tltiu r<RS>, <IMMEDIATE>"
3386 *mipsII:
3387 *mipsIII:
3388 *mipsIV:
3389 *mipsV:
3390 *mips32:
3391 *mips64:
3392 *vr4100:
3393 *vr5000:
3394 {
3395   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3396     SignalException (Trap, instruction_0);
3397 }
3398
3399
3400 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3401 "tltu r<RS>, r<RT>"
3402 *mipsII:
3403 *mipsIII:
3404 *mipsIV:
3405 *mipsV:
3406 *mips32:
3407 *mips64:
3408 *vr4100:
3409 *vr5000:
3410 {
3411   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3412     SignalException (Trap, instruction_0);
3413 }
3414
3415
3416 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3417 "tne r<RS>, r<RT>"
3418 *mipsII:
3419 *mipsIII:
3420 *mipsIV:
3421 *mipsV:
3422 *mips32:
3423 *mips64:
3424 *vr4100:
3425 *vr5000:
3426 {
3427   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3428     SignalException (Trap, instruction_0);
3429 }
3430
3431
3432 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3433 "tne r<RS>, <IMMEDIATE>"
3434 *mipsII:
3435 *mipsIII:
3436 *mipsIV:
3437 *mipsV:
3438 *mips32:
3439 *mips64:
3440 *vr4100:
3441 *vr5000:
3442 {
3443   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3444     SignalException (Trap, instruction_0);
3445 }
3446
3447
3448 :function:::void:do_xor:int rs, int rt, int rd
3449 {
3450   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3451   GPR[rd] = GPR[rs] ^ GPR[rt];
3452   TRACE_ALU_RESULT (GPR[rd]);
3453 }
3454
3455 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3456 "xor r<RD>, r<RS>, r<RT>"
3457 *mipsI:
3458 *mipsII:
3459 *mipsIII:
3460 *mipsIV:
3461 *mipsV:
3462 *mips32:
3463 *mips64:
3464 *vr4100:
3465 *vr5000:
3466 *r3900:
3467 {
3468   do_xor (SD_, RS, RT, RD);
3469 }
3470
3471
3472 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3473 {
3474   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3475   GPR[rt] = GPR[rs] ^ immediate;
3476   TRACE_ALU_RESULT (GPR[rt]);
3477 }
3478
3479 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3480 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3481 *mipsI:
3482 *mipsII:
3483 *mipsIII:
3484 *mipsIV:
3485 *mipsV:
3486 *mips32:
3487 *mips64:
3488 *vr4100:
3489 *vr5000:
3490 *r3900:
3491 {
3492   do_xori (SD_, RS, RT, IMMEDIATE);
3493 }
3494
3495 \f
3496 //
3497 // MIPS Architecture:
3498 //
3499 //        FPU Instruction Set (COP1 & COP1X)
3500 //
3501
3502
3503 :%s::::FMT:int fmt
3504 {
3505   switch (fmt)
3506     {
3507     case fmt_single: return "s";
3508     case fmt_double: return "d";
3509     case fmt_word: return "w";
3510     case fmt_long: return "l";
3511     default: return "?";
3512     }
3513 }
3514
3515 :%s::::X:int x
3516 {
3517   switch (x)
3518     {
3519     case 0: return "f";
3520     case 1: return "t";
3521     default: return "?";
3522     }
3523 }
3524
3525 :%s::::TF:int tf
3526 {
3527   if (tf)
3528     return "t";
3529   else
3530     return "f";
3531 }
3532
3533 :%s::::ND:int nd
3534 {
3535   if (nd)
3536     return "l";
3537   else
3538     return "";
3539 }
3540
3541 :%s::::COND:int cond
3542 {
3543   switch (cond)
3544     {
3545     case 00: return "f";
3546     case 01: return "un";
3547     case 02: return "eq";
3548     case 03: return "ueq";
3549     case 04: return "olt";
3550     case 05: return "ult";
3551     case 06: return "ole";
3552     case 07: return "ule";
3553     case 010: return "sf";
3554     case 011: return "ngle";
3555     case 012: return "seq";
3556     case 013: return "ngl";
3557     case 014: return "lt";
3558     case 015: return "nge";
3559     case 016: return "le";
3560     case 017: return "ngt";
3561     default: return "?";
3562     }
3563 }
3564
3565
3566 // Helpers:
3567 //
3568 // Check that the given FPU format is usable, and signal a
3569 // ReservedInstruction exception if not.
3570 //
3571
3572 // check_fmt checks that the format is single or double.
3573 :function:::void:check_fmt:int fmt, instruction_word insn
3574 *mipsI:
3575 *mipsII:
3576 *mipsIII:
3577 *mipsIV:
3578 *mipsV:
3579 *mips32:
3580 *mips64:
3581 *vr4100:
3582 *vr5000:
3583 *r3900:
3584 {
3585   if ((fmt != fmt_single) && (fmt != fmt_double))
3586     SignalException (ReservedInstruction, insn);
3587 }
3588
3589 // check_fmt_p checks that the format is single, double, or paired single.
3590 :function:::void:check_fmt_p:int fmt, instruction_word insn
3591 *mipsI:
3592 *mipsII:
3593 *mipsIII:
3594 *mipsIV:
3595 *mips32:
3596 *vr4100:
3597 *vr5000:
3598 *r3900:
3599 {
3600   /* None of these ISAs support Paired Single, so just fall back to
3601      the single/double check.  */
3602   check_fmt (SD_, fmt, insn);
3603 }
3604
3605 :function:::void:check_fmt_p:int fmt, instruction_word insn
3606 *mipsV:
3607 *mips64:
3608 {
3609 #if 0 /* XXX FIXME: FP code doesn't yet support paired single ops.  */
3610   if ((fmt != fmt_single) && (fmt != fmt_double)
3611       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3612     SignalException (ReservedInstruction, insn);
3613 #else
3614   check_fmt (SD_, fmt, insn);
3615 #endif
3616 }
3617
3618
3619 // Helper:
3620 //
3621 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3622 // exception if not.
3623 //
3624
3625 :function:::void:check_fpu:
3626 *mipsI:
3627 *mipsII:
3628 *mipsIII:
3629 *mipsIV:
3630 *mipsV:
3631 *mips32:
3632 *mips64:
3633 *vr4100:
3634 *vr5000:
3635 *r3900:
3636 {
3637   if (! COP_Usable (1))
3638     SignalExceptionCoProcessorUnusable (1);
3639 }
3640
3641
3642 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3643 "abs.%s<FMT> f<FD>, f<FS>"
3644 *mipsI:
3645 *mipsII:
3646 *mipsIII:
3647 *mipsIV:
3648 *mipsV:
3649 *mips32:
3650 *mips64:
3651 *vr4100:
3652 *vr5000:
3653 *r3900:
3654 {
3655   int fmt = FMT;
3656   check_fpu (SD_);
3657   check_fmt_p (SD_, fmt, instruction_0);
3658   StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3659 }
3660
3661
3662
3663 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3664 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3665 *mipsI:
3666 *mipsII:
3667 *mipsIII:
3668 *mipsIV:
3669 *mipsV:
3670 *mips32:
3671 *mips64:
3672 *vr4100:
3673 *vr5000:
3674 *r3900:
3675 {
3676   int fmt = FMT;
3677   check_fpu (SD_);
3678   check_fmt_p (SD_, fmt, instruction_0);
3679   StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3680 }
3681
3682
3683
3684 // BC1F
3685 // BC1FL
3686 // BC1T
3687 // BC1TL
3688
3689 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3690 "bc1%s<TF>%s<ND> <OFFSET>"
3691 *mipsI:
3692 *mipsII:
3693 *mipsIII:
3694 {
3695   check_fpu (SD_);
3696   check_branch_bug ();
3697   TRACE_BRANCH_INPUT (PREVCOC1());
3698   if (PREVCOC1() == TF)
3699     {
3700       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3701       TRACE_BRANCH_RESULT (dest);
3702       mark_branch_bug (dest);
3703       DELAY_SLOT (dest);
3704     }
3705   else if (ND)
3706     {
3707       TRACE_BRANCH_RESULT (0);
3708       NULLIFY_NEXT_INSTRUCTION ();
3709     }
3710   else
3711     {
3712       TRACE_BRANCH_RESULT (NIA);
3713     }
3714 }
3715
3716 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3717 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3718 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3719 *mipsIV:
3720 *mipsV:
3721 *mips32:
3722 *mips64:
3723 #*vr4100:
3724 *vr5000:
3725 *r3900:
3726 {
3727   check_fpu (SD_);
3728   check_branch_bug ();
3729   if (GETFCC(CC) == TF)
3730     {
3731       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3732       mark_branch_bug (dest);
3733       DELAY_SLOT (dest);
3734     }
3735   else if (ND)
3736     {
3737       NULLIFY_NEXT_INSTRUCTION ();
3738     }
3739 }
3740
3741
3742
3743
3744
3745
3746 // C.EQ.S
3747 // C.EQ.D
3748 // ...
3749
3750 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3751 {
3752   int less;
3753   int equal;
3754   int unordered;
3755   int condition;
3756   unsigned64 ofs = ValueFPR (fs, fmt);
3757   unsigned64 oft = ValueFPR (ft, fmt);
3758   if (NaN (ofs, fmt) || NaN (oft, fmt))
3759     {
3760       if (FCSR & FP_ENABLE (IO))
3761         {
3762           FCSR |= FP_CAUSE (IO);
3763           SignalExceptionFPE ();
3764         }
3765       less = 0;
3766       equal = 0;
3767       unordered = 1;
3768     }
3769   else
3770     {
3771       less = Less (ofs, oft, fmt);
3772       equal = Equal (ofs, oft, fmt);
3773       unordered = 0;
3774     }
3775   condition = (((cond & (1 << 2)) && less)
3776                || ((cond & (1 << 1)) && equal)
3777                || ((cond & (1 << 0)) && unordered));
3778   SETFCC (cc, condition);
3779 }
3780
3781 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3782 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3783 *mipsI:
3784 *mipsII:
3785 *mipsIII:
3786 {
3787   int fmt = FMT;
3788   check_fpu (SD_);
3789   check_fmt_p (SD_, fmt, instruction_0);
3790   do_c_cond_fmt (SD_, fmt, FT, FS, 0, COND, instruction_0);
3791 }
3792
3793 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3794 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3795 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3796 *mipsIV:
3797 *mipsV:
3798 *mips32:
3799 *mips64:
3800 *vr4100:
3801 *vr5000:
3802 *r3900:
3803 {
3804   int fmt = FMT;
3805   check_fpu (SD_);
3806   check_fmt_p (SD_, fmt, instruction_0);
3807   do_c_cond_fmt (SD_, fmt, FT, FS, CC, COND, instruction_0);
3808 }
3809
3810
3811 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3812 "ceil.l.%s<FMT> f<FD>, f<FS>"
3813 *mipsIII:
3814 *mipsIV:
3815 *mipsV:
3816 *mips64:
3817 *vr4100:
3818 *vr5000:
3819 *r3900:
3820 {
3821   int fmt = FMT;
3822   check_fpu (SD_);
3823   check_fmt (SD_, fmt, instruction_0);
3824   StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3825 }
3826
3827
3828 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3829 *mipsII:
3830 *mipsIII:
3831 *mipsIV:
3832 *mipsV:
3833 *mips32:
3834 *mips64:
3835 *vr4100:
3836 *vr5000:
3837 *r3900:
3838 {
3839   int fmt = FMT;
3840   check_fpu (SD_);
3841   check_fmt (SD_, fmt, instruction_0);
3842   StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3843 }
3844
3845
3846 // CFC1
3847 // CTC1
3848 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3849 "c%s<X>c1 r<RT>, f<FS>"
3850 *mipsI:
3851 *mipsII:
3852 *mipsIII:
3853 {
3854   check_fpu (SD_);
3855   if (X)
3856     {
3857       if (FS == 0)
3858         PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3859       else if (FS == 31)
3860         PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3861       /* else NOP */
3862       PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3863     }
3864   else
3865     { /* control from */
3866       if (FS == 0)
3867         PENDING_FILL(RT, EXTEND32 (FCR0));
3868       else if (FS == 31)
3869         PENDING_FILL(RT, EXTEND32 (FCR31));
3870       /* else NOP */
3871     }
3872 }
3873 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3874 "c%s<X>c1 r<RT>, f<FS>"
3875 *mipsIV:
3876 *mipsV:
3877 *mips32:
3878 *mips64:
3879 *vr4100:
3880 *vr5000:
3881 *r3900:
3882 {
3883   check_fpu (SD_);
3884   if (X)
3885     {
3886       /* control to */
3887       TRACE_ALU_INPUT1 (GPR[RT]);
3888       if (FS == 0)
3889         {
3890           FCR0 = VL4_8(GPR[RT]);
3891           TRACE_ALU_RESULT (FCR0);
3892         }
3893       else if (FS == 31)
3894         {
3895           FCR31 = VL4_8(GPR[RT]);
3896           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3897           TRACE_ALU_RESULT (FCR31);
3898         }
3899       else
3900         {
3901           TRACE_ALU_RESULT0 ();
3902         }
3903       /* else NOP */
3904     }
3905   else
3906     { /* control from */
3907       if (FS == 0)
3908         {
3909           TRACE_ALU_INPUT1 (FCR0);
3910           GPR[RT] = EXTEND32 (FCR0);
3911         }
3912       else if (FS == 31)
3913         {
3914           TRACE_ALU_INPUT1 (FCR31);
3915           GPR[RT] = EXTEND32 (FCR31);
3916         }
3917       TRACE_ALU_RESULT (GPR[RT]);
3918       /* else NOP */
3919     }
3920 }
3921
3922
3923 //
3924 // FIXME: Does not correctly differentiate between mips*
3925 //
3926 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3927 "cvt.d.%s<FMT> f<FD>, f<FS>"
3928 *mipsI:
3929 *mipsII:
3930 *mipsIII:
3931 *mipsIV:
3932 *mipsV:
3933 *mips32:
3934 *mips64:
3935 *vr4100:
3936 *vr5000:
3937 *r3900:
3938 {
3939   int fmt = FMT;
3940   check_fpu (SD_);
3941   {
3942     if ((fmt == fmt_double) | 0)
3943       SignalException (ReservedInstruction, instruction_0);
3944     else
3945       StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3946   }
3947 }
3948
3949
3950 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3951 "cvt.l.%s<FMT> f<FD>, f<FS>"
3952 *mipsIII:
3953 *mipsIV:
3954 *mipsV:
3955 *mips64:
3956 *vr4100:
3957 *vr5000:
3958 *r3900:
3959 {
3960   int fmt = FMT;
3961   check_fpu (SD_);
3962   {
3963     if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3964       SignalException (ReservedInstruction, instruction_0);
3965     else
3966       StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3967   }
3968 }
3969
3970
3971 //
3972 // FIXME: Does not correctly differentiate between mips*
3973 //
3974 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3975 "cvt.s.%s<FMT> f<FD>, f<FS>"
3976 *mipsI:
3977 *mipsII:
3978 *mipsIII:
3979 *mipsIV:
3980 *mipsV:
3981 *mips32:
3982 *mips64:
3983 *vr4100:
3984 *vr5000:
3985 *r3900:
3986 {
3987   int fmt = FMT;
3988   check_fpu (SD_);
3989   {
3990     if ((fmt == fmt_single) | 0)
3991       SignalException (ReservedInstruction, instruction_0);
3992     else
3993       StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
3994   }
3995 }
3996
3997
3998 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3999 "cvt.w.%s<FMT> f<FD>, f<FS>"
4000 *mipsI:
4001 *mipsII:
4002 *mipsIII:
4003 *mipsIV:
4004 *mipsV:
4005 *mips32:
4006 *mips64:
4007 *vr4100:
4008 *vr5000:
4009 *r3900:
4010 {
4011   int fmt = FMT;
4012   check_fpu (SD_);
4013   {
4014     if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4015       SignalException (ReservedInstruction, instruction_0);
4016     else
4017       StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
4018   }
4019 }
4020
4021
4022 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4023 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4024 *mipsI:
4025 *mipsII:
4026 *mipsIII:
4027 *mipsIV:
4028 *mipsV:
4029 *mips32:
4030 *mips64:
4031 *vr4100:
4032 *vr5000:
4033 *r3900:
4034 {
4035   int fmt = FMT;
4036   check_fpu (SD_);
4037   check_fmt (SD_, fmt, instruction_0);
4038   StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4039 }
4040
4041
4042 // DMFC1
4043 // DMTC1
4044 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
4045 "dm%s<X>c1 r<RT>, f<FS>"
4046 *mipsIII:
4047 {
4048   check_fpu (SD_);
4049   check_u64 (SD_, instruction_0);
4050   if (X)
4051     {
4052       if (SizeFGR() == 64)
4053         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4054       else if ((FS & 0x1) == 0)
4055         {
4056           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4057           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4058         }
4059     }
4060   else
4061     {
4062       if (SizeFGR() == 64)
4063         PENDING_FILL(RT,FGR[FS]);
4064       else if ((FS & 0x1) == 0)
4065         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4066       else
4067         {
4068           if (STATE_VERBOSE_P(SD))
4069             sim_io_eprintf (SD,
4070               "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
4071               (long) CIA);
4072           PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4073         }
4074     }
4075 }
4076 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
4077 "dm%s<X>c1 r<RT>, f<FS>"
4078 *mipsIV:
4079 *mipsV:
4080 *mips64:
4081 *vr4100:
4082 *vr5000:
4083 *r3900:
4084 {
4085   check_fpu (SD_);
4086   check_u64 (SD_, instruction_0);
4087   if (X)
4088     {
4089       if (SizeFGR() == 64)
4090         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4091       else if ((FS & 0x1) == 0)
4092         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4093     }
4094   else
4095     {
4096       if (SizeFGR() == 64)
4097         GPR[RT] = FGR[FS];
4098       else if ((FS & 0x1) == 0)
4099         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4100       else
4101         {
4102           if (STATE_VERBOSE_P(SD))
4103             sim_io_eprintf (SD,
4104               "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
4105                             (long) CIA);
4106           GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4107         }
4108     }
4109 }
4110
4111
4112 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4113 "floor.l.%s<FMT> f<FD>, f<FS>"
4114 *mipsIII:
4115 *mipsIV:
4116 *mipsV:
4117 *mips64:
4118 *vr4100:
4119 *vr5000:
4120 *r3900:
4121 {
4122   int fmt = FMT;
4123   check_fpu (SD_);
4124   check_fmt (SD_, fmt, instruction_0);
4125   StoreFPR(FD,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
4126 }
4127
4128
4129 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4130 "floor.w.%s<FMT> f<FD>, f<FS>"
4131 *mipsII:
4132 *mipsIII:
4133 *mipsIV:
4134 *mipsV:
4135 *mips32:
4136 *mips64:
4137 *vr4100:
4138 *vr5000:
4139 *r3900:
4140 {
4141   int fmt = FMT;
4142   check_fpu (SD_);
4143   check_fmt (SD_, fmt, instruction_0);
4144   StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
4145 }
4146
4147
4148 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
4149 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4150 *mipsII:
4151 *mipsIII:
4152 *mipsIV:
4153 *mipsV:
4154 *mips32:
4155 *mips64:
4156 *vr4100:
4157 *vr5000:
4158 *r3900:
4159 {
4160   check_fpu (SD_);
4161   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4162 }
4163
4164
4165 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4166 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4167 *mipsIV:
4168 *mipsV:
4169 *mips64:
4170 *vr5000:
4171 {
4172   check_fpu (SD_);
4173   check_u64 (SD_, instruction_0);
4174   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4175 }
4176
4177
4178
4179 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4180 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4181 *mipsI:
4182 *mipsII:
4183 *mipsIII:
4184 *mipsIV:
4185 *mipsV:
4186 *mips32:
4187 *mips64:
4188 *vr4100:
4189 *vr5000:
4190 *r3900:
4191 {
4192   check_fpu (SD_);
4193   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4194 }
4195
4196
4197 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4198 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4199 *mipsIV:
4200 *mipsV:
4201 *mips64:
4202 *vr5000:
4203 {
4204   check_fpu (SD_);
4205   check_u64 (SD_, instruction_0);
4206   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4207 }
4208
4209
4210
4211 //
4212 // FIXME: Not correct for mips*
4213 //
4214 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4215 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4216 *mipsIV:
4217 *mipsV:
4218 *mips64:
4219 *vr5000:
4220 {
4221   check_fpu (SD_);
4222   {
4223     StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
4224   }
4225 }
4226
4227
4228 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4229 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4230 *mipsIV:
4231 *mipsV:
4232 *mips64:
4233 *vr5000:
4234 {
4235   check_fpu (SD_);
4236   {
4237     StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
4238   }
4239 }
4240
4241
4242 // MFC1
4243 // MTC1
4244 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
4245 "m%s<X>c1 r<RT>, f<FS>"
4246 *mipsI:
4247 *mipsII:
4248 *mipsIII:
4249 {
4250   check_fpu (SD_);
4251   if (X)
4252     { /*MTC1*/
4253       if (SizeFGR() == 64)
4254         {
4255           if (STATE_VERBOSE_P(SD))
4256             sim_io_eprintf (SD,
4257                             "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
4258                             (long) CIA);
4259           PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4260         }
4261       else
4262         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4263     }
4264   else /*MFC1*/
4265     PENDING_FILL (RT, EXTEND32 (FGR[FS]));
4266 }
4267 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
4268 "m%s<X>c1 r<RT>, f<FS>"
4269 *mipsIV:
4270 *mipsV:
4271 *mips32:
4272 *mips64:
4273 *vr4100:
4274 *vr5000:
4275 *r3900:
4276 {
4277   int fs = FS;
4278   check_fpu (SD_);
4279   if (X)
4280     /*MTC1*/
4281     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4282   else /*MFC1*/
4283     GPR[RT] = EXTEND32 (FGR[FS]);
4284 }
4285
4286
4287 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4288 "mov.%s<FMT> f<FD>, f<FS>"
4289 *mipsI:
4290 *mipsII:
4291 *mipsIII:
4292 *mipsIV:
4293 *mipsV:
4294 *mips32:
4295 *mips64:
4296 *vr4100:
4297 *vr5000:
4298 *r3900:
4299 {
4300   int fmt = FMT;
4301   check_fpu (SD_);
4302   check_fmt_p (SD_, fmt, instruction_0);
4303   StoreFPR(FD,fmt,ValueFPR(FS,fmt));
4304 }
4305
4306
4307 // MOVF
4308 // MOVT
4309 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4310 "mov%s<TF> r<RD>, r<RS>, <CC>"
4311 *mipsIV:
4312 *mipsV:
4313 *mips32:
4314 *mips64:
4315 *vr5000:
4316 {
4317   check_fpu (SD_);
4318   if (GETFCC(CC) == TF)
4319     GPR[RD] = GPR[RS];
4320 }
4321
4322
4323 // MOVF.fmt
4324 // MOVT.fmt
4325 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4326 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4327 *mipsIV:
4328 *mipsV:
4329 *mips32:
4330 *mips64:
4331 *vr5000:
4332 {
4333   int fmt = FMT;
4334   check_fpu (SD_);
4335   {
4336    if (GETFCC(CC) == TF)
4337      StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4338    else
4339      StoreFPR (FD, fmt, ValueFPR (FD, fmt));
4340   }
4341 }
4342
4343
4344 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4345 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4346 *mipsIV:
4347 *mipsV:
4348 *mips32:
4349 *mips64:
4350 *vr5000:
4351 {
4352   check_fpu (SD_);
4353   if (GPR[RT] != 0)
4354     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4355   else
4356     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4357 }
4358
4359
4360 // MOVT see MOVtf
4361
4362
4363 // MOVT.fmt see MOVtf.fmt
4364
4365
4366
4367 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4368 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4369 *mipsIV:
4370 *mipsV:
4371 *mips32:
4372 *mips64:
4373 *vr5000:
4374 {
4375   check_fpu (SD_);
4376   if (GPR[RT] == 0)
4377     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4378   else
4379     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4380 }
4381
4382
4383 // MSUB.fmt
4384 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
4385 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
4386 *mipsIV:
4387 *mipsV:
4388 *mips64:
4389 *vr5000:
4390 {
4391   check_fpu (SD_);
4392   StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
4393 }
4394
4395
4396 // MSUB.fmt
4397 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
4398 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
4399 *mipsIV:
4400 *mipsV:
4401 *mips64:
4402 *vr5000:
4403 {
4404   check_fpu (SD_);
4405   StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
4406 }
4407
4408
4409 // MTC1 see MxC1
4410
4411
4412 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4413 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4414 *mipsI:
4415 *mipsII:
4416 *mipsIII:
4417 *mipsIV:
4418 *mipsV:
4419 *mips32:
4420 *mips64:
4421 *vr4100:
4422 *vr5000:
4423 *r3900:
4424 {
4425   int fmt = FMT;
4426   check_fpu (SD_);
4427   check_fmt_p (SD_, fmt, instruction_0);
4428   StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4429 }
4430
4431
4432 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4433 "neg.%s<FMT> f<FD>, f<FS>"
4434 *mipsI:
4435 *mipsII:
4436 *mipsIII:
4437 *mipsIV:
4438 *mipsV:
4439 *mips32:
4440 *mips64:
4441 *vr4100:
4442 *vr5000:
4443 *r3900:
4444 {
4445   int fmt = FMT;
4446   check_fpu (SD_);
4447   check_fmt_p (SD_, fmt, instruction_0);
4448   StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
4449 }
4450
4451
4452 // NMADD.fmt
4453 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
4454 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
4455 *mipsIV:
4456 *mipsV:
4457 *mips64:
4458 *vr5000:
4459 {
4460   check_fpu (SD_);
4461   StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
4462 }
4463
4464
4465 // NMADD.fmt
4466 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
4467 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
4468 *mipsIV:
4469 *mipsV:
4470 *mips64:
4471 *vr5000:
4472 {
4473   check_fpu (SD_);
4474   StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
4475 }
4476
4477
4478 // NMSUB.fmt
4479 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
4480 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
4481 *mipsIV:
4482 *mipsV:
4483 *mips64:
4484 *vr5000:
4485 {
4486   check_fpu (SD_);
4487   StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
4488 }
4489
4490
4491 // NMSUB.fmt
4492 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
4493 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
4494 *mipsIV:
4495 *mipsV:
4496 *mips64:
4497 *vr5000:
4498 {
4499   check_fpu (SD_);
4500   StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
4501 }
4502
4503
4504 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4505 "prefx <HINT>, r<INDEX>(r<BASE>)"
4506 *mipsIV:
4507 *mipsV:
4508 *mips64:
4509 *vr5000:
4510 {
4511   address_word base = GPR[BASE];
4512   address_word index = GPR[INDEX];
4513   {
4514     address_word vaddr = loadstore_ea (SD_, base, index);
4515     address_word paddr;
4516     int uncached;
4517     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4518       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4519   }
4520 }
4521
4522 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4523 "recip.%s<FMT> f<FD>, f<FS>"
4524 *mipsIV:
4525 *mipsV:
4526 *mips64:
4527 *vr5000:
4528 {
4529   int fmt = FMT;
4530   check_fpu (SD_);
4531   check_fmt (SD_, fmt, instruction_0);
4532   StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
4533 }
4534
4535
4536 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4537 "round.l.%s<FMT> f<FD>, f<FS>"
4538 *mipsIII:
4539 *mipsIV:
4540 *mipsV:
4541 *mips64:
4542 *vr4100:
4543 *vr5000:
4544 *r3900:
4545 {
4546   int fmt = FMT;
4547   check_fpu (SD_);
4548   check_fmt (SD_, fmt, instruction_0);
4549   StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
4550 }
4551
4552
4553 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4554 "round.w.%s<FMT> f<FD>, f<FS>"
4555 *mipsII:
4556 *mipsIII:
4557 *mipsIV:
4558 *mipsV:
4559 *mips32:
4560 *mips64:
4561 *vr4100:
4562 *vr5000:
4563 *r3900:
4564 {
4565   int fmt = FMT;
4566   check_fpu (SD_);
4567   check_fmt (SD_, fmt, instruction_0);
4568   StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
4569 }
4570
4571
4572 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4573 *mipsIV:
4574 *mipsV:
4575 *mips64:
4576 "rsqrt.%s<FMT> f<FD>, f<FS>"
4577 *vr5000:
4578 {
4579   int fmt = FMT;
4580   check_fpu (SD_);
4581   check_fmt (SD_, fmt, instruction_0);
4582   StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
4583 }
4584
4585
4586 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
4587 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4588 *mipsII:
4589 *mipsIII:
4590 *mipsIV:
4591 *mipsV:
4592 *mips32:
4593 *mips64:
4594 *vr4100:
4595 *vr5000:
4596 *r3900:
4597 {
4598   check_fpu (SD_);
4599   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4600 }
4601
4602
4603 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4604 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4605 *mipsIV:
4606 *mipsV:
4607 *mips64:
4608 *vr5000:
4609 {
4610   check_fpu (SD_);
4611   check_u64 (SD_, instruction_0);
4612   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4613 }
4614
4615
4616 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4617 "sqrt.%s<FMT> f<FD>, f<FS>"
4618 *mipsII:
4619 *mipsIII:
4620 *mipsIV:
4621 *mipsV:
4622 *mips32:
4623 *mips64:
4624 *vr4100:
4625 *vr5000:
4626 *r3900:
4627 {
4628   int fmt = FMT;
4629   check_fpu (SD_);
4630   check_fmt (SD_, fmt, instruction_0);
4631   StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4632 }
4633
4634
4635 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4636 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4637 *mipsI:
4638 *mipsII:
4639 *mipsIII:
4640 *mipsIV:
4641 *mipsV:
4642 *mips32:
4643 *mips64:
4644 *vr4100:
4645 *vr5000:
4646 *r3900:
4647 {
4648   int fmt = FMT;
4649   check_fpu (SD_);
4650   check_fmt_p (SD_, fmt, instruction_0);
4651   StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4652 }
4653
4654
4655
4656 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4657 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4658 *mipsI:
4659 *mipsII:
4660 *mipsIII:
4661 *mipsIV:
4662 *mipsV:
4663 *mips32:
4664 *mips64:
4665 *vr4100:
4666 *vr5000:
4667 *r3900:
4668 {
4669   address_word base = GPR[BASE];
4670   address_word offset = EXTEND16 (OFFSET);
4671   check_fpu (SD_);
4672   {
4673     address_word vaddr = loadstore_ea (SD_, base, offset);
4674     address_word paddr;
4675     int uncached;
4676     if ((vaddr & 3) != 0)
4677       {
4678         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4679       }
4680     else
4681       {
4682         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4683           {
4684             uword64 memval = 0;
4685             uword64 memval1 = 0;
4686             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4687             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4688             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4689             unsigned int byte;
4690             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4691             byte = ((vaddr & mask) ^ bigendiancpu);
4692             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4693             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4694           }
4695       }
4696   }
4697 }
4698
4699
4700 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4701 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4702 *mipsIV:
4703 *mipsV:
4704 *mips64:
4705 *vr5000:
4706 {
4707
4708   address_word base = GPR[BASE];
4709   address_word index = GPR[INDEX];
4710   check_fpu (SD_);
4711   check_u64 (SD_, instruction_0);
4712   {
4713    address_word vaddr = loadstore_ea (SD_, base, index);
4714    address_word paddr;
4715    int uncached;
4716    if ((vaddr & 3) != 0)
4717      {
4718        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4719      }
4720    else
4721    {
4722     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4723     {
4724      unsigned64 memval = 0;
4725      unsigned64 memval1 = 0;
4726      unsigned64 mask = 0x7;
4727      unsigned int byte;
4728      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4729      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4730      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4731       {
4732        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4733       }
4734     }
4735    }
4736   }
4737 }
4738
4739
4740 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4741 "trunc.l.%s<FMT> f<FD>, f<FS>"
4742 *mipsIII:
4743 *mipsIV:
4744 *mipsV:
4745 *mips64:
4746 *vr4100:
4747 *vr5000:
4748 *r3900:
4749 {
4750   int fmt = FMT;
4751   check_fpu (SD_);
4752   check_fmt (SD_, fmt, instruction_0);
4753   StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4754 }
4755
4756
4757 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4758 "trunc.w.%s<FMT> f<FD>, f<FS>"
4759 *mipsII:
4760 *mipsIII:
4761 *mipsIV:
4762 *mipsV:
4763 *mips32:
4764 *mips64:
4765 *vr4100:
4766 *vr5000:
4767 *r3900:
4768 {
4769   int fmt = FMT;
4770   check_fpu (SD_);
4771   check_fmt (SD_, fmt, instruction_0);
4772   StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4773 }
4774
4775 \f
4776 //
4777 // MIPS Architecture:
4778 //
4779 //        System Control Instruction Set (COP0)
4780 //
4781
4782
4783 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4784 "bc0f <OFFSET>"
4785 *mipsI:
4786 *mipsII:
4787 *mipsIII:
4788 *mipsIV:
4789 *mipsV:
4790 *mips32:
4791 *mips64:
4792 *vr4100:
4793 *vr5000:
4794
4795 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4796 "bc0f <OFFSET>"
4797 // stub needed for eCos as tx39 hardware bug workaround
4798 *r3900:
4799 {
4800   /* do nothing */
4801 }
4802
4803
4804 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4805 "bc0fl <OFFSET>"
4806 *mipsI:
4807 *mipsII:
4808 *mipsIII:
4809 *mipsIV:
4810 *mipsV:
4811 *mips32:
4812 *mips64:
4813 *vr4100:
4814 *vr5000:
4815
4816
4817 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4818 "bc0t <OFFSET>"
4819 *mipsI:
4820 *mipsII:
4821 *mipsIII:
4822 *mipsIV:
4823 *mipsV:
4824 *mips32:
4825 *mips64:
4826 *vr4100:
4827
4828
4829 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4830 "bc0tl <OFFSET>"
4831 *mipsI:
4832 *mipsII:
4833 *mipsIII:
4834 *mipsIV:
4835 *mipsV:
4836 *mips32:
4837 *mips64:
4838 *vr4100:
4839 *vr5000:
4840
4841
4842 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4843 "cache <OP>, <OFFSET>(r<BASE>)"
4844 *mipsIII:
4845 *mipsIV:
4846 *mipsV:
4847 *mips32:
4848 *mips64:
4849 *vr4100:
4850 *vr5000:
4851 *r3900:
4852 {
4853   address_word base = GPR[BASE];
4854   address_word offset = EXTEND16 (OFFSET);
4855   {
4856     address_word vaddr = loadstore_ea (SD_, base, offset);
4857     address_word paddr;
4858     int uncached;
4859     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4860       CacheOp(OP,vaddr,paddr,instruction_0);
4861   }
4862 }
4863
4864
4865 010000,1,0000000000000000000,111001:COP0:32::DI
4866 "di"
4867 *mipsI:
4868 *mipsII:
4869 *mipsIII:
4870 *mipsIV:
4871 *mipsV:
4872 *vr4100:
4873 *vr5000:
4874
4875
4876 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4877 "dmfc0 r<RT>, r<RD>"
4878 *mipsIII:
4879 *mipsIV:
4880 *mipsV:
4881 *mips64:
4882 {
4883   check_u64 (SD_, instruction_0);
4884   DecodeCoproc (instruction_0);
4885 }
4886
4887
4888 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4889 "dmtc0 r<RT>, r<RD>"
4890 *mipsIII:
4891 *mipsIV:
4892 *mipsV:
4893 *mips64:
4894 {
4895   check_u64 (SD_, instruction_0);
4896   DecodeCoproc (instruction_0);
4897 }
4898
4899
4900 010000,1,0000000000000000000,111000:COP0:32::EI
4901 "ei"
4902 *mipsI:
4903 *mipsII:
4904 *mipsIII:
4905 *mipsIV:
4906 *mipsV:
4907 *mips64:
4908 *vr4100:
4909 *vr5000:
4910
4911
4912 010000,1,0000000000000000000,011000:COP0:32::ERET
4913 "eret"
4914 *mipsIII:
4915 *mipsIV:
4916 *mipsV:
4917 *mips32:
4918 *mips64:
4919 *vr4100:
4920 *vr5000:
4921 {
4922   if (SR & status_ERL)
4923     {
4924       /* Oops, not yet available */
4925       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4926       NIA = EPC;
4927       SR &= ~status_ERL;
4928     }
4929   else
4930     {
4931       NIA = EPC;
4932       SR &= ~status_EXL;
4933     }
4934 }
4935
4936
4937 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4938 "mfc0 r<RT>, r<RD> # <REGX>"
4939 *mipsI:
4940 *mipsII:
4941 *mipsIII:
4942 *mipsIV:
4943 *mipsV:
4944 *mips32:
4945 *mips64:
4946 *vr4100:
4947 *vr5000:
4948 *r3900:
4949 {
4950   TRACE_ALU_INPUT0 ();
4951   DecodeCoproc (instruction_0);
4952   TRACE_ALU_RESULT (GPR[RT]);
4953 }
4954
4955 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4956 "mtc0 r<RT>, r<RD> # <REGX>"
4957 *mipsI:
4958 *mipsII:
4959 *mipsIII:
4960 *mipsIV:
4961 *mipsV:
4962 *mips32:
4963 *mips64:
4964 *vr4100:
4965 *vr5000:
4966 *r3900:
4967 {
4968   DecodeCoproc (instruction_0);
4969 }
4970
4971
4972 010000,1,0000000000000000000,010000:COP0:32::RFE
4973 "rfe"
4974 *mipsI:
4975 *mipsII:
4976 *mipsIII:
4977 *mipsIV:
4978 *mipsV:
4979 *vr4100:
4980 *vr5000:
4981 *r3900:
4982 {
4983   DecodeCoproc (instruction_0);
4984 }
4985
4986
4987 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4988 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4989 *mipsI:
4990 *mipsII:
4991 *mipsIII:
4992 *mipsIV:
4993 *mipsV:
4994 *mips32:
4995 *mips64:
4996 *vr4100:
4997 *r3900:
4998 {
4999   DecodeCoproc (instruction_0);
5000 }
5001
5002
5003
5004 010000,1,0000000000000000000,001000:COP0:32::TLBP
5005 "tlbp"
5006 *mipsI:
5007 *mipsII:
5008 *mipsIII:
5009 *mipsIV:
5010 *mipsV:
5011 *mips32:
5012 *mips64:
5013 *vr4100:
5014 *vr5000:
5015
5016
5017 010000,1,0000000000000000000,000001:COP0:32::TLBR
5018 "tlbr"
5019 *mipsI:
5020 *mipsII:
5021 *mipsIII:
5022 *mipsIV:
5023 *mipsV:
5024 *mips32:
5025 *mips64:
5026 *vr4100:
5027 *vr5000:
5028
5029
5030 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5031 "tlbwi"
5032 *mipsI:
5033 *mipsII:
5034 *mipsIII:
5035 *mipsIV:
5036 *mipsV:
5037 *mips32:
5038 *mips64:
5039 *vr4100:
5040 *vr5000:
5041
5042
5043 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5044 "tlbwr"
5045 *mipsI:
5046 *mipsII:
5047 *mipsIII:
5048 *mipsIV:
5049 *mipsV:
5050 *mips32:
5051 *mips64:
5052 *vr4100:
5053 *vr5000:
5054
5055 \f
5056 :include:::m16.igen
5057 :include:::tx.igen
5058 :include:::vr.igen
5059 \f