sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips32r6:mipsisa32r6:
  50 :model:::mips64:mipsisa64:
  51 :model:::mips64r2:mipsisa64r2:
  52 :model:::mips64r6:mipsisa64r6:
  53
  54 //  Vendor ISAs:
  55 //
  56 //  Standard MIPS ISA instructions used for these models are listed here,
  57 //  as are functions needed by those standard instructions.  Instructions
  58 //  which are model-dependent and which are not in the standard MIPS ISAs
  59 //  (or which pre-date or use different encodings than the standard
  60 //  instructions) are (for the most part) in separate .igen files.
  61 :model:::vr4100:mips4100:               // vr.igen
  62 :model:::vr4120:mips4120:
  63 :model:::vr5000:mips5000:
  64 :model:::vr5400:mips5400:
  65 :model:::vr5500:mips5500:
  66 :model:::r3900:mips3900:                // tx.igen
  67
  68 //  MIPS Application Specific Extensions (ASEs)
  69 //
  70 //  Instructions for the ASEs are in separate .igen files.
  71 //  ASEs add instructions on to a base ISA.
  72 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  73 :model:::mips16e:mips16e:               // m16e.igen
  74 :model:::mips3d:mips3d:                 // mips3d.igen
  75 :model:::mdmx:mdmx:                     // mdmx.igen
  76 :model:::dsp:dsp:                       // dsp.igen
  77 :model:::dsp2:dsp2:                     // dsp2.igen
  78 :model:::smartmips:smartmips:           // smartmips.igen
  79 :model:::micromips32:micromips64:       // micromips.igen
  80 :model:::micromips64:micromips64:       // micromips.igen
  81 :model:::micromipsdsp:micromipsdsp:     // micromipsdsp.igen
  82
  83 //  Vendor Extensions
  84 //
  85 //  Instructions specific to these extensions are in separate .igen files.
  86 //  Extensions add instructions on to a base ISA.
  87 :model:::sb1:sb1:                       // sb1.igen
  88
  89
  90 // Pseudo instructions known by IGEN
  91 :internal::::illegal:
  92 {
  93   SignalException (ReservedInstruction, 0);
  94 }
  95
  96
  97 // Pseudo instructions known by interp.c
  98 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  99 000000,5.*,5.*,5.*,5.OP,111001:SPECIAL:32::RSVD
 100 "rsvd <OP>"
 101 {
 102   SignalException (ReservedInstruction, instruction_0);
 103 }
 104
 105
 106
 107 // Helpers:
 108 //
 109 // Check if given instruction is CTI, if so signal
 110 //
 111 :function:::void:signal_if_cti:instruction_word instr
 112 {
 113   uint32_t maj = (instr & 0xfc000000) >> 26;
 114   uint32_t special = instr & 0x3f;
 115   if ((maj & 0x3e) == 0x06 /* Branch/Jump */
 116       || ((maj & 0x38) == 0 && !((maj & 0x6) == 0))
 117       || maj == 0x18
 118       || (maj & 0x37) == 0x32
 119       || (maj & 0x37) == 0x36
 120       || ((maj == 0) && (special == 0x9))
 121       /* DERET/ERET/WAIT */
 122       || ((maj == 0x10) && (instr & 0x02000000)
 123           && (special == 0x1f || special == 0x18 || special == 0x20)))
 124     {
 125       SignalException (ReservedInstruction, instr);
 126     }
 127 }
 128
 129 //
 130 // Simulate a 32 bit delayslot instruction
 131 //
 132
 133 :function:::address_word:delayslot32:address_word target
 134 {
 135   instruction_word delay_insn;
 136   sim_events_slip (SD, 1);
 137   DSPC = CIA;
 138   CIA = CIA + 4; /* NOTE not mips16 */
 139   STATE |= simDELAYSLOT;
 140   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 141   signal_if_cti (SD_, delay_insn);
 142   ENGINE_ISSUE_PREFIX_HOOK();
 143   idecode_issue (CPU_, delay_insn, (CIA));
 144   STATE &= ~simDELAYSLOT;
 145   return target;
 146 }
 147
 148 //
 149 // Simulate a 32 bit forbidden slot instruction
 150 //
 151
 152 :function:::address_word:forbiddenslot32:
 153 *mips32r6:
 154 *mips64r6:
 155 {
 156   instruction_word delay_insn;
 157   sim_events_slip (SD, 1);
 158   DSPC = CIA;
 159   CIA = CIA + 4;
 160   STATE |= simFORBIDDENSLOT;
 161   delay_insn = IMEM32 (CIA);
 162   signal_if_cti (SD_, delay_insn);
 163   ENGINE_ISSUE_PREFIX_HOOK ();
 164   idecode_issue (CPU_, delay_insn, (CIA));
 165   STATE &= ~simFORBIDDENSLOT;
 166   return CIA + 4;
 167 }
 168
 169 :function:::address_word:nullify_next_insn32:
 170 {
 171   sim_events_slip (SD, 1);
 172   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 173   return CIA + 8;
 174 }
 175
 176
 177 // Helper:
 178 //
 179 // Calculate an effective address given a base and an offset.
 180 //
 181
 182 :function:::address_word:loadstore_ea:address_word base, address_word offset
 183 *mipsI:
 184 *mipsII:
 185 *mipsIII:
 186 *mipsIV:
 187 *mipsV:
 188 *mips32:
 189 *mips32r2:
 190 *mips32r6:
 191 *vr4100:
 192 *vr5000:
 193 *r3900:
 194 *micromips32:
 195 {
 196   return base + offset;
 197 }
 198
 199 :function:::address_word:loadstore_ea:address_word base, address_word offset
 200 *mips64:
 201 *mips64r2:
 202 *micromips64:
 203 *mips64r6:
 204 {
 205 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 206   /* If in user mode and UX is not set, use 32-bit compatibility effective
 207      address computations as defined in the MIPS64 Architecture for
 208      Programmers Volume III, Revision 0.95, section 4.9.  */
 209   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 210       == (ksu_user << status_KSU_shift))
 211     return (address_word)((int32_t)base + (int32_t)offset);
 212 #endif
 213   return base + offset;
 214 }
 215
 216
 217 // Helper:
 218 //
 219 // Check that a 32-bit register value is properly sign-extended.
 220 // (See NotWordValue in ISA spec.)
 221 //
 222
 223 :function:::int:not_word_value:unsigned_word value
 224 *mipsI:
 225 *mipsII:
 226 *mipsIII:
 227 *mipsIV:
 228 *mipsV:
 229 *vr4100:
 230 *vr5000:
 231 *r3900:
 232 *mips32:
 233 *mips32r2:
 234 *mips32r6:
 235 *mips64:
 236 *mips64r2:
 237 *micromips32:
 238 *micromips64:
 239 *mips64r6:
 240 {
 241 #if WITH_TARGET_WORD_BITSIZE == 64
 242   return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
 243 #else
 244   return 0;
 245 #endif
 246 }
 247
 248 // Helper:
 249 //
 250 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 251 // theoretically portable code which invokes non-portable behaviour from
 252 // running with no indication of the portability issue.
 253 // (See definition of UNPREDICTABLE in ISA spec.)
 254 //
 255
 256 :function:::void:unpredictable:
 257 *mipsI:
 258 *mipsII:
 259 *mipsIII:
 260 *mipsIV:
 261 *mipsV:
 262 *vr4100:
 263 *vr5000:
 264 *r3900:
 265 {
 266 }
 267
 268 :function:::void:unpredictable:
 269 *mips32:
 270 *mips32r2:
 271 *mips32r6:
 272 *mips64:
 273 *mips64r2:
 274 *micromips32:
 275 *micromips64:
 276 *mips64r6:
 277 {
 278   unpredictable_action (CPU, CIA);
 279 }
 280
 281
 282 // Helpers:
 283 //
 284 // Check that an access to a HI/LO register meets timing requirements
 285 //
 286 // In all MIPS ISAs,
 287 //
 288 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 289 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 290 //
 291 // The following restrictions exist for MIPS I - MIPS III:
 292 //
 293 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 294 //      in between makes MF UNPREDICTABLE. (2)
 295 //
 296 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 297 //      in between makes MF UNPREDICTABLE. (3)
 298 //
 299 // On the r3900, restriction (2) is not present, and restriction (3) is not
 300 // present for multiplication.
 301 //
 302 // Unfortunately, there seems to be some confusion about whether the last
 303 // two restrictions should apply to "MIPS IV" as well.  One edition of
 304 // the MIPS IV ISA says they do, but references in later ISA documents
 305 // suggest they don't.
 306 //
 307 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 308 // these restrictions, while others, like the VR5500, don't.  To accomodate
 309 // such differences, the MIPS IV and MIPS V version of these helper functions
 310 // use auxillary routines to determine whether the restriction applies.
 311
 312 // check_mf_cycles:
 313 //
 314 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 315 // to check for restrictions (2) and (3) above.
 316 //
 317 :function:::int:check_mf_cycles:hilo_history *history, int64_t time, const char *new
 318 {
 319   if (history->mf.timestamp + 3 > time)
 320     {
 321       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 322                         itable[MY_INDEX].name,
 323                         new, (long) CIA,
 324                         (long) history->mf.cia);
 325       return 0;
 326     }
 327   return 1;
 328 }
 329
 330
 331 // check_mt_hilo:
 332 //
 333 // Check for restriction (2) above (for ISAs/processors that have it),
 334 // and record timestamps for restriction (1) above.
 335 //
 336 :function:::int:check_mt_hilo:hilo_history *history
 337 *mipsI:
 338 *mipsII:
 339 *mipsIII:
 340 *vr4100:
 341 *vr5000:
 342 {
 343   int64_t time = sim_events_time (SD);
 344   int ok = check_mf_cycles (SD_, history, time, "MT");
 345   history->mt.timestamp = time;
 346   history->mt.cia = CIA;
 347   return ok;
 348 }
 349
 350 :function:::int:check_mt_hilo:hilo_history *history
 351 *mipsIV:
 352 *mipsV:
 353 {
 354   int64_t time = sim_events_time (SD);
 355   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 356             || check_mf_cycles (SD_, history, time, "MT"));
 357   history->mt.timestamp = time;
 358   history->mt.cia = CIA;
 359   return ok;
 360 }
 361
 362 :function:::int:check_mt_hilo:hilo_history *history
 363 *mips32:
 364 *mips32r2:
 365 *mips32r6:
 366 *mips64:
 367 *mips64r2:
 368 *mips64r6:
 369 *r3900:
 370 *micromips32:
 371 *micromips64:
 372 {
 373   int64_t time = sim_events_time (SD);
 374   history->mt.timestamp = time;
 375   history->mt.cia = CIA;
 376   return 1;
 377 }
 378
 379
 380 // check_mf_hilo:
 381 //
 382 // Check for restriction (1) above, and record timestamps for
 383 // restriction (2) and (3) above.
 384 //
 385 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 386 *mipsI:
 387 *mipsII:
 388 *mipsIII:
 389 *mipsIV:
 390 *mipsV:
 391 *mips32:
 392 *mips32r2:
 393 *mips32r6:
 394 *mips64:
 395 *mips64r2:
 396 *mips64r6:
 397 *vr4100:
 398 *vr5000:
 399 *r3900:
 400 *micromips32:
 401 *micromips64:
 402 {
 403   int64_t time = sim_events_time (SD);
 404   int ok = 1;
 405   if (peer != NULL
 406       && peer->mt.timestamp > history->op.timestamp
 407       && history->mt.timestamp < history->op.timestamp
 408       && ! (history->mf.timestamp > history->op.timestamp
 409             && history->mf.timestamp < peer->mt.timestamp)
 410       && ! (peer->mf.timestamp > history->op.timestamp
 411             && peer->mf.timestamp < peer->mt.timestamp))
 412     {
 413       /* The peer has been written to since the last OP yet we have
 414          not */
 415       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 416                         itable[MY_INDEX].name,
 417                         (long) CIA,
 418                         (long) history->op.cia,
 419                         (long) peer->mt.cia);
 420       ok = 0;
 421     }
 422   history->mf.timestamp = time;
 423   history->mf.cia = CIA;
 424   return ok;
 425 }
 426
 427
 428
 429 // check_mult_hilo:
 430 //
 431 // Check for restriction (3) above (for ISAs/processors that have it)
 432 // for MULT ops, and record timestamps for restriction (1) above.
 433 //
 434 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 435 *mipsI:
 436 *mipsII:
 437 *mipsIII:
 438 *vr4100:
 439 *vr5000:
 440 {
 441   int64_t time = sim_events_time (SD);
 442   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 443             && check_mf_cycles (SD_, lo, time, "OP"));
 444   hi->op.timestamp = time;
 445   lo->op.timestamp = time;
 446   hi->op.cia = CIA;
 447   lo->op.cia = CIA;
 448   return ok;
 449 }
 450
 451 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 452 *mipsIV:
 453 *mipsV:
 454 {
 455   int64_t time = sim_events_time (SD);
 456   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 457             || (check_mf_cycles (SD_, hi, time, "OP")
 458                 && check_mf_cycles (SD_, lo, time, "OP")));
 459   hi->op.timestamp = time;
 460   lo->op.timestamp = time;
 461   hi->op.cia = CIA;
 462   lo->op.cia = CIA;
 463   return ok;
 464 }
 465
 466 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 467 *mips32:
 468 *mips32r2:
 469 *mips32r6:
 470 *mips64:
 471 *mips64r2:
 472 *mips64r6:
 473 *r3900:
 474 *micromips32:
 475 *micromips64:
 476 {
 477   /* FIXME: could record the fact that a stall occured if we want */
 478   int64_t time = sim_events_time (SD);
 479   hi->op.timestamp = time;
 480   lo->op.timestamp = time;
 481   hi->op.cia = CIA;
 482   lo->op.cia = CIA;
 483   return 1;
 484 }
 485
 486
 487 // check_div_hilo:
 488 //
 489 // Check for restriction (3) above (for ISAs/processors that have it)
 490 // for DIV ops, and record timestamps for restriction (1) above.
 491 //
 492 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 493 *mipsI:
 494 *mipsII:
 495 *mipsIII:
 496 *vr4100:
 497 *vr5000:
 498 *r3900:
 499 {
 500   int64_t time = sim_events_time (SD);
 501   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 502             && check_mf_cycles (SD_, lo, time, "OP"));
 503   hi->op.timestamp = time;
 504   lo->op.timestamp = time;
 505   hi->op.cia = CIA;
 506   lo->op.cia = CIA;
 507   return ok;
 508 }
 509
 510 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 511 *mipsIV:
 512 *mipsV:
 513 {
 514   int64_t time = sim_events_time (SD);
 515   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 516             || (check_mf_cycles (SD_, hi, time, "OP")
 517                 && check_mf_cycles (SD_, lo, time, "OP")));
 518   hi->op.timestamp = time;
 519   lo->op.timestamp = time;
 520   hi->op.cia = CIA;
 521   lo->op.cia = CIA;
 522   return ok;
 523 }
 524
 525 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 526 *mips32:
 527 *mips32r2:
 528 *mips32r6:
 529 *mips64:
 530 *mips64r2:
 531 *micromips32:
 532 *micromips64:
 533 *mips64r6:
 534 {
 535   int64_t time = sim_events_time (SD);
 536   hi->op.timestamp = time;
 537   lo->op.timestamp = time;
 538   hi->op.cia = CIA;
 539   lo->op.cia = CIA;
 540   return 1;
 541 }
 542
 543
 544 // Helper:
 545 //
 546 // Check that the 64-bit instruction can currently be used, and signal
 547 // a ReservedInstruction exception if not.
 548 //
 549
 550 :function:::void:check_u64:instruction_word insn
 551 *mipsIII:
 552 *mipsIV:
 553 *mipsV:
 554 *vr4100:
 555 *vr5000:
 556 *vr5400:
 557 *vr5500:
 558 *r3900:
 559 {
 560   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 561 }
 562
 563 :function:::void:check_u64:instruction_word insn
 564 *mips16e:
 565 *mips64:
 566 *mips64r2:
 567 *mips32:
 568 *mips32r2:
 569 *mips32r6:
 570 *micromips64:
 571 *micromips32:
 572 *mips64r6:
 573 {
 574 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 575   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 576     SignalException (ReservedInstruction, insn);
 577 #endif
 578 }
 579
 580
 581
 582 //
 583 // MIPS Architecture:
 584 //
 585 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 586 //
 587
 588
 589 :function:::void:do_add:int rs, int rt, int rd
 590 {
 591   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 592     Unpredictable ();
 593   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 594   {
 595     ALU32_BEGIN (GPR[rs]);
 596     ALU32_ADD (GPR[rt]);
 597     ALU32_END (GPR[rd]);   /* This checks for overflow.  */
 598   }
 599   TRACE_ALU_RESULT (GPR[rd]);
 600 }
 601
 602 :function:::void:do_addi:int rs, int rt, uint16_t immediate
 603 {
 604   if (NotWordValue (GPR[rs]))
 605     Unpredictable ();
 606   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 607   {
 608     ALU32_BEGIN (GPR[rs]);
 609     ALU32_ADD (EXTEND16 (immediate));
 610     ALU32_END (GPR[rt]);   /* This checks for overflow.  */
 611   }
 612   TRACE_ALU_RESULT (GPR[rt]);
 613 }
 614
 615 :function:::void:do_andi:int rs, int rt, unsigned int immediate
 616 {
 617   TRACE_ALU_INPUT2 (GPR[rs], immediate);
 618   GPR[rt] = GPR[rs] & immediate;
 619   TRACE_ALU_RESULT (GPR[rt]);
 620 }
 621
 622 :function:::void:do_dadd:int rd, int rs, int rt
 623 {
 624   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 625   {
 626     ALU64_BEGIN (GPR[rs]);
 627     ALU64_ADD (GPR[rt]);
 628     ALU64_END (GPR[rd]);   /* This checks for overflow.  */
 629   }
 630   TRACE_ALU_RESULT (GPR[rd]);
 631 }
 632
 633 :function:::void:do_daddi:int rt, int rs, int immediate
 634 {
 635   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 636   {
 637     ALU64_BEGIN (GPR[rs]);
 638     ALU64_ADD (EXTEND16 (immediate));
 639     ALU64_END (GPR[rt]);   /* This checks for overflow.  */
 640   }
 641   TRACE_ALU_RESULT (GPR[rt]);
 642 }
 643
 644 :function:::void:do_dsll32:int rd, int rt, int shift
 645 {
 646   int s = 32 + shift;
 647   TRACE_ALU_INPUT2 (GPR[rt], s);
 648   GPR[rd] = GPR[rt] << s;
 649   TRACE_ALU_RESULT (GPR[rd]);
 650 }
 651
 652 :function:::void:do_dsra32:int rd, int rt, int shift
 653 {
 654   int s = 32 + shift;
 655   TRACE_ALU_INPUT2 (GPR[rt], s);
 656   GPR[rd] = ((int64_t) GPR[rt]) >> s;
 657   TRACE_ALU_RESULT (GPR[rd]);
 658 }
 659
 660 :function:::void:do_dsrl32:int rd, int rt, int shift
 661 {
 662   int s = 32 + shift;
 663   TRACE_ALU_INPUT2 (GPR[rt], s);
 664   GPR[rd] = (uint64_t) GPR[rt] >> s;
 665   TRACE_ALU_RESULT (GPR[rd]);
 666 }
 667
 668 :function:::void:do_dsub:int rd, int rs, int rt
 669 {
 670   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 671   {
 672     ALU64_BEGIN (GPR[rs]);
 673     ALU64_SUB (GPR[rt]);
 674     ALU64_END (GPR[rd]);   /* This checks for overflow.  */
 675   }
 676   TRACE_ALU_RESULT (GPR[rd]);
 677 }
 678
 679 :function:::void:do_break:address_word instruction_0
 680 {
 681   /* Check for some break instruction which are reserved for use by the
 682      simulator.  */
 683   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 684   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 685       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 686     {
 687       sim_engine_halt (SD, CPU, NULL, cia,
 688                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 689     }
 690   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 691            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 692     {
 693       if (STATE & simDELAYSLOT)
 694         PC = cia - 4; /* reference the branch instruction */
 695       else
 696         PC = cia;
 697       SignalException (BreakPoint, instruction_0);
 698     }
 699
 700   else
 701     {
 702       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 703          the exception. */
 704       SignalException (BreakPoint, instruction_0);
 705     }
 706 }
 707
 708 :function:::void:do_break16:address_word instruction_0
 709 {
 710   if (STATE & simDELAYSLOT)
 711     PC = cia - 2; /* reference the branch instruction */
 712   else
 713     PC = cia;
 714   SignalException (BreakPoint, instruction_0);
 715 }
 716
 717 :function:::void:do_clo:int rd, int rs
 718 {
 719   uint32_t temp = GPR[rs];
 720   uint32_t i, mask;
 721   if (NotWordValue (GPR[rs]))
 722     Unpredictable ();
 723   TRACE_ALU_INPUT1 (GPR[rs]);
 724   for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
 725     {
 726       if ((temp & mask) == 0)
 727         break;
 728       mask >>= 1;
 729     }
 730   GPR[rd] = EXTEND32 (i);
 731   TRACE_ALU_RESULT (GPR[rd]);
 732 }
 733
 734 :function:::void:do_clz:int rd, int rs
 735 {
 736   uint32_t temp = GPR[rs];
 737   uint32_t i, mask;
 738   if (NotWordValue (GPR[rs]))
 739     Unpredictable ();
 740   TRACE_ALU_INPUT1 (GPR[rs]);
 741   for (mask = ((uint32_t)1<<31), i = 0; i < 32; ++i)
 742     {
 743       if ((temp & mask) != 0)
 744         break;
 745       mask >>= 1;
 746     }
 747   GPR[rd] = EXTEND32 (i);
 748   TRACE_ALU_RESULT (GPR[rd]);
 749 }
 750
 751 :function:::void:do_dclo:int rd, int rs
 752 {
 753   uint64_t temp = GPR[rs];
 754   uint32_t i;
 755   uint64_t mask;
 756   TRACE_ALU_INPUT1 (GPR[rs]);
 757   for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
 758     {
 759       if ((temp & mask) == 0)
 760         break;
 761       mask >>= 1;
 762     }
 763   GPR[rd] = EXTEND32 (i);
 764   TRACE_ALU_RESULT (GPR[rd]);
 765 }
 766
 767 :function:::void:do_dclz:int rd, int rs
 768 {
 769   uint64_t temp = GPR[rs];
 770   uint32_t i;
 771   uint64_t mask;
 772   TRACE_ALU_INPUT1 (GPR[rs]);
 773   for (mask = ((uint64_t)1<<63), i = 0; i < 64; ++i)
 774     {
 775       if ((temp & mask) != 0)
 776         break;
 777       mask >>= 1;
 778     }
 779   GPR[rd] = EXTEND32 (i);
 780   TRACE_ALU_RESULT (GPR[rd]);
 781 }
 782
 783 :function:::void:do_lb:int rt, int offset, int base
 784 {
 785   GPR[rt] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[base],
 786                               EXTEND16 (offset)));
 787 }
 788
 789 :function:::void:do_lh:int rt, int offset, int base
 790 {
 791   GPR[rt] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[base],
 792                                EXTEND16 (offset)));
 793 }
 794
 795 :function:::void:do_lwr:int rt, int offset, int base
 796 {
 797   GPR[rt] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[base],
 798                                      EXTEND16 (offset), GPR[rt]));
 799 }
 800
 801 :function:::void:do_lwl:int rt, int offset, int base
 802 {
 803   GPR[rt] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[base],
 804                                     EXTEND16 (offset), GPR[rt]));
 805 }
 806
 807 :function:::void:do_lwc:int num, int rt, int offset, int base
 808 {
 809   COP_LW (num, rt, do_load (SD_, AccessLength_WORD, GPR[base],
 810                             EXTEND16 (offset)));
 811 }
 812
 813 :function:::void:do_lw:int rt, int offset, int base
 814 {
 815   GPR[rt] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[base],
 816                                EXTEND16 (offset)));
 817 }
 818
 819 :function:::void:do_lwu:int rt, int offset, int base, address_word instruction_0
 820 {
 821   check_u64 (SD_, instruction_0);
 822   GPR[rt] = do_load (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset));
 823 }
 824
 825 :function:::void:do_lhu:int rt, int offset, int base
 826 {
 827   GPR[rt] = do_load (SD_, AccessLength_HALFWORD, GPR[base], EXTEND16 (offset));
 828 }
 829
 830 :function:::void:do_ldc:int num, int rt, int offset, int base
 831 {
 832   COP_LD (num, rt, do_load (SD_, AccessLength_DOUBLEWORD, GPR[base],
 833                             EXTEND16 (offset)));
 834 }
 835
 836 :function:::void:do_lbu:int rt, int offset, int base
 837 {
 838   GPR[rt] = do_load (SD_, AccessLength_BYTE, GPR[base], EXTEND16 (offset));
 839 }
 840
 841 :function:::void:do_ll:int rt, int insn_offset, int basereg
 842 {
 843   address_word base = GPR[basereg];
 844   address_word offset = EXTEND16 (insn_offset);
 845     {
 846       address_word vaddr = loadstore_ea (SD_, base, offset);
 847       address_word paddr = vaddr;
 848       if ((vaddr & 3) != 0)
 849         {
 850           SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer,
 851                            sim_core_unaligned_signal);
 852         }
 853       else
 854         {
 855           uint64_t memval = 0;
 856           uint64_t memval1 = 0;
 857           uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
 858           unsigned int shift = 2;
 859           unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
 860           unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
 861           unsigned int byte;
 862           paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
 863           LoadMemory (&memval, &memval1, AccessLength_WORD, paddr, vaddr,
 864                       isDATA, isREAL);
 865           byte = ((vaddr & mask) ^ (bigend << shift));
 866           GPR[rt] = EXTEND32 (memval >> (8 * byte));
 867           LLBIT = 1;
 868         }
 869     }
 870 }
 871
 872 :function:::void:do_lld:int rt, int roffset, int rbase
 873 {
 874   address_word base = GPR[rbase];
 875   address_word offset = EXTEND16 (roffset);
 876   {
 877     address_word vaddr = loadstore_ea (SD_, base, offset);
 878     address_word paddr = vaddr;
 879
 880     if ((vaddr & 7) != 0)
 881       {
 882         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer,
 883                 sim_core_unaligned_signal);
 884       }
 885     else
 886       {
 887         uint64_t memval = 0;
 888         uint64_t memval1 = 0;
 889         LoadMemory (&memval, &memval1, AccessLength_DOUBLEWORD, paddr, vaddr,
 890                     isDATA, isREAL);
 891         GPR[rt] = memval;
 892         LLBIT = 1;
 893       }
 894   }
 895 }
 896
 897 :function:::void:do_lui:int rt, int immediate
 898 {
 899   TRACE_ALU_INPUT1 (immediate);
 900   GPR[rt] = EXTEND32 (immediate << 16);
 901   TRACE_ALU_RESULT (GPR[rt]);
 902 }
 903
 904 :function:::void:do_madd:int rs, int rt
 905 {
 906   int64_t temp;
 907   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 908   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 909     Unpredictable ();
 910   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 911   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
 912           + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
 913   LO = EXTEND32 (temp);
 914   HI = EXTEND32 (VH4_8 (temp));
 915   TRACE_ALU_RESULT2 (HI, LO);
 916 }
 917
 918 :function:::void:do_dsp_madd:int ac, int rs, int rt
 919 {
 920   int64_t temp;
 921   if (ac == 0)
 922     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 923   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 924     Unpredictable ();
 925   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 926   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
 927           + ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
 928   DSPLO(ac) = EXTEND32 (temp);
 929   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
 930   if (ac == 0)
 931     TRACE_ALU_RESULT2 (HI, LO);
 932 }
 933
 934 :function:::void:do_maddu:int rs, int rt
 935 {
 936   uint64_t temp;
 937   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 938   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 939     Unpredictable ();
 940   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 941   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
 942           + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
 943   ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
 944   LO = EXTEND32 (temp);
 945   HI = EXTEND32 (VH4_8 (temp));
 946   TRACE_ALU_RESULT2 (HI, LO);
 947 }
 948
 949 :function:::void:do_dsp_maddu:int ac, int rs, int rt
 950 {
 951   uint64_t temp;
 952   if (ac == 0)
 953     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 954   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 955     Unpredictable ();
 956   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 957   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
 958           + ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
 959   if (ac == 0)
 960     ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
 961   DSPLO(ac) = EXTEND32 (temp);
 962   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
 963   if (ac == 0)
 964     TRACE_ALU_RESULT2 (HI, LO);
 965 }
 966
 967 :function:::void:do_dsp_mfhi:int ac, int rd
 968 {
 969   if (ac == 0)
 970     do_mfhi (SD_, rd);
 971   else
 972     GPR[rd] = DSPHI(ac);
 973 }
 974
 975 :function:::void:do_dsp_mflo:int ac, int rd
 976 {
 977   if (ac == 0)
 978     do_mflo (SD_, rd);
 979   else
 980     GPR[rd] = DSPLO(ac);
 981 }
 982
 983 :function:::void:do_movn:int rd, int rs, int rt
 984 {
 985   if (GPR[rt] != 0)
 986     {
 987       GPR[rd] = GPR[rs];
 988       TRACE_ALU_RESULT (GPR[rd]);
 989     }
 990 }
 991
 992 :function:::void:do_movz:int rd, int rs, int rt
 993 {
 994   if (GPR[rt] == 0)
 995     {
 996       GPR[rd] = GPR[rs];
 997       TRACE_ALU_RESULT (GPR[rd]);
 998     }
 999 }
1000
1001 :function:::void:do_msub:int rs, int rt
1002 {
1003   int64_t temp;
1004   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1005   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1006     Unpredictable ();
1007   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1008   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
1009           - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
1010   LO = EXTEND32 (temp);
1011   HI = EXTEND32 (VH4_8 (temp));
1012   TRACE_ALU_RESULT2 (HI, LO);
1013 }
1014
1015 :function:::void:do_dsp_msub:int ac, int rs, int rt
1016 {
1017   int64_t temp;
1018   if (ac == 0)
1019     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1020   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1021     Unpredictable ();
1022   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1023   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
1024           - ((int64_t) EXTEND32 (GPR[rt]) * (int64_t) EXTEND32 (GPR[rs])));
1025   DSPLO(ac) = EXTEND32 (temp);
1026   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
1027   if (ac == 0)
1028     TRACE_ALU_RESULT2 (HI, LO);
1029 }
1030
1031 :function:::void:do_msubu:int rs, int rt
1032 {
1033   uint64_t temp;
1034   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1035   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1036     Unpredictable ();
1037   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1038   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
1039           - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
1040   LO = EXTEND32 (temp);
1041   HI = EXTEND32 (VH4_8 (temp));
1042   TRACE_ALU_RESULT2 (HI, LO);
1043 }
1044
1045 :function:::void:do_dsp_msubu:int ac, int rs, int rt
1046 {
1047   uint64_t temp;
1048   if (ac == 0)
1049     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1050   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1051     Unpredictable ();
1052   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1053   temp = (U8_4 (VL4_8 (DSPHI(ac)), VL4_8 (DSPLO(ac)))
1054           - ((uint64_t) VL4_8 (GPR[rs]) * (uint64_t) VL4_8 (GPR[rt])));
1055   DSPLO(ac) = EXTEND32 (temp);
1056   DSPHI(ac) = EXTEND32 (VH4_8 (temp));
1057   if (ac == 0)
1058     TRACE_ALU_RESULT2 (HI, LO);
1059 }
1060
1061 :function:::void:do_mthi:int rs
1062 {
1063   check_mt_hilo (SD_, HIHISTORY);
1064   HI = GPR[rs];
1065 }
1066
1067 :function:::void:do_dsp_mthi:int ac, int rs
1068 {
1069   if (ac == 0)
1070     check_mt_hilo (SD_, HIHISTORY);
1071   DSPHI(ac) = GPR[rs];
1072 }
1073
1074 :function:::void:do_mtlo:int rs
1075 {
1076   check_mt_hilo (SD_, LOHISTORY);
1077   LO = GPR[rs];
1078 }
1079
1080 :function:::void:do_dsp_mtlo:int ac, int rs
1081 {
1082   if (ac == 0)
1083     check_mt_hilo (SD_, LOHISTORY);
1084   DSPLO(ac) = GPR[rs];
1085 }
1086
1087 :function:::void:do_mul:int rd, int rs, int rt
1088 {
1089   int64_t prod;
1090   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1091     Unpredictable ();
1092   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1093   prod = (((int64_t)(int32_t) GPR[rs])
1094           * ((int64_t)(int32_t) GPR[rt]));
1095   GPR[rd] = EXTEND32 (VL4_8 (prod));
1096   TRACE_ALU_RESULT (GPR[rd]);
1097 }
1098
1099 :function:::void:do_dsp_mult:int ac, int rs, int rt
1100 {
1101   int64_t prod;
1102   if (ac == 0)
1103     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1104   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1105     Unpredictable ();
1106   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1107   prod = ((int64_t)(int32_t) GPR[rs])
1108           * ((int64_t)(int32_t) GPR[rt]);
1109   DSPLO(ac) = EXTEND32 (VL4_8 (prod));
1110   DSPHI(ac) = EXTEND32 (VH4_8 (prod));
1111   if (ac == 0)
1112   {
1113     ACX = 0;  /* SmartMIPS */
1114     TRACE_ALU_RESULT2 (HI, LO);
1115   }
1116 }
1117
1118 :function:::void:do_dsp_multu:int ac, int rs, int rt
1119 {
1120   uint64_t prod;
1121   if (ac == 0)
1122     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1123   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1124     Unpredictable ();
1125   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1126   prod = ((uint64_t)(uint32_t) GPR[rs])
1127           * ((uint64_t)(uint32_t) GPR[rt]);
1128   DSPLO(ac) = EXTEND32 (VL4_8 (prod));
1129   DSPHI(ac) = EXTEND32 (VH4_8 (prod));
1130   if (ac == 0)
1131     TRACE_ALU_RESULT2 (HI, LO);
1132 }
1133
1134 :function:::void:do_pref:int hint, int insn_offset, int insn_base
1135 {
1136   address_word base = GPR[insn_base];
1137   address_word offset = EXTEND16 (insn_offset);
1138   {
1139     address_word vaddr = loadstore_ea (SD_, base, offset);
1140     address_word paddr = vaddr;
1141     /* Prefetch (paddr, vaddr, isDATA, hint); */
1142   }
1143 }
1144
1145 :function:::void:do_sc:int rt, int offsetarg, int basereg, address_word instruction_0, int store_ll_bit
1146 {
1147   uint32_t instruction = instruction_0;
1148   address_word base = GPR[basereg];
1149   address_word offset = EXTEND16 (offsetarg);
1150   {
1151     address_word vaddr = loadstore_ea (SD_, base, offset);
1152     address_word paddr = vaddr;
1153
1154     if ((vaddr & 3) != 0)
1155       {
1156         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
1157                          sim_core_unaligned_signal);
1158       }
1159     else
1160       {
1161         uint64_t memval = 0;
1162         uint64_t memval1 = 0;
1163         uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1164         address_word reverseendian =
1165           (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1166         address_word bigendiancpu =
1167           (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1168         unsigned int byte;
1169         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1170         byte = ((vaddr & mask) ^ bigendiancpu);
1171         memval = ((uint64_t) GPR[rt] << (8 * byte));
1172         if (LLBIT)
1173           StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
1174                         isREAL);
1175         if (store_ll_bit)
1176           GPR[rt] = LLBIT;
1177       }
1178   }
1179 }
1180
1181 :function:::void:do_scd:int rt, int roffset, int rbase, int store_ll_bit
1182 {
1183   address_word base = GPR[rbase];
1184   address_word offset = EXTEND16 (roffset);
1185   {
1186     address_word vaddr = loadstore_ea (SD_, base, offset);
1187     address_word paddr = vaddr;
1188
1189     if ((vaddr & 7) != 0)
1190       {
1191         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer,
1192                          sim_core_unaligned_signal);
1193       }
1194     else
1195       {
1196         uint64_t memval = 0;
1197         uint64_t memval1 = 0;
1198         memval = GPR[rt];
1199         if (LLBIT)
1200           StoreMemory (AccessLength_DOUBLEWORD, memval, memval1, paddr, vaddr,
1201                        isREAL);
1202         if (store_ll_bit)
1203           GPR[rt] = LLBIT;
1204       }
1205   }
1206 }
1207
1208 :function:::void:do_sub:int rs, int rt, int rd
1209 {
1210   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1211     Unpredictable ();
1212   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1213   {
1214     ALU32_BEGIN (GPR[rs]);
1215     ALU32_SUB (GPR[rt]);
1216     ALU32_END (GPR[rd]);   /* This checks for overflow.  */
1217   }
1218   TRACE_ALU_RESULT (GPR[rd]);
1219 }
1220
1221 :function:::void:do_sw:int rt, int offset, int base
1222 {
1223   do_store (SD_, AccessLength_WORD, GPR[base], EXTEND16 (offset), GPR[rt]);
1224 }
1225
1226 :function:::void:do_teq:int rs, int rt, address_word instruction_0
1227 {
1228   if ((signed_word) GPR[rs] == (signed_word) GPR[rt])
1229     SignalException (Trap, instruction_0);
1230 }
1231
1232 :function:::void:do_teqi:int rs, int immediate, address_word instruction_0
1233 {
1234   if ((signed_word) GPR[rs] == (signed_word) EXTEND16 (immediate))
1235     SignalException (Trap, instruction_0);
1236 }
1237
1238 :function:::void:do_tge:int rs, int rt, address_word instruction_0
1239 {
1240   if ((signed_word) GPR[rs] >= (signed_word) GPR[rt])
1241     SignalException (Trap, instruction_0);
1242 }
1243
1244 :function:::void:do_tgei:int rs, int immediate, address_word instruction_0
1245 {
1246   if ((signed_word) GPR[rs] >= (signed_word) EXTEND16 (immediate))
1247     SignalException (Trap, instruction_0);
1248 }
1249
1250 :function:::void:do_tgeiu:int rs, int immediate, address_word instruction_0
1251 {
1252   if ((unsigned_word) GPR[rs] >= (unsigned_word) EXTEND16 (immediate))
1253     SignalException (Trap, instruction_0);
1254 }
1255
1256 :function:::void:do_tgeu:int rs ,int rt, address_word instruction_0
1257 {
1258   if ((unsigned_word) GPR[rs] >= (unsigned_word) GPR[rt])
1259     SignalException (Trap, instruction_0);
1260 }
1261
1262 :function:::void:do_tlt:int rs, int rt, address_word instruction_0
1263 {
1264   if ((signed_word) GPR[rs] < (signed_word) GPR[rt])
1265     SignalException (Trap, instruction_0);
1266 }
1267
1268 :function:::void:do_tlti:int rs, int immediate, address_word instruction_0
1269 {
1270   if ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate))
1271     SignalException (Trap, instruction_0);
1272 }
1273
1274 :function:::void:do_tltiu:int rs, int immediate, address_word instruction_0
1275 {
1276   if ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate))
1277     SignalException (Trap, instruction_0);
1278 }
1279
1280 :function:::void:do_tltu:int rs, int rt, address_word instruction_0
1281 {
1282   if ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt])
1283     SignalException (Trap, instruction_0);
1284 }
1285
1286 :function:::void:do_tne:int rs, int rt, address_word instruction_0
1287 {
1288   if ((signed_word) GPR[rs] != (signed_word) GPR[rt])
1289     SignalException (Trap, instruction_0);
1290 }
1291
1292 :function:::void:do_tnei:int rs, int immediate, address_word instruction_0
1293 {
1294   if ((signed_word) GPR[rs] != (signed_word) EXTEND16 (immediate))
1295     SignalException (Trap, instruction_0);
1296 }
1297
1298 :function:::void:do_abs_fmt:int fmt, int fd, int fs, address_word instruction_0
1299 {
1300   check_fpu (SD_);
1301   check_fmt_p (SD_, fmt, instruction_0);
1302   StoreFPR (fd, fmt, AbsoluteValue (ValueFPR (fs, fmt), fmt));
1303 }
1304
1305 :function:::void:do_add_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1306 {
1307   check_fpu (SD_);
1308   check_fmt_p (SD_, fmt, instruction_0);
1309   StoreFPR (fd, fmt, Add (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1310 }
1311
1312 :function:::void:do_alnv_ps:int fd, int fs, int ft, int rs, address_word instruction_0
1313 {
1314   uint64_t fsx;
1315   uint64_t ftx;
1316   uint64_t fdx;
1317   check_fpu (SD_);
1318   check_u64 (SD_, instruction_0);
1319   fsx = ValueFPR (fs, fmt_ps);
1320   if ((GPR[rs] & 0x3) != 0)
1321     Unpredictable ();
1322   if ((GPR[rs] & 0x4) == 0)
1323     fdx = fsx;
1324   else
1325     {
1326       ftx = ValueFPR (ft, fmt_ps);
1327       if (BigEndianCPU)
1328         fdx = PackPS (PSLower (fsx), PSUpper (ftx));
1329       else
1330         fdx = PackPS (PSLower (ftx), PSUpper (fsx));
1331     }
1332   StoreFPR (fd, fmt_ps, fdx);
1333 }
1334
1335 :function:::void:do_c_cond_fmt:int cond, int fmt, int cc, int fs, int ft, address_word instruction_0
1336 {
1337   check_fpu (SD_);
1338   check_fmt_p (SD_, fmt, instruction_0);
1339   Compare (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt, cond, cc);
1340   TRACE_ALU_RESULT (ValueFCR (31));
1341 }
1342
1343 :function:::void:do_ceil_fmt:int type, int fmt, int fd, int fs, address_word instruction_0
1344 {
1345   check_fpu (SD_);
1346   check_fmt_p (SD_, fmt, instruction_0);
1347   StoreFPR (fd, type, Convert (FP_RM_TOPINF, ValueFPR (fs, fmt), fmt,
1348             type));
1349 }
1350
1351 :function:::void:do_cfc1:int rt, int fs
1352 {
1353   check_fpu (SD_);
1354   if (fs == 0 || fs == 25 || fs == 26 || fs == 28 || fs == 31)
1355     {
1356       unsigned_word  fcr = ValueFCR (fs);
1357       TRACE_ALU_INPUT1 (fcr);
1358       GPR[rt] = fcr;
1359     }
1360   /* else NOP */
1361   TRACE_ALU_RESULT (GPR[rt]);
1362 }
1363
1364 :function:::void:do_ctc1:int rt, int fs
1365 {
1366   check_fpu (SD_);
1367   TRACE_ALU_INPUT1 (GPR[rt]);
1368   if (fs == 25 || fs == 26 || fs == 28 || fs == 31)
1369       StoreFCR (fs, GPR[rt]);
1370   /* else NOP */
1371 }
1372
1373 :function:::void:do_cvt_d_fmt:int fmt, int fd, int fs, address_word instruction_0
1374 {
1375   check_fpu (SD_);
1376   if ((fmt == fmt_double) | 0)
1377     SignalException (ReservedInstruction, instruction_0);
1378   StoreFPR (fd, fmt_double, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1379             fmt_double));
1380 }
1381
1382 :function:::void:do_cvt_l_fmt:int fmt, int fd, int fs, address_word instruction_0
1383 {
1384   check_fpu (SD_);
1385   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
1386     SignalException (ReservedInstruction, instruction_0);
1387   StoreFPR (fd, fmt_long, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1388             fmt_long));
1389 }
1390
1391 :function:::void:do_cvt_ps_s:int fd, int fs, int ft, address_word instruction_0
1392 {
1393   check_fpu (SD_);
1394   check_u64 (SD_, instruction_0);
1395   StoreFPR (fd, fmt_ps, PackPS (ValueFPR (fs, fmt_single),
1396                                 ValueFPR (ft, fmt_single)));
1397 }
1398
1399 :function:::void:do_cvt_s_fmt:int fmt, int fd, int fs, address_word instruction_0
1400 {
1401   check_fpu (SD_);
1402   if ((fmt == fmt_single) | 0)
1403     SignalException (ReservedInstruction, instruction_0);
1404   StoreFPR (fd, fmt_single, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1405             fmt_single));
1406 }
1407
1408 :function:::void:do_cvt_s_pl:int fd, int fs, address_word instruction_0
1409 {
1410   check_fpu (SD_);
1411   check_u64 (SD_, instruction_0);
1412   StoreFPR (fd, fmt_single, PSLower (ValueFPR (fs, fmt_ps)));
1413 }
1414
1415 :function:::void:do_cvt_s_pu:int fd, int fs, address_word instruction_0
1416 {
1417   check_fpu (SD_);
1418   check_u64 (SD_, instruction_0);
1419   StoreFPR (fd, fmt_single, PSUpper (ValueFPR (fs, fmt_ps)));
1420 }
1421
1422 :function:::void:do_cvt_w_fmt:int fmt, int fd, int fs, address_word instruction_0
1423 {
1424   check_fpu (SD_);
1425   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
1426     SignalException (ReservedInstruction, instruction_0);
1427   StoreFPR (fd, fmt_word, Convert (GETRM (), ValueFPR (fs, fmt), fmt,
1428             fmt_word));
1429 }
1430
1431 :function:::void:do_div_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1432 {
1433   check_fpu (SD_);
1434   StoreFPR (fd, fmt, Divide (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1435 }
1436
1437 :function:::void:do_dmfc1b:int rt, int fs
1438 *mipsIV:
1439 *mipsV:
1440 *mips64:
1441 *mips64r2:
1442 *mips64r6:
1443 *vr4100:
1444 *vr5000:
1445 *r3900:
1446 *micromips64:
1447 {
1448   if (SizeFGR () == 64)
1449     GPR[rt] = FGR[fs];
1450   else if ((fs & 0x1) == 0)
1451     GPR[rt] = SET64HI (FGR[fs+1]) | FGR[fs];
1452   else
1453     GPR[rt] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
1454   TRACE_ALU_RESULT (GPR[rt]);
1455 }
1456
1457 :function:::void:do_dmtc1b:int rt, int fs
1458 {
1459   if (SizeFGR () == 64)
1460     StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
1461   else if ((fs & 0x1) == 0)
1462     StoreFPR (fs, fmt_uninterpreted_64, GPR[rt]);
1463   else
1464     Unpredictable ();
1465 }
1466
1467 :function:::void:do_floor_fmt:int type, int fmt, int fd, int fs
1468 {
1469   check_fpu (SD_);
1470   StoreFPR (fd, type, Convert (FP_RM_TOMINF, ValueFPR (fs, fmt), fmt,
1471             type));
1472 }
1473
1474 :function:::void:do_luxc1_32:int fd, int rindex, int rbase
1475 *mips32r2:
1476 *micromips32:
1477 {
1478   address_word base = GPR[rbase];
1479   address_word index = GPR[rindex];
1480   address_word vaddr = base + index;
1481   check_fpu (SD_);
1482   if (SizeFGR () != 64)
1483     Unpredictable ();
1484   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1485   if ((vaddr & 0x7) != 0)
1486     index -= (vaddr & 0x7);
1487   COP_LD (1, fd, do_load_double (SD_, base, index));
1488 }
1489
1490 :function:::void:do_luxc1_64:int fd, int rindex, int rbase
1491 {
1492   address_word base = GPR[rbase];
1493   address_word index = GPR[rindex];
1494   address_word vaddr = base + index;
1495   if (SizeFGR () != 64)
1496     Unpredictable ();
1497   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1498   if ((vaddr & 0x7) != 0)
1499     index -= (vaddr & 0x7);
1500   COP_LD (1, fd, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
1501
1502 }
1503
1504 :function:::void:do_lwc1:int ft, int offset, int base
1505 {
1506   check_fpu (SD_);
1507   COP_LW (1, ft, do_load (SD_, AccessLength_WORD, GPR[base],
1508                           EXTEND16 (offset)));
1509 }
1510
1511 :function:::void:do_lwxc1:int fd, int index, int base, address_word instruction_0
1512 {
1513   check_fpu (SD_);
1514   check_u64 (SD_, instruction_0);
1515   COP_LW (1, fd, do_load (SD_, AccessLength_WORD, GPR[base], GPR[index]));
1516 }
1517
1518 :function:::void:do_madd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1519 {
1520   check_fpu (SD_);
1521   check_u64 (SD_, instruction_0);
1522   check_fmt_p (SD_, fmt, instruction_0);
1523   StoreFPR (fd, fmt, MultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1524                                   ValueFPR (fr, fmt), fmt));
1525 }
1526
1527 :function:::void:do_mfc1b:int rt, int fs
1528 {
1529   check_fpu (SD_);
1530   GPR[rt] = EXTEND32 (FGR[fs]);
1531   TRACE_ALU_RESULT (GPR[rt]);
1532 }
1533
1534 :function:::void:do_mov_fmt:int fmt, int fd, int fs, address_word instruction_0
1535 {
1536   check_fpu (SD_);
1537   check_fmt_p (SD_, fmt, instruction_0);
1538   StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1539 }
1540
1541 :function:::void:do_movtf:int tf, int rd, int rs, int cc
1542 {
1543   check_fpu (SD_);
1544   if (GETFCC(cc) == tf)
1545     GPR[rd] = GPR[rs];
1546 }
1547
1548 :function:::void:do_movtf_fmt:int tf, int fmt, int fd, int fs, int cc
1549 {
1550   check_fpu (SD_);
1551   if (fmt != fmt_ps)
1552   {
1553     if (GETFCC(cc) == tf)
1554       StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1555     else
1556       StoreFPR (fd, fmt, ValueFPR (fd, fmt));   /* set fmt */
1557   }
1558   else
1559   {
1560     uint64_t fdx;
1561     fdx = PackPS (PSUpper (ValueFPR ((GETFCC (cc+1) == tf) ? fs : fd,
1562                                       fmt_ps)),
1563                   PSLower (ValueFPR ((GETFCC (cc+0) == tf) ? fs : fd,
1564                                       fmt_ps)));
1565     StoreFPR (fd, fmt_ps, fdx);
1566   }
1567 }
1568
1569 :function:::void:do_movn_fmt:int fmt, int fd, int fs, int rt
1570 {
1571   check_fpu (SD_);
1572   if (GPR[rt] != 0)
1573     StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1574   else
1575     StoreFPR (fd, fmt, ValueFPR (fd, fmt));
1576 }
1577
1578 :function:::void:do_movz_fmt:int fmt, int fd, int fs, int rt
1579 {
1580   check_fpu (SD_);
1581   if (GPR[rt] == 0)
1582     StoreFPR (fd, fmt, ValueFPR (fs, fmt));
1583   else
1584     StoreFPR (fd, fmt, ValueFPR (fd, fmt));
1585 }
1586
1587 :function:::void:do_msub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1588 {
1589   check_fpu (SD_);
1590   check_u64 (SD_, instruction_0);
1591   check_fmt_p (SD_, fmt, instruction_0);
1592   StoreFPR (fd, fmt, MultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1593                                   ValueFPR (fr, fmt), fmt));
1594 }
1595
1596 :function:::void:do_mtc1b:int rt, int fs
1597 {
1598   check_fpu (SD_);
1599   StoreFPR (fs, fmt_uninterpreted_32, VL4_8 (GPR[rt]));
1600 }
1601
1602 :function:::void:do_mul_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1603 {
1604   check_fpu (SD_);
1605   check_fmt_p (SD_, fmt, instruction_0);
1606   StoreFPR (fd, fmt, Multiply (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1607 }
1608
1609 :function:::void:do_neg_fmt:int fmt, int fd, int fs, address_word instruction_0
1610 {
1611   check_fpu (SD_);
1612   check_fmt_p (SD_, fmt, instruction_0);
1613   StoreFPR (fd, fmt, Negate (ValueFPR (fs, fmt), fmt));
1614 }
1615
1616 :function:::void:do_nmadd_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1617 {
1618   check_fpu (SD_);
1619   check_u64 (SD_, instruction_0);
1620   check_fmt_p (SD_, fmt, instruction_0);
1621   StoreFPR (fd, fmt, NegMultiplyAdd (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1622                                      ValueFPR (fr, fmt), fmt));
1623 }
1624
1625 :function:::void:do_nmsub_fmt:int fmt, int fd, int fr, int fs, int ft, address_word instruction_0
1626 {
1627   check_fpu (SD_);
1628   check_u64 (SD_, instruction_0);
1629   check_fmt_p (SD_, fmt, instruction_0);
1630   StoreFPR (fd, fmt, NegMultiplySub (ValueFPR (fs, fmt), ValueFPR (ft, fmt),
1631                                      ValueFPR (fr, fmt), fmt));
1632 }
1633
1634 :function:::void:do_pll_ps:int fd, int fs, int ft, address_word instruction_0
1635 {
1636   check_fpu (SD_);
1637   check_u64 (SD_, instruction_0);
1638   StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
1639                                 PSLower (ValueFPR (ft, fmt_ps))));
1640 }
1641
1642 :function:::void:do_plu_ps:int fd, int fs, int ft, address_word instruction_0
1643 {
1644   check_fpu (SD_);
1645   check_u64 (SD_, instruction_0);
1646   StoreFPR (fd, fmt_ps, PackPS (PSLower (ValueFPR (fs, fmt_ps)),
1647                                 PSUpper (ValueFPR (ft, fmt_ps))));
1648 }
1649
1650 :function:::void:do_pul_ps:int fd, int fs, int ft, address_word instruction_0
1651 {
1652   check_fpu (SD_);
1653   check_u64 (SD_, instruction_0);
1654   StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
1655                                 PSLower (ValueFPR (ft, fmt_ps))));
1656 }
1657
1658 :function:::void:do_puu_ps:int fd, int fs, int ft, address_word instruction_0
1659 {
1660   check_fpu (SD_);
1661   check_u64 (SD_, instruction_0);
1662   StoreFPR (fd, fmt_ps, PackPS (PSUpper (ValueFPR (fs, fmt_ps)),
1663                                 PSUpper (ValueFPR (ft, fmt_ps))));
1664 }
1665
1666 :function:::void:do_recip_fmt:int fmt, int fd, int fs
1667 {
1668   check_fpu (SD_);
1669   StoreFPR (fd, fmt, Recip (ValueFPR (fs, fmt), fmt));
1670 }
1671
1672 :function:::void:do_round_fmt:int type, int fmt, int fd, int fs
1673 {
1674   check_fpu (SD_);
1675   StoreFPR (fd, type, Convert (FP_RM_NEAREST, ValueFPR (fs, fmt), fmt,
1676             type));
1677 }
1678
1679 :function:::void:do_rsqrt_fmt:int fmt, int fd, int fs
1680 {
1681   check_fpu (SD_);
1682   StoreFPR (fd, fmt, RSquareRoot (ValueFPR (fs, fmt), fmt));
1683 }
1684
1685 :function:::void:do_prefx:int hint, int rindex, int rbase
1686 {
1687   address_word base = GPR[rbase];
1688   address_word index = GPR[rindex];
1689   {
1690     address_word vaddr = loadstore_ea (SD_, base, index);
1691     address_word paddr = vaddr;
1692     /* Prefetch (paddr, vaddr, isDATA, hint); */
1693   }
1694 }
1695
1696 :function:::void:do_sdc1:int ft, int offset, int base
1697 *mipsII:
1698 *mips32:
1699 *mips32r2:
1700 *mips32r6:
1701 *micromips32:
1702 {
1703   check_fpu (SD_);
1704   do_store_double (SD_, GPR[base], EXTEND16 (offset), COP_SD (1, ft));
1705 }
1706
1707 :function:::void:do_suxc1_32:int fs, int rindex, int rbase
1708 *mips32r2:
1709 *micromips32:
1710 {
1711   address_word base = GPR[rbase];
1712   address_word index = GPR[rindex];
1713   address_word vaddr = base + index;
1714   check_fpu (SD_);
1715   if (SizeFGR () != 64)
1716     Unpredictable ();
1717   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1718   if ((vaddr & 0x7) != 0)
1719     index -= (vaddr & 0x7);
1720   do_store_double (SD_, base, index, COP_SD (1, fs));
1721 }
1722
1723 :function:::void:do_suxc1_64:int fs, int rindex, int rbase
1724 {
1725   address_word base = GPR[rbase];
1726   address_word index = GPR[rindex];
1727   address_word vaddr = base + index;
1728   if (SizeFGR () != 64)
1729     Unpredictable ();
1730   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
1731   if ((vaddr & 0x7) != 0)
1732     index -= (vaddr & 0x7);
1733   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, fs));
1734 }
1735
1736 :function:::void:do_sqrt_fmt:int fmt, int fd, int fs
1737 {
1738   check_fpu (SD_);
1739   StoreFPR (fd, fmt,  (SquareRoot (ValueFPR (fs, fmt), fmt)));
1740 }
1741
1742 :function:::void:do_sub_fmt:int fmt, int fd, int fs, int ft, address_word instruction_0
1743 {
1744   check_fpu (SD_);
1745   check_fmt_p (SD_, fmt, instruction_0);
1746   StoreFPR (fd, fmt, Sub (ValueFPR (fs, fmt), ValueFPR (ft, fmt), fmt));
1747 }
1748
1749 :function:::void:do_swc1:int ft, int roffset, int rbase, address_word instruction_0
1750 {
1751   address_word base = GPR[rbase];
1752   address_word offset = EXTEND16 (roffset);
1753   check_fpu (SD_);
1754   {
1755     address_word vaddr = loadstore_ea (SD_, base, offset);
1756     address_word paddr = vaddr;
1757
1758     if ((vaddr & 3) != 0)
1759       {
1760         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr,
1761                          write_transfer, sim_core_unaligned_signal);
1762       }
1763     else
1764       {
1765         uword64 memval = 0;
1766         uword64 memval1 = 0;
1767         uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1768         address_word reverseendian =
1769           (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1770         address_word bigendiancpu =
1771           (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1772         unsigned int byte;
1773         paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1774         byte = ((vaddr & mask) ^ bigendiancpu);
1775         memval = (((uword64)COP_SW(1, ft)) << (8 * byte));
1776         StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr, isREAL);
1777       }
1778   }
1779 }
1780
1781 :function:::void:do_swxc1:int fs, int rindex, int rbase, address_word instruction_0
1782 {
1783   address_word base = GPR[rbase];
1784   address_word index = GPR[rindex];
1785   check_fpu (SD_);
1786   check_u64 (SD_, instruction_0);
1787     {
1788       address_word vaddr = loadstore_ea (SD_, base, index);
1789       address_word paddr = vaddr;
1790
1791       if ((vaddr & 3) != 0)
1792         {
1793           SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer,
1794                            sim_core_unaligned_signal);
1795         }
1796       else
1797         {
1798           uint64_t memval = 0;
1799           uint64_t memval1 = 0;
1800           uint64_t mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1801           address_word reverseendian =
1802             (ReverseEndian ? (mask ^ AccessLength_WORD) : 0);
1803           address_word bigendiancpu =
1804             (BigEndianCPU ? (mask ^ AccessLength_WORD) : 0);
1805           unsigned int byte;
1806           paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1807           byte = ((vaddr & mask) ^ bigendiancpu);
1808           memval = (((uint64_t)COP_SW(1,fs)) << (8 * byte));
1809           StoreMemory (AccessLength_WORD, memval, memval1, paddr, vaddr,
1810                        isREAL);
1811         }
1812   }
1813 }
1814
1815 :function:::void:do_trunc_fmt:int type, int fmt, int fd, int fs
1816 {
1817   check_fpu (SD_);
1818   StoreFPR (fd, type, Convert (FP_RM_TOZERO, ValueFPR (fs, fmt), fmt,
1819             type));
1820 }
1821
1822 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
1823 "add r<RD>, r<RS>, r<RT>"
1824 *mipsI:
1825 *mipsII:
1826 *mipsIII:
1827 *mipsIV:
1828 *mipsV:
1829 *mips32:
1830 *mips32r2:
1831 *mips32r6:
1832 *mips64:
1833 *mips64r2:
1834 *mips64r6:
1835 *vr4100:
1836 *vr5000:
1837 *r3900:
1838 {
1839   do_add (SD_, RS, RT, RD);
1840 }
1841
1842
1843
1844 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
1845 "addi r<RT>, r<RS>, <IMMEDIATE>"
1846 *mipsI:
1847 *mipsII:
1848 *mipsIII:
1849 *mipsIV:
1850 *mipsV:
1851 *mips32:
1852 *mips32r2:
1853 *mips64:
1854 *mips64r2:
1855 *vr4100:
1856 *vr5000:
1857 *r3900:
1858 {
1859   do_addi (SD_, RS, RT, IMMEDIATE);
1860 }
1861
1862
1863
1864 :function:::void:do_addiu:int rs, int rt, uint16_t immediate
1865 {
1866   if (NotWordValue (GPR[rs]))
1867     Unpredictable ();
1868   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1869   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
1870   TRACE_ALU_RESULT (GPR[rt]);
1871 }
1872
1873 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
1874 "addiu r<RT>, r<RS>, <IMMEDIATE>"
1875 *mipsI:
1876 *mipsII:
1877 *mipsIII:
1878 *mipsIV:
1879 *mipsV:
1880 *mips32:
1881 *mips32r2:
1882 *mips32r6:
1883 *mips64:
1884 *mips64r2:
1885 *mips64r6:
1886 *vr4100:
1887 *vr5000:
1888 *r3900:
1889 {
1890   do_addiu (SD_, RS, RT, IMMEDIATE);
1891 }
1892
1893
1894
1895 :function:::void:do_addu:int rs, int rt, int rd
1896 {
1897   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
1898     Unpredictable ();
1899   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1900   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
1901   TRACE_ALU_RESULT (GPR[rd]);
1902 }
1903
1904 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
1905 "addu r<RD>, r<RS>, r<RT>"
1906 *mipsI:
1907 *mipsII:
1908 *mipsIII:
1909 *mipsIV:
1910 *mipsV:
1911 *mips32:
1912 *mips32r2:
1913 *mips32r6:
1914 *mips64:
1915 *mips64r2:
1916 *mips64r6:
1917 *vr4100:
1918 *vr5000:
1919 *r3900:
1920 {
1921   do_addu (SD_, RS, RT, RD);
1922 }
1923
1924
1925
1926 :function:::void:do_and:int rs, int rt, int rd
1927 {
1928   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1929   GPR[rd] = GPR[rs] & GPR[rt];
1930   TRACE_ALU_RESULT (GPR[rd]);
1931 }
1932
1933 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
1934 "and r<RD>, r<RS>, r<RT>"
1935 *mipsI:
1936 *mipsII:
1937 *mipsIII:
1938 *mipsIV:
1939 *mipsV:
1940 *mips32:
1941 *mips32r2:
1942 *mips32r6:
1943 *mips64:
1944 *mips64r2:
1945 *mips64r6:
1946 *vr4100:
1947 *vr5000:
1948 *r3900:
1949 {
1950   do_and (SD_, RS, RT, RD);
1951 }
1952
1953
1954
1955 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
1956 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
1957 *mipsI:
1958 *mipsII:
1959 *mipsIII:
1960 *mipsIV:
1961 *mipsV:
1962 *mips32:
1963 *mips32r2:
1964 *mips32r6:
1965 *mips64:
1966 *mips64r2:
1967 *mips64r6:
1968 *vr4100:
1969 *vr5000:
1970 *r3900:
1971 {
1972   do_andi (SD_,RS, RT, IMMEDIATE);
1973 }
1974
1975
1976
1977 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
1978 "beq r<RS>, r<RT>, <OFFSET>"
1979 *mipsI:
1980 *mipsII:
1981 *mipsIII:
1982 *mipsIV:
1983 *mipsV:
1984 *mips32:
1985 *mips32r2:
1986 *mips64:
1987 *mips64r2:
1988 *vr4100:
1989 *vr5000:
1990 *r3900:
1991 {
1992   address_word offset = EXTEND16 (OFFSET) << 2;
1993   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
1994     {
1995       DELAY_SLOT (NIA + offset);
1996     }
1997 }
1998
1999
2000 000100,5.RS,5.RT,16.OFFSET:R6:32::BEQ
2001 "beq r<RS>, r<RT>, <OFFSET>"
2002 *mips32r6:
2003 *mips64r6:
2004 {
2005   address_word offset = EXTEND16 (OFFSET) << 2;
2006   if (GPR[RS] == GPR[RT])
2007     DELAY_SLOT (NIA  + offset);
2008   else
2009     FORBIDDEN_SLOT ();
2010 }
2011
2012 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
2013 "beql r<RS>, r<RT>, <OFFSET>"
2014 *mipsII:
2015 *mipsIII:
2016 *mipsIV:
2017 *mipsV:
2018 *mips32:
2019 *mips32r2:
2020 *mips64:
2021 *mips64r2:
2022 *vr4100:
2023 *vr5000:
2024 *r3900:
2025 {
2026   address_word offset = EXTEND16 (OFFSET) << 2;
2027   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2028     {
2029       DELAY_SLOT (NIA + offset);
2030     }
2031   else
2032     NULLIFY_NEXT_INSTRUCTION ();
2033 }
2034
2035
2036
2037 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
2038 "bgez r<RS>, <OFFSET>"
2039 *mipsI:
2040 *mipsII:
2041 *mipsIII:
2042 *mipsIV:
2043 *mipsV:
2044 *mips32:
2045 *mips32r2:
2046 *mips32r6:
2047 *mips64:
2048 *mips64r2:
2049 *mips64r6:
2050 *vr4100:
2051 *vr5000:
2052 *r3900:
2053 {
2054   address_word offset = EXTEND16 (OFFSET) << 2;
2055   if ((signed_word) GPR[RS] >= 0)
2056     {
2057       DELAY_SLOT (NIA + offset);
2058     }
2059 }
2060
2061
2062
2063 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
2064 "bgezal r<RS>, <OFFSET>"
2065 *mipsI:
2066 *mipsII:
2067 *mipsIII:
2068 *mipsIV:
2069 *mipsV:
2070 *mips32:
2071 *mips32r2:
2072 *mips64:
2073 *mips64r2:
2074 *vr4100:
2075 *vr5000:
2076 *r3900:
2077 {
2078   address_word offset = EXTEND16 (OFFSET) << 2;
2079   if (RS == 31)
2080     Unpredictable ();
2081   RA = (CIA + 8);
2082   if ((signed_word) GPR[RS] >= 0)
2083     {
2084       DELAY_SLOT (NIA + offset);
2085     }
2086 }
2087
2088 000001,00000,10001,16.OFFSET:REGIMM:32::BAL
2089 "bal <OFFSET>"
2090 *mips32r6:
2091 *mips64r6:
2092 {
2093   address_word offset = EXTEND16 (OFFSET) << 2;
2094   RA = (CIA + 8);
2095   DELAY_SLOT (NIA + offset);
2096 }
2097
2098 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
2099 "bgezall r<RS>, <OFFSET>"
2100 *mipsII:
2101 *mipsIII:
2102 *mipsIV:
2103 *mipsV:
2104 *mips32:
2105 *mips32r2:
2106 *mips64:
2107 *mips64r2:
2108 *vr4100:
2109 *vr5000:
2110 *r3900:
2111 {
2112   address_word offset = EXTEND16 (OFFSET) << 2;
2113   if (RS == 31)
2114     Unpredictable ();
2115   RA = (CIA + 8);
2116   /* NOTE: The branch occurs AFTER the next instruction has been
2117      executed */
2118   if ((signed_word) GPR[RS] >= 0)
2119     {
2120       DELAY_SLOT (NIA + offset);
2121     }
2122   else
2123     NULLIFY_NEXT_INSTRUCTION ();
2124 }
2125
2126
2127
2128 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
2129 "bgezl r<RS>, <OFFSET>"
2130 *mipsII:
2131 *mipsIII:
2132 *mipsIV:
2133 *mipsV:
2134 *mips32:
2135 *mips32r2:
2136 *mips64:
2137 *mips64r2:
2138 *vr4100:
2139 *vr5000:
2140 *r3900:
2141 {
2142   address_word offset = EXTEND16 (OFFSET) << 2;
2143   if ((signed_word) GPR[RS] >= 0)
2144     {
2145       DELAY_SLOT (NIA + offset);
2146     }
2147   else
2148     NULLIFY_NEXT_INSTRUCTION ();
2149 }
2150
2151
2152
2153 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
2154 "bgtz r<RS>, <OFFSET>"
2155 *mipsI:
2156 *mipsII:
2157 *mipsIII:
2158 *mipsIV:
2159 *mipsV:
2160 *mips32:
2161 *mips32r2:
2162 *mips32r6:
2163 *mips64:
2164 *mips64r2:
2165 *mips64r6:
2166 *vr4100:
2167 *vr5000:
2168 *r3900:
2169 {
2170   address_word offset = EXTEND16 (OFFSET) << 2;
2171   if ((signed_word) GPR[RS] > 0)
2172     {
2173       DELAY_SLOT (NIA + offset);
2174     }
2175 }
2176
2177
2178
2179 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
2180 "bgtzl r<RS>, <OFFSET>"
2181 *mipsII:
2182 *mipsIII:
2183 *mipsIV:
2184 *mipsV:
2185 *mips32:
2186 *mips32r2:
2187 *mips64:
2188 *mips64r2:
2189 *vr4100:
2190 *vr5000:
2191 *r3900:
2192 {
2193   address_word offset = EXTEND16 (OFFSET) << 2;
2194   /* NOTE: The branch occurs AFTER the next instruction has been
2195      executed */
2196   if ((signed_word) GPR[RS] > 0)
2197     {
2198       DELAY_SLOT (NIA + offset);
2199     }
2200   else
2201     NULLIFY_NEXT_INSTRUCTION ();
2202 }
2203
2204
2205
2206 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
2207 "blez r<RS>, <OFFSET>"
2208 *mipsI:
2209 *mipsII:
2210 *mipsIII:
2211 *mipsIV:
2212 *mipsV:
2213 *mips32:
2214 *mips32r2:
2215 *mips32r6:
2216 *mips64:
2217 *mips64r2:
2218 *mips64r6:
2219 *vr4100:
2220 *vr5000:
2221 *r3900:
2222 {
2223   address_word offset = EXTEND16 (OFFSET) << 2;
2224   /* NOTE: The branch occurs AFTER the next instruction has been
2225      executed */
2226   if ((signed_word) GPR[RS] <= 0)
2227     {
2228       DELAY_SLOT (NIA + offset);
2229     }
2230 }
2231
2232
2233
2234 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
2235 "bgezl r<RS>, <OFFSET>"
2236 *mipsII:
2237 *mipsIII:
2238 *mipsIV:
2239 *mipsV:
2240 *mips32:
2241 *mips32r2:
2242 *mips64:
2243 *mips64r2:
2244 *vr4100:
2245 *vr5000:
2246 *r3900:
2247 {
2248   address_word offset = EXTEND16 (OFFSET) << 2;
2249   if ((signed_word) GPR[RS] <= 0)
2250     {
2251       DELAY_SLOT (NIA + offset);
2252     }
2253   else
2254     NULLIFY_NEXT_INSTRUCTION ();
2255 }
2256
2257
2258
2259 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
2260 "bltz r<RS>, <OFFSET>"
2261 *mipsI:
2262 *mipsII:
2263 *mipsIII:
2264 *mipsIV:
2265 *mipsV:
2266 *mips32:
2267 *mips32r2:
2268 *mips32r6:
2269 *mips64:
2270 *mips64r2:
2271 *mips64r6:
2272 *vr4100:
2273 *vr5000:
2274 *r3900:
2275 {
2276   address_word offset = EXTEND16 (OFFSET) << 2;
2277   if ((signed_word) GPR[RS] < 0)
2278     {
2279       DELAY_SLOT (NIA + offset);
2280     }
2281 }
2282
2283
2284
2285 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
2286 "bltzal r<RS>, <OFFSET>"
2287 *mipsI:
2288 *mipsII:
2289 *mipsIII:
2290 *mipsIV:
2291 *mipsV:
2292 *mips32:
2293 *mips32r2:
2294 *mips64:
2295 *mips64r2:
2296 *vr4100:
2297 *vr5000:
2298 *r3900:
2299 {
2300   address_word offset = EXTEND16 (OFFSET) << 2;
2301   if (RS == 31)
2302     Unpredictable ();
2303   RA = (CIA + 8);
2304   /* NOTE: The branch occurs AFTER the next instruction has been
2305      executed */
2306   if ((signed_word) GPR[RS] < 0)
2307     {
2308       DELAY_SLOT (NIA + offset);
2309     }
2310 }
2311
2312
2313
2314 000001,00000,10000,16.OFFSET:REGIMM:32::NAL
2315 "nal <OFFSET>"
2316 *mips32r6:
2317 *mips64r6:
2318 {
2319   address_word offset = EXTEND16 (OFFSET) << 2;
2320   RA = (CIA + 8);
2321   FORBIDDEN_SLOT ();
2322 }
2323
2324
2325
2326 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
2327 "bltzall r<RS>, <OFFSET>"
2328 *mipsII:
2329 *mipsIII:
2330 *mipsIV:
2331 *mipsV:
2332 *mips32:
2333 *mips32r2:
2334 *mips64:
2335 *mips64r2:
2336 *vr4100:
2337 *vr5000:
2338 *r3900:
2339 {
2340   address_word offset = EXTEND16 (OFFSET) << 2;
2341   if (RS == 31)
2342     Unpredictable ();
2343   RA = (CIA + 8);
2344   if ((signed_word) GPR[RS] < 0)
2345     {
2346       DELAY_SLOT (NIA + offset);
2347     }
2348   else
2349     NULLIFY_NEXT_INSTRUCTION ();
2350 }
2351
2352
2353
2354 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
2355 "bltzl r<RS>, <OFFSET>"
2356 *mipsII:
2357 *mipsIII:
2358 *mipsIV:
2359 *mipsV:
2360 *mips32:
2361 *mips32r2:
2362 *mips64:
2363 *mips64r2:
2364 *vr4100:
2365 *vr5000:
2366 *r3900:
2367 {
2368   address_word offset = EXTEND16 (OFFSET) << 2;
2369   /* NOTE: The branch occurs AFTER the next instruction has been
2370      executed */
2371   if ((signed_word) GPR[RS] < 0)
2372     {
2373       DELAY_SLOT (NIA + offset);
2374     }
2375   else
2376     NULLIFY_NEXT_INSTRUCTION ();
2377 }
2378
2379
2380
2381 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
2382 "bne r<RS>, r<RT>, <OFFSET>"
2383 *mipsI:
2384 *mipsII:
2385 *mipsIII:
2386 *mipsIV:
2387 *mipsV:
2388 *mips32:
2389 *mips32r2:
2390 *mips32r6:
2391 *mips64:
2392 *mips64r2:
2393 *mips64r6:
2394 *vr4100:
2395 *vr5000:
2396 *r3900:
2397 {
2398   address_word offset = EXTEND16 (OFFSET) << 2;
2399   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2400     {
2401       DELAY_SLOT (NIA + offset);
2402     }
2403 }
2404
2405
2406
2407 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
2408 "bnel r<RS>, r<RT>, <OFFSET>"
2409 *mipsII:
2410 *mipsIII:
2411 *mipsIV:
2412 *mipsV:
2413 *mips32:
2414 *mips32r2:
2415 *mips64:
2416 *mips64r2:
2417 *vr4100:
2418 *vr5000:
2419 *r3900:
2420 {
2421   address_word offset = EXTEND16 (OFFSET) << 2;
2422   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2423     {
2424       DELAY_SLOT (NIA + offset);
2425     }
2426   else
2427     NULLIFY_NEXT_INSTRUCTION ();
2428 }
2429
2430
2431
2432 000000,20.CODE,001101:SPECIAL:32::BREAK
2433 "break %#lx<CODE>"
2434 *mipsI:
2435 *mipsII:
2436 *mipsIII:
2437 *mipsIV:
2438 *mipsV:
2439 *mips32:
2440 *mips32r2:
2441 *mips32r6:
2442 *mips64:
2443 *mips64r2:
2444 *mips64r6:
2445 *vr4100:
2446 *vr5000:
2447 *r3900:
2448 {
2449   do_break (SD_, instruction_0);
2450 }
2451
2452
2453
2454 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
2455 "clo r<RD>, r<RS>"
2456 *mips32:
2457 *mips32r2:
2458 *mips64:
2459 *mips64r2:
2460 *vr5500:
2461 {
2462   if (RT != RD)
2463     Unpredictable ();
2464   do_clo (SD_, RD, RS);
2465 }
2466
2467
2468
2469 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
2470 "clz r<RD>, r<RS>"
2471 *mips32:
2472 *mips32r2:
2473 *mips64:
2474 *mips64r2:
2475 *vr5500:
2476 {
2477   if (RT != RD)
2478     Unpredictable ();
2479   do_clz (SD_, RD, RS);
2480 }
2481
2482
2483
2484 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
2485 "dadd r<RD>, r<RS>, r<RT>"
2486 *mipsIII:
2487 *mipsIV:
2488 *mipsV:
2489 *mips64:
2490 *mips64r2:
2491 *mips64r6:
2492 *vr4100:
2493 *vr5000:
2494 {
2495   check_u64 (SD_, instruction_0);
2496   do_dadd (SD_, RD, RS, RT);
2497 }
2498
2499
2500
2501 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
2502 "daddi r<RT>, r<RS>, <IMMEDIATE>"
2503 *mipsIII:
2504 *mipsIV:
2505 *mipsV:
2506 *mips64:
2507 *mips64r2:
2508 *vr4100:
2509 *vr5000:
2510 {
2511   check_u64 (SD_, instruction_0);
2512   do_daddi (SD_, RT, RS, IMMEDIATE);
2513 }
2514
2515
2516
2517 :function:::void:do_daddiu:int rs, int rt, uint16_t immediate
2518 {
2519   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2520   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
2521   TRACE_ALU_RESULT (GPR[rt]);
2522 }
2523
2524 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
2525 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
2526 *mipsIII:
2527 *mipsIV:
2528 *mipsV:
2529 *mips64:
2530 *mips64r2:
2531 *mips64r6:
2532 *vr4100:
2533 *vr5000:
2534 {
2535   check_u64 (SD_, instruction_0);
2536   do_daddiu (SD_, RS, RT, IMMEDIATE);
2537 }
2538
2539
2540
2541 :function:::void:do_daddu:int rs, int rt, int rd
2542 {
2543   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2544   GPR[rd] = GPR[rs] + GPR[rt];
2545   TRACE_ALU_RESULT (GPR[rd]);
2546 }
2547
2548 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
2549 "daddu r<RD>, r<RS>, r<RT>"
2550 *mipsIII:
2551 *mipsIV:
2552 *mipsV:
2553 *mips64:
2554 *mips64r2:
2555 *mips64r6:
2556 *vr4100:
2557 *vr5000:
2558 {
2559   check_u64 (SD_, instruction_0);
2560   do_daddu (SD_, RS, RT, RD);
2561 }
2562
2563
2564
2565 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
2566 "dclo r<RD>, r<RS>"
2567 *mips64:
2568 *mips64r2:
2569 *vr5500:
2570 {
2571   if (RT != RD)
2572     Unpredictable ();
2573   check_u64 (SD_, instruction_0);
2574   if (RT != RD)
2575     Unpredictable ();
2576   do_dclo (SD_, RD, RS);
2577 }
2578
2579
2580
2581 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
2582 "dclz r<RD>, r<RS>"
2583 *mips64:
2584 *mips64r2:
2585 *vr5500:
2586 {
2587   if (RT != RD)
2588     Unpredictable ();
2589   check_u64 (SD_, instruction_0);
2590   if (RT != RD)
2591     Unpredictable ();
2592   do_dclz (SD_, RD, RS);
2593 }
2594
2595
2596
2597 :function:::void:do_ddiv:int rs, int rt
2598 {
2599   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2600   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2601   {
2602     int64_t n = GPR[rs];
2603     int64_t d = GPR[rt];
2604     int64_t hi;
2605     int64_t lo;
2606     if (d == 0)
2607       {
2608         lo = SIGNED64 (0x8000000000000000);
2609         hi = 0;
2610       }
2611     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
2612       {
2613         lo = SIGNED64 (0x8000000000000000);
2614         hi = 0;
2615       }
2616     else
2617       {
2618         lo = (n / d);
2619         hi = (n % d);
2620       }
2621     HI = hi;
2622     LO = lo;
2623   }
2624   TRACE_ALU_RESULT2 (HI, LO);
2625 }
2626
2627 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
2628 "ddiv r<RS>, r<RT>"
2629 *mipsIII:
2630 *mipsIV:
2631 *mipsV:
2632 *mips64:
2633 *mips64r2:
2634 *vr4100:
2635 *vr5000:
2636 {
2637   check_u64 (SD_, instruction_0);
2638   do_ddiv (SD_, RS, RT);
2639 }
2640
2641
2642
2643 :function:::void:do_ddivu:int rs, int rt
2644 {
2645   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2646   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2647   {
2648     uint64_t n = GPR[rs];
2649     uint64_t d = GPR[rt];
2650     uint64_t hi;
2651     uint64_t lo;
2652     if (d == 0)
2653       {
2654         lo = SIGNED64 (0x8000000000000000);
2655         hi = 0;
2656       }
2657     else
2658       {
2659         lo = (n / d);
2660         hi = (n % d);
2661       }
2662     HI = hi;
2663     LO = lo;
2664   }
2665   TRACE_ALU_RESULT2 (HI, LO);
2666 }
2667
2668 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
2669 "ddivu r<RS>, r<RT>"
2670 *mipsIII:
2671 *mipsIV:
2672 *mipsV:
2673 *mips64:
2674 *mips64r2:
2675 *vr4100:
2676 *vr5000:
2677 {
2678   check_u64 (SD_, instruction_0);
2679   do_ddivu (SD_, RS, RT);
2680 }
2681
2682 :function:::void:do_div:int rs, int rt
2683 {
2684   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2685   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2686   {
2687     int32_t n = GPR[rs];
2688     int32_t d = GPR[rt];
2689     if (d == 0)
2690       {
2691         LO = EXTEND32 (0x80000000);
2692         HI = EXTEND32 (0);
2693       }
2694     else if (n == SIGNED32 (0x80000000) && d == -1)
2695       {
2696         LO = EXTEND32 (0x80000000);
2697         HI = EXTEND32 (0);
2698       }
2699     else
2700       {
2701         LO = EXTEND32 (n / d);
2702         HI = EXTEND32 (n % d);
2703       }
2704   }
2705   TRACE_ALU_RESULT2 (HI, LO);
2706 }
2707
2708 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
2709 "div r<RS>, r<RT>"
2710 *mipsI:
2711 *mipsII:
2712 *mipsIII:
2713 *mipsIV:
2714 *mipsV:
2715 *mips32:
2716 *mips32r2:
2717 *mips64:
2718 *mips64r2:
2719 *vr4100:
2720 *vr5000:
2721 *r3900:
2722 {
2723   do_div (SD_, RS, RT);
2724 }
2725
2726
2727
2728 :function:::void:do_divu:int rs, int rt
2729 {
2730   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
2731   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2732   {
2733     uint32_t n = GPR[rs];
2734     uint32_t d = GPR[rt];
2735     if (d == 0)
2736       {
2737         LO = EXTEND32 (0x80000000);
2738         HI = EXTEND32 (0);
2739       }
2740     else
2741       {
2742         LO = EXTEND32 (n / d);
2743         HI = EXTEND32 (n % d);
2744       }
2745   }
2746   TRACE_ALU_RESULT2 (HI, LO);
2747 }
2748
2749 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
2750 "divu r<RS>, r<RT>"
2751 *mipsI:
2752 *mipsII:
2753 *mipsIII:
2754 *mipsIV:
2755 *mipsV:
2756 *mips32:
2757 *mips32r2:
2758 *mips64:
2759 *mips64r2:
2760 *vr4100:
2761 *vr5000:
2762 *r3900:
2763 {
2764   do_divu (SD_, RS, RT);
2765 }
2766
2767
2768 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
2769 {
2770   uint64_t lo;
2771   uint64_t hi;
2772   uint64_t m00;
2773   uint64_t m01;
2774   uint64_t m10;
2775   uint64_t m11;
2776   uint64_t mid;
2777   int sign;
2778   uint64_t op1 = GPR[rs];
2779   uint64_t op2 = GPR[rt];
2780   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2781   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2782   /* make signed multiply unsigned */
2783   sign = 0;
2784   if (signed_p)
2785     {
2786       if ((int64_t) op1 < 0)
2787         {
2788           op1 = - op1;
2789           ++sign;
2790         }
2791       if ((int64_t) op2 < 0)
2792         {
2793           op2 = - op2;
2794           ++sign;
2795         }
2796     }
2797   /* multiply out the 4 sub products */
2798   m00 = ((uint64_t) VL4_8 (op1) * (uint64_t) VL4_8 (op2));
2799   m10 = ((uint64_t) VH4_8 (op1) * (uint64_t) VL4_8 (op2));
2800   m01 = ((uint64_t) VL4_8 (op1) * (uint64_t) VH4_8 (op2));
2801   m11 = ((uint64_t) VH4_8 (op1) * (uint64_t) VH4_8 (op2));
2802   /* add the products */
2803   mid = ((uint64_t) VH4_8 (m00)
2804          + (uint64_t) VL4_8 (m10)
2805          + (uint64_t) VL4_8 (m01));
2806   lo = U8_4 (mid, m00);
2807   hi = (m11
2808         + (uint64_t) VH4_8 (mid)
2809         + (uint64_t) VH4_8 (m01)
2810         + (uint64_t) VH4_8 (m10));
2811   /* fix the sign */
2812   if (sign & 1)
2813     {
2814       lo = -lo;
2815       if (lo == 0)
2816         hi = -hi;
2817       else
2818         hi = -hi - 1;
2819     }
2820   /* save the result HI/LO (and a gpr) */
2821   LO = lo;
2822   HI = hi;
2823   if (rd != 0)
2824     GPR[rd] = lo;
2825   TRACE_ALU_RESULT2 (HI, LO);
2826 }
2827
2828 :function:::void:do_dmult:int rs, int rt, int rd
2829 {
2830   do_dmultx (SD_, rs, rt, rd, 1);
2831 }
2832
2833 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
2834 "dmult r<RS>, r<RT>"
2835 *mipsIII:
2836 *mipsIV:
2837 *mipsV:
2838 *mips64:
2839 *mips64r2:
2840 *vr4100:
2841 {
2842   check_u64 (SD_, instruction_0);
2843   do_dmult (SD_, RS, RT, 0);
2844 }
2845
2846 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
2847 "dmult r<RS>, r<RT>":RD == 0
2848 "dmult r<RD>, r<RS>, r<RT>"
2849 *vr5000:
2850 {
2851   check_u64 (SD_, instruction_0);
2852   do_dmult (SD_, RS, RT, RD);
2853 }
2854
2855
2856
2857 :function:::void:do_dmultu:int rs, int rt, int rd
2858 {
2859   do_dmultx (SD_, rs, rt, rd, 0);
2860 }
2861
2862 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
2863 "dmultu r<RS>, r<RT>"
2864 *mipsIII:
2865 *mipsIV:
2866 *mipsV:
2867 *mips64:
2868 *mips64r2:
2869 *vr4100:
2870 {
2871   check_u64 (SD_, instruction_0);
2872   do_dmultu (SD_, RS, RT, 0);
2873 }
2874
2875 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
2876 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
2877 "dmultu r<RS>, r<RT>"
2878 *vr5000:
2879 {
2880   check_u64 (SD_, instruction_0);
2881   do_dmultu (SD_, RS, RT, RD);
2882 }
2883
2884
2885 :function:::uint64_t:do_dror:uint64_t x,uint64_t y
2886 {
2887   uint64_t result;
2888
2889   y &= 63;
2890   TRACE_ALU_INPUT2 (x, y);
2891   result = ROTR64 (x, y);
2892   TRACE_ALU_RESULT (result);
2893   return result;
2894 }
2895
2896 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
2897 "dror r<RD>, r<RT>, <SHIFT>"
2898 *mips64r2:
2899 *mips64r6:
2900 *vr5400:
2901 *vr5500:
2902 {
2903   check_u64 (SD_, instruction_0);
2904   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
2905 }
2906
2907 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
2908 "dror32 r<RD>, r<RT>, <SHIFT>"
2909 *mips64r2:
2910 *mips64r6:
2911 *vr5400:
2912 *vr5500:
2913 {
2914   check_u64 (SD_, instruction_0);
2915   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
2916 }
2917
2918 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
2919 "drorv r<RD>, r<RT>, r<RS>"
2920 *mips64r2:
2921 *mips64r6:
2922 *vr5400:
2923 *vr5500:
2924 {
2925   check_u64 (SD_, instruction_0);
2926   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
2927 }
2928
2929
2930 :function:::void:do_dsll:int rt, int rd, int shift
2931 {
2932   TRACE_ALU_INPUT2 (GPR[rt], shift);
2933   GPR[rd] = GPR[rt] << shift;
2934   TRACE_ALU_RESULT (GPR[rd]);
2935 }
2936
2937 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
2938 "dsll r<RD>, r<RT>, <SHIFT>"
2939 *mipsIII:
2940 *mipsIV:
2941 *mipsV:
2942 *mips64:
2943 *mips64r2:
2944 *mips64r6:
2945 *vr4100:
2946 *vr5000:
2947 {
2948   check_u64 (SD_, instruction_0);
2949   do_dsll (SD_, RT, RD, SHIFT);
2950 }
2951
2952
2953 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
2954 "dsll32 r<RD>, r<RT>, <SHIFT>"
2955 *mipsIII:
2956 *mipsIV:
2957 *mipsV:
2958 *mips64:
2959 *mips64r2:
2960 *mips64r6:
2961 *vr4100:
2962 *vr5000:
2963 {
2964   check_u64 (SD_, instruction_0);
2965   do_dsll32 (SD_, RD, RT, SHIFT);
2966 }
2967
2968 :function:::void:do_dsllv:int rs, int rt, int rd
2969 {
2970   int s = MASKED64 (GPR[rs], 5, 0);
2971   TRACE_ALU_INPUT2 (GPR[rt], s);
2972   GPR[rd] = GPR[rt] << s;
2973   TRACE_ALU_RESULT (GPR[rd]);
2974 }
2975
2976 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
2977 "dsllv r<RD>, r<RT>, r<RS>"
2978 *mipsIII:
2979 *mipsIV:
2980 *mipsV:
2981 *mips64:
2982 *mips64r2:
2983 *mips64r6:
2984 *vr4100:
2985 *vr5000:
2986 {
2987   check_u64 (SD_, instruction_0);
2988   do_dsllv (SD_, RS, RT, RD);
2989 }
2990
2991 :function:::void:do_dsra:int rt, int rd, int shift
2992 {
2993   TRACE_ALU_INPUT2 (GPR[rt], shift);
2994   GPR[rd] = ((int64_t) GPR[rt]) >> shift;
2995   TRACE_ALU_RESULT (GPR[rd]);
2996 }
2997
2998
2999 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
3000 "dsra r<RD>, r<RT>, <SHIFT>"
3001 *mipsIII:
3002 *mipsIV:
3003 *mipsV:
3004 *mips64:
3005 *mips64r2:
3006 *mips64r6:
3007 *vr4100:
3008 *vr5000:
3009 {
3010   check_u64 (SD_, instruction_0);
3011   do_dsra (SD_, RT, RD, SHIFT);
3012 }
3013
3014
3015 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
3016 "dsra32 r<RD>, r<RT>, <SHIFT>"
3017 *mipsIII:
3018 *mipsIV:
3019 *mipsV:
3020 *mips64:
3021 *mips64r2:
3022 *mips64r6:
3023 *vr4100:
3024 *vr5000:
3025 {
3026   check_u64 (SD_, instruction_0);
3027   do_dsra32 (SD_, RD, RT, SHIFT);
3028 }
3029
3030
3031 :function:::void:do_dsrav:int rs, int rt, int rd
3032 {
3033   int s = MASKED64 (GPR[rs], 5, 0);
3034   TRACE_ALU_INPUT2 (GPR[rt], s);
3035   GPR[rd] = ((int64_t) GPR[rt]) >> s;
3036   TRACE_ALU_RESULT (GPR[rd]);
3037 }
3038
3039 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
3040 "dsrav r<RD>, r<RT>, r<RS>"
3041 *mipsIII:
3042 *mipsIV:
3043 *mipsV:
3044 *mips64:
3045 *mips64r2:
3046 *mips64r6:
3047 *vr4100:
3048 *vr5000:
3049 {
3050   check_u64 (SD_, instruction_0);
3051   do_dsrav (SD_, RS, RT, RD);
3052 }
3053
3054 :function:::void:do_dsrl:int rt, int rd, int shift
3055 {
3056   TRACE_ALU_INPUT2 (GPR[rt], shift);
3057   GPR[rd] = (uint64_t) GPR[rt] >> shift;
3058   TRACE_ALU_RESULT (GPR[rd]);
3059 }
3060
3061
3062 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
3063 "dsrl r<RD>, r<RT>, <SHIFT>"
3064 *mipsIII:
3065 *mipsIV:
3066 *mipsV:
3067 *mips64:
3068 *mips64r2:
3069 *mips64r6:
3070 *vr4100:
3071 *vr5000:
3072 {
3073   check_u64 (SD_, instruction_0);
3074   do_dsrl (SD_, RT, RD, SHIFT);
3075 }
3076
3077
3078 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
3079 "dsrl32 r<RD>, r<RT>, <SHIFT>"
3080 *mipsIII:
3081 *mipsIV:
3082 *mipsV:
3083 *mips64:
3084 *mips64r2:
3085 *mips64r6:
3086 *vr4100:
3087 *vr5000:
3088 {
3089   check_u64 (SD_, instruction_0);
3090   do_dsrl32 (SD_, RD, RT, SHIFT);
3091 }
3092
3093
3094 :function:::void:do_dsrlv:int rs, int rt, int rd
3095 {
3096   int s = MASKED64 (GPR[rs], 5, 0);
3097   TRACE_ALU_INPUT2 (GPR[rt], s);
3098   GPR[rd] = (uint64_t) GPR[rt] >> s;
3099   TRACE_ALU_RESULT (GPR[rd]);
3100 }
3101
3102
3103
3104 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
3105 "dsrlv r<RD>, r<RT>, r<RS>"
3106 *mipsIII:
3107 *mipsIV:
3108 *mipsV:
3109 *mips64:
3110 *mips64r2:
3111 *mips64r6:
3112 *vr4100:
3113 *vr5000:
3114 {
3115   check_u64 (SD_, instruction_0);
3116   do_dsrlv (SD_, RS, RT, RD);
3117 }
3118
3119
3120 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
3121 "dsub r<RD>, r<RS>, r<RT>"
3122 *mipsIII:
3123 *mipsIV:
3124 *mipsV:
3125 *mips64:
3126 *mips64r2:
3127 *mips64r6:
3128 *vr4100:
3129 *vr5000:
3130 {
3131   check_u64 (SD_, instruction_0);
3132   do_dsub (SD_, RD, RS, RT);
3133 }
3134
3135
3136 :function:::void:do_dsubu:int rs, int rt, int rd
3137 {
3138   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3139   GPR[rd] = GPR[rs] - GPR[rt];
3140   TRACE_ALU_RESULT (GPR[rd]);
3141 }
3142
3143 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
3144 "dsubu r<RD>, r<RS>, r<RT>"
3145 *mipsIII:
3146 *mipsIV:
3147 *mipsV:
3148 *mips64:
3149 *mips64r2:
3150 *mips64r6:
3151 *vr4100:
3152 *vr5000:
3153 {
3154   check_u64 (SD_, instruction_0);
3155   do_dsubu (SD_, RS, RT, RD);
3156 }
3157
3158
3159 000010,26.INSTR_INDEX:NORMAL:32::J
3160 "j <INSTR_INDEX>"
3161 *mipsI:
3162 *mipsII:
3163 *mipsIII:
3164 *mipsIV:
3165 *mipsV:
3166 *mips32:
3167 *mips32r2:
3168 *mips32r6:
3169 *mips64:
3170 *mips64r2:
3171 *mips64r6:
3172 *vr4100:
3173 *vr5000:
3174 *r3900:
3175 {
3176   /* NOTE: The region used is that of the delay slot NIA and NOT the
3177      current instruction */
3178   address_word region = (NIA & MASK (63, 28));
3179   DELAY_SLOT (region | (INSTR_INDEX << 2));
3180 }
3181
3182
3183 000011,26.INSTR_INDEX:NORMAL:32::JAL
3184 "jal <INSTR_INDEX>"
3185 *mipsI:
3186 *mipsII:
3187 *mipsIII:
3188 *mipsIV:
3189 *mipsV:
3190 *mips32:
3191 *mips32r2:
3192 *mips32r6:
3193 *mips64:
3194 *mips64r2:
3195 *mips64r6:
3196 *vr4100:
3197 *vr5000:
3198 *r3900:
3199 {
3200   /* NOTE: The region used is that of the delay slot and NOT the
3201      current instruction */
3202   address_word region = (NIA & MASK (63, 28));
3203   GPR[31] = CIA + 8;
3204   DELAY_SLOT (region | (INSTR_INDEX << 2));
3205 }
3206
3207 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
3208 "jalr r<RS>":RD == 31
3209 "jalr r<RD>, r<RS>"
3210 *mipsI:
3211 *mipsII:
3212 *mipsIII:
3213 *mipsIV:
3214 *mipsV:
3215 *mips32:
3216 *mips32r2:
3217 *mips32r6:
3218 *mips64:
3219 *mips64r2:
3220 *mips64r6:
3221 *vr4100:
3222 *vr5000:
3223 *r3900:
3224 {
3225   address_word temp = GPR[RS];
3226   GPR[RD] = CIA + 8;
3227   DELAY_SLOT (temp);
3228 }
3229
3230 000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
3231 "jalr.hb r<RS>":RD == 31
3232 "jalr.hb r<RD>, r<RS>"
3233 *mips32r2:
3234 *mips32r6:
3235 *mips64r2:
3236 *mips64r6:
3237 {
3238   address_word temp = GPR[RS];
3239   GPR[RD] = CIA + 8;
3240   DELAY_SLOT (temp);
3241 }
3242
3243 000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
3244 "jr r<RS>"
3245 *mipsI:
3246 *mipsII:
3247 *mipsIII:
3248 *mipsIV:
3249 *mipsV:
3250 *mips32:
3251 *mips32r2:
3252 *mips32r6:
3253 *mips64:
3254 *mips64r2:
3255 *mips64r6:
3256 *vr4100:
3257 *vr5000:
3258 *r3900:
3259 {
3260   DELAY_SLOT (GPR[RS]);
3261 }
3262
3263 000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
3264 "jr.hb r<RS>"
3265 *mips32r2:
3266 *mips32r6:
3267 *mips64r2:
3268 *mips64r6:
3269 {
3270   DELAY_SLOT (GPR[RS]);
3271 }
3272
3273 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
3274 {
3275   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3276   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3277   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3278   unsigned int byte;
3279   address_word paddr;
3280   uint64_t memval;
3281   address_word vaddr;
3282
3283   paddr = vaddr = loadstore_ea (SD_, base, offset);
3284   if ((vaddr & access) != 0)
3285     {
3286       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
3287     }
3288   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3289   LoadMemory (&memval, NULL, access, paddr, vaddr, isDATA, isREAL);
3290   byte = ((vaddr & mask) ^ bigendiancpu);
3291   return (memval >> (8 * byte));
3292 }
3293
3294 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3295 {
3296   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3297   address_word reverseendian = (ReverseEndian ? -1 : 0);
3298   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3299   unsigned int byte;
3300   unsigned int word;
3301   address_word paddr;
3302   uint64_t memval;
3303   address_word vaddr;
3304   int nr_lhs_bits;
3305   int nr_rhs_bits;
3306   unsigned_word lhs_mask;
3307   unsigned_word temp;
3308
3309   paddr = vaddr = loadstore_ea (SD_, base, offset);
3310   paddr = (paddr ^ (reverseendian & mask));
3311   if (BigEndianMem == 0)
3312     paddr = paddr & ~access;
3313
3314   /* compute where within the word/mem we are */
3315   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3316   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3317   nr_lhs_bits = 8 * byte + 8;
3318   nr_rhs_bits = 8 * access - 8 * byte;
3319   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3320
3321   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3322            (long) ((uint64_t) vaddr >> 32), (long) vaddr,
3323            (long) ((uint64_t) paddr >> 32), (long) paddr,
3324            word, byte, nr_lhs_bits, nr_rhs_bits); */
3325
3326   LoadMemory (&memval, NULL, byte, paddr, vaddr, isDATA, isREAL);
3327   if (word == 0)
3328     {
3329       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
3330       temp = (memval << nr_rhs_bits);
3331     }
3332   else
3333     {
3334       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
3335       temp = (memval >> nr_lhs_bits);
3336     }
3337   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
3338   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
3339
3340   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
3341            (long) ((uint64_t) memval >> 32), (long) memval,
3342            (long) ((uint64_t) temp >> 32), (long) temp,
3343            (long) ((uint64_t) lhs_mask >> 32), (long) lhs_mask,
3344            (long) (rt >> 32), (long) rt); */
3345   return rt;
3346 }
3347
3348 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3349 {
3350   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3351   address_word reverseendian = (ReverseEndian ? -1 : 0);
3352   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3353   unsigned int byte;
3354   address_word paddr;
3355   uint64_t memval;
3356   address_word vaddr;
3357
3358   paddr = vaddr = loadstore_ea (SD_, base, offset);
3359   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
3360   paddr = (paddr ^ (reverseendian & mask));
3361   if (BigEndianMem != 0)
3362     paddr = paddr & ~access;
3363   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3364   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
3365   LoadMemory (&memval, NULL, access - (access & byte), paddr, vaddr, isDATA, isREAL);
3366   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
3367      (long) paddr, byte, (long) paddr, (long) memval); */
3368   {
3369     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
3370     rt &= ~screen;
3371     rt |= (memval >> (8 * byte)) & screen;
3372   }
3373   return rt;
3374 }
3375
3376
3377 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
3378 "lb r<RT>, <OFFSET>(r<BASE>)"
3379 *mipsI:
3380 *mipsII:
3381 *mipsIII:
3382 *mipsIV:
3383 *mipsV:
3384 *mips32:
3385 *mips32r2:
3386 *mips32r6:
3387 *mips64:
3388 *mips64r2:
3389 *mips64r6:
3390 *vr4100:
3391 *vr5000:
3392 *r3900:
3393 {
3394   do_lb (SD_,RT,OFFSET,BASE);
3395 }
3396
3397
3398 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
3399 "lbu r<RT>, <OFFSET>(r<BASE>)"
3400 *mipsI:
3401 *mipsII:
3402 *mipsIII:
3403 *mipsIV:
3404 *mipsV:
3405 *mips32:
3406 *mips32r2:
3407 *mips32r6:
3408 *mips64:
3409 *mips64r2:
3410 *mips64r6:
3411 *vr4100:
3412 *vr5000:
3413 *r3900:
3414 {
3415   do_lbu (SD_, RT,OFFSET,BASE);
3416 }
3417
3418
3419 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
3420 "ld r<RT>, <OFFSET>(r<BASE>)"
3421 *mipsIII:
3422 *mipsIV:
3423 *mipsV:
3424 *mips64:
3425 *mips64r2:
3426 *mips64r6:
3427 *vr4100:
3428 *vr5000:
3429 {
3430   check_u64 (SD_, instruction_0);
3431   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3432 }
3433
3434
3435 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
3436 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3437 *mipsII:
3438 *mipsIII:
3439 *mipsIV:
3440 *mipsV:
3441 *mips32:
3442 *mips32r2:
3443 *mips64:
3444 *mips64r2:
3445 *vr4100:
3446 *vr5000:
3447 *r3900:
3448 {
3449   do_ldc (SD_, ZZ, RT, OFFSET, BASE);
3450 }
3451
3452
3453
3454
3455 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
3456 "ldl r<RT>, <OFFSET>(r<BASE>)"
3457 *mipsIII:
3458 *mipsIV:
3459 *mipsV:
3460 *mips64:
3461 *mips64r2:
3462 *vr4100:
3463 *vr5000:
3464 {
3465   check_u64 (SD_, instruction_0);
3466   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3467 }
3468
3469
3470 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
3471 "ldr r<RT>, <OFFSET>(r<BASE>)"
3472 *mipsIII:
3473 *mipsIV:
3474 *mipsV:
3475 *mips64:
3476 *mips64r2:
3477 *vr4100:
3478 *vr5000:
3479 {
3480   check_u64 (SD_, instruction_0);
3481   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3482 }
3483
3484
3485 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
3486 "lh r<RT>, <OFFSET>(r<BASE>)"
3487 *mipsI:
3488 *mipsII:
3489 *mipsIII:
3490 *mipsIV:
3491 *mipsV:
3492 *mips32:
3493 *mips32r2:
3494 *mips32r6:
3495 *mips64:
3496 *mips64r2:
3497 *mips64r6:
3498 *vr4100:
3499 *vr5000:
3500 *r3900:
3501 {
3502   do_lh (SD_,RT,OFFSET,BASE);
3503 }
3504
3505
3506 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
3507 "lhu r<RT>, <OFFSET>(r<BASE>)"
3508 *mipsI:
3509 *mipsII:
3510 *mipsIII:
3511 *mipsIV:
3512 *mipsV:
3513 *mips32:
3514 *mips32r2:
3515 *mips32r6:
3516 *mips64:
3517 *mips64r2:
3518 *mips64r6:
3519 *vr4100:
3520 *vr5000:
3521 *r3900:
3522 {
3523   do_lhu (SD_,RT,OFFSET,BASE);
3524 }
3525
3526
3527 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
3528 "ll r<RT>, <OFFSET>(r<BASE>)"
3529 *mipsII:
3530 *mipsIII:
3531 *mipsIV:
3532 *mipsV:
3533 *mips32:
3534 *mips32r2:
3535 *mips64:
3536 *mips64r2:
3537 *vr4100:
3538 *vr5000:
3539 {
3540   do_ll (SD_, RT, OFFSET, BASE);
3541 }
3542
3543
3544 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
3545 "lld r<RT>, <OFFSET>(r<BASE>)"
3546 *mipsIII:
3547 *mipsIV:
3548 *mipsV:
3549 *mips64:
3550 *mips64r2:
3551 *vr4100:
3552 *vr5000:
3553 {
3554   check_u64 (SD_, instruction_0);
3555   do_lld (SD_, RT, OFFSET, BASE);
3556 }
3557
3558
3559 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
3560 "lui r<RT>, %#lx<IMMEDIATE>"
3561 *mipsI:
3562 *mipsII:
3563 *mipsIII:
3564 *mipsIV:
3565 *mipsV:
3566 *mips32:
3567 *mips32r2:
3568 *mips32r6:
3569 *mips64:
3570 *mips64r2:
3571 *mips64r6:
3572 *vr4100:
3573 *vr5000:
3574 *r3900:
3575 {
3576   do_lui (SD_, RT, IMMEDIATE);
3577 }
3578
3579
3580 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
3581 "lw r<RT>, <OFFSET>(r<BASE>)"
3582 *mipsI:
3583 *mipsII:
3584 *mipsIII:
3585 *mipsIV:
3586 *mipsV:
3587 *mips32:
3588 *mips32r2:
3589 *mips32r6:
3590 *mips64:
3591 *mips64r2:
3592 *mips64r6:
3593 *vr4100:
3594 *vr5000:
3595 *r3900:
3596 {
3597   do_lw (SD_,RT,OFFSET,BASE);
3598 }
3599
3600
3601 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
3602 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3603 *mipsI:
3604 *mipsII:
3605 *mipsIII:
3606 *mipsIV:
3607 *mipsV:
3608 *mips32:
3609 *mips32r2:
3610 *mips64:
3611 *mips64r2:
3612 *vr4100:
3613 *vr5000:
3614 *r3900:
3615 {
3616   do_lwc (SD_, ZZ, RT, OFFSET, BASE);
3617 }
3618
3619
3620 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
3621 "lwl r<RT>, <OFFSET>(r<BASE>)"
3622 *mipsI:
3623 *mipsII:
3624 *mipsIII:
3625 *mipsIV:
3626 *mipsV:
3627 *mips32:
3628 *mips32r2:
3629 *mips64:
3630 *mips64r2:
3631 *vr4100:
3632 *vr5000:
3633 *r3900:
3634 {
3635   do_lwl (SD_, RT, OFFSET, BASE);
3636 }
3637
3638
3639 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
3640 "lwr r<RT>, <OFFSET>(r<BASE>)"
3641 *mipsI:
3642 *mipsII:
3643 *mipsIII:
3644 *mipsIV:
3645 *mipsV:
3646 *mips32:
3647 *mips32r2:
3648 *mips64:
3649 *mips64r2:
3650 *vr4100:
3651 *vr5000:
3652 *r3900:
3653 {
3654   do_lwr (SD_, RT, OFFSET, BASE);
3655 }
3656
3657
3658 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
3659 "lwu r<RT>, <OFFSET>(r<BASE>)"
3660 *mipsIII:
3661 *mipsIV:
3662 *mipsV:
3663 *mips64:
3664 *mips64r2:
3665 *mips64r6:
3666 *vr4100:
3667 *vr5000:
3668 {
3669   do_lwu (SD_, RT, OFFSET, BASE, instruction_0);
3670 }
3671
3672
3673
3674 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
3675 "madd r<RS>, r<RT>"
3676 *mips32:
3677 *mips64:
3678 *vr5500:
3679 {
3680   do_madd (SD_, RS, RT);
3681 }
3682
3683
3684 011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
3685 "madd r<RS>, r<RT>":AC == 0
3686 "madd ac<AC>, r<RS>, r<RT>"
3687 *mips32r2:
3688 *mips64r2:
3689 *dsp2:
3690 {
3691   do_dsp_madd (SD_, AC, RS, RT);
3692 }
3693
3694
3695 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
3696 "maddu r<RS>, r<RT>"
3697 *mips32:
3698 *mips64:
3699 *vr5500:
3700 {
3701   do_maddu (SD_, RS, RT);
3702 }
3703
3704
3705 011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
3706 "maddu r<RS>, r<RT>":AC == 0
3707 "maddu ac<AC>, r<RS>, r<RT>"
3708 *mips32r2:
3709 *mips64r2:
3710 *dsp2:
3711 {
3712   do_dsp_maddu (SD_, AC, RS, RT);
3713 }
3714
3715
3716 :function:::void:do_mfhi:int rd
3717 {
3718   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
3719   TRACE_ALU_INPUT1 (HI);
3720   GPR[rd] = HI;
3721   TRACE_ALU_RESULT (GPR[rd]);
3722 }
3723
3724 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
3725 "mfhi r<RD>"
3726 *mipsI:
3727 *mipsII:
3728 *mipsIII:
3729 *mipsIV:
3730 *mipsV:
3731 *vr4100:
3732 *vr5000:
3733 *r3900:
3734 *mips32:
3735 *mips64:
3736 {
3737   do_mfhi (SD_, RD);
3738 }
3739
3740
3741 000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
3742 "mfhi r<RD>":AC == 0
3743 "mfhi r<RD>, ac<AC>"
3744 *mips32r2:
3745 *mips64r2:
3746 *dsp:
3747 {
3748   do_dsp_mfhi (SD_, AC, RD);
3749 }
3750
3751
3752 :function:::void:do_mflo:int rd
3753 {
3754   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
3755   TRACE_ALU_INPUT1 (LO);
3756   GPR[rd] = LO;
3757   TRACE_ALU_RESULT (GPR[rd]);
3758 }
3759
3760 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
3761 "mflo r<RD>"
3762 *mipsI:
3763 *mipsII:
3764 *mipsIII:
3765 *mipsIV:
3766 *mipsV:
3767 *vr4100:
3768 *vr5000:
3769 *r3900:
3770 *mips32:
3771 *mips64:
3772 {
3773   do_mflo (SD_, RD);
3774 }
3775
3776
3777 000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
3778 "mflo r<RD>":AC == 0
3779 "mflo r<RD>, ac<AC>"
3780 *mips32r2:
3781 *mips64r2:
3782 *dsp:
3783 {
3784   do_dsp_mflo (SD_, AC, RD);
3785 }
3786
3787
3788 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
3789 "movn r<RD>, r<RS>, r<RT>"
3790 *mipsIV:
3791 *mipsV:
3792 *mips32:
3793 *mips32r2:
3794 *mips64:
3795 *mips64r2:
3796 *vr5000:
3797 {
3798   do_movn (SD_, RD, RS, RT);
3799 }
3800
3801
3802
3803 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
3804 "movz r<RD>, r<RS>, r<RT>"
3805 *mipsIV:
3806 *mipsV:
3807 *mips32:
3808 *mips32r2:
3809 *mips64:
3810 *mips64r2:
3811 *vr5000:
3812 {
3813   do_movz (SD_, RD, RS, RT);
3814 }
3815
3816
3817
3818 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
3819 "msub r<RS>, r<RT>"
3820 *mips32:
3821 *mips64:
3822 *vr5500:
3823 {
3824   do_msub (SD_, RS, RT);
3825 }
3826
3827
3828 011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
3829 "msub r<RS>, r<RT>":AC == 0
3830 "msub ac<AC>, r<RS>, r<RT>"
3831 *mips32r2:
3832 *mips64r2:
3833 *dsp2:
3834 {
3835   do_dsp_msub (SD_, AC, RS, RT);
3836 }
3837
3838
3839 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
3840 "msubu r<RS>, r<RT>"
3841 *mips32:
3842 *mips64:
3843 *vr5500:
3844 {
3845   do_msubu (SD_, RS, RT);
3846 }
3847
3848
3849 011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
3850 "msubu r<RS>, r<RT>":AC == 0
3851 "msubu ac<AC>, r<RS>, r<RT>"
3852 *mips32r2:
3853 *mips64r2:
3854 *dsp2:
3855 {
3856   do_dsp_msubu (SD_, AC, RS, RT);
3857 }
3858
3859
3860 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
3861 "mthi r<RS>"
3862 *mipsI:
3863 *mipsII:
3864 *mipsIII:
3865 *mipsIV:
3866 *mipsV:
3867 *vr4100:
3868 *vr5000:
3869 *r3900:
3870 *mips32:
3871 *mips64:
3872 {
3873   do_mthi (SD_, RS);
3874 }
3875
3876
3877 000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
3878 "mthi r<RS>":AC == 0
3879 "mthi r<RS>, ac<AC>"
3880 *mips32r2:
3881 *mips64r2:
3882 *dsp:
3883 {
3884   do_dsp_mthi (SD_, AC, RS);
3885 }
3886
3887
3888 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
3889 "mtlo r<RS>"
3890 *mipsI:
3891 *mipsII:
3892 *mipsIII:
3893 *mipsIV:
3894 *mipsV:
3895 *vr4100:
3896 *vr5000:
3897 *r3900:
3898 *mips32:
3899 *mips64:
3900 {
3901   do_mtlo (SD_, RS);
3902 }
3903
3904
3905 000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
3906 "mtlo r<RS>":AC == 0
3907 "mtlo r<RS>, ac<AC>"
3908 *mips32r2:
3909 *mips64r2:
3910 *dsp:
3911 {
3912   do_dsp_mtlo (SD_, AC, RS);
3913 }
3914
3915
3916 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
3917 "mul r<RD>, r<RS>, r<RT>"
3918 *mips32:
3919 *mips32r2:
3920 *mips64:
3921 *mips64r2:
3922 *vr5500:
3923 {
3924   do_mul (SD_, RD, RS, RT);
3925 }
3926
3927
3928
3929 :function:::void:do_mult:int rs, int rt, int rd
3930 {
3931   int64_t prod;
3932   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
3933   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3934     Unpredictable ();
3935   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3936   prod = (((int64_t)(int32_t) GPR[rs])
3937           * ((int64_t)(int32_t) GPR[rt]));
3938   LO = EXTEND32 (VL4_8 (prod));
3939   HI = EXTEND32 (VH4_8 (prod));
3940   ACX = 0;  /* SmartMIPS */
3941   if (rd != 0)
3942     GPR[rd] = LO;
3943   TRACE_ALU_RESULT2 (HI, LO);
3944 }
3945
3946 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
3947 "mult r<RS>, r<RT>"
3948 *mipsI:
3949 *mipsII:
3950 *mipsIII:
3951 *mipsIV:
3952 *mipsV:
3953 *mips32:
3954 *mips64:
3955 *vr4100:
3956 {
3957   do_mult (SD_, RS, RT, 0);
3958 }
3959
3960
3961 000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
3962 "mult r<RS>, r<RT>":AC == 0
3963 "mult ac<AC>, r<RS>, r<RT>"
3964 *mips32r2:
3965 *mips64r2:
3966 *dsp2:
3967 {
3968   do_dsp_mult (SD_, AC, RS, RT);
3969 }
3970
3971
3972 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
3973 "mult r<RS>, r<RT>":RD == 0
3974 "mult r<RD>, r<RS>, r<RT>"
3975 *vr5000:
3976 *r3900:
3977 {
3978   do_mult (SD_, RS, RT, RD);
3979 }
3980
3981
3982 :function:::void:do_multu:int rs, int rt, int rd
3983 {
3984   uint64_t prod;
3985   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
3986   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3987     Unpredictable ();
3988   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3989   prod = (((uint64_t)(uint32_t) GPR[rs])
3990           * ((uint64_t)(uint32_t) GPR[rt]));
3991   LO = EXTEND32 (VL4_8 (prod));
3992   HI = EXTEND32 (VH4_8 (prod));
3993   if (rd != 0)
3994     GPR[rd] = LO;
3995   TRACE_ALU_RESULT2 (HI, LO);
3996 }
3997
3998 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
3999 "multu r<RS>, r<RT>"
4000 *mipsI:
4001 *mipsII:
4002 *mipsIII:
4003 *mipsIV:
4004 *mipsV:
4005 *mips32:
4006 *mips64:
4007 *vr4100:
4008 {
4009   do_multu (SD_, RS, RT, 0);
4010 }
4011
4012
4013 000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
4014 "multu r<RS>, r<RT>":AC == 0
4015 "multu r<RS>, r<RT>"
4016 *mips32r2:
4017 *mips64r2:
4018 *dsp2:
4019 {
4020   do_dsp_multu (SD_, AC, RS, RT);
4021 }
4022
4023
4024 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
4025 "multu r<RS>, r<RT>":RD == 0
4026 "multu r<RD>, r<RS>, r<RT>"
4027 *vr5000:
4028 *r3900:
4029 {
4030   do_multu (SD_, RS, RT, RD);
4031 }
4032
4033
4034 :function:::void:do_nor:int rs, int rt, int rd
4035 {
4036   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4037   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
4038   TRACE_ALU_RESULT (GPR[rd]);
4039 }
4040
4041 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
4042 "nor r<RD>, r<RS>, r<RT>"
4043 *mipsI:
4044 *mipsII:
4045 *mipsIII:
4046 *mipsIV:
4047 *mipsV:
4048 *mips32:
4049 *mips32r2:
4050 *mips32r6:
4051 *mips64:
4052 *mips64r2:
4053 *mips64r6:
4054 *vr4100:
4055 *vr5000:
4056 *r3900:
4057 {
4058   do_nor (SD_, RS, RT, RD);
4059 }
4060
4061
4062 :function:::void:do_or:int rs, int rt, int rd
4063 {
4064   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4065   GPR[rd] = (GPR[rs] | GPR[rt]);
4066   TRACE_ALU_RESULT (GPR[rd]);
4067 }
4068
4069 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
4070 "or r<RD>, r<RS>, r<RT>"
4071 *mipsI:
4072 *mipsII:
4073 *mipsIII:
4074 *mipsIV:
4075 *mipsV:
4076 *mips32:
4077 *mips32r2:
4078 *mips32r6:
4079 *mips64:
4080 *mips64r2:
4081 *mips64r6:
4082 *vr4100:
4083 *vr5000:
4084 *r3900:
4085 {
4086   do_or (SD_, RS, RT, RD);
4087 }
4088
4089
4090
4091 :function:::void:do_ori:int rs, int rt, unsigned immediate
4092 {
4093   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4094   GPR[rt] = (GPR[rs] | immediate);
4095   TRACE_ALU_RESULT (GPR[rt]);
4096 }
4097
4098 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
4099 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
4100 *mipsI:
4101 *mipsII:
4102 *mipsIII:
4103 *mipsIV:
4104 *mipsV:
4105 *mips32:
4106 *mips32r2:
4107 *mips32r6:
4108 *mips64:
4109 *mips64r2:
4110 *mips64r6:
4111 *vr4100:
4112 *vr5000:
4113 *r3900:
4114 {
4115   do_ori (SD_, RS, RT, IMMEDIATE);
4116 }
4117
4118
4119 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
4120 "pref <HINT>, <OFFSET>(r<BASE>)"
4121 *mipsIV:
4122 *mipsV:
4123 *mips32:
4124 *mips32r2:
4125 *mips64:
4126 *mips64r2:
4127 *vr5000:
4128 {
4129   do_pref (SD_, HINT, OFFSET, BASE);
4130 }
4131
4132
4133 :function:::uint64_t:do_ror:uint32_t x,uint32_t y
4134 {
4135   uint64_t result;
4136
4137   y &= 31;
4138   TRACE_ALU_INPUT2 (x, y);
4139   result = EXTEND32 (ROTR32 (x, y));
4140   TRACE_ALU_RESULT (result);
4141   return result;
4142 }
4143
4144 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
4145 "ror r<RD>, r<RT>, <SHIFT>"
4146 *mips32r2:
4147 *mips32r6:
4148 *mips64r2:
4149 *mips64r6:
4150 *smartmips:
4151 *vr5400:
4152 *vr5500:
4153 {
4154   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
4155 }
4156
4157 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
4158 "rorv r<RD>, r<RT>, r<RS>"
4159 *mips32r2:
4160 *mips32r6:
4161 *mips64r2:
4162 *mips64r6:
4163 *smartmips:
4164 *vr5400:
4165 *vr5500:
4166 {
4167   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
4168 }
4169
4170
4171 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
4172 {
4173   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4174   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
4175   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
4176   unsigned int byte;
4177   address_word paddr;
4178   uint64_t memval;
4179   address_word vaddr;
4180
4181   paddr = vaddr = loadstore_ea (SD_, base, offset);
4182   if ((vaddr & access) != 0)
4183     {
4184       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
4185     }
4186   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4187   byte = ((vaddr & mask) ^ bigendiancpu);
4188   memval = (word << (8 * byte));
4189   StoreMemory (access, memval, 0, paddr, vaddr, isREAL);
4190 }
4191
4192 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
4193 {
4194   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4195   address_word reverseendian = (ReverseEndian ? -1 : 0);
4196   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
4197   unsigned int byte;
4198   unsigned int word;
4199   address_word paddr;
4200   uint64_t memval;
4201   address_word vaddr;
4202   int nr_lhs_bits;
4203   int nr_rhs_bits;
4204
4205   paddr = vaddr = loadstore_ea (SD_, base, offset);
4206   paddr = (paddr ^ (reverseendian & mask));
4207   if (BigEndianMem == 0)
4208     paddr = paddr & ~access;
4209
4210   /* compute where within the word/mem we are */
4211   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
4212   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
4213   nr_lhs_bits = 8 * byte + 8;
4214   nr_rhs_bits = 8 * access - 8 * byte;
4215   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
4216   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
4217            (long) ((uint64_t) vaddr >> 32), (long) vaddr,
4218            (long) ((uint64_t) paddr >> 32), (long) paddr,
4219            word, byte, nr_lhs_bits, nr_rhs_bits); */
4220
4221   if (word == 0)
4222     {
4223       memval = (rt >> nr_rhs_bits);
4224     }
4225   else
4226     {
4227       memval = (rt << nr_lhs_bits);
4228     }
4229   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
4230            (long) ((uint64_t) rt >> 32), (long) rt,
4231            (long) ((uint64_t) memval >> 32), (long) memval); */
4232   StoreMemory (byte, memval, 0, paddr, vaddr, isREAL);
4233 }
4234
4235 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
4236 {
4237   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4238   address_word reverseendian = (ReverseEndian ? -1 : 0);
4239   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
4240   unsigned int byte;
4241   address_word paddr;
4242   uint64_t memval;
4243   address_word vaddr;
4244
4245   paddr = vaddr = loadstore_ea (SD_, base, offset);
4246   paddr = (paddr ^ (reverseendian & mask));
4247   if (BigEndianMem != 0)
4248     paddr &= ~access;
4249   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
4250   memval = (rt << (byte * 8));
4251   StoreMemory (access - (access & byte), memval, 0, paddr, vaddr, isREAL);
4252 }
4253
4254
4255 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
4256 "sb r<RT>, <OFFSET>(r<BASE>)"
4257 *mipsI:
4258 *mipsII:
4259 *mipsIII:
4260 *mipsIV:
4261 *mipsV:
4262 *mips32:
4263 *mips32r2:
4264 *mips32r6:
4265 *mips64:
4266 *mips64r2:
4267 *mips64r6:
4268 *vr4100:
4269 *vr5000:
4270 *r3900:
4271 {
4272   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4273 }
4274
4275
4276 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
4277 "sc r<RT>, <OFFSET>(r<BASE>)"
4278 *mipsII:
4279 *mipsIII:
4280 *mipsIV:
4281 *mipsV:
4282 *mips32:
4283 *mips32r2:
4284 *mips64:
4285 *mips64r2:
4286 *vr4100:
4287 *vr5000:
4288 {
4289   do_sc (SD_, RT, OFFSET, BASE, instruction_0, 1);
4290 }
4291
4292
4293 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
4294 "scd r<RT>, <OFFSET>(r<BASE>)"
4295 *mipsIII:
4296 *mipsIV:
4297 *mipsV:
4298 *mips64:
4299 *mips64r2:
4300 *vr4100:
4301 *vr5000:
4302 {
4303   check_u64 (SD_, instruction_0);
4304   do_scd (SD_, RT, OFFSET, BASE, 1);
4305 }
4306
4307
4308 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
4309 "sd r<RT>, <OFFSET>(r<BASE>)"
4310 *mipsIII:
4311 *mipsIV:
4312 *mipsV:
4313 *mips64:
4314 *mips64r2:
4315 *mips64r6:
4316 *vr4100:
4317 *vr5000:
4318 {
4319   check_u64 (SD_, instruction_0);
4320   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4321 }
4322
4323
4324 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
4325 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
4326 *mipsII:
4327 *mipsIII:
4328 *mipsIV:
4329 *mipsV:
4330 *mips32:
4331 *mips32r2:
4332 *mips64:
4333 *mips64r2:
4334 *vr4100:
4335 *vr5000:
4336 {
4337   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
4338 }
4339
4340
4341 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
4342 "sdl r<RT>, <OFFSET>(r<BASE>)"
4343 *mipsIII:
4344 *mipsIV:
4345 *mipsV:
4346 *mips64:
4347 *mips64r2:
4348 *vr4100:
4349 *vr5000:
4350 {
4351   check_u64 (SD_, instruction_0);
4352   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4353 }
4354
4355
4356 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
4357 "sdr r<RT>, <OFFSET>(r<BASE>)"
4358 *mipsIII:
4359 *mipsIV:
4360 *mipsV:
4361 *mips64:
4362 *mips64r2:
4363 *vr4100:
4364 *vr5000:
4365 {
4366   check_u64 (SD_, instruction_0);
4367   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4368 }
4369
4370
4371
4372 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
4373 "sh r<RT>, <OFFSET>(r<BASE>)"
4374 *mipsI:
4375 *mipsII:
4376 *mipsIII:
4377 *mipsIV:
4378 *mipsV:
4379 *mips32:
4380 *mips32r2:
4381 *mips32r6:
4382 *mips64:
4383 *mips64r2:
4384 *mips64r6:
4385 *vr4100:
4386 *vr5000:
4387 *r3900:
4388 {
4389   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4390 }
4391
4392
4393 :function:::void:do_sll:int rt, int rd, int shift
4394 {
4395   uint32_t temp = (GPR[rt] << shift);
4396   TRACE_ALU_INPUT2 (GPR[rt], shift);
4397   GPR[rd] = EXTEND32 (temp);
4398   TRACE_ALU_RESULT (GPR[rd]);
4399 }
4400
4401 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
4402 "nop":RD == 0 && RT == 0 && SHIFT == 0
4403 "sll r<RD>, r<RT>, <SHIFT>"
4404 *mipsI:
4405 *mipsII:
4406 *mipsIII:
4407 *mipsIV:
4408 *mipsV:
4409 *vr4100:
4410 *vr5000:
4411 *r3900:
4412 {
4413   /* Skip shift for NOP, so that there won't be lots of extraneous
4414      trace output.  */
4415   if (RD != 0 || RT != 0 || SHIFT != 0)
4416     do_sll (SD_, RT, RD, SHIFT);
4417 }
4418
4419 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
4420 "nop":RD == 0 && RT == 0 && SHIFT == 0
4421 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
4422 "ehb":RD == 0 && RT == 0 && SHIFT == 3
4423 "sll r<RD>, r<RT>, <SHIFT>"
4424 *mips32:
4425 *mips32r2:
4426 *mips32r6:
4427 *mips64:
4428 *mips64r2:
4429 *mips64r6:
4430 {
4431   do_sll (SD_, RT, RD, SHIFT);
4432 }
4433
4434
4435 :function:::void:do_sllv:int rs, int rt, int rd
4436 {
4437   int s = MASKED (GPR[rs], 4, 0);
4438   uint32_t temp = (GPR[rt] << s);
4439   TRACE_ALU_INPUT2 (GPR[rt], s);
4440   GPR[rd] = EXTEND32 (temp);
4441   TRACE_ALU_RESULT (GPR[rd]);
4442 }
4443
4444 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
4445 "sllv r<RD>, r<RT>, r<RS>"
4446 *mipsI:
4447 *mipsII:
4448 *mipsIII:
4449 *mipsIV:
4450 *mipsV:
4451 *mips32:
4452 *mips32r2:
4453 *mips32r6:
4454 *mips64:
4455 *mips64r2:
4456 *mips64r6:
4457 *vr4100:
4458 *vr5000:
4459 *r3900:
4460 {
4461   do_sllv (SD_, RS, RT, RD);
4462 }
4463
4464
4465 :function:::void:do_slt:int rs, int rt, int rd
4466 {
4467   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4468   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
4469   TRACE_ALU_RESULT (GPR[rd]);
4470 }
4471
4472 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
4473 "slt r<RD>, r<RS>, r<RT>"
4474 *mipsI:
4475 *mipsII:
4476 *mipsIII:
4477 *mipsIV:
4478 *mipsV:
4479 *mips32:
4480 *mips32r2:
4481 *mips32r6:
4482 *mips64:
4483 *mips64r2:
4484 *mips64r6:
4485 *vr4100:
4486 *vr5000:
4487 *r3900:
4488 {
4489   do_slt (SD_, RS, RT, RD);
4490 }
4491
4492
4493 :function:::void:do_slti:int rs, int rt, uint16_t immediate
4494 {
4495   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
4496   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
4497   TRACE_ALU_RESULT (GPR[rt]);
4498 }
4499
4500 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
4501 "slti r<RT>, r<RS>, <IMMEDIATE>"
4502 *mipsI:
4503 *mipsII:
4504 *mipsIII:
4505 *mipsIV:
4506 *mipsV:
4507 *mips32:
4508 *mips32r2:
4509 *mips32r6:
4510 *mips64:
4511 *mips64r2:
4512 *mips64r6:
4513 *vr4100:
4514 *vr5000:
4515 *r3900:
4516 {
4517   do_slti (SD_, RS, RT, IMMEDIATE);
4518 }
4519
4520
4521 :function:::void:do_sltiu:int rs, int rt, uint16_t immediate
4522 {
4523   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
4524   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
4525   TRACE_ALU_RESULT (GPR[rt]);
4526 }
4527
4528 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
4529 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
4530 *mipsI:
4531 *mipsII:
4532 *mipsIII:
4533 *mipsIV:
4534 *mipsV:
4535 *mips32:
4536 *mips32r2:
4537 *mips32r6:
4538 *mips64:
4539 *mips64r2:
4540 *mips64r6:
4541 *vr4100:
4542 *vr5000:
4543 *r3900:
4544 {
4545   do_sltiu (SD_, RS, RT, IMMEDIATE);
4546 }
4547
4548
4549
4550 :function:::void:do_sltu:int rs, int rt, int rd
4551 {
4552   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4553   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
4554   TRACE_ALU_RESULT (GPR[rd]);
4555 }
4556
4557 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
4558 "sltu r<RD>, r<RS>, r<RT>"
4559 *mipsI:
4560 *mipsII:
4561 *mipsIII:
4562 *mipsIV:
4563 *mipsV:
4564 *mips32:
4565 *mips32r2:
4566 *mips32r6:
4567 *mips64:
4568 *mips64r2:
4569 *mips64r6:
4570 *vr4100:
4571 *vr5000:
4572 *r3900:
4573 {
4574   do_sltu (SD_, RS, RT, RD);
4575 }
4576
4577
4578 :function:::void:do_sra:int rt, int rd, int shift
4579 {
4580   int32_t temp = (int32_t) GPR[rt] >> shift;
4581   if (NotWordValue (GPR[rt]))
4582     Unpredictable ();
4583   TRACE_ALU_INPUT2 (GPR[rt], shift);
4584   GPR[rd] = EXTEND32 (temp);
4585   TRACE_ALU_RESULT (GPR[rd]);
4586 }
4587
4588 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
4589 "sra r<RD>, r<RT>, <SHIFT>"
4590 *mipsI:
4591 *mipsII:
4592 *mipsIII:
4593 *mipsIV:
4594 *mipsV:
4595 *mips32:
4596 *mips32r2:
4597 *mips32r6:
4598 *mips64:
4599 *mips64r2:
4600 *mips64r6:
4601 *vr4100:
4602 *vr5000:
4603 *r3900:
4604 {
4605   do_sra (SD_, RT, RD, SHIFT);
4606 }
4607
4608
4609
4610 :function:::void:do_srav:int rs, int rt, int rd
4611 {
4612   int s = MASKED (GPR[rs], 4, 0);
4613   int32_t temp = (int32_t) GPR[rt] >> s;
4614   if (NotWordValue (GPR[rt]))
4615     Unpredictable ();
4616   TRACE_ALU_INPUT2 (GPR[rt], s);
4617   GPR[rd] = EXTEND32 (temp);
4618   TRACE_ALU_RESULT (GPR[rd]);
4619 }
4620
4621 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
4622 "srav r<RD>, r<RT>, r<RS>"
4623 *mipsI:
4624 *mipsII:
4625 *mipsIII:
4626 *mipsIV:
4627 *mipsV:
4628 *mips32:
4629 *mips32r2:
4630 *mips32r6:
4631 *mips64:
4632 *mips64r2:
4633 *mips64r6:
4634 *vr4100:
4635 *vr5000:
4636 *r3900:
4637 {
4638   do_srav (SD_, RS, RT, RD);
4639 }
4640
4641
4642
4643 :function:::void:do_srl:int rt, int rd, int shift
4644 {
4645   uint32_t temp = (uint32_t) GPR[rt] >> shift;
4646   if (NotWordValue (GPR[rt]))
4647     Unpredictable ();
4648   TRACE_ALU_INPUT2 (GPR[rt], shift);
4649   GPR[rd] = EXTEND32 (temp);
4650   TRACE_ALU_RESULT (GPR[rd]);
4651 }
4652
4653 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
4654 "srl r<RD>, r<RT>, <SHIFT>"
4655 *mipsI:
4656 *mipsII:
4657 *mipsIII:
4658 *mipsIV:
4659 *mipsV:
4660 *mips32:
4661 *mips32r2:
4662 *mips32r6:
4663 *mips64:
4664 *mips64r2:
4665 *mips64r6:
4666 *vr4100:
4667 *vr5000:
4668 *r3900:
4669 {
4670   do_srl (SD_, RT, RD, SHIFT);
4671 }
4672
4673
4674 :function:::void:do_srlv:int rs, int rt, int rd
4675 {
4676   int s = MASKED (GPR[rs], 4, 0);
4677   uint32_t temp = (uint32_t) GPR[rt] >> s;
4678   if (NotWordValue (GPR[rt]))
4679     Unpredictable ();
4680   TRACE_ALU_INPUT2 (GPR[rt], s);
4681   GPR[rd] = EXTEND32 (temp);
4682   TRACE_ALU_RESULT (GPR[rd]);
4683 }
4684
4685 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
4686 "srlv r<RD>, r<RT>, r<RS>"
4687 *mipsI:
4688 *mipsII:
4689 *mipsIII:
4690 *mipsIV:
4691 *mipsV:
4692 *mips32:
4693 *mips32r2:
4694 *mips32r6:
4695 *mips64:
4696 *mips64r2:
4697 *mips64r6:
4698 *vr4100:
4699 *vr5000:
4700 *r3900:
4701 {
4702   do_srlv (SD_, RS, RT, RD);
4703 }
4704
4705
4706 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
4707 "sub r<RD>, r<RS>, r<RT>"
4708 *mipsI:
4709 *mipsII:
4710 *mipsIII:
4711 *mipsIV:
4712 *mipsV:
4713 *mips32:
4714 *mips32r2:
4715 *mips32r6:
4716 *mips64:
4717 *mips64r2:
4718 *mips64r6:
4719 *vr4100:
4720 *vr5000:
4721 *r3900:
4722 {
4723   do_sub (SD_, RD, RS, RT);
4724 }
4725
4726
4727 :function:::void:do_subu:int rs, int rt, int rd
4728 {
4729   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
4730     Unpredictable ();
4731   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4732   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
4733   TRACE_ALU_RESULT (GPR[rd]);
4734 }
4735
4736 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
4737 "subu r<RD>, r<RS>, r<RT>"
4738 *mipsI:
4739 *mipsII:
4740 *mipsIII:
4741 *mipsIV:
4742 *mipsV:
4743 *mips32:
4744 *mips32r2:
4745 *mips32r6:
4746 *mips64:
4747 *mips64r2:
4748 *mips64r6:
4749 *vr4100:
4750 *vr5000:
4751 *r3900:
4752 {
4753   do_subu (SD_, RS, RT, RD);
4754 }
4755
4756
4757 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
4758 "sw r<RT>, <OFFSET>(r<BASE>)"
4759 *mipsI:
4760 *mipsII:
4761 *mipsIII:
4762 *mipsIV:
4763 *mipsV:
4764 *mips32:
4765 *mips32r2:
4766 *mips32r6:
4767 *mips64:
4768 *mips64r2:
4769 *mips64r6:
4770 *vr4100:
4771 *r3900:
4772 *vr5000:
4773 {
4774   do_sw (SD_, RT, OFFSET, BASE);
4775 }
4776
4777
4778 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
4779 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
4780 *mipsI:
4781 *mipsII:
4782 *mipsIII:
4783 *mipsIV:
4784 *mipsV:
4785 *mips32:
4786 *mips32r2:
4787 *mips64:
4788 *mips64r2:
4789 *vr4100:
4790 *vr5000:
4791 *r3900:
4792 {
4793   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
4794 }
4795
4796
4797 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
4798 "swl r<RT>, <OFFSET>(r<BASE>)"
4799 *mipsI:
4800 *mipsII:
4801 *mipsIII:
4802 *mipsIV:
4803 *mipsV:
4804 *mips32:
4805 *mips32r2:
4806 *mips64:
4807 *mips64r2:
4808 *vr4100:
4809 *vr5000:
4810 *r3900:
4811 {
4812   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4813 }
4814
4815
4816 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
4817 "swr r<RT>, <OFFSET>(r<BASE>)"
4818 *mipsI:
4819 *mipsII:
4820 *mipsIII:
4821 *mipsIV:
4822 *mipsV:
4823 *mips32:
4824 *mips32r2:
4825 *mips64:
4826 *mips64r2:
4827 *vr4100:
4828 *vr5000:
4829 *r3900:
4830 {
4831   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
4832 }
4833
4834
4835 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
4836 "sync":STYPE == 0
4837 "sync <STYPE>"
4838 *mipsII:
4839 *mipsIII:
4840 *mipsIV:
4841 *mipsV:
4842 *mips32:
4843 *mips32r2:
4844 *mips32r6:
4845 *mips64:
4846 *mips64r2:
4847 *mips64r6:
4848 *vr4100:
4849 *vr5000:
4850 *r3900:
4851 {
4852   SyncOperation (STYPE);
4853 }
4854
4855
4856 000000,20.CODE,001100:SPECIAL:32::SYSCALL
4857 "syscall %#lx<CODE>"
4858 *mipsI:
4859 *mipsII:
4860 *mipsIII:
4861 *mipsIV:
4862 *mipsV:
4863 *mips32:
4864 *mips32r2:
4865 *mips32r6:
4866 *mips64:
4867 *mips64r2:
4868 *mips64r6:
4869 *vr4100:
4870 *vr5000:
4871 *r3900:
4872 {
4873   SignalException (SystemCall, instruction_0);
4874 }
4875
4876
4877 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
4878 "teq r<RS>, r<RT>"
4879 *mipsII:
4880 *mipsIII:
4881 *mipsIV:
4882 *mipsV:
4883 *mips32:
4884 *mips32r2:
4885 *mips32r6:
4886 *mips64:
4887 *mips64r2:
4888 *mips64r6:
4889 *vr4100:
4890 *vr5000:
4891 {
4892   do_teq (SD_, RS, RT, instruction_0);
4893 }
4894
4895
4896 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
4897 "teqi r<RS>, <IMMEDIATE>"
4898 *mipsII:
4899 *mipsIII:
4900 *mipsIV:
4901 *mipsV:
4902 *mips32:
4903 *mips32r2:
4904 *mips64:
4905 *mips64r2:
4906 *vr4100:
4907 *vr5000:
4908 {
4909   do_teqi (SD_, RS, IMMEDIATE, instruction_0);
4910 }
4911
4912
4913 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
4914 "tge r<RS>, r<RT>"
4915 *mipsII:
4916 *mipsIII:
4917 *mipsIV:
4918 *mipsV:
4919 *mips32:
4920 *mips32r2:
4921 *mips32r6:
4922 *mips64:
4923 *mips64r2:
4924 *mips64r6:
4925 *vr4100:
4926 *vr5000:
4927 {
4928   do_tge (SD_, RS, RT, instruction_0);
4929 }
4930
4931
4932 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
4933 "tgei r<RS>, <IMMEDIATE>"
4934 *mipsII:
4935 *mipsIII:
4936 *mipsIV:
4937 *mipsV:
4938 *mips32:
4939 *mips32r2:
4940 *mips64:
4941 *mips64r2:
4942 *vr4100:
4943 *vr5000:
4944 {
4945   do_tgei (SD_, RS, IMMEDIATE, instruction_0);
4946 }
4947
4948
4949 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
4950 "tgeiu r<RS>, <IMMEDIATE>"
4951 *mipsII:
4952 *mipsIII:
4953 *mipsIV:
4954 *mipsV:
4955 *mips32:
4956 *mips32r2:
4957 *mips64:
4958 *mips64r2:
4959 *vr4100:
4960 *vr5000:
4961 {
4962   do_tgeiu (SD_, RS, IMMEDIATE, instruction_0);
4963 }
4964
4965
4966 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
4967 "tgeu r<RS>, r<RT>"
4968 *mipsII:
4969 *mipsIII:
4970 *mipsIV:
4971 *mipsV:
4972 *mips32:
4973 *mips32r2:
4974 *mips32r6:
4975 *mips64:
4976 *mips64r2:
4977 *mips64r6:
4978 *vr4100:
4979 *vr5000:
4980 {
4981   do_tgeu (SD_, RS, RT, instruction_0);
4982 }
4983
4984
4985 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
4986 "tlt r<RS>, r<RT>"
4987 *mipsII:
4988 *mipsIII:
4989 *mipsIV:
4990 *mipsV:
4991 *mips32:
4992 *mips32r2:
4993 *mips32r6:
4994 *mips64:
4995 *mips64r2:
4996 *mips64r6:
4997 *vr4100:
4998 *vr5000:
4999 {
5000   do_tlt (SD_, RS, RT, instruction_0);
5001 }
5002
5003
5004 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
5005 "tlti r<RS>, <IMMEDIATE>"
5006 *mipsII:
5007 *mipsIII:
5008 *mipsIV:
5009 *mipsV:
5010 *mips32:
5011 *mips32r2:
5012 *mips64:
5013 *mips64r2:
5014 *vr4100:
5015 *vr5000:
5016 {
5017   do_tlti (SD_, RS, IMMEDIATE, instruction_0);
5018 }
5019
5020
5021 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
5022 "tltiu r<RS>, <IMMEDIATE>"
5023 *mipsII:
5024 *mipsIII:
5025 *mipsIV:
5026 *mipsV:
5027 *mips32:
5028 *mips32r2:
5029 *mips64:
5030 *mips64r2:
5031 *vr4100:
5032 *vr5000:
5033 {
5034   do_tltiu (SD_, RS, IMMEDIATE, instruction_0);
5035 }
5036
5037
5038 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
5039 "tltu r<RS>, r<RT>"
5040 *mipsII:
5041 *mipsIII:
5042 *mipsIV:
5043 *mipsV:
5044 *mips32:
5045 *mips32r2:
5046 *mips32r6:
5047 *mips64:
5048 *mips64r2:
5049 *mips64r6:
5050 *vr4100:
5051 *vr5000:
5052 {
5053   do_tltu (SD_, RS, RT, instruction_0);
5054 }
5055
5056
5057 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
5058 "tne r<RS>, r<RT>"
5059 *mipsII:
5060 *mipsIII:
5061 *mipsIV:
5062 *mipsV:
5063 *mips32:
5064 *mips32r2:
5065 *mips32r6:
5066 *mips64:
5067 *mips64r2:
5068 *mips64r6:
5069 *vr4100:
5070 *vr5000:
5071 {
5072   do_tne (SD_, RS, RT, instruction_0);
5073 }
5074
5075
5076 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
5077 "tnei r<RS>, <IMMEDIATE>"
5078 *mipsII:
5079 *mipsIII:
5080 *mipsIV:
5081 *mipsV:
5082 *mips32:
5083 *mips32r2:
5084 *mips64:
5085 *mips64r2:
5086 *vr4100:
5087 *vr5000:
5088 {
5089   do_tnei (SD_, RS, IMMEDIATE, instruction_0);
5090 }
5091
5092
5093 :function:::void:do_xor:int rs, int rt, int rd
5094 {
5095   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
5096   GPR[rd] = GPR[rs] ^ GPR[rt];
5097   TRACE_ALU_RESULT (GPR[rd]);
5098 }
5099
5100 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
5101 "xor r<RD>, r<RS>, r<RT>"
5102 *mipsI:
5103 *mipsII:
5104 *mipsIII:
5105 *mipsIV:
5106 *mipsV:
5107 *mips32:
5108 *mips32r2:
5109 *mips32r6:
5110 *mips64:
5111 *mips64r2:
5112 *mips64r6:
5113 *vr4100:
5114 *vr5000:
5115 *r3900:
5116 {
5117   do_xor (SD_, RS, RT, RD);
5118 }
5119
5120
5121 :function:::void:do_xori:int rs, int rt, uint16_t immediate
5122 {
5123   TRACE_ALU_INPUT2 (GPR[rs], immediate);
5124   GPR[rt] = GPR[rs] ^ immediate;
5125   TRACE_ALU_RESULT (GPR[rt]);
5126 }
5127
5128 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
5129 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
5130 *mipsI:
5131 *mipsII:
5132 *mipsIII:
5133 *mipsIV:
5134 *mipsV:
5135 *mips32:
5136 *mips32r2:
5137 *mips32r6:
5138 *mips64:
5139 *mips64r2:
5140 *mips64r6:
5141 *vr4100:
5142 *vr5000:
5143 *r3900:
5144 {
5145   do_xori (SD_, RS, RT, IMMEDIATE);
5146 }
5147
5148
5149 //
5150 // MIPS Architecture:
5151 //
5152 //        FPU Instruction Set (COP1 & COP1X)
5153 //
5154
5155
5156 :%s::::FMT:int fmt
5157 {
5158   switch (fmt)
5159     {
5160     case fmt_single: return "s";
5161     case fmt_double: return "d";
5162     case fmt_word: return "w";
5163     case fmt_long: return "l";
5164     case fmt_ps: return "ps";
5165     default: return "?";
5166     }
5167 }
5168
5169 :%s::::TF:int tf
5170 {
5171   if (tf)
5172     return "t";
5173   else
5174     return "f";
5175 }
5176
5177 :%s::::ND:int nd
5178 {
5179   if (nd)
5180     return "l";
5181   else
5182     return "";
5183 }
5184
5185 :%s::::COND:int cond
5186 {
5187   switch (cond)
5188     {
5189     case 00: return "f";
5190     case 01: return "un";
5191     case 02: return "eq";
5192     case 03: return "ueq";
5193     case 04: return "olt";
5194     case 05: return "ult";
5195     case 06: return "ole";
5196     case 07: return "ule";
5197     case 010: return "sf";
5198     case 011: return "ngle";
5199     case 012: return "seq";
5200     case 013: return "ngl";
5201     case 014: return "lt";
5202     case 015: return "nge";
5203     case 016: return "le";
5204     case 017: return "ngt";
5205     default: return "?";
5206     }
5207 }
5208
5209
5210 // Helpers:
5211 //
5212 // Check that the given FPU format is usable, and signal a
5213 // ReservedInstruction exception if not.
5214 //
5215
5216 // check_fmt_p checks that the format is single, double, or paired single.
5217 :function:::void:check_fmt_p:int fmt, instruction_word insn
5218 *mipsI:
5219 *mipsII:
5220 *mipsIII:
5221 *mipsIV:
5222 *mips32:
5223 *mips32r6:
5224 *mips64r6:
5225 *vr4100:
5226 *vr5000:
5227 *r3900:
5228 {
5229   /* None of these ISAs support Paired Single, so just fall back to
5230      the single/double check.  */
5231   if ((fmt != fmt_single) && (fmt != fmt_double))
5232     SignalException (ReservedInstruction, insn);
5233 }
5234
5235 :function:::void:check_fmt_p:int fmt, instruction_word insn
5236 *mips32r2:
5237 *micromips32:
5238 {
5239   if ((fmt != fmt_single) && (fmt != fmt_double) && (fmt != fmt_ps))
5240     SignalException (ReservedInstruction, insn);
5241 }
5242
5243 :function:::void:check_fmt_p:int fmt, instruction_word insn
5244 *mipsV:
5245 *mips64:
5246 *mips64r2:
5247 *micromips64:
5248 {
5249   if ((fmt != fmt_single) && (fmt != fmt_double)
5250       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
5251     SignalException (ReservedInstruction, insn);
5252 }
5253
5254
5255 // Helper:
5256 //
5257 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
5258 // exception if not.
5259 //
5260
5261 :function:::void:check_fpu:
5262 *mipsI:
5263 *mipsII:
5264 *mipsIII:
5265 *mipsIV:
5266 *mipsV:
5267 *mips32:
5268 *mips32r2:
5269 *mips64:
5270 *mips64r2:
5271 *vr4100:
5272 *vr5000:
5273 *r3900:
5274 *micromips32:
5275 *micromips64:
5276 {
5277   if (! COP_Usable (1))
5278     SignalExceptionCoProcessorUnusable (1);
5279
5280   FCSR &= ~(fcsr_NAN2008_mask | fcsr_ABS2008_mask);
5281   sim_fpu_quiet_nan_inverted = true;
5282 }
5283
5284 // Helper:
5285 //
5286 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
5287 // exception if not.
5288 //
5289
5290 :function:::void:check_fpu:
5291 *mips32r6:
5292 *mips64r6:
5293 {
5294   if (! COP_Usable (1))
5295     SignalExceptionCoProcessorUnusable (1);
5296
5297   FCSR |= (fcsr_NAN2008_mask | fcsr_ABS2008_mask);
5298   sim_fpu_quiet_nan_inverted = 0;
5299   sim_fpu_set_mode (sim_fpu_ieee754_2008);
5300 }
5301
5302 // Helper:
5303 //
5304 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
5305 // or MIPS32.  do_load cannot be used instead because it returns an
5306 // unsigned_word, which is limited to the size of the machine's registers.
5307 //
5308
5309 :function:::uint64_t:do_load_double:address_word base, address_word offset
5310 *mipsII:
5311 *mips32:
5312 *mips32r2:
5313 *mips32r6:
5314 *micromips32:
5315 {
5316   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
5317   address_word vaddr;
5318   address_word paddr;
5319   uint64_t memval;
5320   uint64_t v;
5321
5322   paddr = vaddr = loadstore_ea (SD_, base, offset);
5323   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
5324     {
5325       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
5326                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
5327                        sim_core_unaligned_signal);
5328     }
5329   LoadMemory (&memval, NULL, AccessLength_WORD, paddr, vaddr, isDATA, isREAL);
5330   v = (uint64_t)memval;
5331   LoadMemory (&memval, NULL, AccessLength_WORD, paddr + 4, vaddr + 4, isDATA,
5332               isREAL);
5333   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
5334 }
5335
5336
5337 // Helper:
5338 //
5339 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
5340 // or MIPS32.  do_load cannot be used instead because it returns an
5341 // unsigned_word, which is limited to the size of the machine's registers.
5342 //
5343
5344 :function:::void:do_store_double:address_word base, address_word offset, uint64_t v
5345 *mipsII:
5346 *mips32:
5347 *mips32r2:
5348 *micromips32:
5349  *mips32r6:
5350 {
5351   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
5352   address_word vaddr;
5353   address_word paddr;
5354   uint64_t memval;
5355
5356   paddr = vaddr = loadstore_ea (SD_, base, offset);
5357   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
5358     {
5359       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
5360                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
5361                        sim_core_unaligned_signal);
5362     }
5363   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
5364   StoreMemory (AccessLength_WORD, memval, 0, paddr, vaddr, isREAL);
5365   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
5366   StoreMemory (AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4, isREAL);
5367 }
5368
5369
5370 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
5371 "abs.%s<FMT> f<FD>, f<FS>"
5372 *mipsI:
5373 *mipsII:
5374 *mipsIII:
5375 *mipsIV:
5376 *mipsV:
5377 *mips32:
5378 *mips32r2:
5379 *mips32r6:
5380 *mips64:
5381 *mips64r2:
5382 *mips64r6:
5383 *vr4100:
5384 *vr5000:
5385 *r3900:
5386 {
5387   do_abs_fmt (SD_, FMT, FD, FS, instruction_0);
5388 }
5389
5390
5391
5392 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
5393 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
5394 *mipsI:
5395 *mipsII:
5396 *mipsIII:
5397 *mipsIV:
5398 *mipsV:
5399 *mips32:
5400 *mips32r2:
5401 *mips32r6:
5402 *mips64:
5403 *mips64r2:
5404 *mips64r6:
5405 *vr4100:
5406 *vr5000:
5407 *r3900:
5408 {
5409   do_add_fmt (SD_, FMT, FD, FS, FT, instruction_0);
5410 }
5411
5412
5413 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:32,f::ALNV.PS
5414 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
5415 *mipsV:
5416 *mips32r2:
5417 *mips64:
5418 *mips64r2:
5419 {
5420   do_alnv_ps (SD_, FD, FS, FT, RS, instruction_0);
5421 }
5422
5423
5424 // BC1F
5425 // BC1FL
5426 // BC1T
5427 // BC1TL
5428
5429 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
5430 "bc1%s<TF>%s<ND> <OFFSET>"
5431 *mipsI:
5432 *mipsII:
5433 *mipsIII:
5434 {
5435   check_fpu (SD_);
5436   TRACE_BRANCH_INPUT (PREVCOC1());
5437   if (PREVCOC1() == TF)
5438     {
5439       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5440       TRACE_BRANCH_RESULT (dest);
5441       DELAY_SLOT (dest);
5442     }
5443   else if (ND)
5444     {
5445       TRACE_BRANCH_RESULT (0);
5446       NULLIFY_NEXT_INSTRUCTION ();
5447     }
5448   else
5449     {
5450       TRACE_BRANCH_RESULT (NIA);
5451     }
5452 }
5453
5454 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
5455 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
5456 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
5457 *mipsIV:
5458 *mipsV:
5459 *mips32:
5460 *mips32r2:
5461 *mips64:
5462 *mips64r2:
5463 #*vr4100:
5464 *vr5000:
5465 *r3900:
5466 {
5467   check_fpu (SD_);
5468   if (GETFCC(CC) == TF)
5469     {
5470       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
5471       DELAY_SLOT (dest);
5472     }
5473   else if (ND)
5474     {
5475       NULLIFY_NEXT_INSTRUCTION ();
5476     }
5477 }
5478
5479
5480 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
5481 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
5482 *mipsI:
5483 *mipsII:
5484 *mipsIII:
5485 {
5486   int fmt = FMT;
5487   check_fpu (SD_);
5488   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
5489   TRACE_ALU_RESULT (ValueFCR (31));
5490 }
5491
5492 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
5493 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
5494 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
5495 *mipsIV:
5496 *mipsV:
5497 *mips32:
5498 *mips32r2:
5499 *mips64:
5500 *mips64r2:
5501 *vr4100:
5502 *vr5000:
5503 *r3900:
5504 {
5505   do_c_cond_fmt (SD_, COND, FMT, CC, FS, FT, instruction_0);
5506 }
5507
5508
5509 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:32,f::CEIL.L.fmt
5510 "ceil.l.%s<FMT> f<FD>, f<FS>"
5511 *mipsIII:
5512 *mipsIV:
5513 *mipsV:
5514 *mips32r2:
5515 *mips32r6:
5516 *mips64:
5517 *mips64r2:
5518 *mips64r6:
5519 *vr4100:
5520 *vr5000:
5521 *r3900:
5522 {
5523   do_ceil_fmt (SD_, fmt_long, FMT, FD, FS, instruction_0);
5524 }
5525
5526
5527 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
5528 "ceil.w.%s<FMT> f<FD>, f<FS>"
5529 *mipsII:
5530 *mipsIII:
5531 *mipsIV:
5532 *mipsV:
5533 *mips32:
5534 *mips32r2:
5535 *mips32r6:
5536 *mips64:
5537 *mips64r2:
5538 *mips64r6:
5539 *vr4100:
5540 *vr5000:
5541 *r3900:
5542 {
5543   do_ceil_fmt (SD_, fmt_word, FMT, FD, FS, instruction_0);
5544 }
5545
5546
5547 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
5548 "cfc1 r<RT>, f<FS>"
5549 *mipsI:
5550 *mipsII:
5551 *mipsIII:
5552 {
5553   check_fpu (SD_);
5554   if (FS == 0)
5555     PENDING_FILL (RT, EXTEND32 (FCR0));
5556   else if (FS == 31)
5557     PENDING_FILL (RT, EXTEND32 (FCR31));
5558   /* else NOP */
5559 }
5560
5561 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
5562 "cfc1 r<RT>, f<FS>"
5563 *mipsIV:
5564 *vr4100:
5565 *vr5000:
5566 *r3900:
5567 {
5568   check_fpu (SD_);
5569   if (FS == 0 || FS == 31)
5570     {
5571       unsigned_word  fcr = ValueFCR (FS);
5572       TRACE_ALU_INPUT1 (fcr);
5573       GPR[RT] = fcr;
5574     }
5575   /* else NOP */
5576   TRACE_ALU_RESULT (GPR[RT]);
5577 }
5578
5579 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
5580 "cfc1 r<RT>, f<FS>"
5581 *mipsV:
5582 *mips32:
5583 *mips32r2:
5584 *mips32r6:
5585 *mips64:
5586 *mips64r2:
5587 *mips64r6:
5588 {
5589   do_cfc1 (SD_, RT, FS);
5590 }
5591
5592 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
5593 "ctc1 r<RT>, f<FS>"
5594 *mipsI:
5595 *mipsII:
5596 *mipsIII:
5597 {
5598   check_fpu (SD_);
5599   if (FS == 31)
5600     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
5601   /* else NOP */
5602 }
5603
5604 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
5605 "ctc1 r<RT>, f<FS>"
5606 *mipsIV:
5607 *vr4100:
5608 *vr5000:
5609 *r3900:
5610 {
5611   check_fpu (SD_);
5612   TRACE_ALU_INPUT1 (GPR[RT]);
5613   if (FS == 31)
5614     StoreFCR (FS, GPR[RT]);
5615   /* else NOP */
5616 }
5617
5618 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
5619 "ctc1 r<RT>, f<FS>"
5620 *mipsV:
5621 *mips32:
5622 *mips32r2:
5623 *mips32r6:
5624 *mips64:
5625 *mips64r2:
5626 *mips64r6:
5627 {
5628   do_ctc1 (SD_, RT, FS);
5629 }
5630
5631
5632 //
5633 // FIXME: Does not correctly differentiate between mips*
5634 //
5635 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
5636 "cvt.d.%s<FMT> f<FD>, f<FS>"
5637 *mipsI:
5638 *mipsII:
5639 *mipsIII:
5640 *mipsIV:
5641 *mipsV:
5642 *mips32:
5643 *mips32r2:
5644 *mips32r6:
5645 *mips64:
5646 *mips64r2:
5647 *mips64r6:
5648 *vr4100:
5649 *vr5000:
5650 *r3900:
5651 {
5652   do_cvt_d_fmt (SD_, FMT, FD, FS, instruction_0);
5653 }
5654
5655
5656 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:32,f::CVT.L.fmt
5657 "cvt.l.%s<FMT> f<FD>, f<FS>"
5658 *mipsIII:
5659 *mipsIV:
5660 *mipsV:
5661 *mips32r2:
5662 *mips32r6:
5663 *mips64:
5664 *mips64r2:
5665 *mips64r6:
5666 *vr4100:
5667 *vr5000:
5668 *r3900:
5669 {
5670   do_cvt_l_fmt (SD_, FMT, FD, FS, instruction_0);
5671 }
5672
5673
5674 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:32,f::CVT.PS.S
5675 "cvt.ps.s f<FD>, f<FS>, f<FT>"
5676 *mipsV:
5677 *mips32r2:
5678 *mips64:
5679 *mips64r2:
5680 {
5681   do_cvt_ps_s (SD_, FD, FS, FT, instruction_0);
5682 }
5683
5684
5685 //
5686 // FIXME: Does not correctly differentiate between mips*
5687 //
5688 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
5689 "cvt.s.%s<FMT> f<FD>, f<FS>"
5690 *mipsI:
5691 *mipsII:
5692 *mipsIII:
5693 *mipsIV:
5694 *mipsV:
5695 *mips32:
5696 *mips32r2:
5697 *mips32r6:
5698 *mips64:
5699 *mips64r2:
5700 *mips64r6:
5701 *vr4100:
5702 *vr5000:
5703 *r3900:
5704 {
5705   do_cvt_s_fmt (SD_, FMT, FD, FS, instruction_0);
5706 }
5707
5708
5709 010001,10,110,00000,5.FS,5.FD,101000:COP1:32,f::CVT.S.PL
5710 "cvt.s.pl f<FD>, f<FS>"
5711 *mipsV:
5712 *mips32r2:
5713 *mips64:
5714 *mips64r2:
5715 {
5716   do_cvt_s_pl (SD_, FD, FS, instruction_0);
5717 }
5718
5719
5720 010001,10,110,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.PU
5721 "cvt.s.pu f<FD>, f<FS>"
5722 *mipsV:
5723 *mips32r2:
5724 *mips64:
5725 *mips64r2:
5726 {
5727   do_cvt_s_pu (SD_, FD, FS, instruction_0);
5728 }
5729
5730
5731 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
5732 "cvt.w.%s<FMT> f<FD>, f<FS>"
5733 *mipsI:
5734 *mipsII:
5735 *mipsIII:
5736 *mipsIV:
5737 *mipsV:
5738 *mips32:
5739 *mips32r2:
5740 *mips32r6:
5741 *mips64:
5742 *mips64r2:
5743 *mips64r6:
5744 *vr4100:
5745 *vr5000:
5746 *r3900:
5747 {
5748   do_cvt_w_fmt (SD_, FMT, FD, FS, instruction_0);
5749 }
5750
5751
5752 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
5753 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
5754 *mipsI:
5755 *mipsII:
5756 *mipsIII:
5757 *mipsIV:
5758 *mipsV:
5759 *mips32:
5760 *mips32r2:
5761 *mips32r6:
5762 *mips64:
5763 *mips64r2:
5764 *mips64r6:
5765 *vr4100:
5766 *vr5000:
5767 *r3900:
5768 {
5769   do_div_fmt (SD_, FMT, FD, FS, FT, instruction_0);
5770 }
5771
5772
5773 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
5774 "dmfc1 r<RT>, f<FS>"
5775 *mipsIII:
5776 {
5777   uint64_t v;
5778   check_fpu (SD_);
5779   check_u64 (SD_, instruction_0);
5780   if (SizeFGR () == 64)
5781     v = FGR[FS];
5782   else if ((FS & 0x1) == 0)
5783     v = SET64HI (FGR[FS+1]) | FGR[FS];
5784   else
5785     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
5786   PENDING_FILL (RT, v);
5787   TRACE_ALU_RESULT (v);
5788 }
5789
5790 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
5791 "dmfc1 r<RT>, f<FS>"
5792 *mipsIV:
5793 *mipsV:
5794 *mips64:
5795 *mips64r2:
5796 *mips64r6:
5797 *vr4100:
5798 *vr5000:
5799 *r3900:
5800 {
5801   check_fpu (SD_);
5802   check_u64 (SD_, instruction_0);
5803   do_dmfc1b (SD_, RT, FS);
5804 }
5805
5806
5807 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
5808 "dmtc1 r<RT>, f<FS>"
5809 *mipsIII:
5810 {
5811   uint64_t v;
5812   check_fpu (SD_);
5813   check_u64 (SD_, instruction_0);
5814   if (SizeFGR () == 64)
5815     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
5816   else if ((FS & 0x1) == 0)
5817     {
5818       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
5819       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5820     }
5821   else
5822     Unpredictable ();
5823   TRACE_FP_RESULT (GPR[RT]);
5824 }
5825
5826 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
5827 "dmtc1 r<RT>, f<FS>"
5828 *mipsIV:
5829 *mipsV:
5830 *mips64:
5831 *mips64r2:
5832 *mips64r6:
5833 *vr4100:
5834 *vr5000:
5835 *r3900:
5836 {
5837   check_fpu (SD_);
5838   check_u64 (SD_, instruction_0);
5839   do_dmtc1b (SD_, RT, FS);
5840 }
5841
5842
5843 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:32,f::FLOOR.L.fmt
5844 "floor.l.%s<FMT> f<FD>, f<FS>"
5845 *mipsIII:
5846 *mipsIV:
5847 *mipsV:
5848 *mips32r2:
5849 *mips32r6:
5850 *mips64:
5851 *mips64r2:
5852 *mips64r6:
5853 *vr4100:
5854 *vr5000:
5855 *r3900:
5856 {
5857   do_floor_fmt (SD_, fmt_long, FMT, FD, FS);
5858 }
5859
5860
5861 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
5862 "floor.w.%s<FMT> f<FD>, f<FS>"
5863 *mipsII:
5864 *mipsIII:
5865 *mipsIV:
5866 *mipsV:
5867 *mips32:
5868 *mips32r2:
5869 *mips32r6:
5870 *mips64:
5871 *mips64r2:
5872 *mips64r6:
5873 *vr4100:
5874 *vr5000:
5875 *r3900:
5876 {
5877   do_floor_fmt (SD_, fmt_word, FMT, FD, FS);
5878 }
5879
5880
5881 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
5882 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5883 *mipsII:
5884 *mips32:
5885 *mips32r2:
5886 *mips32r6:
5887 {
5888   check_fpu (SD_);
5889   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
5890 }
5891
5892
5893 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
5894 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
5895 *mipsIII:
5896 *mipsIV:
5897 *mipsV:
5898 *mips64:
5899 *mips64r2:
5900 *mips64r6:
5901 *vr4100:
5902 *vr5000:
5903 *r3900:
5904 {
5905   check_fpu (SD_);
5906   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
5907 }
5908
5909
5910 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:32,f::LDXC1
5911 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5912 *mips32r2:
5913 {
5914   check_fpu (SD_);
5915   COP_LD (1, FD, do_load_double (SD_, GPR[BASE], GPR[INDEX]));
5916 }
5917
5918
5919 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
5920 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
5921 *mipsIV:
5922 *mipsV:
5923 *mips64:
5924 *mips64r2:
5925 *vr5000:
5926 {
5927   check_fpu (SD_);
5928   check_u64 (SD_, instruction_0);
5929   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
5930 }
5931
5932
5933 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:32,f::LUXC1
5934 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
5935 *mips32r2:
5936 {
5937   do_luxc1_32 (SD_, FD, INDEX, BASE);
5938 }
5939
5940
5941 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
5942 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
5943 *mipsV:
5944 *mips64:
5945 *mips64r2:
5946 {
5947   check_fpu (SD_);
5948   check_u64 (SD_, instruction_0);
5949   do_luxc1_64 (SD_, FD, INDEX, BASE);
5950 }
5951
5952
5953 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
5954 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
5955 *mipsI:
5956 *mipsII:
5957 *mipsIII:
5958 *mipsIV:
5959 *mipsV:
5960 *mips32:
5961 *mips32r2:
5962 *mips32r6:
5963 *mips64:
5964 *mips64r2:
5965 *mips64r6:
5966 *vr4100:
5967 *vr5000:
5968 *r3900:
5969 {
5970   do_lwc1 (SD_, FT, OFFSET, BASE);
5971 }
5972
5973
5974 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32,f::LWXC1
5975 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
5976 *mipsIV:
5977 *mipsV:
5978 *mips32r2:
5979 *mips64:
5980 *mips64r2:
5981 *vr5000:
5982 {
5983   do_lwxc1 (SD_, FD, INDEX, BASE, instruction_0);
5984 }
5985
5986
5987
5988 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:32,f::MADD.fmt
5989 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5990 *mipsIV:
5991 *mipsV:
5992 *mips32r2:
5993 *mips64:
5994 *mips64r2:
5995 *vr5000:
5996 {
5997   do_madd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
5998 }
5999
6000
6001 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
6002 "mfc1 r<RT>, f<FS>"
6003 *mipsI:
6004 *mipsII:
6005 *mipsIII:
6006 {
6007   uint64_t v;
6008   check_fpu (SD_);
6009   v = EXTEND32 (FGR[FS]);
6010   PENDING_FILL (RT, v);
6011   TRACE_ALU_RESULT (v);
6012 }
6013
6014 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
6015 "mfc1 r<RT>, f<FS>"
6016 *mipsIV:
6017 *mipsV:
6018 *mips32:
6019 *mips32r2:
6020 *mips32r6:
6021 *mips64:
6022 *mips64r2:
6023 *mips64r6:
6024 *vr4100:
6025 *vr5000:
6026 *r3900:
6027 {
6028   do_mfc1b (SD_, RT, FS);
6029 }
6030
6031
6032 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
6033 "mov.%s<FMT> f<FD>, f<FS>"
6034 *mipsI:
6035 *mipsII:
6036 *mipsIII:
6037 *mipsIV:
6038 *mipsV:
6039 *mips32:
6040 *mips32r2:
6041 *mips32r6:
6042 *mips64:
6043 *mips64r2:
6044 *mips64r6:
6045 *vr4100:
6046 *vr5000:
6047 *r3900:
6048 {
6049   do_mov_fmt (SD_, FMT, FD, FS, instruction_0);
6050 }
6051
6052
6053 // MOVF
6054 // MOVT
6055 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
6056 "mov%s<TF> r<RD>, r<RS>, <CC>"
6057 *mipsIV:
6058 *mipsV:
6059 *mips32:
6060 *mips32r2:
6061 *mips64:
6062 *mips64r2:
6063 *vr5000:
6064 {
6065   do_movtf (SD_, TF, RD, RS, CC);
6066 }
6067
6068
6069 // MOVF.fmt
6070 // MOVT.fmt
6071 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
6072 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
6073 *mipsIV:
6074 *mipsV:
6075 *mips32:
6076 *mips32r2:
6077 *mips64:
6078 *mips64r2:
6079 *vr5000:
6080 {
6081   do_movtf_fmt (SD_, TF, FMT, FD, FS, CC);
6082 }
6083
6084
6085 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
6086 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
6087 *mipsIV:
6088 *mipsV:
6089 *mips32:
6090 *mips32r2:
6091 *mips64:
6092 *mips64r2:
6093 *vr5000:
6094 {
6095   do_movn_fmt (SD_, FMT, FD, FS, RT);
6096 }
6097
6098
6099 // MOVT see MOVtf
6100
6101
6102 // MOVT.fmt see MOVtf.fmt
6103
6104
6105
6106 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
6107 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
6108 *mipsIV:
6109 *mipsV:
6110 *mips32:
6111 *mips32r2:
6112 *mips64:
6113 *mips64r2:
6114 *vr5000:
6115 {
6116   do_movz_fmt (SD_, FMT, FD, FS, RT);
6117 }
6118
6119
6120 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:32,f::MSUB.fmt
6121 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
6122 *mipsIV:
6123 *mipsV:
6124 *mips32r2:
6125 *mips64:
6126 *mips64r2:
6127 *vr5000:
6128 {
6129   do_msub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
6130 }
6131
6132
6133 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
6134 "mtc1 r<RT>, f<FS>"
6135 *mipsI:
6136 *mipsII:
6137 *mipsIII:
6138 {
6139   check_fpu (SD_);
6140   if (SizeFGR () == 64)
6141     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
6142   else
6143     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
6144   TRACE_FP_RESULT (GPR[RT]);
6145 }
6146
6147 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
6148 "mtc1 r<RT>, f<FS>"
6149 *mipsIV:
6150 *mipsV:
6151 *mips32:
6152 *mips32r2:
6153 *mips32r6:
6154 *mips64:
6155 *mips64r2:
6156 *mips64r6:
6157 *vr4100:
6158 *vr5000:
6159 *r3900:
6160 {
6161   do_mtc1b (SD_, RT, FS);
6162 }
6163
6164
6165 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
6166 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
6167 *mipsI:
6168 *mipsII:
6169 *mipsIII:
6170 *mipsIV:
6171 *mipsV:
6172 *mips32:
6173 *mips32r2:
6174 *mips32r6:
6175 *mips64:
6176 *mips64r2:
6177 *mips64r6:
6178 *vr4100:
6179 *vr5000:
6180 *r3900:
6181 {
6182   do_mul_fmt (SD_, FMT, FD, FS, FT, instruction_0);
6183 }
6184
6185
6186 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
6187 "neg.%s<FMT> f<FD>, f<FS>"
6188 *mipsI:
6189 *mipsII:
6190 *mipsIII:
6191 *mipsIV:
6192 *mipsV:
6193 *mips32:
6194 *mips32r2:
6195 *mips32r6:
6196 *mips64:
6197 *mips64r2:
6198 *mips64r6:
6199 *vr4100:
6200 *vr5000:
6201 *r3900:
6202 {
6203   do_neg_fmt (SD_, FMT, FD, FS, instruction_0);
6204 }
6205
6206
6207 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:32,f::NMADD.fmt
6208 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
6209 *mipsIV:
6210 *mipsV:
6211 *mips32r2:
6212 *mips64:
6213 *mips64r2:
6214 *vr5000:
6215 {
6216   do_nmadd_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
6217 }
6218
6219
6220 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:32,f::NMSUB.fmt
6221 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
6222 *mipsIV:
6223 *mipsV:
6224 *mips32r2:
6225 *mips64:
6226 *mips64r2:
6227 *vr5000:
6228 {
6229   do_nmsub_fmt (SD_, FMT, FD, FR, FS, FT, instruction_0);
6230 }
6231
6232
6233 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:32,f::PLL.PS
6234 "pll.ps f<FD>, f<FS>, f<FT>"
6235 *mipsV:
6236 *mips32r2:
6237 *mips64:
6238 *mips64r2:
6239 {
6240   do_pll_ps (SD_, FD, FS, FT, instruction_0);
6241 }
6242
6243
6244 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:32,f::PLU.PS
6245 "plu.ps f<FD>, f<FS>, f<FT>"
6246 *mipsV:
6247 *mips32r2:
6248 *mips64:
6249 *mips64r2:
6250 {
6251   do_plu_ps (SD_, FD, FS, FT, instruction_0);
6252 }
6253
6254
6255 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:32::PREFX
6256 "prefx <HINT>, r<INDEX>(r<BASE>)"
6257 *mipsIV:
6258 *mipsV:
6259 *mips32r2:
6260 *mips64:
6261 *mips64r2:
6262 *vr5000:
6263 {
6264   do_prefx (SD_, HINT, INDEX, BASE);
6265 }
6266
6267
6268 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:32,f::PUL.PS
6269 "pul.ps f<FD>, f<FS>, f<FT>"
6270 *mipsV:
6271 *mips32r2:
6272 *mips64:
6273 *mips64r2:
6274 {
6275   do_pul_ps (SD_, FD, FS, FT, instruction_0);
6276 }
6277
6278
6279 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:32,f::PUU.PS
6280 "puu.ps f<FD>, f<FS>, f<FT>"
6281 *mipsV:
6282 *mips32r2:
6283 *mips64:
6284 *mips64r2:
6285 {
6286   do_puu_ps (SD_, FD, FS, FT, instruction_0);
6287 }
6288
6289
6290 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
6291 "recip.%s<FMT> f<FD>, f<FS>"
6292 *mipsIV:
6293 *mipsV:
6294 *mips32r2:
6295 *mips32r6:
6296 *mips64:
6297 *mips64r2:
6298 *mips64r6:
6299 *vr5000:
6300 {
6301   do_recip_fmt (SD_, FMT, FD, FS);
6302 }
6303
6304
6305 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:32,f::ROUND.L.fmt
6306 "round.l.%s<FMT> f<FD>, f<FS>"
6307 *mipsIII:
6308 *mipsIV:
6309 *mipsV:
6310 *mips32r2:
6311 *mips32r6:
6312 *mips64:
6313 *mips64r2:
6314 *mips64r6:
6315 *vr4100:
6316 *vr5000:
6317 *r3900:
6318 {
6319   do_round_fmt (SD_, fmt_long, FMT, FD, FS);
6320 }
6321
6322
6323 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
6324 "round.w.%s<FMT> f<FD>, f<FS>"
6325 *mipsII:
6326 *mipsIII:
6327 *mipsIV:
6328 *mipsV:
6329 *mips32:
6330 *mips32r2:
6331 *mips32r6:
6332 *mips64:
6333 *mips64r2:
6334 *mips64r6:
6335 *vr4100:
6336 *vr5000:
6337 *r3900:
6338 {
6339   do_round_fmt (SD_, fmt_word, FMT, FD, FS);
6340 }
6341
6342
6343 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
6344 "rsqrt.%s<FMT> f<FD>, f<FS>"
6345 *mipsIV:
6346 *mipsV:
6347 *mips32r2:
6348 *mips32r6:
6349 *mips64:
6350 *mips64r2:
6351 *mips64r6:
6352 *vr5000:
6353 {
6354   do_rsqrt_fmt (SD_, FMT, FD, FS);
6355 }
6356
6357
6358 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
6359 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
6360 *mipsII:
6361 *mips32:
6362 *mips32r2:
6363 *mips32r6:
6364 {
6365   do_sdc1 (SD_, FT, OFFSET, BASE);
6366 }
6367
6368
6369 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
6370 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
6371 *mipsIII:
6372 *mipsIV:
6373 *mipsV:
6374 *mips64:
6375 *mips64r2:
6376 *mips64r6:
6377 *vr4100:
6378 *vr5000:
6379 *r3900:
6380 {
6381   check_fpu (SD_);
6382   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
6383 }
6384
6385
6386 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:32,f::SDXC1
6387 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
6388 *mips32r2:
6389 {
6390   check_fpu (SD_);
6391   do_store_double (SD_, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
6392 }
6393
6394
6395 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
6396 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
6397 *mipsIV:
6398 *mipsV:
6399 *mips64:
6400 *mips64r2:
6401 *vr5000:
6402 {
6403   check_fpu (SD_);
6404   check_u64 (SD_, instruction_0);
6405   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
6406 }
6407
6408
6409 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:32,f::SUXC1
6410 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
6411 *mips32r2:
6412 {
6413   do_suxc1_32 (SD_, FS, INDEX, BASE);
6414 }
6415
6416
6417 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
6418 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
6419 *mipsV:
6420 *mips64:
6421 *mips64r2:
6422 {
6423   check_fpu (SD_);
6424   check_u64 (SD_, instruction_0);
6425   do_suxc1_64 (SD_, FS, INDEX, BASE);
6426 }
6427
6428
6429 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
6430 "sqrt.%s<FMT> f<FD>, f<FS>"
6431 *mipsII:
6432 *mipsIII:
6433 *mipsIV:
6434 *mipsV:
6435 *mips32:
6436 *mips32r2:
6437 *mips32r6:
6438 *mips64:
6439 *mips64r2:
6440 *mips64r6:
6441 *vr4100:
6442 *vr5000:
6443 *r3900:
6444 {
6445   do_sqrt_fmt (SD_, FMT, FD, FS);
6446 }
6447
6448
6449 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
6450 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
6451 *mipsI:
6452 *mipsII:
6453 *mipsIII:
6454 *mipsIV:
6455 *mipsV:
6456 *mips32:
6457 *mips32r2:
6458 *mips32r6:
6459 *mips64:
6460 *mips64r2:
6461 *mips64r6:
6462 *vr4100:
6463 *vr5000:
6464 *r3900:
6465 {
6466   do_sub_fmt (SD_, FMT, FD, FS, FT, instruction_0);
6467 }
6468
6469
6470
6471 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
6472 "swc1 f<FT>, <OFFSET>(r<BASE>)"
6473 *mipsI:
6474 *mipsII:
6475 *mipsIII:
6476 *mipsIV:
6477 *mipsV:
6478 *mips32:
6479 *mips32r2:
6480 *mips32r6:
6481 *mips64:
6482 *mips64r2:
6483 *mips64r6:
6484 *vr4100:
6485 *vr5000:
6486 *r3900:
6487 {
6488   do_swc1 (SD_, FT, OFFSET, BASE, instruction_0);
6489 }
6490
6491
6492 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
6493 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
6494 *mipsIV:
6495 *mipsV:
6496 *mips32r2:
6497 *mips64:
6498 *mips64r2:
6499 *vr5000:
6500 {
6501   do_swxc1 (SD_, FS, INDEX, BASE, instruction_0);
6502 }
6503
6504
6505 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:32,f::TRUNC.L.fmt
6506 "trunc.l.%s<FMT> f<FD>, f<FS>"
6507 *mipsIII:
6508 *mipsIV:
6509 *mipsV:
6510 *mips32r2:
6511 *mips32r6:
6512 *mips64:
6513 *mips64r2:
6514 *mips64r6:
6515 *vr4100:
6516 *vr5000:
6517 *r3900:
6518 {
6519   do_trunc_fmt (SD_, fmt_long, FMT, FD, FS);
6520 }
6521
6522
6523 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
6524 "trunc.w.%s<FMT> f<FD>, f<FS>"
6525 *mipsII:
6526 *mipsIII:
6527 *mipsIV:
6528 *mipsV:
6529 *mips32:
6530 *mips32r2:
6531 *mips32r6:
6532 *mips64:
6533 *mips64r2:
6534 *mips64r6:
6535 *vr4100:
6536 *vr5000:
6537 *r3900:
6538 {
6539   do_trunc_fmt (SD_, fmt_word, FMT, FD, FS);
6540 }
6541
6542
6543 //
6544 // MIPS Architecture:
6545 //
6546 //        System Control Instruction Set (COP0)
6547 //
6548
6549
6550 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6551 "bc0f <OFFSET>"
6552 *mipsI:
6553 *mipsII:
6554 *mipsIII:
6555 *mipsIV:
6556 *mipsV:
6557 *mips32:
6558 *mips32r2:
6559 *mips32r6:
6560 *mips64:
6561 *mips64r2:
6562 *mips64r6:
6563 *vr4100:
6564 *vr5000:
6565
6566 010000,01000,00000,16.OFFSET:COP0:32::BC0F
6567 "bc0f <OFFSET>"
6568 // stub needed for eCos as tx39 hardware bug workaround
6569 *r3900:
6570 {
6571   /* do nothing */
6572 }
6573
6574
6575 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
6576 "bc0fl <OFFSET>"
6577 *mipsI:
6578 *mipsII:
6579 *mipsIII:
6580 *mipsIV:
6581 *mipsV:
6582 *mips32:
6583 *mips32r2:
6584 *mips32r6:
6585 *mips64:
6586 *mips64r2:
6587 *mips64r6:
6588 *vr4100:
6589 *vr5000:
6590
6591
6592 010000,01000,00001,16.OFFSET:COP0:32::BC0T
6593 "bc0t <OFFSET>"
6594 *mipsI:
6595 *mipsII:
6596 *mipsIII:
6597 *mipsIV:
6598 *mipsV:
6599 *mips32:
6600 *mips32r2:
6601 *mips32r6:
6602 *mips64:
6603 *mips64r2:
6604 *mips64r6:
6605 *vr4100:
6606
6607
6608 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
6609 "bc0tl <OFFSET>"
6610 *mipsI:
6611 *mipsII:
6612 *mipsIII:
6613 *mipsIV:
6614 *mipsV:
6615 *mips32:
6616 *mips32r2:
6617 *mips32r6:
6618 *mips64:
6619 *mips64r2:
6620 *mips64r6:
6621 *vr4100:
6622 *vr5000:
6623
6624 :function:::void:do_cache:int op, int rbase, int roffset, address_word instruction_0
6625 {
6626   address_word base = GPR[rbase];
6627   address_word offset = EXTEND16 (roffset);
6628   {
6629     address_word vaddr = loadstore_ea (SD_, base, offset);
6630     address_word paddr = vaddr;
6631     CacheOp(op, vaddr, paddr, instruction_0);
6632   }
6633 }
6634
6635 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
6636 "cache <OP>, <OFFSET>(r<BASE>)"
6637 *mipsIII:
6638 *mipsIV:
6639 *mipsV:
6640 *mips32:
6641 *mips32r2:
6642 *mips64:
6643 *mips64r2:
6644 *vr4100:
6645 *vr5000:
6646 *r3900:
6647 {
6648   do_cache (SD_, OP, BASE, OFFSET, instruction_0);
6649 }
6650
6651
6652 010000,00001,5.RT,5.RD,00000000,3.SEL:COP0:64::DMFC0
6653 "dmfc0 r<RT>, r<RD>"
6654 *mipsIII:
6655 *mipsIV:
6656 *mipsV:
6657 *mips64:
6658 *mips64r2:
6659 *mips64r6:
6660 {
6661   check_u64 (SD_, instruction_0);
6662   DecodeCoproc (instruction_0, 0, cp0_dmfc0, RT, RD, SEL);
6663 }
6664
6665
6666 010000,00101,5.RT,5.RD,00000000,3.SEL:COP0:64::DMTC0
6667 "dmtc0 r<RT>, r<RD>"
6668 *mipsIII:
6669 *mipsIV:
6670 *mipsV:
6671 *mips64:
6672 *mips64r2:
6673 *mips64r6:
6674 {
6675   check_u64 (SD_, instruction_0);
6676   DecodeCoproc (instruction_0, 0, cp0_dmtc0, RT, RD, SEL);
6677 }
6678
6679
6680 010000,1,0000000000000000000,011000:COP0:32::ERET
6681 "eret"
6682 *mipsIII:
6683 *mipsIV:
6684 *mipsV:
6685 *mips32:
6686 *mips32r2:
6687 *mips32r6:
6688 *mips64:
6689 *mips64r2:
6690 *mips64r6:
6691 *vr4100:
6692 *vr5000:
6693 {
6694   if (SR & status_ERL)
6695     {
6696       /* Oops, not yet available */
6697       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
6698       NIA = EPC;
6699       SR &= ~status_ERL;
6700     }
6701   else
6702     {
6703       NIA = EPC;
6704       SR &= ~status_EXL;
6705     }
6706 }
6707
6708
6709 010000,00000,5.RT,5.RD,00000000,3.SEL:COP0:32::MFC0
6710 "mfc0 r<RT>, r<RD> # <SEL>"
6711 *mipsI:
6712 *mipsII:
6713 *mipsIII:
6714 *mipsIV:
6715 *mipsV:
6716 *mips32:
6717 *mips32r2:
6718 *mips32r6:
6719 *mips64:
6720 *mips64r2:
6721 *mips64r6:
6722 *vr4100:
6723 *vr5000:
6724 *r3900:
6725 {
6726   TRACE_ALU_INPUT0 ();
6727   DecodeCoproc (instruction_0, 0, cp0_mfc0, RT, RD, SEL);
6728   TRACE_ALU_RESULT (GPR[RT]);
6729 }
6730
6731 010000,00100,5.RT,5.RD,00000000,3.SEL:COP0:32::MTC0
6732 "mtc0 r<RT>, r<RD> # <SEL>"
6733 *mipsI:
6734 *mipsII:
6735 *mipsIII:
6736 *mipsIV:
6737 *mipsV:
6738 *mips32:
6739 *mips32r2:
6740 *mips32r6:
6741 *mips64:
6742 *mips64r2:
6743 *mips64r6:
6744 *vr4100:
6745 *vr5000:
6746 *r3900:
6747 {
6748   DecodeCoproc (instruction_0, 0, cp0_mtc0, RT, RD, SEL);
6749 }
6750
6751
6752 010000,1,0000000000000000000,010000:COP0:32::RFE
6753 "rfe"
6754 *mipsI:
6755 *mipsII:
6756 *mipsIII:
6757 *mipsIV:
6758 *mipsV:
6759 *vr4100:
6760 *vr5000:
6761 *r3900:
6762 {
6763   DecodeCoproc (instruction_0, 0, cp0_rfe, 0, 0, 0x10);
6764 }
6765
6766
6767 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
6768 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
6769 *mipsI:
6770 *mipsII:
6771 *mipsIII:
6772 *mipsIV:
6773 *mipsV:
6774 *mips32:
6775 *mips32r2:
6776 *mips32r6:
6777 *mips64:
6778 *mips64r2:
6779 *mips64r6:
6780 *vr4100:
6781 *r3900:
6782 {
6783   DecodeCoproc (instruction_0, 2, 0, 0, 0, 0);
6784 }
6785
6786
6787
6788 010000,1,0000000000000000000,001000:COP0:32::TLBP
6789 "tlbp"
6790 *mipsI:
6791 *mipsII:
6792 *mipsIII:
6793 *mipsIV:
6794 *mipsV:
6795 *mips32:
6796 *mips32r2:
6797 *mips32r6:
6798 *mips64:
6799 *mips64r2:
6800 *mips64r6:
6801 *vr4100:
6802 *vr5000:
6803
6804
6805 010000,1,0000000000000000000,000001:COP0:32::TLBR
6806 "tlbr"
6807 *mipsI:
6808 *mipsII:
6809 *mipsIII:
6810 *mipsIV:
6811 *mipsV:
6812 *mips32:
6813 *mips32r2:
6814 *mips32r6:
6815 *mips64:
6816 *mips64r2:
6817 *mips64r6:
6818 *vr4100:
6819 *vr5000:
6820
6821
6822 010000,1,0000000000000000000,000010:COP0:32::TLBWI
6823 "tlbwi"
6824 *mipsI:
6825 *mipsII:
6826 *mipsIII:
6827 *mipsIV:
6828 *mipsV:
6829 *mips32:
6830 *mips32r2:
6831 *mips32r6:
6832 *mips64:
6833 *mips64r2:
6834 *mips64r6:
6835 *vr4100:
6836 *vr5000:
6837
6838
6839 010000,1,0000000000000000000,000110:COP0:32::TLBWR
6840 "tlbwr"
6841 *mipsI:
6842 *mipsII:
6843 *mipsIII:
6844 *mipsIV:
6845 *mipsV:
6846 *mips32:
6847 *mips32r2:
6848 *mips32r6:
6849 *mips64:
6850 *mips64r2:
6851 *mips64r6:
6852 *vr4100:
6853 *vr5000:
6854
6855
6856 :include:::mips3264r2.igen
6857 :include:::mips3264r6.igen
6858 :include:::m16.igen
6859 :include:::m16e.igen
6860 :include:::mdmx.igen
6861 :include:::mips3d.igen
6862 :include:::sb1.igen
6863 :include:::tx.igen
6864 :include:::vr.igen
6865 :include:::dsp.igen
6866 :include:::dsp2.igen
6867 :include:::smartmips.igen
6868 :include:::micromips.igen
6869 :include:::micromipsdsp.igen
6870