sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator are defined below.
  38 //
  39 // When placing models in the instruction descriptions, please place
  40 // them one per line, in the order given here.
  41
  42 //  MIPS ISAs:
  43 //
  44 //  Instructions and related functions for these models are included in
  45 //  this file.
  46 :model:::mipsI:mips3000:
  47 :model:::mipsII:mips6000:
  48 :model:::mipsIII:mips4000:
  49 :model:::mipsIV:mips8000:
  50 :model:::mipsV:mipsisaV:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr5000:mips5000:
  61 :model:::r3900:mips3900:                // tx.igen
  62
  63 //  MIPS Application Specific Extensions (ASEs)
  64 //
  65 //  Instructions for the ASEs are in separate .igen files.
  66 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  67
  68
  69 // Pseudo instructions known by IGEN
  70 :internal::::illegal:
  71 {
  72   SignalException (ReservedInstruction, 0);
  73 }
  74
  75
  76 // Pseudo instructions known by interp.c
  77 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  78 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  79 "rsvd <OP>"
  80 {
  81   SignalException (ReservedInstruction, instruction_0);
  82 }
  83
  84
  85
  86 // Helper:
  87 //
  88 // Simulate a 32 bit delayslot instruction
  89 //
  90
  91 :function:::address_word:delayslot32:address_word target
  92 {
  93   instruction_word delay_insn;
  94   sim_events_slip (SD, 1);
  95   DSPC = CIA;
  96   CIA = CIA + 4; /* NOTE not mips16 */
  97   STATE |= simDELAYSLOT;
  98   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  99   ENGINE_ISSUE_PREFIX_HOOK();
 100   idecode_issue (CPU_, delay_insn, (CIA));
 101   STATE &= ~simDELAYSLOT;
 102   return target;
 103 }
 104
 105 :function:::address_word:nullify_next_insn32:
 106 {
 107   sim_events_slip (SD, 1);
 108   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 109   return CIA + 8;
 110 }
 111
 112 // Helper:
 113 //
 114 // Check that an access to a HI/LO register meets timing requirements
 115 //
 116 // The following requirements exist:
 117 //
 118 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 119 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 120 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 121 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 122 //
 123
 124 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 125 {
 126   if (history->mf.timestamp + 3 > time)
 127     {
 128       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 129                         itable[MY_INDEX].name,
 130                         new, (long) CIA,
 131                         (long) history->mf.cia);
 132       return 0;
 133     }
 134   return 1;
 135 }
 136
 137 :function:::int:check_mt_hilo:hilo_history *history
 138 *mipsI:
 139 *mipsII:
 140 *mipsIII:
 141 *mipsIV:
 142 *mipsV:
 143 *vr4100:
 144 *vr5000:
 145 {
 146   signed64 time = sim_events_time (SD);
 147   int ok = check_mf_cycles (SD_, history, time, "MT");
 148   history->mt.timestamp = time;
 149   history->mt.cia = CIA;
 150   return ok;
 151 }
 152
 153 :function:::int:check_mt_hilo:hilo_history *history
 154 *r3900:
 155 {
 156   signed64 time = sim_events_time (SD);
 157   history->mt.timestamp = time;
 158   history->mt.cia = CIA;
 159   return 1;
 160 }
 161
 162
 163 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 164 *mipsI:
 165 *mipsII:
 166 *mipsIII:
 167 *mipsIV:
 168 *mipsV:
 169 *vr4100:
 170 *vr5000:
 171 *r3900:
 172 {
 173   signed64 time = sim_events_time (SD);
 174   int ok = 1;
 175   if (peer != NULL
 176       && peer->mt.timestamp > history->op.timestamp
 177       && history->mt.timestamp < history->op.timestamp
 178       && ! (history->mf.timestamp > history->op.timestamp
 179             && history->mf.timestamp < peer->mt.timestamp)
 180       && ! (peer->mf.timestamp > history->op.timestamp
 181             && peer->mf.timestamp < peer->mt.timestamp))
 182     {
 183       /* The peer has been written to since the last OP yet we have
 184          not */
 185       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 186                         itable[MY_INDEX].name,
 187                         (long) CIA,
 188                         (long) history->op.cia,
 189                         (long) peer->mt.cia);
 190       ok = 0;
 191     }
 192   history->mf.timestamp = time;
 193   history->mf.cia = CIA;
 194   return ok;
 195 }
 196
 197
 198
 199 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 200 *mipsI:
 201 *mipsII:
 202 *mipsIII:
 203 *mipsIV:
 204 *mipsV:
 205 *vr4100:
 206 *vr5000:
 207 {
 208   signed64 time = sim_events_time (SD);
 209   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 210             && check_mf_cycles (SD_, lo, time, "OP"));
 211   hi->op.timestamp = time;
 212   lo->op.timestamp = time;
 213   hi->op.cia = CIA;
 214   lo->op.cia = CIA;
 215   return ok;
 216 }
 217
 218 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 219 // a mf{hi,lo}
 220 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 221 *r3900:
 222 {
 223   /* FIXME: could record the fact that a stall occured if we want */
 224   signed64 time = sim_events_time (SD);
 225   hi->op.timestamp = time;
 226   lo->op.timestamp = time;
 227   hi->op.cia = CIA;
 228   lo->op.cia = CIA;
 229   return 1;
 230 }
 231
 232
 233 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 234 *mipsI:
 235 *mipsII:
 236 *mipsIII:
 237 *mipsIV:
 238 *mipsV:
 239 *vr4100:
 240 *vr5000:
 241 *r3900:
 242 {
 243   signed64 time = sim_events_time (SD);
 244   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 245             && check_mf_cycles (SD_, lo, time, "OP"));
 246   hi->op.timestamp = time;
 247   lo->op.timestamp = time;
 248   hi->op.cia = CIA;
 249   lo->op.cia = CIA;
 250   return ok;
 251 }
 252
 253
 254 // Helper:
 255 //
 256 // Check that the 64-bit instruction can currently be used, and signal
 257 // an ReservedInstruction exception if not.
 258 //
 259
 260 :function:::void:check_u64:instruction_word insn
 261 *mipsIII:
 262 *mipsIV:
 263 *mipsV:
 264 *vr4100:
 265 *vr5000:
 266 {
 267   // On mips64, if UserMode check SR:PX & SR:UX bits.
 268   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 269 }
 270
 271
 272
 273 //
 274 // MIPS Architecture:
 275 //
 276 //        CPU Instruction Set (mipsI - mipsV)
 277 //
 278
 279
 280
 281 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 282 "add r<RD>, r<RS>, r<RT>"
 283 *mipsI:
 284 *mipsII:
 285 *mipsIII:
 286 *mipsIV:
 287 *mipsV:
 288 *vr4100:
 289 *vr5000:
 290 *r3900:
 291 {
 292   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 293   {
 294     ALU32_BEGIN (GPR[RS]);
 295     ALU32_ADD (GPR[RT]);
 296     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 297   }
 298   TRACE_ALU_RESULT (GPR[RD]);
 299 }
 300
 301
 302
 303 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 304 "addi r<RT>, r<RS>, <IMMEDIATE>"
 305 *mipsI:
 306 *mipsII:
 307 *mipsIII:
 308 *mipsIV:
 309 *mipsV:
 310 *vr4100:
 311 *vr5000:
 312 *r3900:
 313 {
 314   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 315   {
 316     ALU32_BEGIN (GPR[RS]);
 317     ALU32_ADD (EXTEND16 (IMMEDIATE));
 318     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 319   }
 320   TRACE_ALU_RESULT (GPR[RT]);
 321 }
 322
 323
 324
 325 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 326 {
 327   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 328   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 329   TRACE_ALU_RESULT (GPR[rt]);
 330 }
 331
 332 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 333 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 334 *mipsI:
 335 *mipsII:
 336 *mipsIII:
 337 *mipsIV:
 338 *mipsV:
 339 *vr4100:
 340 *vr5000:
 341 *r3900:
 342 {
 343   do_addiu (SD_, RS, RT, IMMEDIATE);
 344 }
 345
 346
 347
 348 :function:::void:do_addu:int rs, int rt, int rd
 349 {
 350   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 351   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 352   TRACE_ALU_RESULT (GPR[rd]);
 353 }
 354
 355 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 356 "addu r<RD>, r<RS>, r<RT>"
 357 *mipsI:
 358 *mipsII:
 359 *mipsIII:
 360 *mipsIV:
 361 *mipsV:
 362 *vr4100:
 363 *vr5000:
 364 *r3900:
 365 {
 366   do_addu (SD_, RS, RT, RD);
 367 }
 368
 369
 370
 371 :function:::void:do_and:int rs, int rt, int rd
 372 {
 373   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 374   GPR[rd] = GPR[rs] & GPR[rt];
 375   TRACE_ALU_RESULT (GPR[rd]);
 376 }
 377
 378 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 379 "and r<RD>, r<RS>, r<RT>"
 380 *mipsI:
 381 *mipsII:
 382 *mipsIII:
 383 *mipsIV:
 384 *mipsV:
 385 *vr4100:
 386 *vr5000:
 387 *r3900:
 388 {
 389   do_and (SD_, RS, RT, RD);
 390 }
 391
 392
 393
 394 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 395 "and r<RT>, r<RS>, <IMMEDIATE>"
 396 *mipsI:
 397 *mipsII:
 398 *mipsIII:
 399 *mipsIV:
 400 *mipsV:
 401 *vr4100:
 402 *vr5000:
 403 *r3900:
 404 {
 405   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 406   GPR[RT] = GPR[RS] & IMMEDIATE;
 407   TRACE_ALU_RESULT (GPR[RT]);
 408 }
 409
 410
 411
 412 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 413 "beq r<RS>, r<RT>, <OFFSET>"
 414 *mipsI:
 415 *mipsII:
 416 *mipsIII:
 417 *mipsIV:
 418 *mipsV:
 419 *vr4100:
 420 *vr5000:
 421 *r3900:
 422 {
 423   address_word offset = EXTEND16 (OFFSET) << 2;
 424   check_branch_bug ();
 425   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 426     {
 427       mark_branch_bug (NIA+offset);
 428       DELAY_SLOT (NIA + offset);
 429     }
 430 }
 431
 432
 433
 434 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 435 "beql r<RS>, r<RT>, <OFFSET>"
 436 *mipsII:
 437 *mipsIII:
 438 *mipsIV:
 439 *mipsV:
 440 *vr4100:
 441 *vr5000:
 442 *r3900:
 443 {
 444   address_word offset = EXTEND16 (OFFSET) << 2;
 445   check_branch_bug ();
 446   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 447     {
 448       mark_branch_bug (NIA+offset);
 449       DELAY_SLOT (NIA + offset);
 450     }
 451   else
 452     NULLIFY_NEXT_INSTRUCTION ();
 453 }
 454
 455
 456
 457 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 458 "bgez r<RS>, <OFFSET>"
 459 *mipsI:
 460 *mipsII:
 461 *mipsIII:
 462 *mipsIV:
 463 *mipsV:
 464 *vr4100:
 465 *vr5000:
 466 *r3900:
 467 {
 468   address_word offset = EXTEND16 (OFFSET) << 2;
 469   check_branch_bug ();
 470   if ((signed_word) GPR[RS] >= 0)
 471     {
 472       mark_branch_bug (NIA+offset);
 473       DELAY_SLOT (NIA + offset);
 474     }
 475 }
 476
 477
 478
 479 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 480 "bgezal r<RS>, <OFFSET>"
 481 *mipsI:
 482 *mipsII:
 483 *mipsIII:
 484 *mipsIV:
 485 *mipsV:
 486 *vr4100:
 487 *vr5000:
 488 *r3900:
 489 {
 490   address_word offset = EXTEND16 (OFFSET) << 2;
 491   check_branch_bug ();
 492   RA = (CIA + 8);
 493   if ((signed_word) GPR[RS] >= 0)
 494     {
 495       mark_branch_bug (NIA+offset);
 496       DELAY_SLOT (NIA + offset);
 497     }
 498 }
 499
 500
 501
 502 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 503 "bgezall r<RS>, <OFFSET>"
 504 *mipsII:
 505 *mipsIII:
 506 *mipsIV:
 507 *mipsV:
 508 *vr4100:
 509 *vr5000:
 510 *r3900:
 511 {
 512   address_word offset = EXTEND16 (OFFSET) << 2;
 513   check_branch_bug ();
 514   RA = (CIA + 8);
 515   /* NOTE: The branch occurs AFTER the next instruction has been
 516      executed */
 517   if ((signed_word) GPR[RS] >= 0)
 518     {
 519       mark_branch_bug (NIA+offset);
 520       DELAY_SLOT (NIA + offset);
 521     }
 522   else
 523     NULLIFY_NEXT_INSTRUCTION ();
 524 }
 525
 526
 527
 528 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 529 "bgezl r<RS>, <OFFSET>"
 530 *mipsII:
 531 *mipsIII:
 532 *mipsIV:
 533 *mipsV:
 534 *vr4100:
 535 *vr5000:
 536 *r3900:
 537 {
 538   address_word offset = EXTEND16 (OFFSET) << 2;
 539   check_branch_bug ();
 540   if ((signed_word) GPR[RS] >= 0)
 541     {
 542       mark_branch_bug (NIA+offset);
 543       DELAY_SLOT (NIA + offset);
 544     }
 545   else
 546     NULLIFY_NEXT_INSTRUCTION ();
 547 }
 548
 549
 550
 551 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 552 "bgtz r<RS>, <OFFSET>"
 553 *mipsI:
 554 *mipsII:
 555 *mipsIII:
 556 *mipsIV:
 557 *mipsV:
 558 *vr4100:
 559 *vr5000:
 560 *r3900:
 561 {
 562   address_word offset = EXTEND16 (OFFSET) << 2;
 563   check_branch_bug ();
 564   if ((signed_word) GPR[RS] > 0)
 565     {
 566       mark_branch_bug (NIA+offset);
 567       DELAY_SLOT (NIA + offset);
 568     }
 569 }
 570
 571
 572
 573 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 574 "bgtzl r<RS>, <OFFSET>"
 575 *mipsII:
 576 *mipsIII:
 577 *mipsIV:
 578 *mipsV:
 579 *vr4100:
 580 *vr5000:
 581 *r3900:
 582 {
 583   address_word offset = EXTEND16 (OFFSET) << 2;
 584   check_branch_bug ();
 585   /* NOTE: The branch occurs AFTER the next instruction has been
 586      executed */
 587   if ((signed_word) GPR[RS] > 0)
 588     {
 589       mark_branch_bug (NIA+offset);
 590       DELAY_SLOT (NIA + offset);
 591     }
 592   else
 593     NULLIFY_NEXT_INSTRUCTION ();
 594 }
 595
 596
 597
 598 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 599 "blez r<RS>, <OFFSET>"
 600 *mipsI:
 601 *mipsII:
 602 *mipsIII:
 603 *mipsIV:
 604 *mipsV:
 605 *vr4100:
 606 *vr5000:
 607 *r3900:
 608 {
 609   address_word offset = EXTEND16 (OFFSET) << 2;
 610   check_branch_bug ();
 611   /* NOTE: The branch occurs AFTER the next instruction has been
 612      executed */
 613   if ((signed_word) GPR[RS] <= 0)
 614     {
 615       mark_branch_bug (NIA+offset);
 616       DELAY_SLOT (NIA + offset);
 617     }
 618 }
 619
 620
 621
 622 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 623 "bgezl r<RS>, <OFFSET>"
 624 *mipsII:
 625 *mipsIII:
 626 *mipsIV:
 627 *mipsV:
 628 *vr4100:
 629 *vr5000:
 630 *r3900:
 631 {
 632   address_word offset = EXTEND16 (OFFSET) << 2;
 633   check_branch_bug ();
 634   if ((signed_word) GPR[RS] <= 0)
 635     {
 636       mark_branch_bug (NIA+offset);
 637       DELAY_SLOT (NIA + offset);
 638     }
 639   else
 640     NULLIFY_NEXT_INSTRUCTION ();
 641 }
 642
 643
 644
 645 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 646 "bltz r<RS>, <OFFSET>"
 647 *mipsI:
 648 *mipsII:
 649 *mipsIII:
 650 *mipsIV:
 651 *mipsV:
 652 *vr4100:
 653 *vr5000:
 654 *r3900:
 655 {
 656   address_word offset = EXTEND16 (OFFSET) << 2;
 657   check_branch_bug ();
 658   if ((signed_word) GPR[RS] < 0)
 659     {
 660       mark_branch_bug (NIA+offset);
 661       DELAY_SLOT (NIA + offset);
 662     }
 663 }
 664
 665
 666
 667 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 668 "bltzal r<RS>, <OFFSET>"
 669 *mipsI:
 670 *mipsII:
 671 *mipsIII:
 672 *mipsIV:
 673 *mipsV:
 674 *vr4100:
 675 *vr5000:
 676 *r3900:
 677 {
 678   address_word offset = EXTEND16 (OFFSET) << 2;
 679   check_branch_bug ();
 680   RA = (CIA + 8);
 681   /* NOTE: The branch occurs AFTER the next instruction has been
 682      executed */
 683   if ((signed_word) GPR[RS] < 0)
 684     {
 685       mark_branch_bug (NIA+offset);
 686       DELAY_SLOT (NIA + offset);
 687     }
 688 }
 689
 690
 691
 692 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 693 "bltzall r<RS>, <OFFSET>"
 694 *mipsII:
 695 *mipsIII:
 696 *mipsIV:
 697 *mipsV:
 698 *vr4100:
 699 *vr5000:
 700 *r3900:
 701 {
 702   address_word offset = EXTEND16 (OFFSET) << 2;
 703   check_branch_bug ();
 704   RA = (CIA + 8);
 705   if ((signed_word) GPR[RS] < 0)
 706     {
 707       mark_branch_bug (NIA+offset);
 708       DELAY_SLOT (NIA + offset);
 709     }
 710   else
 711     NULLIFY_NEXT_INSTRUCTION ();
 712 }
 713
 714
 715
 716 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 717 "bltzl r<RS>, <OFFSET>"
 718 *mipsII:
 719 *mipsIII:
 720 *mipsIV:
 721 *mipsV:
 722 *vr4100:
 723 *vr5000:
 724 *r3900:
 725 {
 726   address_word offset = EXTEND16 (OFFSET) << 2;
 727   check_branch_bug ();
 728   /* NOTE: The branch occurs AFTER the next instruction has been
 729      executed */
 730   if ((signed_word) GPR[RS] < 0)
 731     {
 732       mark_branch_bug (NIA+offset);
 733       DELAY_SLOT (NIA + offset);
 734     }
 735   else
 736     NULLIFY_NEXT_INSTRUCTION ();
 737 }
 738
 739
 740
 741 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 742 "bne r<RS>, r<RT>, <OFFSET>"
 743 *mipsI:
 744 *mipsII:
 745 *mipsIII:
 746 *mipsIV:
 747 *mipsV:
 748 *vr4100:
 749 *vr5000:
 750 *r3900:
 751 {
 752   address_word offset = EXTEND16 (OFFSET) << 2;
 753   check_branch_bug ();
 754   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 755     {
 756       mark_branch_bug (NIA+offset);
 757       DELAY_SLOT (NIA + offset);
 758     }
 759 }
 760
 761
 762
 763 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 764 "bnel r<RS>, r<RT>, <OFFSET>"
 765 *mipsII:
 766 *mipsIII:
 767 *mipsIV:
 768 *mipsV:
 769 *vr4100:
 770 *vr5000:
 771 *r3900:
 772 {
 773   address_word offset = EXTEND16 (OFFSET) << 2;
 774   check_branch_bug ();
 775   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 776     {
 777       mark_branch_bug (NIA+offset);
 778       DELAY_SLOT (NIA + offset);
 779     }
 780   else
 781     NULLIFY_NEXT_INSTRUCTION ();
 782 }
 783
 784
 785
 786 000000,20.CODE,001101:SPECIAL:32::BREAK
 787 "break <CODE>"
 788 *mipsI:
 789 *mipsII:
 790 *mipsIII:
 791 *mipsIV:
 792 *mipsV:
 793 *vr4100:
 794 *vr5000:
 795 *r3900:
 796 {
 797   /* Check for some break instruction which are reserved for use by the simulator.  */
 798   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 799   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 800       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 801     {
 802       sim_engine_halt (SD, CPU, NULL, cia,
 803                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 804     }
 805   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 806            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 807     {
 808       if (STATE & simDELAYSLOT)
 809         PC = cia - 4; /* reference the branch instruction */
 810       else
 811         PC = cia;
 812       SignalException(BreakPoint, instruction_0);
 813     }
 814
 815   else
 816     {
 817       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 818          the exception. */
 819       SignalException(BreakPoint, instruction_0);
 820     }
 821 }
 822
 823
 824
 825 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 826 "dadd r<RD>, r<RS>, r<RT>"
 827 *mipsIII:
 828 *mipsIV:
 829 *mipsV:
 830 *vr4100:
 831 *vr5000:
 832 {
 833   check_u64 (SD_, instruction_0);
 834   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 835   {
 836     ALU64_BEGIN (GPR[RS]);
 837     ALU64_ADD (GPR[RT]);
 838     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
 839   }
 840   TRACE_ALU_RESULT (GPR[RD]);
 841 }
 842
 843
 844
 845 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 846 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 847 *mipsIII:
 848 *mipsIV:
 849 *mipsV:
 850 *vr4100:
 851 *vr5000:
 852 {
 853   check_u64 (SD_, instruction_0);
 854   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 855   {
 856     ALU64_BEGIN (GPR[RS]);
 857     ALU64_ADD (EXTEND16 (IMMEDIATE));
 858     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
 859   }
 860   TRACE_ALU_RESULT (GPR[RT]);
 861 }
 862
 863
 864
 865 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 866 {
 867   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 868   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 869   TRACE_ALU_RESULT (GPR[rt]);
 870 }
 871
 872 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 873 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
 874 *mipsIII:
 875 *mipsIV:
 876 *mipsV:
 877 *vr4100:
 878 *vr5000:
 879 {
 880   check_u64 (SD_, instruction_0);
 881   do_daddiu (SD_, RS, RT, IMMEDIATE);
 882 }
 883
 884
 885
 886 :function:::void:do_daddu:int rs, int rt, int rd
 887 {
 888   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 889   GPR[rd] = GPR[rs] + GPR[rt];
 890   TRACE_ALU_RESULT (GPR[rd]);
 891 }
 892
 893 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 894 "daddu r<RD>, r<RS>, r<RT>"
 895 *mipsIII:
 896 *mipsIV:
 897 *mipsV:
 898 *vr4100:
 899 *vr5000:
 900 {
 901   check_u64 (SD_, instruction_0);
 902   do_daddu (SD_, RS, RT, RD);
 903 }
 904
 905
 906
 907 :function:::void:do_ddiv:int rs, int rt
 908 {
 909   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 910   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 911   {
 912     signed64 n = GPR[rs];
 913     signed64 d = GPR[rt];
 914     signed64 hi;
 915     signed64 lo;
 916     if (d == 0)
 917       {
 918         lo = SIGNED64 (0x8000000000000000);
 919         hi = 0;
 920       }
 921     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 922       {
 923         lo = SIGNED64 (0x8000000000000000);
 924         hi = 0;
 925       }
 926     else
 927       {
 928         lo = (n / d);
 929         hi = (n % d);
 930       }
 931     HI = hi;
 932     LO = lo;
 933   }
 934   TRACE_ALU_RESULT2 (HI, LO);
 935 }
 936
 937 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
 938 "ddiv r<RS>, r<RT>"
 939 *mipsIII:
 940 *mipsIV:
 941 *mipsV:
 942 *vr4100:
 943 *vr5000:
 944 {
 945   check_u64 (SD_, instruction_0);
 946   do_ddiv (SD_, RS, RT);
 947 }
 948
 949
 950
 951 :function:::void:do_ddivu:int rs, int rt
 952 {
 953   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 954   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 955   {
 956     unsigned64 n = GPR[rs];
 957     unsigned64 d = GPR[rt];
 958     unsigned64 hi;
 959     unsigned64 lo;
 960     if (d == 0)
 961       {
 962         lo = SIGNED64 (0x8000000000000000);
 963         hi = 0;
 964       }
 965     else
 966       {
 967         lo = (n / d);
 968         hi = (n % d);
 969       }
 970     HI = hi;
 971     LO = lo;
 972   }
 973   TRACE_ALU_RESULT2 (HI, LO);
 974 }
 975
 976 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 977 "ddivu r<RS>, r<RT>"
 978 *mipsIII:
 979 *mipsIV:
 980 *mipsV:
 981 *vr4100:
 982 *vr5000:
 983 {
 984   check_u64 (SD_, instruction_0);
 985   do_ddivu (SD_, RS, RT);
 986 }
 987
 988
 989
 990 :function:::void:do_div:int rs, int rt
 991 {
 992   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 993   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 994   {
 995     signed32 n = GPR[rs];
 996     signed32 d = GPR[rt];
 997     if (d == 0)
 998       {
 999         LO = EXTEND32 (0x80000000);
1000         HI = EXTEND32 (0);
1001       }
1002     else if (n == SIGNED32 (0x80000000) && d == -1)
1003       {
1004         LO = EXTEND32 (0x80000000);
1005         HI = EXTEND32 (0);
1006       }
1007     else
1008       {
1009         LO = EXTEND32 (n / d);
1010         HI = EXTEND32 (n % d);
1011       }
1012   }
1013   TRACE_ALU_RESULT2 (HI, LO);
1014 }
1015
1016 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1017 "div r<RS>, r<RT>"
1018 *mipsI:
1019 *mipsII:
1020 *mipsIII:
1021 *mipsIV:
1022 *mipsV:
1023 *vr4100:
1024 *vr5000:
1025 *r3900:
1026 {
1027   do_div (SD_, RS, RT);
1028 }
1029
1030
1031
1032 :function:::void:do_divu:int rs, int rt
1033 {
1034   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1035   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1036   {
1037     unsigned32 n = GPR[rs];
1038     unsigned32 d = GPR[rt];
1039     if (d == 0)
1040       {
1041         LO = EXTEND32 (0x80000000);
1042         HI = EXTEND32 (0);
1043       }
1044     else
1045       {
1046         LO = EXTEND32 (n / d);
1047         HI = EXTEND32 (n % d);
1048       }
1049   }
1050   TRACE_ALU_RESULT2 (HI, LO);
1051 }
1052
1053 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1054 "divu r<RS>, r<RT>"
1055 *mipsI:
1056 *mipsII:
1057 *mipsIII:
1058 *mipsIV:
1059 *mipsV:
1060 *vr4100:
1061 *vr5000:
1062 *r3900:
1063 {
1064   do_divu (SD_, RS, RT);
1065 }
1066
1067
1068
1069 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1070 {
1071   unsigned64 lo;
1072   unsigned64 hi;
1073   unsigned64 m00;
1074   unsigned64 m01;
1075   unsigned64 m10;
1076   unsigned64 m11;
1077   unsigned64 mid;
1078   int sign;
1079   unsigned64 op1 = GPR[rs];
1080   unsigned64 op2 = GPR[rt];
1081   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1082   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1083   /* make signed multiply unsigned */
1084   sign = 0;
1085   if (signed_p)
1086     {
1087       if (op1 < 0)
1088         {
1089           op1 = - op1;
1090           ++sign;
1091         }
1092       if (op2 < 0)
1093         {
1094           op2 = - op2;
1095           ++sign;
1096         }
1097     }
1098   /* multiply out the 4 sub products */
1099   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1100   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1101   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1102   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1103   /* add the products */
1104   mid = ((unsigned64) VH4_8 (m00)
1105          + (unsigned64) VL4_8 (m10)
1106          + (unsigned64) VL4_8 (m01));
1107   lo = U8_4 (mid, m00);
1108   hi = (m11
1109         + (unsigned64) VH4_8 (mid)
1110         + (unsigned64) VH4_8 (m01)
1111         + (unsigned64) VH4_8 (m10));
1112   /* fix the sign */
1113   if (sign & 1)
1114     {
1115       lo = -lo;
1116       if (lo == 0)
1117         hi = -hi;
1118       else
1119         hi = -hi - 1;
1120     }
1121   /* save the result HI/LO (and a gpr) */
1122   LO = lo;
1123   HI = hi;
1124   if (rd != 0)
1125     GPR[rd] = lo;
1126   TRACE_ALU_RESULT2 (HI, LO);
1127 }
1128
1129 :function:::void:do_dmult:int rs, int rt, int rd
1130 {
1131   do_dmultx (SD_, rs, rt, rd, 1);
1132 }
1133
1134 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1135 "dmult r<RS>, r<RT>"
1136 *mipsIII:
1137 *mipsIV:
1138 *mipsV:
1139 *vr4100:
1140 {
1141   check_u64 (SD_, instruction_0);
1142   do_dmult (SD_, RS, RT, 0);
1143 }
1144
1145 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1146 "dmult r<RS>, r<RT>":RD == 0
1147 "dmult r<RD>, r<RS>, r<RT>"
1148 *vr5000:
1149 {
1150   check_u64 (SD_, instruction_0);
1151   do_dmult (SD_, RS, RT, RD);
1152 }
1153
1154
1155
1156 :function:::void:do_dmultu:int rs, int rt, int rd
1157 {
1158   do_dmultx (SD_, rs, rt, rd, 0);
1159 }
1160
1161 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1162 "dmultu r<RS>, r<RT>"
1163 *mipsIII:
1164 *mipsIV:
1165 *mipsV:
1166 *vr4100:
1167 {
1168   check_u64 (SD_, instruction_0);
1169   do_dmultu (SD_, RS, RT, 0);
1170 }
1171
1172 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1173 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1174 "dmultu r<RS>, r<RT>"
1175 *vr5000:
1176 {
1177   check_u64 (SD_, instruction_0);
1178   do_dmultu (SD_, RS, RT, RD);
1179 }
1180
1181 :function:::void:do_dsll:int rt, int rd, int shift
1182 {
1183   TRACE_ALU_INPUT2 (GPR[rt], shift);
1184   GPR[rd] = GPR[rt] << shift;
1185   TRACE_ALU_RESULT (GPR[rd]);
1186 }
1187
1188 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1189 "dsll r<RD>, r<RT>, <SHIFT>"
1190 *mipsIII:
1191 *mipsIV:
1192 *mipsV:
1193 *vr4100:
1194 *vr5000:
1195 {
1196   check_u64 (SD_, instruction_0);
1197   do_dsll (SD_, RT, RD, SHIFT);
1198 }
1199
1200
1201 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1202 "dsll32 r<RD>, r<RT>, <SHIFT>"
1203 *mipsIII:
1204 *mipsIV:
1205 *mipsV:
1206 *vr4100:
1207 *vr5000:
1208 {
1209   int s = 32 + SHIFT;
1210   check_u64 (SD_, instruction_0);
1211   TRACE_ALU_INPUT2 (GPR[RT], s);
1212   GPR[RD] = GPR[RT] << s;
1213   TRACE_ALU_RESULT (GPR[RD]);
1214 }
1215
1216 :function:::void:do_dsllv:int rs, int rt, int rd
1217 {
1218   int s = MASKED64 (GPR[rs], 5, 0);
1219   TRACE_ALU_INPUT2 (GPR[rt], s);
1220   GPR[rd] = GPR[rt] << s;
1221   TRACE_ALU_RESULT (GPR[rd]);
1222 }
1223
1224 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1225 "dsllv r<RD>, r<RT>, r<RS>"
1226 *mipsIII:
1227 *mipsIV:
1228 *mipsV:
1229 *vr4100:
1230 *vr5000:
1231 {
1232   check_u64 (SD_, instruction_0);
1233   do_dsllv (SD_, RS, RT, RD);
1234 }
1235
1236 :function:::void:do_dsra:int rt, int rd, int shift
1237 {
1238   TRACE_ALU_INPUT2 (GPR[rt], shift);
1239   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1240   TRACE_ALU_RESULT (GPR[rd]);
1241 }
1242
1243
1244 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1245 "dsra r<RD>, r<RT>, <SHIFT>"
1246 *mipsIII:
1247 *mipsIV:
1248 *mipsV:
1249 *vr4100:
1250 *vr5000:
1251 {
1252   check_u64 (SD_, instruction_0);
1253   do_dsra (SD_, RT, RD, SHIFT);
1254 }
1255
1256
1257 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1258 "dsra32 r<RD>, r<RT>, <SHIFT>"
1259 *mipsIII:
1260 *mipsIV:
1261 *mipsV:
1262 *vr4100:
1263 *vr5000:
1264 {
1265   int s = 32 + SHIFT;
1266   check_u64 (SD_, instruction_0);
1267   TRACE_ALU_INPUT2 (GPR[RT], s);
1268   GPR[RD] = ((signed64) GPR[RT]) >> s;
1269   TRACE_ALU_RESULT (GPR[RD]);
1270 }
1271
1272
1273 :function:::void:do_dsrav:int rs, int rt, int rd
1274 {
1275   int s = MASKED64 (GPR[rs], 5, 0);
1276   TRACE_ALU_INPUT2 (GPR[rt], s);
1277   GPR[rd] = ((signed64) GPR[rt]) >> s;
1278   TRACE_ALU_RESULT (GPR[rd]);
1279 }
1280
1281 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1282 "dsrav r<RD>, r<RT>, r<RS>"
1283 *mipsIII:
1284 *mipsIV:
1285 *mipsV:
1286 *vr4100:
1287 *vr5000:
1288 {
1289   check_u64 (SD_, instruction_0);
1290   do_dsrav (SD_, RS, RT, RD);
1291 }
1292
1293 :function:::void:do_dsrl:int rt, int rd, int shift
1294 {
1295   TRACE_ALU_INPUT2 (GPR[rt], shift);
1296   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1297   TRACE_ALU_RESULT (GPR[rd]);
1298 }
1299
1300
1301 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1302 "dsrl r<RD>, r<RT>, <SHIFT>"
1303 *mipsIII:
1304 *mipsIV:
1305 *mipsV:
1306 *vr4100:
1307 *vr5000:
1308 {
1309   check_u64 (SD_, instruction_0);
1310   do_dsrl (SD_, RT, RD, SHIFT);
1311 }
1312
1313
1314 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1315 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1316 *mipsIII:
1317 *mipsIV:
1318 *mipsV:
1319 *vr4100:
1320 *vr5000:
1321 {
1322   int s = 32 + SHIFT;
1323   check_u64 (SD_, instruction_0);
1324   TRACE_ALU_INPUT2 (GPR[RT], s);
1325   GPR[RD] = (unsigned64) GPR[RT] >> s;
1326   TRACE_ALU_RESULT (GPR[RD]);
1327 }
1328
1329
1330 :function:::void:do_dsrlv:int rs, int rt, int rd
1331 {
1332   int s = MASKED64 (GPR[rs], 5, 0);
1333   TRACE_ALU_INPUT2 (GPR[rt], s);
1334   GPR[rd] = (unsigned64) GPR[rt] >> s;
1335   TRACE_ALU_RESULT (GPR[rd]);
1336 }
1337
1338
1339
1340 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1341 "dsrlv r<RD>, r<RT>, r<RS>"
1342 *mipsIII:
1343 *mipsIV:
1344 *mipsV:
1345 *vr4100:
1346 *vr5000:
1347 {
1348   check_u64 (SD_, instruction_0);
1349   do_dsrlv (SD_, RS, RT, RD);
1350 }
1351
1352
1353 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1354 "dsub r<RD>, r<RS>, r<RT>"
1355 *mipsIII:
1356 *mipsIV:
1357 *mipsV:
1358 *vr4100:
1359 *vr5000:
1360 {
1361   check_u64 (SD_, instruction_0);
1362   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1363   {
1364     ALU64_BEGIN (GPR[RS]);
1365     ALU64_SUB (GPR[RT]);
1366     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1367   }
1368   TRACE_ALU_RESULT (GPR[RD]);
1369 }
1370
1371
1372 :function:::void:do_dsubu:int rs, int rt, int rd
1373 {
1374   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1375   GPR[rd] = GPR[rs] - GPR[rt];
1376   TRACE_ALU_RESULT (GPR[rd]);
1377 }
1378
1379 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1380 "dsubu r<RD>, r<RS>, r<RT>"
1381 *mipsIII:
1382 *mipsIV:
1383 *mipsV:
1384 *vr4100:
1385 *vr5000:
1386 {
1387   check_u64 (SD_, instruction_0);
1388   do_dsubu (SD_, RS, RT, RD);
1389 }
1390
1391
1392 000010,26.INSTR_INDEX:NORMAL:32::J
1393 "j <INSTR_INDEX>"
1394 *mipsI:
1395 *mipsII:
1396 *mipsIII:
1397 *mipsIV:
1398 *mipsV:
1399 *vr4100:
1400 *vr5000:
1401 *r3900:
1402 {
1403   /* NOTE: The region used is that of the delay slot NIA and NOT the
1404      current instruction */
1405   address_word region = (NIA & MASK (63, 28));
1406   DELAY_SLOT (region | (INSTR_INDEX << 2));
1407 }
1408
1409
1410 000011,26.INSTR_INDEX:NORMAL:32::JAL
1411 "jal <INSTR_INDEX>"
1412 *mipsI:
1413 *mipsII:
1414 *mipsIII:
1415 *mipsIV:
1416 *mipsV:
1417 *vr4100:
1418 *vr5000:
1419 *r3900:
1420 {
1421   /* NOTE: The region used is that of the delay slot and NOT the
1422      current instruction */
1423   address_word region = (NIA & MASK (63, 28));
1424   GPR[31] = CIA + 8;
1425   DELAY_SLOT (region | (INSTR_INDEX << 2));
1426 }
1427
1428 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1429 "jalr r<RS>":RD == 31
1430 "jalr r<RD>, r<RS>"
1431 *mipsI:
1432 *mipsII:
1433 *mipsIII:
1434 *mipsIV:
1435 *mipsV:
1436 *vr4100:
1437 *vr5000:
1438 *r3900:
1439 {
1440   address_word temp = GPR[RS];
1441   GPR[RD] = CIA + 8;
1442   DELAY_SLOT (temp);
1443 }
1444
1445
1446 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1447 "jr r<RS>"
1448 *mipsI:
1449 *mipsII:
1450 *mipsIII:
1451 *mipsIV:
1452 *mipsV:
1453 *vr4100:
1454 *vr5000:
1455 *r3900:
1456 {
1457   DELAY_SLOT (GPR[RS]);
1458 }
1459
1460
1461 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1462 {
1463   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1464   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1465   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1466   unsigned int byte;
1467   address_word paddr;
1468   int uncached;
1469   unsigned64 memval;
1470   address_word vaddr;
1471
1472   vaddr = base + offset;
1473   if ((vaddr & access) != 0)
1474     {
1475       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1476     }
1477   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1478   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1479   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1480   byte = ((vaddr & mask) ^ bigendiancpu);
1481   return (memval >> (8 * byte));
1482 }
1483
1484 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1485 {
1486   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1487   address_word reverseendian = (ReverseEndian ? -1 : 0);
1488   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1489   unsigned int byte;
1490   unsigned int word;
1491   address_word paddr;
1492   int uncached;
1493   unsigned64 memval;
1494   address_word vaddr;
1495   int nr_lhs_bits;
1496   int nr_rhs_bits;
1497   unsigned_word lhs_mask;
1498   unsigned_word temp;
1499
1500   vaddr = base + offset;
1501   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1502   paddr = (paddr ^ (reverseendian & mask));
1503   if (BigEndianMem == 0)
1504     paddr = paddr & ~access;
1505
1506   /* compute where within the word/mem we are */
1507   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1508   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1509   nr_lhs_bits = 8 * byte + 8;
1510   nr_rhs_bits = 8 * access - 8 * byte;
1511   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1512
1513   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1514            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1515            (long) ((unsigned64) paddr >> 32), (long) paddr,
1516            word, byte, nr_lhs_bits, nr_rhs_bits); */
1517
1518   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1519   if (word == 0)
1520     {
1521       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1522       temp = (memval << nr_rhs_bits);
1523     }
1524   else
1525     {
1526       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1527       temp = (memval >> nr_lhs_bits);
1528     }
1529   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1530   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1531
1532   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1533            (long) ((unsigned64) memval >> 32), (long) memval,
1534            (long) ((unsigned64) temp >> 32), (long) temp,
1535            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1536            (long) (rt >> 32), (long) rt); */
1537   return rt;
1538 }
1539
1540 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1541 {
1542   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1543   address_word reverseendian = (ReverseEndian ? -1 : 0);
1544   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1545   unsigned int byte;
1546   address_word paddr;
1547   int uncached;
1548   unsigned64 memval;
1549   address_word vaddr;
1550
1551   vaddr = base + offset;
1552   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1553   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1554   paddr = (paddr ^ (reverseendian & mask));
1555   if (BigEndianMem != 0)
1556     paddr = paddr & ~access;
1557   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1558   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1559   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1560   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1561      (long) paddr, byte, (long) paddr, (long) memval); */
1562   {
1563     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1564     rt &= ~screen;
1565     rt |= (memval >> (8 * byte)) & screen;
1566   }
1567   return rt;
1568 }
1569
1570
1571 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1572 "lb r<RT>, <OFFSET>(r<BASE>)"
1573 *mipsI:
1574 *mipsII:
1575 *mipsIII:
1576 *mipsIV:
1577 *mipsV:
1578 *vr4100:
1579 *vr5000:
1580 *r3900:
1581 {
1582   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1583 }
1584
1585
1586 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1587 "lbu r<RT>, <OFFSET>(r<BASE>)"
1588 *mipsI:
1589 *mipsII:
1590 *mipsIII:
1591 *mipsIV:
1592 *mipsV:
1593 *vr4100:
1594 *vr5000:
1595 *r3900:
1596 {
1597   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1598 }
1599
1600
1601 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1602 "ld r<RT>, <OFFSET>(r<BASE>)"
1603 *mipsIII:
1604 *mipsIV:
1605 *mipsV:
1606 *vr4100:
1607 *vr5000:
1608 {
1609   check_u64 (SD_, instruction_0);
1610   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1611 }
1612
1613
1614 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1615 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1616 *mipsII:
1617 *mipsIII:
1618 *mipsIV:
1619 *mipsV:
1620 *vr4100:
1621 *vr5000:
1622 *r3900:
1623 {
1624   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1625 }
1626
1627
1628
1629
1630 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1631 "ldl r<RT>, <OFFSET>(r<BASE>)"
1632 *mipsIII:
1633 *mipsIV:
1634 *mipsV:
1635 *vr4100:
1636 *vr5000:
1637 {
1638   check_u64 (SD_, instruction_0);
1639   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1640 }
1641
1642
1643 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1644 "ldr r<RT>, <OFFSET>(r<BASE>)"
1645 *mipsIII:
1646 *mipsIV:
1647 *mipsV:
1648 *vr4100:
1649 *vr5000:
1650 {
1651   check_u64 (SD_, instruction_0);
1652   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1653 }
1654
1655
1656 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1657 "lh r<RT>, <OFFSET>(r<BASE>)"
1658 *mipsI:
1659 *mipsII:
1660 *mipsIII:
1661 *mipsIV:
1662 *mipsV:
1663 *vr4100:
1664 *vr5000:
1665 *r3900:
1666 {
1667   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1668 }
1669
1670
1671 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1672 "lhu r<RT>, <OFFSET>(r<BASE>)"
1673 *mipsI:
1674 *mipsII:
1675 *mipsIII:
1676 *mipsIV:
1677 *mipsV:
1678 *vr4100:
1679 *vr5000:
1680 *r3900:
1681 {
1682   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1683 }
1684
1685
1686 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1687 "ll r<RT>, <OFFSET>(r<BASE>)"
1688 *mipsII:
1689 *mipsIII:
1690 *mipsIV:
1691 *mipsV:
1692 *vr4100:
1693 *vr5000:
1694 {
1695   address_word base = GPR[BASE];
1696   address_word offset = EXTEND16 (OFFSET);
1697   {
1698     address_word vaddr = ((unsigned64)base + offset);
1699     address_word paddr;
1700     int uncached;
1701     if ((vaddr & 3) != 0)
1702       {
1703         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1704       }
1705     else
1706       {
1707         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1708           {
1709             unsigned64 memval = 0;
1710             unsigned64 memval1 = 0;
1711             unsigned64 mask = 0x7;
1712             unsigned int shift = 2;
1713             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1714             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1715             unsigned int byte;
1716             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1717             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1718             byte = ((vaddr & mask) ^ (bigend << shift));
1719             GPR[RT] = EXTEND32 (memval >> (8 * byte));
1720             LLBIT = 1;
1721           }
1722       }
1723   }
1724 }
1725
1726
1727 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1728 "lld r<RT>, <OFFSET>(r<BASE>)"
1729 *mipsIII:
1730 *mipsIV:
1731 *mipsV:
1732 *vr4100:
1733 *vr5000:
1734 {
1735   address_word base = GPR[BASE];
1736   address_word offset = EXTEND16 (OFFSET);
1737   check_u64 (SD_, instruction_0);
1738   {
1739     address_word vaddr = ((unsigned64)base + offset);
1740     address_word paddr;
1741     int uncached;
1742     if ((vaddr & 7) != 0)
1743       {
1744         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1745       }
1746     else
1747       {
1748         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1749           {
1750             unsigned64 memval = 0;
1751             unsigned64 memval1 = 0;
1752             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1753             GPR[RT] = memval;
1754             LLBIT = 1;
1755           }
1756       }
1757   }
1758 }
1759
1760
1761 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1762 "lui r<RT>, <IMMEDIATE>"
1763 *mipsI:
1764 *mipsII:
1765 *mipsIII:
1766 *mipsIV:
1767 *mipsV:
1768 *vr4100:
1769 *vr5000:
1770 *r3900:
1771 {
1772   TRACE_ALU_INPUT1 (IMMEDIATE);
1773   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1774   TRACE_ALU_RESULT (GPR[RT]);
1775 }
1776
1777
1778 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1779 "lw r<RT>, <OFFSET>(r<BASE>)"
1780 *mipsI:
1781 *mipsII:
1782 *mipsIII:
1783 *mipsIV:
1784 *mipsV:
1785 *vr4100:
1786 *vr5000:
1787 *r3900:
1788 {
1789   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1790 }
1791
1792
1793 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1794 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1795 *mipsI:
1796 *mipsII:
1797 *mipsIII:
1798 *mipsIV:
1799 *mipsV:
1800 *vr4100:
1801 *vr5000:
1802 *r3900:
1803 {
1804   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1805 }
1806
1807
1808 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1809 "lwl r<RT>, <OFFSET>(r<BASE>)"
1810 *mipsI:
1811 *mipsII:
1812 *mipsIII:
1813 *mipsIV:
1814 *mipsV:
1815 *vr4100:
1816 *vr5000:
1817 *r3900:
1818 {
1819   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1820 }
1821
1822
1823 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1824 "lwr r<RT>, <OFFSET>(r<BASE>)"
1825 *mipsI:
1826 *mipsII:
1827 *mipsIII:
1828 *mipsIV:
1829 *mipsV:
1830 *vr4100:
1831 *vr5000:
1832 *r3900:
1833 {
1834   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1835 }
1836
1837
1838 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
1839 "lwu r<RT>, <OFFSET>(r<BASE>)"
1840 *mipsIII:
1841 *mipsIV:
1842 *mipsV:
1843 *vr4100:
1844 *vr5000:
1845 {
1846   check_u64 (SD_, instruction_0);
1847   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1848 }
1849
1850
1851 :function:::void:do_mfhi:int rd
1852 {
1853   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1854   TRACE_ALU_INPUT1 (HI);
1855   GPR[rd] = HI;
1856   TRACE_ALU_RESULT (GPR[rd]);
1857 }
1858
1859 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1860 "mfhi r<RD>"
1861 *mipsI:
1862 *mipsII:
1863 *mipsIII:
1864 *mipsIV:
1865 *mipsV:
1866 *vr4100:
1867 *vr5000:
1868 *r3900:
1869 {
1870   do_mfhi (SD_, RD);
1871 }
1872
1873
1874
1875 :function:::void:do_mflo:int rd
1876 {
1877   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1878   TRACE_ALU_INPUT1 (LO);
1879   GPR[rd] = LO;
1880   TRACE_ALU_RESULT (GPR[rd]);
1881 }
1882
1883 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1884 "mflo r<RD>"
1885 *mipsI:
1886 *mipsII:
1887 *mipsIII:
1888 *mipsIV:
1889 *mipsV:
1890 *vr4100:
1891 *vr5000:
1892 *r3900:
1893 {
1894   do_mflo (SD_, RD);
1895 }
1896
1897
1898
1899 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
1900 "movn r<RD>, r<RS>, r<RT>"
1901 *mipsIV:
1902 *mipsV:
1903 *vr5000:
1904 {
1905   if (GPR[RT] != 0)
1906     GPR[RD] = GPR[RS];
1907 }
1908
1909
1910
1911 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
1912 "movz r<RD>, r<RS>, r<RT>"
1913 *mipsIV:
1914 *mipsV:
1915 *vr5000:
1916 {
1917   if (GPR[RT] == 0)
1918     GPR[RD] = GPR[RS];
1919 }
1920
1921
1922
1923 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1924 "mthi r<RS>"
1925 *mipsI:
1926 *mipsII:
1927 *mipsIII:
1928 *mipsIV:
1929 *mipsV:
1930 *vr4100:
1931 *vr5000:
1932 *r3900:
1933 {
1934   check_mt_hilo (SD_, HIHISTORY);
1935   HI = GPR[RS];
1936 }
1937
1938
1939
1940 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
1941 "mtlo r<RS>"
1942 *mipsI:
1943 *mipsII:
1944 *mipsIII:
1945 *mipsIV:
1946 *mipsV:
1947 *vr4100:
1948 *vr5000:
1949 *r3900:
1950 {
1951   check_mt_hilo (SD_, LOHISTORY);
1952   LO = GPR[RS];
1953 }
1954
1955
1956
1957 :function:::void:do_mult:int rs, int rt, int rd
1958 {
1959   signed64 prod;
1960   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1961   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1962   prod = (((signed64)(signed32) GPR[rs])
1963           * ((signed64)(signed32) GPR[rt]));
1964   LO = EXTEND32 (VL4_8 (prod));
1965   HI = EXTEND32 (VH4_8 (prod));
1966   if (rd != 0)
1967     GPR[rd] = LO;
1968   TRACE_ALU_RESULT2 (HI, LO);
1969 }
1970
1971 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
1972 "mult r<RS>, r<RT>"
1973 *mipsI:
1974 *mipsII:
1975 *mipsIII:
1976 *mipsIV:
1977 *mipsV:
1978 *vr4100:
1979 {
1980   do_mult (SD_, RS, RT, 0);
1981 }
1982
1983
1984 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
1985 "mult r<RS>, r<RT>":RD == 0
1986 "mult r<RD>, r<RS>, r<RT>"
1987 *vr5000:
1988 *r3900:
1989 {
1990   do_mult (SD_, RS, RT, RD);
1991 }
1992
1993
1994 :function:::void:do_multu:int rs, int rt, int rd
1995 {
1996   unsigned64 prod;
1997   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1998   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1999   prod = (((unsigned64)(unsigned32) GPR[rs])
2000           * ((unsigned64)(unsigned32) GPR[rt]));
2001   LO = EXTEND32 (VL4_8 (prod));
2002   HI = EXTEND32 (VH4_8 (prod));
2003   if (rd != 0)
2004     GPR[rd] = LO;
2005   TRACE_ALU_RESULT2 (HI, LO);
2006 }
2007
2008 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2009 "multu r<RS>, r<RT>"
2010 *mipsI:
2011 *mipsII:
2012 *mipsIII:
2013 *mipsIV:
2014 *mipsV:
2015 *vr4100:
2016 {
2017   do_multu (SD_, RS, RT, 0);
2018 }
2019
2020 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2021 "multu r<RS>, r<RT>":RD == 0
2022 "multu r<RD>, r<RS>, r<RT>"
2023 *vr5000:
2024 *r3900:
2025 {
2026   do_multu (SD_, RS, RT, RD);
2027 }
2028
2029
2030 :function:::void:do_nor:int rs, int rt, int rd
2031 {
2032   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2033   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2034   TRACE_ALU_RESULT (GPR[rd]);
2035 }
2036
2037 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2038 "nor r<RD>, r<RS>, r<RT>"
2039 *mipsI:
2040 *mipsII:
2041 *mipsIII:
2042 *mipsIV:
2043 *mipsV:
2044 *vr4100:
2045 *vr5000:
2046 *r3900:
2047 {
2048   do_nor (SD_, RS, RT, RD);
2049 }
2050
2051
2052 :function:::void:do_or:int rs, int rt, int rd
2053 {
2054   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2055   GPR[rd] = (GPR[rs] | GPR[rt]);
2056   TRACE_ALU_RESULT (GPR[rd]);
2057 }
2058
2059 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2060 "or r<RD>, r<RS>, r<RT>"
2061 *mipsI:
2062 *mipsII:
2063 *mipsIII:
2064 *mipsIV:
2065 *mipsV:
2066 *vr4100:
2067 *vr5000:
2068 *r3900:
2069 {
2070   do_or (SD_, RS, RT, RD);
2071 }
2072
2073
2074
2075 :function:::void:do_ori:int rs, int rt, unsigned immediate
2076 {
2077   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2078   GPR[rt] = (GPR[rs] | immediate);
2079   TRACE_ALU_RESULT (GPR[rt]);
2080 }
2081
2082 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2083 "ori r<RT>, r<RS>, <IMMEDIATE>"
2084 *mipsI:
2085 *mipsII:
2086 *mipsIII:
2087 *mipsIV:
2088 *mipsV:
2089 *vr4100:
2090 *vr5000:
2091 *r3900:
2092 {
2093   do_ori (SD_, RS, RT, IMMEDIATE);
2094 }
2095
2096
2097 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2098 "pref <HINT>, <OFFSET>(r<BASE>)"
2099 *mipsIV:
2100 *mipsV:
2101 *vr5000:
2102 {
2103   address_word base = GPR[BASE];
2104   address_word offset = EXTEND16 (OFFSET);
2105   {
2106     address_word vaddr = ((unsigned64)base + offset);
2107     address_word paddr;
2108     int uncached;
2109     {
2110       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2111         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2112     }
2113   }
2114 }
2115
2116
2117 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2118 {
2119   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2120   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2121   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2122   unsigned int byte;
2123   address_word paddr;
2124   int uncached;
2125   unsigned64 memval;
2126   address_word vaddr;
2127
2128   vaddr = base + offset;
2129   if ((vaddr & access) != 0)
2130     {
2131       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2132     }
2133   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2134   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2135   byte = ((vaddr & mask) ^ bigendiancpu);
2136   memval = (word << (8 * byte));
2137   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2138 }
2139
2140 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2141 {
2142   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2143   address_word reverseendian = (ReverseEndian ? -1 : 0);
2144   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2145   unsigned int byte;
2146   unsigned int word;
2147   address_word paddr;
2148   int uncached;
2149   unsigned64 memval;
2150   address_word vaddr;
2151   int nr_lhs_bits;
2152   int nr_rhs_bits;
2153
2154   vaddr = base + offset;
2155   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2156   paddr = (paddr ^ (reverseendian & mask));
2157   if (BigEndianMem == 0)
2158     paddr = paddr & ~access;
2159
2160   /* compute where within the word/mem we are */
2161   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2162   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2163   nr_lhs_bits = 8 * byte + 8;
2164   nr_rhs_bits = 8 * access - 8 * byte;
2165   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2166   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2167            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2168            (long) ((unsigned64) paddr >> 32), (long) paddr,
2169            word, byte, nr_lhs_bits, nr_rhs_bits); */
2170
2171   if (word == 0)
2172     {
2173       memval = (rt >> nr_rhs_bits);
2174     }
2175   else
2176     {
2177       memval = (rt << nr_lhs_bits);
2178     }
2179   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2180            (long) ((unsigned64) rt >> 32), (long) rt,
2181            (long) ((unsigned64) memval >> 32), (long) memval); */
2182   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2183 }
2184
2185 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2186 {
2187   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2188   address_word reverseendian = (ReverseEndian ? -1 : 0);
2189   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2190   unsigned int byte;
2191   address_word paddr;
2192   int uncached;
2193   unsigned64 memval;
2194   address_word vaddr;
2195
2196   vaddr = base + offset;
2197   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2198   paddr = (paddr ^ (reverseendian & mask));
2199   if (BigEndianMem != 0)
2200     paddr &= ~access;
2201   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2202   memval = (rt << (byte * 8));
2203   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2204 }
2205
2206
2207 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2208 "sb r<RT>, <OFFSET>(r<BASE>)"
2209 *mipsI:
2210 *mipsII:
2211 *mipsIII:
2212 *mipsIV:
2213 *mipsV:
2214 *vr4100:
2215 *vr5000:
2216 *r3900:
2217 {
2218   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2219 }
2220
2221
2222 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2223 "sc r<RT>, <OFFSET>(r<BASE>)"
2224 *mipsII:
2225 *mipsIII:
2226 *mipsIV:
2227 *mipsV:
2228 *vr4100:
2229 *vr5000:
2230 {
2231   unsigned32 instruction = instruction_0;
2232   address_word base = GPR[BASE];
2233   address_word offset = EXTEND16 (OFFSET);
2234   {
2235     address_word vaddr = ((unsigned64)base + offset);
2236     address_word paddr;
2237     int uncached;
2238     if ((vaddr & 3) != 0)
2239       {
2240         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2241       }
2242     else
2243       {
2244         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2245           {
2246             unsigned64 memval = 0;
2247             unsigned64 memval1 = 0;
2248             unsigned64 mask = 0x7;
2249             unsigned int byte;
2250             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2251             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2252             memval = ((unsigned64) GPR[RT] << (8 * byte));
2253             if (LLBIT)
2254               {
2255                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2256               }
2257             GPR[RT] = LLBIT;
2258           }
2259       }
2260   }
2261 }
2262
2263
2264 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2265 "scd r<RT>, <OFFSET>(r<BASE>)"
2266 *mipsIII:
2267 *mipsIV:
2268 *mipsV:
2269 *vr4100:
2270 *vr5000:
2271 {
2272   address_word base = GPR[BASE];
2273   address_word offset = EXTEND16 (OFFSET);
2274   check_u64 (SD_, instruction_0);
2275   {
2276     address_word vaddr = ((unsigned64)base + offset);
2277     address_word paddr;
2278     int uncached;
2279     if ((vaddr & 7) != 0)
2280       {
2281         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2282       }
2283     else
2284       {
2285         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2286           {
2287             unsigned64 memval = 0;
2288             unsigned64 memval1 = 0;
2289             memval = GPR[RT];
2290             if (LLBIT)
2291               {
2292                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2293               }
2294             GPR[RT] = LLBIT;
2295           }
2296       }
2297   }
2298 }
2299
2300
2301 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2302 "sd r<RT>, <OFFSET>(r<BASE>)"
2303 *mipsIII:
2304 *mipsIV:
2305 *mipsV:
2306 *vr4100:
2307 *vr5000:
2308 {
2309   check_u64 (SD_, instruction_0);
2310   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2311 }
2312
2313
2314 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2315 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2316 *mipsII:
2317 *mipsIII:
2318 *mipsIV:
2319 *mipsV:
2320 *vr4100:
2321 *vr5000:
2322 {
2323   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2324 }
2325
2326
2327 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2328 "sdl r<RT>, <OFFSET>(r<BASE>)"
2329 *mipsIII:
2330 *mipsIV:
2331 *mipsV:
2332 *vr4100:
2333 *vr5000:
2334 {
2335   check_u64 (SD_, instruction_0);
2336   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2337 }
2338
2339
2340 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2341 "sdr r<RT>, <OFFSET>(r<BASE>)"
2342 *mipsIII:
2343 *mipsIV:
2344 *mipsV:
2345 *vr4100:
2346 *vr5000:
2347 {
2348   check_u64 (SD_, instruction_0);
2349   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2350 }
2351
2352
2353 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2354 "sh r<RT>, <OFFSET>(r<BASE>)"
2355 *mipsI:
2356 *mipsII:
2357 *mipsIII:
2358 *mipsIV:
2359 *mipsV:
2360 *vr4100:
2361 *vr5000:
2362 *r3900:
2363 {
2364   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2365 }
2366
2367
2368 :function:::void:do_sll:int rt, int rd, int shift
2369 {
2370   unsigned32 temp = (GPR[rt] << shift);
2371   TRACE_ALU_INPUT2 (GPR[rt], shift);
2372   GPR[rd] = EXTEND32 (temp);
2373   TRACE_ALU_RESULT (GPR[rd]);
2374 }
2375
2376 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2377 "nop":RD == 0 && RT == 0 && SHIFT == 0
2378 "sll r<RD>, r<RT>, <SHIFT>"
2379 *mipsI:
2380 *mipsII:
2381 *mipsIII:
2382 *mipsIV:
2383 *mipsV:
2384 *vr4100:
2385 *vr5000:
2386 *r3900:
2387 {
2388   /* Skip shift for NOP, so that there won't be lots of extraneous
2389      trace output.  */
2390   if (RD != 0 || RT != 0 || SHIFT != 0)
2391     do_sll (SD_, RT, RD, SHIFT);
2392 }
2393
2394
2395 :function:::void:do_sllv:int rs, int rt, int rd
2396 {
2397   int s = MASKED (GPR[rs], 4, 0);
2398   unsigned32 temp = (GPR[rt] << s);
2399   TRACE_ALU_INPUT2 (GPR[rt], s);
2400   GPR[rd] = EXTEND32 (temp);
2401   TRACE_ALU_RESULT (GPR[rd]);
2402 }
2403
2404 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2405 "sllv r<RD>, r<RT>, r<RS>"
2406 *mipsI:
2407 *mipsII:
2408 *mipsIII:
2409 *mipsIV:
2410 *mipsV:
2411 *vr4100:
2412 *vr5000:
2413 *r3900:
2414 {
2415   do_sllv (SD_, RS, RT, RD);
2416 }
2417
2418
2419 :function:::void:do_slt:int rs, int rt, int rd
2420 {
2421   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2422   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2423   TRACE_ALU_RESULT (GPR[rd]);
2424 }
2425
2426 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2427 "slt r<RD>, r<RS>, r<RT>"
2428 *mipsI:
2429 *mipsII:
2430 *mipsIII:
2431 *mipsIV:
2432 *mipsV:
2433 *vr4100:
2434 *vr5000:
2435 *r3900:
2436 {
2437   do_slt (SD_, RS, RT, RD);
2438 }
2439
2440
2441 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2442 {
2443   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2444   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2445   TRACE_ALU_RESULT (GPR[rt]);
2446 }
2447
2448 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2449 "slti r<RT>, r<RS>, <IMMEDIATE>"
2450 *mipsI:
2451 *mipsII:
2452 *mipsIII:
2453 *mipsIV:
2454 *mipsV:
2455 *vr4100:
2456 *vr5000:
2457 *r3900:
2458 {
2459   do_slti (SD_, RS, RT, IMMEDIATE);
2460 }
2461
2462
2463 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2464 {
2465   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2466   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2467   TRACE_ALU_RESULT (GPR[rt]);
2468 }
2469
2470 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2471 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2472 *mipsI:
2473 *mipsII:
2474 *mipsIII:
2475 *mipsIV:
2476 *mipsV:
2477 *vr4100:
2478 *vr5000:
2479 *r3900:
2480 {
2481   do_sltiu (SD_, RS, RT, IMMEDIATE);
2482 }
2483
2484
2485
2486 :function:::void:do_sltu:int rs, int rt, int rd
2487 {
2488   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2489   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2490   TRACE_ALU_RESULT (GPR[rd]);
2491 }
2492
2493 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
2494 "sltu r<RD>, r<RS>, r<RT>"
2495 *mipsI:
2496 *mipsII:
2497 *mipsIII:
2498 *mipsIV:
2499 *mipsV:
2500 *vr4100:
2501 *vr5000:
2502 *r3900:
2503 {
2504   do_sltu (SD_, RS, RT, RD);
2505 }
2506
2507
2508 :function:::void:do_sra:int rt, int rd, int shift
2509 {
2510   signed32 temp = (signed32) GPR[rt] >> shift;
2511   TRACE_ALU_INPUT2 (GPR[rt], shift);
2512   GPR[rd] = EXTEND32 (temp);
2513   TRACE_ALU_RESULT (GPR[rd]);
2514 }
2515
2516 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2517 "sra r<RD>, r<RT>, <SHIFT>"
2518 *mipsI:
2519 *mipsII:
2520 *mipsIII:
2521 *mipsIV:
2522 *mipsV:
2523 *vr4100:
2524 *vr5000:
2525 *r3900:
2526 {
2527   do_sra (SD_, RT, RD, SHIFT);
2528 }
2529
2530
2531
2532 :function:::void:do_srav:int rs, int rt, int rd
2533 {
2534   int s = MASKED (GPR[rs], 4, 0);
2535   signed32 temp = (signed32) GPR[rt] >> s;
2536   TRACE_ALU_INPUT2 (GPR[rt], s);
2537   GPR[rd] = EXTEND32 (temp);
2538   TRACE_ALU_RESULT (GPR[rd]);
2539 }
2540
2541 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
2542 "srav r<RD>, r<RT>, r<RS>"
2543 *mipsI:
2544 *mipsII:
2545 *mipsIII:
2546 *mipsIV:
2547 *mipsV:
2548 *vr4100:
2549 *vr5000:
2550 *r3900:
2551 {
2552   do_srav (SD_, RS, RT, RD);
2553 }
2554
2555
2556
2557 :function:::void:do_srl:int rt, int rd, int shift
2558 {
2559   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2560   TRACE_ALU_INPUT2 (GPR[rt], shift);
2561   GPR[rd] = EXTEND32 (temp);
2562   TRACE_ALU_RESULT (GPR[rd]);
2563 }
2564
2565 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2566 "srl r<RD>, r<RT>, <SHIFT>"
2567 *mipsI:
2568 *mipsII:
2569 *mipsIII:
2570 *mipsIV:
2571 *mipsV:
2572 *vr4100:
2573 *vr5000:
2574 *r3900:
2575 {
2576   do_srl (SD_, RT, RD, SHIFT);
2577 }
2578
2579
2580 :function:::void:do_srlv:int rs, int rt, int rd
2581 {
2582   int s = MASKED (GPR[rs], 4, 0);
2583   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2584   TRACE_ALU_INPUT2 (GPR[rt], s);
2585   GPR[rd] = EXTEND32 (temp);
2586   TRACE_ALU_RESULT (GPR[rd]);
2587 }
2588
2589 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
2590 "srlv r<RD>, r<RT>, r<RS>"
2591 *mipsI:
2592 *mipsII:
2593 *mipsIII:
2594 *mipsIV:
2595 *mipsV:
2596 *vr4100:
2597 *vr5000:
2598 *r3900:
2599 {
2600   do_srlv (SD_, RS, RT, RD);
2601 }
2602
2603
2604 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
2605 "sub r<RD>, r<RS>, r<RT>"
2606 *mipsI:
2607 *mipsII:
2608 *mipsIII:
2609 *mipsIV:
2610 *mipsV:
2611 *vr4100:
2612 *vr5000:
2613 *r3900:
2614 {
2615   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2616   {
2617     ALU32_BEGIN (GPR[RS]);
2618     ALU32_SUB (GPR[RT]);
2619     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
2620   }
2621   TRACE_ALU_RESULT (GPR[RD]);
2622 }
2623
2624
2625 :function:::void:do_subu:int rs, int rt, int rd
2626 {
2627   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2628   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2629   TRACE_ALU_RESULT (GPR[rd]);
2630 }
2631
2632 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
2633 "subu r<RD>, r<RS>, r<RT>"
2634 *mipsI:
2635 *mipsII:
2636 *mipsIII:
2637 *mipsIV:
2638 *mipsV:
2639 *vr4100:
2640 *vr5000:
2641 *r3900:
2642 {
2643   do_subu (SD_, RS, RT, RD);
2644 }
2645
2646
2647 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2648 "sw r<RT>, <OFFSET>(r<BASE>)"
2649 *mipsI:
2650 *mipsII:
2651 *mipsIII:
2652 *mipsIV:
2653 *mipsV:
2654 *vr4100:
2655 *r3900:
2656 *vr5000:
2657 {
2658   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2659 }
2660
2661
2662 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2663 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2664 *mipsI:
2665 *mipsII:
2666 *mipsIII:
2667 *mipsIV:
2668 *mipsV:
2669 *vr4100:
2670 *vr5000:
2671 *r3900:
2672 {
2673   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2674 }
2675
2676
2677 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2678 "swl r<RT>, <OFFSET>(r<BASE>)"
2679 *mipsI:
2680 *mipsII:
2681 *mipsIII:
2682 *mipsIV:
2683 *mipsV:
2684 *vr4100:
2685 *vr5000:
2686 *r3900:
2687 {
2688   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2689 }
2690
2691
2692 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2693 "swr r<RT>, <OFFSET>(r<BASE>)"
2694 *mipsI:
2695 *mipsII:
2696 *mipsIII:
2697 *mipsIV:
2698 *mipsV:
2699 *vr4100:
2700 *vr5000:
2701 *r3900:
2702 {
2703   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2704 }
2705
2706
2707 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2708 "sync":STYPE == 0
2709 "sync <STYPE>"
2710 *mipsII:
2711 *mipsIII:
2712 *mipsIV:
2713 *mipsV:
2714 *vr4100:
2715 *vr5000:
2716 *r3900:
2717 {
2718   SyncOperation (STYPE);
2719 }
2720
2721
2722 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2723 "syscall <CODE>"
2724 *mipsI:
2725 *mipsII:
2726 *mipsIII:
2727 *mipsIV:
2728 *mipsV:
2729 *vr4100:
2730 *vr5000:
2731 *r3900:
2732 {
2733   SignalException(SystemCall, instruction_0);
2734 }
2735
2736
2737 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2738 "teq r<RS>, r<RT>"
2739 *mipsII:
2740 *mipsIII:
2741 *mipsIV:
2742 *mipsV:
2743 *vr4100:
2744 *vr5000:
2745 {
2746   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2747     SignalException(Trap, instruction_0);
2748 }
2749
2750
2751 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2752 "teqi r<RS>, <IMMEDIATE>"
2753 *mipsII:
2754 *mipsIII:
2755 *mipsIV:
2756 *mipsV:
2757 *vr4100:
2758 *vr5000:
2759 {
2760   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2761     SignalException(Trap, instruction_0);
2762 }
2763
2764
2765 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2766 "tge r<RS>, r<RT>"
2767 *mipsII:
2768 *mipsIII:
2769 *mipsIV:
2770 *mipsV:
2771 *vr4100:
2772 *vr5000:
2773 {
2774   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2775     SignalException(Trap, instruction_0);
2776 }
2777
2778
2779 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2780 "tgei r<RS>, <IMMEDIATE>"
2781 *mipsII:
2782 *mipsIII:
2783 *mipsIV:
2784 *mipsV:
2785 *vr4100:
2786 *vr5000:
2787 {
2788   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2789     SignalException(Trap, instruction_0);
2790 }
2791
2792
2793 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2794 "tgeiu r<RS>, <IMMEDIATE>"
2795 *mipsII:
2796 *mipsIII:
2797 *mipsIV:
2798 *mipsV:
2799 *vr4100:
2800 *vr5000:
2801 {
2802   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2803     SignalException(Trap, instruction_0);
2804 }
2805
2806
2807 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2808 "tgeu r<RS>, r<RT>"
2809 *mipsII:
2810 *mipsIII:
2811 *mipsIV:
2812 *mipsV:
2813 *vr4100:
2814 *vr5000:
2815 {
2816   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2817     SignalException(Trap, instruction_0);
2818 }
2819
2820
2821 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2822 "tlt r<RS>, r<RT>"
2823 *mipsII:
2824 *mipsIII:
2825 *mipsIV:
2826 *mipsV:
2827 *vr4100:
2828 *vr5000:
2829 {
2830   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2831     SignalException(Trap, instruction_0);
2832 }
2833
2834
2835 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2836 "tlti r<RS>, <IMMEDIATE>"
2837 *mipsII:
2838 *mipsIII:
2839 *mipsIV:
2840 *mipsV:
2841 *vr4100:
2842 *vr5000:
2843 {
2844   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2845     SignalException(Trap, instruction_0);
2846 }
2847
2848
2849 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2850 "tltiu r<RS>, <IMMEDIATE>"
2851 *mipsII:
2852 *mipsIII:
2853 *mipsIV:
2854 *mipsV:
2855 *vr4100:
2856 *vr5000:
2857 {
2858   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2859     SignalException(Trap, instruction_0);
2860 }
2861
2862
2863 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2864 "tltu r<RS>, r<RT>"
2865 *mipsII:
2866 *mipsIII:
2867 *mipsIV:
2868 *mipsV:
2869 *vr4100:
2870 *vr5000:
2871 {
2872   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2873     SignalException(Trap, instruction_0);
2874 }
2875
2876
2877 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2878 "tne r<RS>, r<RT>"
2879 *mipsII:
2880 *mipsIII:
2881 *mipsIV:
2882 *mipsV:
2883 *vr4100:
2884 *vr5000:
2885 {
2886   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2887     SignalException(Trap, instruction_0);
2888 }
2889
2890
2891 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2892 "tne r<RS>, <IMMEDIATE>"
2893 *mipsII:
2894 *mipsIII:
2895 *mipsIV:
2896 *mipsV:
2897 *vr4100:
2898 *vr5000:
2899 {
2900   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2901     SignalException(Trap, instruction_0);
2902 }
2903
2904
2905 :function:::void:do_xor:int rs, int rt, int rd
2906 {
2907   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2908   GPR[rd] = GPR[rs] ^ GPR[rt];
2909   TRACE_ALU_RESULT (GPR[rd]);
2910 }
2911
2912 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
2913 "xor r<RD>, r<RS>, r<RT>"
2914 *mipsI:
2915 *mipsII:
2916 *mipsIII:
2917 *mipsIV:
2918 *mipsV:
2919 *vr4100:
2920 *vr5000:
2921 *r3900:
2922 {
2923   do_xor (SD_, RS, RT, RD);
2924 }
2925
2926
2927 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2928 {
2929   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2930   GPR[rt] = GPR[rs] ^ immediate;
2931   TRACE_ALU_RESULT (GPR[rt]);
2932 }
2933
2934 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2935 "xori r<RT>, r<RS>, <IMMEDIATE>"
2936 *mipsI:
2937 *mipsII:
2938 *mipsIII:
2939 *mipsIV:
2940 *mipsV:
2941 *vr4100:
2942 *vr5000:
2943 *r3900:
2944 {
2945   do_xori (SD_, RS, RT, IMMEDIATE);
2946 }
2947
2948 \f
2949 //
2950 // MIPS Architecture:
2951 //
2952 //        FPU Instruction Set (COP1 & COP1X)
2953 //
2954
2955
2956 :%s::::FMT:int fmt
2957 {
2958   switch (fmt)
2959     {
2960     case fmt_single: return "s";
2961     case fmt_double: return "d";
2962     case fmt_word: return "w";
2963     case fmt_long: return "l";
2964     default: return "?";
2965     }
2966 }
2967
2968 :%s::::X:int x
2969 {
2970   switch (x)
2971     {
2972     case 0: return "f";
2973     case 1: return "t";
2974     default: return "?";
2975     }
2976 }
2977
2978 :%s::::TF:int tf
2979 {
2980   if (tf)
2981     return "t";
2982   else
2983     return "f";
2984 }
2985
2986 :%s::::ND:int nd
2987 {
2988   if (nd)
2989     return "l";
2990   else
2991     return "";
2992 }
2993
2994 :%s::::COND:int cond
2995 {
2996   switch (cond)
2997     {
2998     case 00: return "f";
2999     case 01: return "un";
3000     case 02: return "eq";
3001     case 03: return "ueq";
3002     case 04: return "olt";
3003     case 05: return "ult";
3004     case 06: return "ole";
3005     case 07: return "ule";
3006     case 010: return "sf";
3007     case 011: return "ngle";
3008     case 012: return "seq";
3009     case 013: return "ngl";
3010     case 014: return "lt";
3011     case 015: return "nge";
3012     case 016: return "le";
3013     case 017: return "ngt";
3014     default: return "?";
3015     }
3016 }
3017
3018 // Helper:
3019 //
3020 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3021 // exception if not.
3022 //
3023
3024 :function:::void:check_fpu:
3025 *mipsI:
3026 *mipsII:
3027 *mipsIII:
3028 *mipsIV:
3029 *mipsV:
3030 *vr4100:
3031 *vr5000:
3032 *r3900:
3033 {
3034 #if 0   /* XXX FIXME: For now, never treat the FPU as disabled.  */
3035   if (! COP_Usable (1))
3036     SignalExceptionCoProcessorUnusable (1);
3037 #endif
3038 }
3039
3040
3041 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3042 "abs.%s<FMT> f<FD>, f<FS>"
3043 *mipsI:
3044 *mipsII:
3045 *mipsIII:
3046 *mipsIV:
3047 *mipsV:
3048 *vr4100:
3049 *vr5000:
3050 *r3900:
3051 {
3052   int fmt = FMT;
3053   check_fpu(SD_);
3054   {
3055     if ((fmt != fmt_single) && (fmt != fmt_double))
3056       SignalException(ReservedInstruction,instruction_0);
3057     else
3058       StoreFPR(FD,fmt,AbsoluteValue(ValueFPR(FS,fmt),fmt));
3059   }
3060 }
3061
3062
3063
3064 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3065 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3066 *mipsI:
3067 *mipsII:
3068 *mipsIII:
3069 *mipsIV:
3070 *mipsV:
3071 *vr4100:
3072 *vr5000:
3073 *r3900:
3074 {
3075   int fmt = FMT;
3076   check_fpu(SD_);
3077   {
3078     if ((fmt != fmt_single) && (fmt != fmt_double))
3079       SignalException(ReservedInstruction, instruction_0);
3080     else
3081       StoreFPR(FD,fmt,Add(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3082   }
3083 }
3084
3085
3086
3087 // BC1F
3088 // BC1FL
3089 // BC1T
3090 // BC1TL
3091
3092 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3093 "bc1%s<TF>%s<ND> <OFFSET>"
3094 *mipsI:
3095 *mipsII:
3096 *mipsIII:
3097 {
3098   check_fpu(SD_);
3099   check_branch_bug ();
3100   TRACE_BRANCH_INPUT (PREVCOC1());
3101   if (PREVCOC1() == TF)
3102     {
3103       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3104       TRACE_BRANCH_RESULT (dest);
3105       mark_branch_bug (dest);
3106       DELAY_SLOT (dest);
3107     }
3108   else if (ND)
3109     {
3110       TRACE_BRANCH_RESULT (0);
3111       NULLIFY_NEXT_INSTRUCTION ();
3112     }
3113   else
3114     {
3115       TRACE_BRANCH_RESULT (NIA);
3116     }
3117 }
3118
3119 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3120 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3121 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3122 *mipsIV:
3123 *mipsV:
3124 #*vr4100:
3125 *vr5000:
3126 *r3900:
3127 {
3128   check_fpu(SD_);
3129   check_branch_bug ();
3130   if (GETFCC(CC) == TF)
3131     {
3132       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3133       mark_branch_bug (dest);
3134       DELAY_SLOT (dest);
3135     }
3136   else if (ND)
3137     {
3138       NULLIFY_NEXT_INSTRUCTION ();
3139     }
3140 }
3141
3142
3143
3144
3145
3146
3147 // C.EQ.S
3148 // C.EQ.D
3149 // ...
3150
3151 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
3152 {
3153   if ((fmt != fmt_single) && (fmt != fmt_double))
3154     SignalException (ReservedInstruction, insn);
3155   else
3156     {
3157       int less;
3158       int equal;
3159       int unordered;
3160       int condition;
3161       unsigned64 ofs = ValueFPR (fs, fmt);
3162       unsigned64 oft = ValueFPR (ft, fmt);
3163       if (NaN (ofs, fmt) || NaN (oft, fmt))
3164         {
3165           if (FCSR & FP_ENABLE (IO))
3166             {
3167               FCSR |= FP_CAUSE (IO);
3168               SignalExceptionFPE ();
3169             }
3170           less = 0;
3171           equal = 0;
3172           unordered = 1;
3173         }
3174       else
3175         {
3176           less = Less (ofs, oft, fmt);
3177           equal = Equal (ofs, oft, fmt);
3178           unordered = 0;
3179         }
3180       condition = (((cond & (1 << 2)) && less)
3181                    || ((cond & (1 << 1)) && equal)
3182                    || ((cond & (1 << 0)) && unordered));
3183       SETFCC (cc, condition);
3184     }
3185 }
3186
3187 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3188 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3189 *mipsI:
3190 *mipsII:
3191 *mipsIII:
3192 {
3193   check_fpu(SD_);
3194   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
3195 }
3196
3197 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3198 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3199 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3200 *mipsIV:
3201 *mipsV:
3202 *vr4100:
3203 *vr5000:
3204 *r3900:
3205 {
3206   check_fpu(SD_);
3207   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
3208 }
3209
3210
3211 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3212 "ceil.l.%s<FMT> f<FD>, f<FS>"
3213 *mipsIII:
3214 *mipsIV:
3215 *mipsV:
3216 *vr4100:
3217 *vr5000:
3218 *r3900:
3219 {
3220   int fmt = FMT;
3221   check_fpu(SD_);
3222   {
3223     if ((fmt != fmt_single) && (fmt != fmt_double))
3224       SignalException(ReservedInstruction,instruction_0);
3225     else
3226       StoreFPR(FD,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_long));
3227   }
3228 }
3229
3230
3231 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3232 *mipsII:
3233 *mipsIII:
3234 *mipsIV:
3235 *mipsV:
3236 *vr4100:
3237 *vr5000:
3238 *r3900:
3239 {
3240   int fmt = FMT;
3241   check_fpu(SD_);
3242   {
3243   if ((fmt != fmt_single) && (fmt != fmt_double))
3244    SignalException(ReservedInstruction,instruction_0);
3245   else
3246    StoreFPR(FD,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(FS,fmt),fmt,fmt_word));
3247   }
3248 }
3249
3250
3251 // CFC1
3252 // CTC1
3253 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32,f::CxC1
3254 "c%s<X>c1 r<RT>, f<FS>"
3255 *mipsI:
3256 *mipsII:
3257 *mipsIII:
3258 {
3259   check_fpu(SD_);
3260   if (X)
3261     {
3262       if (FS == 0)
3263         PENDING_FILL(FCR0IDX,VL4_8(GPR[RT]));
3264       else if (FS == 31)
3265         PENDING_FILL(FCR31IDX,VL4_8(GPR[RT]));
3266       /* else NOP */
3267       PENDING_SCHED(FCSR, FCR31 & (1<<23), 1, 23);
3268     }
3269   else
3270     { /* control from */
3271       if (FS == 0)
3272         PENDING_FILL(RT, EXTEND32 (FCR0));
3273       else if (FS == 31)
3274         PENDING_FILL(RT, EXTEND32 (FCR31));
3275       /* else NOP */
3276     }
3277 }
3278 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32,f::CxC1
3279 "c%s<X>c1 r<RT>, f<FS>"
3280 *mipsIV:
3281 *mipsV:
3282 *vr4100:
3283 *vr5000:
3284 *r3900:
3285 {
3286   check_fpu(SD_);
3287   if (X)
3288     {
3289       /* control to */
3290       TRACE_ALU_INPUT1 (GPR[RT]);
3291       if (FS == 0)
3292         {
3293           FCR0 = VL4_8(GPR[RT]);
3294           TRACE_ALU_RESULT (FCR0);
3295         }
3296       else if (FS == 31)
3297         {
3298           FCR31 = VL4_8(GPR[RT]);
3299           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
3300           TRACE_ALU_RESULT (FCR31);
3301         }
3302       else
3303         {
3304           TRACE_ALU_RESULT0 ();
3305         }
3306       /* else NOP */
3307     }
3308   else
3309     { /* control from */
3310       if (FS == 0)
3311         {
3312           TRACE_ALU_INPUT1 (FCR0);
3313           GPR[RT] = EXTEND32 (FCR0);
3314         }
3315       else if (FS == 31)
3316         {
3317           TRACE_ALU_INPUT1 (FCR31);
3318           GPR[RT] = EXTEND32 (FCR31);
3319         }
3320       TRACE_ALU_RESULT (GPR[RT]);
3321       /* else NOP */
3322     }
3323 }
3324
3325
3326 //
3327 // FIXME: Does not correctly differentiate between mips*
3328 //
3329 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
3330 "cvt.d.%s<FMT> f<FD>, f<FS>"
3331 *mipsI:
3332 *mipsII:
3333 *mipsIII:
3334 *mipsIV:
3335 *mipsV:
3336 *vr4100:
3337 *vr5000:
3338 *r3900:
3339 {
3340   int fmt = FMT;
3341   check_fpu(SD_);
3342   {
3343     if ((fmt == fmt_double) | 0)
3344       SignalException(ReservedInstruction,instruction_0);
3345     else
3346       StoreFPR(FD,fmt_double,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_double));
3347   }
3348 }
3349
3350
3351 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
3352 "cvt.l.%s<FMT> f<FD>, f<FS>"
3353 *mipsIII:
3354 *mipsIV:
3355 *mipsV:
3356 *vr4100:
3357 *vr5000:
3358 *r3900:
3359 {
3360   int fmt = FMT;
3361   check_fpu(SD_);
3362   {
3363     if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
3364       SignalException(ReservedInstruction,instruction_0);
3365     else
3366       StoreFPR(FD,fmt_long,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_long));
3367   }
3368 }
3369
3370
3371 //
3372 // FIXME: Does not correctly differentiate between mips*
3373 //
3374 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
3375 "cvt.s.%s<FMT> f<FD>, f<FS>"
3376 *mipsI:
3377 *mipsII:
3378 *mipsIII:
3379 *mipsIV:
3380 *mipsV:
3381 *vr4100:
3382 *vr5000:
3383 *r3900:
3384 {
3385   int fmt = FMT;
3386   check_fpu(SD_);
3387   {
3388     if ((fmt == fmt_single) | 0)
3389       SignalException(ReservedInstruction,instruction_0);
3390     else
3391       StoreFPR(FD,fmt_single,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_single));
3392   }
3393 }
3394
3395
3396 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
3397 "cvt.w.%s<FMT> f<FD>, f<FS>"
3398 *mipsI:
3399 *mipsII:
3400 *mipsIII:
3401 *mipsIV:
3402 *mipsV:
3403 *vr4100:
3404 *vr5000:
3405 *r3900:
3406 {
3407   int fmt = FMT;
3408   check_fpu(SD_);
3409   {
3410     if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
3411       SignalException(ReservedInstruction,instruction_0);
3412     else
3413       StoreFPR(FD,fmt_word,Convert(GETRM(),ValueFPR(FS,fmt),fmt,fmt_word));
3414   }
3415 }
3416
3417
3418 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
3419 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
3420 *mipsI:
3421 *mipsII:
3422 *mipsIII:
3423 *mipsIV:
3424 *mipsV:
3425 *vr4100:
3426 *vr5000:
3427 *r3900:
3428 {
3429   int fmt = FMT;
3430   check_fpu(SD_);
3431   {
3432     if ((fmt != fmt_single) && (fmt != fmt_double))
3433       SignalException(ReservedInstruction,instruction_0);
3434     else
3435       StoreFPR(FD,fmt,Divide(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3436   }
3437 }
3438
3439
3440 // DMFC1
3441 // DMTC1
3442 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64,f::DMxC1
3443 "dm%s<X>c1 r<RT>, f<FS>"
3444 *mipsIII:
3445 {
3446   check_fpu(SD_);
3447   check_u64 (SD_, instruction_0);
3448   if (X)
3449     {
3450       if (SizeFGR() == 64)
3451         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3452       else if ((FS & 0x1) == 0)
3453         {
3454           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3455           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3456         }
3457     }
3458   else
3459     {
3460       if (SizeFGR() == 64)
3461         PENDING_FILL(RT,FGR[FS]);
3462       else if ((FS & 0x1) == 0)
3463         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3464       else
3465         {
3466           if (STATE_VERBOSE_P(SD))
3467             sim_io_eprintf (SD,
3468               "Warning: PC 0x%lx: semantic_DMxC1_COP1Sa 32-bit use of odd FPR number\n",
3469               (long) CIA);
3470           PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3471         }
3472     }
3473 }
3474 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64,f::DMxC1
3475 "dm%s<X>c1 r<RT>, f<FS>"
3476 *mipsIV:
3477 *mipsV:
3478 *vr4100:
3479 *vr5000:
3480 *r3900:
3481 {
3482   check_fpu(SD_);
3483   check_u64 (SD_, instruction_0);
3484   if (X)
3485     {
3486       if (SizeFGR() == 64)
3487         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3488       else if ((FS & 0x1) == 0)
3489         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3490     }
3491   else
3492     {
3493       if (SizeFGR() == 64)
3494         GPR[RT] = FGR[FS];
3495       else if ((FS & 0x1) == 0)
3496         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3497       else
3498         {
3499           if (STATE_VERBOSE_P(SD))
3500             sim_io_eprintf (SD,
3501               "Warning: PC 0x%lx: DMxC1 32-bit use of odd FPR number\n",
3502                             (long) CIA);
3503           GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3504         }
3505     }
3506 }
3507
3508
3509 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
3510 "floor.l.%s<FMT> f<FD>, f<FS>"
3511 *mipsIII:
3512 *mipsIV:
3513 *mipsV:
3514 *vr4100:
3515 *vr5000:
3516 *r3900:
3517 {
3518   int fmt = FMT;
3519   check_fpu(SD_);
3520   {
3521     if ((fmt != fmt_single) && (fmt != fmt_double))
3522       SignalException(ReservedInstruction,instruction_0);
3523     else
3524       StoreFPR(FS,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_long));
3525   }
3526 }
3527
3528
3529 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
3530 "floor.w.%s<FMT> f<FD>, f<FS>"
3531 *mipsII:
3532 *mipsIII:
3533 *mipsIV:
3534 *mipsV:
3535 *vr4100:
3536 *vr5000:
3537 *r3900:
3538 {
3539   int fmt = FMT;
3540   check_fpu(SD_);
3541   {
3542     if ((fmt != fmt_single) && (fmt != fmt_double))
3543       SignalException(ReservedInstruction,instruction_0);
3544     else
3545       StoreFPR(FD,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(FS,fmt),fmt,fmt_word));
3546   }
3547 }
3548
3549
3550 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1
3551 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3552 *mipsII:
3553 *mipsIII:
3554 *mipsIV:
3555 *mipsV:
3556 *vr4100:
3557 *vr5000:
3558 *r3900:
3559 {
3560   check_fpu(SD_);
3561   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3562 }
3563
3564
3565 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
3566 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3567 *mipsIV:
3568 *mipsV:
3569 *vr5000:
3570 {
3571   check_fpu(SD_);
3572   check_u64 (SD_, instruction_0);
3573   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3574 }
3575
3576
3577
3578 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
3579 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3580 *mipsI:
3581 *mipsII:
3582 *mipsIII:
3583 *mipsIV:
3584 *mipsV:
3585 *vr4100:
3586 *vr5000:
3587 *r3900:
3588 {
3589   check_fpu(SD_);
3590   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3591 }
3592
3593
3594 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
3595 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3596 *mipsIV:
3597 *mipsV:
3598 *vr5000:
3599 {
3600   check_fpu(SD_);
3601   check_u64 (SD_, instruction_0);
3602   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3603 }
3604
3605
3606
3607 //
3608 // FIXME: Not correct for mips*
3609 //
3610 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3611 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3612 *mipsIV:
3613 *mipsV:
3614 *vr5000:
3615 {
3616   check_fpu(SD_);
3617   {
3618     StoreFPR(FD,fmt_double,Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3619   }
3620 }
3621
3622
3623 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3624 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3625 *mipsIV:
3626 *mipsV:
3627 *vr5000:
3628 {
3629   check_fpu(SD_);
3630   {
3631     StoreFPR(FD,fmt_single,Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3632   }
3633 }
3634
3635
3636 // MFC1
3637 // MTC1
3638 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32,f::MxC1
3639 "m%s<X>c1 r<RT>, f<FS>"
3640 *mipsI:
3641 *mipsII:
3642 *mipsIII:
3643 {
3644   check_fpu(SD_);
3645   if (X)
3646     { /*MTC1*/
3647       if (SizeFGR() == 64)
3648         {
3649           if (STATE_VERBOSE_P(SD))
3650             sim_io_eprintf (SD,
3651                             "Warning:  PC 0x%lx: MTC1 not DMTC1 with 64 bit regs\n",
3652                             (long) CIA);
3653           PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3654         }
3655       else
3656         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3657     }
3658   else /*MFC1*/
3659     PENDING_FILL (RT, EXTEND32 (FGR[FS]));
3660 }
3661 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32,f::MxC1
3662 "m%s<X>c1 r<RT>, f<FS>"
3663 *mipsIV:
3664 *mipsV:
3665 *vr4100:
3666 *vr5000:
3667 *r3900:
3668 {
3669   int fs = FS;
3670   check_fpu(SD_);
3671   if (X)
3672     /*MTC1*/
3673     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3674   else /*MFC1*/
3675     GPR[RT] = EXTEND32 (FGR[FS]);
3676 }
3677
3678
3679 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
3680 "mov.%s<FMT> f<FD>, f<FS>"
3681 *mipsI:
3682 *mipsII:
3683 *mipsIII:
3684 *mipsIV:
3685 *mipsV:
3686 *vr4100:
3687 *vr5000:
3688 *r3900:
3689 {
3690   int fmt = FMT;
3691   check_fpu(SD_);
3692   StoreFPR(FD,fmt,ValueFPR(FS,fmt));
3693 }
3694
3695
3696 // MOVF
3697 // MOVT
3698 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
3699 "mov%s<TF> r<RD>, r<RS>, <CC>"
3700 *mipsIV:
3701 *mipsV:
3702 *vr5000:
3703 {
3704   check_fpu(SD_);
3705   if (GETFCC(CC) == TF)
3706     GPR[RD] = GPR[RS];
3707 }
3708
3709
3710 // MOVF.fmt
3711 // MOVT.fmt
3712 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
3713 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3714 *mipsIV:
3715 *mipsV:
3716 *vr5000:
3717 {
3718   int fmt = FMT;
3719   check_fpu(SD_);
3720   {
3721    if (GETFCC(CC) == TF)
3722      StoreFPR (FD, fmt, ValueFPR (FS, fmt));
3723    else
3724      StoreFPR (FD, fmt, ValueFPR (FD, fmt));
3725   }
3726 }
3727
3728
3729 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
3730 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
3731 *mipsIV:
3732 *mipsV:
3733 *vr5000:
3734 {
3735   check_fpu(SD_);
3736   if (GPR[RT] != 0)
3737     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3738   else
3739     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3740 }
3741
3742
3743 // MOVT see MOVtf
3744
3745
3746 // MOVT.fmt see MOVtf.fmt
3747
3748
3749
3750 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
3751 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3752 *mipsIV:
3753 *mipsV:
3754 *vr5000:
3755 {
3756   check_fpu(SD_);
3757   if (GPR[RT] == 0)
3758     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
3759   else
3760     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
3761 }
3762
3763
3764 // MSUB.fmt
3765 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32,f::MSUB.D
3766 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3767 *mipsIV:
3768 *mipsV:
3769 *vr5000:
3770 {
3771   check_fpu(SD_);
3772   StoreFPR(FD,fmt_double,Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double));
3773 }
3774
3775
3776 // MSUB.fmt
3777 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32,f::MSUB.S
3778 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3779 *mipsIV:
3780 *mipsV:
3781 *vr5000:
3782 {
3783   check_fpu(SD_);
3784   StoreFPR(FD,fmt_single,Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single));
3785 }
3786
3787
3788 // MTC1 see MxC1
3789
3790
3791 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
3792 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3793 *mipsI:
3794 *mipsII:
3795 *mipsIII:
3796 *mipsIV:
3797 *mipsV:
3798 *vr4100:
3799 *vr5000:
3800 *r3900:
3801 {
3802   int fmt = FMT;
3803   check_fpu(SD_);
3804   {
3805     if ((fmt != fmt_single) && (fmt != fmt_double))
3806       SignalException(ReservedInstruction,instruction_0);
3807     else
3808       StoreFPR(FD,fmt,Multiply(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
3809   }
3810 }
3811
3812
3813 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
3814 "neg.%s<FMT> f<FD>, f<FS>"
3815 *mipsI:
3816 *mipsII:
3817 *mipsIII:
3818 *mipsIV:
3819 *mipsV:
3820 *vr4100:
3821 *vr5000:
3822 *r3900:
3823 {
3824   int fmt = FMT;
3825   check_fpu(SD_);
3826   {
3827     if ((fmt != fmt_single) && (fmt != fmt_double))
3828       SignalException(ReservedInstruction,instruction_0);
3829     else
3830       StoreFPR(FD,fmt,Negate(ValueFPR(FS,fmt),fmt));
3831   }
3832 }
3833
3834
3835 // NMADD.fmt
3836 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32,f::NMADD.D
3837 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3838 *mipsIV:
3839 *mipsV:
3840 *vr5000:
3841 {
3842   check_fpu(SD_);
3843   StoreFPR(FD,fmt_double,Negate(Add(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3844 }
3845
3846
3847 // NMADD.fmt
3848 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32,f::NMADD.S
3849 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3850 *mipsIV:
3851 *mipsV:
3852 *vr5000:
3853 {
3854   check_fpu(SD_);
3855   StoreFPR(FD,fmt_single,Negate(Add(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3856 }
3857
3858
3859 // NMSUB.fmt
3860 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32,f::NMSUB.D
3861 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3862 *mipsIV:
3863 *mipsV:
3864 *vr5000:
3865 {
3866   check_fpu(SD_);
3867   StoreFPR(FD,fmt_double,Negate(Sub(Multiply(ValueFPR(FS,fmt_double),ValueFPR(FT,fmt_double),fmt_double),ValueFPR(FR,fmt_double),fmt_double),fmt_double));
3868 }
3869
3870
3871 // NMSUB.fmt
3872 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32,f::NMSUB.S
3873 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3874 *mipsIV:
3875 *mipsV:
3876 *vr5000:
3877 {
3878   check_fpu(SD_);
3879   StoreFPR(FD,fmt_single,Negate(Sub(Multiply(ValueFPR(FS,fmt_single),ValueFPR(FT,fmt_single),fmt_single),ValueFPR(FR,fmt_single),fmt_single),fmt_single));
3880 }
3881
3882
3883 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
3884 "prefx <HINT>, r<INDEX>(r<BASE>)"
3885 *mipsIV:
3886 *mipsV:
3887 *vr5000:
3888 {
3889   address_word base = GPR[BASE];
3890   address_word index = GPR[INDEX];
3891   {
3892     address_word vaddr = ((unsigned64)base + (unsigned64)index);
3893     address_word paddr;
3894     int uncached;
3895     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3896       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3897   }
3898 }
3899
3900 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
3901 "recip.%s<FMT> f<FD>, f<FS>"
3902 *mipsIV:
3903 *mipsV:
3904 *vr5000:
3905 {
3906   int fmt = FMT;
3907   check_fpu(SD_);
3908   {
3909   if ((fmt != fmt_single) && (fmt != fmt_double))
3910    SignalException(ReservedInstruction,instruction_0);
3911   else
3912    StoreFPR(FD,fmt,Recip(ValueFPR(FS,fmt),fmt));
3913   }
3914 }
3915
3916
3917 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
3918 "round.l.%s<FMT> f<FD>, f<FS>"
3919 *mipsIII:
3920 *mipsIV:
3921 *mipsV:
3922 *vr4100:
3923 *vr5000:
3924 *r3900:
3925 {
3926   int fmt = FMT;
3927   check_fpu(SD_);
3928   {
3929     if ((fmt != fmt_single) && (fmt != fmt_double))
3930       SignalException(ReservedInstruction,instruction_0);
3931     else
3932       StoreFPR(FD,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_long));
3933   }
3934 }
3935
3936
3937 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
3938 "round.w.%s<FMT> f<FD>, f<FS>"
3939 *mipsII:
3940 *mipsIII:
3941 *mipsIV:
3942 *mipsV:
3943 *vr4100:
3944 *vr5000:
3945 *r3900:
3946 {
3947   int fmt = FMT;
3948   check_fpu(SD_);
3949   {
3950   if ((fmt != fmt_single) && (fmt != fmt_double))
3951    SignalException(ReservedInstruction,instruction_0);
3952   else
3953    StoreFPR(FD,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(FS,fmt),fmt,fmt_word));
3954   }
3955 }
3956
3957
3958 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
3959 *mipsIV:
3960 *mipsV:
3961 "rsqrt.%s<FMT> f<FD>, f<FS>"
3962 *vr5000:
3963 {
3964   int fmt = FMT;
3965   check_fpu(SD_);
3966   {
3967   if ((fmt != fmt_single) && (fmt != fmt_double))
3968    SignalException(ReservedInstruction,instruction_0);
3969   else
3970    StoreFPR(FD,fmt,Recip(SquareRoot(ValueFPR(FS,fmt),fmt),fmt));
3971   }
3972 }
3973
3974
3975 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1
3976 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
3977 *mipsII:
3978 *mipsIII:
3979 *mipsIV:
3980 *mipsV:
3981 *vr4100:
3982 *vr5000:
3983 *r3900:
3984 {
3985   check_fpu(SD_);
3986   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3987 }
3988
3989
3990 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
3991 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
3992 *mipsIV:
3993 *mipsV:
3994 *vr5000:
3995 {
3996   check_fpu(SD_);
3997   check_u64 (SD_, instruction_0);
3998   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
3999 }
4000
4001
4002 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4003 "sqrt.%s<FMT> f<FD>, f<FS>"
4004 *mipsII:
4005 *mipsIII:
4006 *mipsIV:
4007 *mipsV:
4008 *vr4100:
4009 *vr5000:
4010 *r3900:
4011 {
4012   int fmt = FMT;
4013   check_fpu(SD_);
4014   {
4015     if ((fmt != fmt_single) && (fmt != fmt_double))
4016       SignalException(ReservedInstruction,instruction_0);
4017     else
4018       StoreFPR(FD,fmt,(SquareRoot(ValueFPR(FS,fmt),fmt)));
4019   }
4020 }
4021
4022
4023 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4024 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4025 *mipsI:
4026 *mipsII:
4027 *mipsIII:
4028 *mipsIV:
4029 *mipsV:
4030 *vr4100:
4031 *vr5000:
4032 *r3900:
4033 {
4034   int fmt = FMT;
4035   check_fpu(SD_);
4036   {
4037     if ((fmt != fmt_single) && (fmt != fmt_double))
4038       SignalException(ReservedInstruction,instruction_0);
4039     else
4040       StoreFPR(FD,fmt,Sub(ValueFPR(FS,fmt),ValueFPR(FT,fmt),fmt));
4041   }
4042 }
4043
4044
4045
4046 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4047 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4048 *mipsI:
4049 *mipsII:
4050 *mipsIII:
4051 *mipsIV:
4052 *mipsV:
4053 *vr4100:
4054 *vr5000:
4055 *r3900:
4056 {
4057   signed_word offset = EXTEND16 (OFFSET);
4058   check_fpu(SD_);
4059   {
4060     address_word vaddr = ((uword64)GPR[BASE] + offset);
4061     address_word paddr;
4062     int uncached;
4063     if ((vaddr & 3) != 0)
4064       {
4065         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4066       }
4067     else
4068       {
4069         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4070           {
4071             uword64 memval = 0;
4072             uword64 memval1 = 0;
4073             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4074             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4075             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4076             unsigned int byte;
4077             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4078             byte = ((vaddr & mask) ^ bigendiancpu);
4079             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4080             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4081           }
4082       }
4083   }
4084 }
4085
4086
4087 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4088 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4089 *mipsIV:
4090 *mipsV:
4091 *vr5000:
4092 {
4093
4094   address_word base = GPR[BASE];
4095   address_word index = GPR[INDEX];
4096   check_fpu(SD_);
4097   check_u64 (SD_, instruction_0);
4098   {
4099    address_word vaddr = ((unsigned64)base + index);
4100    address_word paddr;
4101    int uncached;
4102    if ((vaddr & 3) != 0)
4103      {
4104        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4105      }
4106    else
4107    {
4108     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4109     {
4110      unsigned64 memval = 0;
4111      unsigned64 memval1 = 0;
4112      unsigned64 mask = 0x7;
4113      unsigned int byte;
4114      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4115      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4116      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4117       {
4118        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4119       }
4120     }
4121    }
4122   }
4123 }
4124
4125
4126 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4127 "trunc.l.%s<FMT> f<FD>, f<FS>"
4128 *mipsIII:
4129 *mipsIV:
4130 *mipsV:
4131 *vr4100:
4132 *vr5000:
4133 *r3900:
4134 {
4135   int fmt = FMT;
4136   check_fpu(SD_);
4137   {
4138   if ((fmt != fmt_single) && (fmt != fmt_double))
4139    SignalException(ReservedInstruction,instruction_0);
4140   else
4141    StoreFPR(FD,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_long));
4142   }
4143 }
4144
4145
4146 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4147 "trunc.w.%s<FMT> f<FD>, f<FS>"
4148 *mipsII:
4149 *mipsIII:
4150 *mipsIV:
4151 *mipsV:
4152 *vr4100:
4153 *vr5000:
4154 *r3900:
4155 {
4156   int fmt = FMT;
4157   check_fpu(SD_);
4158   {
4159   if ((fmt != fmt_single) && (fmt != fmt_double))
4160    SignalException(ReservedInstruction,instruction_0);
4161   else
4162    StoreFPR(FD,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(FS,fmt),fmt,fmt_word));
4163   }
4164 }
4165
4166 \f
4167 //
4168 // MIPS Architecture:
4169 //
4170 //        System Control Instruction Set (COP0)
4171 //
4172
4173
4174 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4175 "bc0f <OFFSET>"
4176 *mipsI:
4177 *mipsII:
4178 *mipsIII:
4179 *mipsIV:
4180 *mipsV:
4181 *vr4100:
4182 *vr5000:
4183
4184 010000,01000,00000,16.OFFSET:COP0:32::BC0F
4185 "bc0f <OFFSET>"
4186 // stub needed for eCos as tx39 hardware bug workaround
4187 *r3900:
4188 {
4189   /* do nothing */
4190 }
4191
4192
4193 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
4194 "bc0fl <OFFSET>"
4195 *mipsI:
4196 *mipsII:
4197 *mipsIII:
4198 *mipsIV:
4199 *mipsV:
4200 *vr4100:
4201 *vr5000:
4202
4203
4204 010000,01000,00001,16.OFFSET:COP0:32::BC0T
4205 "bc0t <OFFSET>"
4206 *mipsI:
4207 *mipsII:
4208 *mipsIII:
4209 *mipsIV:
4210 *mipsV:
4211 *vr4100:
4212
4213
4214 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
4215 "bc0tl <OFFSET>"
4216 *mipsI:
4217 *mipsII:
4218 *mipsIII:
4219 *mipsIV:
4220 *mipsV:
4221 *vr4100:
4222 *vr5000:
4223
4224
4225 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
4226 "cache <OP>, <OFFSET>(r<BASE>)"
4227 *mipsIII:
4228 *mipsIV:
4229 *mipsV:
4230 *vr4100:
4231 *vr5000:
4232 *r3900:
4233 {
4234   address_word base = GPR[BASE];
4235   address_word offset = EXTEND16 (OFFSET);
4236   {
4237     address_word vaddr = (base + offset);
4238     address_word paddr;
4239     int uncached;
4240     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4241       CacheOp(OP,vaddr,paddr,instruction_0);
4242   }
4243 }
4244
4245
4246 010000,1,0000000000000000000,111001:COP0:32::DI
4247 "di"
4248 *mipsI:
4249 *mipsII:
4250 *mipsIII:
4251 *mipsIV:
4252 *mipsV:
4253 *vr4100:
4254 *vr5000:
4255
4256
4257 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
4258 "dmfc0 r<RT>, r<RD>"
4259 *mipsIII:
4260 *mipsIV:
4261 *mipsV:
4262 {
4263   check_u64 (SD_, instruction_0);
4264   DecodeCoproc (instruction_0);
4265 }
4266
4267
4268 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
4269 "dmtc0 r<RT>, r<RD>"
4270 *mipsIII:
4271 *mipsIV:
4272 *mipsV:
4273 {
4274   check_u64 (SD_, instruction_0);
4275   DecodeCoproc (instruction_0);
4276 }
4277
4278
4279 010000,1,0000000000000000000,111000:COP0:32::EI
4280 "ei"
4281 *mipsI:
4282 *mipsII:
4283 *mipsIII:
4284 *mipsIV:
4285 *mipsV:
4286 *vr4100:
4287 *vr5000:
4288
4289
4290 010000,1,0000000000000000000,011000:COP0:32::ERET
4291 "eret"
4292 *mipsIII:
4293 *mipsIV:
4294 *mipsV:
4295 *vr4100:
4296 *vr5000:
4297 {
4298   if (SR & status_ERL)
4299     {
4300       /* Oops, not yet available */
4301       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
4302       NIA = EPC;
4303       SR &= ~status_ERL;
4304     }
4305   else
4306     {
4307       NIA = EPC;
4308       SR &= ~status_EXL;
4309     }
4310 }
4311
4312
4313 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
4314 "mfc0 r<RT>, r<RD> # <REGX>"
4315 *mipsI:
4316 *mipsII:
4317 *mipsIII:
4318 *mipsIV:
4319 *mipsV:
4320 *vr4100:
4321 *vr5000:
4322 *r3900:
4323 {
4324   TRACE_ALU_INPUT0 ();
4325   DecodeCoproc (instruction_0);
4326   TRACE_ALU_RESULT (GPR[RT]);
4327 }
4328
4329 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
4330 "mtc0 r<RT>, r<RD> # <REGX>"
4331 *mipsI:
4332 *mipsII:
4333 *mipsIII:
4334 *mipsIV:
4335 *mipsV:
4336 *vr4100:
4337 *vr5000:
4338 *r3900:
4339 {
4340   DecodeCoproc (instruction_0);
4341 }
4342
4343
4344 010000,1,0000000000000000000,010000:COP0:32::RFE
4345 "rfe"
4346 *mipsI:
4347 *mipsII:
4348 *mipsIII:
4349 *mipsIV:
4350 *mipsV:
4351 *vr4100:
4352 *vr5000:
4353 *r3900:
4354 {
4355   DecodeCoproc (instruction_0);
4356 }
4357
4358
4359 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
4360 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
4361 *mipsI:
4362 *mipsII:
4363 *mipsIII:
4364 *mipsIV:
4365 *mipsV:
4366 *vr4100:
4367 *r3900:
4368 {
4369   DecodeCoproc (instruction_0);
4370 }
4371
4372
4373
4374 010000,1,0000000000000000000,001000:COP0:32::TLBP
4375 "tlbp"
4376 *mipsI:
4377 *mipsII:
4378 *mipsIII:
4379 *mipsIV:
4380 *mipsV:
4381 *vr4100:
4382 *vr5000:
4383
4384
4385 010000,1,0000000000000000000,000001:COP0:32::TLBR
4386 "tlbr"
4387 *mipsI:
4388 *mipsII:
4389 *mipsIII:
4390 *mipsIV:
4391 *mipsV:
4392 *vr4100:
4393 *vr5000:
4394
4395
4396 010000,1,0000000000000000000,000010:COP0:32::TLBWI
4397 "tlbwi"
4398 *mipsI:
4399 *mipsII:
4400 *mipsIII:
4401 *mipsIV:
4402 *mipsV:
4403 *vr4100:
4404 *vr5000:
4405
4406
4407 010000,1,0000000000000000000,000110:COP0:32::TLBWR
4408 "tlbwr"
4409 *mipsI:
4410 *mipsII:
4411 *mipsIII:
4412 *mipsIV:
4413 *mipsV:
4414 *vr4100:
4415 *vr5000:
4416
4417 \f
4418 :include:::m16.igen
4419 :include:::tx.igen
4420 :include:::vr.igen
4421 \f