sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips16e:mips16e:               // m16e.igen
  72 :model:::mips3d:mips3d:                 // mips3d.igen
  73 :model:::mdmx:mdmx:                     // mdmx.igen
  74 :model:::dsp:dsp:                       // dsp.igen
  75 :model:::smartmips:smartmips:           // smartmips.igen
  76
  77 //  Vendor Extensions
  78 //
  79 //  Instructions specific to these extensions are in separate .igen files.
  80 //  Extensions add instructions on to a base ISA.
  81 :model:::sb1:sb1:                       // sb1.igen
  82
  83
  84 // Pseudo instructions known by IGEN
  85 :internal::::illegal:
  86 {
  87   SignalException (ReservedInstruction, 0);
  88 }
  89
  90
  91 // Pseudo instructions known by interp.c
  92 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  93 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  94 "rsvd <OP>"
  95 {
  96   SignalException (ReservedInstruction, instruction_0);
  97 }
  98
  99
 100
 101 // Helper:
 102 //
 103 // Simulate a 32 bit delayslot instruction
 104 //
 105
 106 :function:::address_word:delayslot32:address_word target
 107 {
 108   instruction_word delay_insn;
 109   sim_events_slip (SD, 1);
 110   DSPC = CIA;
 111   CIA = CIA + 4; /* NOTE not mips16 */
 112   STATE |= simDELAYSLOT;
 113   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 114   ENGINE_ISSUE_PREFIX_HOOK();
 115   idecode_issue (CPU_, delay_insn, (CIA));
 116   STATE &= ~simDELAYSLOT;
 117   return target;
 118 }
 119
 120 :function:::address_word:nullify_next_insn32:
 121 {
 122   sim_events_slip (SD, 1);
 123   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 124   return CIA + 8;
 125 }
 126
 127
 128 // Helper:
 129 //
 130 // Calculate an effective address given a base and an offset.
 131 //
 132
 133 :function:::address_word:loadstore_ea:address_word base, address_word offset
 134 *mipsI:
 135 *mipsII:
 136 *mipsIII:
 137 *mipsIV:
 138 *mipsV:
 139 *mips32:
 140 *mips32r2:
 141 *vr4100:
 142 *vr5000:
 143 *r3900:
 144 {
 145   return base + offset;
 146 }
 147
 148 :function:::address_word:loadstore_ea:address_word base, address_word offset
 149 *mips64:
 150 *mips64r2:
 151 {
 152 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 153   /* If in user mode and UX is not set, use 32-bit compatibility effective
 154      address computations as defined in the MIPS64 Architecture for
 155      Programmers Volume III, Revision 0.95, section 4.9.  */
 156   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 157       == (ksu_user << status_KSU_shift))
 158     return (address_word)((signed32)base + (signed32)offset);
 159 #endif
 160   return base + offset;
 161 }
 162
 163
 164 // Helper:
 165 //
 166 // Check that a 32-bit register value is properly sign-extended.
 167 // (See NotWordValue in ISA spec.)
 168 //
 169
 170 :function:::int:not_word_value:unsigned_word value
 171 *mipsI:
 172 *mipsII:
 173 *mipsIII:
 174 *mipsIV:
 175 *mipsV:
 176 *vr4100:
 177 *vr5000:
 178 *r3900:
 179 *mips32:
 180 *mips32r2:
 181 *mips64:
 182 *mips64r2:
 183 {
 184 #if WITH_TARGET_WORD_BITSIZE == 64
 185   return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
 186 #else
 187   return 0;
 188 #endif
 189 }
 190
 191 // Helper:
 192 //
 193 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 194 // theoretically portable code which invokes non-portable behaviour from
 195 // running with no indication of the portability issue.
 196 // (See definition of UNPREDICTABLE in ISA spec.)
 197 //
 198
 199 :function:::void:unpredictable:
 200 *mipsI:
 201 *mipsII:
 202 *mipsIII:
 203 *mipsIV:
 204 *mipsV:
 205 *vr4100:
 206 *vr5000:
 207 *r3900:
 208 {
 209 }
 210
 211 :function:::void:unpredictable:
 212 *mips32:
 213 *mips32r2:
 214 *mips64:
 215 *mips64r2:
 216 {
 217   unpredictable_action (CPU, CIA);
 218 }
 219
 220
 221 // Helpers:
 222 //
 223 // Check that an access to a HI/LO register meets timing requirements
 224 //
 225 // In all MIPS ISAs,
 226 //
 227 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 228 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 229 //
 230 // The following restrictions exist for MIPS I - MIPS III:
 231 //
 232 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 233 //      in between makes MF UNPREDICTABLE. (2)
 234 //
 235 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 236 //      in between makes MF UNPREDICTABLE. (3)
 237 //
 238 // On the r3900, restriction (2) is not present, and restriction (3) is not
 239 // present for multiplication.
 240 //
 241 // Unfortunately, there seems to be some confusion about whether the last
 242 // two restrictions should apply to "MIPS IV" as well.  One edition of
 243 // the MIPS IV ISA says they do, but references in later ISA documents
 244 // suggest they don't.
 245 //
 246 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 247 // these restrictions, while others, like the VR5500, don't.  To accomodate
 248 // such differences, the MIPS IV and MIPS V version of these helper functions
 249 // use auxillary routines to determine whether the restriction applies.
 250
 251 // check_mf_cycles:
 252 //
 253 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 254 // to check for restrictions (2) and (3) above.
 255 //
 256 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 257 {
 258   if (history->mf.timestamp + 3 > time)
 259     {
 260       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 261                         itable[MY_INDEX].name,
 262                         new, (long) CIA,
 263                         (long) history->mf.cia);
 264       return 0;
 265     }
 266   return 1;
 267 }
 268
 269
 270 // check_mt_hilo:
 271 //
 272 // Check for restriction (2) above (for ISAs/processors that have it),
 273 // and record timestamps for restriction (1) above.
 274 //
 275 :function:::int:check_mt_hilo:hilo_history *history
 276 *mipsI:
 277 *mipsII:
 278 *mipsIII:
 279 *vr4100:
 280 *vr5000:
 281 {
 282   signed64 time = sim_events_time (SD);
 283   int ok = check_mf_cycles (SD_, history, time, "MT");
 284   history->mt.timestamp = time;
 285   history->mt.cia = CIA;
 286   return ok;
 287 }
 288
 289 :function:::int:check_mt_hilo:hilo_history *history
 290 *mipsIV:
 291 *mipsV:
 292 {
 293   signed64 time = sim_events_time (SD);
 294   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 295             || check_mf_cycles (SD_, history, time, "MT"));
 296   history->mt.timestamp = time;
 297   history->mt.cia = CIA;
 298   return ok;
 299 }
 300
 301 :function:::int:check_mt_hilo:hilo_history *history
 302 *mips32:
 303 *mips32r2:
 304 *mips64:
 305 *mips64r2:
 306 *r3900:
 307 {
 308   signed64 time = sim_events_time (SD);
 309   history->mt.timestamp = time;
 310   history->mt.cia = CIA;
 311   return 1;
 312 }
 313
 314
 315 // check_mf_hilo:
 316 //
 317 // Check for restriction (1) above, and record timestamps for
 318 // restriction (2) and (3) above.
 319 //
 320 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 321 *mipsI:
 322 *mipsII:
 323 *mipsIII:
 324 *mipsIV:
 325 *mipsV:
 326 *mips32:
 327 *mips32r2:
 328 *mips64:
 329 *mips64r2:
 330 *vr4100:
 331 *vr5000:
 332 *r3900:
 333 {
 334   signed64 time = sim_events_time (SD);
 335   int ok = 1;
 336   if (peer != NULL
 337       && peer->mt.timestamp > history->op.timestamp
 338       && history->mt.timestamp < history->op.timestamp
 339       && ! (history->mf.timestamp > history->op.timestamp
 340             && history->mf.timestamp < peer->mt.timestamp)
 341       && ! (peer->mf.timestamp > history->op.timestamp
 342             && peer->mf.timestamp < peer->mt.timestamp))
 343     {
 344       /* The peer has been written to since the last OP yet we have
 345          not */
 346       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 347                         itable[MY_INDEX].name,
 348                         (long) CIA,
 349                         (long) history->op.cia,
 350                         (long) peer->mt.cia);
 351       ok = 0;
 352     }
 353   history->mf.timestamp = time;
 354   history->mf.cia = CIA;
 355   return ok;
 356 }
 357
 358
 359
 360 // check_mult_hilo:
 361 //
 362 // Check for restriction (3) above (for ISAs/processors that have it)
 363 // for MULT ops, and record timestamps for restriction (1) above.
 364 //
 365 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 366 *mipsI:
 367 *mipsII:
 368 *mipsIII:
 369 *vr4100:
 370 *vr5000:
 371 {
 372   signed64 time = sim_events_time (SD);
 373   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 374             && check_mf_cycles (SD_, lo, time, "OP"));
 375   hi->op.timestamp = time;
 376   lo->op.timestamp = time;
 377   hi->op.cia = CIA;
 378   lo->op.cia = CIA;
 379   return ok;
 380 }
 381
 382 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 383 *mipsIV:
 384 *mipsV:
 385 {
 386   signed64 time = sim_events_time (SD);
 387   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 388             || (check_mf_cycles (SD_, hi, time, "OP")
 389                 && check_mf_cycles (SD_, lo, time, "OP")));
 390   hi->op.timestamp = time;
 391   lo->op.timestamp = time;
 392   hi->op.cia = CIA;
 393   lo->op.cia = CIA;
 394   return ok;
 395 }
 396
 397 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 398 *mips32:
 399 *mips32r2:
 400 *mips64:
 401 *mips64r2:
 402 *r3900:
 403 {
 404   /* FIXME: could record the fact that a stall occured if we want */
 405   signed64 time = sim_events_time (SD);
 406   hi->op.timestamp = time;
 407   lo->op.timestamp = time;
 408   hi->op.cia = CIA;
 409   lo->op.cia = CIA;
 410   return 1;
 411 }
 412
 413
 414 // check_div_hilo:
 415 //
 416 // Check for restriction (3) above (for ISAs/processors that have it)
 417 // for DIV ops, and record timestamps for restriction (1) above.
 418 //
 419 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 420 *mipsI:
 421 *mipsII:
 422 *mipsIII:
 423 *vr4100:
 424 *vr5000:
 425 *r3900:
 426 {
 427   signed64 time = sim_events_time (SD);
 428   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 429             && check_mf_cycles (SD_, lo, time, "OP"));
 430   hi->op.timestamp = time;
 431   lo->op.timestamp = time;
 432   hi->op.cia = CIA;
 433   lo->op.cia = CIA;
 434   return ok;
 435 }
 436
 437 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 438 *mipsIV:
 439 *mipsV:
 440 {
 441   signed64 time = sim_events_time (SD);
 442   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 443             || (check_mf_cycles (SD_, hi, time, "OP")
 444                 && check_mf_cycles (SD_, lo, time, "OP")));
 445   hi->op.timestamp = time;
 446   lo->op.timestamp = time;
 447   hi->op.cia = CIA;
 448   lo->op.cia = CIA;
 449   return ok;
 450 }
 451
 452 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 453 *mips32:
 454 *mips32r2:
 455 *mips64:
 456 *mips64r2:
 457 {
 458   signed64 time = sim_events_time (SD);
 459   hi->op.timestamp = time;
 460   lo->op.timestamp = time;
 461   hi->op.cia = CIA;
 462   lo->op.cia = CIA;
 463   return 1;
 464 }
 465
 466
 467 // Helper:
 468 //
 469 // Check that the 64-bit instruction can currently be used, and signal
 470 // a ReservedInstruction exception if not.
 471 //
 472
 473 :function:::void:check_u64:instruction_word insn
 474 *mipsIII:
 475 *mipsIV:
 476 *mipsV:
 477 *vr4100:
 478 *vr5000:
 479 *vr5400:
 480 *vr5500:
 481 {
 482   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 483 }
 484
 485 :function:::void:check_u64:instruction_word insn
 486 *mips16e:
 487 *mips64:
 488 *mips64r2:
 489 {
 490 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 491   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 492     SignalException (ReservedInstruction, insn);
 493 #endif
 494 }
 495
 496
 497
 498 //
 499 // MIPS Architecture:
 500 //
 501 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 502 //
 503
 504
 505
 506 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 507 "add r<RD>, r<RS>, r<RT>"
 508 *mipsI:
 509 *mipsII:
 510 *mipsIII:
 511 *mipsIV:
 512 *mipsV:
 513 *mips32:
 514 *mips32r2:
 515 *mips64:
 516 *mips64r2:
 517 *vr4100:
 518 *vr5000:
 519 *r3900:
 520 {
 521   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 522     Unpredictable ();
 523   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 524   {
 525     ALU32_BEGIN (GPR[RS]);
 526     ALU32_ADD (GPR[RT]);
 527     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 528   }
 529   TRACE_ALU_RESULT (GPR[RD]);
 530 }
 531
 532
 533
 534 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 535 "addi r<RT>, r<RS>, <IMMEDIATE>"
 536 *mipsI:
 537 *mipsII:
 538 *mipsIII:
 539 *mipsIV:
 540 *mipsV:
 541 *mips32:
 542 *mips32r2:
 543 *mips64:
 544 *mips64r2:
 545 *vr4100:
 546 *vr5000:
 547 *r3900:
 548 {
 549   if (NotWordValue (GPR[RS]))
 550     Unpredictable ();
 551   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 552   {
 553     ALU32_BEGIN (GPR[RS]);
 554     ALU32_ADD (EXTEND16 (IMMEDIATE));
 555     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 556   }
 557   TRACE_ALU_RESULT (GPR[RT]);
 558 }
 559
 560
 561
 562 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 563 {
 564   if (NotWordValue (GPR[rs]))
 565     Unpredictable ();
 566   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 567   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 568   TRACE_ALU_RESULT (GPR[rt]);
 569 }
 570
 571 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 572 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 573 *mipsI:
 574 *mipsII:
 575 *mipsIII:
 576 *mipsIV:
 577 *mipsV:
 578 *mips32:
 579 *mips32r2:
 580 *mips64:
 581 *mips64r2:
 582 *vr4100:
 583 *vr5000:
 584 *r3900:
 585 {
 586   do_addiu (SD_, RS, RT, IMMEDIATE);
 587 }
 588
 589
 590
 591 :function:::void:do_addu:int rs, int rt, int rd
 592 {
 593   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 594     Unpredictable ();
 595   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 596   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 597   TRACE_ALU_RESULT (GPR[rd]);
 598 }
 599
 600 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 601 "addu r<RD>, r<RS>, r<RT>"
 602 *mipsI:
 603 *mipsII:
 604 *mipsIII:
 605 *mipsIV:
 606 *mipsV:
 607 *mips32:
 608 *mips32r2:
 609 *mips64:
 610 *mips64r2:
 611 *vr4100:
 612 *vr5000:
 613 *r3900:
 614 {
 615   do_addu (SD_, RS, RT, RD);
 616 }
 617
 618
 619
 620 :function:::void:do_and:int rs, int rt, int rd
 621 {
 622   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 623   GPR[rd] = GPR[rs] & GPR[rt];
 624   TRACE_ALU_RESULT (GPR[rd]);
 625 }
 626
 627 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 628 "and r<RD>, r<RS>, r<RT>"
 629 *mipsI:
 630 *mipsII:
 631 *mipsIII:
 632 *mipsIV:
 633 *mipsV:
 634 *mips32:
 635 *mips32r2:
 636 *mips64:
 637 *mips64r2:
 638 *vr4100:
 639 *vr5000:
 640 *r3900:
 641 {
 642   do_and (SD_, RS, RT, RD);
 643 }
 644
 645
 646
 647 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 648 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 649 *mipsI:
 650 *mipsII:
 651 *mipsIII:
 652 *mipsIV:
 653 *mipsV:
 654 *mips32:
 655 *mips32r2:
 656 *mips64:
 657 *mips64r2:
 658 *vr4100:
 659 *vr5000:
 660 *r3900:
 661 {
 662   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 663   GPR[RT] = GPR[RS] & IMMEDIATE;
 664   TRACE_ALU_RESULT (GPR[RT]);
 665 }
 666
 667
 668
 669 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 670 "beq r<RS>, r<RT>, <OFFSET>"
 671 *mipsI:
 672 *mipsII:
 673 *mipsIII:
 674 *mipsIV:
 675 *mipsV:
 676 *mips32:
 677 *mips32r2:
 678 *mips64:
 679 *mips64r2:
 680 *vr4100:
 681 *vr5000:
 682 *r3900:
 683 {
 684   address_word offset = EXTEND16 (OFFSET) << 2;
 685   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 686     {
 687       DELAY_SLOT (NIA + offset);
 688     }
 689 }
 690
 691
 692
 693 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 694 "beql r<RS>, r<RT>, <OFFSET>"
 695 *mipsII:
 696 *mipsIII:
 697 *mipsIV:
 698 *mipsV:
 699 *mips32:
 700 *mips32r2:
 701 *mips64:
 702 *mips64r2:
 703 *vr4100:
 704 *vr5000:
 705 *r3900:
 706 {
 707   address_word offset = EXTEND16 (OFFSET) << 2;
 708   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 709     {
 710       DELAY_SLOT (NIA + offset);
 711     }
 712   else
 713     NULLIFY_NEXT_INSTRUCTION ();
 714 }
 715
 716
 717
 718 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 719 "bgez r<RS>, <OFFSET>"
 720 *mipsI:
 721 *mipsII:
 722 *mipsIII:
 723 *mipsIV:
 724 *mipsV:
 725 *mips32:
 726 *mips32r2:
 727 *mips64:
 728 *mips64r2:
 729 *vr4100:
 730 *vr5000:
 731 *r3900:
 732 {
 733   address_word offset = EXTEND16 (OFFSET) << 2;
 734   if ((signed_word) GPR[RS] >= 0)
 735     {
 736       DELAY_SLOT (NIA + offset);
 737     }
 738 }
 739
 740
 741
 742 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 743 "bgezal r<RS>, <OFFSET>"
 744 *mipsI:
 745 *mipsII:
 746 *mipsIII:
 747 *mipsIV:
 748 *mipsV:
 749 *mips32:
 750 *mips32r2:
 751 *mips64:
 752 *mips64r2:
 753 *vr4100:
 754 *vr5000:
 755 *r3900:
 756 {
 757   address_word offset = EXTEND16 (OFFSET) << 2;
 758   if (RS == 31)
 759     Unpredictable ();
 760   RA = (CIA + 8);
 761   if ((signed_word) GPR[RS] >= 0)
 762     {
 763       DELAY_SLOT (NIA + offset);
 764     }
 765 }
 766
 767
 768
 769 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 770 "bgezall r<RS>, <OFFSET>"
 771 *mipsII:
 772 *mipsIII:
 773 *mipsIV:
 774 *mipsV:
 775 *mips32:
 776 *mips32r2:
 777 *mips64:
 778 *mips64r2:
 779 *vr4100:
 780 *vr5000:
 781 *r3900:
 782 {
 783   address_word offset = EXTEND16 (OFFSET) << 2;
 784   if (RS == 31)
 785     Unpredictable ();
 786   RA = (CIA + 8);
 787   /* NOTE: The branch occurs AFTER the next instruction has been
 788      executed */
 789   if ((signed_word) GPR[RS] >= 0)
 790     {
 791       DELAY_SLOT (NIA + offset);
 792     }
 793   else
 794     NULLIFY_NEXT_INSTRUCTION ();
 795 }
 796
 797
 798
 799 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 800 "bgezl r<RS>, <OFFSET>"
 801 *mipsII:
 802 *mipsIII:
 803 *mipsIV:
 804 *mipsV:
 805 *mips32:
 806 *mips32r2:
 807 *mips64:
 808 *mips64r2:
 809 *vr4100:
 810 *vr5000:
 811 *r3900:
 812 {
 813   address_word offset = EXTEND16 (OFFSET) << 2;
 814   if ((signed_word) GPR[RS] >= 0)
 815     {
 816       DELAY_SLOT (NIA + offset);
 817     }
 818   else
 819     NULLIFY_NEXT_INSTRUCTION ();
 820 }
 821
 822
 823
 824 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 825 "bgtz r<RS>, <OFFSET>"
 826 *mipsI:
 827 *mipsII:
 828 *mipsIII:
 829 *mipsIV:
 830 *mipsV:
 831 *mips32:
 832 *mips32r2:
 833 *mips64:
 834 *mips64r2:
 835 *vr4100:
 836 *vr5000:
 837 *r3900:
 838 {
 839   address_word offset = EXTEND16 (OFFSET) << 2;
 840   if ((signed_word) GPR[RS] > 0)
 841     {
 842       DELAY_SLOT (NIA + offset);
 843     }
 844 }
 845
 846
 847
 848 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 849 "bgtzl r<RS>, <OFFSET>"
 850 *mipsII:
 851 *mipsIII:
 852 *mipsIV:
 853 *mipsV:
 854 *mips32:
 855 *mips32r2:
 856 *mips64:
 857 *mips64r2:
 858 *vr4100:
 859 *vr5000:
 860 *r3900:
 861 {
 862   address_word offset = EXTEND16 (OFFSET) << 2;
 863   /* NOTE: The branch occurs AFTER the next instruction has been
 864      executed */
 865   if ((signed_word) GPR[RS] > 0)
 866     {
 867       DELAY_SLOT (NIA + offset);
 868     }
 869   else
 870     NULLIFY_NEXT_INSTRUCTION ();
 871 }
 872
 873
 874
 875 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 876 "blez r<RS>, <OFFSET>"
 877 *mipsI:
 878 *mipsII:
 879 *mipsIII:
 880 *mipsIV:
 881 *mipsV:
 882 *mips32:
 883 *mips32r2:
 884 *mips64:
 885 *mips64r2:
 886 *vr4100:
 887 *vr5000:
 888 *r3900:
 889 {
 890   address_word offset = EXTEND16 (OFFSET) << 2;
 891   /* NOTE: The branch occurs AFTER the next instruction has been
 892      executed */
 893   if ((signed_word) GPR[RS] <= 0)
 894     {
 895       DELAY_SLOT (NIA + offset);
 896     }
 897 }
 898
 899
 900
 901 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 902 "bgezl r<RS>, <OFFSET>"
 903 *mipsII:
 904 *mipsIII:
 905 *mipsIV:
 906 *mipsV:
 907 *mips32:
 908 *mips32r2:
 909 *mips64:
 910 *mips64r2:
 911 *vr4100:
 912 *vr5000:
 913 *r3900:
 914 {
 915   address_word offset = EXTEND16 (OFFSET) << 2;
 916   if ((signed_word) GPR[RS] <= 0)
 917     {
 918       DELAY_SLOT (NIA + offset);
 919     }
 920   else
 921     NULLIFY_NEXT_INSTRUCTION ();
 922 }
 923
 924
 925
 926 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 927 "bltz r<RS>, <OFFSET>"
 928 *mipsI:
 929 *mipsII:
 930 *mipsIII:
 931 *mipsIV:
 932 *mipsV:
 933 *mips32:
 934 *mips32r2:
 935 *mips64:
 936 *mips64r2:
 937 *vr4100:
 938 *vr5000:
 939 *r3900:
 940 {
 941   address_word offset = EXTEND16 (OFFSET) << 2;
 942   if ((signed_word) GPR[RS] < 0)
 943     {
 944       DELAY_SLOT (NIA + offset);
 945     }
 946 }
 947
 948
 949
 950 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 951 "bltzal r<RS>, <OFFSET>"
 952 *mipsI:
 953 *mipsII:
 954 *mipsIII:
 955 *mipsIV:
 956 *mipsV:
 957 *mips32:
 958 *mips32r2:
 959 *mips64:
 960 *mips64r2:
 961 *vr4100:
 962 *vr5000:
 963 *r3900:
 964 {
 965   address_word offset = EXTEND16 (OFFSET) << 2;
 966   if (RS == 31)
 967     Unpredictable ();
 968   RA = (CIA + 8);
 969   /* NOTE: The branch occurs AFTER the next instruction has been
 970      executed */
 971   if ((signed_word) GPR[RS] < 0)
 972     {
 973       DELAY_SLOT (NIA + offset);
 974     }
 975 }
 976
 977
 978
 979 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 980 "bltzall r<RS>, <OFFSET>"
 981 *mipsII:
 982 *mipsIII:
 983 *mipsIV:
 984 *mipsV:
 985 *mips32:
 986 *mips32r2:
 987 *mips64:
 988 *mips64r2:
 989 *vr4100:
 990 *vr5000:
 991 *r3900:
 992 {
 993   address_word offset = EXTEND16 (OFFSET) << 2;
 994   if (RS == 31)
 995     Unpredictable ();
 996   RA = (CIA + 8);
 997   if ((signed_word) GPR[RS] < 0)
 998     {
 999       DELAY_SLOT (NIA + offset);
1000     }
1001   else
1002     NULLIFY_NEXT_INSTRUCTION ();
1003 }
1004
1005
1006
1007 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1008 "bltzl r<RS>, <OFFSET>"
1009 *mipsII:
1010 *mipsIII:
1011 *mipsIV:
1012 *mipsV:
1013 *mips32:
1014 *mips32r2:
1015 *mips64:
1016 *mips64r2:
1017 *vr4100:
1018 *vr5000:
1019 *r3900:
1020 {
1021   address_word offset = EXTEND16 (OFFSET) << 2;
1022   /* NOTE: The branch occurs AFTER the next instruction has been
1023      executed */
1024   if ((signed_word) GPR[RS] < 0)
1025     {
1026       DELAY_SLOT (NIA + offset);
1027     }
1028   else
1029     NULLIFY_NEXT_INSTRUCTION ();
1030 }
1031
1032
1033
1034 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1035 "bne r<RS>, r<RT>, <OFFSET>"
1036 *mipsI:
1037 *mipsII:
1038 *mipsIII:
1039 *mipsIV:
1040 *mipsV:
1041 *mips32:
1042 *mips32r2:
1043 *mips64:
1044 *mips64r2:
1045 *vr4100:
1046 *vr5000:
1047 *r3900:
1048 {
1049   address_word offset = EXTEND16 (OFFSET) << 2;
1050   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1051     {
1052       DELAY_SLOT (NIA + offset);
1053     }
1054 }
1055
1056
1057
1058 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1059 "bnel r<RS>, r<RT>, <OFFSET>"
1060 *mipsII:
1061 *mipsIII:
1062 *mipsIV:
1063 *mipsV:
1064 *mips32:
1065 *mips32r2:
1066 *mips64:
1067 *mips64r2:
1068 *vr4100:
1069 *vr5000:
1070 *r3900:
1071 {
1072   address_word offset = EXTEND16 (OFFSET) << 2;
1073   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1074     {
1075       DELAY_SLOT (NIA + offset);
1076     }
1077   else
1078     NULLIFY_NEXT_INSTRUCTION ();
1079 }
1080
1081
1082
1083 000000,20.CODE,001101:SPECIAL:32::BREAK
1084 "break %#lx<CODE>"
1085 *mipsI:
1086 *mipsII:
1087 *mipsIII:
1088 *mipsIV:
1089 *mipsV:
1090 *mips32:
1091 *mips32r2:
1092 *mips64:
1093 *mips64r2:
1094 *vr4100:
1095 *vr5000:
1096 *r3900:
1097 {
1098   /* Check for some break instruction which are reserved for use by the simulator.  */
1099   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1100   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1101       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1102     {
1103       sim_engine_halt (SD, CPU, NULL, cia,
1104                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1105     }
1106   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1107            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1108     {
1109       if (STATE & simDELAYSLOT)
1110         PC = cia - 4; /* reference the branch instruction */
1111       else
1112         PC = cia;
1113       SignalException (BreakPoint, instruction_0);
1114     }
1115
1116   else
1117     {
1118       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1119          the exception. */
1120       SignalException (BreakPoint, instruction_0);
1121     }
1122 }
1123
1124
1125
1126 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1127 "clo r<RD>, r<RS>"
1128 *mips32:
1129 *mips32r2:
1130 *mips64:
1131 *mips64r2:
1132 *vr5500:
1133 {
1134   unsigned32 temp = GPR[RS];
1135   unsigned32 i, mask;
1136   if (RT != RD)
1137     Unpredictable ();
1138   if (NotWordValue (GPR[RS]))
1139     Unpredictable ();
1140   TRACE_ALU_INPUT1 (GPR[RS]);
1141   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1142     {
1143       if ((temp & mask) == 0)
1144         break;
1145       mask >>= 1;
1146     }
1147   GPR[RD] = EXTEND32 (i);
1148   TRACE_ALU_RESULT (GPR[RD]);
1149 }
1150
1151
1152
1153 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1154 "clz r<RD>, r<RS>"
1155 *mips32:
1156 *mips32r2:
1157 *mips64:
1158 *mips64r2:
1159 *vr5500:
1160 {
1161   unsigned32 temp = GPR[RS];
1162   unsigned32 i, mask;
1163   if (RT != RD)
1164     Unpredictable ();
1165   if (NotWordValue (GPR[RS]))
1166     Unpredictable ();
1167   TRACE_ALU_INPUT1 (GPR[RS]);
1168   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1169     {
1170       if ((temp & mask) != 0)
1171         break;
1172       mask >>= 1;
1173     }
1174   GPR[RD] = EXTEND32 (i);
1175   TRACE_ALU_RESULT (GPR[RD]);
1176 }
1177
1178
1179
1180 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1181 "dadd r<RD>, r<RS>, r<RT>"
1182 *mipsIII:
1183 *mipsIV:
1184 *mipsV:
1185 *mips64:
1186 *mips64r2:
1187 *vr4100:
1188 *vr5000:
1189 {
1190   check_u64 (SD_, instruction_0);
1191   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1192   {
1193     ALU64_BEGIN (GPR[RS]);
1194     ALU64_ADD (GPR[RT]);
1195     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1196   }
1197   TRACE_ALU_RESULT (GPR[RD]);
1198 }
1199
1200
1201
1202 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1203 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1204 *mipsIII:
1205 *mipsIV:
1206 *mipsV:
1207 *mips64:
1208 *mips64r2:
1209 *vr4100:
1210 *vr5000:
1211 {
1212   check_u64 (SD_, instruction_0);
1213   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1214   {
1215     ALU64_BEGIN (GPR[RS]);
1216     ALU64_ADD (EXTEND16 (IMMEDIATE));
1217     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1218   }
1219   TRACE_ALU_RESULT (GPR[RT]);
1220 }
1221
1222
1223
1224 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1225 {
1226   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1227   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1228   TRACE_ALU_RESULT (GPR[rt]);
1229 }
1230
1231 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1232 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1233 *mipsIII:
1234 *mipsIV:
1235 *mipsV:
1236 *mips64:
1237 *mips64r2:
1238 *vr4100:
1239 *vr5000:
1240 {
1241   check_u64 (SD_, instruction_0);
1242   do_daddiu (SD_, RS, RT, IMMEDIATE);
1243 }
1244
1245
1246
1247 :function:::void:do_daddu:int rs, int rt, int rd
1248 {
1249   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1250   GPR[rd] = GPR[rs] + GPR[rt];
1251   TRACE_ALU_RESULT (GPR[rd]);
1252 }
1253
1254 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1255 "daddu r<RD>, r<RS>, r<RT>"
1256 *mipsIII:
1257 *mipsIV:
1258 *mipsV:
1259 *mips64:
1260 *mips64r2:
1261 *vr4100:
1262 *vr5000:
1263 {
1264   check_u64 (SD_, instruction_0);
1265   do_daddu (SD_, RS, RT, RD);
1266 }
1267
1268
1269
1270 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1271 "dclo r<RD>, r<RS>"
1272 *mips64:
1273 *mips64r2:
1274 *vr5500:
1275 {
1276   unsigned64 temp = GPR[RS];
1277   unsigned32 i;
1278   unsigned64 mask;
1279   check_u64 (SD_, instruction_0);
1280   if (RT != RD)
1281     Unpredictable ();
1282   TRACE_ALU_INPUT1 (GPR[RS]);
1283   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1284     {
1285       if ((temp & mask) == 0)
1286         break;
1287       mask >>= 1;
1288     }
1289   GPR[RD] = EXTEND32 (i);
1290   TRACE_ALU_RESULT (GPR[RD]);
1291 }
1292
1293
1294
1295 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1296 "dclz r<RD>, r<RS>"
1297 *mips64:
1298 *mips64r2:
1299 *vr5500:
1300 {
1301   unsigned64 temp = GPR[RS];
1302   unsigned32 i;
1303   unsigned64 mask;
1304   check_u64 (SD_, instruction_0);
1305   if (RT != RD)
1306     Unpredictable ();
1307   TRACE_ALU_INPUT1 (GPR[RS]);
1308   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1309     {
1310       if ((temp & mask) != 0)
1311         break;
1312       mask >>= 1;
1313     }
1314   GPR[RD] = EXTEND32 (i);
1315   TRACE_ALU_RESULT (GPR[RD]);
1316 }
1317
1318
1319
1320 :function:::void:do_ddiv:int rs, int rt
1321 {
1322   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1323   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1324   {
1325     signed64 n = GPR[rs];
1326     signed64 d = GPR[rt];
1327     signed64 hi;
1328     signed64 lo;
1329     if (d == 0)
1330       {
1331         lo = SIGNED64 (0x8000000000000000);
1332         hi = 0;
1333       }
1334     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1335       {
1336         lo = SIGNED64 (0x8000000000000000);
1337         hi = 0;
1338       }
1339     else
1340       {
1341         lo = (n / d);
1342         hi = (n % d);
1343       }
1344     HI = hi;
1345     LO = lo;
1346   }
1347   TRACE_ALU_RESULT2 (HI, LO);
1348 }
1349
1350 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1351 "ddiv r<RS>, r<RT>"
1352 *mipsIII:
1353 *mipsIV:
1354 *mipsV:
1355 *mips64:
1356 *mips64r2:
1357 *vr4100:
1358 *vr5000:
1359 {
1360   check_u64 (SD_, instruction_0);
1361   do_ddiv (SD_, RS, RT);
1362 }
1363
1364
1365
1366 :function:::void:do_ddivu:int rs, int rt
1367 {
1368   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1369   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1370   {
1371     unsigned64 n = GPR[rs];
1372     unsigned64 d = GPR[rt];
1373     unsigned64 hi;
1374     unsigned64 lo;
1375     if (d == 0)
1376       {
1377         lo = SIGNED64 (0x8000000000000000);
1378         hi = 0;
1379       }
1380     else
1381       {
1382         lo = (n / d);
1383         hi = (n % d);
1384       }
1385     HI = hi;
1386     LO = lo;
1387   }
1388   TRACE_ALU_RESULT2 (HI, LO);
1389 }
1390
1391 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1392 "ddivu r<RS>, r<RT>"
1393 *mipsIII:
1394 *mipsIV:
1395 *mipsV:
1396 *mips64:
1397 *mips64r2:
1398 *vr4100:
1399 *vr5000:
1400 {
1401   check_u64 (SD_, instruction_0);
1402   do_ddivu (SD_, RS, RT);
1403 }
1404
1405 :function:::void:do_div:int rs, int rt
1406 {
1407   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1408   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1409   {
1410     signed32 n = GPR[rs];
1411     signed32 d = GPR[rt];
1412     if (d == 0)
1413       {
1414         LO = EXTEND32 (0x80000000);
1415         HI = EXTEND32 (0);
1416       }
1417     else if (n == SIGNED32 (0x80000000) && d == -1)
1418       {
1419         LO = EXTEND32 (0x80000000);
1420         HI = EXTEND32 (0);
1421       }
1422     else
1423       {
1424         LO = EXTEND32 (n / d);
1425         HI = EXTEND32 (n % d);
1426       }
1427   }
1428   TRACE_ALU_RESULT2 (HI, LO);
1429 }
1430
1431 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1432 "div r<RS>, r<RT>"
1433 *mipsI:
1434 *mipsII:
1435 *mipsIII:
1436 *mipsIV:
1437 *mipsV:
1438 *mips32:
1439 *mips32r2:
1440 *mips64:
1441 *mips64r2:
1442 *vr4100:
1443 *vr5000:
1444 *r3900:
1445 {
1446   do_div (SD_, RS, RT);
1447 }
1448
1449
1450
1451 :function:::void:do_divu:int rs, int rt
1452 {
1453   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1454   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1455   {
1456     unsigned32 n = GPR[rs];
1457     unsigned32 d = GPR[rt];
1458     if (d == 0)
1459       {
1460         LO = EXTEND32 (0x80000000);
1461         HI = EXTEND32 (0);
1462       }
1463     else
1464       {
1465         LO = EXTEND32 (n / d);
1466         HI = EXTEND32 (n % d);
1467       }
1468   }
1469   TRACE_ALU_RESULT2 (HI, LO);
1470 }
1471
1472 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1473 "divu r<RS>, r<RT>"
1474 *mipsI:
1475 *mipsII:
1476 *mipsIII:
1477 *mipsIV:
1478 *mipsV:
1479 *mips32:
1480 *mips32r2:
1481 *mips64:
1482 *mips64r2:
1483 *vr4100:
1484 *vr5000:
1485 *r3900:
1486 {
1487   do_divu (SD_, RS, RT);
1488 }
1489
1490
1491 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1492 {
1493   unsigned64 lo;
1494   unsigned64 hi;
1495   unsigned64 m00;
1496   unsigned64 m01;
1497   unsigned64 m10;
1498   unsigned64 m11;
1499   unsigned64 mid;
1500   int sign;
1501   unsigned64 op1 = GPR[rs];
1502   unsigned64 op2 = GPR[rt];
1503   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1504   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1505   /* make signed multiply unsigned */
1506   sign = 0;
1507   if (signed_p)
1508     {
1509       if ((signed64) op1 < 0)
1510         {
1511           op1 = - op1;
1512           ++sign;
1513         }
1514       if ((signed64) op2 < 0)
1515         {
1516           op2 = - op2;
1517           ++sign;
1518         }
1519     }
1520   /* multiply out the 4 sub products */
1521   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1522   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1523   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1524   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1525   /* add the products */
1526   mid = ((unsigned64) VH4_8 (m00)
1527          + (unsigned64) VL4_8 (m10)
1528          + (unsigned64) VL4_8 (m01));
1529   lo = U8_4 (mid, m00);
1530   hi = (m11
1531         + (unsigned64) VH4_8 (mid)
1532         + (unsigned64) VH4_8 (m01)
1533         + (unsigned64) VH4_8 (m10));
1534   /* fix the sign */
1535   if (sign & 1)
1536     {
1537       lo = -lo;
1538       if (lo == 0)
1539         hi = -hi;
1540       else
1541         hi = -hi - 1;
1542     }
1543   /* save the result HI/LO (and a gpr) */
1544   LO = lo;
1545   HI = hi;
1546   if (rd != 0)
1547     GPR[rd] = lo;
1548   TRACE_ALU_RESULT2 (HI, LO);
1549 }
1550
1551 :function:::void:do_dmult:int rs, int rt, int rd
1552 {
1553   do_dmultx (SD_, rs, rt, rd, 1);
1554 }
1555
1556 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1557 "dmult r<RS>, r<RT>"
1558 *mipsIII:
1559 *mipsIV:
1560 *mipsV:
1561 *mips64:
1562 *mips64r2:
1563 *vr4100:
1564 {
1565   check_u64 (SD_, instruction_0);
1566   do_dmult (SD_, RS, RT, 0);
1567 }
1568
1569 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1570 "dmult r<RS>, r<RT>":RD == 0
1571 "dmult r<RD>, r<RS>, r<RT>"
1572 *vr5000:
1573 {
1574   check_u64 (SD_, instruction_0);
1575   do_dmult (SD_, RS, RT, RD);
1576 }
1577
1578
1579
1580 :function:::void:do_dmultu:int rs, int rt, int rd
1581 {
1582   do_dmultx (SD_, rs, rt, rd, 0);
1583 }
1584
1585 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1586 "dmultu r<RS>, r<RT>"
1587 *mipsIII:
1588 *mipsIV:
1589 *mipsV:
1590 *mips64:
1591 *mips64r2:
1592 *vr4100:
1593 {
1594   check_u64 (SD_, instruction_0);
1595   do_dmultu (SD_, RS, RT, 0);
1596 }
1597
1598 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1599 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1600 "dmultu r<RS>, r<RT>"
1601 *vr5000:
1602 {
1603   check_u64 (SD_, instruction_0);
1604   do_dmultu (SD_, RS, RT, RD);
1605 }
1606
1607
1608 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1609 {
1610   unsigned64 result;
1611
1612   y &= 63;
1613   TRACE_ALU_INPUT2 (x, y);
1614   result = ROTR64 (x, y);
1615   TRACE_ALU_RESULT (result);
1616   return result;
1617 }
1618
1619 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1620 "dror r<RD>, r<RT>, <SHIFT>"
1621 *mips64r2:
1622 *vr5400:
1623 *vr5500:
1624 {
1625   check_u64 (SD_, instruction_0);
1626   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1627 }
1628
1629 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1630 "dror32 r<RD>, r<RT>, <SHIFT>"
1631 *mips64r2:
1632 *vr5400:
1633 *vr5500:
1634 {
1635   check_u64 (SD_, instruction_0);
1636   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1637 }
1638
1639 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1640 "drorv r<RD>, r<RT>, r<RS>"
1641 *mips64r2:
1642 *vr5400:
1643 *vr5500:
1644 {
1645   check_u64 (SD_, instruction_0);
1646   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1647 }
1648
1649
1650 :function:::void:do_dsll:int rt, int rd, int shift
1651 {
1652   TRACE_ALU_INPUT2 (GPR[rt], shift);
1653   GPR[rd] = GPR[rt] << shift;
1654   TRACE_ALU_RESULT (GPR[rd]);
1655 }
1656
1657 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1658 "dsll r<RD>, r<RT>, <SHIFT>"
1659 *mipsIII:
1660 *mipsIV:
1661 *mipsV:
1662 *mips64:
1663 *mips64r2:
1664 *vr4100:
1665 *vr5000:
1666 {
1667   check_u64 (SD_, instruction_0);
1668   do_dsll (SD_, RT, RD, SHIFT);
1669 }
1670
1671
1672 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1673 "dsll32 r<RD>, r<RT>, <SHIFT>"
1674 *mipsIII:
1675 *mipsIV:
1676 *mipsV:
1677 *mips64:
1678 *mips64r2:
1679 *vr4100:
1680 *vr5000:
1681 {
1682   int s = 32 + SHIFT;
1683   check_u64 (SD_, instruction_0);
1684   TRACE_ALU_INPUT2 (GPR[RT], s);
1685   GPR[RD] = GPR[RT] << s;
1686   TRACE_ALU_RESULT (GPR[RD]);
1687 }
1688
1689 :function:::void:do_dsllv:int rs, int rt, int rd
1690 {
1691   int s = MASKED64 (GPR[rs], 5, 0);
1692   TRACE_ALU_INPUT2 (GPR[rt], s);
1693   GPR[rd] = GPR[rt] << s;
1694   TRACE_ALU_RESULT (GPR[rd]);
1695 }
1696
1697 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1698 "dsllv r<RD>, r<RT>, r<RS>"
1699 *mipsIII:
1700 *mipsIV:
1701 *mipsV:
1702 *mips64:
1703 *mips64r2:
1704 *vr4100:
1705 *vr5000:
1706 {
1707   check_u64 (SD_, instruction_0);
1708   do_dsllv (SD_, RS, RT, RD);
1709 }
1710
1711 :function:::void:do_dsra:int rt, int rd, int shift
1712 {
1713   TRACE_ALU_INPUT2 (GPR[rt], shift);
1714   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1715   TRACE_ALU_RESULT (GPR[rd]);
1716 }
1717
1718
1719 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1720 "dsra r<RD>, r<RT>, <SHIFT>"
1721 *mipsIII:
1722 *mipsIV:
1723 *mipsV:
1724 *mips64:
1725 *mips64r2:
1726 *vr4100:
1727 *vr5000:
1728 {
1729   check_u64 (SD_, instruction_0);
1730   do_dsra (SD_, RT, RD, SHIFT);
1731 }
1732
1733
1734 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1735 "dsra32 r<RD>, r<RT>, <SHIFT>"
1736 *mipsIII:
1737 *mipsIV:
1738 *mipsV:
1739 *mips64:
1740 *mips64r2:
1741 *vr4100:
1742 *vr5000:
1743 {
1744   int s = 32 + SHIFT;
1745   check_u64 (SD_, instruction_0);
1746   TRACE_ALU_INPUT2 (GPR[RT], s);
1747   GPR[RD] = ((signed64) GPR[RT]) >> s;
1748   TRACE_ALU_RESULT (GPR[RD]);
1749 }
1750
1751
1752 :function:::void:do_dsrav:int rs, int rt, int rd
1753 {
1754   int s = MASKED64 (GPR[rs], 5, 0);
1755   TRACE_ALU_INPUT2 (GPR[rt], s);
1756   GPR[rd] = ((signed64) GPR[rt]) >> s;
1757   TRACE_ALU_RESULT (GPR[rd]);
1758 }
1759
1760 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1761 "dsrav r<RD>, r<RT>, r<RS>"
1762 *mipsIII:
1763 *mipsIV:
1764 *mipsV:
1765 *mips64:
1766 *mips64r2:
1767 *vr4100:
1768 *vr5000:
1769 {
1770   check_u64 (SD_, instruction_0);
1771   do_dsrav (SD_, RS, RT, RD);
1772 }
1773
1774 :function:::void:do_dsrl:int rt, int rd, int shift
1775 {
1776   TRACE_ALU_INPUT2 (GPR[rt], shift);
1777   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1778   TRACE_ALU_RESULT (GPR[rd]);
1779 }
1780
1781
1782 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1783 "dsrl r<RD>, r<RT>, <SHIFT>"
1784 *mipsIII:
1785 *mipsIV:
1786 *mipsV:
1787 *mips64:
1788 *mips64r2:
1789 *vr4100:
1790 *vr5000:
1791 {
1792   check_u64 (SD_, instruction_0);
1793   do_dsrl (SD_, RT, RD, SHIFT);
1794 }
1795
1796
1797 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1798 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1799 *mipsIII:
1800 *mipsIV:
1801 *mipsV:
1802 *mips64:
1803 *mips64r2:
1804 *vr4100:
1805 *vr5000:
1806 {
1807   int s = 32 + SHIFT;
1808   check_u64 (SD_, instruction_0);
1809   TRACE_ALU_INPUT2 (GPR[RT], s);
1810   GPR[RD] = (unsigned64) GPR[RT] >> s;
1811   TRACE_ALU_RESULT (GPR[RD]);
1812 }
1813
1814
1815 :function:::void:do_dsrlv:int rs, int rt, int rd
1816 {
1817   int s = MASKED64 (GPR[rs], 5, 0);
1818   TRACE_ALU_INPUT2 (GPR[rt], s);
1819   GPR[rd] = (unsigned64) GPR[rt] >> s;
1820   TRACE_ALU_RESULT (GPR[rd]);
1821 }
1822
1823
1824
1825 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1826 "dsrlv r<RD>, r<RT>, r<RS>"
1827 *mipsIII:
1828 *mipsIV:
1829 *mipsV:
1830 *mips64:
1831 *mips64r2:
1832 *vr4100:
1833 *vr5000:
1834 {
1835   check_u64 (SD_, instruction_0);
1836   do_dsrlv (SD_, RS, RT, RD);
1837 }
1838
1839
1840 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1841 "dsub r<RD>, r<RS>, r<RT>"
1842 *mipsIII:
1843 *mipsIV:
1844 *mipsV:
1845 *mips64:
1846 *mips64r2:
1847 *vr4100:
1848 *vr5000:
1849 {
1850   check_u64 (SD_, instruction_0);
1851   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1852   {
1853     ALU64_BEGIN (GPR[RS]);
1854     ALU64_SUB (GPR[RT]);
1855     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1856   }
1857   TRACE_ALU_RESULT (GPR[RD]);
1858 }
1859
1860
1861 :function:::void:do_dsubu:int rs, int rt, int rd
1862 {
1863   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1864   GPR[rd] = GPR[rs] - GPR[rt];
1865   TRACE_ALU_RESULT (GPR[rd]);
1866 }
1867
1868 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1869 "dsubu r<RD>, r<RS>, r<RT>"
1870 *mipsIII:
1871 *mipsIV:
1872 *mipsV:
1873 *mips64:
1874 *mips64r2:
1875 *vr4100:
1876 *vr5000:
1877 {
1878   check_u64 (SD_, instruction_0);
1879   do_dsubu (SD_, RS, RT, RD);
1880 }
1881
1882
1883 000010,26.INSTR_INDEX:NORMAL:32::J
1884 "j <INSTR_INDEX>"
1885 *mipsI:
1886 *mipsII:
1887 *mipsIII:
1888 *mipsIV:
1889 *mipsV:
1890 *mips32:
1891 *mips32r2:
1892 *mips64:
1893 *mips64r2:
1894 *vr4100:
1895 *vr5000:
1896 *r3900:
1897 {
1898   /* NOTE: The region used is that of the delay slot NIA and NOT the
1899      current instruction */
1900   address_word region = (NIA & MASK (63, 28));
1901   DELAY_SLOT (region | (INSTR_INDEX << 2));
1902 }
1903
1904
1905 000011,26.INSTR_INDEX:NORMAL:32::JAL
1906 "jal <INSTR_INDEX>"
1907 *mipsI:
1908 *mipsII:
1909 *mipsIII:
1910 *mipsIV:
1911 *mipsV:
1912 *mips32:
1913 *mips32r2:
1914 *mips64:
1915 *mips64r2:
1916 *vr4100:
1917 *vr5000:
1918 *r3900:
1919 {
1920   /* NOTE: The region used is that of the delay slot and NOT the
1921      current instruction */
1922   address_word region = (NIA & MASK (63, 28));
1923   GPR[31] = CIA + 8;
1924   DELAY_SLOT (region | (INSTR_INDEX << 2));
1925 }
1926
1927 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1928 "jalr r<RS>":RD == 31
1929 "jalr r<RD>, r<RS>"
1930 *mipsI:
1931 *mipsII:
1932 *mipsIII:
1933 *mipsIV:
1934 *mipsV:
1935 *mips32:
1936 *mips32r2:
1937 *mips64:
1938 *mips64r2:
1939 *vr4100:
1940 *vr5000:
1941 *r3900:
1942 {
1943   address_word temp = GPR[RS];
1944   GPR[RD] = CIA + 8;
1945   DELAY_SLOT (temp);
1946 }
1947
1948
1949 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1950 "jr r<RS>"
1951 *mipsI:
1952 *mipsII:
1953 *mipsIII:
1954 *mipsIV:
1955 *mipsV:
1956 *mips32:
1957 *mips32r2:
1958 *mips64:
1959 *mips64r2:
1960 *vr4100:
1961 *vr5000:
1962 *r3900:
1963 {
1964   DELAY_SLOT (GPR[RS]);
1965 }
1966
1967
1968 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1969 {
1970   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1971   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1972   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1973   unsigned int byte;
1974   address_word paddr;
1975   int uncached;
1976   unsigned64 memval;
1977   address_word vaddr;
1978
1979   vaddr = loadstore_ea (SD_, base, offset);
1980   if ((vaddr & access) != 0)
1981     {
1982       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1983     }
1984   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1985   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1986   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1987   byte = ((vaddr & mask) ^ bigendiancpu);
1988   return (memval >> (8 * byte));
1989 }
1990
1991 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1992 {
1993   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1994   address_word reverseendian = (ReverseEndian ? -1 : 0);
1995   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1996   unsigned int byte;
1997   unsigned int word;
1998   address_word paddr;
1999   int uncached;
2000   unsigned64 memval;
2001   address_word vaddr;
2002   int nr_lhs_bits;
2003   int nr_rhs_bits;
2004   unsigned_word lhs_mask;
2005   unsigned_word temp;
2006
2007   vaddr = loadstore_ea (SD_, base, offset);
2008   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2009   paddr = (paddr ^ (reverseendian & mask));
2010   if (BigEndianMem == 0)
2011     paddr = paddr & ~access;
2012
2013   /* compute where within the word/mem we are */
2014   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2015   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2016   nr_lhs_bits = 8 * byte + 8;
2017   nr_rhs_bits = 8 * access - 8 * byte;
2018   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2019
2020   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2021            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2022            (long) ((unsigned64) paddr >> 32), (long) paddr,
2023            word, byte, nr_lhs_bits, nr_rhs_bits); */
2024
2025   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2026   if (word == 0)
2027     {
2028       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2029       temp = (memval << nr_rhs_bits);
2030     }
2031   else
2032     {
2033       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2034       temp = (memval >> nr_lhs_bits);
2035     }
2036   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2037   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2038
2039   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2040            (long) ((unsigned64) memval >> 32), (long) memval,
2041            (long) ((unsigned64) temp >> 32), (long) temp,
2042            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2043            (long) (rt >> 32), (long) rt); */
2044   return rt;
2045 }
2046
2047 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2048 {
2049   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2050   address_word reverseendian = (ReverseEndian ? -1 : 0);
2051   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2052   unsigned int byte;
2053   address_word paddr;
2054   int uncached;
2055   unsigned64 memval;
2056   address_word vaddr;
2057
2058   vaddr = loadstore_ea (SD_, base, offset);
2059   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2060   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2061   paddr = (paddr ^ (reverseendian & mask));
2062   if (BigEndianMem != 0)
2063     paddr = paddr & ~access;
2064   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2065   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2066   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2067   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2068      (long) paddr, byte, (long) paddr, (long) memval); */
2069   {
2070     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2071     rt &= ~screen;
2072     rt |= (memval >> (8 * byte)) & screen;
2073   }
2074   return rt;
2075 }
2076
2077
2078 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2079 "lb r<RT>, <OFFSET>(r<BASE>)"
2080 *mipsI:
2081 *mipsII:
2082 *mipsIII:
2083 *mipsIV:
2084 *mipsV:
2085 *mips32:
2086 *mips32r2:
2087 *mips64:
2088 *mips64r2:
2089 *vr4100:
2090 *vr5000:
2091 *r3900:
2092 {
2093   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2094 }
2095
2096
2097 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2098 "lbu r<RT>, <OFFSET>(r<BASE>)"
2099 *mipsI:
2100 *mipsII:
2101 *mipsIII:
2102 *mipsIV:
2103 *mipsV:
2104 *mips32:
2105 *mips32r2:
2106 *mips64:
2107 *mips64r2:
2108 *vr4100:
2109 *vr5000:
2110 *r3900:
2111 {
2112   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2113 }
2114
2115
2116 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2117 "ld r<RT>, <OFFSET>(r<BASE>)"
2118 *mipsIII:
2119 *mipsIV:
2120 *mipsV:
2121 *mips64:
2122 *mips64r2:
2123 *vr4100:
2124 *vr5000:
2125 {
2126   check_u64 (SD_, instruction_0);
2127   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2128 }
2129
2130
2131 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2132 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2133 *mipsII:
2134 *mipsIII:
2135 *mipsIV:
2136 *mipsV:
2137 *mips32:
2138 *mips32r2:
2139 *mips64:
2140 *mips64r2:
2141 *vr4100:
2142 *vr5000:
2143 *r3900:
2144 {
2145   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2146 }
2147
2148
2149
2150
2151 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2152 "ldl r<RT>, <OFFSET>(r<BASE>)"
2153 *mipsIII:
2154 *mipsIV:
2155 *mipsV:
2156 *mips64:
2157 *mips64r2:
2158 *vr4100:
2159 *vr5000:
2160 {
2161   check_u64 (SD_, instruction_0);
2162   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2163 }
2164
2165
2166 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2167 "ldr r<RT>, <OFFSET>(r<BASE>)"
2168 *mipsIII:
2169 *mipsIV:
2170 *mipsV:
2171 *mips64:
2172 *mips64r2:
2173 *vr4100:
2174 *vr5000:
2175 {
2176   check_u64 (SD_, instruction_0);
2177   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2178 }
2179
2180
2181 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2182 "lh r<RT>, <OFFSET>(r<BASE>)"
2183 *mipsI:
2184 *mipsII:
2185 *mipsIII:
2186 *mipsIV:
2187 *mipsV:
2188 *mips32:
2189 *mips32r2:
2190 *mips64:
2191 *mips64r2:
2192 *vr4100:
2193 *vr5000:
2194 *r3900:
2195 {
2196   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2197 }
2198
2199
2200 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2201 "lhu r<RT>, <OFFSET>(r<BASE>)"
2202 *mipsI:
2203 *mipsII:
2204 *mipsIII:
2205 *mipsIV:
2206 *mipsV:
2207 *mips32:
2208 *mips32r2:
2209 *mips64:
2210 *mips64r2:
2211 *vr4100:
2212 *vr5000:
2213 *r3900:
2214 {
2215   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2216 }
2217
2218
2219 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2220 "ll r<RT>, <OFFSET>(r<BASE>)"
2221 *mipsII:
2222 *mipsIII:
2223 *mipsIV:
2224 *mipsV:
2225 *mips32:
2226 *mips32r2:
2227 *mips64:
2228 *mips64r2:
2229 *vr4100:
2230 *vr5000:
2231 {
2232   address_word base = GPR[BASE];
2233   address_word offset = EXTEND16 (OFFSET);
2234   {
2235     address_word vaddr = loadstore_ea (SD_, base, offset);
2236     address_word paddr;
2237     int uncached;
2238     if ((vaddr & 3) != 0)
2239       {
2240         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2241       }
2242     else
2243       {
2244         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2245           {
2246             unsigned64 memval = 0;
2247             unsigned64 memval1 = 0;
2248             unsigned64 mask = 0x7;
2249             unsigned int shift = 2;
2250             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2251             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2252             unsigned int byte;
2253             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2254             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2255             byte = ((vaddr & mask) ^ (bigend << shift));
2256             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2257             LLBIT = 1;
2258           }
2259       }
2260   }
2261 }
2262
2263
2264 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2265 "lld r<RT>, <OFFSET>(r<BASE>)"
2266 *mipsIII:
2267 *mipsIV:
2268 *mipsV:
2269 *mips64:
2270 *mips64r2:
2271 *vr4100:
2272 *vr5000:
2273 {
2274   address_word base = GPR[BASE];
2275   address_word offset = EXTEND16 (OFFSET);
2276   check_u64 (SD_, instruction_0);
2277   {
2278     address_word vaddr = loadstore_ea (SD_, base, offset);
2279     address_word paddr;
2280     int uncached;
2281     if ((vaddr & 7) != 0)
2282       {
2283         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2284       }
2285     else
2286       {
2287         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2288           {
2289             unsigned64 memval = 0;
2290             unsigned64 memval1 = 0;
2291             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2292             GPR[RT] = memval;
2293             LLBIT = 1;
2294           }
2295       }
2296   }
2297 }
2298
2299
2300 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2301 "lui r<RT>, %#lx<IMMEDIATE>"
2302 *mipsI:
2303 *mipsII:
2304 *mipsIII:
2305 *mipsIV:
2306 *mipsV:
2307 *mips32:
2308 *mips32r2:
2309 *mips64:
2310 *mips64r2:
2311 *vr4100:
2312 *vr5000:
2313 *r3900:
2314 {
2315   TRACE_ALU_INPUT1 (IMMEDIATE);
2316   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2317   TRACE_ALU_RESULT (GPR[RT]);
2318 }
2319
2320
2321 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2322 "lw r<RT>, <OFFSET>(r<BASE>)"
2323 *mipsI:
2324 *mipsII:
2325 *mipsIII:
2326 *mipsIV:
2327 *mipsV:
2328 *mips32:
2329 *mips32r2:
2330 *mips64:
2331 *mips64r2:
2332 *vr4100:
2333 *vr5000:
2334 *r3900:
2335 {
2336   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2337 }
2338
2339
2340 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2341 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2342 *mipsI:
2343 *mipsII:
2344 *mipsIII:
2345 *mipsIV:
2346 *mipsV:
2347 *mips32:
2348 *mips32r2:
2349 *mips64:
2350 *mips64r2:
2351 *vr4100:
2352 *vr5000:
2353 *r3900:
2354 {
2355   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2356 }
2357
2358
2359 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2360 "lwl r<RT>, <OFFSET>(r<BASE>)"
2361 *mipsI:
2362 *mipsII:
2363 *mipsIII:
2364 *mipsIV:
2365 *mipsV:
2366 *mips32:
2367 *mips32r2:
2368 *mips64:
2369 *mips64r2:
2370 *vr4100:
2371 *vr5000:
2372 *r3900:
2373 {
2374   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2375 }
2376
2377
2378 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2379 "lwr r<RT>, <OFFSET>(r<BASE>)"
2380 *mipsI:
2381 *mipsII:
2382 *mipsIII:
2383 *mipsIV:
2384 *mipsV:
2385 *mips32:
2386 *mips32r2:
2387 *mips64:
2388 *mips64r2:
2389 *vr4100:
2390 *vr5000:
2391 *r3900:
2392 {
2393   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2394 }
2395
2396
2397 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2398 "lwu r<RT>, <OFFSET>(r<BASE>)"
2399 *mipsIII:
2400 *mipsIV:
2401 *mipsV:
2402 *mips64:
2403 *mips64r2:
2404 *vr4100:
2405 *vr5000:
2406 {
2407   check_u64 (SD_, instruction_0);
2408   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2409 }
2410
2411
2412
2413 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2414 "madd r<RS>, r<RT>"
2415 *mips32:
2416 *mips32r2:
2417 *mips64:
2418 *mips64r2:
2419 *vr5500:
2420 {
2421   signed64 temp;
2422   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2423   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2424     Unpredictable ();
2425   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2426   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2427           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2428   LO = EXTEND32 (temp);
2429   HI = EXTEND32 (VH4_8 (temp));
2430   TRACE_ALU_RESULT2 (HI, LO);
2431 }
2432
2433
2434
2435 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2436 "maddu r<RS>, r<RT>"
2437 *mips32:
2438 *mips32r2:
2439 *mips64:
2440 *mips64r2:
2441 *vr5500:
2442 {
2443   unsigned64 temp;
2444   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2445   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2446     Unpredictable ();
2447   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2448   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2449           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2450   ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
2451   LO = EXTEND32 (temp);
2452   HI = EXTEND32 (VH4_8 (temp));
2453   TRACE_ALU_RESULT2 (HI, LO);
2454 }
2455
2456
2457 :function:::void:do_mfhi:int rd
2458 {
2459   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2460   TRACE_ALU_INPUT1 (HI);
2461   GPR[rd] = HI;
2462   TRACE_ALU_RESULT (GPR[rd]);
2463 }
2464
2465 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2466 "mfhi r<RD>"
2467 *mipsI:
2468 *mipsII:
2469 *mipsIII:
2470 *mipsIV:
2471 *mipsV:
2472 *vr4100:
2473 *vr5000:
2474 *r3900:
2475 {
2476   do_mfhi (SD_, RD);
2477 }
2478
2479
2480
2481 :function:::void:do_mflo:int rd
2482 {
2483   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2484   TRACE_ALU_INPUT1 (LO);
2485   GPR[rd] = LO;
2486   TRACE_ALU_RESULT (GPR[rd]);
2487 }
2488
2489 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2490 "mflo r<RD>"
2491 *mipsI:
2492 *mipsII:
2493 *mipsIII:
2494 *mipsIV:
2495 *mipsV:
2496 *vr4100:
2497 *vr5000:
2498 *r3900:
2499 {
2500   do_mflo (SD_, RD);
2501 }
2502
2503
2504
2505 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2506 "movn r<RD>, r<RS>, r<RT>"
2507 *mipsIV:
2508 *mipsV:
2509 *mips32:
2510 *mips32r2:
2511 *mips64:
2512 *mips64r2:
2513 *vr5000:
2514 {
2515   if (GPR[RT] != 0)
2516     {
2517       GPR[RD] = GPR[RS];
2518       TRACE_ALU_RESULT (GPR[RD]);
2519     }
2520 }
2521
2522
2523
2524 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2525 "movz r<RD>, r<RS>, r<RT>"
2526 *mipsIV:
2527 *mipsV:
2528 *mips32:
2529 *mips32r2:
2530 *mips64:
2531 *mips64r2:
2532 *vr5000:
2533 {
2534   if (GPR[RT] == 0)
2535     {
2536       GPR[RD] = GPR[RS];
2537       TRACE_ALU_RESULT (GPR[RD]);
2538     }
2539 }
2540
2541
2542
2543 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2544 "msub r<RS>, r<RT>"
2545 *mips32:
2546 *mips32r2:
2547 *mips64:
2548 *mips64r2:
2549 *vr5500:
2550 {
2551   signed64 temp;
2552   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2553   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2554     Unpredictable ();
2555   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2556   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2557           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2558   LO = EXTEND32 (temp);
2559   HI = EXTEND32 (VH4_8 (temp));
2560   TRACE_ALU_RESULT2 (HI, LO);
2561 }
2562
2563
2564
2565 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2566 "msubu r<RS>, r<RT>"
2567 *mips32:
2568 *mips32r2:
2569 *mips64:
2570 *mips64r2:
2571 *vr5500:
2572 {
2573   unsigned64 temp;
2574   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2575   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2576     Unpredictable ();
2577   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2578   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2579           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2580   LO = EXTEND32 (temp);
2581   HI = EXTEND32 (VH4_8 (temp));
2582   TRACE_ALU_RESULT2 (HI, LO);
2583 }
2584
2585
2586
2587 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2588 "mthi r<RS>"
2589 *mipsI:
2590 *mipsII:
2591 *mipsIII:
2592 *mipsIV:
2593 *mipsV:
2594 *vr4100:
2595 *vr5000:
2596 *r3900:
2597 {
2598   check_mt_hilo (SD_, HIHISTORY);
2599   HI = GPR[RS];
2600 }
2601
2602
2603
2604 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2605 "mtlo r<RS>"
2606 *mipsI:
2607 *mipsII:
2608 *mipsIII:
2609 *mipsIV:
2610 *mipsV:
2611 *vr4100:
2612 *vr5000:
2613 *r3900:
2614 {
2615   check_mt_hilo (SD_, LOHISTORY);
2616   LO = GPR[RS];
2617 }
2618
2619
2620
2621 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2622 "mul r<RD>, r<RS>, r<RT>"
2623 *mips32:
2624 *mips32r2:
2625 *mips64:
2626 *mips64r2:
2627 *vr5500:
2628 {
2629   signed64 prod;
2630   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2631     Unpredictable ();
2632   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2633   prod = (((signed64)(signed32) GPR[RS])
2634           * ((signed64)(signed32) GPR[RT]));
2635   GPR[RD] = EXTEND32 (VL4_8 (prod));
2636   TRACE_ALU_RESULT (GPR[RD]);
2637 }
2638
2639
2640
2641 :function:::void:do_mult:int rs, int rt, int rd
2642 {
2643   signed64 prod;
2644   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2645   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2646     Unpredictable ();
2647   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2648   prod = (((signed64)(signed32) GPR[rs])
2649           * ((signed64)(signed32) GPR[rt]));
2650   LO = EXTEND32 (VL4_8 (prod));
2651   HI = EXTEND32 (VH4_8 (prod));
2652   ACX = 0;  /* SmartMIPS */
2653   if (rd != 0)
2654     GPR[rd] = LO;
2655   TRACE_ALU_RESULT2 (HI, LO);
2656 }
2657
2658 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2659 "mult r<RS>, r<RT>"
2660 *mipsI:
2661 *mipsII:
2662 *mipsIII:
2663 *mipsIV:
2664 *mipsV:
2665 *mips32:
2666 *mips32r2:
2667 *mips64:
2668 *mips64r2:
2669 *vr4100:
2670 {
2671   do_mult (SD_, RS, RT, 0);
2672 }
2673
2674
2675 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2676 "mult r<RS>, r<RT>":RD == 0
2677 "mult r<RD>, r<RS>, r<RT>"
2678 *vr5000:
2679 *r3900:
2680 {
2681   do_mult (SD_, RS, RT, RD);
2682 }
2683
2684
2685 :function:::void:do_multu:int rs, int rt, int rd
2686 {
2687   unsigned64 prod;
2688   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2689   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2690     Unpredictable ();
2691   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2692   prod = (((unsigned64)(unsigned32) GPR[rs])
2693           * ((unsigned64)(unsigned32) GPR[rt]));
2694   LO = EXTEND32 (VL4_8 (prod));
2695   HI = EXTEND32 (VH4_8 (prod));
2696   if (rd != 0)
2697     GPR[rd] = LO;
2698   TRACE_ALU_RESULT2 (HI, LO);
2699 }
2700
2701 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2702 "multu r<RS>, r<RT>"
2703 *mipsI:
2704 *mipsII:
2705 *mipsIII:
2706 *mipsIV:
2707 *mipsV:
2708 *mips32:
2709 *mips32r2:
2710 *mips64:
2711 *mips64r2:
2712 *vr4100:
2713 {
2714   do_multu (SD_, RS, RT, 0);
2715 }
2716
2717 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2718 "multu r<RS>, r<RT>":RD == 0
2719 "multu r<RD>, r<RS>, r<RT>"
2720 *vr5000:
2721 *r3900:
2722 {
2723   do_multu (SD_, RS, RT, RD);
2724 }
2725
2726
2727 :function:::void:do_nor:int rs, int rt, int rd
2728 {
2729   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2730   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2731   TRACE_ALU_RESULT (GPR[rd]);
2732 }
2733
2734 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2735 "nor r<RD>, r<RS>, r<RT>"
2736 *mipsI:
2737 *mipsII:
2738 *mipsIII:
2739 *mipsIV:
2740 *mipsV:
2741 *mips32:
2742 *mips32r2:
2743 *mips64:
2744 *mips64r2:
2745 *vr4100:
2746 *vr5000:
2747 *r3900:
2748 {
2749   do_nor (SD_, RS, RT, RD);
2750 }
2751
2752
2753 :function:::void:do_or:int rs, int rt, int rd
2754 {
2755   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2756   GPR[rd] = (GPR[rs] | GPR[rt]);
2757   TRACE_ALU_RESULT (GPR[rd]);
2758 }
2759
2760 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2761 "or r<RD>, r<RS>, r<RT>"
2762 *mipsI:
2763 *mipsII:
2764 *mipsIII:
2765 *mipsIV:
2766 *mipsV:
2767 *mips32:
2768 *mips32r2:
2769 *mips64:
2770 *mips64r2:
2771 *vr4100:
2772 *vr5000:
2773 *r3900:
2774 {
2775   do_or (SD_, RS, RT, RD);
2776 }
2777
2778
2779
2780 :function:::void:do_ori:int rs, int rt, unsigned immediate
2781 {
2782   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2783   GPR[rt] = (GPR[rs] | immediate);
2784   TRACE_ALU_RESULT (GPR[rt]);
2785 }
2786
2787 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2788 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2789 *mipsI:
2790 *mipsII:
2791 *mipsIII:
2792 *mipsIV:
2793 *mipsV:
2794 *mips32:
2795 *mips32r2:
2796 *mips64:
2797 *mips64r2:
2798 *vr4100:
2799 *vr5000:
2800 *r3900:
2801 {
2802   do_ori (SD_, RS, RT, IMMEDIATE);
2803 }
2804
2805
2806 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2807 "pref <HINT>, <OFFSET>(r<BASE>)"
2808 *mipsIV:
2809 *mipsV:
2810 *mips32:
2811 *mips32r2:
2812 *mips64:
2813 *mips64r2:
2814 *vr5000:
2815 {
2816   address_word base = GPR[BASE];
2817   address_word offset = EXTEND16 (OFFSET);
2818   {
2819     address_word vaddr = loadstore_ea (SD_, base, offset);
2820     address_word paddr;
2821     int uncached;
2822     {
2823       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2824         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2825     }
2826   }
2827 }
2828
2829
2830 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
2831 {
2832   unsigned64 result;
2833
2834   y &= 31;
2835   TRACE_ALU_INPUT2 (x, y);
2836   result = EXTEND32 (ROTR32 (x, y));
2837   TRACE_ALU_RESULT (result);
2838   return result;
2839 }
2840
2841 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
2842 "ror r<RD>, r<RT>, <SHIFT>"
2843 *mips32r2:
2844 *mips64r2:
2845 *smartmips:
2846 *vr5400:
2847 *vr5500:
2848 {
2849   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
2850 }
2851
2852 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
2853 "rorv r<RD>, r<RT>, r<RS>"
2854 *mips32r2:
2855 *mips64r2:
2856 *smartmips:
2857 *vr5400:
2858 *vr5500:
2859 {
2860   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
2861 }
2862
2863
2864 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2865 {
2866   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2867   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2868   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2869   unsigned int byte;
2870   address_word paddr;
2871   int uncached;
2872   unsigned64 memval;
2873   address_word vaddr;
2874
2875   vaddr = loadstore_ea (SD_, base, offset);
2876   if ((vaddr & access) != 0)
2877     {
2878       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2879     }
2880   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2881   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2882   byte = ((vaddr & mask) ^ bigendiancpu);
2883   memval = (word << (8 * byte));
2884   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2885 }
2886
2887 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2888 {
2889   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2890   address_word reverseendian = (ReverseEndian ? -1 : 0);
2891   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2892   unsigned int byte;
2893   unsigned int word;
2894   address_word paddr;
2895   int uncached;
2896   unsigned64 memval;
2897   address_word vaddr;
2898   int nr_lhs_bits;
2899   int nr_rhs_bits;
2900
2901   vaddr = loadstore_ea (SD_, base, offset);
2902   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2903   paddr = (paddr ^ (reverseendian & mask));
2904   if (BigEndianMem == 0)
2905     paddr = paddr & ~access;
2906
2907   /* compute where within the word/mem we are */
2908   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2909   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2910   nr_lhs_bits = 8 * byte + 8;
2911   nr_rhs_bits = 8 * access - 8 * byte;
2912   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2913   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2914            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2915            (long) ((unsigned64) paddr >> 32), (long) paddr,
2916            word, byte, nr_lhs_bits, nr_rhs_bits); */
2917
2918   if (word == 0)
2919     {
2920       memval = (rt >> nr_rhs_bits);
2921     }
2922   else
2923     {
2924       memval = (rt << nr_lhs_bits);
2925     }
2926   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2927            (long) ((unsigned64) rt >> 32), (long) rt,
2928            (long) ((unsigned64) memval >> 32), (long) memval); */
2929   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2930 }
2931
2932 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2933 {
2934   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2935   address_word reverseendian = (ReverseEndian ? -1 : 0);
2936   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2937   unsigned int byte;
2938   address_word paddr;
2939   int uncached;
2940   unsigned64 memval;
2941   address_word vaddr;
2942
2943   vaddr = loadstore_ea (SD_, base, offset);
2944   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2945   paddr = (paddr ^ (reverseendian & mask));
2946   if (BigEndianMem != 0)
2947     paddr &= ~access;
2948   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2949   memval = (rt << (byte * 8));
2950   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2951 }
2952
2953
2954 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2955 "sb r<RT>, <OFFSET>(r<BASE>)"
2956 *mipsI:
2957 *mipsII:
2958 *mipsIII:
2959 *mipsIV:
2960 *mipsV:
2961 *mips32:
2962 *mips32r2:
2963 *mips64:
2964 *mips64r2:
2965 *vr4100:
2966 *vr5000:
2967 *r3900:
2968 {
2969   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2970 }
2971
2972
2973 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2974 "sc r<RT>, <OFFSET>(r<BASE>)"
2975 *mipsII:
2976 *mipsIII:
2977 *mipsIV:
2978 *mipsV:
2979 *mips32:
2980 *mips32r2:
2981 *mips64:
2982 *mips64r2:
2983 *vr4100:
2984 *vr5000:
2985 {
2986   unsigned32 instruction = instruction_0;
2987   address_word base = GPR[BASE];
2988   address_word offset = EXTEND16 (OFFSET);
2989   {
2990     address_word vaddr = loadstore_ea (SD_, base, offset);
2991     address_word paddr;
2992     int uncached;
2993     if ((vaddr & 3) != 0)
2994       {
2995         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2996       }
2997     else
2998       {
2999         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3000           {
3001             unsigned64 memval = 0;
3002             unsigned64 memval1 = 0;
3003             unsigned64 mask = 0x7;
3004             unsigned int byte;
3005             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3006             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3007             memval = ((unsigned64) GPR[RT] << (8 * byte));
3008             if (LLBIT)
3009               {
3010                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3011               }
3012             GPR[RT] = LLBIT;
3013           }
3014       }
3015   }
3016 }
3017
3018
3019 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3020 "scd r<RT>, <OFFSET>(r<BASE>)"
3021 *mipsIII:
3022 *mipsIV:
3023 *mipsV:
3024 *mips64:
3025 *mips64r2:
3026 *vr4100:
3027 *vr5000:
3028 {
3029   address_word base = GPR[BASE];
3030   address_word offset = EXTEND16 (OFFSET);
3031   check_u64 (SD_, instruction_0);
3032   {
3033     address_word vaddr = loadstore_ea (SD_, base, offset);
3034     address_word paddr;
3035     int uncached;
3036     if ((vaddr & 7) != 0)
3037       {
3038         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3039       }
3040     else
3041       {
3042         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3043           {
3044             unsigned64 memval = 0;
3045             unsigned64 memval1 = 0;
3046             memval = GPR[RT];
3047             if (LLBIT)
3048               {
3049                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3050               }
3051             GPR[RT] = LLBIT;
3052           }
3053       }
3054   }
3055 }
3056
3057
3058 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3059 "sd r<RT>, <OFFSET>(r<BASE>)"
3060 *mipsIII:
3061 *mipsIV:
3062 *mipsV:
3063 *mips64:
3064 *mips64r2:
3065 *vr4100:
3066 *vr5000:
3067 {
3068   check_u64 (SD_, instruction_0);
3069   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3070 }
3071
3072
3073 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3074 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3075 *mipsII:
3076 *mipsIII:
3077 *mipsIV:
3078 *mipsV:
3079 *mips32:
3080 *mips32r2:
3081 *mips64:
3082 *mips64r2:
3083 *vr4100:
3084 *vr5000:
3085 {
3086   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3087 }
3088
3089
3090 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3091 "sdl r<RT>, <OFFSET>(r<BASE>)"
3092 *mipsIII:
3093 *mipsIV:
3094 *mipsV:
3095 *mips64:
3096 *mips64r2:
3097 *vr4100:
3098 *vr5000:
3099 {
3100   check_u64 (SD_, instruction_0);
3101   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3102 }
3103
3104
3105 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3106 "sdr r<RT>, <OFFSET>(r<BASE>)"
3107 *mipsIII:
3108 *mipsIV:
3109 *mipsV:
3110 *mips64:
3111 *mips64r2:
3112 *vr4100:
3113 *vr5000:
3114 {
3115   check_u64 (SD_, instruction_0);
3116   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3117 }
3118
3119
3120
3121 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3122 "sh r<RT>, <OFFSET>(r<BASE>)"
3123 *mipsI:
3124 *mipsII:
3125 *mipsIII:
3126 *mipsIV:
3127 *mipsV:
3128 *mips32:
3129 *mips32r2:
3130 *mips64:
3131 *mips64r2:
3132 *vr4100:
3133 *vr5000:
3134 *r3900:
3135 {
3136   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3137 }
3138
3139
3140 :function:::void:do_sll:int rt, int rd, int shift
3141 {
3142   unsigned32 temp = (GPR[rt] << shift);
3143   TRACE_ALU_INPUT2 (GPR[rt], shift);
3144   GPR[rd] = EXTEND32 (temp);
3145   TRACE_ALU_RESULT (GPR[rd]);
3146 }
3147
3148 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3149 "nop":RD == 0 && RT == 0 && SHIFT == 0
3150 "sll r<RD>, r<RT>, <SHIFT>"
3151 *mipsI:
3152 *mipsII:
3153 *mipsIII:
3154 *mipsIV:
3155 *mipsV:
3156 *vr4100:
3157 *vr5000:
3158 *r3900:
3159 {
3160   /* Skip shift for NOP, so that there won't be lots of extraneous
3161      trace output.  */
3162   if (RD != 0 || RT != 0 || SHIFT != 0)
3163     do_sll (SD_, RT, RD, SHIFT);
3164 }
3165
3166 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3167 "nop":RD == 0 && RT == 0 && SHIFT == 0
3168 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3169 "sll r<RD>, r<RT>, <SHIFT>"
3170 *mips32:
3171 *mips32r2:
3172 *mips64:
3173 *mips64r2:
3174 {
3175   /* Skip shift for NOP and SSNOP, so that there won't be lots of
3176      extraneous trace output.  */
3177   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3178     do_sll (SD_, RT, RD, SHIFT);
3179 }
3180
3181
3182 :function:::void:do_sllv:int rs, int rt, int rd
3183 {
3184   int s = MASKED (GPR[rs], 4, 0);
3185   unsigned32 temp = (GPR[rt] << s);
3186   TRACE_ALU_INPUT2 (GPR[rt], s);
3187   GPR[rd] = EXTEND32 (temp);
3188   TRACE_ALU_RESULT (GPR[rd]);
3189 }
3190
3191 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3192 "sllv r<RD>, r<RT>, r<RS>"
3193 *mipsI:
3194 *mipsII:
3195 *mipsIII:
3196 *mipsIV:
3197 *mipsV:
3198 *mips32:
3199 *mips32r2:
3200 *mips64:
3201 *mips64r2:
3202 *vr4100:
3203 *vr5000:
3204 *r3900:
3205 {
3206   do_sllv (SD_, RS, RT, RD);
3207 }
3208
3209
3210 :function:::void:do_slt:int rs, int rt, int rd
3211 {
3212   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3213   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3214   TRACE_ALU_RESULT (GPR[rd]);
3215 }
3216
3217 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3218 "slt r<RD>, r<RS>, r<RT>"
3219 *mipsI:
3220 *mipsII:
3221 *mipsIII:
3222 *mipsIV:
3223 *mipsV:
3224 *mips32:
3225 *mips32r2:
3226 *mips64:
3227 *mips64r2:
3228 *vr4100:
3229 *vr5000:
3230 *r3900:
3231 {
3232   do_slt (SD_, RS, RT, RD);
3233 }
3234
3235
3236 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3237 {
3238   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3239   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3240   TRACE_ALU_RESULT (GPR[rt]);
3241 }
3242
3243 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3244 "slti r<RT>, r<RS>, <IMMEDIATE>"
3245 *mipsI:
3246 *mipsII:
3247 *mipsIII:
3248 *mipsIV:
3249 *mipsV:
3250 *mips32:
3251 *mips32r2:
3252 *mips64:
3253 *mips64r2:
3254 *vr4100:
3255 *vr5000:
3256 *r3900:
3257 {
3258   do_slti (SD_, RS, RT, IMMEDIATE);
3259 }
3260
3261
3262 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3263 {
3264   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3265   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3266   TRACE_ALU_RESULT (GPR[rt]);
3267 }
3268
3269 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3270 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3271 *mipsI:
3272 *mipsII:
3273 *mipsIII:
3274 *mipsIV:
3275 *mipsV:
3276 *mips32:
3277 *mips32r2:
3278 *mips64:
3279 *mips64r2:
3280 *vr4100:
3281 *vr5000:
3282 *r3900:
3283 {
3284   do_sltiu (SD_, RS, RT, IMMEDIATE);
3285 }
3286
3287
3288
3289 :function:::void:do_sltu:int rs, int rt, int rd
3290 {
3291   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3292   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3293   TRACE_ALU_RESULT (GPR[rd]);
3294 }
3295
3296 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3297 "sltu r<RD>, r<RS>, r<RT>"
3298 *mipsI:
3299 *mipsII:
3300 *mipsIII:
3301 *mipsIV:
3302 *mipsV:
3303 *mips32:
3304 *mips32r2:
3305 *mips64:
3306 *mips64r2:
3307 *vr4100:
3308 *vr5000:
3309 *r3900:
3310 {
3311   do_sltu (SD_, RS, RT, RD);
3312 }
3313
3314
3315 :function:::void:do_sra:int rt, int rd, int shift
3316 {
3317   signed32 temp = (signed32) GPR[rt] >> shift;
3318   if (NotWordValue (GPR[rt]))
3319     Unpredictable ();
3320   TRACE_ALU_INPUT2 (GPR[rt], shift);
3321   GPR[rd] = EXTEND32 (temp);
3322   TRACE_ALU_RESULT (GPR[rd]);
3323 }
3324
3325 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3326 "sra r<RD>, r<RT>, <SHIFT>"
3327 *mipsI:
3328 *mipsII:
3329 *mipsIII:
3330 *mipsIV:
3331 *mipsV:
3332 *mips32:
3333 *mips32r2:
3334 *mips64:
3335 *mips64r2:
3336 *vr4100:
3337 *vr5000:
3338 *r3900:
3339 {
3340   do_sra (SD_, RT, RD, SHIFT);
3341 }
3342
3343
3344
3345 :function:::void:do_srav:int rs, int rt, int rd
3346 {
3347   int s = MASKED (GPR[rs], 4, 0);
3348   signed32 temp = (signed32) GPR[rt] >> s;
3349   if (NotWordValue (GPR[rt]))
3350     Unpredictable ();
3351   TRACE_ALU_INPUT2 (GPR[rt], s);
3352   GPR[rd] = EXTEND32 (temp);
3353   TRACE_ALU_RESULT (GPR[rd]);
3354 }
3355
3356 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3357 "srav r<RD>, r<RT>, r<RS>"
3358 *mipsI:
3359 *mipsII:
3360 *mipsIII:
3361 *mipsIV:
3362 *mipsV:
3363 *mips32:
3364 *mips32r2:
3365 *mips64:
3366 *mips64r2:
3367 *vr4100:
3368 *vr5000:
3369 *r3900:
3370 {
3371   do_srav (SD_, RS, RT, RD);
3372 }
3373
3374
3375
3376 :function:::void:do_srl:int rt, int rd, int shift
3377 {
3378   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3379   if (NotWordValue (GPR[rt]))
3380     Unpredictable ();
3381   TRACE_ALU_INPUT2 (GPR[rt], shift);
3382   GPR[rd] = EXTEND32 (temp);
3383   TRACE_ALU_RESULT (GPR[rd]);
3384 }
3385
3386 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3387 "srl r<RD>, r<RT>, <SHIFT>"
3388 *mipsI:
3389 *mipsII:
3390 *mipsIII:
3391 *mipsIV:
3392 *mipsV:
3393 *mips32:
3394 *mips32r2:
3395 *mips64:
3396 *mips64r2:
3397 *vr4100:
3398 *vr5000:
3399 *r3900:
3400 {
3401   do_srl (SD_, RT, RD, SHIFT);
3402 }
3403
3404
3405 :function:::void:do_srlv:int rs, int rt, int rd
3406 {
3407   int s = MASKED (GPR[rs], 4, 0);
3408   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3409   if (NotWordValue (GPR[rt]))
3410     Unpredictable ();
3411   TRACE_ALU_INPUT2 (GPR[rt], s);
3412   GPR[rd] = EXTEND32 (temp);
3413   TRACE_ALU_RESULT (GPR[rd]);
3414 }
3415
3416 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3417 "srlv r<RD>, r<RT>, r<RS>"
3418 *mipsI:
3419 *mipsII:
3420 *mipsIII:
3421 *mipsIV:
3422 *mipsV:
3423 *mips32:
3424 *mips32r2:
3425 *mips64:
3426 *mips64r2:
3427 *vr4100:
3428 *vr5000:
3429 *r3900:
3430 {
3431   do_srlv (SD_, RS, RT, RD);
3432 }
3433
3434
3435 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3436 "sub r<RD>, r<RS>, r<RT>"
3437 *mipsI:
3438 *mipsII:
3439 *mipsIII:
3440 *mipsIV:
3441 *mipsV:
3442 *mips32:
3443 *mips32r2:
3444 *mips64:
3445 *mips64r2:
3446 *vr4100:
3447 *vr5000:
3448 *r3900:
3449 {
3450   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3451     Unpredictable ();
3452   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3453   {
3454     ALU32_BEGIN (GPR[RS]);
3455     ALU32_SUB (GPR[RT]);
3456     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3457   }
3458   TRACE_ALU_RESULT (GPR[RD]);
3459 }
3460
3461
3462 :function:::void:do_subu:int rs, int rt, int rd
3463 {
3464   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3465     Unpredictable ();
3466   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3467   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3468   TRACE_ALU_RESULT (GPR[rd]);
3469 }
3470
3471 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3472 "subu r<RD>, r<RS>, r<RT>"
3473 *mipsI:
3474 *mipsII:
3475 *mipsIII:
3476 *mipsIV:
3477 *mipsV:
3478 *mips32:
3479 *mips32r2:
3480 *mips64:
3481 *mips64r2:
3482 *vr4100:
3483 *vr5000:
3484 *r3900:
3485 {
3486   do_subu (SD_, RS, RT, RD);
3487 }
3488
3489
3490 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3491 "sw r<RT>, <OFFSET>(r<BASE>)"
3492 *mipsI:
3493 *mipsII:
3494 *mipsIII:
3495 *mipsIV:
3496 *mipsV:
3497 *mips32:
3498 *mips32r2:
3499 *mips64:
3500 *mips64r2:
3501 *vr4100:
3502 *r3900:
3503 *vr5000:
3504 {
3505   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3506 }
3507
3508
3509 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3510 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3511 *mipsI:
3512 *mipsII:
3513 *mipsIII:
3514 *mipsIV:
3515 *mipsV:
3516 *mips32:
3517 *mips32r2:
3518 *mips64:
3519 *mips64r2:
3520 *vr4100:
3521 *vr5000:
3522 *r3900:
3523 {
3524   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3525 }
3526
3527
3528 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3529 "swl r<RT>, <OFFSET>(r<BASE>)"
3530 *mipsI:
3531 *mipsII:
3532 *mipsIII:
3533 *mipsIV:
3534 *mipsV:
3535 *mips32:
3536 *mips32r2:
3537 *mips64:
3538 *mips64r2:
3539 *vr4100:
3540 *vr5000:
3541 *r3900:
3542 {
3543   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3544 }
3545
3546
3547 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3548 "swr r<RT>, <OFFSET>(r<BASE>)"
3549 *mipsI:
3550 *mipsII:
3551 *mipsIII:
3552 *mipsIV:
3553 *mipsV:
3554 *mips32:
3555 *mips32r2:
3556 *mips64:
3557 *mips64r2:
3558 *vr4100:
3559 *vr5000:
3560 *r3900:
3561 {
3562   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3563 }
3564
3565
3566 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3567 "sync":STYPE == 0
3568 "sync <STYPE>"
3569 *mipsII:
3570 *mipsIII:
3571 *mipsIV:
3572 *mipsV:
3573 *mips32:
3574 *mips32r2:
3575 *mips64:
3576 *mips64r2:
3577 *vr4100:
3578 *vr5000:
3579 *r3900:
3580 {
3581   SyncOperation (STYPE);
3582 }
3583
3584
3585 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3586 "syscall %#lx<CODE>"
3587 *mipsI:
3588 *mipsII:
3589 *mipsIII:
3590 *mipsIV:
3591 *mipsV:
3592 *mips32:
3593 *mips32r2:
3594 *mips64:
3595 *mips64r2:
3596 *vr4100:
3597 *vr5000:
3598 *r3900:
3599 {
3600   SignalException (SystemCall, instruction_0);
3601 }
3602
3603
3604 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3605 "teq r<RS>, r<RT>"
3606 *mipsII:
3607 *mipsIII:
3608 *mipsIV:
3609 *mipsV:
3610 *mips32:
3611 *mips32r2:
3612 *mips64:
3613 *mips64r2:
3614 *vr4100:
3615 *vr5000:
3616 {
3617   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3618     SignalException (Trap, instruction_0);
3619 }
3620
3621
3622 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3623 "teqi r<RS>, <IMMEDIATE>"
3624 *mipsII:
3625 *mipsIII:
3626 *mipsIV:
3627 *mipsV:
3628 *mips32:
3629 *mips32r2:
3630 *mips64:
3631 *mips64r2:
3632 *vr4100:
3633 *vr5000:
3634 {
3635   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3636     SignalException (Trap, instruction_0);
3637 }
3638
3639
3640 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3641 "tge r<RS>, r<RT>"
3642 *mipsII:
3643 *mipsIII:
3644 *mipsIV:
3645 *mipsV:
3646 *mips32:
3647 *mips32r2:
3648 *mips64:
3649 *mips64r2:
3650 *vr4100:
3651 *vr5000:
3652 {
3653   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3654     SignalException (Trap, instruction_0);
3655 }
3656
3657
3658 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3659 "tgei r<RS>, <IMMEDIATE>"
3660 *mipsII:
3661 *mipsIII:
3662 *mipsIV:
3663 *mipsV:
3664 *mips32:
3665 *mips32r2:
3666 *mips64:
3667 *mips64r2:
3668 *vr4100:
3669 *vr5000:
3670 {
3671   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3672     SignalException (Trap, instruction_0);
3673 }
3674
3675
3676 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3677 "tgeiu r<RS>, <IMMEDIATE>"
3678 *mipsII:
3679 *mipsIII:
3680 *mipsIV:
3681 *mipsV:
3682 *mips32:
3683 *mips32r2:
3684 *mips64:
3685 *mips64r2:
3686 *vr4100:
3687 *vr5000:
3688 {
3689   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3690     SignalException (Trap, instruction_0);
3691 }
3692
3693
3694 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3695 "tgeu r<RS>, r<RT>"
3696 *mipsII:
3697 *mipsIII:
3698 *mipsIV:
3699 *mipsV:
3700 *mips32:
3701 *mips32r2:
3702 *mips64:
3703 *mips64r2:
3704 *vr4100:
3705 *vr5000:
3706 {
3707   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3708     SignalException (Trap, instruction_0);
3709 }
3710
3711
3712 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3713 "tlt r<RS>, r<RT>"
3714 *mipsII:
3715 *mipsIII:
3716 *mipsIV:
3717 *mipsV:
3718 *mips32:
3719 *mips32r2:
3720 *mips64:
3721 *mips64r2:
3722 *vr4100:
3723 *vr5000:
3724 {
3725   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3726     SignalException (Trap, instruction_0);
3727 }
3728
3729
3730 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3731 "tlti r<RS>, <IMMEDIATE>"
3732 *mipsII:
3733 *mipsIII:
3734 *mipsIV:
3735 *mipsV:
3736 *mips32:
3737 *mips32r2:
3738 *mips64:
3739 *mips64r2:
3740 *vr4100:
3741 *vr5000:
3742 {
3743   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3744     SignalException (Trap, instruction_0);
3745 }
3746
3747
3748 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3749 "tltiu r<RS>, <IMMEDIATE>"
3750 *mipsII:
3751 *mipsIII:
3752 *mipsIV:
3753 *mipsV:
3754 *mips32:
3755 *mips32r2:
3756 *mips64:
3757 *mips64r2:
3758 *vr4100:
3759 *vr5000:
3760 {
3761   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3762     SignalException (Trap, instruction_0);
3763 }
3764
3765
3766 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3767 "tltu r<RS>, r<RT>"
3768 *mipsII:
3769 *mipsIII:
3770 *mipsIV:
3771 *mipsV:
3772 *mips32:
3773 *mips32r2:
3774 *mips64:
3775 *mips64r2:
3776 *vr4100:
3777 *vr5000:
3778 {
3779   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3780     SignalException (Trap, instruction_0);
3781 }
3782
3783
3784 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3785 "tne r<RS>, r<RT>"
3786 *mipsII:
3787 *mipsIII:
3788 *mipsIV:
3789 *mipsV:
3790 *mips32:
3791 *mips32r2:
3792 *mips64:
3793 *mips64r2:
3794 *vr4100:
3795 *vr5000:
3796 {
3797   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3798     SignalException (Trap, instruction_0);
3799 }
3800
3801
3802 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3803 "tnei r<RS>, <IMMEDIATE>"
3804 *mipsII:
3805 *mipsIII:
3806 *mipsIV:
3807 *mipsV:
3808 *mips32:
3809 *mips32r2:
3810 *mips64:
3811 *mips64r2:
3812 *vr4100:
3813 *vr5000:
3814 {
3815   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3816     SignalException (Trap, instruction_0);
3817 }
3818
3819
3820 :function:::void:do_xor:int rs, int rt, int rd
3821 {
3822   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3823   GPR[rd] = GPR[rs] ^ GPR[rt];
3824   TRACE_ALU_RESULT (GPR[rd]);
3825 }
3826
3827 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3828 "xor r<RD>, r<RS>, r<RT>"
3829 *mipsI:
3830 *mipsII:
3831 *mipsIII:
3832 *mipsIV:
3833 *mipsV:
3834 *mips32:
3835 *mips32r2:
3836 *mips64:
3837 *mips64r2:
3838 *vr4100:
3839 *vr5000:
3840 *r3900:
3841 {
3842   do_xor (SD_, RS, RT, RD);
3843 }
3844
3845
3846 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3847 {
3848   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3849   GPR[rt] = GPR[rs] ^ immediate;
3850   TRACE_ALU_RESULT (GPR[rt]);
3851 }
3852
3853 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3854 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3855 *mipsI:
3856 *mipsII:
3857 *mipsIII:
3858 *mipsIV:
3859 *mipsV:
3860 *mips32:
3861 *mips32r2:
3862 *mips64:
3863 *mips64r2:
3864 *vr4100:
3865 *vr5000:
3866 *r3900:
3867 {
3868   do_xori (SD_, RS, RT, IMMEDIATE);
3869 }
3870
3871 \f
3872 //
3873 // MIPS Architecture:
3874 //
3875 //        FPU Instruction Set (COP1 & COP1X)
3876 //
3877
3878
3879 :%s::::FMT:int fmt
3880 {
3881   switch (fmt)
3882     {
3883     case fmt_single: return "s";
3884     case fmt_double: return "d";
3885     case fmt_word: return "w";
3886     case fmt_long: return "l";
3887     case fmt_ps: return "ps";
3888     default: return "?";
3889     }
3890 }
3891
3892 :%s::::TF:int tf
3893 {
3894   if (tf)
3895     return "t";
3896   else
3897     return "f";
3898 }
3899
3900 :%s::::ND:int nd
3901 {
3902   if (nd)
3903     return "l";
3904   else
3905     return "";
3906 }
3907
3908 :%s::::COND:int cond
3909 {
3910   switch (cond)
3911     {
3912     case 00: return "f";
3913     case 01: return "un";
3914     case 02: return "eq";
3915     case 03: return "ueq";
3916     case 04: return "olt";
3917     case 05: return "ult";
3918     case 06: return "ole";
3919     case 07: return "ule";
3920     case 010: return "sf";
3921     case 011: return "ngle";
3922     case 012: return "seq";
3923     case 013: return "ngl";
3924     case 014: return "lt";
3925     case 015: return "nge";
3926     case 016: return "le";
3927     case 017: return "ngt";
3928     default: return "?";
3929     }
3930 }
3931
3932
3933 // Helpers:
3934 //
3935 // Check that the given FPU format is usable, and signal a
3936 // ReservedInstruction exception if not.
3937 //
3938
3939 // check_fmt_p checks that the format is single, double, or paired single.
3940 :function:::void:check_fmt_p:int fmt, instruction_word insn
3941 *mipsI:
3942 *mipsII:
3943 *mipsIII:
3944 *mipsIV:
3945 *mips32:
3946 *mips32r2:
3947 *vr4100:
3948 *vr5000:
3949 *r3900:
3950 {
3951   /* None of these ISAs support Paired Single, so just fall back to
3952      the single/double check.  */
3953   if ((fmt != fmt_single) && (fmt != fmt_double))
3954     SignalException (ReservedInstruction, insn);
3955 }
3956
3957 :function:::void:check_fmt_p:int fmt, instruction_word insn
3958 *mipsV:
3959 *mips64:
3960 *mips64r2:
3961 {
3962   if ((fmt != fmt_single) && (fmt != fmt_double)
3963       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3964     SignalException (ReservedInstruction, insn);
3965 }
3966
3967
3968 // Helper:
3969 //
3970 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3971 // exception if not.
3972 //
3973
3974 :function:::void:check_fpu:
3975 *mipsI:
3976 *mipsII:
3977 *mipsIII:
3978 *mipsIV:
3979 *mipsV:
3980 *mips32:
3981 *mips32r2:
3982 *mips64:
3983 *mips64r2:
3984 *vr4100:
3985 *vr5000:
3986 *r3900:
3987 {
3988   if (! COP_Usable (1))
3989     SignalExceptionCoProcessorUnusable (1);
3990 }
3991
3992
3993 // Helper:
3994 //
3995 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3996 // or MIPS32.  do_load cannot be used instead because it returns an
3997 // unsigned_word, which is limited to the size of the machine's registers.
3998 //
3999
4000 :function:::unsigned64:do_load_double:address_word base, address_word offset
4001 *mipsII:
4002 *mips32:
4003 *mips32r2:
4004 {
4005   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4006   address_word vaddr;
4007   address_word paddr;
4008   int uncached;
4009   unsigned64 memval;
4010   unsigned64 v;
4011
4012   vaddr = loadstore_ea (SD_, base, offset);
4013   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4014     {
4015       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4016                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4017                        sim_core_unaligned_signal);
4018     }
4019   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4020                       isREAL);
4021   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4022               isDATA, isREAL);
4023   v = (unsigned64)memval;
4024   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4025               isDATA, isREAL);
4026   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4027 }
4028
4029
4030 // Helper:
4031 //
4032 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4033 // or MIPS32.  do_load cannot be used instead because it returns an
4034 // unsigned_word, which is limited to the size of the machine's registers.
4035 //
4036
4037 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4038 *mipsII:
4039 *mips32:
4040 *mips32r2:
4041 {
4042   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4043   address_word vaddr;
4044   address_word paddr;
4045   int uncached;
4046   unsigned64 memval;
4047
4048   vaddr = loadstore_ea (SD_, base, offset);
4049   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4050     {
4051       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4052                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4053                        sim_core_unaligned_signal);
4054     }
4055   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4056                       isREAL);
4057   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4058   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4059                isREAL);
4060   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4061   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4062                isREAL);
4063 }
4064
4065
4066 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4067 "abs.%s<FMT> f<FD>, f<FS>"
4068 *mipsI:
4069 *mipsII:
4070 *mipsIII:
4071 *mipsIV:
4072 *mipsV:
4073 *mips32:
4074 *mips32r2:
4075 *mips64:
4076 *mips64r2:
4077 *vr4100:
4078 *vr5000:
4079 *r3900:
4080 {
4081   int fmt = FMT;
4082   check_fpu (SD_);
4083   check_fmt_p (SD_, fmt, instruction_0);
4084   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4085 }
4086
4087
4088
4089 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4090 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4091 *mipsI:
4092 *mipsII:
4093 *mipsIII:
4094 *mipsIV:
4095 *mipsV:
4096 *mips32:
4097 *mips32r2:
4098 *mips64:
4099 *mips64r2:
4100 *vr4100:
4101 *vr5000:
4102 *r3900:
4103 {
4104   int fmt = FMT;
4105   check_fpu (SD_);
4106   check_fmt_p (SD_, fmt, instruction_0);
4107   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4108 }
4109
4110
4111 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4112 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4113 *mipsV:
4114 *mips64:
4115 *mips64r2:
4116 {
4117   unsigned64 fs;
4118   unsigned64 ft;
4119   unsigned64 fd;
4120   check_fpu (SD_);
4121   check_u64 (SD_, instruction_0);
4122   fs = ValueFPR (FS, fmt_ps);
4123   if ((GPR[RS] & 0x3) != 0)
4124     Unpredictable ();
4125   if ((GPR[RS] & 0x4) == 0)
4126     fd = fs;
4127   else
4128     {
4129       ft = ValueFPR (FT, fmt_ps);
4130       if (BigEndianCPU)
4131         fd = PackPS (PSLower (fs), PSUpper (ft));
4132       else
4133         fd = PackPS (PSLower (ft), PSUpper (fs));
4134     }
4135   StoreFPR (FD, fmt_ps, fd);
4136 }
4137
4138
4139 // BC1F
4140 // BC1FL
4141 // BC1T
4142 // BC1TL
4143
4144 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4145 "bc1%s<TF>%s<ND> <OFFSET>"
4146 *mipsI:
4147 *mipsII:
4148 *mipsIII:
4149 {
4150   check_fpu (SD_);
4151   TRACE_BRANCH_INPUT (PREVCOC1());
4152   if (PREVCOC1() == TF)
4153     {
4154       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4155       TRACE_BRANCH_RESULT (dest);
4156       DELAY_SLOT (dest);
4157     }
4158   else if (ND)
4159     {
4160       TRACE_BRANCH_RESULT (0);
4161       NULLIFY_NEXT_INSTRUCTION ();
4162     }
4163   else
4164     {
4165       TRACE_BRANCH_RESULT (NIA);
4166     }
4167 }
4168
4169 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4170 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4171 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4172 *mipsIV:
4173 *mipsV:
4174 *mips32:
4175 *mips32r2:
4176 *mips64:
4177 *mips64r2:
4178 #*vr4100:
4179 *vr5000:
4180 *r3900:
4181 {
4182   check_fpu (SD_);
4183   if (GETFCC(CC) == TF)
4184     {
4185       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4186       DELAY_SLOT (dest);
4187     }
4188   else if (ND)
4189     {
4190       NULLIFY_NEXT_INSTRUCTION ();
4191     }
4192 }
4193
4194
4195 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4196 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4197 *mipsI:
4198 *mipsII:
4199 *mipsIII:
4200 {
4201   int fmt = FMT;
4202   check_fpu (SD_);
4203   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4204   TRACE_ALU_RESULT (ValueFCR (31));
4205 }
4206
4207 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4208 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4209 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4210 *mipsIV:
4211 *mipsV:
4212 *mips32:
4213 *mips32r2:
4214 *mips64:
4215 *mips64r2:
4216 *vr4100:
4217 *vr5000:
4218 *r3900:
4219 {
4220   int fmt = FMT;
4221   check_fpu (SD_);
4222   check_fmt_p (SD_, fmt, instruction_0);
4223   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4224   TRACE_ALU_RESULT (ValueFCR (31));
4225 }
4226
4227
4228 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4229 "ceil.l.%s<FMT> f<FD>, f<FS>"
4230 *mipsIII:
4231 *mipsIV:
4232 *mipsV:
4233 *mips64:
4234 *mips64r2:
4235 *vr4100:
4236 *vr5000:
4237 *r3900:
4238 {
4239   int fmt = FMT;
4240   check_fpu (SD_);
4241   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4242             fmt_long));
4243 }
4244
4245
4246 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4247 "ceil.w.%s<FMT> f<FD>, f<FS>"
4248 *mipsII:
4249 *mipsIII:
4250 *mipsIV:
4251 *mipsV:
4252 *mips32:
4253 *mips32r2:
4254 *mips64:
4255 *mips64r2:
4256 *vr4100:
4257 *vr5000:
4258 *r3900:
4259 {
4260   int fmt = FMT;
4261   check_fpu (SD_);
4262   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4263             fmt_word));
4264 }
4265
4266
4267 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4268 "cfc1 r<RT>, f<FS>"
4269 *mipsI:
4270 *mipsII:
4271 *mipsIII:
4272 {
4273   check_fpu (SD_);
4274   if (FS == 0)
4275     PENDING_FILL (RT, EXTEND32 (FCR0));
4276   else if (FS == 31)
4277     PENDING_FILL (RT, EXTEND32 (FCR31));
4278   /* else NOP */
4279 }
4280
4281 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4282 "cfc1 r<RT>, f<FS>"
4283 *mipsIV:
4284 *vr4100:
4285 *vr5000:
4286 *r3900:
4287 {
4288   check_fpu (SD_);
4289   if (FS == 0 || FS == 31)
4290     {
4291       unsigned_word  fcr = ValueFCR (FS);
4292       TRACE_ALU_INPUT1 (fcr);
4293       GPR[RT] = fcr;
4294     }
4295   /* else NOP */
4296   TRACE_ALU_RESULT (GPR[RT]);
4297 }
4298
4299 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4300 "cfc1 r<RT>, f<FS>"
4301 *mipsV:
4302 *mips32:
4303 *mips32r2:
4304 *mips64:
4305 *mips64r2:
4306 {
4307   check_fpu (SD_);
4308   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4309     {
4310       unsigned_word  fcr = ValueFCR (FS);
4311       TRACE_ALU_INPUT1 (fcr);
4312       GPR[RT] = fcr;
4313     }
4314   /* else NOP */
4315   TRACE_ALU_RESULT (GPR[RT]);
4316 }
4317
4318 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4319 "ctc1 r<RT>, f<FS>"
4320 *mipsI:
4321 *mipsII:
4322 *mipsIII:
4323 {
4324   check_fpu (SD_);
4325   if (FS == 31)
4326     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4327   /* else NOP */
4328 }
4329
4330 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4331 "ctc1 r<RT>, f<FS>"
4332 *mipsIV:
4333 *vr4100:
4334 *vr5000:
4335 *r3900:
4336 {
4337   check_fpu (SD_);
4338   TRACE_ALU_INPUT1 (GPR[RT]);
4339   if (FS == 31)
4340     StoreFCR (FS, GPR[RT]);
4341   /* else NOP */
4342 }
4343
4344 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4345 "ctc1 r<RT>, f<FS>"
4346 *mipsV:
4347 *mips32:
4348 *mips32r2:
4349 *mips64:
4350 *mips64r2:
4351 {
4352   check_fpu (SD_);
4353   TRACE_ALU_INPUT1 (GPR[RT]);
4354   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4355       StoreFCR (FS, GPR[RT]);
4356   /* else NOP */
4357 }
4358
4359
4360 //
4361 // FIXME: Does not correctly differentiate between mips*
4362 //
4363 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4364 "cvt.d.%s<FMT> f<FD>, f<FS>"
4365 *mipsI:
4366 *mipsII:
4367 *mipsIII:
4368 *mipsIV:
4369 *mipsV:
4370 *mips32:
4371 *mips32r2:
4372 *mips64:
4373 *mips64r2:
4374 *vr4100:
4375 *vr5000:
4376 *r3900:
4377 {
4378   int fmt = FMT;
4379   check_fpu (SD_);
4380   if ((fmt == fmt_double) | 0)
4381     SignalException (ReservedInstruction, instruction_0);
4382   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4383             fmt_double));
4384 }
4385
4386
4387 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4388 "cvt.l.%s<FMT> f<FD>, f<FS>"
4389 *mipsIII:
4390 *mipsIV:
4391 *mipsV:
4392 *mips64:
4393 *mips64r2:
4394 *vr4100:
4395 *vr5000:
4396 *r3900:
4397 {
4398   int fmt = FMT;
4399   check_fpu (SD_);
4400   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4401     SignalException (ReservedInstruction, instruction_0);
4402   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4403             fmt_long));
4404 }
4405
4406
4407 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4408 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4409 *mipsV:
4410 *mips64:
4411 *mips64r2:
4412 {
4413   check_fpu (SD_);
4414   check_u64 (SD_, instruction_0);
4415   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4416                                 ValueFPR (FT, fmt_single)));
4417 }
4418
4419
4420 //
4421 // FIXME: Does not correctly differentiate between mips*
4422 //
4423 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4424 "cvt.s.%s<FMT> f<FD>, f<FS>"
4425 *mipsI:
4426 *mipsII:
4427 *mipsIII:
4428 *mipsIV:
4429 *mipsV:
4430 *mips32:
4431 *mips32r2:
4432 *mips64:
4433 *mips64r2:
4434 *vr4100:
4435 *vr5000:
4436 *r3900:
4437 {
4438   int fmt = FMT;
4439   check_fpu (SD_);
4440   if ((fmt == fmt_single) | 0)
4441     SignalException (ReservedInstruction, instruction_0);
4442   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4443             fmt_single));
4444 }
4445
4446
4447 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4448 "cvt.s.pl f<FD>, f<FS>"
4449 *mipsV:
4450 *mips64:
4451 *mips64r2:
4452 {
4453   check_fpu (SD_);
4454   check_u64 (SD_, instruction_0);
4455   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4456 }
4457
4458
4459 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4460 "cvt.s.pu f<FD>, f<FS>"
4461 *mipsV:
4462 *mips64:
4463 *mips64r2:
4464 {
4465   check_fpu (SD_);
4466   check_u64 (SD_, instruction_0);
4467   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4468 }
4469
4470
4471 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4472 "cvt.w.%s<FMT> f<FD>, f<FS>"
4473 *mipsI:
4474 *mipsII:
4475 *mipsIII:
4476 *mipsIV:
4477 *mipsV:
4478 *mips32:
4479 *mips32r2:
4480 *mips64:
4481 *mips64r2:
4482 *vr4100:
4483 *vr5000:
4484 *r3900:
4485 {
4486   int fmt = FMT;
4487   check_fpu (SD_);
4488   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4489     SignalException (ReservedInstruction, instruction_0);
4490   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4491             fmt_word));
4492 }
4493
4494
4495 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4496 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4497 *mipsI:
4498 *mipsII:
4499 *mipsIII:
4500 *mipsIV:
4501 *mipsV:
4502 *mips32:
4503 *mips32r2:
4504 *mips64:
4505 *mips64r2:
4506 *vr4100:
4507 *vr5000:
4508 *r3900:
4509 {
4510   int fmt = FMT;
4511   check_fpu (SD_);
4512   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4513 }
4514
4515
4516 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4517 "dmfc1 r<RT>, f<FS>"
4518 *mipsIII:
4519 {
4520   unsigned64 v;
4521   check_fpu (SD_);
4522   check_u64 (SD_, instruction_0);
4523   if (SizeFGR () == 64)
4524     v = FGR[FS];
4525   else if ((FS & 0x1) == 0)
4526     v = SET64HI (FGR[FS+1]) | FGR[FS];
4527   else
4528     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4529   PENDING_FILL (RT, v);
4530   TRACE_ALU_RESULT (v);
4531 }
4532
4533 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4534 "dmfc1 r<RT>, f<FS>"
4535 *mipsIV:
4536 *mipsV:
4537 *mips64:
4538 *mips64r2:
4539 *vr4100:
4540 *vr5000:
4541 *r3900:
4542 {
4543   check_fpu (SD_);
4544   check_u64 (SD_, instruction_0);
4545   if (SizeFGR () == 64)
4546     GPR[RT] = FGR[FS];
4547   else if ((FS & 0x1) == 0)
4548     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4549   else
4550     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4551   TRACE_ALU_RESULT (GPR[RT]);
4552 }
4553
4554
4555 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4556 "dmtc1 r<RT>, f<FS>"
4557 *mipsIII:
4558 {
4559   unsigned64 v;
4560   check_fpu (SD_);
4561   check_u64 (SD_, instruction_0);
4562   if (SizeFGR () == 64)
4563     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4564   else if ((FS & 0x1) == 0)
4565     {
4566       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4567       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4568     }
4569   else
4570     Unpredictable ();
4571   TRACE_FP_RESULT (GPR[RT]);
4572 }
4573
4574 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4575 "dmtc1 r<RT>, f<FS>"
4576 *mipsIV:
4577 *mipsV:
4578 *mips64:
4579 *mips64r2:
4580 *vr4100:
4581 *vr5000:
4582 *r3900:
4583 {
4584   check_fpu (SD_);
4585   check_u64 (SD_, instruction_0);
4586   if (SizeFGR () == 64)
4587     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4588   else if ((FS & 0x1) == 0)
4589     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4590   else
4591     Unpredictable ();
4592 }
4593
4594
4595 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4596 "floor.l.%s<FMT> f<FD>, f<FS>"
4597 *mipsIII:
4598 *mipsIV:
4599 *mipsV:
4600 *mips64:
4601 *mips64r2:
4602 *vr4100:
4603 *vr5000:
4604 *r3900:
4605 {
4606   int fmt = FMT;
4607   check_fpu (SD_);
4608   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4609             fmt_long));
4610 }
4611
4612
4613 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4614 "floor.w.%s<FMT> f<FD>, f<FS>"
4615 *mipsII:
4616 *mipsIII:
4617 *mipsIV:
4618 *mipsV:
4619 *mips32:
4620 *mips32r2:
4621 *mips64:
4622 *mips64r2:
4623 *vr4100:
4624 *vr5000:
4625 *r3900:
4626 {
4627   int fmt = FMT;
4628   check_fpu (SD_);
4629   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4630             fmt_word));
4631 }
4632
4633
4634 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4635 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4636 *mipsII:
4637 *mips32:
4638 *mips32r2:
4639 {
4640   check_fpu (SD_);
4641   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4642 }
4643
4644
4645 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4646 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4647 *mipsIII:
4648 *mipsIV:
4649 *mipsV:
4650 *mips64:
4651 *mips64r2:
4652 *vr4100:
4653 *vr5000:
4654 *r3900:
4655 {
4656   check_fpu (SD_);
4657   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4658 }
4659
4660
4661 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4662 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4663 *mipsIV:
4664 *mipsV:
4665 *mips64:
4666 *mips64r2:
4667 *vr5000:
4668 {
4669   check_fpu (SD_);
4670   check_u64 (SD_, instruction_0);
4671   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4672 }
4673
4674
4675 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4676 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4677 *mipsV:
4678 *mips64:
4679 *mips64r2:
4680 {
4681   address_word base = GPR[BASE];
4682   address_word index = GPR[INDEX];
4683   address_word vaddr = base + index;
4684   check_fpu (SD_);
4685   check_u64 (SD_, instruction_0);
4686   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4687   if ((vaddr & 0x7) != 0)
4688     index -= (vaddr & 0x7);
4689   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4690 }
4691
4692
4693 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4694 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4695 *mipsI:
4696 *mipsII:
4697 *mipsIII:
4698 *mipsIV:
4699 *mipsV:
4700 *mips32:
4701 *mips32r2:
4702 *mips64:
4703 *mips64r2:
4704 *vr4100:
4705 *vr5000:
4706 *r3900:
4707 {
4708   check_fpu (SD_);
4709   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4710 }
4711
4712
4713 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4714 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4715 *mipsIV:
4716 *mipsV:
4717 *mips64:
4718 *mips64r2:
4719 *vr5000:
4720 {
4721   check_fpu (SD_);
4722   check_u64 (SD_, instruction_0);
4723   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4724 }
4725
4726
4727
4728 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4729 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4730 *mipsIV:
4731 *mipsV:
4732 *mips64:
4733 *mips64r2:
4734 *vr5000:
4735 {
4736   int fmt = FMT;
4737   check_fpu (SD_);
4738   check_u64 (SD_, instruction_0);
4739   check_fmt_p (SD_, fmt, instruction_0);
4740   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4741                                   ValueFPR (FR, fmt), fmt));
4742 }
4743
4744
4745 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4746 "mfc1 r<RT>, f<FS>"
4747 *mipsI:
4748 *mipsII:
4749 *mipsIII:
4750 {
4751   unsigned64 v;
4752   check_fpu (SD_);
4753   v = EXTEND32 (FGR[FS]);
4754   PENDING_FILL (RT, v);
4755   TRACE_ALU_RESULT (v);
4756 }
4757
4758 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4759 "mfc1 r<RT>, f<FS>"
4760 *mipsIV:
4761 *mipsV:
4762 *mips32:
4763 *mips32r2:
4764 *mips64:
4765 *mips64r2:
4766 *vr4100:
4767 *vr5000:
4768 *r3900:
4769 {
4770   check_fpu (SD_);
4771   GPR[RT] = EXTEND32 (FGR[FS]);
4772   TRACE_ALU_RESULT (GPR[RT]);
4773 }
4774
4775
4776 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4777 "mov.%s<FMT> f<FD>, f<FS>"
4778 *mipsI:
4779 *mipsII:
4780 *mipsIII:
4781 *mipsIV:
4782 *mipsV:
4783 *mips32:
4784 *mips32r2:
4785 *mips64:
4786 *mips64r2:
4787 *vr4100:
4788 *vr5000:
4789 *r3900:
4790 {
4791   int fmt = FMT;
4792   check_fpu (SD_);
4793   check_fmt_p (SD_, fmt, instruction_0);
4794   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4795 }
4796
4797
4798 // MOVF
4799 // MOVT
4800 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4801 "mov%s<TF> r<RD>, r<RS>, <CC>"
4802 *mipsIV:
4803 *mipsV:
4804 *mips32:
4805 *mips32r2:
4806 *mips64:
4807 *mips64r2:
4808 *vr5000:
4809 {
4810   check_fpu (SD_);
4811   if (GETFCC(CC) == TF)
4812     GPR[RD] = GPR[RS];
4813 }
4814
4815
4816 // MOVF.fmt
4817 // MOVT.fmt
4818 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4819 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4820 *mipsIV:
4821 *mipsV:
4822 *mips32:
4823 *mips32r2:
4824 *mips64:
4825 *mips64r2:
4826 *vr5000:
4827 {
4828   int fmt = FMT;
4829   check_fpu (SD_);
4830   if (fmt != fmt_ps)
4831     {
4832       if (GETFCC(CC) == TF)
4833         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4834       else
4835         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4836     }
4837   else
4838     {
4839       unsigned64 fd;
4840       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4841                                       fmt_ps)),
4842                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4843                                       fmt_ps)));
4844       StoreFPR (FD, fmt_ps, fd);
4845     }
4846 }
4847
4848
4849 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4850 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4851 *mipsIV:
4852 *mipsV:
4853 *mips32:
4854 *mips32r2:
4855 *mips64:
4856 *mips64r2:
4857 *vr5000:
4858 {
4859   check_fpu (SD_);
4860   if (GPR[RT] != 0)
4861     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4862   else
4863     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4864 }
4865
4866
4867 // MOVT see MOVtf
4868
4869
4870 // MOVT.fmt see MOVtf.fmt
4871
4872
4873
4874 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4875 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4876 *mipsIV:
4877 *mipsV:
4878 *mips32:
4879 *mips32r2:
4880 *mips64:
4881 *mips64r2:
4882 *vr5000:
4883 {
4884   check_fpu (SD_);
4885   if (GPR[RT] == 0)
4886     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4887   else
4888     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4889 }
4890
4891
4892 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
4893 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4894 *mipsIV:
4895 *mipsV:
4896 *mips64:
4897 *mips64r2:
4898 *vr5000:
4899 {
4900   int fmt = FMT;
4901   check_fpu (SD_);
4902   check_u64 (SD_, instruction_0);
4903   check_fmt_p (SD_, fmt, instruction_0);
4904   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4905                                   ValueFPR (FR, fmt), fmt));
4906 }
4907
4908
4909 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4910 "mtc1 r<RT>, f<FS>"
4911 *mipsI:
4912 *mipsII:
4913 *mipsIII:
4914 {
4915   check_fpu (SD_);
4916   if (SizeFGR () == 64)
4917     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4918   else
4919     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4920   TRACE_FP_RESULT (GPR[RT]);
4921 }
4922
4923 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4924 "mtc1 r<RT>, f<FS>"
4925 *mipsIV:
4926 *mipsV:
4927 *mips32:
4928 *mips32r2:
4929 *mips64:
4930 *mips64r2:
4931 *vr4100:
4932 *vr5000:
4933 *r3900:
4934 {
4935   check_fpu (SD_);
4936   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4937 }
4938
4939
4940 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4941 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4942 *mipsI:
4943 *mipsII:
4944 *mipsIII:
4945 *mipsIV:
4946 *mipsV:
4947 *mips32:
4948 *mips32r2:
4949 *mips64:
4950 *mips64r2:
4951 *vr4100:
4952 *vr5000:
4953 *r3900:
4954 {
4955   int fmt = FMT;
4956   check_fpu (SD_);
4957   check_fmt_p (SD_, fmt, instruction_0);
4958   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4959 }
4960
4961
4962 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4963 "neg.%s<FMT> f<FD>, f<FS>"
4964 *mipsI:
4965 *mipsII:
4966 *mipsIII:
4967 *mipsIV:
4968 *mipsV:
4969 *mips32:
4970 *mips32r2:
4971 *mips64:
4972 *mips64r2:
4973 *vr4100:
4974 *vr5000:
4975 *r3900:
4976 {
4977   int fmt = FMT;
4978   check_fpu (SD_);
4979   check_fmt_p (SD_, fmt, instruction_0);
4980   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4981 }
4982
4983
4984 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
4985 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4986 *mipsIV:
4987 *mipsV:
4988 *mips64:
4989 *mips64r2:
4990 *vr5000:
4991 {
4992   int fmt = FMT;
4993   check_fpu (SD_);
4994   check_u64 (SD_, instruction_0);
4995   check_fmt_p (SD_, fmt, instruction_0);
4996   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4997                                      ValueFPR (FR, fmt), fmt));
4998 }
4999
5000
5001 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5002 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5003 *mipsIV:
5004 *mipsV:
5005 *mips64:
5006 *mips64r2:
5007 *vr5000:
5008 {
5009   int fmt = FMT;
5010   check_fpu (SD_);
5011   check_u64 (SD_, instruction_0);
5012   check_fmt_p (SD_, fmt, instruction_0);
5013   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5014                                      ValueFPR (FR, fmt), fmt));
5015 }
5016
5017
5018 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5019 "pll.ps f<FD>, f<FS>, f<FT>"
5020 *mipsV:
5021 *mips64:
5022 *mips64r2:
5023 {
5024   check_fpu (SD_);
5025   check_u64 (SD_, instruction_0);
5026   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5027                                 PSLower (ValueFPR (FT, fmt_ps))));
5028 }
5029
5030
5031 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5032 "plu.ps f<FD>, f<FS>, f<FT>"
5033 *mipsV:
5034 *mips64:
5035 *mips64r2:
5036 {
5037   check_fpu (SD_);
5038   check_u64 (SD_, instruction_0);
5039   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5040                                 PSUpper (ValueFPR (FT, fmt_ps))));
5041 }
5042
5043
5044 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5045 "prefx <HINT>, r<INDEX>(r<BASE>)"
5046 *mipsIV:
5047 *mipsV:
5048 *mips64:
5049 *mips64r2:
5050 *vr5000:
5051 {
5052   address_word base = GPR[BASE];
5053   address_word index = GPR[INDEX];
5054   {
5055     address_word vaddr = loadstore_ea (SD_, base, index);
5056     address_word paddr;
5057     int uncached;
5058     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5059       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5060   }
5061 }
5062
5063
5064 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5065 "pul.ps f<FD>, f<FS>, f<FT>"
5066 *mipsV:
5067 *mips64:
5068 *mips64r2:
5069 {
5070   check_fpu (SD_);
5071   check_u64 (SD_, instruction_0);
5072   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5073                                 PSLower (ValueFPR (FT, fmt_ps))));
5074 }
5075
5076
5077 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5078 "puu.ps f<FD>, f<FS>, f<FT>"
5079 *mipsV:
5080 *mips64:
5081 *mips64r2:
5082 {
5083   check_fpu (SD_);
5084   check_u64 (SD_, instruction_0);
5085   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5086                                 PSUpper (ValueFPR (FT, fmt_ps))));
5087 }
5088
5089
5090 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5091 "recip.%s<FMT> f<FD>, f<FS>"
5092 *mipsIV:
5093 *mipsV:
5094 *mips64:
5095 *mips64r2:
5096 *vr5000:
5097 {
5098   int fmt = FMT;
5099   check_fpu (SD_);
5100   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5101 }
5102
5103
5104 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5105 "round.l.%s<FMT> f<FD>, f<FS>"
5106 *mipsIII:
5107 *mipsIV:
5108 *mipsV:
5109 *mips64:
5110 *mips64r2:
5111 *vr4100:
5112 *vr5000:
5113 *r3900:
5114 {
5115   int fmt = FMT;
5116   check_fpu (SD_);
5117   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5118             fmt_long));
5119 }
5120
5121
5122 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5123 "round.w.%s<FMT> f<FD>, f<FS>"
5124 *mipsII:
5125 *mipsIII:
5126 *mipsIV:
5127 *mipsV:
5128 *mips32:
5129 *mips32r2:
5130 *mips64:
5131 *mips64r2:
5132 *vr4100:
5133 *vr5000:
5134 *r3900:
5135 {
5136   int fmt = FMT;
5137   check_fpu (SD_);
5138   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5139             fmt_word));
5140 }
5141
5142
5143 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5144 "rsqrt.%s<FMT> f<FD>, f<FS>"
5145 *mipsIV:
5146 *mipsV:
5147 *mips64:
5148 *mips64r2:
5149 *vr5000:
5150 {
5151   int fmt = FMT;
5152   check_fpu (SD_);
5153   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5154 }
5155
5156
5157 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5158 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5159 *mipsII:
5160 *mips32:
5161 *mips32r2:
5162 {
5163   check_fpu (SD_);
5164   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5165 }
5166
5167
5168 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5169 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5170 *mipsIII:
5171 *mipsIV:
5172 *mipsV:
5173 *mips64:
5174 *mips64r2:
5175 *vr4100:
5176 *vr5000:
5177 *r3900:
5178 {
5179   check_fpu (SD_);
5180   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5181 }
5182
5183
5184 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5185 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5186 *mipsIV:
5187 *mipsV:
5188 *mips64:
5189 *mips64r2:
5190 *vr5000:
5191 {
5192   check_fpu (SD_);
5193   check_u64 (SD_, instruction_0);
5194   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5195 }
5196
5197
5198 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5199 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5200 *mipsV:
5201 *mips64:
5202 *mips64r2:
5203 {
5204   unsigned64 v;
5205   address_word base = GPR[BASE];
5206   address_word index = GPR[INDEX];
5207   address_word vaddr = base + index;
5208   check_fpu (SD_);
5209   check_u64 (SD_, instruction_0);
5210   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
5211   if ((vaddr & 0x7) != 0)
5212     index -= (vaddr & 0x7);
5213   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5214 }
5215
5216
5217 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5218 "sqrt.%s<FMT> f<FD>, f<FS>"
5219 *mipsII:
5220 *mipsIII:
5221 *mipsIV:
5222 *mipsV:
5223 *mips32:
5224 *mips32r2:
5225 *mips64:
5226 *mips64r2:
5227 *vr4100:
5228 *vr5000:
5229 *r3900:
5230 {
5231   int fmt = FMT;
5232   check_fpu (SD_);
5233   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
5234 }
5235
5236
5237 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5238 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5239 *mipsI:
5240 *mipsII:
5241 *mipsIII:
5242 *mipsIV:
5243 *mipsV:
5244 *mips32:
5245 *mips32r2:
5246 *mips64:
5247 *mips64r2:
5248 *vr4100:
5249 *vr5000:
5250 *r3900:
5251 {
5252   int fmt = FMT;
5253   check_fpu (SD_);
5254   check_fmt_p (SD_, fmt, instruction_0);
5255   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5256 }
5257
5258
5259
5260 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5261 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5262 *mipsI:
5263 *mipsII:
5264 *mipsIII:
5265 *mipsIV:
5266 *mipsV:
5267 *mips32:
5268 *mips32r2:
5269 *mips64:
5270 *mips64r2:
5271 *vr4100:
5272 *vr5000:
5273 *r3900:
5274 {
5275   address_word base = GPR[BASE];
5276   address_word offset = EXTEND16 (OFFSET);
5277   check_fpu (SD_);
5278   {
5279     address_word vaddr = loadstore_ea (SD_, base, offset);
5280     address_word paddr;
5281     int uncached;
5282     if ((vaddr & 3) != 0)
5283       {
5284         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5285       }
5286     else
5287       {
5288         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5289           {
5290             uword64 memval = 0;
5291             uword64 memval1 = 0;
5292             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5293             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5294             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5295             unsigned int byte;
5296             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5297             byte = ((vaddr & mask) ^ bigendiancpu);
5298             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5299             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5300           }
5301       }
5302   }
5303 }
5304
5305
5306 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5307 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5308 *mipsIV:
5309 *mipsV:
5310 *mips64:
5311 *mips64r2:
5312 *vr5000:
5313 {
5314
5315   address_word base = GPR[BASE];
5316   address_word index = GPR[INDEX];
5317   check_fpu (SD_);
5318   check_u64 (SD_, instruction_0);
5319   {
5320    address_word vaddr = loadstore_ea (SD_, base, index);
5321    address_word paddr;
5322    int uncached;
5323    if ((vaddr & 3) != 0)
5324      {
5325        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5326      }
5327    else
5328    {
5329     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5330     {
5331      unsigned64 memval = 0;
5332      unsigned64 memval1 = 0;
5333      unsigned64 mask = 0x7;
5334      unsigned int byte;
5335      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5336      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5337      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5338       {
5339        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5340       }
5341     }
5342    }
5343   }
5344 }
5345
5346
5347 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5348 "trunc.l.%s<FMT> f<FD>, f<FS>"
5349 *mipsIII:
5350 *mipsIV:
5351 *mipsV:
5352 *mips64:
5353 *mips64r2:
5354 *vr4100:
5355 *vr5000:
5356 *r3900:
5357 {
5358   int fmt = FMT;
5359   check_fpu (SD_);
5360   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5361             fmt_long));
5362 }
5363
5364
5365 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5366 "trunc.w.%s<FMT> f<FD>, f<FS>"
5367 *mipsII:
5368 *mipsIII:
5369 *mipsIV:
5370 *mipsV:
5371 *mips32:
5372 *mips32r2:
5373 *mips64:
5374 *mips64r2:
5375 *vr4100:
5376 *vr5000:
5377 *r3900:
5378 {
5379   int fmt = FMT;
5380   check_fpu (SD_);
5381   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5382             fmt_word));
5383 }
5384
5385 \f
5386 //
5387 // MIPS Architecture:
5388 //
5389 //        System Control Instruction Set (COP0)
5390 //
5391
5392
5393 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5394 "bc0f <OFFSET>"
5395 *mipsI:
5396 *mipsII:
5397 *mipsIII:
5398 *mipsIV:
5399 *mipsV:
5400 *mips32:
5401 *mips32r2:
5402 *mips64:
5403 *mips64r2:
5404 *vr4100:
5405 *vr5000:
5406
5407 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5408 "bc0f <OFFSET>"
5409 // stub needed for eCos as tx39 hardware bug workaround
5410 *r3900:
5411 {
5412   /* do nothing */
5413 }
5414
5415
5416 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5417 "bc0fl <OFFSET>"
5418 *mipsI:
5419 *mipsII:
5420 *mipsIII:
5421 *mipsIV:
5422 *mipsV:
5423 *mips32:
5424 *mips32r2:
5425 *mips64:
5426 *mips64r2:
5427 *vr4100:
5428 *vr5000:
5429
5430
5431 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5432 "bc0t <OFFSET>"
5433 *mipsI:
5434 *mipsII:
5435 *mipsIII:
5436 *mipsIV:
5437 *mipsV:
5438 *mips32:
5439 *mips32r2:
5440 *mips64:
5441 *mips64r2:
5442 *vr4100:
5443
5444
5445 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5446 "bc0tl <OFFSET>"
5447 *mipsI:
5448 *mipsII:
5449 *mipsIII:
5450 *mipsIV:
5451 *mipsV:
5452 *mips32:
5453 *mips32r2:
5454 *mips64:
5455 *mips64r2:
5456 *vr4100:
5457 *vr5000:
5458
5459
5460 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5461 "cache <OP>, <OFFSET>(r<BASE>)"
5462 *mipsIII:
5463 *mipsIV:
5464 *mipsV:
5465 *mips32:
5466 *mips32r2:
5467 *mips64:
5468 *mips64r2:
5469 *vr4100:
5470 *vr5000:
5471 *r3900:
5472 {
5473   address_word base = GPR[BASE];
5474   address_word offset = EXTEND16 (OFFSET);
5475   {
5476     address_word vaddr = loadstore_ea (SD_, base, offset);
5477     address_word paddr;
5478     int uncached;
5479     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5480       CacheOp(OP,vaddr,paddr,instruction_0);
5481   }
5482 }
5483
5484
5485 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5486 "dmfc0 r<RT>, r<RD>"
5487 *mipsIII:
5488 *mipsIV:
5489 *mipsV:
5490 *mips64:
5491 *mips64r2:
5492 {
5493   check_u64 (SD_, instruction_0);
5494   DecodeCoproc (instruction_0);
5495 }
5496
5497
5498 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5499 "dmtc0 r<RT>, r<RD>"
5500 *mipsIII:
5501 *mipsIV:
5502 *mipsV:
5503 *mips64:
5504 *mips64r2:
5505 {
5506   check_u64 (SD_, instruction_0);
5507   DecodeCoproc (instruction_0);
5508 }
5509
5510
5511 010000,1,0000000000000000000,011000:COP0:32::ERET
5512 "eret"
5513 *mipsIII:
5514 *mipsIV:
5515 *mipsV:
5516 *mips32:
5517 *mips32r2:
5518 *mips64:
5519 *mips64r2:
5520 *vr4100:
5521 *vr5000:
5522 {
5523   if (SR & status_ERL)
5524     {
5525       /* Oops, not yet available */
5526       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5527       NIA = EPC;
5528       SR &= ~status_ERL;
5529     }
5530   else
5531     {
5532       NIA = EPC;
5533       SR &= ~status_EXL;
5534     }
5535 }
5536
5537
5538 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5539 "mfc0 r<RT>, r<RD> # <REGX>"
5540 *mipsI:
5541 *mipsII:
5542 *mipsIII:
5543 *mipsIV:
5544 *mipsV:
5545 *mips32:
5546 *mips32r2:
5547 *mips64:
5548 *mips64r2:
5549 *vr4100:
5550 *vr5000:
5551 *r3900:
5552 {
5553   TRACE_ALU_INPUT0 ();
5554   DecodeCoproc (instruction_0);
5555   TRACE_ALU_RESULT (GPR[RT]);
5556 }
5557
5558 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5559 "mtc0 r<RT>, r<RD> # <REGX>"
5560 *mipsI:
5561 *mipsII:
5562 *mipsIII:
5563 *mipsIV:
5564 *mipsV:
5565 *mips32:
5566 *mips32r2:
5567 *mips64:
5568 *mips64r2:
5569 *vr4100:
5570 *vr5000:
5571 *r3900:
5572 {
5573   DecodeCoproc (instruction_0);
5574 }
5575
5576
5577 010000,1,0000000000000000000,010000:COP0:32::RFE
5578 "rfe"
5579 *mipsI:
5580 *mipsII:
5581 *mipsIII:
5582 *mipsIV:
5583 *mipsV:
5584 *vr4100:
5585 *vr5000:
5586 *r3900:
5587 {
5588   DecodeCoproc (instruction_0);
5589 }
5590
5591
5592 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5593 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5594 *mipsI:
5595 *mipsII:
5596 *mipsIII:
5597 *mipsIV:
5598 *mipsV:
5599 *mips32:
5600 *mips32r2:
5601 *mips64:
5602 *mips64r2:
5603 *vr4100:
5604 *r3900:
5605 {
5606   DecodeCoproc (instruction_0);
5607 }
5608
5609
5610
5611 010000,1,0000000000000000000,001000:COP0:32::TLBP
5612 "tlbp"
5613 *mipsI:
5614 *mipsII:
5615 *mipsIII:
5616 *mipsIV:
5617 *mipsV:
5618 *mips32:
5619 *mips32r2:
5620 *mips64:
5621 *mips64r2:
5622 *vr4100:
5623 *vr5000:
5624
5625
5626 010000,1,0000000000000000000,000001:COP0:32::TLBR
5627 "tlbr"
5628 *mipsI:
5629 *mipsII:
5630 *mipsIII:
5631 *mipsIV:
5632 *mipsV:
5633 *mips32:
5634 *mips32r2:
5635 *mips64:
5636 *mips64r2:
5637 *vr4100:
5638 *vr5000:
5639
5640
5641 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5642 "tlbwi"
5643 *mipsI:
5644 *mipsII:
5645 *mipsIII:
5646 *mipsIV:
5647 *mipsV:
5648 *mips32:
5649 *mips32r2:
5650 *mips64:
5651 *mips64r2:
5652 *vr4100:
5653 *vr5000:
5654
5655
5656 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5657 "tlbwr"
5658 *mipsI:
5659 *mipsII:
5660 *mipsIII:
5661 *mipsIV:
5662 *mipsV:
5663 *mips32:
5664 *mips32r2:
5665 *mips64:
5666 *mips64r2:
5667 *vr4100:
5668 *vr5000:
5669
5670
5671 :include:::mips3264r2.igen
5672 :include:::m16.igen
5673 :include:::m16e.igen
5674 :include:::mdmx.igen
5675 :include:::mips3d.igen
5676 :include:::sb1.igen
5677 :include:::tx.igen
5678 :include:::vr.igen
5679 :include:::dsp.igen
5680 :include:::smartmips.igen
5681