sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator
  38 :model:::mipsI:mips3000:
  39 :model:::mipsII:mips6000:
  40 :model:::mipsIII:mips4000:
  41 :model:::mipsIV:mips8000:
  42 :model:::mips16:mips16:
  43 // start-sanitize-r5900
  44 :model:::r5900:mips5900:
  45 // end-sanitize-r5900
  46 :model:::r3900:mips3900:
  47 // start-sanitize-tx19
  48 :model:::tx19:tx19:
  49 // end-sanitize-tx19
  50 :model:::vr4100:mips4100:
  51 // start-sanitize-vr4320
  52 :model:::vr4320:mips4320:
  53 // end-sanitize-vr4320
  54 // start-sanitize-cygnus
  55 :model:::vr5400:mips5400:
  56 :model:::mdmx:mdmx:
  57 // end-sanitize-cygnus
  58 :model:::vr5000:mips5000:
  59
  60
  61
  62 // Pseudo instructions known by IGEN
  63 :internal::::illegal:
  64 {
  65   SignalException (ReservedInstruction, 0);
  66 }
  67
  68
  69 // Pseudo instructions known by interp.c
  70 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  71 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  72 "rsvd <OP>"
  73 {
  74   SignalException (ReservedInstruction, instruction_0);
  75 }
  76
  77
  78
  79 // Helper:
  80 //
  81 // Simulate a 32 bit delayslot instruction
  82 //
  83
  84 :function:::address_word:delayslot32:address_word target
  85 {
  86   instruction_word delay_insn;
  87   sim_events_slip (SD, 1);
  88   DSPC = CIA;
  89   CIA = CIA + 4; /* NOTE not mips16 */
  90   STATE |= simDELAYSLOT;
  91   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  92   idecode_issue (CPU_, delay_insn, (CIA));
  93   STATE &= ~simDELAYSLOT;
  94   return target;
  95 }
  96
  97 :function:::address_word:nullify_next_insn32:
  98 {
  99   sim_events_slip (SD, 1);
 100   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 101   return CIA + 8;
 102 }
 103
 104 // start-sanitize-branchbug4011
 105 :function:::void:check_4011_branch_bug:
 106 {
 107   if (BRANCHBUG4011_OPTION == 2 && BRANCHBUG4011_LAST_TARGET == CIA)
 108     sim_engine_abort (SD, CPU, CIA, "4011 BRANCH BUG: %s at 0x%08lx was target of branch at 0x%08lx\n",
 109                       itable[MY_INDEX].name,
 110                       (long) CIA,
 111                       (long) BRANCHBUG4011_LAST_CIA);
 112 }
 113
 114 :function:::void:mark_4011_branch_bug:address_word target
 115 {
 116   if (BRANCHBUG4011_OPTION)
 117     {
 118       BRANCHBUG4011_OPTION = 2;
 119       BRANCHBUG4011_LAST_TARGET = target;
 120       BRANCHBUG4011_LAST_CIA = CIA;
 121     }
 122 }
 123
 124 // end-sanitize-branchbug4011
 125 // Helper:
 126 //
 127 // Check that an access to a HI/LO register meets timing requirements
 128 //
 129 // The following requirements exist:
 130 //
 131 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 132 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
 133 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 134 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 135 //
 136
 137 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 138 {
 139   if (history->mf.timestamp + 3 > time)
 140     {
 141       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 142                         itable[MY_INDEX].name,
 143                         new, (long) CIA,
 144                         (long) history->mf.cia);
 145       return 0;
 146     }
 147   return 1;
 148 }
 149
 150 :function:::int:check_mt_hilo:hilo_history *history
 151 *mipsI,mipsII,mipsIII,mipsIV:
 152 *vr4100:
 153 *vr5000:
 154 // start-sanitize-vr4320
 155 *vr4320:
 156 // end-sanitize-vr4320
 157 // start-sanitize-cygnus
 158 *vr5400:
 159 // end-sanitize-cygnus
 160 {
 161   signed64 time = sim_events_time (SD);
 162   int ok = check_mf_cycles (SD_, history, time, "MT");
 163   history->mt.timestamp = time;
 164   history->mt.cia = CIA;
 165   return ok;
 166 }
 167
 168 :function:::int:check_mt_hilo:hilo_history *history
 169 *r3900:
 170 // start-sanitize-tx19
 171 *tx19:
 172 // end-sanitize-tx19
 173 // start-sanitize-r5900
 174 *r5900:
 175 // end-sanitize-r5900
 176 {
 177   signed64 time = sim_events_time (SD);
 178   history->mt.timestamp = time;
 179   history->mt.cia = CIA;
 180   return 1;
 181 }
 182
 183
 184 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 185 *mipsI,mipsII,mipsIII,mipsIV:
 186 *vr4100:
 187 *vr5000:
 188 // start-sanitize-vr4320
 189 *vr4320:
 190 // end-sanitize-vr4320
 191 // start-sanitize-cygnus
 192 *vr5400:
 193 // end-sanitize-cygnus
 194 *r3900:
 195 // start-sanitize-tx19
 196 *tx19:
 197 // end-sanitize-tx19
 198 {
 199   signed64 time = sim_events_time (SD);
 200   int ok = 1;
 201   if (peer != NULL
 202       && peer->mt.timestamp > history->op.timestamp
 203       && history->mt.timestamp < history->op.timestamp
 204       && ! (history->mf.timestamp > history->op.timestamp
 205             && history->mf.timestamp < peer->mt.timestamp)
 206       && ! (peer->mf.timestamp > history->op.timestamp
 207             && peer->mf.timestamp < peer->mt.timestamp))
 208     {
 209       /* The peer has been written to since the last OP yet we have
 210          not */
 211       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 212                         itable[MY_INDEX].name,
 213                         (long) CIA,
 214                         (long) history->op.cia,
 215                         (long) peer->mt.cia);
 216       ok = 0;
 217     }
 218   history->mf.timestamp = time;
 219   history->mf.cia = CIA;
 220   return ok;
 221 }
 222
 223 // start-sanitize-r5900
 224 // The r5900 mfhi et.al insns _can_ be exectuted immediatly after a div
 225 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 226 // end-sanitize-r5900
 227 // start-sanitize-r5900
 228 *r5900:
 229 // end-sanitize-r5900
 230 // start-sanitize-r5900
 231 {
 232   /* FIXME: could record the fact that a stall occured if we want */
 233   signed64 time = sim_events_time (SD);
 234   history->mf.timestamp = time;
 235   history->mf.cia = CIA;
 236   return 1;
 237 }
 238 // end-sanitize-r5900
 239
 240
 241 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 242 *mipsI,mipsII,mipsIII,mipsIV:
 243 *vr4100:
 244 *vr5000:
 245 // start-sanitize-vr4320
 246 *vr4320:
 247 // end-sanitize-vr4320
 248 // start-sanitize-cygnus
 249 *vr5400:
 250 // end-sanitize-cygnus
 251 {
 252   signed64 time = sim_events_time (SD);
 253   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 254             && check_mf_cycles (SD_, lo, time, "OP"));
 255   hi->op.timestamp = time;
 256   lo->op.timestamp = time;
 257   hi->op.cia = CIA;
 258   lo->op.cia = CIA;
 259   return ok;
 260 }
 261
 262 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 263 // a mf{hi,lo}
 264 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 265 *r3900:
 266 // start-sanitize-tx19
 267 *tx19:
 268 // end-sanitize-tx19
 269 // start-sanitize-r5900
 270 *r5900:
 271 // end-sanitize-r5900
 272 {
 273   /* FIXME: could record the fact that a stall occured if we want */
 274   signed64 time = sim_events_time (SD);
 275   hi->op.timestamp = time;
 276   lo->op.timestamp = time;
 277   hi->op.cia = CIA;
 278   lo->op.cia = CIA;
 279   return 1;
 280 }
 281
 282
 283 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 284 *mipsI,mipsII,mipsIII,mipsIV:
 285 *vr4100:
 286 *vr5000:
 287 // start-sanitize-vr4320
 288 *vr4320:
 289 // end-sanitize-vr4320
 290 // start-sanitize-cygnus
 291 *vr5400:
 292 // end-sanitize-cygnus
 293 *r3900:
 294 // start-sanitize-tx19
 295 *tx19:
 296 // end-sanitize-tx19
 297 {
 298   signed64 time = sim_events_time (SD);
 299   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 300             && check_mf_cycles (SD_, lo, time, "OP"));
 301   hi->op.timestamp = time;
 302   lo->op.timestamp = time;
 303   hi->op.cia = CIA;
 304   lo->op.cia = CIA;
 305   return ok;
 306 }
 307
 308
 309 // start-sanitize-r5900
 310 // The r5900 div et.al insns _can_ be exectuted immediatly after
 311 // a mf{hi,lo}
 312 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 313 // end-sanitize-r5900
 314 // start-sanitize-r5900
 315 *r5900:
 316 // end-sanitize-r5900
 317 // start-sanitize-r5900
 318 {
 319   /* FIXME: could record the fact that a stall occured if we want */
 320   signed64 time = sim_events_time (SD);
 321   hi->op.timestamp = time;
 322   lo->op.timestamp = time;
 323   hi->op.cia = CIA;
 324   lo->op.cia = CIA;
 325   return 1;
 326 }
 327 // end-sanitize-r5900
 328
 329
 330
 331 //
 332 // Mips Architecture:
 333 //
 334 //        CPU Instruction Set (mipsI - mipsIV)
 335 //
 336
 337
 338
 339 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 340 "add r<RD>, r<RS>, r<RT>"
 341 *mipsI,mipsII,mipsIII,mipsIV:
 342 *vr4100:
 343 *vr5000:
 344 // start-sanitize-vr4320
 345 *vr4320:
 346 // end-sanitize-vr4320
 347 // start-sanitize-cygnus
 348 *vr5400:
 349 // end-sanitize-cygnus
 350 // start-sanitize-r5900
 351 *r5900:
 352 // end-sanitize-r5900
 353 *r3900:
 354 // start-sanitize-tx19
 355 *tx19:
 356 // end-sanitize-tx19
 357 {
 358   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 359   {
 360     ALU32_BEGIN (GPR[RS]);
 361     ALU32_ADD (GPR[RT]);
 362     ALU32_END (GPR[RD]);
 363   }
 364   TRACE_ALU_RESULT (GPR[RD]);
 365 }
 366
 367
 368
 369 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 370 "addi r<RT>, r<RS>, IMMEDIATE"
 371 *mipsI,mipsII,mipsIII,mipsIV:
 372 *vr4100:
 373 *vr5000:
 374 // start-sanitize-vr4320
 375 *vr4320:
 376 // end-sanitize-vr4320
 377 // start-sanitize-cygnus
 378 *vr5400:
 379 // end-sanitize-cygnus
 380 // start-sanitize-r5900
 381 *r5900:
 382 // end-sanitize-r5900
 383 *r3900:
 384 // start-sanitize-tx19
 385 *tx19:
 386 // end-sanitize-tx19
 387 {
 388   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 389   {
 390     ALU32_BEGIN (GPR[RS]);
 391     ALU32_ADD (EXTEND16 (IMMEDIATE));
 392     ALU32_END (GPR[RT]);
 393   }
 394   TRACE_ALU_RESULT (GPR[RT]);
 395 }
 396
 397
 398
 399 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 400 {
 401   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 402   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 403   TRACE_ALU_RESULT (GPR[rt]);
 404 }
 405
 406 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 407 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 408 *mipsI,mipsII,mipsIII,mipsIV:
 409 *vr4100:
 410 *vr5000:
 411 // start-sanitize-vr4320
 412 *vr4320:
 413 // end-sanitize-vr4320
 414 // start-sanitize-cygnus
 415 *vr5400:
 416 // end-sanitize-cygnus
 417 // start-sanitize-r5900
 418 *r5900:
 419 // end-sanitize-r5900
 420 *r3900:
 421 // start-sanitize-tx19
 422 *tx19:
 423 // end-sanitize-tx19
 424 {
 425   do_addiu (SD_, RS, RT, IMMEDIATE);
 426 }
 427
 428
 429
 430 :function:::void:do_addu:int rs, int rt, int rd
 431 {
 432   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 433   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 434   TRACE_ALU_RESULT (GPR[rd]);
 435 }
 436
 437 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 438 "addu r<RD>, r<RS>, r<RT>"
 439 *mipsI,mipsII,mipsIII,mipsIV:
 440 *vr4100:
 441 *vr5000:
 442 // start-sanitize-vr4320
 443 *vr4320:
 444 // end-sanitize-vr4320
 445 // start-sanitize-cygnus
 446 *vr5400:
 447 // end-sanitize-cygnus
 448 // start-sanitize-r5900
 449 *r5900:
 450 // end-sanitize-r5900
 451 *r3900:
 452 // start-sanitize-tx19
 453 *tx19:
 454 // end-sanitize-tx19
 455 {
 456   do_addu (SD_, RS, RT, RD);
 457 }
 458
 459
 460
 461 :function:::void:do_and:int rs, int rt, int rd
 462 {
 463   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 464   GPR[rd] = GPR[rs] & GPR[rt];
 465   TRACE_ALU_RESULT (GPR[rd]);
 466 }
 467
 468 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 469 "and r<RD>, r<RS>, r<RT>"
 470 *mipsI,mipsII,mipsIII,mipsIV:
 471 *vr4100:
 472 *vr5000:
 473 // start-sanitize-vr4320
 474 *vr4320:
 475 // end-sanitize-vr4320
 476 // start-sanitize-cygnus
 477 *vr5400:
 478 // end-sanitize-cygnus
 479 // start-sanitize-r5900
 480 *r5900:
 481 // end-sanitize-r5900
 482 *r3900:
 483 // start-sanitize-tx19
 484 *tx19:
 485 // end-sanitize-tx19
 486 {
 487   do_and (SD_, RS, RT, RD);
 488 }
 489
 490
 491
 492 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 493 "and r<RT>, r<RS>, <IMMEDIATE>"
 494 *mipsI,mipsII,mipsIII,mipsIV:
 495 *vr4100:
 496 *vr5000:
 497 // start-sanitize-vr4320
 498 *vr4320:
 499 // end-sanitize-vr4320
 500 // start-sanitize-cygnus
 501 *vr5400:
 502 // end-sanitize-cygnus
 503 // start-sanitize-r5900
 504 *r5900:
 505 // end-sanitize-r5900
 506 *r3900:
 507 // start-sanitize-tx19
 508 *tx19:
 509 // end-sanitize-tx19
 510 {
 511   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 512   GPR[RT] = GPR[RS] & IMMEDIATE;
 513   TRACE_ALU_RESULT (GPR[RT]);
 514 }
 515
 516
 517
 518 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 519 "beq r<RS>, r<RT>, <OFFSET>"
 520 *mipsI,mipsII,mipsIII,mipsIV:
 521 *vr4100:
 522 *vr5000:
 523 // start-sanitize-vr4320
 524 *vr4320:
 525 // end-sanitize-vr4320
 526 // start-sanitize-cygnus
 527 *vr5400:
 528 // end-sanitize-cygnus
 529 // start-sanitize-r5900
 530 *r5900:
 531 // end-sanitize-r5900
 532 *r3900:
 533 // start-sanitize-tx19
 534 *tx19:
 535 // end-sanitize-tx19
 536 {
 537   address_word offset = EXTEND16 (OFFSET) << 2;
 538   check_branch_bug ();
 539   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 540     {
 541       mark_branch_bug (NIA+offset);
 542       DELAY_SLOT (NIA + offset);
 543     }
 544 }
 545
 546
 547
 548 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 549 "beql r<RS>, r<RT>, <OFFSET>"
 550 *mipsII:
 551 *mipsIII:
 552 *mipsIV:
 553 *vr4100:
 554 *vr5000:
 555 // start-sanitize-vr4320
 556 *vr4320:
 557 // end-sanitize-vr4320
 558 // start-sanitize-cygnus
 559 *vr5400:
 560 // end-sanitize-cygnus
 561 // start-sanitize-r5900
 562 *r5900:
 563 // end-sanitize-r5900
 564 *r3900:
 565 // start-sanitize-tx19
 566 *tx19:
 567 // end-sanitize-tx19
 568 {
 569   address_word offset = EXTEND16 (OFFSET) << 2;
 570   check_branch_bug ();
 571   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 572     {
 573       mark_branch_bug (NIA+offset);
 574       DELAY_SLOT (NIA + offset);
 575     }
 576   else
 577     NULLIFY_NEXT_INSTRUCTION ();
 578 }
 579
 580
 581
 582 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 583 "bgez r<RS>, <OFFSET>"
 584 *mipsI,mipsII,mipsIII,mipsIV:
 585 *vr4100:
 586 *vr5000:
 587 // start-sanitize-vr4320
 588 *vr4320:
 589 // end-sanitize-vr4320
 590 // start-sanitize-cygnus
 591 *vr5400:
 592 // end-sanitize-cygnus
 593 // start-sanitize-r5900
 594 *r5900:
 595 // end-sanitize-r5900
 596 *r3900:
 597 // start-sanitize-tx19
 598 *tx19:
 599 // end-sanitize-tx19
 600 {
 601   address_word offset = EXTEND16 (OFFSET) << 2;
 602   check_branch_bug ();
 603   if ((signed_word) GPR[RS] >= 0)
 604     {
 605       mark_branch_bug (NIA+offset);
 606       DELAY_SLOT (NIA + offset);
 607     }
 608 }
 609
 610
 611
 612 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 613 "bgezal r<RS>, <OFFSET>"
 614 *mipsI,mipsII,mipsIII,mipsIV:
 615 *vr4100:
 616 *vr5000:
 617 // start-sanitize-vr4320
 618 *vr4320:
 619 // end-sanitize-vr4320
 620 // start-sanitize-cygnus
 621 *vr5400:
 622 // end-sanitize-cygnus
 623 // start-sanitize-r5900
 624 *r5900:
 625 // end-sanitize-r5900
 626 *r3900:
 627 // start-sanitize-tx19
 628 *tx19:
 629 // end-sanitize-tx19
 630 {
 631   address_word offset = EXTEND16 (OFFSET) << 2;
 632   check_branch_bug ();
 633   RA = (CIA + 8);
 634   if ((signed_word) GPR[RS] >= 0)
 635     {
 636       mark_branch_bug (NIA+offset);
 637       DELAY_SLOT (NIA + offset);
 638     }
 639 }
 640
 641
 642
 643 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 644 "bgezall r<RS>, <OFFSET>"
 645 *mipsII:
 646 *mipsIII:
 647 *mipsIV:
 648 *vr4100:
 649 *vr5000:
 650 // start-sanitize-vr4320
 651 *vr4320:
 652 // end-sanitize-vr4320
 653 // start-sanitize-cygnus
 654 *vr5400:
 655 // end-sanitize-cygnus
 656 // start-sanitize-r5900
 657 *r5900:
 658 // end-sanitize-r5900
 659 *r3900:
 660 // start-sanitize-tx19
 661 *tx19:
 662 // end-sanitize-tx19
 663 {
 664   address_word offset = EXTEND16 (OFFSET) << 2;
 665   check_branch_bug ();
 666   RA = (CIA + 8);
 667   /* NOTE: The branch occurs AFTER the next instruction has been
 668      executed */
 669   if ((signed_word) GPR[RS] >= 0)
 670     {
 671       mark_branch_bug (NIA+offset);
 672       DELAY_SLOT (NIA + offset);
 673     }
 674   else
 675     NULLIFY_NEXT_INSTRUCTION ();
 676 }
 677
 678
 679
 680 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 681 "bgezl r<RS>, <OFFSET>"
 682 *mipsII:
 683 *mipsIII:
 684 *mipsIV:
 685 *vr4100:
 686 *vr5000:
 687 // start-sanitize-vr4320
 688 *vr4320:
 689 // end-sanitize-vr4320
 690 // start-sanitize-cygnus
 691 *vr5400:
 692 // end-sanitize-cygnus
 693 // start-sanitize-r5900
 694 *r5900:
 695 // end-sanitize-r5900
 696 *r3900:
 697 // start-sanitize-tx19
 698 *tx19:
 699 // end-sanitize-tx19
 700 {
 701   address_word offset = EXTEND16 (OFFSET) << 2;
 702   check_branch_bug ();
 703   if ((signed_word) GPR[RS] >= 0)
 704     {
 705       mark_branch_bug (NIA+offset);
 706       DELAY_SLOT (NIA + offset);
 707     }
 708   else
 709     NULLIFY_NEXT_INSTRUCTION ();
 710 }
 711
 712
 713
 714 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 715 "bgtz r<RS>, <OFFSET>"
 716 *mipsI,mipsII,mipsIII,mipsIV:
 717 *vr4100:
 718 *vr5000:
 719 // start-sanitize-vr4320
 720 *vr4320:
 721 // end-sanitize-vr4320
 722 // start-sanitize-cygnus
 723 *vr5400:
 724 // end-sanitize-cygnus
 725 // start-sanitize-r5900
 726 *r5900:
 727 // end-sanitize-r5900
 728 *r3900:
 729 // start-sanitize-tx19
 730 *tx19:
 731 // end-sanitize-tx19
 732 {
 733   address_word offset = EXTEND16 (OFFSET) << 2;
 734   check_branch_bug ();
 735   if ((signed_word) GPR[RS] > 0)
 736     {
 737       mark_branch_bug (NIA+offset);
 738       DELAY_SLOT (NIA + offset);
 739     }
 740 }
 741
 742
 743
 744 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 745 "bgtzl r<RS>, <OFFSET>"
 746 *mipsII:
 747 *mipsIII:
 748 *mipsIV:
 749 *vr4100:
 750 *vr5000:
 751 // start-sanitize-vr4320
 752 *vr4320:
 753 // end-sanitize-vr4320
 754 // start-sanitize-cygnus
 755 *vr5400:
 756 // end-sanitize-cygnus
 757 // start-sanitize-r5900
 758 *r5900:
 759 // end-sanitize-r5900
 760 *r3900:
 761 // start-sanitize-tx19
 762 *tx19:
 763 // end-sanitize-tx19
 764 {
 765   address_word offset = EXTEND16 (OFFSET) << 2;
 766   check_branch_bug ();
 767   /* NOTE: The branch occurs AFTER the next instruction has been
 768      executed */
 769   if ((signed_word) GPR[RS] > 0)
 770     {
 771       mark_branch_bug (NIA+offset);
 772       DELAY_SLOT (NIA + offset);
 773     }
 774   else
 775     NULLIFY_NEXT_INSTRUCTION ();
 776 }
 777
 778
 779
 780 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 781 "blez r<RS>, <OFFSET>"
 782 *mipsI,mipsII,mipsIII,mipsIV:
 783 *vr4100:
 784 *vr5000:
 785 // start-sanitize-vr4320
 786 *vr4320:
 787 // end-sanitize-vr4320
 788 // start-sanitize-cygnus
 789 *vr5400:
 790 // end-sanitize-cygnus
 791 // start-sanitize-r5900
 792 *r5900:
 793 // end-sanitize-r5900
 794 *r3900:
 795 // start-sanitize-tx19
 796 *tx19:
 797 // end-sanitize-tx19
 798 {
 799   address_word offset = EXTEND16 (OFFSET) << 2;
 800   check_branch_bug ();
 801   /* NOTE: The branch occurs AFTER the next instruction has been
 802      executed */
 803   if ((signed_word) GPR[RS] <= 0)
 804     {
 805       mark_branch_bug (NIA+offset);
 806       DELAY_SLOT (NIA + offset);
 807     }
 808 }
 809
 810
 811
 812 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 813 "bgezl r<RS>, <OFFSET>"
 814 *mipsII:
 815 *mipsIII:
 816 *mipsIV:
 817 *vr4100:
 818 *vr5000:
 819 // start-sanitize-vr4320
 820 *vr4320:
 821 // end-sanitize-vr4320
 822 // start-sanitize-cygnus
 823 *vr5400:
 824 // end-sanitize-cygnus
 825 // start-sanitize-r5900
 826 *r5900:
 827 // end-sanitize-r5900
 828 *r3900:
 829 // start-sanitize-tx19
 830 *tx19:
 831 // end-sanitize-tx19
 832 {
 833   address_word offset = EXTEND16 (OFFSET) << 2;
 834   check_branch_bug ();
 835   if ((signed_word) GPR[RS] <= 0)
 836     {
 837       mark_branch_bug (NIA+offset);
 838       DELAY_SLOT (NIA + offset);
 839     }
 840   else
 841     NULLIFY_NEXT_INSTRUCTION ();
 842 }
 843
 844
 845
 846 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 847 "bltz r<RS>, <OFFSET>"
 848 *mipsI,mipsII,mipsIII,mipsIV:
 849 *vr4100:
 850 *vr5000:
 851 // start-sanitize-vr4320
 852 *vr4320:
 853 // end-sanitize-vr4320
 854 // start-sanitize-cygnus
 855 *vr5400:
 856 // end-sanitize-cygnus
 857 // start-sanitize-r5900
 858 *r5900:
 859 // end-sanitize-r5900
 860 *r3900:
 861 // start-sanitize-tx19
 862 *tx19:
 863 // end-sanitize-tx19
 864 {
 865   address_word offset = EXTEND16 (OFFSET) << 2;
 866   check_branch_bug ();
 867   if ((signed_word) GPR[RS] < 0)
 868     {
 869       mark_branch_bug (NIA+offset);
 870       DELAY_SLOT (NIA + offset);
 871     }
 872 }
 873
 874
 875
 876 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 877 "bltzal r<RS>, <OFFSET>"
 878 *mipsI,mipsII,mipsIII,mipsIV:
 879 *vr4100:
 880 *vr5000:
 881 // start-sanitize-vr4320
 882 *vr4320:
 883 // end-sanitize-vr4320
 884 // start-sanitize-cygnus
 885 *vr5400:
 886 // end-sanitize-cygnus
 887 // start-sanitize-r5900
 888 *r5900:
 889 // end-sanitize-r5900
 890 *r3900:
 891 // start-sanitize-tx19
 892 *tx19:
 893 // end-sanitize-tx19
 894 {
 895   address_word offset = EXTEND16 (OFFSET) << 2;
 896   check_branch_bug ();
 897   RA = (CIA + 8);
 898   /* NOTE: The branch occurs AFTER the next instruction has been
 899      executed */
 900   if ((signed_word) GPR[RS] < 0)
 901     {
 902       mark_branch_bug (NIA+offset);
 903       DELAY_SLOT (NIA + offset);
 904     }
 905 }
 906
 907
 908
 909 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 910 "bltzall r<RS>, <OFFSET>"
 911 *mipsII:
 912 *mipsIII:
 913 *mipsIV:
 914 *vr4100:
 915 *vr5000:
 916 // start-sanitize-vr4320
 917 *vr4320:
 918 // end-sanitize-vr4320
 919 // start-sanitize-cygnus
 920 *vr5400:
 921 // end-sanitize-cygnus
 922 // start-sanitize-r5900
 923 *r5900:
 924 // end-sanitize-r5900
 925 *r3900:
 926 // start-sanitize-tx19
 927 *tx19:
 928 // end-sanitize-tx19
 929 {
 930   address_word offset = EXTEND16 (OFFSET) << 2;
 931   check_branch_bug ();
 932   RA = (CIA + 8);
 933   if ((signed_word) GPR[RS] < 0)
 934     {
 935       mark_branch_bug (NIA+offset);
 936       DELAY_SLOT (NIA + offset);
 937     }
 938   else
 939     NULLIFY_NEXT_INSTRUCTION ();
 940 }
 941
 942
 943
 944 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 945 "bltzl r<RS>, <OFFSET>"
 946 *mipsII:
 947 *mipsIII:
 948 *mipsIV:
 949 *vr4100:
 950 *vr5000:
 951 // start-sanitize-vr4320
 952 *vr4320:
 953 // end-sanitize-vr4320
 954 // start-sanitize-cygnus
 955 *vr5400:
 956 // end-sanitize-cygnus
 957 // start-sanitize-r5900
 958 *r5900:
 959 // end-sanitize-r5900
 960 *r3900:
 961 // start-sanitize-tx19
 962 *tx19:
 963 // end-sanitize-tx19
 964 {
 965   address_word offset = EXTEND16 (OFFSET) << 2;
 966   check_branch_bug ();
 967   /* NOTE: The branch occurs AFTER the next instruction has been
 968      executed */
 969   if ((signed_word) GPR[RS] < 0)
 970     {
 971       mark_branch_bug (NIA+offset);
 972       DELAY_SLOT (NIA + offset);
 973     }
 974   else
 975     NULLIFY_NEXT_INSTRUCTION ();
 976 }
 977
 978
 979
 980 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 981 "bne r<RS>, r<RT>, <OFFSET>"
 982 *mipsI,mipsII,mipsIII,mipsIV:
 983 *vr4100:
 984 *vr5000:
 985 // start-sanitize-vr4320
 986 *vr4320:
 987 // end-sanitize-vr4320
 988 // start-sanitize-cygnus
 989 *vr5400:
 990 // end-sanitize-cygnus
 991 // start-sanitize-r5900
 992 *r5900:
 993 // end-sanitize-r5900
 994 *r3900:
 995 // start-sanitize-tx19
 996 *tx19:
 997 // end-sanitize-tx19
 998 {
 999   address_word offset = EXTEND16 (OFFSET) << 2;
1000   check_branch_bug ();
1001   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1002     {
1003       mark_branch_bug (NIA+offset);
1004       DELAY_SLOT (NIA + offset);
1005     }
1006 }
1007
1008
1009
1010 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1011 "bnel r<RS>, r<RT>, <OFFSET>"
1012 *mipsII:
1013 *mipsIII:
1014 *mipsIV:
1015 *vr4100:
1016 *vr5000:
1017 // start-sanitize-vr4320
1018 *vr4320:
1019 // end-sanitize-vr4320
1020 // start-sanitize-cygnus
1021 *vr5400:
1022 // end-sanitize-cygnus
1023 // start-sanitize-r5900
1024 *r5900:
1025 // end-sanitize-r5900
1026 *r3900:
1027 // start-sanitize-tx19
1028 *tx19:
1029 // end-sanitize-tx19
1030 {
1031   address_word offset = EXTEND16 (OFFSET) << 2;
1032   check_branch_bug ();
1033   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1034     {
1035       mark_branch_bug (NIA+offset);
1036       DELAY_SLOT (NIA + offset);
1037     }
1038   else
1039     NULLIFY_NEXT_INSTRUCTION ();
1040 }
1041
1042
1043
1044 000000,20.CODE,001101:SPECIAL:32::BREAK
1045 "break"
1046 *mipsI,mipsII,mipsIII,mipsIV:
1047 *vr4100:
1048 *vr5000:
1049 // start-sanitize-vr4320
1050 *vr4320:
1051 // end-sanitize-vr4320
1052 // start-sanitize-cygnus
1053 *vr5400:
1054 // end-sanitize-cygnus
1055 // start-sanitize-r5900
1056 *r5900:
1057 // end-sanitize-r5900
1058 *r3900:
1059 // start-sanitize-tx19
1060 *tx19:
1061 // end-sanitize-tx19
1062 {
1063   /* Check for some break instruction which are reserved for use by the simulator.  */
1064   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1065   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1066       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1067     {
1068       sim_engine_halt (SD, CPU, NULL, cia,
1069                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1070     }
1071   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1072            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1073     {
1074       if (STATE & simDELAYSLOT)
1075         PC = cia - 4; /* reference the branch instruction */
1076       else
1077         PC = cia;
1078       sim_engine_halt (SD, CPU, NULL, cia, sim_stopped, SIM_SIGTRAP);
1079     }
1080 // start-sanitize-sky
1081 #ifdef TARGET_SKY
1082   else if (break_code == (HALT_INSTRUCTION_PASS & HALT_INSTRUCTION_MASK))
1083     {
1084       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 0);
1085     }
1086   else if (break_code == (HALT_INSTRUCTION_FAIL & HALT_INSTRUCTION_MASK))
1087     {
1088       sim_engine_halt (SD, CPU, NULL, cia, sim_exited, 15);
1089     }
1090   else if (break_code == (PRINTF_INSTRUCTION & HALT_INSTRUCTION_MASK))
1091     {
1092       sim_monitor(SD, CPU, cia, 316);   /* Magic number for idt printf routine. */
1093     }
1094   else if (break_code == (LOAD_INSTRUCTION & HALT_INSTRUCTION_MASK))
1095     {
1096       /* This is a multi-phase load instruction.  Load next configured
1097          executable and return its starting PC in A0 ($4). */
1098
1099       if (STATE_MLOAD_INDEX (SD) == STATE_MLOAD_COUNT (SD))
1100         {
1101           sim_io_eprintf (SD, "Cannot load program %d.  Not enough load-next options.\n",
1102                           STATE_MLOAD_COUNT (SD));
1103           A0 = 0;
1104         }
1105       else
1106         {
1107           char* next = STATE_MLOAD_NAME (SD) [STATE_MLOAD_INDEX (SD)];
1108           SIM_RC rc;
1109
1110           STATE_MLOAD_INDEX (SD) ++;
1111
1112           /* call sim_load_file, preserving most previous state */
1113           rc = sim_load (SD, next, NULL, 0);
1114           if(rc != SIM_RC_OK)
1115             {
1116               sim_io_eprintf (SD, "Error during multi-phase load #%d.\n",
1117                               STATE_MLOAD_INDEX (SD));
1118               A0 = 0;
1119             }
1120           else
1121             A0 = STATE_START_ADDR (SD);
1122         }
1123     }
1124 #endif TARGET_SKY
1125 // end-sanitize-sky
1126
1127   else
1128     {
1129       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1130          the exception. */
1131       SignalException(BreakPoint, instruction_0);
1132     }
1133 }
1134
1135
1136
1137
1138
1139
1140 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1141 "dadd r<RD>, r<RS>, r<RT>"
1142 *mipsIII:
1143 *mipsIV:
1144 *vr4100:
1145 *vr5000:
1146 // start-sanitize-vr4320
1147 *vr4320:
1148 // end-sanitize-vr4320
1149 // start-sanitize-cygnus
1150 *vr5400:
1151 // end-sanitize-cygnus
1152 // start-sanitize-r5900
1153 *r5900:
1154 // end-sanitize-r5900
1155 // start-sanitize-tx19
1156 *tx19:
1157 // end-sanitize-tx19
1158 {
1159   /* this check's for overflow */
1160   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1161   {
1162     ALU64_BEGIN (GPR[RS]);
1163     ALU64_ADD (GPR[RT]);
1164     ALU64_END (GPR[RD]);
1165   }
1166   TRACE_ALU_RESULT (GPR[RD]);
1167 }
1168
1169
1170
1171 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1172 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1173 *mipsIII:
1174 *mipsIV:
1175 *vr4100:
1176 *vr5000:
1177 // start-sanitize-vr4320
1178 *vr4320:
1179 // end-sanitize-vr4320
1180 // start-sanitize-cygnus
1181 *vr5400:
1182 // end-sanitize-cygnus
1183 // start-sanitize-r5900
1184 *r5900:
1185 // end-sanitize-r5900
1186 // start-sanitize-tx19
1187 *tx19:
1188 // end-sanitize-tx19
1189 {
1190   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1191   {
1192     ALU64_BEGIN (GPR[RS]);
1193     ALU64_ADD (EXTEND16 (IMMEDIATE));
1194     ALU64_END (GPR[RT]);
1195   }
1196   TRACE_ALU_RESULT (GPR[RT]);
1197 }
1198
1199
1200
1201 :function:64::void:do_daddiu:int rs, int rt, unsigned16 immediate
1202 {
1203   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1204   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1205   TRACE_ALU_RESULT (GPR[rt]);
1206 }
1207
1208 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1209 "daddu r<RT>, r<RS>, <IMMEDIATE>"
1210 *mipsIII:
1211 *mipsIV:
1212 *vr4100:
1213 *vr5000:
1214 // start-sanitize-vr4320
1215 *vr4320:
1216 // end-sanitize-vr4320
1217 // start-sanitize-cygnus
1218 *vr5400:
1219 // end-sanitize-cygnus
1220 // start-sanitize-r5900
1221 *r5900:
1222 // end-sanitize-r5900
1223 // start-sanitize-tx19
1224 *tx19:
1225 // end-sanitize-tx19
1226 {
1227   do_daddiu (SD_, RS, RT, IMMEDIATE);
1228 }
1229
1230
1231
1232 :function:::void:do_daddu:int rs, int rt, int rd
1233 {
1234   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1235   GPR[rd] = GPR[rs] + GPR[rt];
1236   TRACE_ALU_RESULT (GPR[rd]);
1237 }
1238
1239 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1240 "daddu r<RD>, r<RS>, r<RT>"
1241 *mipsIII:
1242 *mipsIV:
1243 *vr4100:
1244 *vr5000:
1245 // start-sanitize-vr4320
1246 *vr4320:
1247 // end-sanitize-vr4320
1248 // start-sanitize-cygnus
1249 *vr5400:
1250 // end-sanitize-cygnus
1251 // start-sanitize-r5900
1252 *r5900:
1253 // end-sanitize-r5900
1254 // start-sanitize-tx19
1255 *tx19:
1256 // end-sanitize-tx19
1257 {
1258   do_daddu (SD_, RS, RT, RD);
1259 }
1260
1261
1262
1263 :function:64::void:do_ddiv:int rs, int rt
1264 {
1265   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1266   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1267   {
1268     signed64 n = GPR[rs];
1269     signed64 d = GPR[rt];
1270     if (d == 0)
1271       {
1272         LO = SIGNED64 (0x8000000000000000);
1273         HI = 0;
1274       }
1275     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1276       {
1277         LO = SIGNED64 (0x8000000000000000);
1278         HI = 0;
1279       }
1280     else
1281       {
1282         LO = (n / d);
1283         HI = (n % d);
1284       }
1285   }
1286   TRACE_ALU_RESULT2 (HI, LO);
1287 }
1288
1289 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
1290 "ddiv r<RS>, r<RT>"
1291 *mipsIII:
1292 *mipsIV:
1293 *vr4100:
1294 *vr5000:
1295 // start-sanitize-vr4320
1296 *vr4320:
1297 // end-sanitize-vr4320
1298 // start-sanitize-cygnus
1299 *vr5400:
1300 // end-sanitize-cygnus
1301 // start-sanitize-r5900
1302 *r5900:
1303 // end-sanitize-r5900
1304 // start-sanitize-tx19
1305 *tx19:
1306 // end-sanitize-tx19
1307 {
1308   do_ddiv (SD_, RS, RT);
1309 }
1310
1311
1312
1313 :function:64::void:do_ddivu:int rs, int rt
1314 {
1315   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1316   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1317   {
1318     unsigned64 n = GPR[rs];
1319     unsigned64 d = GPR[rt];
1320     if (d == 0)
1321       {
1322         LO = SIGNED64 (0x8000000000000000);
1323         HI = 0;
1324       }
1325     else
1326       {
1327         LO = (n / d);
1328         HI = (n % d);
1329       }
1330   }
1331   TRACE_ALU_RESULT2 (HI, LO);
1332 }
1333
1334 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1335 "ddivu r<RS>, r<RT>"
1336 *mipsIII:
1337 *mipsIV:
1338 *vr4100:
1339 *vr5000:
1340 // start-sanitize-vr4320
1341 *vr4320:
1342 // end-sanitize-vr4320
1343 // start-sanitize-cygnus
1344 *vr5400:
1345 // end-sanitize-cygnus
1346 // start-sanitize-tx19
1347 *tx19:
1348 // end-sanitize-tx19
1349 {
1350   do_ddivu (SD_, RS, RT);
1351 }
1352
1353
1354
1355 :function:::void:do_div:int rs, int rt
1356 {
1357   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1358   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1359   {
1360     signed32 n = GPR[rs];
1361     signed32 d = GPR[rt];
1362     if (d == 0)
1363       {
1364         LO = EXTEND32 (0x80000000);
1365         HI = EXTEND32 (0);
1366       }
1367     else if (n == SIGNED32 (0x80000000) && d == -1)
1368       {
1369         LO = EXTEND32 (0x80000000);
1370         HI = EXTEND32 (0);
1371       }
1372     else
1373       {
1374         LO = EXTEND32 (n / d);
1375         HI = EXTEND32 (n % d);
1376       }
1377   }
1378   TRACE_ALU_RESULT2 (HI, LO);
1379 }
1380
1381 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
1382 "div r<RS>, r<RT>"
1383 *mipsI,mipsII,mipsIII,mipsIV:
1384 *vr4100:
1385 *vr5000:
1386 // start-sanitize-vr4320
1387 *vr4320:
1388 // end-sanitize-vr4320
1389 // start-sanitize-cygnus
1390 *vr5400:
1391 // end-sanitize-cygnus
1392 // start-sanitize-r5900
1393 *r5900:
1394 // end-sanitize-r5900
1395 *r3900:
1396 // start-sanitize-tx19
1397 *tx19:
1398 // end-sanitize-tx19
1399 {
1400   do_div (SD_, RS, RT);
1401 }
1402
1403
1404
1405 :function:::void:do_divu:int rs, int rt
1406 {
1407   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1408   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1409   {
1410     unsigned32 n = GPR[rs];
1411     unsigned32 d = GPR[rt];
1412     if (d == 0)
1413       {
1414         LO = EXTEND32 (0x80000000);
1415         HI = EXTEND32 (0);
1416       }
1417    else
1418      {
1419        LO = EXTEND32 (n / d);
1420        HI = EXTEND32 (n % d);
1421      }
1422   }
1423   TRACE_ALU_RESULT2 (HI, LO);
1424 }
1425
1426 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
1427 "divu r<RS>, r<RT>"
1428 *mipsI,mipsII,mipsIII,mipsIV:
1429 *vr4100:
1430 *vr5000:
1431 // start-sanitize-vr4320
1432 *vr4320:
1433 // end-sanitize-vr4320
1434 // start-sanitize-cygnus
1435 *vr5400:
1436 // end-sanitize-cygnus
1437 // start-sanitize-r5900
1438 *r5900:
1439 // end-sanitize-r5900
1440 *r3900:
1441 // start-sanitize-tx19
1442 *tx19:
1443 // end-sanitize-tx19
1444 {
1445   do_divu (SD_, RS, RT);
1446 }
1447
1448
1449
1450 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1451 {
1452   unsigned64 lo;
1453   unsigned64 hi;
1454   unsigned64 m00;
1455   unsigned64 m01;
1456   unsigned64 m10;
1457   unsigned64 m11;
1458   unsigned64 mid;
1459   int sign;
1460   unsigned64 op1 = GPR[rs];
1461   unsigned64 op2 = GPR[rt];
1462   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1463   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1464   /* make signed multiply unsigned */
1465   sign = 0;
1466   if (signed_p)
1467     {
1468       if (op1 < 0)
1469         {
1470           op1 = - op1;
1471           ++sign;
1472         }
1473       if (op2 < 0)
1474         {
1475           op2 = - op2;
1476           ++sign;
1477         }
1478     }
1479   /* multuply out the 4 sub products */
1480   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1481   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1482   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1483   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1484   /* add the products */
1485   mid = ((unsigned64) VH4_8 (m00)
1486          + (unsigned64) VL4_8 (m10)
1487          + (unsigned64) VL4_8 (m01));
1488   lo = U8_4 (mid, m00);
1489   hi = (m11
1490         + (unsigned64) VH4_8 (mid)
1491         + (unsigned64) VH4_8 (m01)
1492         + (unsigned64) VH4_8 (m10));
1493   /* fix the sign */
1494   if (sign & 1)
1495     {
1496       lo = -lo;
1497       if (lo == 0)
1498         hi = -hi;
1499       else
1500         hi = -hi - 1;
1501     }
1502   /* save the result HI/LO (and a gpr) */
1503   LO = lo;
1504   HI = hi;
1505   if (rd != 0)
1506     GPR[rd] = lo;
1507   TRACE_ALU_RESULT2 (HI, LO);
1508 }
1509
1510 :function:::void:do_dmult:int rs, int rt, int rd
1511 {
1512   do_dmultx (SD_, rs, rt, rd, 1);
1513 }
1514
1515 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
1516 "dmult r<RS>, r<RT>"
1517 *mipsIII,mipsIV:
1518 *vr4100:
1519 // start-sanitize-tx19
1520 *tx19:
1521 // end-sanitize-tx19
1522 // start-sanitize-vr4320
1523 *vr4320:
1524 // end-sanitize-vr4320
1525 {
1526   do_dmult (SD_, RS, RT, 0);
1527 }
1528
1529 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1530 "dmult r<RS>, r<RT>":RD == 0
1531 "dmult r<RD>, r<RS>, r<RT>"
1532 *vr5000:
1533 // start-sanitize-cygnus
1534 *vr5400:
1535 // end-sanitize-cygnus
1536 {
1537   do_dmult (SD_, RS, RT, RD);
1538 }
1539
1540
1541
1542 :function:::void:do_dmultu:int rs, int rt, int rd
1543 {
1544   do_dmultx (SD_, rs, rt, rd, 0);
1545 }
1546
1547 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1548 "dmultu r<RS>, r<RT>"
1549 *mipsIII,mipsIV:
1550 *vr4100:
1551 // start-sanitize-tx19
1552 *tx19:
1553 // end-sanitize-tx19
1554 // start-sanitize-vr4320
1555 *vr4320:
1556 // end-sanitize-vr4320
1557 {
1558   do_dmultu (SD_, RS, RT, 0);
1559 }
1560
1561 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1562 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1563 "dmultu r<RS>, r<RT>"
1564 *vr5000:
1565 // start-sanitize-cygnus
1566 *vr5400:
1567 // end-sanitize-cygnus
1568 {
1569   do_dmultu (SD_, RS, RT, RD);
1570 }
1571
1572
1573
1574 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1575 "dsll r<RD>, r<RT>, <SHIFT>"
1576 *mipsIII:
1577 *mipsIV:
1578 *vr4100:
1579 *vr5000:
1580 // start-sanitize-vr4320
1581 *vr4320:
1582 // end-sanitize-vr4320
1583 // start-sanitize-cygnus
1584 *vr5400:
1585 // end-sanitize-cygnus
1586 // start-sanitize-r5900
1587 *r5900:
1588 // end-sanitize-r5900
1589 // start-sanitize-tx19
1590 *tx19:
1591 // end-sanitize-tx19
1592 {
1593   int s = SHIFT;
1594   GPR[RD] = GPR[RT] << s;
1595 }
1596
1597
1598 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1599 "dsll32 r<RD>, r<RT>, <SHIFT>"
1600 *mipsIII:
1601 *mipsIV:
1602 *vr4100:
1603 *vr5000:
1604 // start-sanitize-vr4320
1605 *vr4320:
1606 // end-sanitize-vr4320
1607 // start-sanitize-cygnus
1608 *vr5400:
1609 // end-sanitize-cygnus
1610 // start-sanitize-r5900
1611 *r5900:
1612 // end-sanitize-r5900
1613 // start-sanitize-tx19
1614 *tx19:
1615 // end-sanitize-tx19
1616 {
1617   int s = 32 + SHIFT;
1618   GPR[RD] = GPR[RT] << s;
1619 }
1620
1621
1622
1623 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1624 "dsllv r<RD>, r<RT>, r<RS>"
1625 *mipsIII:
1626 *mipsIV:
1627 *vr4100:
1628 *vr5000:
1629 // start-sanitize-vr4320
1630 *vr4320:
1631 // end-sanitize-vr4320
1632 // start-sanitize-cygnus
1633 *vr5400:
1634 // end-sanitize-cygnus
1635 // start-sanitize-r5900
1636 *r5900:
1637 // end-sanitize-r5900
1638 // start-sanitize-tx19
1639 *tx19:
1640 // end-sanitize-tx19
1641 {
1642   int s = MASKED64 (GPR[RS], 5, 0);
1643   GPR[RD] = GPR[RT] << s;
1644 }
1645
1646
1647
1648 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1649 "dsra r<RD>, r<RT>, <SHIFT>"
1650 *mipsIII:
1651 *mipsIV:
1652 *vr4100:
1653 *vr5000:
1654 // start-sanitize-vr4320
1655 *vr4320:
1656 // end-sanitize-vr4320
1657 // start-sanitize-cygnus
1658 *vr5400:
1659 // end-sanitize-cygnus
1660 // start-sanitize-r5900
1661 *r5900:
1662 // end-sanitize-r5900
1663 // start-sanitize-tx19
1664 *tx19:
1665 // end-sanitize-tx19
1666 {
1667   int s = SHIFT;
1668   GPR[RD] = ((signed64) GPR[RT]) >> s;
1669 }
1670
1671
1672 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1673 "dsra32 r<RT>, r<RD>, <SHIFT>"
1674 *mipsIII:
1675 *mipsIV:
1676 *vr4100:
1677 *vr5000:
1678 // start-sanitize-vr4320
1679 *vr4320:
1680 // end-sanitize-vr4320
1681 // start-sanitize-cygnus
1682 *vr5400:
1683 // end-sanitize-cygnus
1684 // start-sanitize-r5900
1685 *r5900:
1686 // end-sanitize-r5900
1687 // start-sanitize-tx19
1688 *tx19:
1689 // end-sanitize-tx19
1690 {
1691   int s = 32 + SHIFT;
1692   GPR[RD] = ((signed64) GPR[RT]) >> s;
1693 }
1694
1695
1696 :function:::void:do_dsrav:int rs, int rt, int rd
1697 {
1698   int s = MASKED64 (GPR[rs], 5, 0);
1699   TRACE_ALU_INPUT2 (GPR[rt], s);
1700   GPR[rd] = ((signed64) GPR[rt]) >> s;
1701   TRACE_ALU_RESULT (GPR[rd]);
1702 }
1703
1704 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1705 "dsra32 r<RT>, r<RD>, r<RS>"
1706 *mipsIII:
1707 *mipsIV:
1708 *vr4100:
1709 *vr5000:
1710 // start-sanitize-vr4320
1711 *vr4320:
1712 // end-sanitize-vr4320
1713 // start-sanitize-cygnus
1714 *vr5400:
1715 // end-sanitize-cygnus
1716 // start-sanitize-r5900
1717 *r5900:
1718 // end-sanitize-r5900
1719 // start-sanitize-tx19
1720 *tx19:
1721 // end-sanitize-tx19
1722 {
1723   do_dsrav (SD_, RS, RT, RD);
1724 }
1725
1726
1727 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1728 "dsrl r<RD>, r<RT>, <SHIFT>"
1729 *mipsIII:
1730 *mipsIV:
1731 *vr4100:
1732 *vr5000:
1733 // start-sanitize-vr4320
1734 *vr4320:
1735 // end-sanitize-vr4320
1736 // start-sanitize-cygnus
1737 *vr5400:
1738 // end-sanitize-cygnus
1739 // start-sanitize-r5900
1740 *r5900:
1741 // end-sanitize-r5900
1742 // start-sanitize-tx19
1743 *tx19:
1744 // end-sanitize-tx19
1745 {
1746   int s = SHIFT;
1747   GPR[RD] = (unsigned64) GPR[RT] >> s;
1748 }
1749
1750
1751 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1752 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1753 *mipsIII:
1754 *mipsIV:
1755 *vr4100:
1756 *vr5000:
1757 // start-sanitize-vr4320
1758 *vr4320:
1759 // end-sanitize-vr4320
1760 // start-sanitize-cygnus
1761 *vr5400:
1762 // end-sanitize-cygnus
1763 // start-sanitize-r5900
1764 *r5900:
1765 // end-sanitize-r5900
1766 // start-sanitize-tx19
1767 *tx19:
1768 // end-sanitize-tx19
1769 {
1770   int s = 32 + SHIFT;
1771   GPR[RD] = (unsigned64) GPR[RT] >> s;
1772 }
1773
1774
1775 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1776 "dsrl32 r<RD>, r<RT>, r<RS>"
1777 *mipsIII:
1778 *mipsIV:
1779 *vr4100:
1780 *vr5000:
1781 // start-sanitize-vr4320
1782 *vr4320:
1783 // end-sanitize-vr4320
1784 // start-sanitize-cygnus
1785 *vr5400:
1786 // end-sanitize-cygnus
1787 // start-sanitize-r5900
1788 *r5900:
1789 // end-sanitize-r5900
1790 // start-sanitize-tx19
1791 *tx19:
1792 // end-sanitize-tx19
1793 {
1794   int s = MASKED64 (GPR[RS], 5, 0);
1795   GPR[RD] = (unsigned64) GPR[RT] >> s;
1796 }
1797
1798
1799 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1800 "dsub r<RD>, r<RS>, r<RT>"
1801 *mipsIII:
1802 *mipsIV:
1803 *vr4100:
1804 *vr5000:
1805 // start-sanitize-vr4320
1806 *vr4320:
1807 // end-sanitize-vr4320
1808 // start-sanitize-cygnus
1809 *vr5400:
1810 // end-sanitize-cygnus
1811 // start-sanitize-r5900
1812 *r5900:
1813 // end-sanitize-r5900
1814 // start-sanitize-tx19
1815 *tx19:
1816 // end-sanitize-tx19
1817 {
1818   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1819   {
1820     ALU64_BEGIN (GPR[RS]);
1821     ALU64_SUB (GPR[RT]);
1822     ALU64_END (GPR[RD]);
1823   }
1824   TRACE_ALU_RESULT (GPR[RD]);
1825 }
1826
1827
1828 :function:::void:do_dsubu:int rs, int rt, int rd
1829 {
1830   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1831   GPR[rd] = GPR[rs] - GPR[rt];
1832   TRACE_ALU_RESULT (GPR[rd]);
1833 }
1834
1835 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1836 "dsubu r<RD>, r<RS>, r<RT>"
1837 *mipsIII:
1838 *mipsIV:
1839 *vr4100:
1840 *vr5000:
1841 // start-sanitize-vr4320
1842 *vr4320:
1843 // end-sanitize-vr4320
1844 // start-sanitize-cygnus
1845 *vr5400:
1846 // end-sanitize-cygnus
1847 // start-sanitize-r5900
1848 *r5900:
1849 // end-sanitize-r5900
1850 // start-sanitize-tx19
1851 *tx19:
1852 // end-sanitize-tx19
1853 {
1854   do_dsubu (SD_, RS, RT, RD);
1855 }
1856
1857
1858 000010,26.INSTR_INDEX:NORMAL:32::J
1859 "j <INSTR_INDEX>"
1860 *mipsI,mipsII,mipsIII,mipsIV:
1861 *vr4100:
1862 *vr5000:
1863 // start-sanitize-vr4320
1864 *vr4320:
1865 // end-sanitize-vr4320
1866 // start-sanitize-cygnus
1867 *vr5400:
1868 // end-sanitize-cygnus
1869 // start-sanitize-r5900
1870 *r5900:
1871 // end-sanitize-r5900
1872 *r3900:
1873 // start-sanitize-tx19
1874 *tx19:
1875 // end-sanitize-tx19
1876 {
1877   /* NOTE: The region used is that of the delay slot NIA and NOT the
1878      current instruction */
1879   address_word region = (NIA & MASK (63, 28));
1880   DELAY_SLOT (region | (INSTR_INDEX << 2));
1881 }
1882
1883
1884 000011,26.INSTR_INDEX:NORMAL:32::JAL
1885 "jal <INSTR_INDEX>"
1886 *mipsI,mipsII,mipsIII,mipsIV:
1887 *vr4100:
1888 *vr5000:
1889 // start-sanitize-vr4320
1890 *vr4320:
1891 // end-sanitize-vr4320
1892 // start-sanitize-cygnus
1893 *vr5400:
1894 // end-sanitize-cygnus
1895 // start-sanitize-r5900
1896 *r5900:
1897 // end-sanitize-r5900
1898 *r3900:
1899 // start-sanitize-tx19
1900 *tx19:
1901 // end-sanitize-tx19
1902 {
1903   /* NOTE: The region used is that of the delay slot and NOT the
1904      current instruction */
1905   address_word region = (NIA & MASK (63, 28));
1906   GPR[31] = CIA + 8;
1907   DELAY_SLOT (region | (INSTR_INDEX << 2));
1908 }
1909
1910
1911 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1912 "jalr r<RS>":RD == 31
1913 "jalr r<RD>, r<RS>"
1914 *mipsI,mipsII,mipsIII,mipsIV:
1915 *vr4100:
1916 *vr5000:
1917 // start-sanitize-vr4320
1918 *vr4320:
1919 // end-sanitize-vr4320
1920 // start-sanitize-cygnus
1921 *vr5400:
1922 // end-sanitize-cygnus
1923 // start-sanitize-r5900
1924 *r5900:
1925 // end-sanitize-r5900
1926 *r3900:
1927 // start-sanitize-tx19
1928 *tx19:
1929 // end-sanitize-tx19
1930 {
1931   address_word temp = GPR[RS];
1932   GPR[RD] = CIA + 8;
1933   DELAY_SLOT (temp);
1934 }
1935
1936
1937 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1938 "jr r<RS>"
1939 *mipsI,mipsII,mipsIII,mipsIV:
1940 *vr4100:
1941 *vr5000:
1942 // start-sanitize-vr4320
1943 *vr4320:
1944 // end-sanitize-vr4320
1945 // start-sanitize-cygnus
1946 *vr5400:
1947 // end-sanitize-cygnus
1948 // start-sanitize-r5900
1949 *r5900:
1950 // end-sanitize-r5900
1951 *r3900:
1952 // start-sanitize-tx19
1953 *tx19:
1954 // end-sanitize-tx19
1955 {
1956   DELAY_SLOT (GPR[RS]);
1957 }
1958
1959
1960 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1961 {
1962   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1963   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1964   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1965   unsigned int byte;
1966   address_word paddr;
1967   int uncached;
1968   unsigned64 memval;
1969   address_word vaddr;
1970
1971   vaddr = base + offset;
1972   if ((vaddr & access) != 0)
1973     SignalExceptionAddressLoad ();
1974   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1975   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1976   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1977   byte = ((vaddr & mask) ^ bigendiancpu);
1978   return (memval >> (8 * byte));
1979 }
1980
1981
1982 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1983 "lb r<RT>, <OFFSET>(r<BASE>)"
1984 *mipsI,mipsII,mipsIII,mipsIV:
1985 *vr4100:
1986 *vr5000:
1987 // start-sanitize-vr4320
1988 *vr4320:
1989 // end-sanitize-vr4320
1990 // start-sanitize-cygnus
1991 *vr5400:
1992 // end-sanitize-cygnus
1993 // start-sanitize-r5900
1994 *r5900:
1995 // end-sanitize-r5900
1996 *r3900:
1997 // start-sanitize-tx19
1998 *tx19:
1999 // end-sanitize-tx19
2000 {
2001   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2002 }
2003
2004
2005 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2006 "lbu r<RT>, <OFFSET>(r<BASE>)"
2007 *mipsI,mipsII,mipsIII,mipsIV:
2008 *vr4100:
2009 *vr5000:
2010 // start-sanitize-vr4320
2011 *vr4320:
2012 // end-sanitize-vr4320
2013 // start-sanitize-cygnus
2014 *vr5400:
2015 // end-sanitize-cygnus
2016 // start-sanitize-r5900
2017 *r5900:
2018 // end-sanitize-r5900
2019 *r3900:
2020 // start-sanitize-tx19
2021 *tx19:
2022 // end-sanitize-tx19
2023 {
2024   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2025 }
2026
2027
2028 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2029 "ld r<RT>, <OFFSET>(r<BASE>)"
2030 *mipsIII:
2031 *mipsIV:
2032 *vr4100:
2033 *vr5000:
2034 // start-sanitize-vr4320
2035 *vr4320:
2036 // end-sanitize-vr4320
2037 // start-sanitize-cygnus
2038 *vr5400:
2039 // end-sanitize-cygnus
2040 // start-sanitize-r5900
2041 *r5900:
2042 // end-sanitize-r5900
2043 // start-sanitize-tx19
2044 *tx19:
2045 // end-sanitize-tx19
2046 {
2047   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2048 }
2049
2050
2051 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2052 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2053 *mipsII:
2054 *mipsIII:
2055 *mipsIV:
2056 *vr4100:
2057 *vr5000:
2058 // start-sanitize-vr4320
2059 *vr4320:
2060 // end-sanitize-vr4320
2061 // start-sanitize-cygnus
2062 *vr5400:
2063 // end-sanitize-cygnus
2064 *r3900:
2065 // start-sanitize-tx19
2066 *tx19:
2067 // end-sanitize-tx19
2068 {
2069   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2070 }
2071
2072
2073
2074
2075 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2076 "ldl r<RT>, <OFFSET>(r<BASE>)"
2077 *mipsIII:
2078 *mipsIV:
2079 *vr4100:
2080 *vr5000:
2081 // start-sanitize-vr4320
2082 *vr4320:
2083 // end-sanitize-vr4320
2084 // start-sanitize-cygnus
2085 *vr5400:
2086 // end-sanitize-cygnus
2087 // start-sanitize-r5900
2088 *r5900:
2089 // end-sanitize-r5900
2090 // start-sanitize-tx19
2091 *tx19:
2092 // end-sanitize-tx19
2093 {
2094   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2095 }
2096
2097
2098 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2099 "ldr r<RT>, <OFFSET>(r<BASE>)"
2100 *mipsIII:
2101 *mipsIV:
2102 *vr4100:
2103 *vr5000:
2104 // start-sanitize-vr4320
2105 *vr4320:
2106 // end-sanitize-vr4320
2107 // start-sanitize-cygnus
2108 *vr5400:
2109 // end-sanitize-cygnus
2110 // start-sanitize-r5900
2111 *r5900:
2112 // end-sanitize-r5900
2113 // start-sanitize-tx19
2114 *tx19:
2115 // end-sanitize-tx19
2116 {
2117   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2118 }
2119
2120
2121 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2122 "lh r<RT>, <OFFSET>(r<BASE>)"
2123 *mipsI,mipsII,mipsIII,mipsIV:
2124 *vr4100:
2125 *vr5000:
2126 // start-sanitize-vr4320
2127 *vr4320:
2128 // end-sanitize-vr4320
2129 // start-sanitize-cygnus
2130 *vr5400:
2131 // end-sanitize-cygnus
2132 // start-sanitize-r5900
2133 *r5900:
2134 // end-sanitize-r5900
2135 *r3900:
2136 // start-sanitize-tx19
2137 *tx19:
2138 // end-sanitize-tx19
2139 {
2140   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2141 }
2142
2143
2144 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2145 "lhu r<RT>, <OFFSET>(r<BASE>)"
2146 *mipsI,mipsII,mipsIII,mipsIV:
2147 *vr4100:
2148 *vr5000:
2149 // start-sanitize-vr4320
2150 *vr4320:
2151 // end-sanitize-vr4320
2152 // start-sanitize-cygnus
2153 *vr5400:
2154 // end-sanitize-cygnus
2155 // start-sanitize-r5900
2156 *r5900:
2157 // end-sanitize-r5900
2158 *r3900:
2159 // start-sanitize-tx19
2160 *tx19:
2161 // end-sanitize-tx19
2162 {
2163   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2164 }
2165
2166
2167 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2168 "ll r<RT>, <OFFSET>(r<BASE>)"
2169 *mipsII:
2170 *mipsIII:
2171 *mipsIV:
2172 *vr4100:
2173 *vr5000:
2174 // start-sanitize-vr4320
2175 *vr4320:
2176 // end-sanitize-vr4320
2177 // start-sanitize-cygnus
2178 *vr5400:
2179 // end-sanitize-cygnus
2180 // start-sanitize-r5900
2181 *r5900:
2182 // end-sanitize-r5900
2183 // start-sanitize-tx19
2184 *tx19:
2185 // end-sanitize-tx19
2186 {
2187   unsigned32 instruction = instruction_0;
2188   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2189   int destreg = ((instruction >> 16) & 0x0000001F);
2190   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2191   {
2192     address_word vaddr = ((unsigned64)op1 + offset);
2193     address_word paddr;
2194     int uncached;
2195     if ((vaddr & 3) != 0)
2196       SignalExceptionAddressLoad();
2197     else
2198       {
2199         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2200           {
2201             unsigned64 memval = 0;
2202             unsigned64 memval1 = 0;
2203             unsigned64 mask = 0x7;
2204             unsigned int shift = 2;
2205             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2206             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2207             unsigned int byte;
2208             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2209             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2210             byte = ((vaddr & mask) ^ (bigend << shift));
2211             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
2212             LLBIT = 1;
2213           }
2214       }
2215   }
2216 }
2217
2218
2219 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2220 "lld r<RT>, <OFFSET>(r<BASE>)"
2221 *mipsIII:
2222 *mipsIV:
2223 *vr4100:
2224 *vr5000:
2225 // start-sanitize-vr4320
2226 *vr4320:
2227 // end-sanitize-vr4320
2228 // start-sanitize-cygnus
2229 *vr5400:
2230 // end-sanitize-cygnus
2231 // start-sanitize-r5900
2232 *r5900:
2233 // end-sanitize-r5900
2234 // start-sanitize-tx19
2235 *tx19:
2236 // end-sanitize-tx19
2237 {
2238   unsigned32 instruction = instruction_0;
2239   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2240   int destreg = ((instruction >> 16) & 0x0000001F);
2241   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2242   {
2243     address_word vaddr = ((unsigned64)op1 + offset);
2244     address_word paddr;
2245     int uncached;
2246     if ((vaddr & 7) != 0)
2247       SignalExceptionAddressLoad();
2248     else
2249       {
2250         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2251           {
2252             unsigned64 memval = 0;
2253             unsigned64 memval1 = 0;
2254             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2255             GPR[destreg] = memval;
2256             LLBIT = 1;
2257           }
2258       }
2259   }
2260 }
2261
2262
2263 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2264 "lui r<RT>, <IMMEDIATE>"
2265 *mipsI,mipsII,mipsIII,mipsIV:
2266 *vr4100:
2267 *vr5000:
2268 // start-sanitize-vr4320
2269 *vr4320:
2270 // end-sanitize-vr4320
2271 // start-sanitize-cygnus
2272 *vr5400:
2273 // end-sanitize-cygnus
2274 // start-sanitize-r5900
2275 *r5900:
2276 // end-sanitize-r5900
2277 *r3900:
2278 // start-sanitize-tx19
2279 *tx19:
2280 // end-sanitize-tx19
2281 {
2282   TRACE_ALU_INPUT1 (IMMEDIATE);
2283   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2284   TRACE_ALU_RESULT (GPR[RT]);
2285 }
2286
2287
2288 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2289 "lw r<RT>, <OFFSET>(r<BASE>)"
2290 *mipsI,mipsII,mipsIII,mipsIV:
2291 *vr4100:
2292 *vr5000:
2293 // start-sanitize-vr4320
2294 *vr4320:
2295 // end-sanitize-vr4320
2296 // start-sanitize-cygnus
2297 *vr5400:
2298 // end-sanitize-cygnus
2299 // start-sanitize-r5900
2300 *r5900:
2301 // end-sanitize-r5900
2302 *r3900:
2303 // start-sanitize-tx19
2304 *tx19:
2305 // end-sanitize-tx19
2306 {
2307   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2308 }
2309
2310
2311 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2312 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2313 *mipsI,mipsII,mipsIII,mipsIV:
2314 *vr4100:
2315 *vr5000:
2316 // start-sanitize-vr4320
2317 *vr4320:
2318 // end-sanitize-vr4320
2319 // start-sanitize-cygnus
2320 *vr5400:
2321 // end-sanitize-cygnus
2322 // start-sanitize-r5900
2323 *r5900:
2324 // end-sanitize-r5900
2325 *r3900:
2326 // start-sanitize-tx19
2327 *tx19:
2328 // end-sanitize-tx19
2329 {
2330   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2331 }
2332
2333
2334 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2335 {
2336   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2337   address_word reverseendian = (ReverseEndian ? -1 : 0);
2338   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2339   unsigned int byte;
2340   unsigned int word;
2341   address_word paddr;
2342   int uncached;
2343   unsigned64 memval;
2344   address_word vaddr;
2345   int nr_lhs_bits;
2346   int nr_rhs_bits;
2347   unsigned_word lhs_mask;
2348   unsigned_word temp;
2349
2350   vaddr = base + offset;
2351   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2352   paddr = (paddr ^ (reverseendian & mask));
2353   if (BigEndianMem == 0)
2354     paddr = paddr & ~access;
2355
2356   /* compute where within the word/mem we are */
2357   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2358   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2359   nr_lhs_bits = 8 * byte + 8;
2360   nr_rhs_bits = 8 * access - 8 * byte;
2361   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2362
2363   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2364            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2365            (long) ((unsigned64) paddr >> 32), (long) paddr,
2366            word, byte, nr_lhs_bits, nr_rhs_bits); */
2367
2368   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2369   if (word == 0)
2370     {
2371       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2372       temp = (memval << nr_rhs_bits);
2373     }
2374   else
2375     {
2376       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2377       temp = (memval >> nr_lhs_bits);
2378     }
2379   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2380   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2381
2382   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2383            (long) ((unsigned64) memval >> 32), (long) memval,
2384            (long) ((unsigned64) temp >> 32), (long) temp,
2385            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2386            (long) (rt >> 32), (long) rt); */
2387   return rt;
2388 }
2389
2390
2391 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2392 "lwl r<RT>, <OFFSET>(r<BASE>)"
2393 *mipsI,mipsII,mipsIII,mipsIV:
2394 *vr4100:
2395 *vr5000:
2396 // start-sanitize-vr4320
2397 *vr4320:
2398 // end-sanitize-vr4320
2399 // start-sanitize-cygnus
2400 *vr5400:
2401 // end-sanitize-cygnus
2402 // start-sanitize-r5900
2403 *r5900:
2404 // end-sanitize-r5900
2405 *r3900:
2406 // start-sanitize-tx19
2407 *tx19:
2408 // end-sanitize-tx19
2409 {
2410   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND32 (OFFSET), GPR[RT]));
2411 }
2412
2413
2414 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2415 {
2416   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2417   address_word reverseendian = (ReverseEndian ? -1 : 0);
2418   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2419   unsigned int byte;
2420   address_word paddr;
2421   int uncached;
2422   unsigned64 memval;
2423   address_word vaddr;
2424
2425   vaddr = base + offset;
2426   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2427   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2428   paddr = (paddr ^ (reverseendian & mask));
2429   if (BigEndianMem != 0)
2430     paddr = paddr & ~access;
2431   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2432   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2433   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2434   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2435      (long) paddr, byte, (long) paddr, (long) memval); */
2436   {
2437     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2438     rt &= ~screen;
2439     rt |= (memval >> (8 * byte)) & screen;
2440   }
2441   return rt;
2442 }
2443
2444
2445 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2446 "lwr r<RT>, <OFFSET>(r<BASE>)"
2447 *mipsI,mipsII,mipsIII,mipsIV:
2448 *vr4100:
2449 *vr5000:
2450 // start-sanitize-vr4320
2451 *vr4320:
2452 // end-sanitize-vr4320
2453 // start-sanitize-cygnus
2454 *vr5400:
2455 // end-sanitize-cygnus
2456 // start-sanitize-r5900
2457 *r5900:
2458 // end-sanitize-r5900
2459 *r3900:
2460 // start-sanitize-tx19
2461 *tx19:
2462 // end-sanitize-tx19
2463 {
2464   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2465 }
2466
2467
2468 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
2469 "lwu r<RT>, <OFFSET>(r<BASE>)"
2470 *mipsIII:
2471 *mipsIV:
2472 *vr4100:
2473 *vr5000:
2474 // start-sanitize-vr4320
2475 *vr4320:
2476 // end-sanitize-vr4320
2477 // start-sanitize-cygnus
2478 *vr5400:
2479 // end-sanitize-cygnus
2480 // start-sanitize-r5900
2481 *r5900:
2482 // end-sanitize-r5900
2483 // start-sanitize-tx19
2484 *tx19:
2485 // end-sanitize-tx19
2486 {
2487   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2488 }
2489
2490
2491 :function:::void:do_mfhi:int rd
2492 {
2493   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2494   TRACE_ALU_INPUT1 (HI);
2495   GPR[rd] = HI;
2496   TRACE_ALU_RESULT (GPR[rd]);
2497 }
2498
2499 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2500 "mfhi r<RD>"
2501 *mipsI,mipsII,mipsIII,mipsIV:
2502 *vr4100:
2503 *vr5000:
2504 // start-sanitize-vr4320
2505 *vr4320:
2506 // end-sanitize-vr4320
2507 // start-sanitize-cygnus
2508 *vr5400:
2509 // end-sanitize-cygnus
2510 // start-sanitize-r5900
2511 *r5900:
2512 // end-sanitize-r5900
2513 *r3900:
2514 // start-sanitize-tx19
2515 *tx19:
2516 // end-sanitize-tx19
2517 {
2518   do_mfhi (SD_, RD);
2519 }
2520
2521
2522
2523 :function:::void:do_mflo:int rd
2524 {
2525   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2526   TRACE_ALU_INPUT1 (LO);
2527   GPR[rd] = LO;
2528   TRACE_ALU_RESULT (GPR[rd]);
2529 }
2530
2531 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2532 "mflo r<RD>"
2533 *mipsI,mipsII,mipsIII,mipsIV:
2534 *vr4100:
2535 *vr5000:
2536 // start-sanitize-vr4320
2537 *vr4320:
2538 // end-sanitize-vr4320
2539 // start-sanitize-cygnus
2540 *vr5400:
2541 // end-sanitize-cygnus
2542 // start-sanitize-r5900
2543 *r5900:
2544 // end-sanitize-r5900
2545 *r3900:
2546 // start-sanitize-tx19
2547 *tx19:
2548 // end-sanitize-tx19
2549 {
2550   do_mflo (SD_, RD);
2551 }
2552
2553
2554
2555 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
2556 "movn r<RD>, r<RS>, r<RT>"
2557 *mipsIV:
2558 *vr5000:
2559 // start-sanitize-vr4320
2560 *vr4320:
2561 // end-sanitize-vr4320
2562 // start-sanitize-cygnus
2563 *vr5400:
2564 // end-sanitize-cygnus
2565 // start-sanitize-r5900
2566 *r5900:
2567 // end-sanitize-r5900
2568 {
2569   if (GPR[RT] != 0)
2570     GPR[RD] = GPR[RS];
2571 }
2572
2573
2574
2575 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
2576 "movz r<RD>, r<RS>, r<RT>"
2577 *mipsIV:
2578 *vr5000:
2579 // start-sanitize-vr4320
2580 *vr4320:
2581 // end-sanitize-vr4320
2582 // start-sanitize-cygnus
2583 *vr5400:
2584 // end-sanitize-cygnus
2585 // start-sanitize-r5900
2586 *r5900:
2587 // end-sanitize-r5900
2588 {
2589   if (GPR[RT] == 0)
2590     GPR[RD] = GPR[RS];
2591 }
2592
2593
2594
2595 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2596 "mthi r<RS>"
2597 *mipsI,mipsII,mipsIII,mipsIV:
2598 *vr4100:
2599 *vr5000:
2600 // start-sanitize-vr4320
2601 *vr4320:
2602 // end-sanitize-vr4320
2603 // start-sanitize-cygnus
2604 *vr5400:
2605 // end-sanitize-cygnus
2606 // start-sanitize-r5900
2607 *r5900:
2608 // end-sanitize-r5900
2609 *r3900:
2610 // start-sanitize-tx19
2611 *tx19:
2612 // end-sanitize-tx19
2613 {
2614   check_mt_hilo (SD_, HIHISTORY);
2615   HI = GPR[RS];
2616 }
2617
2618
2619
2620 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
2621 "mtlo r<RS>"
2622 *mipsI,mipsII,mipsIII,mipsIV:
2623 *vr4100:
2624 *vr5000:
2625 // start-sanitize-vr4320
2626 *vr4320:
2627 // end-sanitize-vr4320
2628 // start-sanitize-cygnus
2629 *vr5400:
2630 // end-sanitize-cygnus
2631 // start-sanitize-r5900
2632 *r5900:
2633 // end-sanitize-r5900
2634 *r3900:
2635 // start-sanitize-tx19
2636 *tx19:
2637 // end-sanitize-tx19
2638 {
2639   check_mt_hilo (SD_, LOHISTORY);
2640   LO = GPR[RS];
2641 }
2642
2643
2644
2645 :function:::void:do_mult:int rs, int rt, int rd
2646 {
2647   signed64 prod;
2648   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2649   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2650   prod = (((signed64)(signed32) GPR[rs])
2651           * ((signed64)(signed32) GPR[rt]));
2652   LO = EXTEND32 (VL4_8 (prod));
2653   HI = EXTEND32 (VH4_8 (prod));
2654   if (rd != 0)
2655     GPR[rd] = LO;
2656   TRACE_ALU_RESULT2 (HI, LO);
2657 }
2658
2659 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
2660 "mult r<RS>, r<RT>"
2661 *mipsI,mipsII,mipsIII,mipsIV:
2662 *vr4100:
2663 // start-sanitize-vr4320
2664 *vr4320:
2665 // end-sanitize-vr4320
2666 {
2667   do_mult (SD_, RS, RT, 0);
2668 }
2669
2670
2671 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
2672 "mult r<RD>, r<RS>, r<RT>"
2673 *vr5000:
2674 // start-sanitize-cygnus
2675 *vr5400:
2676 // end-sanitize-cygnus
2677 // start-sanitize-r5900
2678 *r5900:
2679 // end-sanitize-r5900
2680 *r3900:
2681 // start-sanitize-tx19
2682 *tx19:
2683 // end-sanitize-tx19
2684 {
2685   do_mult (SD_, RS, RT, RD);
2686 }
2687
2688
2689 :function:::void:do_multu:int rs, int rt, int rd
2690 {
2691   unsigned64 prod;
2692   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2693   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2694   prod = (((unsigned64)(unsigned32) GPR[rs])
2695           * ((unsigned64)(unsigned32) GPR[rt]));
2696   LO = EXTEND32 (VL4_8 (prod));
2697   HI = EXTEND32 (VH4_8 (prod));
2698   if (rd != 0)
2699     GPR[rd] = LO;
2700   TRACE_ALU_RESULT2 (HI, LO);
2701 }
2702
2703 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
2704 "multu r<RS>, r<RT>"
2705 *mipsI,mipsII,mipsIII,mipsIV:
2706 *vr4100:
2707 // start-sanitize-vr4320
2708 *vr4320:
2709 // end-sanitize-vr4320
2710 {
2711   do_multu (SD_, RS, RT, 0);
2712 }
2713
2714 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
2715 "multu r<RD>, r<RS>, r<RT>"
2716 *vr5000:
2717 // start-sanitize-cygnus
2718 *vr5400:
2719 // end-sanitize-cygnus
2720 // start-sanitize-r5900
2721 *r5900:
2722 // end-sanitize-r5900
2723 *r3900:
2724 // start-sanitize-tx19
2725 *tx19:
2726 // end-sanitize-tx19
2727 {
2728   do_multu (SD_, RS, RT, 0);
2729 }
2730
2731
2732 :function:::void:do_nor:int rs, int rt, int rd
2733 {
2734   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2735   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2736   TRACE_ALU_RESULT (GPR[rd]);
2737 }
2738
2739 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2740 "nor r<RD>, r<RS>, r<RT>"
2741 *mipsI,mipsII,mipsIII,mipsIV:
2742 *vr4100:
2743 *vr5000:
2744 // start-sanitize-vr4320
2745 *vr4320:
2746 // end-sanitize-vr4320
2747 // start-sanitize-cygnus
2748 *vr5400:
2749 // end-sanitize-cygnus
2750 // start-sanitize-r5900
2751 *r5900:
2752 // end-sanitize-r5900
2753 *r3900:
2754 // start-sanitize-tx19
2755 *tx19:
2756 // end-sanitize-tx19
2757 {
2758   do_nor (SD_, RS, RT, RD);
2759 }
2760
2761
2762 :function:::void:do_or:int rs, int rt, int rd
2763 {
2764   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2765   GPR[rd] = (GPR[rs] | GPR[rt]);
2766   TRACE_ALU_RESULT (GPR[rd]);
2767 }
2768
2769 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2770 "or r<RD>, r<RS>, r<RT>"
2771 *mipsI,mipsII,mipsIII,mipsIV:
2772 *vr4100:
2773 *vr5000:
2774 // start-sanitize-vr4320
2775 *vr4320:
2776 // end-sanitize-vr4320
2777 // start-sanitize-cygnus
2778 *vr5400:
2779 // end-sanitize-cygnus
2780 // start-sanitize-r5900
2781 *r5900:
2782 // end-sanitize-r5900
2783 *r3900:
2784 // start-sanitize-tx19
2785 *tx19:
2786 // end-sanitize-tx19
2787 {
2788   do_or (SD_, RS, RT, RD);
2789 }
2790
2791
2792
2793 :function:::void:do_ori:int rs, int rt, unsigned immediate
2794 {
2795   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2796   GPR[rt] = (GPR[rs] | immediate);
2797   TRACE_ALU_RESULT (GPR[rt]);
2798 }
2799
2800 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2801 "ori r<RT>, r<RS>, <IMMEDIATE>"
2802 *mipsI,mipsII,mipsIII,mipsIV:
2803 *vr4100:
2804 *vr5000:
2805 // start-sanitize-vr4320
2806 *vr4320:
2807 // end-sanitize-vr4320
2808 // start-sanitize-cygnus
2809 *vr5400:
2810 // end-sanitize-cygnus
2811 // start-sanitize-r5900
2812 *r5900:
2813 // end-sanitize-r5900
2814 *r3900:
2815 // start-sanitize-tx19
2816 *tx19:
2817 // end-sanitize-tx19
2818 {
2819   do_ori (SD_, RS, RT, IMMEDIATE);
2820 }
2821
2822
2823 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
2824 *mipsIV:
2825 *vr5000:
2826 // start-sanitize-vr4320
2827 *vr4320:
2828 // end-sanitize-vr4320
2829 // start-sanitize-cygnus
2830 *vr5400:
2831 // end-sanitize-cygnus
2832 // start-sanitize-r5900
2833 *r5900:
2834 // end-sanitize-r5900
2835 {
2836   unsigned32 instruction = instruction_0;
2837   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2838   int hint = ((instruction >> 16) & 0x0000001F);
2839   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2840   {
2841     address_word vaddr = ((unsigned64)op1 + offset);
2842     address_word paddr;
2843     int uncached;
2844     {
2845       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2846         Prefetch(uncached,paddr,vaddr,isDATA,hint);
2847     }
2848   }
2849 }
2850
2851 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2852 {
2853   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2854   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2855   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2856   unsigned int byte;
2857   address_word paddr;
2858   int uncached;
2859   unsigned64 memval;
2860   address_word vaddr;
2861
2862   vaddr = base + offset;
2863   if ((vaddr & access) != 0)
2864     SignalExceptionAddressStore ();
2865   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2866   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2867   byte = ((vaddr & mask) ^ bigendiancpu);
2868   memval = (word << (8 * byte));
2869   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2870 }
2871
2872
2873 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2874 "sb r<RT>, <OFFSET>(r<BASE>)"
2875 *mipsI,mipsII,mipsIII,mipsIV:
2876 *vr4100:
2877 *vr5000:
2878 // start-sanitize-vr4320
2879 *vr4320:
2880 // end-sanitize-vr4320
2881 // start-sanitize-cygnus
2882 *vr5400:
2883 // end-sanitize-cygnus
2884 // start-sanitize-r5900
2885 *r5900:
2886 // end-sanitize-r5900
2887 *r3900:
2888 // start-sanitize-tx19
2889 *tx19:
2890 // end-sanitize-tx19
2891 {
2892   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2893 }
2894
2895
2896 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2897 "sc r<RT>, <OFFSET>(r<BASE>)"
2898 *mipsII:
2899 *mipsIII:
2900 *mipsIV:
2901 *vr4100:
2902 *vr5000:
2903 // start-sanitize-vr4320
2904 *vr4320:
2905 // end-sanitize-vr4320
2906 // start-sanitize-cygnus
2907 *vr5400:
2908 // end-sanitize-cygnus
2909 // start-sanitize-r5900
2910 *r5900:
2911 // end-sanitize-r5900
2912 // start-sanitize-tx19
2913 *tx19:
2914 // end-sanitize-tx19
2915 {
2916   unsigned32 instruction = instruction_0;
2917   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2918   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2919   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2920   {
2921     address_word vaddr = ((unsigned64)op1 + offset);
2922     address_word paddr;
2923     int uncached;
2924     if ((vaddr & 3) != 0)
2925       SignalExceptionAddressStore();
2926     else
2927       {
2928         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2929           {
2930             unsigned64 memval = 0;
2931             unsigned64 memval1 = 0;
2932             unsigned64 mask = 0x7;
2933             unsigned int byte;
2934             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2935             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2936             memval = ((unsigned64) op2 << (8 * byte));
2937             if (LLBIT)
2938               {
2939                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2940               }
2941             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2942           }
2943       }
2944   }
2945 }
2946
2947
2948 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2949 "scd r<RT>, <OFFSET>(r<BASE>)"
2950 *mipsIII:
2951 *mipsIV:
2952 *vr4100:
2953 *vr5000:
2954 // start-sanitize-vr4320
2955 *vr4320:
2956 // end-sanitize-vr4320
2957 // start-sanitize-cygnus
2958 *vr5400:
2959 // end-sanitize-cygnus
2960 // start-sanitize-r5900
2961 *r5900:
2962 // end-sanitize-r5900
2963 // start-sanitize-tx19
2964 *tx19:
2965 // end-sanitize-tx19
2966 {
2967   unsigned32 instruction = instruction_0;
2968   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
2969   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
2970   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
2971   {
2972     address_word vaddr = ((unsigned64)op1 + offset);
2973     address_word paddr;
2974     int uncached;
2975     if ((vaddr & 7) != 0)
2976       SignalExceptionAddressStore();
2977     else
2978       {
2979         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2980           {
2981             unsigned64 memval = 0;
2982             unsigned64 memval1 = 0;
2983             memval = op2;
2984             if (LLBIT)
2985               {
2986                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2987               }
2988             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
2989           }
2990       }
2991   }
2992 }
2993
2994
2995 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2996 "sd r<RT>, <OFFSET>(r<BASE>)"
2997 *mipsIII:
2998 *mipsIV:
2999 *vr4100:
3000 *vr5000:
3001 // start-sanitize-vr4320
3002 *vr4320:
3003 // end-sanitize-vr4320
3004 // start-sanitize-cygnus
3005 *vr5400:
3006 // end-sanitize-cygnus
3007 // start-sanitize-r5900
3008 *r5900:
3009 // end-sanitize-r5900
3010 // start-sanitize-tx19
3011 *tx19:
3012 // end-sanitize-tx19
3013 {
3014   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3015 }
3016
3017
3018 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3019 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3020 *mipsII:
3021 *mipsIII:
3022 *mipsIV:
3023 *vr4100:
3024 *vr5000:
3025 // start-sanitize-vr4320
3026 *vr4320:
3027 // end-sanitize-vr4320
3028 // start-sanitize-cygnus
3029 *vr5400:
3030 // end-sanitize-cygnus
3031 // start-sanitize-tx19
3032 *tx19:
3033 // end-sanitize-tx19
3034 {
3035   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3036 }
3037
3038
3039 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3040 "sdl r<RT>, <OFFSET>(r<BASE>)"
3041 *mipsIII:
3042 *mipsIV:
3043 *vr4100:
3044 *vr5000:
3045 // start-sanitize-vr4320
3046 *vr4320:
3047 // end-sanitize-vr4320
3048 // start-sanitize-cygnus
3049 *vr5400:
3050 // end-sanitize-cygnus
3051 // start-sanitize-r5900
3052 *r5900:
3053 // end-sanitize-r5900
3054 // start-sanitize-tx19
3055 *tx19:
3056 // end-sanitize-tx19
3057 {
3058   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3059 }
3060
3061
3062 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3063 "sdr r<RT>, <OFFSET>(r<BASE>)"
3064 *mipsIII:
3065 *mipsIV:
3066 *vr4100:
3067 *vr5000:
3068 // start-sanitize-vr4320
3069 *vr4320:
3070 // end-sanitize-vr4320
3071 // start-sanitize-cygnus
3072 *vr5400:
3073 // end-sanitize-cygnus
3074 // start-sanitize-r5900
3075 *r5900:
3076 // end-sanitize-r5900
3077 // start-sanitize-tx19
3078 *tx19:
3079 // end-sanitize-tx19
3080 {
3081   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3082 }
3083
3084
3085 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3086 "sh r<RT>, <OFFSET>(r<BASE>)"
3087 *mipsI,mipsII,mipsIII,mipsIV:
3088 *vr4100:
3089 *vr5000:
3090 // start-sanitize-vr4320
3091 *vr4320:
3092 // end-sanitize-vr4320
3093 // start-sanitize-cygnus
3094 *vr5400:
3095 // end-sanitize-cygnus
3096 // start-sanitize-r5900
3097 *r5900:
3098 // end-sanitize-r5900
3099 *r3900:
3100 // start-sanitize-tx19
3101 *tx19:
3102 // end-sanitize-tx19
3103 {
3104   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3105 }
3106
3107
3108 :function:::void:do_sll:int rt, int rd, int shift
3109 {
3110   unsigned32 temp = (GPR[rt] << shift);
3111   TRACE_ALU_INPUT2 (GPR[rt], shift);
3112   GPR[rd] = EXTEND32 (temp);
3113   TRACE_ALU_RESULT (GPR[rd]);
3114 }
3115
3116 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
3117 "sll r<RD>, r<RT>, <SHIFT>"
3118 *mipsI,mipsII,mipsIII,mipsIV:
3119 *vr4100:
3120 *vr5000:
3121 // start-sanitize-vr4320
3122 *vr4320:
3123 // end-sanitize-vr4320
3124 // start-sanitize-cygnus
3125 *vr5400:
3126 // end-sanitize-cygnus
3127 // start-sanitize-r5900
3128 *r5900:
3129 // end-sanitize-r5900
3130 *r3900:
3131 // start-sanitize-tx19
3132 *tx19:
3133 // end-sanitize-tx19
3134 {
3135   do_sll (SD_, RT, RD, SHIFT);
3136 }
3137
3138
3139 :function:::void:do_sllv:int rs, int rt, int rd
3140 {
3141   int s = MASKED (GPR[rs], 4, 0);
3142   unsigned32 temp = (GPR[rt] << s);
3143   TRACE_ALU_INPUT2 (GPR[rt], s);
3144   GPR[rd] = EXTEND32 (temp);
3145   TRACE_ALU_RESULT (GPR[rd]);
3146 }
3147
3148 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
3149 "sllv r<RD>, r<RT>, r<RS>"
3150 *mipsI,mipsII,mipsIII,mipsIV:
3151 *vr4100:
3152 *vr5000:
3153 // start-sanitize-vr4320
3154 *vr4320:
3155 // end-sanitize-vr4320
3156 // start-sanitize-cygnus
3157 *vr5400:
3158 // end-sanitize-cygnus
3159 // start-sanitize-r5900
3160 *r5900:
3161 // end-sanitize-r5900
3162 *r3900:
3163 // start-sanitize-tx19
3164 *tx19:
3165 // end-sanitize-tx19
3166 {
3167   do_sllv (SD_, RS, RT, RD);
3168 }
3169
3170
3171 :function:::void:do_slt:int rs, int rt, int rd
3172 {
3173   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3174   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3175   TRACE_ALU_RESULT (GPR[rd]);
3176 }
3177
3178 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
3179 "slt r<RD>, r<RS>, r<RT>"
3180 *mipsI,mipsII,mipsIII,mipsIV:
3181 *vr4100:
3182 *vr5000:
3183 // start-sanitize-vr4320
3184 *vr4320:
3185 // end-sanitize-vr4320
3186 // start-sanitize-cygnus
3187 *vr5400:
3188 // end-sanitize-cygnus
3189 // start-sanitize-r5900
3190 *r5900:
3191 // end-sanitize-r5900
3192 *r3900:
3193 // start-sanitize-tx19
3194 *tx19:
3195 // end-sanitize-tx19
3196 {
3197   do_slt (SD_, RS, RT, RD);
3198 }
3199
3200
3201 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3202 {
3203   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3204   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3205   TRACE_ALU_RESULT (GPR[rt]);
3206 }
3207
3208 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3209 "slti r<RT>, r<RS>, <IMMEDIATE>"
3210 *mipsI,mipsII,mipsIII,mipsIV:
3211 *vr4100:
3212 *vr5000:
3213 // start-sanitize-vr4320
3214 *vr4320:
3215 // end-sanitize-vr4320
3216 // start-sanitize-cygnus
3217 *vr5400:
3218 // end-sanitize-cygnus
3219 // start-sanitize-r5900
3220 *r5900:
3221 // end-sanitize-r5900
3222 *r3900:
3223 // start-sanitize-tx19
3224 *tx19:
3225 // end-sanitize-tx19
3226 {
3227   do_slti (SD_, RS, RT, IMMEDIATE);
3228 }
3229
3230
3231 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3232 {
3233   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3234   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3235   TRACE_ALU_RESULT (GPR[rt]);
3236 }
3237
3238 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3239 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3240 *mipsI,mipsII,mipsIII,mipsIV:
3241 *vr4100:
3242 *vr5000:
3243 // start-sanitize-vr4320
3244 *vr4320:
3245 // end-sanitize-vr4320
3246 // start-sanitize-cygnus
3247 *vr5400:
3248 // end-sanitize-cygnus
3249 // start-sanitize-r5900
3250 *r5900:
3251 // end-sanitize-r5900
3252 *r3900:
3253 // start-sanitize-tx19
3254 *tx19:
3255 // end-sanitize-tx19
3256 {
3257   do_sltiu (SD_, RS, RT, IMMEDIATE);
3258 }
3259
3260
3261
3262 :function:::void:do_sltu:int rs, int rt, int rd
3263 {
3264   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3265   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3266   TRACE_ALU_RESULT (GPR[rd]);
3267 }
3268
3269 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
3270 "sltu r<RD>, r<RS>, r<RT>"
3271 *mipsI,mipsII,mipsIII,mipsIV:
3272 *vr4100:
3273 *vr5000:
3274 // start-sanitize-vr4320
3275 *vr4320:
3276 // end-sanitize-vr4320
3277 // start-sanitize-cygnus
3278 *vr5400:
3279 // end-sanitize-cygnus
3280 // start-sanitize-r5900
3281 *r5900:
3282 // end-sanitize-r5900
3283 *r3900:
3284 // start-sanitize-tx19
3285 *tx19:
3286 // end-sanitize-tx19
3287 {
3288   do_sltu (SD_, RS, RT, RD);
3289 }
3290
3291
3292 :function:::void:do_sra:int rt, int rd, int shift
3293 {
3294   signed32 temp = (signed32) GPR[rt] >> shift;
3295   TRACE_ALU_INPUT2 (GPR[rt], shift);
3296   GPR[rd] = EXTEND32 (temp);
3297   TRACE_ALU_RESULT (GPR[rd]);
3298 }
3299
3300 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3301 "sra r<RD>, r<RT>, <SHIFT>"
3302 *mipsI,mipsII,mipsIII,mipsIV:
3303 *vr4100:
3304 *vr5000:
3305 // start-sanitize-vr4320
3306 *vr4320:
3307 // end-sanitize-vr4320
3308 // start-sanitize-cygnus
3309 *vr5400:
3310 // end-sanitize-cygnus
3311 // start-sanitize-r5900
3312 *r5900:
3313 // end-sanitize-r5900
3314 *r3900:
3315 // start-sanitize-tx19
3316 *tx19:
3317 // end-sanitize-tx19
3318 {
3319   do_sra (SD_, RT, RD, SHIFT);
3320 }
3321
3322
3323
3324 :function:::void:do_srav:int rs, int rt, int rd
3325 {
3326   int s = MASKED (GPR[rs], 4, 0);
3327   signed32 temp = (signed32) GPR[rt] >> s;
3328   TRACE_ALU_INPUT2 (GPR[rt], s);
3329   GPR[rd] = EXTEND32 (temp);
3330   TRACE_ALU_RESULT (GPR[rd]);
3331 }
3332
3333 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
3334 "srav r<RD>, r<RT>, r<RS>"
3335 *mipsI,mipsII,mipsIII,mipsIV:
3336 *vr4100:
3337 *vr5000:
3338 // start-sanitize-vr4320
3339 *vr4320:
3340 // end-sanitize-vr4320
3341 // start-sanitize-cygnus
3342 *vr5400:
3343 // end-sanitize-cygnus
3344 // start-sanitize-r5900
3345 *r5900:
3346 // end-sanitize-r5900
3347 *r3900:
3348 // start-sanitize-tx19
3349 *tx19:
3350 // end-sanitize-tx19
3351 {
3352   do_srav (SD_, RS, RT, RD);
3353 }
3354
3355
3356
3357 :function:::void:do_srl:int rt, int rd, int shift
3358 {
3359   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3360   TRACE_ALU_INPUT2 (GPR[rt], shift);
3361   GPR[rd] = EXTEND32 (temp);
3362   TRACE_ALU_RESULT (GPR[rd]);
3363 }
3364
3365 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3366 "srl r<RD>, r<RT>, <SHIFT>"
3367 *mipsI,mipsII,mipsIII,mipsIV:
3368 *vr4100:
3369 *vr5000:
3370 // start-sanitize-vr4320
3371 *vr4320:
3372 // end-sanitize-vr4320
3373 // start-sanitize-cygnus
3374 *vr5400:
3375 // end-sanitize-cygnus
3376 // start-sanitize-r5900
3377 *r5900:
3378 // end-sanitize-r5900
3379 *r3900:
3380 // start-sanitize-tx19
3381 *tx19:
3382 // end-sanitize-tx19
3383 {
3384   do_srl (SD_, RT, RD, SHIFT);
3385 }
3386
3387
3388 :function:::void:do_srlv:int rs, int rt, int rd
3389 {
3390   int s = MASKED (GPR[rs], 4, 0);
3391   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3392   TRACE_ALU_INPUT2 (GPR[rt], s);
3393   GPR[rd] = EXTEND32 (temp);
3394   TRACE_ALU_RESULT (GPR[rd]);
3395 }
3396
3397 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
3398 "srlv r<RD>, r<RT>, r<RS>"
3399 *mipsI,mipsII,mipsIII,mipsIV:
3400 *vr4100:
3401 *vr5000:
3402 // start-sanitize-vr4320
3403 *vr4320:
3404 // end-sanitize-vr4320
3405 // start-sanitize-cygnus
3406 *vr5400:
3407 // end-sanitize-cygnus
3408 // start-sanitize-r5900
3409 *r5900:
3410 // end-sanitize-r5900
3411 *r3900:
3412 // start-sanitize-tx19
3413 *tx19:
3414 // end-sanitize-tx19
3415 {
3416   do_srlv (SD_, RS, RT, RD);
3417 }
3418
3419
3420 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
3421 "sub r<RD>, r<RS>, r<RT>"
3422 *mipsI,mipsII,mipsIII,mipsIV:
3423 *vr4100:
3424 *vr5000:
3425 // start-sanitize-vr4320
3426 *vr4320:
3427 // end-sanitize-vr4320
3428 // start-sanitize-cygnus
3429 *vr5400:
3430 // end-sanitize-cygnus
3431 // start-sanitize-r5900
3432 *r5900:
3433 // end-sanitize-r5900
3434 *r3900:
3435 // start-sanitize-tx19
3436 *tx19:
3437 // end-sanitize-tx19
3438 {
3439   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3440   {
3441     ALU32_BEGIN (GPR[RS]);
3442     ALU32_SUB (GPR[RT]);
3443     ALU32_END (GPR[RD]);
3444   }
3445   TRACE_ALU_RESULT (GPR[RD]);
3446 }
3447
3448
3449 :function:::void:do_subu:int rs, int rt, int rd
3450 {
3451   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3452   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3453   TRACE_ALU_RESULT (GPR[rd]);
3454 }
3455
3456 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
3457 "subu r<RD>, r<RS>, r<RT>"
3458 *mipsI,mipsII,mipsIII,mipsIV:
3459 *vr4100:
3460 *vr5000:
3461 // start-sanitize-vr4320
3462 *vr4320:
3463 // end-sanitize-vr4320
3464 // start-sanitize-cygnus
3465 *vr5400:
3466 // end-sanitize-cygnus
3467 // start-sanitize-r5900
3468 *r5900:
3469 // end-sanitize-r5900
3470 *r3900:
3471 // start-sanitize-tx19
3472 *tx19:
3473 // end-sanitize-tx19
3474 {
3475   do_subu (SD_, RS, RT, RD);
3476 }
3477
3478
3479 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3480 "sw r<RT>, <OFFSET>(r<BASE>)"
3481 *mipsI,mipsII,mipsIII,mipsIV:
3482 *vr4100:
3483 // start-sanitize-tx19
3484 *tx19:
3485 // end-sanitize-tx19
3486 *r3900:
3487 // start-sanitize-vr4320
3488 *vr4320:
3489 // end-sanitize-vr4320
3490 *vr5000:
3491 // start-sanitize-cygnus
3492 *vr5400:
3493 // end-sanitize-cygnus
3494 // start-sanitize-r5900
3495 *r5900:
3496 // end-sanitize-r5900
3497 {
3498   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3499 }
3500
3501
3502 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3503 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3504 *mipsI,mipsII,mipsIII,mipsIV:
3505 *vr4100:
3506 *vr5000:
3507 // start-sanitize-vr4320
3508 *vr4320:
3509 // end-sanitize-vr4320
3510 // start-sanitize-cygnus
3511 *vr5400:
3512 // end-sanitize-cygnus
3513 *r3900:
3514 // start-sanitize-tx19
3515 *tx19:
3516 // end-sanitize-tx19
3517 {
3518   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3519 }
3520
3521
3522
3523 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3524 {
3525   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3526   address_word reverseendian = (ReverseEndian ? -1 : 0);
3527   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3528   unsigned int byte;
3529   unsigned int word;
3530   address_word paddr;
3531   int uncached;
3532   unsigned64 memval;
3533   address_word vaddr;
3534   int nr_lhs_bits;
3535   int nr_rhs_bits;
3536
3537   vaddr = base + offset;
3538   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3539   paddr = (paddr ^ (reverseendian & mask));
3540   if (BigEndianMem == 0)
3541     paddr = paddr & ~access;
3542
3543   /* compute where within the word/mem we are */
3544   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3545   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3546   nr_lhs_bits = 8 * byte + 8;
3547   nr_rhs_bits = 8 * access - 8 * byte;
3548   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3549   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3550            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3551            (long) ((unsigned64) paddr >> 32), (long) paddr,
3552            word, byte, nr_lhs_bits, nr_rhs_bits); */
3553
3554   if (word == 0)
3555     {
3556       memval = (rt >> nr_rhs_bits);
3557     }
3558   else
3559     {
3560       memval = (rt << nr_lhs_bits);
3561     }
3562   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3563            (long) ((unsigned64) rt >> 32), (long) rt,
3564            (long) ((unsigned64) memval >> 32), (long) memval); */
3565   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3566 }
3567
3568
3569 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3570 "swl r<RT>, <OFFSET>(r<BASE>)"
3571 *mipsI,mipsII,mipsIII,mipsIV:
3572 *vr4100:
3573 *vr5000:
3574 // start-sanitize-vr4320
3575 *vr4320:
3576 // end-sanitize-vr4320
3577 // start-sanitize-cygnus
3578 *vr5400:
3579 // end-sanitize-cygnus
3580 // start-sanitize-r5900
3581 *r5900:
3582 // end-sanitize-r5900
3583 *r3900:
3584 // start-sanitize-tx19
3585 *tx19:
3586 // end-sanitize-tx19
3587 {
3588   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3589 }
3590
3591
3592 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3593 {
3594   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3595   address_word reverseendian = (ReverseEndian ? -1 : 0);
3596   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3597   unsigned int byte;
3598   address_word paddr;
3599   int uncached;
3600   unsigned64 memval;
3601   address_word vaddr;
3602
3603   vaddr = base + offset;
3604   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3605   paddr = (paddr ^ (reverseendian & mask));
3606   if (BigEndianMem != 0)
3607     paddr &= ~access;
3608   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3609   memval = (rt << (byte * 8));
3610   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3611 }
3612
3613 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3614 "swr r<RT>, <OFFSET>(r<BASE>)"
3615 *mipsI,mipsII,mipsIII,mipsIV:
3616 *vr4100:
3617 *vr5000:
3618 // start-sanitize-vr4320
3619 *vr4320:
3620 // end-sanitize-vr4320
3621 // start-sanitize-cygnus
3622 *vr5400:
3623 // end-sanitize-cygnus
3624 // start-sanitize-r5900
3625 *r5900:
3626 // end-sanitize-r5900
3627 *r3900:
3628 // start-sanitize-tx19
3629 *tx19:
3630 // end-sanitize-tx19
3631 {
3632   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3633 }
3634
3635
3636 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3637 "sync":STYPE == 0
3638 "sync <STYPE>"
3639 *mipsII:
3640 *mipsIII:
3641 *mipsIV:
3642 *vr4100:
3643 *vr5000:
3644 // start-sanitize-vr4320
3645 *vr4320:
3646 // end-sanitize-vr4320
3647 // start-sanitize-cygnus
3648 *vr5400:
3649 // end-sanitize-cygnus
3650 // start-sanitize-r5900
3651 *r5900:
3652 // end-sanitize-r5900
3653 *r3900:
3654 // start-sanitize-tx19
3655 *tx19:
3656 // end-sanitize-tx19
3657 {
3658   SyncOperation (STYPE);
3659 }
3660
3661
3662 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3663 "syscall <CODE>"
3664 *mipsI,mipsII,mipsIII,mipsIV:
3665 *vr4100:
3666 *vr5000:
3667 // start-sanitize-vr4320
3668 *vr4320:
3669 // end-sanitize-vr4320
3670 // start-sanitize-cygnus
3671 *vr5400:
3672 // end-sanitize-cygnus
3673 // start-sanitize-r5900
3674 *r5900:
3675 // end-sanitize-r5900
3676 *r3900:
3677 // start-sanitize-tx19
3678 *tx19:
3679 // end-sanitize-tx19
3680 {
3681   SignalException(SystemCall, instruction_0);
3682 }
3683
3684
3685 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3686 "teq r<RS>, r<RT>"
3687 *mipsII:
3688 *mipsIII:
3689 *mipsIV:
3690 *vr4100:
3691 *vr5000:
3692 // start-sanitize-vr4320
3693 *vr4320:
3694 // end-sanitize-vr4320
3695 // start-sanitize-cygnus
3696 *vr5400:
3697 // end-sanitize-cygnus
3698 // start-sanitize-r5900
3699 *r5900:
3700 // end-sanitize-r5900
3701 // start-sanitize-tx19
3702 *tx19:
3703 // end-sanitize-tx19
3704 {
3705   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3706     SignalException(Trap, instruction_0);
3707 }
3708
3709
3710 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3711 "teqi r<RS>, <IMMEDIATE>"
3712 *mipsII:
3713 *mipsIII:
3714 *mipsIV:
3715 *vr4100:
3716 *vr5000:
3717 // start-sanitize-vr4320
3718 *vr4320:
3719 // end-sanitize-vr4320
3720 // start-sanitize-cygnus
3721 *vr5400:
3722 // end-sanitize-cygnus
3723 // start-sanitize-r5900
3724 *r5900:
3725 // end-sanitize-r5900
3726 // start-sanitize-tx19
3727 *tx19:
3728 // end-sanitize-tx19
3729 {
3730   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3731     SignalException(Trap, instruction_0);
3732 }
3733
3734
3735 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3736 "tge r<RS>, r<RT>"
3737 *mipsII:
3738 *mipsIII:
3739 *mipsIV:
3740 *vr4100:
3741 *vr5000:
3742 // start-sanitize-vr4320
3743 *vr4320:
3744 // end-sanitize-vr4320
3745 // start-sanitize-cygnus
3746 *vr5400:
3747 // end-sanitize-cygnus
3748 // start-sanitize-r5900
3749 *r5900:
3750 // end-sanitize-r5900
3751 // start-sanitize-tx19
3752 *tx19:
3753 // end-sanitize-tx19
3754 {
3755   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3756     SignalException(Trap, instruction_0);
3757 }
3758
3759
3760 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3761 "tgei r<RS>, <IMMEDIATE>"
3762 *mipsII:
3763 *mipsIII:
3764 *mipsIV:
3765 *vr4100:
3766 *vr5000:
3767 // start-sanitize-vr4320
3768 *vr4320:
3769 // end-sanitize-vr4320
3770 // start-sanitize-cygnus
3771 *vr5400:
3772 // end-sanitize-cygnus
3773 // start-sanitize-r5900
3774 *r5900:
3775 // end-sanitize-r5900
3776 // start-sanitize-tx19
3777 *tx19:
3778 // end-sanitize-tx19
3779 {
3780   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3781     SignalException(Trap, instruction_0);
3782 }
3783
3784
3785 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3786 "tgeiu r<RS>, <IMMEDIATE>"
3787 *mipsII:
3788 *mipsIII:
3789 *mipsIV:
3790 *vr4100:
3791 *vr5000:
3792 // start-sanitize-vr4320
3793 *vr4320:
3794 // end-sanitize-vr4320
3795 // start-sanitize-cygnus
3796 *vr5400:
3797 // end-sanitize-cygnus
3798 // start-sanitize-r5900
3799 *r5900:
3800 // end-sanitize-r5900
3801 // start-sanitize-tx19
3802 *tx19:
3803 // end-sanitize-tx19
3804 {
3805   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3806     SignalException(Trap, instruction_0);
3807 }
3808
3809
3810 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3811 "tgeu r<RS>, r<RT>"
3812 *mipsII:
3813 *mipsIII:
3814 *mipsIV:
3815 *vr4100:
3816 *vr5000:
3817 // start-sanitize-vr4320
3818 *vr4320:
3819 // end-sanitize-vr4320
3820 // start-sanitize-cygnus
3821 *vr5400:
3822 // end-sanitize-cygnus
3823 // start-sanitize-r5900
3824 *r5900:
3825 // end-sanitize-r5900
3826 // start-sanitize-tx19
3827 *tx19:
3828 // end-sanitize-tx19
3829 {
3830   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3831     SignalException(Trap, instruction_0);
3832 }
3833
3834
3835 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3836 "tlt r<RS>, r<RT>"
3837 *mipsII:
3838 *mipsIII:
3839 *mipsIV:
3840 *vr4100:
3841 *vr5000:
3842 // start-sanitize-vr4320
3843 *vr4320:
3844 // end-sanitize-vr4320
3845 // start-sanitize-cygnus
3846 *vr5400:
3847 // end-sanitize-cygnus
3848 // start-sanitize-r5900
3849 *r5900:
3850 // end-sanitize-r5900
3851 // start-sanitize-tx19
3852 *tx19:
3853 // end-sanitize-tx19
3854 {
3855   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3856     SignalException(Trap, instruction_0);
3857 }
3858
3859
3860 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3861 "tlti r<RS>, <IMMEDIATE>"
3862 *mipsII:
3863 *mipsIII:
3864 *mipsIV:
3865 *vr4100:
3866 *vr5000:
3867 // start-sanitize-vr4320
3868 *vr4320:
3869 // end-sanitize-vr4320
3870 // start-sanitize-cygnus
3871 *vr5400:
3872 // end-sanitize-cygnus
3873 // start-sanitize-r5900
3874 *r5900:
3875 // end-sanitize-r5900
3876 // start-sanitize-tx19
3877 *tx19:
3878 // end-sanitize-tx19
3879 {
3880   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3881     SignalException(Trap, instruction_0);
3882 }
3883
3884
3885 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3886 "tltiu r<RS>, <IMMEDIATE>"
3887 *mipsII:
3888 *mipsIII:
3889 *mipsIV:
3890 *vr4100:
3891 *vr5000:
3892 // start-sanitize-vr4320
3893 *vr4320:
3894 // end-sanitize-vr4320
3895 // start-sanitize-cygnus
3896 *vr5400:
3897 // end-sanitize-cygnus
3898 // start-sanitize-r5900
3899 *r5900:
3900 // end-sanitize-r5900
3901 // start-sanitize-tx19
3902 *tx19:
3903 // end-sanitize-tx19
3904 {
3905   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3906     SignalException(Trap, instruction_0);
3907 }
3908
3909
3910 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3911 "tltu r<RS>, r<RT>"
3912 *mipsII:
3913 *mipsIII:
3914 *mipsIV:
3915 *vr4100:
3916 *vr5000:
3917 // start-sanitize-vr4320
3918 *vr4320:
3919 // end-sanitize-vr4320
3920 // start-sanitize-cygnus
3921 *vr5400:
3922 // end-sanitize-cygnus
3923 // start-sanitize-r5900
3924 *r5900:
3925 // end-sanitize-r5900
3926 // start-sanitize-tx19
3927 *tx19:
3928 // end-sanitize-tx19
3929 {
3930   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3931     SignalException(Trap, instruction_0);
3932 }
3933
3934
3935 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3936 "tne r<RS>, r<RT>"
3937 *mipsII:
3938 *mipsIII:
3939 *mipsIV:
3940 *vr4100:
3941 *vr5000:
3942 // start-sanitize-vr4320
3943 *vr4320:
3944 // end-sanitize-vr4320
3945 // start-sanitize-cygnus
3946 *vr5400:
3947 // end-sanitize-cygnus
3948 // start-sanitize-r5900
3949 *r5900:
3950 // end-sanitize-r5900
3951 // start-sanitize-tx19
3952 *tx19:
3953 // end-sanitize-tx19
3954 {
3955   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3956     SignalException(Trap, instruction_0);
3957 }
3958
3959
3960 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3961 "tne r<RS>, <IMMEDIATE>"
3962 *mipsII:
3963 *mipsIII:
3964 *mipsIV:
3965 *vr4100:
3966 *vr5000:
3967 // start-sanitize-vr4320
3968 *vr4320:
3969 // end-sanitize-vr4320
3970 // start-sanitize-cygnus
3971 *vr5400:
3972 // end-sanitize-cygnus
3973 // start-sanitize-r5900
3974 *r5900:
3975 // end-sanitize-r5900
3976 // start-sanitize-tx19
3977 *tx19:
3978 // end-sanitize-tx19
3979 {
3980   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3981     SignalException(Trap, instruction_0);
3982 }
3983
3984
3985 :function:::void:do_xor:int rs, int rt, int rd
3986 {
3987   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3988   GPR[rd] = GPR[rs] ^ GPR[rt];
3989   TRACE_ALU_RESULT (GPR[rd]);
3990 }
3991
3992 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
3993 "xor r<RD>, r<RS>, r<RT>"
3994 *mipsI,mipsII,mipsIII,mipsIV:
3995 *vr4100:
3996 *vr5000:
3997 // start-sanitize-vr4320
3998 *vr4320:
3999 // end-sanitize-vr4320
4000 // start-sanitize-cygnus
4001 *vr5400:
4002 // end-sanitize-cygnus
4003 // start-sanitize-r5900
4004 *r5900:
4005 // end-sanitize-r5900
4006 *r3900:
4007 // start-sanitize-tx19
4008 *tx19:
4009 // end-sanitize-tx19
4010 {
4011   do_xor (SD_, RS, RT, RD);
4012 }
4013
4014
4015 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4016 {
4017   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4018   GPR[rt] = GPR[rs] ^ immediate;
4019   TRACE_ALU_RESULT (GPR[rt]);
4020 }
4021
4022 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4023 "xori r<RT>, r<RS>, <IMMEDIATE>"
4024 *mipsI,mipsII,mipsIII,mipsIV:
4025 *vr4100:
4026 *vr5000:
4027 // start-sanitize-vr4320
4028 *vr4320:
4029 // end-sanitize-vr4320
4030 // start-sanitize-cygnus
4031 *vr5400:
4032 // end-sanitize-cygnus
4033 // start-sanitize-r5900
4034 *r5900:
4035 // end-sanitize-r5900
4036 *r3900:
4037 // start-sanitize-tx19
4038 *tx19:
4039 // end-sanitize-tx19
4040 {
4041   do_xori (SD_, RS, RT, IMMEDIATE);
4042 }
4043
4044 \f
4045 //
4046 // MIPS Architecture:
4047 //
4048 //        FPU Instruction Set (COP1 & COP1X)
4049 //
4050
4051
4052 :%s::::FMT:int fmt
4053 {
4054   switch (fmt)
4055     {
4056     case fmt_single: return "s";
4057     case fmt_double: return "d";
4058     case fmt_word: return "w";
4059     case fmt_long: return "l";
4060     default: return "?";
4061     }
4062 }
4063
4064 :%s::::X:int x
4065 {
4066   switch (x)
4067     {
4068     case 0: return "f";
4069     case 1: return "t";
4070     default: return "?";
4071     }
4072 }
4073
4074 :%s::::TF:int tf
4075 {
4076   if (tf)
4077     return "t";
4078   else
4079     return "f";
4080 }
4081
4082 :%s::::ND:int nd
4083 {
4084   if (nd)
4085     return "l";
4086   else
4087     return "";
4088 }
4089
4090 :%s::::COND:int cond
4091 {
4092   switch (cond)
4093     {
4094     case 00: return "f";
4095     case 01: return "un";
4096     case 02: return "eq";
4097     case 03: return "ueq";
4098     case 04: return "olt";
4099     case 05: return "ult";
4100     case 06: return "ole";
4101     case 07: return "ule";
4102     case 010: return "sf";
4103     case 011: return "ngle";
4104     case 012: return "seq";
4105     case 013: return "ngl";
4106     case 014: return "lt";
4107     case 015: return "nge";
4108     case 016: return "le";
4109     case 017: return "ngt";
4110     default: return "?";
4111     }
4112 }
4113
4114
4115 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4116 "abs.%s<FMT> f<FD>, f<FS>"
4117 *mipsI,mipsII,mipsIII,mipsIV:
4118 *vr4100:
4119 *vr5000:
4120 // start-sanitize-vr4320
4121 *vr4320:
4122 // end-sanitize-vr4320
4123 // start-sanitize-cygnus
4124 *vr5400:
4125 // end-sanitize-cygnus
4126 *r3900:
4127 // start-sanitize-tx19
4128 *tx19:
4129 // end-sanitize-tx19
4130 {
4131   unsigned32 instruction = instruction_0;
4132   int destreg = ((instruction >> 6) & 0x0000001F);
4133   int fs = ((instruction >> 11) & 0x0000001F);
4134   int format = ((instruction >> 21) & 0x00000007);
4135   {
4136     if ((format != fmt_single) && (format != fmt_double))
4137       SignalException(ReservedInstruction,instruction);
4138     else
4139       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
4140   }
4141 }
4142
4143
4144
4145 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4146 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4147 *mipsI,mipsII,mipsIII,mipsIV:
4148 *vr4100:
4149 *vr5000:
4150 // start-sanitize-vr4320
4151 *vr4320:
4152 // end-sanitize-vr4320
4153 // start-sanitize-cygnus
4154 *vr5400:
4155 // end-sanitize-cygnus
4156 *r3900:
4157 // start-sanitize-tx19
4158 *tx19:
4159 // end-sanitize-tx19
4160 {
4161   unsigned32 instruction = instruction_0;
4162   int destreg = ((instruction >> 6) & 0x0000001F);
4163   int fs = ((instruction >> 11) & 0x0000001F);
4164   int ft = ((instruction >> 16) & 0x0000001F);
4165   int format = ((instruction >> 21) & 0x00000007);
4166   {
4167     if ((format != fmt_single) && (format != fmt_double))
4168       SignalException(ReservedInstruction, instruction);
4169     else
4170       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
4171   }
4172 }
4173
4174
4175
4176 // BC1F
4177 // BC1FL
4178 // BC1T
4179 // BC1TL
4180
4181 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4182 "bc1%s<TF>%s<ND> <OFFSET>"
4183 *mipsI,mipsII,mipsIII:
4184 *vr4100:
4185 // start-sanitize-r5900
4186 *r5900:
4187 // end-sanitize-r5900
4188 {
4189   check_branch_bug ();
4190   TRACE_BRANCH_INPUT (PREVCOC1());
4191   if (PREVCOC1() == TF)
4192     {
4193       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4194       TRACE_BRANCH_RESULT (dest);
4195       mark_branch_bug (dest);
4196       DELAY_SLOT (dest);
4197     }
4198   else if (ND)
4199     {
4200       TRACE_BRANCH_RESULT (0);
4201       NULLIFY_NEXT_INSTRUCTION ();
4202     }
4203   else
4204     {
4205       TRACE_BRANCH_RESULT (NIA);
4206     }
4207 }
4208
4209 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1
4210 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4211 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4212 *mipsIV:
4213 *vr5000:
4214 // start-sanitize-vr4320
4215 *vr4320:
4216 // end-sanitize-vr4320
4217 // start-sanitize-cygnus
4218 *vr5400:
4219 // end-sanitize-cygnus
4220 *r3900:
4221 // start-sanitize-tx19
4222 *tx19:
4223 // end-sanitize-tx19
4224 {
4225   check_branch_bug ();
4226   if (GETFCC(CC) == TF)
4227     {
4228       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4229       mark_branch_bug (dest);
4230       DELAY_SLOT (dest);
4231     }
4232   else if (ND)
4233     {
4234       NULLIFY_NEXT_INSTRUCTION ();
4235     }
4236 }
4237
4238
4239
4240
4241
4242
4243 // C.EQ.S
4244 // C.EQ.D
4245 // ...
4246
4247 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
4248 {
4249   if ((fmt != fmt_single) && (fmt != fmt_double))
4250     SignalException (ReservedInstruction, insn);
4251   else
4252     {
4253       int less;
4254       int equal;
4255       int unordered;
4256       int condition;
4257       unsigned64 ofs = ValueFPR (fs, fmt);
4258       unsigned64 oft = ValueFPR (ft, fmt);
4259       if (NaN (ofs, fmt) || NaN (oft, fmt))
4260         {
4261           if (FCSR & FP_ENABLE (IO))
4262             {
4263               FCSR |= FP_CAUSE (IO);
4264               SignalExceptionFPE ();
4265             }
4266           less = 0;
4267           equal = 0;
4268           unordered = 1;
4269         }
4270       else
4271         {
4272           less = Less (ofs, oft, fmt);
4273           equal = Equal (ofs, oft, fmt);
4274           unordered = 0;
4275         }
4276       condition = (((cond & (1 << 2)) && less)
4277                    || ((cond & (1 << 1)) && equal)
4278                    || ((cond & (1 << 0)) && unordered));
4279       SETFCC (cc, condition);
4280     }
4281 }
4282
4283 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmt
4284 *mipsI,mipsII,mipsIII:
4285 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4286 {
4287   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
4288 }
4289
4290 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmt
4291 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4292 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4293 *mipsIV:
4294 *vr4100:
4295 *vr5000:
4296 // start-sanitize-vr4320
4297 *vr4320:
4298 // end-sanitize-vr4320
4299 // start-sanitize-cygnus
4300 *vr5400:
4301 // end-sanitize-cygnus
4302 *r3900:
4303 // start-sanitize-tx19
4304 *tx19:
4305 // end-sanitize-tx19
4306 {
4307   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
4308 }
4309
4310
4311 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
4312 "ceil.l.%s<FMT> f<FD>, f<FS>"
4313 *mipsIII:
4314 *mipsIV:
4315 *vr4100:
4316 *vr5000:
4317 // start-sanitize-vr4320
4318 *vr4320:
4319 // end-sanitize-vr4320
4320 // start-sanitize-cygnus
4321 *vr5400:
4322 // end-sanitize-cygnus
4323 // start-sanitize-r5900
4324 *r5900:
4325 // end-sanitize-r5900
4326 *r3900:
4327 // start-sanitize-tx19
4328 *tx19:
4329 // end-sanitize-tx19
4330 {
4331   unsigned32 instruction = instruction_0;
4332   int destreg = ((instruction >> 6) & 0x0000001F);
4333   int fs = ((instruction >> 11) & 0x0000001F);
4334   int format = ((instruction >> 21) & 0x00000007);
4335   {
4336     if ((format != fmt_single) && (format != fmt_double))
4337       SignalException(ReservedInstruction,instruction);
4338     else
4339       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
4340   }
4341 }
4342
4343
4344 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
4345 *mipsII:
4346 *mipsIII:
4347 *mipsIV:
4348 *vr4100:
4349 *vr5000:
4350 // start-sanitize-vr4320
4351 *vr4320:
4352 // end-sanitize-vr4320
4353 // start-sanitize-cygnus
4354 *vr5400:
4355 // end-sanitize-cygnus
4356 // start-sanitize-r5900
4357 *r5900:
4358 // end-sanitize-r5900
4359 *r3900:
4360 // start-sanitize-tx19
4361 *tx19:
4362 // end-sanitize-tx19
4363 {
4364   unsigned32 instruction = instruction_0;
4365   int destreg = ((instruction >> 6) & 0x0000001F);
4366   int fs = ((instruction >> 11) & 0x0000001F);
4367   int format = ((instruction >> 21) & 0x00000007);
4368   {
4369   if ((format != fmt_single) && (format != fmt_double))
4370    SignalException(ReservedInstruction,instruction);
4371   else
4372    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
4373   }
4374 }
4375
4376
4377 // CFC1
4378 // CTC1
4379 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4380 "c%s<X>c1 r<RT>, f<FS>"
4381 *mipsI:
4382 *mipsII:
4383 *mipsIII:
4384 {
4385   if (X)
4386     {
4387       if (FS == 0)
4388         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
4389       else if (FS == 31)
4390         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
4391       /* else NOP */
4392       PENDING_FILL(COCIDX,0); /* special case */
4393     }
4394   else
4395     { /* control from */
4396       if (FS == 0)
4397         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
4398       else if (FS == 31)
4399         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
4400       /* else NOP */
4401     }
4402 }
4403 010001,00,X,10,5.RT,5.FS,00000000000:COP1S:32::CxC1
4404 "c%s<X>c1 r<RT>, f<FS>"
4405 *mipsIV:
4406 *vr4100:
4407 *vr5000:
4408 // start-sanitize-vr4320
4409 *vr4320:
4410 // end-sanitize-vr4320
4411 // start-sanitize-cygnus
4412 *vr5400:
4413 // end-sanitize-cygnus
4414 *r3900:
4415 // start-sanitize-tx19
4416 *tx19:
4417 // end-sanitize-tx19
4418 {
4419   if (X)
4420     {
4421       /* control to */
4422       TRACE_ALU_INPUT1 (GPR[RT]);
4423       if (FS == 0)
4424         {
4425           FCR0 = VL4_8(GPR[RT]);
4426           TRACE_ALU_RESULT (FCR0);
4427         }
4428       else if (FS == 31)
4429         {
4430           FCR31 = VL4_8(GPR[RT]);
4431           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
4432           TRACE_ALU_RESULT (FCR31);
4433         }
4434       else
4435         {
4436           TRACE_ALU_RESULT0 ();
4437         }
4438       /* else NOP */
4439     }
4440   else
4441     { /* control from */
4442       if (FS == 0)
4443         {
4444           TRACE_ALU_INPUT1 (FCR0);
4445           GPR[RT] = SIGNEXTEND (FCR0, 32);
4446         }
4447       else if (FS == 31)
4448         {
4449           TRACE_ALU_INPUT1 (FCR31);
4450           GPR[RT] = SIGNEXTEND (FCR31, 32);
4451         }
4452       TRACE_ALU_RESULT (GPR[RT]);
4453       /* else NOP */
4454     }
4455 }
4456
4457
4458 //
4459 // FIXME: Does not correctly differentiate between mips*
4460 //
4461 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
4462 "cvt.d.%s<FMT> f<FD>, f<FS>"
4463 *mipsI,mipsII,mipsIII,mipsIV:
4464 *vr4100:
4465 *vr5000:
4466 // start-sanitize-vr4320
4467 *vr4320:
4468 // end-sanitize-vr4320
4469 // start-sanitize-cygnus
4470 *vr5400:
4471 // end-sanitize-cygnus
4472 *r3900:
4473 // start-sanitize-tx19
4474 *tx19:
4475 // end-sanitize-tx19
4476 {
4477   unsigned32 instruction = instruction_0;
4478   int destreg = ((instruction >> 6) & 0x0000001F);
4479   int fs = ((instruction >> 11) & 0x0000001F);
4480   int format = ((instruction >> 21) & 0x00000007);
4481   {
4482     if ((format == fmt_double) | 0)
4483       SignalException(ReservedInstruction,instruction);
4484     else
4485       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
4486   }
4487 }
4488
4489
4490 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
4491 "cvt.l.%s<FMT> f<FD>, f<FS>"
4492 *mipsIII:
4493 *mipsIV:
4494 *vr4100:
4495 *vr5000:
4496 // start-sanitize-vr4320
4497 *vr4320:
4498 // end-sanitize-vr4320
4499 // start-sanitize-cygnus
4500 *vr5400:
4501 // end-sanitize-cygnus
4502 *r3900:
4503 // start-sanitize-tx19
4504 *tx19:
4505 // end-sanitize-tx19
4506 {
4507   unsigned32 instruction = instruction_0;
4508   int destreg = ((instruction >> 6) & 0x0000001F);
4509   int fs = ((instruction >> 11) & 0x0000001F);
4510   int format = ((instruction >> 21) & 0x00000007);
4511   {
4512     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
4513       SignalException(ReservedInstruction,instruction);
4514     else
4515       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
4516   }
4517 }
4518
4519
4520 //
4521 // FIXME: Does not correctly differentiate between mips*
4522 //
4523 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
4524 "cvt.s.%s<FMT> f<FD>, f<FS>"
4525 *mipsI,mipsII,mipsIII,mipsIV:
4526 *vr4100:
4527 *vr5000:
4528 // start-sanitize-vr4320
4529 *vr4320:
4530 // end-sanitize-vr4320
4531 // start-sanitize-cygnus
4532 *vr5400:
4533 // end-sanitize-cygnus
4534 *r3900:
4535 // start-sanitize-tx19
4536 *tx19:
4537 // end-sanitize-tx19
4538 {
4539   unsigned32 instruction = instruction_0;
4540   int destreg = ((instruction >> 6) & 0x0000001F);
4541   int fs = ((instruction >> 11) & 0x0000001F);
4542   int format = ((instruction >> 21) & 0x00000007);
4543   {
4544     if ((format == fmt_single) | 0)
4545       SignalException(ReservedInstruction,instruction);
4546     else
4547       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
4548   }
4549 }
4550
4551
4552 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
4553 "cvt.w.%s<FMT> f<FD>, f<FS>"
4554 *mipsI,mipsII,mipsIII,mipsIV:
4555 *vr4100:
4556 *vr5000:
4557 // start-sanitize-vr4320
4558 *vr4320:
4559 // end-sanitize-vr4320
4560 // start-sanitize-cygnus
4561 *vr5400:
4562 // end-sanitize-cygnus
4563 *r3900:
4564 // start-sanitize-tx19
4565 *tx19:
4566 // end-sanitize-tx19
4567 {
4568   unsigned32 instruction = instruction_0;
4569   int destreg = ((instruction >> 6) & 0x0000001F);
4570   int fs = ((instruction >> 11) & 0x0000001F);
4571   int format = ((instruction >> 21) & 0x00000007);
4572   {
4573     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
4574       SignalException(ReservedInstruction,instruction);
4575     else
4576       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
4577   }
4578 }
4579
4580
4581 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
4582 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4583 *mipsI,mipsII,mipsIII,mipsIV:
4584 *vr4100:
4585 *vr5000:
4586 // start-sanitize-vr4320
4587 *vr4320:
4588 // end-sanitize-vr4320
4589 // start-sanitize-cygnus
4590 *vr5400:
4591 // end-sanitize-cygnus
4592 *r3900:
4593 // start-sanitize-tx19
4594 *tx19:
4595 // end-sanitize-tx19
4596 {
4597   unsigned32 instruction = instruction_0;
4598   int destreg = ((instruction >> 6) & 0x0000001F);
4599   int fs = ((instruction >> 11) & 0x0000001F);
4600   int ft = ((instruction >> 16) & 0x0000001F);
4601   int format = ((instruction >> 21) & 0x00000007);
4602   {
4603     if ((format != fmt_single) && (format != fmt_double))
4604       SignalException(ReservedInstruction,instruction);
4605     else
4606       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
4607   }
4608 }
4609
4610
4611 // DMFC1
4612 // DMTC1
4613 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4614 "dm%s<X>c1 r<RT>, f<FS>"
4615 *mipsIII:
4616 {
4617   if (X)
4618     {
4619       if (SizeFGR() == 64)
4620         PENDING_FILL((FS + FGRIDX),GPR[RT]);
4621       else if ((FS & 0x1) == 0)
4622         {
4623           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
4624           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
4625         }
4626     }
4627   else
4628     {
4629       if (SizeFGR() == 64)
4630         PENDING_FILL(RT,FGR[FS]);
4631       else if ((FS & 0x1) == 0)
4632         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
4633       else
4634         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
4635     }
4636 }
4637 010001,00,X,01,5.RT,5.FS,00000000000:COP1S:64::DMxC1
4638 "dm%s<X>c1 r<RT>, f<FS>"
4639 *mipsIV:
4640 *vr4100:
4641 *vr5000:
4642 // start-sanitize-vr4320
4643 *vr4320:
4644 // end-sanitize-vr4320
4645 // start-sanitize-cygnus
4646 *vr5400:
4647 // end-sanitize-cygnus
4648 // start-sanitize-r5900
4649 *r5900:
4650 // end-sanitize-r5900
4651 *r3900:
4652 // start-sanitize-tx19
4653 *tx19:
4654 // end-sanitize-tx19
4655 {
4656   if (X)
4657     {
4658       if (SizeFGR() == 64)
4659         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4660       else if ((FS & 0x1) == 0)
4661         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
4662     }
4663   else
4664     {
4665       if (SizeFGR() == 64)
4666         GPR[RT] = FGR[FS];
4667       else if ((FS & 0x1) == 0)
4668         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4669       else
4670         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4671     }
4672 }
4673
4674
4675 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
4676 "floor.l.%s<FMT> f<FD>, f<FS>"
4677 *mipsIII:
4678 *mipsIV:
4679 *vr4100:
4680 *vr5000:
4681 // start-sanitize-vr4320
4682 *vr4320:
4683 // end-sanitize-vr4320
4684 // start-sanitize-cygnus
4685 *vr5400:
4686 // end-sanitize-cygnus
4687 // start-sanitize-r5900
4688 *r5900:
4689 // end-sanitize-r5900
4690 *r3900:
4691 // start-sanitize-tx19
4692 *tx19:
4693 // end-sanitize-tx19
4694 {
4695   unsigned32 instruction = instruction_0;
4696   int destreg = ((instruction >> 6) & 0x0000001F);
4697   int fs = ((instruction >> 11) & 0x0000001F);
4698   int format = ((instruction >> 21) & 0x00000007);
4699   {
4700     if ((format != fmt_single) && (format != fmt_double))
4701       SignalException(ReservedInstruction,instruction);
4702     else
4703       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
4704   }
4705 }
4706
4707
4708 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
4709 "floor.w.%s<FMT> f<FD>, f<FS>"
4710 *mipsII:
4711 *mipsIII:
4712 *mipsIV:
4713 *vr4100:
4714 *vr5000:
4715 // start-sanitize-vr4320
4716 *vr4320:
4717 // end-sanitize-vr4320
4718 // start-sanitize-cygnus
4719 *vr5400:
4720 // end-sanitize-cygnus
4721 // start-sanitize-r5900
4722 *r5900:
4723 // end-sanitize-r5900
4724 *r3900:
4725 // start-sanitize-tx19
4726 *tx19:
4727 // end-sanitize-tx19
4728 {
4729   unsigned32 instruction = instruction_0;
4730   int destreg = ((instruction >> 6) & 0x0000001F);
4731   int fs = ((instruction >> 11) & 0x0000001F);
4732   int format = ((instruction >> 21) & 0x00000007);
4733   {
4734     if ((format != fmt_single) && (format != fmt_double))
4735       SignalException(ReservedInstruction,instruction);
4736     else
4737       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
4738   }
4739 }
4740
4741
4742 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
4743 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4744 *mipsII:
4745 *mipsIII:
4746 *mipsIV:
4747 *vr4100:
4748 *vr5000:
4749 // start-sanitize-vr4320
4750 *vr4320:
4751 // end-sanitize-vr4320
4752 // start-sanitize-cygnus
4753 *vr5400:
4754 // end-sanitize-cygnus
4755 *r3900:
4756 // start-sanitize-tx19
4757 *tx19:
4758 // end-sanitize-tx19
4759 {
4760   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4761 }
4762
4763
4764 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
4765 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4766 *mipsIV:
4767 *vr5000:
4768 // start-sanitize-vr4320
4769 *vr4320:
4770 // end-sanitize-vr4320
4771 // start-sanitize-cygnus
4772 *vr5400:
4773 // end-sanitize-cygnus
4774 {
4775   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4776 }
4777
4778
4779
4780 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
4781 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4782 *mipsI,mipsII,mipsIII,mipsIV:
4783 *vr4100:
4784 *vr5000:
4785 // start-sanitize-vr4320
4786 *vr4320:
4787 // end-sanitize-vr4320
4788 // start-sanitize-cygnus
4789 *vr5400:
4790 // end-sanitize-cygnus
4791 // start-sanitize-r5900
4792 *r5900:
4793 // end-sanitize-r5900
4794 *r3900:
4795 // start-sanitize-tx19
4796 *tx19:
4797 // end-sanitize-tx19
4798 {
4799   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4800 }
4801
4802
4803 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
4804 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4805 *mipsIV:
4806 *vr5000:
4807 // start-sanitize-vr4320
4808 *vr4320:
4809 // end-sanitize-vr4320
4810 // start-sanitize-cygnus
4811 *vr5400:
4812 // end-sanitize-cygnus
4813 {
4814   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4815 }
4816
4817
4818
4819 //
4820 // FIXME: Not correct for mips*
4821 //
4822 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
4823 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
4824 *mipsIV:
4825 *vr5000:
4826 // start-sanitize-vr4320
4827 *vr4320:
4828 // end-sanitize-vr4320
4829 // start-sanitize-cygnus
4830 *vr5400:
4831 // end-sanitize-cygnus
4832 {
4833   unsigned32 instruction = instruction_0;
4834   int destreg = ((instruction >> 6) & 0x0000001F);
4835   int fs = ((instruction >> 11) & 0x0000001F);
4836   int ft = ((instruction >> 16) & 0x0000001F);
4837   int fr = ((instruction >> 21) & 0x0000001F);
4838   {
4839     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
4840   }
4841 }
4842
4843
4844 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
4845 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
4846 *mipsIV:
4847 *vr5000:
4848 // start-sanitize-vr4320
4849 *vr4320:
4850 // end-sanitize-vr4320
4851 // start-sanitize-cygnus
4852 *vr5400:
4853 // end-sanitize-cygnus
4854 {
4855   unsigned32 instruction = instruction_0;
4856   int destreg = ((instruction >> 6) & 0x0000001F);
4857   int fs = ((instruction >> 11) & 0x0000001F);
4858   int ft = ((instruction >> 16) & 0x0000001F);
4859   int fr = ((instruction >> 21) & 0x0000001F);
4860   {
4861     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
4862   }
4863 }
4864
4865
4866 // MFC1
4867 // MTC1
4868 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4869 "m%s<X>c1 r<RT>, f<FS>"
4870 *mipsI:
4871 *mipsII:
4872 *mipsIII:
4873 {
4874   if (X)
4875     { /*MTC1*/
4876       if (SizeFGR() == 64)
4877         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
4878       else
4879         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
4880     }
4881   else /*MFC1*/
4882     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
4883 }
4884 010001,00,X,00,5.RT,5.FS,00000000000:COP1S:32::MxC1
4885 "m%s<X>c1 r<RT>, f<FS>"
4886 *mipsIV:
4887 *vr4100:
4888 *vr5000:
4889 // start-sanitize-vr4320
4890 *vr4320:
4891 // end-sanitize-vr4320
4892 // start-sanitize-cygnus
4893 *vr5400:
4894 // end-sanitize-cygnus
4895 *r3900:
4896 // start-sanitize-tx19
4897 *tx19:
4898 // end-sanitize-tx19
4899 {
4900   if (X)
4901     /*MTC1*/
4902     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4903   else /*MFC1*/
4904     GPR[RT] = SIGNEXTEND(FGR[FS],32);
4905 }
4906
4907
4908 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
4909 "mov.%s<FMT> f<FD>, f<FS>"
4910 *mipsI,mipsII,mipsIII,mipsIV:
4911 *vr4100:
4912 *vr5000:
4913 // start-sanitize-vr4320
4914 *vr4320:
4915 // end-sanitize-vr4320
4916 // start-sanitize-cygnus
4917 *vr5400:
4918 // end-sanitize-cygnus
4919 *r3900:
4920 // start-sanitize-tx19
4921 *tx19:
4922 // end-sanitize-tx19
4923 {
4924   unsigned32 instruction = instruction_0;
4925   int destreg = ((instruction >> 6) & 0x0000001F);
4926   int fs = ((instruction >> 11) & 0x0000001F);
4927   int format = ((instruction >> 21) & 0x00000007);
4928   {
4929     StoreFPR(destreg,format,ValueFPR(fs,format));
4930   }
4931 }
4932
4933
4934 // MOVF
4935 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
4936 "mov%s<TF> r<RD>, r<RS>, <CC>"
4937 *mipsIV:
4938 *vr5000:
4939 // start-sanitize-vr4320
4940 *vr4320:
4941 // end-sanitize-vr4320
4942 // start-sanitize-cygnus
4943 *vr5400:
4944 // end-sanitize-cygnus
4945 // start-sanitize-r5900
4946 *r5900:
4947 // end-sanitize-r5900
4948 {
4949   if (GETFCC(CC) == TF)
4950     GPR[RD] = GPR[RS];
4951 }
4952
4953
4954 // MOVF.fmt
4955 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
4956 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4957 *mipsIV:
4958 *vr5000:
4959 // start-sanitize-vr4320
4960 *vr4320:
4961 // end-sanitize-vr4320
4962 // start-sanitize-cygnus
4963 *vr5400:
4964 // end-sanitize-cygnus
4965 // start-sanitize-r5900
4966 *r5900:
4967 // end-sanitize-r5900
4968 {
4969   unsigned32 instruction = instruction_0;
4970   int format = ((instruction >> 21) & 0x00000007);
4971   {
4972    if (GETFCC(CC) == TF)
4973      StoreFPR (FD, format, ValueFPR (FS, format));
4974    else
4975      StoreFPR (FD, format, ValueFPR (FD, format));
4976   }
4977 }
4978
4979
4980 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
4981 *mipsIV:
4982 *vr5000:
4983 // start-sanitize-vr4320
4984 *vr4320:
4985 // end-sanitize-vr4320
4986 // start-sanitize-cygnus
4987 *vr5400:
4988 // end-sanitize-cygnus
4989 // start-sanitize-r5900
4990 *r5900:
4991 // end-sanitize-r5900
4992 {
4993   unsigned32 instruction = instruction_0;
4994   int destreg = ((instruction >> 6) & 0x0000001F);
4995   int fs = ((instruction >> 11) & 0x0000001F);
4996   int format = ((instruction >> 21) & 0x00000007);
4997   {
4998     StoreFPR(destreg,format,ValueFPR(fs,format));
4999   }
5000 }
5001
5002
5003 // MOVT see MOVtf
5004
5005
5006 // MOVT.fmt see MOVtf.fmt
5007
5008
5009
5010 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
5011 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5012 *mipsIV:
5013 *vr5000:
5014 // start-sanitize-vr4320
5015 *vr4320:
5016 // end-sanitize-vr4320
5017 // start-sanitize-cygnus
5018 *vr5400:
5019 // end-sanitize-cygnus
5020 // start-sanitize-r5900
5021 *r5900:
5022 // end-sanitize-r5900
5023 {
5024   unsigned32 instruction = instruction_0;
5025   int destreg = ((instruction >> 6) & 0x0000001F);
5026   int fs = ((instruction >> 11) & 0x0000001F);
5027   int format = ((instruction >> 21) & 0x00000007);
5028   {
5029    StoreFPR(destreg,format,ValueFPR(fs,format));
5030   }
5031 }
5032
5033
5034 // MSUB.fmt
5035 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
5036 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
5037 *mipsIV:
5038 *vr5000:
5039 // start-sanitize-vr4320
5040 *vr4320:
5041 // end-sanitize-vr4320
5042 // start-sanitize-cygnus
5043 *vr5400:
5044 // end-sanitize-cygnus
5045 // start-sanitize-r5900
5046 *r5900:
5047 // end-sanitize-r5900
5048 {
5049   unsigned32 instruction = instruction_0;
5050   int destreg = ((instruction >> 6) & 0x0000001F);
5051   int fs = ((instruction >> 11) & 0x0000001F);
5052   int ft = ((instruction >> 16) & 0x0000001F);
5053   int fr = ((instruction >> 21) & 0x0000001F);
5054   {
5055     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
5056   }
5057 }
5058
5059
5060 // MSUB.fmt
5061 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
5062 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
5063 *mipsIV:
5064 *vr5000:
5065 // start-sanitize-vr4320
5066 *vr4320:
5067 // end-sanitize-vr4320
5068 // start-sanitize-cygnus
5069 *vr5400:
5070 // end-sanitize-cygnus
5071 // start-sanitize-r5900
5072 *r5900:
5073 // end-sanitize-r5900
5074 {
5075   unsigned32 instruction = instruction_0;
5076   int destreg = ((instruction >> 6) & 0x0000001F);
5077   int fs = ((instruction >> 11) & 0x0000001F);
5078   int ft = ((instruction >> 16) & 0x0000001F);
5079   int fr = ((instruction >> 21) & 0x0000001F);
5080   {
5081    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
5082   }
5083 }
5084
5085
5086 // MTC1 see MxC1
5087
5088
5089 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
5090 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5091 *mipsI,mipsII,mipsIII,mipsIV:
5092 *vr4100:
5093 *vr5000:
5094 // start-sanitize-vr4320
5095 *vr4320:
5096 // end-sanitize-vr4320
5097 // start-sanitize-cygnus
5098 *vr5400:
5099 // end-sanitize-cygnus
5100 *r3900:
5101 // start-sanitize-tx19
5102 *tx19:
5103 // end-sanitize-tx19
5104 {
5105   unsigned32 instruction = instruction_0;
5106   int destreg = ((instruction >> 6) & 0x0000001F);
5107   int fs = ((instruction >> 11) & 0x0000001F);
5108   int ft = ((instruction >> 16) & 0x0000001F);
5109   int format = ((instruction >> 21) & 0x00000007);
5110   {
5111     if ((format != fmt_single) && (format != fmt_double))
5112       SignalException(ReservedInstruction,instruction);
5113     else
5114       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
5115   }
5116 }
5117
5118
5119 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
5120 "neg.%s<FMT> f<FD>, f<FS>"
5121 *mipsI,mipsII,mipsIII,mipsIV:
5122 *vr4100:
5123 *vr5000:
5124 // start-sanitize-vr4320
5125 *vr4320:
5126 // end-sanitize-vr4320
5127 // start-sanitize-cygnus
5128 *vr5400:
5129 // end-sanitize-cygnus
5130 *r3900:
5131 // start-sanitize-tx19
5132 *tx19:
5133 // end-sanitize-tx19
5134 {
5135   unsigned32 instruction = instruction_0;
5136   int destreg = ((instruction >> 6) & 0x0000001F);
5137   int fs = ((instruction >> 11) & 0x0000001F);
5138   int format = ((instruction >> 21) & 0x00000007);
5139   {
5140     if ((format != fmt_single) && (format != fmt_double))
5141       SignalException(ReservedInstruction,instruction);
5142     else
5143       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
5144   }
5145 }
5146
5147
5148 // NMADD.fmt
5149 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
5150 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
5151 *mipsIV:
5152 *vr5000:
5153 // start-sanitize-vr4320
5154 *vr4320:
5155 // end-sanitize-vr4320
5156 // start-sanitize-cygnus
5157 *vr5400:
5158 // end-sanitize-cygnus
5159 {
5160   unsigned32 instruction = instruction_0;
5161   int destreg = ((instruction >> 6) & 0x0000001F);
5162   int fs = ((instruction >> 11) & 0x0000001F);
5163   int ft = ((instruction >> 16) & 0x0000001F);
5164   int fr = ((instruction >> 21) & 0x0000001F);
5165   {
5166    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5167   }
5168 }
5169
5170
5171 // NMADD.fmt
5172 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
5173 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
5174 *mipsIV:
5175 *vr5000:
5176 // start-sanitize-vr4320
5177 *vr4320:
5178 // end-sanitize-vr4320
5179 // start-sanitize-cygnus
5180 *vr5400:
5181 // end-sanitize-cygnus
5182 {
5183   unsigned32 instruction = instruction_0;
5184   int destreg = ((instruction >> 6) & 0x0000001F);
5185   int fs = ((instruction >> 11) & 0x0000001F);
5186   int ft = ((instruction >> 16) & 0x0000001F);
5187   int fr = ((instruction >> 21) & 0x0000001F);
5188   {
5189    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5190   }
5191 }
5192
5193
5194 // NMSUB.fmt
5195 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
5196 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
5197 *mipsIV:
5198 *vr5000:
5199 // start-sanitize-vr4320
5200 *vr4320:
5201 // end-sanitize-vr4320
5202 // start-sanitize-cygnus
5203 *vr5400:
5204 // end-sanitize-cygnus
5205 {
5206   unsigned32 instruction = instruction_0;
5207   int destreg = ((instruction >> 6) & 0x0000001F);
5208   int fs = ((instruction >> 11) & 0x0000001F);
5209   int ft = ((instruction >> 16) & 0x0000001F);
5210   int fr = ((instruction >> 21) & 0x0000001F);
5211   {
5212    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
5213   }
5214 }
5215
5216
5217 // NMSUB.fmt
5218 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
5219 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
5220 *mipsIV:
5221 *vr5000:
5222 // start-sanitize-vr4320
5223 *vr4320:
5224 // end-sanitize-vr4320
5225 // start-sanitize-cygnus
5226 *vr5400:
5227 // end-sanitize-cygnus
5228 {
5229   unsigned32 instruction = instruction_0;
5230   int destreg = ((instruction >> 6) & 0x0000001F);
5231   int fs = ((instruction >> 11) & 0x0000001F);
5232   int ft = ((instruction >> 16) & 0x0000001F);
5233   int fr = ((instruction >> 21) & 0x0000001F);
5234   {
5235     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
5236   }
5237 }
5238
5239
5240 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
5241 "prefx <HINT>, r<INDEX>(r<BASE>)"
5242 *mipsIV:
5243 *vr5000:
5244 // start-sanitize-vr4320
5245 *vr4320:
5246 // end-sanitize-vr4320
5247 // start-sanitize-cygnus
5248 *vr5400:
5249 // end-sanitize-cygnus
5250 {
5251   unsigned32 instruction = instruction_0;
5252   int fs = ((instruction >> 11) & 0x0000001F);
5253   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5254   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5255   {
5256     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
5257     address_word paddr;
5258     int uncached;
5259     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5260       Prefetch(uncached,paddr,vaddr,isDATA,fs);
5261   }
5262 }
5263
5264 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
5265 *mipsIV:
5266 "recip.%s<FMT> f<FD>, f<FS>"
5267 *vr5000:
5268 // start-sanitize-vr4320
5269 *vr4320:
5270 // end-sanitize-vr4320
5271 // start-sanitize-cygnus
5272 *vr5400:
5273 // end-sanitize-cygnus
5274 {
5275   unsigned32 instruction = instruction_0;
5276   int destreg = ((instruction >> 6) & 0x0000001F);
5277   int fs = ((instruction >> 11) & 0x0000001F);
5278   int format = ((instruction >> 21) & 0x00000007);
5279   {
5280   if ((format != fmt_single) && (format != fmt_double))
5281    SignalException(ReservedInstruction,instruction);
5282   else
5283    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
5284   }
5285 }
5286
5287
5288 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
5289 "round.l.%s<FMT> f<FD>, f<FS>"
5290 *mipsIII:
5291 *mipsIV:
5292 *vr4100:
5293 *vr5000:
5294 // start-sanitize-vr4320
5295 *vr4320:
5296 // end-sanitize-vr4320
5297 // start-sanitize-cygnus
5298 *vr5400:
5299 // end-sanitize-cygnus
5300 // start-sanitize-r5900
5301 *r5900:
5302 // end-sanitize-r5900
5303 *r3900:
5304 // start-sanitize-tx19
5305 *tx19:
5306 // end-sanitize-tx19
5307 {
5308   unsigned32 instruction = instruction_0;
5309   int destreg = ((instruction >> 6) & 0x0000001F);
5310   int fs = ((instruction >> 11) & 0x0000001F);
5311   int format = ((instruction >> 21) & 0x00000007);
5312   {
5313     if ((format != fmt_single) && (format != fmt_double))
5314       SignalException(ReservedInstruction,instruction);
5315     else
5316       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
5317   }
5318 }
5319
5320
5321 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
5322 "round.w.%s<FMT> f<FD>, f<FS>"
5323 *mipsII:
5324 *mipsIII:
5325 *mipsIV:
5326 *vr4100:
5327 *vr5000:
5328 // start-sanitize-vr4320
5329 *vr4320:
5330 // end-sanitize-vr4320
5331 // start-sanitize-cygnus
5332 *vr5400:
5333 // end-sanitize-cygnus
5334 // start-sanitize-r5900
5335 *r5900:
5336 // end-sanitize-r5900
5337 *r3900:
5338 // start-sanitize-tx19
5339 *tx19:
5340 // end-sanitize-tx19
5341 {
5342   unsigned32 instruction = instruction_0;
5343   int destreg = ((instruction >> 6) & 0x0000001F);
5344   int fs = ((instruction >> 11) & 0x0000001F);
5345   int format = ((instruction >> 21) & 0x00000007);
5346   {
5347   if ((format != fmt_single) && (format != fmt_double))
5348    SignalException(ReservedInstruction,instruction);
5349   else
5350    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
5351   }
5352 }
5353
5354
5355 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
5356 *mipsIV:
5357 "rsqrt.%s<FMT> f<FD>, f<FS>"
5358 *vr5000:
5359 // start-sanitize-vr4320
5360 *vr4320:
5361 // end-sanitize-vr4320
5362 // start-sanitize-cygnus
5363 *vr5400:
5364 // end-sanitize-cygnus
5365 {
5366   unsigned32 instruction = instruction_0;
5367   int destreg = ((instruction >> 6) & 0x0000001F);
5368   int fs = ((instruction >> 11) & 0x0000001F);
5369   int format = ((instruction >> 21) & 0x00000007);
5370   {
5371   if ((format != fmt_single) && (format != fmt_double))
5372    SignalException(ReservedInstruction,instruction);
5373   else
5374    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
5375   }
5376 }
5377
5378
5379 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
5380 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5381 *mipsII:
5382 *mipsIII:
5383 *mipsIV:
5384 *vr4100:
5385 *vr5000:
5386 // start-sanitize-vr4320
5387 *vr4320:
5388 // end-sanitize-vr4320
5389 // start-sanitize-cygnus
5390 *vr5400:
5391 // end-sanitize-cygnus
5392 *r3900:
5393 // start-sanitize-tx19
5394 *tx19:
5395 // end-sanitize-tx19
5396 {
5397   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5398 }
5399
5400
5401 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
5402 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
5403 *mipsIV:
5404 *vr5000:
5405 // start-sanitize-vr4320
5406 *vr4320:
5407 // end-sanitize-vr4320
5408 // start-sanitize-cygnus
5409 *vr5400:
5410 // end-sanitize-cygnus
5411 {
5412   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5413 }
5414
5415
5416 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
5417 "sqrt.%s<FMT> f<FD>, f<FS>"
5418 *mipsII:
5419 *mipsIII:
5420 *mipsIV:
5421 *vr4100:
5422 *vr5000:
5423 // start-sanitize-vr4320
5424 *vr4320:
5425 // end-sanitize-vr4320
5426 // start-sanitize-cygnus
5427 *vr5400:
5428 // end-sanitize-cygnus
5429 *r3900:
5430 // start-sanitize-tx19
5431 *tx19:
5432 // end-sanitize-tx19
5433 {
5434   unsigned32 instruction = instruction_0;
5435   int destreg = ((instruction >> 6) & 0x0000001F);
5436   int fs = ((instruction >> 11) & 0x0000001F);
5437   int format = ((instruction >> 21) & 0x00000007);
5438   {
5439     if ((format != fmt_single) && (format != fmt_double))
5440       SignalException(ReservedInstruction,instruction);
5441     else
5442       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
5443   }
5444 }
5445
5446
5447 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
5448 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5449 *mipsI,mipsII,mipsIII,mipsIV:
5450 *vr4100:
5451 *vr5000:
5452 // start-sanitize-vr4320
5453 *vr4320:
5454 // end-sanitize-vr4320
5455 // start-sanitize-cygnus
5456 *vr5400:
5457 // end-sanitize-cygnus
5458 *r3900:
5459 // start-sanitize-tx19
5460 *tx19:
5461 // end-sanitize-tx19
5462 {
5463   unsigned32 instruction = instruction_0;
5464   int destreg = ((instruction >> 6) & 0x0000001F);
5465   int fs = ((instruction >> 11) & 0x0000001F);
5466   int ft = ((instruction >> 16) & 0x0000001F);
5467   int format = ((instruction >> 21) & 0x00000007);
5468   {
5469     if ((format != fmt_single) && (format != fmt_double))
5470       SignalException(ReservedInstruction,instruction);
5471     else
5472       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
5473   }
5474 }
5475
5476
5477
5478 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
5479 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5480 *mipsI,mipsII,mipsIII,mipsIV:
5481 *vr4100:
5482 *vr5000:
5483 // start-sanitize-vr4320
5484 *vr4320:
5485 // end-sanitize-vr4320
5486 // start-sanitize-cygnus
5487 *vr5400:
5488 // end-sanitize-cygnus
5489 // start-sanitize-r5900
5490 *r5900:
5491 // end-sanitize-r5900
5492 *r3900:
5493 // start-sanitize-tx19
5494 *tx19:
5495 // end-sanitize-tx19
5496 {
5497   unsigned32 instruction = instruction_0;
5498   signed_word offset = EXTEND16 (OFFSET);
5499   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
5500   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
5501   {
5502     address_word vaddr = ((uword64)op1 + offset);
5503     address_word paddr;
5504     int uncached;
5505     if ((vaddr & 3) != 0)
5506       SignalExceptionAddressStore();
5507     else
5508       {
5509         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5510           {
5511             uword64 memval = 0;
5512             uword64 memval1 = 0;
5513             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5514             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5515             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5516             unsigned int byte;
5517             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5518             byte = ((vaddr & mask) ^ bigendiancpu);
5519             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
5520             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5521           }
5522       }
5523   }
5524 }
5525
5526
5527 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
5528 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5529 *mipsIV:
5530 *vr5000:
5531 // start-sanitize-vr4320
5532 *vr4320:
5533 // end-sanitize-vr4320
5534 // start-sanitize-cygnus
5535 *vr5400:
5536 // end-sanitize-cygnus
5537 {
5538   unsigned32 instruction = instruction_0;
5539   int fs = ((instruction >> 11) & 0x0000001F);
5540   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5541   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5542   {
5543    address_word vaddr = ((unsigned64)op1 + op2);
5544    address_word paddr;
5545    int uncached;
5546    if ((vaddr & 3) != 0)
5547     SignalExceptionAddressStore();
5548    else
5549    {
5550     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5551     {
5552      unsigned64 memval = 0;
5553      unsigned64 memval1 = 0;
5554      unsigned64 mask = 0x7;
5555      unsigned int byte;
5556      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5557      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5558      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
5559       {
5560        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5561       }
5562     }
5563    }
5564   }
5565 }
5566
5567
5568 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
5569 "trunc.l.%s<FMT> f<FD>, f<FS>"
5570 *mipsIII:
5571 *mipsIV:
5572 *vr4100:
5573 *vr5000:
5574 // start-sanitize-vr4320
5575 *vr4320:
5576 // end-sanitize-vr4320
5577 // start-sanitize-cygnus
5578 *vr5400:
5579 // end-sanitize-cygnus
5580 // start-sanitize-r5900
5581 *r5900:
5582 // end-sanitize-r5900
5583 *r3900:
5584 // start-sanitize-tx19
5585 *tx19:
5586 // end-sanitize-tx19
5587 {
5588   unsigned32 instruction = instruction_0;
5589   int destreg = ((instruction >> 6) & 0x0000001F);
5590   int fs = ((instruction >> 11) & 0x0000001F);
5591   int format = ((instruction >> 21) & 0x00000007);
5592   {
5593   if ((format != fmt_single) && (format != fmt_double))
5594    SignalException(ReservedInstruction,instruction);
5595   else
5596    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
5597   }
5598 }
5599
5600
5601 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
5602 "trunc.w.%s<FMT> f<FD>, f<FS>"
5603 *mipsII:
5604 *mipsIII:
5605 *mipsIV:
5606 *vr4100:
5607 *vr5000:
5608 // start-sanitize-vr4320
5609 *vr4320:
5610 // end-sanitize-vr4320
5611 // start-sanitize-cygnus
5612 *vr5400:
5613 // end-sanitize-cygnus
5614 // start-sanitize-r5900
5615 *r5900:
5616 // end-sanitize-r5900
5617 *r3900:
5618 // start-sanitize-tx19
5619 *tx19:
5620 // end-sanitize-tx19
5621 {
5622   unsigned32 instruction = instruction_0;
5623   int destreg = ((instruction >> 6) & 0x0000001F);
5624   int fs = ((instruction >> 11) & 0x0000001F);
5625   int format = ((instruction >> 21) & 0x00000007);
5626   {
5627   if ((format != fmt_single) && (format != fmt_double))
5628    SignalException(ReservedInstruction,instruction);
5629   else
5630    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
5631   }
5632 }
5633
5634 \f
5635 //
5636 // MIPS Architecture:
5637 //
5638 //        System Control Instruction Set (COP0)
5639 //
5640
5641
5642 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5643 "bc0f <OFFSET>"
5644 *mipsI,mipsII,mipsIII,mipsIV:
5645 *vr4100:
5646 *vr5000:
5647 // start-sanitize-vr4320
5648 *vr4320:
5649 // end-sanitize-vr4320
5650 // start-sanitize-cygnus
5651 *vr5400:
5652 // end-sanitize-cygnus
5653
5654
5655 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5656 "bc0fl <OFFSET>"
5657 *mipsI,mipsII,mipsIII,mipsIV:
5658 *vr4100:
5659 *vr5000:
5660 // start-sanitize-vr4320
5661 *vr4320:
5662 // end-sanitize-vr4320
5663 // start-sanitize-cygnus
5664 *vr5400:
5665 // end-sanitize-cygnus
5666
5667
5668 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5669 "bc0t <OFFSET>"
5670 *mipsI,mipsII,mipsIII,mipsIV:
5671 *vr4100:
5672
5673
5674 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5675 "bc0tl <OFFSET>"
5676 *mipsI,mipsII,mipsIII,mipsIV:
5677 *vr4100:
5678 *vr5000:
5679 // start-sanitize-vr4320
5680 *vr4320:
5681 // end-sanitize-vr4320
5682 // start-sanitize-cygnus
5683 *vr5400:
5684 // end-sanitize-cygnus
5685
5686
5687 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5688 *mipsIII:
5689 *mipsIV:
5690 *vr4100:
5691 *vr5000:
5692 // start-sanitize-vr4320
5693 *vr4320:
5694 // end-sanitize-vr4320
5695 // start-sanitize-cygnus
5696 *vr5400:
5697 // end-sanitize-cygnus
5698 *r3900:
5699 // start-sanitize-tx19
5700 *tx19:
5701 // end-sanitize-tx19
5702 {
5703   unsigned32 instruction = instruction_0;
5704   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5705   int hint = ((instruction >> 16) & 0x0000001F);
5706   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5707   {
5708     address_word vaddr = (op1 + offset);
5709     address_word paddr;
5710     int uncached;
5711     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5712       CacheOp(hint,vaddr,paddr,instruction);
5713   }
5714 }
5715
5716
5717 010000,10000,000000000000000,111001:COP0:32::DI
5718 "di"
5719 *mipsI,mipsII,mipsIII,mipsIV:
5720 *vr4100:
5721 *vr5000:
5722 // start-sanitize-vr4320
5723 *vr4320:
5724 // end-sanitize-vr4320
5725 // start-sanitize-cygnus
5726 *vr5400:
5727 // end-sanitize-cygnus
5728
5729
5730 010000,10000,000000000000000,111000:COP0:32::EI
5731 "ei"
5732 *mipsI,mipsII,mipsIII,mipsIV:
5733 *vr4100:
5734 *vr5000:
5735 // start-sanitize-vr4320
5736 *vr4320:
5737 // end-sanitize-vr4320
5738 // start-sanitize-cygnus
5739 *vr5400:
5740 // end-sanitize-cygnus
5741
5742
5743 010000,10000,000000000000000,011000:COP0:32::ERET
5744 "eret"
5745 *mipsIII:
5746 *mipsIV:
5747 *vr4100:
5748 *vr5000:
5749 // start-sanitize-vr4320
5750 *vr4320:
5751 // end-sanitize-vr4320
5752 // start-sanitize-cygnus
5753 *vr5400:
5754 // end-sanitize-cygnus
5755 // start-sanitize-r5900
5756 *r5900:
5757 // end-sanitize-r5900
5758 {
5759   if (SR & status_ERL)
5760     {
5761       /* Oops, not yet available */
5762       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5763       NIA = EPC;
5764       SR &= ~status_ERL;
5765     }
5766   else
5767     {
5768       NIA = EPC;
5769       SR &= ~status_EXL;
5770     }
5771 }
5772
5773
5774 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5775 "mfc0 r<RT>, r<RD> # <REGX>"
5776 *mipsI,mipsII,mipsIII,mipsIV:
5777 *r3900:
5778 *vr4100:
5779 *vr5000:
5780 // start-sanitize-vr4320
5781 *vr4320:
5782 // end-sanitize-vr4320
5783 // start-sanitize-cygnus
5784 *vr5400:
5785 // end-sanitize-cygnus
5786 // start-sanitize-r5900
5787 *r5900:
5788 // end-sanitize-r5900
5789 {
5790   TRACE_ALU_INPUT0 ();
5791   DecodeCoproc (instruction_0);
5792   TRACE_ALU_RESULT (GPR[RT]);
5793 }
5794
5795 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5796 "mtc0 r<RT>, r<RD> # <REGX>"
5797 *mipsI,mipsII,mipsIII,mipsIV:
5798 // start-sanitize-tx19
5799 *tx19:
5800 // end-sanitize-tx19
5801 *r3900:
5802 *vr4100:
5803 // start-sanitize-vr4320
5804 *vr4320:
5805 // end-sanitize-vr4320
5806 *vr5000:
5807 // start-sanitize-cygnus
5808 *vr5400:
5809 // end-sanitize-cygnus
5810 // start-sanitize-r5900
5811 *r5900:
5812 // end-sanitize-r5900
5813 {
5814   DecodeCoproc (instruction_0);
5815 }
5816
5817
5818 010000,10000,000000000000000,010000:COP0:32::RFE
5819 "rfe"
5820 *mipsI,mipsII,mipsIII,mipsIV:
5821 // start-sanitize-tx19
5822 *tx19:
5823 // end-sanitize-tx19
5824 *r3900:
5825 *vr4100:
5826 // start-sanitize-vr4320
5827 *vr4320:
5828 // end-sanitize-vr4320
5829 *vr5000:
5830 // start-sanitize-cygnus
5831 *vr5400:
5832 // end-sanitize-cygnus
5833 // start-sanitize-r5900
5834 *r5900:
5835 // end-sanitize-r5900
5836 {
5837   DecodeCoproc (instruction_0);
5838 }
5839
5840
5841 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5842 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5843 *mipsI,mipsII,mipsIII,mipsIV:
5844 *vr4100:
5845 // start-sanitize-r5900
5846 *r5900:
5847 // end-sanitize-r5900
5848 *r3900:
5849 // start-sanitize-tx19
5850 *tx19:
5851 // end-sanitize-tx19
5852 {
5853   DecodeCoproc (instruction_0);
5854 }
5855
5856
5857
5858 010000,10000,000000000000000,001000:COP0:32::TLBP
5859 "tlbp"
5860 *mipsI,mipsII,mipsIII,mipsIV:
5861 *vr4100:
5862 *vr5000:
5863 // start-sanitize-vr4320
5864 *vr4320:
5865 // end-sanitize-vr4320
5866 // start-sanitize-cygnus
5867 *vr5400:
5868 // end-sanitize-cygnus
5869
5870
5871 010000,10000,000000000000000,000001:COP0:32::TLBR
5872 "tlbr"
5873 *mipsI,mipsII,mipsIII,mipsIV:
5874 *vr4100:
5875 *vr5000:
5876 // start-sanitize-vr4320
5877 *vr4320:
5878 // end-sanitize-vr4320
5879 // start-sanitize-cygnus
5880 *vr5400:
5881 // end-sanitize-cygnus
5882
5883
5884 010000,10000,000000000000000,000010:COP0:32::TLBWI
5885 "tlbwi"
5886 *mipsI,mipsII,mipsIII,mipsIV:
5887 *vr4100:
5888 *vr5000:
5889 // start-sanitize-vr4320
5890 *vr4320:
5891 // end-sanitize-vr4320
5892 // start-sanitize-cygnus
5893 *vr5400:
5894 // end-sanitize-cygnus
5895
5896
5897 010000,10000,000000000000000,000110:COP0:32::TLBWR
5898 "tlbwr"
5899 *mipsI,mipsII,mipsIII,mipsIV:
5900 *vr4100:
5901 *vr5000:
5902 // start-sanitize-vr4320
5903 *vr4320:
5904 // end-sanitize-vr4320
5905 // start-sanitize-cygnus
5906 *vr5400:
5907 // end-sanitize-cygnus
5908
5909 \f
5910 :include:::m16.igen
5911 // start-sanitize-cygnus
5912 :include:64,f::mdmx.igen
5913 // end-sanitize-cygnus
5914 // start-sanitize-r5900
5915 :include::r5900:r5900.igen
5916 // end-sanitize-r5900
5917 :include:::tx.igen
5918 :include:::vr.igen
5919 \f
5920 // start-sanitize-cygnus-never
5921
5922 // // FIXME FIXME FIXME What is this instruction?
5923 // 111011,5.RS,5.RT,16.OFFSET:NORMAL:32::<INT>
5924 // *mipsI:
5925 // *mipsII:
5926 // *mipsIII:
5927 // *mipsIV:
5928 // // start-sanitize-r5900
5929 // *r5900:
5930 // // end-sanitize-r5900
5931 // *r3900:
5932 // // start-sanitize-tx19
5933 // *tx19:
5934 // // end-sanitize-tx19
5935 // {
5936 //   unsigned32 instruction = instruction_0;
5937 //   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
5938 //   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
5939 //   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
5940 //   {
5941 //     if (CoProcPresent(3))
5942 //       SignalException(CoProcessorUnusable);
5943 //     else
5944 //       SignalException(ReservedInstruction,instruction);
5945 //   }
5946 // }
5947
5948 // end-sanitize-cygnus-never
5949 // start-sanitize-cygnus-never
5950
5951 // // FIXME FIXME FIXME What is this?
5952 // 11100,******,00001:RR:16::SDBBP
5953 // *mips16:
5954 // {
5955 //   unsigned32 instruction = instruction_0;
5956 //   if (have_extendval)
5957 //     SignalException (ReservedInstruction, instruction);
5958 //   {
5959 //     SignalException(DebugBreakPoint,instruction);
5960 //   }
5961 // }
5962
5963 // end-sanitize-cygnus-never
5964 // start-sanitize-cygnus-never
5965
5966 // // FIXME FIXME FIXME What is this?
5967 // 000000,********************,001110:SPECIAL:32::SDBBP
5968 // *r3900:
5969 // {
5970 //   unsigned32 instruction = instruction_0;
5971 //   {
5972 //     SignalException(DebugBreakPoint,instruction);
5973 //   }
5974 // }
5975
5976 // end-sanitize-cygnus-never