sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 // In mips.igen, the semantics for many of the instructions were created
   4 // using code generated by gencode.  Those semantic segments could be
   5 // greatly simplified.
   6 //
   7 //    <insn> ::=
   8 //        <insn-word> { "+" <insn-word> }
   9 //        ":" <format-name>
  10 //        ":" <filter-flags>
  11 //        ":" <options>
  12 //        ":" <name>
  13 //        <nl>
  14 //        { <insn-model> }
  15 //        { <insn-mnemonic> }
  16 //        <code-block>
  17 //
  18
  19
  20 // IGEN config - mips16
  21 // :option:16::insn-bit-size:16
  22 // :option:16::hi-bit-nr:15
  23 :option:16::insn-specifying-widths:true
  24 :option:16::gen-delayed-branch:false
  25
  26 // IGEN config - mips32/64..
  27 // :option:32::insn-bit-size:32
  28 // :option:32::hi-bit-nr:31
  29 :option:32::insn-specifying-widths:true
  30 :option:32::gen-delayed-branch:false
  31
  32
  33 // Generate separate simulators for each target
  34 // :option:::multi-sim:true
  35
  36
  37 // Models known by this simulator
  38 :model:::mipsI:mips3000:
  39 :model:::mipsII:mips6000:
  40 :model:::mipsIII:mips4000:
  41 :model:::mipsIV:mips8000:
  42 :model:::mips16:mips16:
  43 :model:::r3900:mips3900:
  44 :model:::vr4100:mips4100:
  45 :model:::vr5000:mips5000:
  46
  47
  48
  49 // Pseudo instructions known by IGEN
  50 :internal::::illegal:
  51 {
  52   SignalException (ReservedInstruction, 0);
  53 }
  54
  55
  56 // Pseudo instructions known by interp.c
  57 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  58 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  59 "rsvd <OP>"
  60 {
  61   SignalException (ReservedInstruction, instruction_0);
  62 }
  63
  64
  65
  66 // Helper:
  67 //
  68 // Simulate a 32 bit delayslot instruction
  69 //
  70
  71 :function:::address_word:delayslot32:address_word target
  72 {
  73   instruction_word delay_insn;
  74   sim_events_slip (SD, 1);
  75   DSPC = CIA;
  76   CIA = CIA + 4; /* NOTE not mips16 */
  77   STATE |= simDELAYSLOT;
  78   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
  79   idecode_issue (CPU_, delay_insn, (CIA));
  80   STATE &= ~simDELAYSLOT;
  81   return target;
  82 }
  83
  84 :function:::address_word:nullify_next_insn32:
  85 {
  86   sim_events_slip (SD, 1);
  87   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
  88   return CIA + 8;
  89 }
  90
  91 // Helper:
  92 //
  93 // Check that an access to a HI/LO register meets timing requirements
  94 //
  95 // The following requirements exist:
  96 //
  97 //   -  A MT {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
  98 //   -  A OP {HI,LO} update was not immediatly preceeded by a MF {HI,LO} read
  99 //   -  A MF {HI,LO} read was not corrupted by a preceeding MT{LO,HI} update
 100 //      corruption occures when MT{LO,HI} is preceeded by a OP {HI,LO}.
 101 //
 102
 103 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 104 {
 105   if (history->mf.timestamp + 3 > time)
 106     {
 107       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 108                         itable[MY_INDEX].name,
 109                         new, (long) CIA,
 110                         (long) history->mf.cia);
 111       return 0;
 112     }
 113   return 1;
 114 }
 115
 116 :function:::int:check_mt_hilo:hilo_history *history
 117 *mipsI,mipsII,mipsIII,mipsIV:
 118 *vr4100:
 119 *vr5000:
 120 {
 121   signed64 time = sim_events_time (SD);
 122   int ok = check_mf_cycles (SD_, history, time, "MT");
 123   history->mt.timestamp = time;
 124   history->mt.cia = CIA;
 125   return ok;
 126 }
 127
 128 :function:::int:check_mt_hilo:hilo_history *history
 129 *r3900:
 130 {
 131   signed64 time = sim_events_time (SD);
 132   history->mt.timestamp = time;
 133   history->mt.cia = CIA;
 134   return 1;
 135 }
 136
 137
 138 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 139 *mipsI,mipsII,mipsIII,mipsIV:
 140 *vr4100:
 141 *vr5000:
 142 *r3900:
 143 {
 144   signed64 time = sim_events_time (SD);
 145   int ok = 1;
 146   if (peer != NULL
 147       && peer->mt.timestamp > history->op.timestamp
 148       && history->mt.timestamp < history->op.timestamp
 149       && ! (history->mf.timestamp > history->op.timestamp
 150             && history->mf.timestamp < peer->mt.timestamp)
 151       && ! (peer->mf.timestamp > history->op.timestamp
 152             && peer->mf.timestamp < peer->mt.timestamp))
 153     {
 154       /* The peer has been written to since the last OP yet we have
 155          not */
 156       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 157                         itable[MY_INDEX].name,
 158                         (long) CIA,
 159                         (long) history->op.cia,
 160                         (long) peer->mt.cia);
 161       ok = 0;
 162     }
 163   history->mf.timestamp = time;
 164   history->mf.cia = CIA;
 165   return ok;
 166 }
 167
 168
 169
 170 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 171 *mipsI,mipsII,mipsIII,mipsIV:
 172 *vr4100:
 173 *vr5000:
 174 {
 175   signed64 time = sim_events_time (SD);
 176   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 177             && check_mf_cycles (SD_, lo, time, "OP"));
 178   hi->op.timestamp = time;
 179   lo->op.timestamp = time;
 180   hi->op.cia = CIA;
 181   lo->op.cia = CIA;
 182   return ok;
 183 }
 184
 185 // The r3900 mult and multu insns _can_ be exectuted immediatly after
 186 // a mf{hi,lo}
 187 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 188 *r3900:
 189 {
 190   /* FIXME: could record the fact that a stall occured if we want */
 191   signed64 time = sim_events_time (SD);
 192   hi->op.timestamp = time;
 193   lo->op.timestamp = time;
 194   hi->op.cia = CIA;
 195   lo->op.cia = CIA;
 196   return 1;
 197 }
 198
 199
 200 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 201 *mipsI,mipsII,mipsIII,mipsIV:
 202 *vr4100:
 203 *vr5000:
 204 *r3900:
 205 {
 206   signed64 time = sim_events_time (SD);
 207   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 208             && check_mf_cycles (SD_, lo, time, "OP"));
 209   hi->op.timestamp = time;
 210   lo->op.timestamp = time;
 211   hi->op.cia = CIA;
 212   lo->op.cia = CIA;
 213   return ok;
 214 }
 215
 216
 217
 218
 219
 220 //
 221 // Mips Architecture:
 222 //
 223 //        CPU Instruction Set (mipsI - mipsIV)
 224 //
 225
 226
 227
 228 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 229 "add r<RD>, r<RS>, r<RT>"
 230 *mipsI,mipsII,mipsIII,mipsIV:
 231 *vr4100:
 232 *vr5000:
 233 *r3900:
 234 {
 235   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 236   {
 237     ALU32_BEGIN (GPR[RS]);
 238     ALU32_ADD (GPR[RT]);
 239     ALU32_END (GPR[RD]);
 240   }
 241   TRACE_ALU_RESULT (GPR[RD]);
 242 }
 243
 244
 245
 246 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 247 "addi r<RT>, r<RS>, IMMEDIATE"
 248 *mipsI,mipsII,mipsIII,mipsIV:
 249 *vr4100:
 250 *vr5000:
 251 *r3900:
 252 {
 253   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 254   {
 255     ALU32_BEGIN (GPR[RS]);
 256     ALU32_ADD (EXTEND16 (IMMEDIATE));
 257     ALU32_END (GPR[RT]);
 258   }
 259   TRACE_ALU_RESULT (GPR[RT]);
 260 }
 261
 262
 263
 264 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 265 {
 266   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 267   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 268   TRACE_ALU_RESULT (GPR[rt]);
 269 }
 270
 271 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 272 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 273 *mipsI,mipsII,mipsIII,mipsIV:
 274 *vr4100:
 275 *vr5000:
 276 *r3900:
 277 {
 278   do_addiu (SD_, RS, RT, IMMEDIATE);
 279 }
 280
 281
 282
 283 :function:::void:do_addu:int rs, int rt, int rd
 284 {
 285   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 286   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 287   TRACE_ALU_RESULT (GPR[rd]);
 288 }
 289
 290 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 291 "addu r<RD>, r<RS>, r<RT>"
 292 *mipsI,mipsII,mipsIII,mipsIV:
 293 *vr4100:
 294 *vr5000:
 295 *r3900:
 296 {
 297   do_addu (SD_, RS, RT, RD);
 298 }
 299
 300
 301
 302 :function:::void:do_and:int rs, int rt, int rd
 303 {
 304   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 305   GPR[rd] = GPR[rs] & GPR[rt];
 306   TRACE_ALU_RESULT (GPR[rd]);
 307 }
 308
 309 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 310 "and r<RD>, r<RS>, r<RT>"
 311 *mipsI,mipsII,mipsIII,mipsIV:
 312 *vr4100:
 313 *vr5000:
 314 *r3900:
 315 {
 316   do_and (SD_, RS, RT, RD);
 317 }
 318
 319
 320
 321 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 322 "and r<RT>, r<RS>, <IMMEDIATE>"
 323 *mipsI,mipsII,mipsIII,mipsIV:
 324 *vr4100:
 325 *vr5000:
 326 *r3900:
 327 {
 328   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 329   GPR[RT] = GPR[RS] & IMMEDIATE;
 330   TRACE_ALU_RESULT (GPR[RT]);
 331 }
 332
 333
 334
 335 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 336 "beq r<RS>, r<RT>, <OFFSET>"
 337 *mipsI,mipsII,mipsIII,mipsIV:
 338 *vr4100:
 339 *vr5000:
 340 *r3900:
 341 {
 342   address_word offset = EXTEND16 (OFFSET) << 2;
 343   check_branch_bug ();
 344   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 345     {
 346       mark_branch_bug (NIA+offset);
 347       DELAY_SLOT (NIA + offset);
 348     }
 349 }
 350
 351
 352
 353 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 354 "beql r<RS>, r<RT>, <OFFSET>"
 355 *mipsII:
 356 *mipsIII:
 357 *mipsIV:
 358 *vr4100:
 359 *vr5000:
 360 *r3900:
 361 {
 362   address_word offset = EXTEND16 (OFFSET) << 2;
 363   check_branch_bug ();
 364   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 365     {
 366       mark_branch_bug (NIA+offset);
 367       DELAY_SLOT (NIA + offset);
 368     }
 369   else
 370     NULLIFY_NEXT_INSTRUCTION ();
 371 }
 372
 373
 374
 375 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 376 "bgez r<RS>, <OFFSET>"
 377 *mipsI,mipsII,mipsIII,mipsIV:
 378 *vr4100:
 379 *vr5000:
 380 *r3900:
 381 {
 382   address_word offset = EXTEND16 (OFFSET) << 2;
 383   check_branch_bug ();
 384   if ((signed_word) GPR[RS] >= 0)
 385     {
 386       mark_branch_bug (NIA+offset);
 387       DELAY_SLOT (NIA + offset);
 388     }
 389 }
 390
 391
 392
 393 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 394 "bgezal r<RS>, <OFFSET>"
 395 *mipsI,mipsII,mipsIII,mipsIV:
 396 *vr4100:
 397 *vr5000:
 398 *r3900:
 399 {
 400   address_word offset = EXTEND16 (OFFSET) << 2;
 401   check_branch_bug ();
 402   RA = (CIA + 8);
 403   if ((signed_word) GPR[RS] >= 0)
 404     {
 405       mark_branch_bug (NIA+offset);
 406       DELAY_SLOT (NIA + offset);
 407     }
 408 }
 409
 410
 411
 412 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 413 "bgezall r<RS>, <OFFSET>"
 414 *mipsII:
 415 *mipsIII:
 416 *mipsIV:
 417 *vr4100:
 418 *vr5000:
 419 *r3900:
 420 {
 421   address_word offset = EXTEND16 (OFFSET) << 2;
 422   check_branch_bug ();
 423   RA = (CIA + 8);
 424   /* NOTE: The branch occurs AFTER the next instruction has been
 425      executed */
 426   if ((signed_word) GPR[RS] >= 0)
 427     {
 428       mark_branch_bug (NIA+offset);
 429       DELAY_SLOT (NIA + offset);
 430     }
 431   else
 432     NULLIFY_NEXT_INSTRUCTION ();
 433 }
 434
 435
 436
 437 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 438 "bgezl r<RS>, <OFFSET>"
 439 *mipsII:
 440 *mipsIII:
 441 *mipsIV:
 442 *vr4100:
 443 *vr5000:
 444 *r3900:
 445 {
 446   address_word offset = EXTEND16 (OFFSET) << 2;
 447   check_branch_bug ();
 448   if ((signed_word) GPR[RS] >= 0)
 449     {
 450       mark_branch_bug (NIA+offset);
 451       DELAY_SLOT (NIA + offset);
 452     }
 453   else
 454     NULLIFY_NEXT_INSTRUCTION ();
 455 }
 456
 457
 458
 459 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 460 "bgtz r<RS>, <OFFSET>"
 461 *mipsI,mipsII,mipsIII,mipsIV:
 462 *vr4100:
 463 *vr5000:
 464 *r3900:
 465 {
 466   address_word offset = EXTEND16 (OFFSET) << 2;
 467   check_branch_bug ();
 468   if ((signed_word) GPR[RS] > 0)
 469     {
 470       mark_branch_bug (NIA+offset);
 471       DELAY_SLOT (NIA + offset);
 472     }
 473 }
 474
 475
 476
 477 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 478 "bgtzl r<RS>, <OFFSET>"
 479 *mipsII:
 480 *mipsIII:
 481 *mipsIV:
 482 *vr4100:
 483 *vr5000:
 484 *r3900:
 485 {
 486   address_word offset = EXTEND16 (OFFSET) << 2;
 487   check_branch_bug ();
 488   /* NOTE: The branch occurs AFTER the next instruction has been
 489      executed */
 490   if ((signed_word) GPR[RS] > 0)
 491     {
 492       mark_branch_bug (NIA+offset);
 493       DELAY_SLOT (NIA + offset);
 494     }
 495   else
 496     NULLIFY_NEXT_INSTRUCTION ();
 497 }
 498
 499
 500
 501 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 502 "blez r<RS>, <OFFSET>"
 503 *mipsI,mipsII,mipsIII,mipsIV:
 504 *vr4100:
 505 *vr5000:
 506 *r3900:
 507 {
 508   address_word offset = EXTEND16 (OFFSET) << 2;
 509   check_branch_bug ();
 510   /* NOTE: The branch occurs AFTER the next instruction has been
 511      executed */
 512   if ((signed_word) GPR[RS] <= 0)
 513     {
 514       mark_branch_bug (NIA+offset);
 515       DELAY_SLOT (NIA + offset);
 516     }
 517 }
 518
 519
 520
 521 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 522 "bgezl r<RS>, <OFFSET>"
 523 *mipsII:
 524 *mipsIII:
 525 *mipsIV:
 526 *vr4100:
 527 *vr5000:
 528 *r3900:
 529 {
 530   address_word offset = EXTEND16 (OFFSET) << 2;
 531   check_branch_bug ();
 532   if ((signed_word) GPR[RS] <= 0)
 533     {
 534       mark_branch_bug (NIA+offset);
 535       DELAY_SLOT (NIA + offset);
 536     }
 537   else
 538     NULLIFY_NEXT_INSTRUCTION ();
 539 }
 540
 541
 542
 543 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 544 "bltz r<RS>, <OFFSET>"
 545 *mipsI,mipsII,mipsIII,mipsIV:
 546 *vr4100:
 547 *vr5000:
 548 *r3900:
 549 {
 550   address_word offset = EXTEND16 (OFFSET) << 2;
 551   check_branch_bug ();
 552   if ((signed_word) GPR[RS] < 0)
 553     {
 554       mark_branch_bug (NIA+offset);
 555       DELAY_SLOT (NIA + offset);
 556     }
 557 }
 558
 559
 560
 561 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 562 "bltzal r<RS>, <OFFSET>"
 563 *mipsI,mipsII,mipsIII,mipsIV:
 564 *vr4100:
 565 *vr5000:
 566 *r3900:
 567 {
 568   address_word offset = EXTEND16 (OFFSET) << 2;
 569   check_branch_bug ();
 570   RA = (CIA + 8);
 571   /* NOTE: The branch occurs AFTER the next instruction has been
 572      executed */
 573   if ((signed_word) GPR[RS] < 0)
 574     {
 575       mark_branch_bug (NIA+offset);
 576       DELAY_SLOT (NIA + offset);
 577     }
 578 }
 579
 580
 581
 582 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 583 "bltzall r<RS>, <OFFSET>"
 584 *mipsII:
 585 *mipsIII:
 586 *mipsIV:
 587 *vr4100:
 588 *vr5000:
 589 *r3900:
 590 {
 591   address_word offset = EXTEND16 (OFFSET) << 2;
 592   check_branch_bug ();
 593   RA = (CIA + 8);
 594   if ((signed_word) GPR[RS] < 0)
 595     {
 596       mark_branch_bug (NIA+offset);
 597       DELAY_SLOT (NIA + offset);
 598     }
 599   else
 600     NULLIFY_NEXT_INSTRUCTION ();
 601 }
 602
 603
 604
 605 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 606 "bltzl r<RS>, <OFFSET>"
 607 *mipsII:
 608 *mipsIII:
 609 *mipsIV:
 610 *vr4100:
 611 *vr5000:
 612 *r3900:
 613 {
 614   address_word offset = EXTEND16 (OFFSET) << 2;
 615   check_branch_bug ();
 616   /* NOTE: The branch occurs AFTER the next instruction has been
 617      executed */
 618   if ((signed_word) GPR[RS] < 0)
 619     {
 620       mark_branch_bug (NIA+offset);
 621       DELAY_SLOT (NIA + offset);
 622     }
 623   else
 624     NULLIFY_NEXT_INSTRUCTION ();
 625 }
 626
 627
 628
 629 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 630 "bne r<RS>, r<RT>, <OFFSET>"
 631 *mipsI,mipsII,mipsIII,mipsIV:
 632 *vr4100:
 633 *vr5000:
 634 *r3900:
 635 {
 636   address_word offset = EXTEND16 (OFFSET) << 2;
 637   check_branch_bug ();
 638   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 639     {
 640       mark_branch_bug (NIA+offset);
 641       DELAY_SLOT (NIA + offset);
 642     }
 643 }
 644
 645
 646
 647 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 648 "bnel r<RS>, r<RT>, <OFFSET>"
 649 *mipsII:
 650 *mipsIII:
 651 *mipsIV:
 652 *vr4100:
 653 *vr5000:
 654 *r3900:
 655 {
 656   address_word offset = EXTEND16 (OFFSET) << 2;
 657   check_branch_bug ();
 658   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 659     {
 660       mark_branch_bug (NIA+offset);
 661       DELAY_SLOT (NIA + offset);
 662     }
 663   else
 664     NULLIFY_NEXT_INSTRUCTION ();
 665 }
 666
 667
 668
 669 000000,20.CODE,001101:SPECIAL:32::BREAK
 670 "break"
 671 *mipsI,mipsII,mipsIII,mipsIV:
 672 *vr4100:
 673 *vr5000:
 674 *r3900:
 675 {
 676   /* Check for some break instruction which are reserved for use by the simulator.  */
 677   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
 678   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 679       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 680     {
 681       sim_engine_halt (SD, CPU, NULL, cia,
 682                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
 683     }
 684   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
 685            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
 686     {
 687       if (STATE & simDELAYSLOT)
 688         PC = cia - 4; /* reference the branch instruction */
 689       else
 690         PC = cia;
 691       SignalException(BreakPoint, instruction_0);
 692     }
 693
 694   else
 695     {
 696       /* If we get this far, we're not an instruction reserved by the sim.  Raise
 697          the exception. */
 698       SignalException(BreakPoint, instruction_0);
 699     }
 700 }
 701
 702
 703
 704
 705
 706
 707 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
 708 "dadd r<RD>, r<RS>, r<RT>"
 709 *mipsIII:
 710 *mipsIV:
 711 *vr4100:
 712 *vr5000:
 713 {
 714   /* this check's for overflow */
 715   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 716   {
 717     ALU64_BEGIN (GPR[RS]);
 718     ALU64_ADD (GPR[RT]);
 719     ALU64_END (GPR[RD]);
 720   }
 721   TRACE_ALU_RESULT (GPR[RD]);
 722 }
 723
 724
 725
 726 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
 727 "daddi r<RT>, r<RS>, <IMMEDIATE>"
 728 *mipsIII:
 729 *mipsIV:
 730 *vr4100:
 731 *vr5000:
 732 {
 733   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 734   {
 735     ALU64_BEGIN (GPR[RS]);
 736     ALU64_ADD (EXTEND16 (IMMEDIATE));
 737     ALU64_END (GPR[RT]);
 738   }
 739   TRACE_ALU_RESULT (GPR[RT]);
 740 }
 741
 742
 743
 744 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
 745 {
 746   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 747   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
 748   TRACE_ALU_RESULT (GPR[rt]);
 749 }
 750
 751 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
 752 "daddu r<RT>, r<RS>, <IMMEDIATE>"
 753 *mipsIII:
 754 *mipsIV:
 755 *vr4100:
 756 *vr5000:
 757 {
 758   do_daddiu (SD_, RS, RT, IMMEDIATE);
 759 }
 760
 761
 762
 763 :function:::void:do_daddu:int rs, int rt, int rd
 764 {
 765   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 766   GPR[rd] = GPR[rs] + GPR[rt];
 767   TRACE_ALU_RESULT (GPR[rd]);
 768 }
 769
 770 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
 771 "daddu r<RD>, r<RS>, r<RT>"
 772 *mipsIII:
 773 *mipsIV:
 774 *vr4100:
 775 *vr5000:
 776 {
 777   do_daddu (SD_, RS, RT, RD);
 778 }
 779
 780
 781
 782 :function:::void:do_ddiv:int rs, int rt
 783 {
 784   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 785   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 786   {
 787     signed64 n = GPR[rs];
 788     signed64 d = GPR[rt];
 789     signed64 hi;
 790     signed64 lo;
 791     if (d == 0)
 792       {
 793         lo = SIGNED64 (0x8000000000000000);
 794         hi = 0;
 795       }
 796     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
 797       {
 798         lo = SIGNED64 (0x8000000000000000);
 799         hi = 0;
 800       }
 801     else
 802       {
 803         lo = (n / d);
 804         hi = (n % d);
 805       }
 806     HI = hi;
 807     LO = lo;
 808   }
 809   TRACE_ALU_RESULT2 (HI, LO);
 810 }
 811
 812 000000,5.RS,5.RT,0000000000011110:SPECIAL:64::DDIV
 813 "ddiv r<RS>, r<RT>"
 814 *mipsIII:
 815 *mipsIV:
 816 *vr4100:
 817 *vr5000:
 818 {
 819   do_ddiv (SD_, RS, RT);
 820 }
 821
 822
 823
 824 :function:::void:do_ddivu:int rs, int rt
 825 {
 826   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 827   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 828   {
 829     unsigned64 n = GPR[rs];
 830     unsigned64 d = GPR[rt];
 831     unsigned64 hi;
 832     unsigned64 lo;
 833     if (d == 0)
 834       {
 835         lo = SIGNED64 (0x8000000000000000);
 836         hi = 0;
 837       }
 838     else
 839       {
 840         lo = (n / d);
 841         hi = (n % d);
 842       }
 843     HI = hi;
 844     LO = lo;
 845   }
 846   TRACE_ALU_RESULT2 (HI, LO);
 847 }
 848
 849 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
 850 "ddivu r<RS>, r<RT>"
 851 *mipsIII:
 852 *mipsIV:
 853 *vr4100:
 854 *vr5000:
 855 {
 856   do_ddivu (SD_, RS, RT);
 857 }
 858
 859
 860
 861 :function:::void:do_div:int rs, int rt
 862 {
 863   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 864   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 865   {
 866     signed32 n = GPR[rs];
 867     signed32 d = GPR[rt];
 868     if (d == 0)
 869       {
 870         LO = EXTEND32 (0x80000000);
 871         HI = EXTEND32 (0);
 872       }
 873     else if (n == SIGNED32 (0x80000000) && d == -1)
 874       {
 875         LO = EXTEND32 (0x80000000);
 876         HI = EXTEND32 (0);
 877       }
 878     else
 879       {
 880         LO = EXTEND32 (n / d);
 881         HI = EXTEND32 (n % d);
 882       }
 883   }
 884   TRACE_ALU_RESULT2 (HI, LO);
 885 }
 886
 887 000000,5.RS,5.RT,0000000000011010:SPECIAL:32::DIV
 888 "div r<RS>, r<RT>"
 889 *mipsI,mipsII,mipsIII,mipsIV:
 890 *vr4100:
 891 *vr5000:
 892 *r3900:
 893 {
 894   do_div (SD_, RS, RT);
 895 }
 896
 897
 898
 899 :function:::void:do_divu:int rs, int rt
 900 {
 901   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
 902   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 903   {
 904     unsigned32 n = GPR[rs];
 905     unsigned32 d = GPR[rt];
 906     if (d == 0)
 907       {
 908         LO = EXTEND32 (0x80000000);
 909         HI = EXTEND32 (0);
 910       }
 911    else
 912      {
 913        LO = EXTEND32 (n / d);
 914        HI = EXTEND32 (n % d);
 915      }
 916   }
 917   TRACE_ALU_RESULT2 (HI, LO);
 918 }
 919
 920 000000,5.RS,5.RT,0000000000011011:SPECIAL:32::DIVU
 921 "divu r<RS>, r<RT>"
 922 *mipsI,mipsII,mipsIII,mipsIV:
 923 *vr4100:
 924 *vr5000:
 925 *r3900:
 926 {
 927   do_divu (SD_, RS, RT);
 928 }
 929
 930
 931
 932 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
 933 {
 934   unsigned64 lo;
 935   unsigned64 hi;
 936   unsigned64 m00;
 937   unsigned64 m01;
 938   unsigned64 m10;
 939   unsigned64 m11;
 940   unsigned64 mid;
 941   int sign;
 942   unsigned64 op1 = GPR[rs];
 943   unsigned64 op2 = GPR[rt];
 944   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
 945   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 946   /* make signed multiply unsigned */
 947   sign = 0;
 948   if (signed_p)
 949     {
 950       if (op1 < 0)
 951         {
 952           op1 = - op1;
 953           ++sign;
 954         }
 955       if (op2 < 0)
 956         {
 957           op2 = - op2;
 958           ++sign;
 959         }
 960     }
 961   /* multuply out the 4 sub products */
 962   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
 963   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
 964   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
 965   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
 966   /* add the products */
 967   mid = ((unsigned64) VH4_8 (m00)
 968          + (unsigned64) VL4_8 (m10)
 969          + (unsigned64) VL4_8 (m01));
 970   lo = U8_4 (mid, m00);
 971   hi = (m11
 972         + (unsigned64) VH4_8 (mid)
 973         + (unsigned64) VH4_8 (m01)
 974         + (unsigned64) VH4_8 (m10));
 975   /* fix the sign */
 976   if (sign & 1)
 977     {
 978       lo = -lo;
 979       if (lo == 0)
 980         hi = -hi;
 981       else
 982         hi = -hi - 1;
 983     }
 984   /* save the result HI/LO (and a gpr) */
 985   LO = lo;
 986   HI = hi;
 987   if (rd != 0)
 988     GPR[rd] = lo;
 989   TRACE_ALU_RESULT2 (HI, LO);
 990 }
 991
 992 :function:::void:do_dmult:int rs, int rt, int rd
 993 {
 994   do_dmultx (SD_, rs, rt, rd, 1);
 995 }
 996
 997 000000,5.RS,5.RT,0000000000011100:SPECIAL:64::DMULT
 998 "dmult r<RS>, r<RT>"
 999 *mipsIII,mipsIV:
1000 *vr4100:
1001 {
1002   do_dmult (SD_, RS, RT, 0);
1003 }
1004
1005 000000,5.RS,5.RT,5.RD,00000011100:SPECIAL:64::DMULT
1006 "dmult r<RS>, r<RT>":RD == 0
1007 "dmult r<RD>, r<RS>, r<RT>"
1008 *vr5000:
1009 {
1010   do_dmult (SD_, RS, RT, RD);
1011 }
1012
1013
1014
1015 :function:::void:do_dmultu:int rs, int rt, int rd
1016 {
1017   do_dmultx (SD_, rs, rt, rd, 0);
1018 }
1019
1020 000000,5.RS,5.RT,0000000000011101:SPECIAL:64::DMULTU
1021 "dmultu r<RS>, r<RT>"
1022 *mipsIII,mipsIV:
1023 *vr4100:
1024 {
1025   do_dmultu (SD_, RS, RT, 0);
1026 }
1027
1028 000000,5.RS,5.RT,5.RD,00000011101:SPECIAL:64::DMULTU
1029 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1030 "dmultu r<RS>, r<RT>"
1031 *vr5000:
1032 {
1033   do_dmultu (SD_, RS, RT, RD);
1034 }
1035
1036 :function:::void:do_dsll:int rt, int rd, int shift
1037 {
1038   GPR[rd] = GPR[rt] << shift;
1039 }
1040
1041 :function:::void:do_dsllv:int rs, int rt, int rd
1042 {
1043   int s = MASKED64 (GPR[rs], 5, 0);
1044   GPR[rd] = GPR[rt] << s;
1045 }
1046
1047
1048 00000000000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1049 "dsll r<RD>, r<RT>, <SHIFT>"
1050 *mipsIII:
1051 *mipsIV:
1052 *vr4100:
1053 *vr5000:
1054 {
1055   do_dsll (SD_, RT, RD, SHIFT);
1056 }
1057
1058
1059 00000000000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1060 "dsll32 r<RD>, r<RT>, <SHIFT>"
1061 *mipsIII:
1062 *mipsIV:
1063 *vr4100:
1064 *vr5000:
1065 {
1066   int s = 32 + SHIFT;
1067   GPR[RD] = GPR[RT] << s;
1068 }
1069
1070 000000,5.RS,5.RT,5.RD,00000010100:SPECIAL:64::DSLLV
1071 "dsllv r<RD>, r<RT>, r<RS>"
1072 *mipsIII:
1073 *mipsIV:
1074 *vr4100:
1075 *vr5000:
1076 {
1077   do_dsllv (SD_, RS, RT, RD);
1078 }
1079
1080 :function:::void:do_dsra:int rt, int rd, int shift
1081 {
1082   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1083 }
1084
1085
1086 00000000000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1087 "dsra r<RD>, r<RT>, <SHIFT>"
1088 *mipsIII:
1089 *mipsIV:
1090 *vr4100:
1091 *vr5000:
1092 {
1093   do_dsra (SD_, RT, RD, SHIFT);
1094 }
1095
1096
1097 00000000000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1098 "dsra32 r<RT>, r<RD>, <SHIFT>"
1099 *mipsIII:
1100 *mipsIV:
1101 *vr4100:
1102 *vr5000:
1103 {
1104   int s = 32 + SHIFT;
1105   GPR[RD] = ((signed64) GPR[RT]) >> s;
1106 }
1107
1108
1109 :function:::void:do_dsrav:int rs, int rt, int rd
1110 {
1111   int s = MASKED64 (GPR[rs], 5, 0);
1112   TRACE_ALU_INPUT2 (GPR[rt], s);
1113   GPR[rd] = ((signed64) GPR[rt]) >> s;
1114   TRACE_ALU_RESULT (GPR[rd]);
1115 }
1116
1117 000000,5.RS,5.RT,5.RD,00000010111:SPECIAL:64::DSRAV
1118 "dsra32 r<RT>, r<RD>, r<RS>"
1119 *mipsIII:
1120 *mipsIV:
1121 *vr4100:
1122 *vr5000:
1123 {
1124   do_dsrav (SD_, RS, RT, RD);
1125 }
1126
1127 :function:::void:do_dsrl:int rt, int rd, int shift
1128 {
1129   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1130 }
1131
1132
1133 00000000000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1134 "dsrl r<RD>, r<RT>, <SHIFT>"
1135 *mipsIII:
1136 *mipsIV:
1137 *vr4100:
1138 *vr5000:
1139 {
1140   do_dsrl (SD_, RT, RD, SHIFT);
1141 }
1142
1143
1144 00000000000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1145 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1146 *mipsIII:
1147 *mipsIV:
1148 *vr4100:
1149 *vr5000:
1150 {
1151   int s = 32 + SHIFT;
1152   GPR[RD] = (unsigned64) GPR[RT] >> s;
1153 }
1154
1155
1156 :function:::void:do_dsrlv:int rs, int rt, int rd
1157 {
1158   int s = MASKED64 (GPR[rs], 5, 0);
1159   GPR[rd] = (unsigned64) GPR[rt] >> s;
1160 }
1161
1162
1163
1164 000000,5.RS,5.RT,5.RD,00000010110:SPECIAL:64::DSRLV
1165 "dsrl32 r<RD>, r<RT>, r<RS>"
1166 *mipsIII:
1167 *mipsIV:
1168 *vr4100:
1169 *vr5000:
1170 {
1171   do_dsrlv (SD_, RS, RT, RD);
1172 }
1173
1174
1175 000000,5.RS,5.RT,5.RD,00000101110:SPECIAL:64::DSUB
1176 "dsub r<RD>, r<RS>, r<RT>"
1177 *mipsIII:
1178 *mipsIV:
1179 *vr4100:
1180 *vr5000:
1181 {
1182   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1183   {
1184     ALU64_BEGIN (GPR[RS]);
1185     ALU64_SUB (GPR[RT]);
1186     ALU64_END (GPR[RD]);
1187   }
1188   TRACE_ALU_RESULT (GPR[RD]);
1189 }
1190
1191
1192 :function:::void:do_dsubu:int rs, int rt, int rd
1193 {
1194   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1195   GPR[rd] = GPR[rs] - GPR[rt];
1196   TRACE_ALU_RESULT (GPR[rd]);
1197 }
1198
1199 000000,5.RS,5.RT,5.RD,00000101111:SPECIAL:64::DSUBU
1200 "dsubu r<RD>, r<RS>, r<RT>"
1201 *mipsIII:
1202 *mipsIV:
1203 *vr4100:
1204 *vr5000:
1205 {
1206   do_dsubu (SD_, RS, RT, RD);
1207 }
1208
1209
1210 000010,26.INSTR_INDEX:NORMAL:32::J
1211 "j <INSTR_INDEX>"
1212 *mipsI,mipsII,mipsIII,mipsIV:
1213 *vr4100:
1214 *vr5000:
1215 *r3900:
1216 {
1217   /* NOTE: The region used is that of the delay slot NIA and NOT the
1218      current instruction */
1219   address_word region = (NIA & MASK (63, 28));
1220   DELAY_SLOT (region | (INSTR_INDEX << 2));
1221 }
1222
1223
1224 000011,26.INSTR_INDEX:NORMAL:32::JAL
1225 "jal <INSTR_INDEX>"
1226 *mipsI,mipsII,mipsIII,mipsIV:
1227 *vr4100:
1228 *vr5000:
1229 *r3900:
1230 {
1231   /* NOTE: The region used is that of the delay slot and NOT the
1232      current instruction */
1233   address_word region = (NIA & MASK (63, 28));
1234   GPR[31] = CIA + 8;
1235   DELAY_SLOT (region | (INSTR_INDEX << 2));
1236 }
1237
1238 000000,5.RS,00000,5.RD,00000001001:SPECIAL:32::JALR
1239 "jalr r<RS>":RD == 31
1240 "jalr r<RD>, r<RS>"
1241 *mipsI,mipsII,mipsIII,mipsIV:
1242 *vr4100:
1243 *vr5000:
1244 *r3900:
1245 {
1246   address_word temp = GPR[RS];
1247   GPR[RD] = CIA + 8;
1248   DELAY_SLOT (temp);
1249 }
1250
1251
1252 000000,5.RS,000000000000000001000:SPECIAL:32::JR
1253 "jr r<RS>"
1254 *mipsI,mipsII,mipsIII,mipsIV:
1255 *vr4100:
1256 *vr5000:
1257 *r3900:
1258 {
1259   DELAY_SLOT (GPR[RS]);
1260 }
1261
1262
1263 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1264 {
1265   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1266   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1267   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1268   unsigned int byte;
1269   address_word paddr;
1270   int uncached;
1271   unsigned64 memval;
1272   address_word vaddr;
1273
1274   vaddr = base + offset;
1275   if ((vaddr & access) != 0)
1276     {
1277       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1278     }
1279   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1280   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1281   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1282   byte = ((vaddr & mask) ^ bigendiancpu);
1283   return (memval >> (8 * byte));
1284 }
1285
1286
1287 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1288 "lb r<RT>, <OFFSET>(r<BASE>)"
1289 *mipsI,mipsII,mipsIII,mipsIV:
1290 *vr4100:
1291 *vr5000:
1292 *r3900:
1293 {
1294   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1295 }
1296
1297
1298 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1299 "lbu r<RT>, <OFFSET>(r<BASE>)"
1300 *mipsI,mipsII,mipsIII,mipsIV:
1301 *vr4100:
1302 *vr5000:
1303 *r3900:
1304 {
1305   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1306 }
1307
1308
1309 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1310 "ld r<RT>, <OFFSET>(r<BASE>)"
1311 *mipsIII:
1312 *mipsIV:
1313 *vr4100:
1314 *vr5000:
1315 {
1316   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1317 }
1318
1319
1320 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1321 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1322 *mipsII:
1323 *mipsIII:
1324 *mipsIV:
1325 *vr4100:
1326 *vr5000:
1327 *r3900:
1328 {
1329   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1330 }
1331
1332
1333
1334
1335 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1336 "ldl r<RT>, <OFFSET>(r<BASE>)"
1337 *mipsIII:
1338 *mipsIV:
1339 *vr4100:
1340 *vr5000:
1341 {
1342   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1343 }
1344
1345
1346 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1347 "ldr r<RT>, <OFFSET>(r<BASE>)"
1348 *mipsIII:
1349 *mipsIV:
1350 *vr4100:
1351 *vr5000:
1352 {
1353   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1354 }
1355
1356
1357 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
1358 "lh r<RT>, <OFFSET>(r<BASE>)"
1359 *mipsI,mipsII,mipsIII,mipsIV:
1360 *vr4100:
1361 *vr5000:
1362 *r3900:
1363 {
1364   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
1365 }
1366
1367
1368 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
1369 "lhu r<RT>, <OFFSET>(r<BASE>)"
1370 *mipsI,mipsII,mipsIII,mipsIV:
1371 *vr4100:
1372 *vr5000:
1373 *r3900:
1374 {
1375   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
1376 }
1377
1378
1379 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
1380 "ll r<RT>, <OFFSET>(r<BASE>)"
1381 *mipsII:
1382 *mipsIII:
1383 *mipsIV:
1384 *vr4100:
1385 *vr5000:
1386 {
1387   unsigned32 instruction = instruction_0;
1388   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1389   int destreg = ((instruction >> 16) & 0x0000001F);
1390   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1391   {
1392     address_word vaddr = ((unsigned64)op1 + offset);
1393     address_word paddr;
1394     int uncached;
1395     if ((vaddr & 3) != 0)
1396       {
1397         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
1398       }
1399     else
1400       {
1401         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1402           {
1403             unsigned64 memval = 0;
1404             unsigned64 memval1 = 0;
1405             unsigned64 mask = 0x7;
1406             unsigned int shift = 2;
1407             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
1408             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
1409             unsigned int byte;
1410             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
1411             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
1412             byte = ((vaddr & mask) ^ (bigend << shift));
1413             GPR[destreg] = (SIGNEXTEND(((memval >> (8 * byte)) & 0xFFFFFFFF),32));
1414             LLBIT = 1;
1415           }
1416       }
1417   }
1418 }
1419
1420
1421 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
1422 "lld r<RT>, <OFFSET>(r<BASE>)"
1423 *mipsIII:
1424 *mipsIV:
1425 *vr4100:
1426 *vr5000:
1427 {
1428   unsigned32 instruction = instruction_0;
1429   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1430   int destreg = ((instruction >> 16) & 0x0000001F);
1431   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1432   {
1433     address_word vaddr = ((unsigned64)op1 + offset);
1434     address_word paddr;
1435     int uncached;
1436     if ((vaddr & 7) != 0)
1437       {
1438         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
1439       }
1440     else
1441       {
1442         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1443           {
1444             unsigned64 memval = 0;
1445             unsigned64 memval1 = 0;
1446             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
1447             GPR[destreg] = memval;
1448             LLBIT = 1;
1449           }
1450       }
1451   }
1452 }
1453
1454
1455 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
1456 "lui r<RT>, <IMMEDIATE>"
1457 *mipsI,mipsII,mipsIII,mipsIV:
1458 *vr4100:
1459 *vr5000:
1460 *r3900:
1461 {
1462   TRACE_ALU_INPUT1 (IMMEDIATE);
1463   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
1464   TRACE_ALU_RESULT (GPR[RT]);
1465 }
1466
1467
1468 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
1469 "lw r<RT>, <OFFSET>(r<BASE>)"
1470 *mipsI,mipsII,mipsIII,mipsIV:
1471 *vr4100:
1472 *vr5000:
1473 *r3900:
1474 {
1475   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1476 }
1477
1478
1479 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
1480 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1481 *mipsI,mipsII,mipsIII,mipsIV:
1482 *vr4100:
1483 *vr5000:
1484 *r3900:
1485 {
1486   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
1487 }
1488
1489
1490 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1491 {
1492   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1493   address_word reverseendian = (ReverseEndian ? -1 : 0);
1494   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1495   unsigned int byte;
1496   unsigned int word;
1497   address_word paddr;
1498   int uncached;
1499   unsigned64 memval;
1500   address_word vaddr;
1501   int nr_lhs_bits;
1502   int nr_rhs_bits;
1503   unsigned_word lhs_mask;
1504   unsigned_word temp;
1505
1506   vaddr = base + offset;
1507   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1508   paddr = (paddr ^ (reverseendian & mask));
1509   if (BigEndianMem == 0)
1510     paddr = paddr & ~access;
1511
1512   /* compute where within the word/mem we are */
1513   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1514   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1515   nr_lhs_bits = 8 * byte + 8;
1516   nr_rhs_bits = 8 * access - 8 * byte;
1517   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1518
1519   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1520            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1521            (long) ((unsigned64) paddr >> 32), (long) paddr,
1522            word, byte, nr_lhs_bits, nr_rhs_bits); */
1523
1524   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1525   if (word == 0)
1526     {
1527       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1528       temp = (memval << nr_rhs_bits);
1529     }
1530   else
1531     {
1532       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1533       temp = (memval >> nr_lhs_bits);
1534     }
1535   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1536   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1537
1538   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1539            (long) ((unsigned64) memval >> 32), (long) memval,
1540            (long) ((unsigned64) temp >> 32), (long) temp,
1541            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1542            (long) (rt >> 32), (long) rt); */
1543   return rt;
1544 }
1545
1546
1547 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
1548 "lwl r<RT>, <OFFSET>(r<BASE>)"
1549 *mipsI,mipsII,mipsIII,mipsIV:
1550 *vr4100:
1551 *vr5000:
1552 *r3900:
1553 {
1554   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1555 }
1556
1557
1558 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1559 {
1560   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1561   address_word reverseendian = (ReverseEndian ? -1 : 0);
1562   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1563   unsigned int byte;
1564   address_word paddr;
1565   int uncached;
1566   unsigned64 memval;
1567   address_word vaddr;
1568
1569   vaddr = base + offset;
1570   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1571   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1572   paddr = (paddr ^ (reverseendian & mask));
1573   if (BigEndianMem != 0)
1574     paddr = paddr & ~access;
1575   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1576   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1577   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1578   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1579      (long) paddr, byte, (long) paddr, (long) memval); */
1580   {
1581     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1582     rt &= ~screen;
1583     rt |= (memval >> (8 * byte)) & screen;
1584   }
1585   return rt;
1586 }
1587
1588
1589 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
1590 "lwr r<RT>, <OFFSET>(r<BASE>)"
1591 *mipsI,mipsII,mipsIII,mipsIV:
1592 *vr4100:
1593 *vr5000:
1594 *r3900:
1595 {
1596   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
1597 }
1598
1599
1600 100111,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWU
1601 "lwu r<RT>, <OFFSET>(r<BASE>)"
1602 *mipsIII:
1603 *mipsIV:
1604 *vr4100:
1605 *vr5000:
1606 {
1607   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
1608 }
1609
1610
1611 :function:::void:do_mfhi:int rd
1612 {
1613   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
1614   TRACE_ALU_INPUT1 (HI);
1615   GPR[rd] = HI;
1616   TRACE_ALU_RESULT (GPR[rd]);
1617 }
1618
1619 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
1620 "mfhi r<RD>"
1621 *mipsI,mipsII,mipsIII,mipsIV:
1622 *vr4100:
1623 *vr5000:
1624 *r3900:
1625 {
1626   do_mfhi (SD_, RD);
1627 }
1628
1629
1630
1631 :function:::void:do_mflo:int rd
1632 {
1633   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
1634   TRACE_ALU_INPUT1 (LO);
1635   GPR[rd] = LO;
1636   TRACE_ALU_RESULT (GPR[rd]);
1637 }
1638
1639 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
1640 "mflo r<RD>"
1641 *mipsI,mipsII,mipsIII,mipsIV:
1642 *vr4100:
1643 *vr5000:
1644 *r3900:
1645 {
1646   do_mflo (SD_, RD);
1647 }
1648
1649
1650
1651 000000,5.RS,5.RT,5.RD,00000001011:SPECIAL:32::MOVN
1652 "movn r<RD>, r<RS>, r<RT>"
1653 *mipsIV:
1654 *vr5000:
1655 {
1656   if (GPR[RT] != 0)
1657     GPR[RD] = GPR[RS];
1658 }
1659
1660
1661
1662 000000,5.RS,5.RT,5.RD,00000001010:SPECIAL:32::MOVZ
1663 "movz r<RD>, r<RS>, r<RT>"
1664 *mipsIV:
1665 *vr5000:
1666 {
1667   if (GPR[RT] == 0)
1668     GPR[RD] = GPR[RS];
1669 }
1670
1671
1672
1673 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
1674 "mthi r<RS>"
1675 *mipsI,mipsII,mipsIII,mipsIV:
1676 *vr4100:
1677 *vr5000:
1678 *r3900:
1679 {
1680   check_mt_hilo (SD_, HIHISTORY);
1681   HI = GPR[RS];
1682 }
1683
1684
1685
1686 000000,5.RS,000000000000000010011:SPECIAL:32::MTLO
1687 "mtlo r<RS>"
1688 *mipsI,mipsII,mipsIII,mipsIV:
1689 *vr4100:
1690 *vr5000:
1691 *r3900:
1692 {
1693   check_mt_hilo (SD_, LOHISTORY);
1694   LO = GPR[RS];
1695 }
1696
1697
1698
1699 :function:::void:do_mult:int rs, int rt, int rd
1700 {
1701   signed64 prod;
1702   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1703   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1704   prod = (((signed64)(signed32) GPR[rs])
1705           * ((signed64)(signed32) GPR[rt]));
1706   LO = EXTEND32 (VL4_8 (prod));
1707   HI = EXTEND32 (VH4_8 (prod));
1708   if (rd != 0)
1709     GPR[rd] = LO;
1710   TRACE_ALU_RESULT2 (HI, LO);
1711 }
1712
1713 000000,5.RS,5.RT,00000,00000011000:SPECIAL:32::MULT
1714 "mult r<RS>, r<RT>"
1715 *mipsI,mipsII,mipsIII,mipsIV:
1716 *vr4100:
1717 {
1718   do_mult (SD_, RS, RT, 0);
1719 }
1720
1721
1722 000000,5.RS,5.RT,5.RD,00000011000:SPECIAL:32::MULT
1723 "mult r<RS>, r<RT>":RD == 0
1724 "mult r<RD>, r<RS>, r<RT>"
1725 *vr5000:
1726 *r3900:
1727 {
1728   do_mult (SD_, RS, RT, RD);
1729 }
1730
1731
1732 :function:::void:do_multu:int rs, int rt, int rd
1733 {
1734   unsigned64 prod;
1735   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1736   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1737   prod = (((unsigned64)(unsigned32) GPR[rs])
1738           * ((unsigned64)(unsigned32) GPR[rt]));
1739   LO = EXTEND32 (VL4_8 (prod));
1740   HI = EXTEND32 (VH4_8 (prod));
1741   if (rd != 0)
1742     GPR[rd] = LO;
1743   TRACE_ALU_RESULT2 (HI, LO);
1744 }
1745
1746 000000,5.RS,5.RT,00000,00000011001:SPECIAL:32::MULTU
1747 "multu r<RS>, r<RT>"
1748 *mipsI,mipsII,mipsIII,mipsIV:
1749 *vr4100:
1750 {
1751   do_multu (SD_, RS, RT, 0);
1752 }
1753
1754 000000,5.RS,5.RT,5.RD,00000011001:SPECIAL:32::MULTU
1755 "multu r<RS>, r<RT>":RD == 0
1756 "multu r<RD>, r<RS>, r<RT>"
1757 *vr5000:
1758 *r3900:
1759 {
1760   do_multu (SD_, RS, RT, 0);
1761 }
1762
1763
1764 :function:::void:do_nor:int rs, int rt, int rd
1765 {
1766   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1767   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
1768   TRACE_ALU_RESULT (GPR[rd]);
1769 }
1770
1771 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
1772 "nor r<RD>, r<RS>, r<RT>"
1773 *mipsI,mipsII,mipsIII,mipsIV:
1774 *vr4100:
1775 *vr5000:
1776 *r3900:
1777 {
1778   do_nor (SD_, RS, RT, RD);
1779 }
1780
1781
1782 :function:::void:do_or:int rs, int rt, int rd
1783 {
1784   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1785   GPR[rd] = (GPR[rs] | GPR[rt]);
1786   TRACE_ALU_RESULT (GPR[rd]);
1787 }
1788
1789 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
1790 "or r<RD>, r<RS>, r<RT>"
1791 *mipsI,mipsII,mipsIII,mipsIV:
1792 *vr4100:
1793 *vr5000:
1794 *r3900:
1795 {
1796   do_or (SD_, RS, RT, RD);
1797 }
1798
1799
1800
1801 :function:::void:do_ori:int rs, int rt, unsigned immediate
1802 {
1803   TRACE_ALU_INPUT2 (GPR[rs], immediate);
1804   GPR[rt] = (GPR[rs] | immediate);
1805   TRACE_ALU_RESULT (GPR[rt]);
1806 }
1807
1808 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
1809 "ori r<RT>, r<RS>, <IMMEDIATE>"
1810 *mipsI,mipsII,mipsIII,mipsIV:
1811 *vr4100:
1812 *vr5000:
1813 *r3900:
1814 {
1815   do_ori (SD_, RS, RT, IMMEDIATE);
1816 }
1817
1818
1819 110011,5.RS,nnnnn,16.OFFSET:NORMAL:32::PREF
1820 *mipsIV:
1821 *vr5000:
1822 {
1823   unsigned32 instruction = instruction_0;
1824   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1825   int hint = ((instruction >> 16) & 0x0000001F);
1826   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1827   {
1828     address_word vaddr = ((unsigned64)op1 + offset);
1829     address_word paddr;
1830     int uncached;
1831     {
1832       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
1833         Prefetch(uncached,paddr,vaddr,isDATA,hint);
1834     }
1835   }
1836 }
1837
1838 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
1839 {
1840   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1841   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1842   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1843   unsigned int byte;
1844   address_word paddr;
1845   int uncached;
1846   unsigned64 memval;
1847   address_word vaddr;
1848
1849   vaddr = base + offset;
1850   if ((vaddr & access) != 0)
1851     {
1852       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
1853     }
1854   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
1855   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1856   byte = ((vaddr & mask) ^ bigendiancpu);
1857   memval = (word << (8 * byte));
1858   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
1859 }
1860
1861
1862 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
1863 "sb r<RT>, <OFFSET>(r<BASE>)"
1864 *mipsI,mipsII,mipsIII,mipsIV:
1865 *vr4100:
1866 *vr5000:
1867 *r3900:
1868 {
1869   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1870 }
1871
1872
1873 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
1874 "sc r<RT>, <OFFSET>(r<BASE>)"
1875 *mipsII:
1876 *mipsIII:
1877 *mipsIV:
1878 *vr4100:
1879 *vr5000:
1880 {
1881   unsigned32 instruction = instruction_0;
1882   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1883   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1884   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1885   {
1886     address_word vaddr = ((unsigned64)op1 + offset);
1887     address_word paddr;
1888     int uncached;
1889     if ((vaddr & 3) != 0)
1890       {
1891         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
1892       }
1893     else
1894       {
1895         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1896           {
1897             unsigned64 memval = 0;
1898             unsigned64 memval1 = 0;
1899             unsigned64 mask = 0x7;
1900             unsigned int byte;
1901             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
1902             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
1903             memval = ((unsigned64) op2 << (8 * byte));
1904             if (LLBIT)
1905               {
1906                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
1907               }
1908             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1909           }
1910       }
1911   }
1912 }
1913
1914
1915 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
1916 "scd r<RT>, <OFFSET>(r<BASE>)"
1917 *mipsIII:
1918 *mipsIV:
1919 *vr4100:
1920 *vr5000:
1921 {
1922   unsigned32 instruction = instruction_0;
1923   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
1924   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
1925   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
1926   {
1927     address_word vaddr = ((unsigned64)op1 + offset);
1928     address_word paddr;
1929     int uncached;
1930     if ((vaddr & 7) != 0)
1931       {
1932         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
1933       }
1934     else
1935       {
1936         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
1937           {
1938             unsigned64 memval = 0;
1939             unsigned64 memval1 = 0;
1940             memval = op2;
1941             if (LLBIT)
1942               {
1943                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
1944               }
1945             GPR[(instruction >> 16) & 0x0000001F] = LLBIT;
1946           }
1947       }
1948   }
1949 }
1950
1951
1952 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
1953 "sd r<RT>, <OFFSET>(r<BASE>)"
1954 *mipsIII:
1955 *mipsIV:
1956 *vr4100:
1957 *vr5000:
1958 {
1959   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1960 }
1961
1962
1963 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
1964 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1965 *mipsII:
1966 *mipsIII:
1967 *mipsIV:
1968 *vr4100:
1969 *vr5000:
1970 {
1971   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
1972 }
1973
1974
1975 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
1976 "sdl r<RT>, <OFFSET>(r<BASE>)"
1977 *mipsIII:
1978 *mipsIV:
1979 *vr4100:
1980 *vr5000:
1981 {
1982   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1983 }
1984
1985
1986 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
1987 "sdr r<RT>, <OFFSET>(r<BASE>)"
1988 *mipsIII:
1989 *mipsIV:
1990 *vr4100:
1991 *vr5000:
1992 {
1993   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1994 }
1995
1996
1997 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
1998 "sh r<RT>, <OFFSET>(r<BASE>)"
1999 *mipsI,mipsII,mipsIII,mipsIV:
2000 *vr4100:
2001 *vr5000:
2002 *r3900:
2003 {
2004   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2005 }
2006
2007
2008 :function:::void:do_sll:int rt, int rd, int shift
2009 {
2010   unsigned32 temp = (GPR[rt] << shift);
2011   TRACE_ALU_INPUT2 (GPR[rt], shift);
2012   GPR[rd] = EXTEND32 (temp);
2013   TRACE_ALU_RESULT (GPR[rd]);
2014 }
2015
2016 00000000000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLL
2017 "sll r<RD>, r<RT>, <SHIFT>"
2018 *mipsI,mipsII,mipsIII,mipsIV:
2019 *vr4100:
2020 *vr5000:
2021 *r3900:
2022 {
2023   do_sll (SD_, RT, RD, SHIFT);
2024 }
2025
2026
2027 :function:::void:do_sllv:int rs, int rt, int rd
2028 {
2029   int s = MASKED (GPR[rs], 4, 0);
2030   unsigned32 temp = (GPR[rt] << s);
2031   TRACE_ALU_INPUT2 (GPR[rt], s);
2032   GPR[rd] = EXTEND32 (temp);
2033   TRACE_ALU_RESULT (GPR[rd]);
2034 }
2035
2036 000000,5.RS,5.RT,5.RD,00000000100:SPECIAL:32::SLLV
2037 "sllv r<RD>, r<RT>, r<RS>"
2038 *mipsI,mipsII,mipsIII,mipsIV:
2039 *vr4100:
2040 *vr5000:
2041 *r3900:
2042 {
2043   do_sllv (SD_, RS, RT, RD);
2044 }
2045
2046
2047 :function:::void:do_slt:int rs, int rt, int rd
2048 {
2049   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2050   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2051   TRACE_ALU_RESULT (GPR[rd]);
2052 }
2053
2054 000000,5.RS,5.RT,5.RD,00000101010:SPECIAL:32::SLT
2055 "slt r<RD>, r<RS>, r<RT>"
2056 *mipsI,mipsII,mipsIII,mipsIV:
2057 *vr4100:
2058 *vr5000:
2059 *r3900:
2060 {
2061   do_slt (SD_, RS, RT, RD);
2062 }
2063
2064
2065 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2066 {
2067   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2068   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2069   TRACE_ALU_RESULT (GPR[rt]);
2070 }
2071
2072 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2073 "slti r<RT>, r<RS>, <IMMEDIATE>"
2074 *mipsI,mipsII,mipsIII,mipsIV:
2075 *vr4100:
2076 *vr5000:
2077 *r3900:
2078 {
2079   do_slti (SD_, RS, RT, IMMEDIATE);
2080 }
2081
2082
2083 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2084 {
2085   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2086   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2087   TRACE_ALU_RESULT (GPR[rt]);
2088 }
2089
2090 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2091 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2092 *mipsI,mipsII,mipsIII,mipsIV:
2093 *vr4100:
2094 *vr5000:
2095 *r3900:
2096 {
2097   do_sltiu (SD_, RS, RT, IMMEDIATE);
2098 }
2099
2100
2101
2102 :function:::void:do_sltu:int rs, int rt, int rd
2103 {
2104   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2105   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
2106   TRACE_ALU_RESULT (GPR[rd]);
2107 }
2108
2109 000000,5.RS,5.RT,5.RD,00000101011:SPECIAL:32::SLTU
2110 "sltu r<RD>, r<RS>, r<RT>"
2111 *mipsI,mipsII,mipsIII,mipsIV:
2112 *vr4100:
2113 *vr5000:
2114 *r3900:
2115 {
2116   do_sltu (SD_, RS, RT, RD);
2117 }
2118
2119
2120 :function:::void:do_sra:int rt, int rd, int shift
2121 {
2122   signed32 temp = (signed32) GPR[rt] >> shift;
2123   TRACE_ALU_INPUT2 (GPR[rt], shift);
2124   GPR[rd] = EXTEND32 (temp);
2125   TRACE_ALU_RESULT (GPR[rd]);
2126 }
2127
2128 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
2129 "sra r<RD>, r<RT>, <SHIFT>"
2130 *mipsI,mipsII,mipsIII,mipsIV:
2131 *vr4100:
2132 *vr5000:
2133 *r3900:
2134 {
2135   do_sra (SD_, RT, RD, SHIFT);
2136 }
2137
2138
2139
2140 :function:::void:do_srav:int rs, int rt, int rd
2141 {
2142   int s = MASKED (GPR[rs], 4, 0);
2143   signed32 temp = (signed32) GPR[rt] >> s;
2144   TRACE_ALU_INPUT2 (GPR[rt], s);
2145   GPR[rd] = EXTEND32 (temp);
2146   TRACE_ALU_RESULT (GPR[rd]);
2147 }
2148
2149 000000,5.RS,5.RT,5.RD,00000000111:SPECIAL:32::SRAV
2150 "srav r<RD>, r<RT>, r<RS>"
2151 *mipsI,mipsII,mipsIII,mipsIV:
2152 *vr4100:
2153 *vr5000:
2154 *r3900:
2155 {
2156   do_srav (SD_, RS, RT, RD);
2157 }
2158
2159
2160
2161 :function:::void:do_srl:int rt, int rd, int shift
2162 {
2163   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
2164   TRACE_ALU_INPUT2 (GPR[rt], shift);
2165   GPR[rd] = EXTEND32 (temp);
2166   TRACE_ALU_RESULT (GPR[rd]);
2167 }
2168
2169 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
2170 "srl r<RD>, r<RT>, <SHIFT>"
2171 *mipsI,mipsII,mipsIII,mipsIV:
2172 *vr4100:
2173 *vr5000:
2174 *r3900:
2175 {
2176   do_srl (SD_, RT, RD, SHIFT);
2177 }
2178
2179
2180 :function:::void:do_srlv:int rs, int rt, int rd
2181 {
2182   int s = MASKED (GPR[rs], 4, 0);
2183   unsigned32 temp = (unsigned32) GPR[rt] >> s;
2184   TRACE_ALU_INPUT2 (GPR[rt], s);
2185   GPR[rd] = EXTEND32 (temp);
2186   TRACE_ALU_RESULT (GPR[rd]);
2187 }
2188
2189 000000,5.RS,5.RT,5.RD,00000000110:SPECIAL:32::SRLV
2190 "srlv r<RD>, r<RT>, r<RS>"
2191 *mipsI,mipsII,mipsIII,mipsIV:
2192 *vr4100:
2193 *vr5000:
2194 *r3900:
2195 {
2196   do_srlv (SD_, RS, RT, RD);
2197 }
2198
2199
2200 000000,5.RS,5.RT,5.RD,00000100010:SPECIAL:32::SUB
2201 "sub r<RD>, r<RS>, r<RT>"
2202 *mipsI,mipsII,mipsIII,mipsIV:
2203 *vr4100:
2204 *vr5000:
2205 *r3900:
2206 {
2207   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2208   {
2209     ALU32_BEGIN (GPR[RS]);
2210     ALU32_SUB (GPR[RT]);
2211     ALU32_END (GPR[RD]);
2212   }
2213   TRACE_ALU_RESULT (GPR[RD]);
2214 }
2215
2216
2217 :function:::void:do_subu:int rs, int rt, int rd
2218 {
2219   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2220   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
2221   TRACE_ALU_RESULT (GPR[rd]);
2222 }
2223
2224 000000,5.RS,5.RT,5.RD,00000100011:SPECIAL:32::SUBU
2225 "subu r<RD>, r<RS>, r<RT>"
2226 *mipsI,mipsII,mipsIII,mipsIV:
2227 *vr4100:
2228 *vr5000:
2229 *r3900:
2230 {
2231   do_subu (SD_, RS, RT, RD);
2232 }
2233
2234
2235 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
2236 "sw r<RT>, <OFFSET>(r<BASE>)"
2237 *mipsI,mipsII,mipsIII,mipsIV:
2238 *vr4100:
2239 *r3900:
2240 *vr5000:
2241 {
2242   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2243 }
2244
2245
2246 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
2247 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2248 *mipsI,mipsII,mipsIII,mipsIV:
2249 *vr4100:
2250 *vr5000:
2251 *r3900:
2252 {
2253   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
2254 }
2255
2256
2257
2258 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2259 {
2260   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2261   address_word reverseendian = (ReverseEndian ? -1 : 0);
2262   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2263   unsigned int byte;
2264   unsigned int word;
2265   address_word paddr;
2266   int uncached;
2267   unsigned64 memval;
2268   address_word vaddr;
2269   int nr_lhs_bits;
2270   int nr_rhs_bits;
2271
2272   vaddr = base + offset;
2273   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2274   paddr = (paddr ^ (reverseendian & mask));
2275   if (BigEndianMem == 0)
2276     paddr = paddr & ~access;
2277
2278   /* compute where within the word/mem we are */
2279   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2280   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2281   nr_lhs_bits = 8 * byte + 8;
2282   nr_rhs_bits = 8 * access - 8 * byte;
2283   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2284   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2285            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2286            (long) ((unsigned64) paddr >> 32), (long) paddr,
2287            word, byte, nr_lhs_bits, nr_rhs_bits); */
2288
2289   if (word == 0)
2290     {
2291       memval = (rt >> nr_rhs_bits);
2292     }
2293   else
2294     {
2295       memval = (rt << nr_lhs_bits);
2296     }
2297   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2298            (long) ((unsigned64) rt >> 32), (long) rt,
2299            (long) ((unsigned64) memval >> 32), (long) memval); */
2300   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2301 }
2302
2303
2304 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
2305 "swl r<RT>, <OFFSET>(r<BASE>)"
2306 *mipsI,mipsII,mipsIII,mipsIV:
2307 *vr4100:
2308 *vr5000:
2309 *r3900:
2310 {
2311   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2312 }
2313
2314
2315 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2316 {
2317   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2318   address_word reverseendian = (ReverseEndian ? -1 : 0);
2319   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2320   unsigned int byte;
2321   address_word paddr;
2322   int uncached;
2323   unsigned64 memval;
2324   address_word vaddr;
2325
2326   vaddr = base + offset;
2327   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2328   paddr = (paddr ^ (reverseendian & mask));
2329   if (BigEndianMem != 0)
2330     paddr &= ~access;
2331   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2332   memval = (rt << (byte * 8));
2333   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2334 }
2335
2336 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
2337 "swr r<RT>, <OFFSET>(r<BASE>)"
2338 *mipsI,mipsII,mipsIII,mipsIV:
2339 *vr4100:
2340 *vr5000:
2341 *r3900:
2342 {
2343   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2344 }
2345
2346
2347 000000000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
2348 "sync":STYPE == 0
2349 "sync <STYPE>"
2350 *mipsII:
2351 *mipsIII:
2352 *mipsIV:
2353 *vr4100:
2354 *vr5000:
2355 *r3900:
2356 {
2357   SyncOperation (STYPE);
2358 }
2359
2360
2361 000000,20.CODE,001100:SPECIAL:32::SYSCALL
2362 "syscall <CODE>"
2363 *mipsI,mipsII,mipsIII,mipsIV:
2364 *vr4100:
2365 *vr5000:
2366 *r3900:
2367 {
2368   SignalException(SystemCall, instruction_0);
2369 }
2370
2371
2372 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
2373 "teq r<RS>, r<RT>"
2374 *mipsII:
2375 *mipsIII:
2376 *mipsIV:
2377 *vr4100:
2378 *vr5000:
2379 {
2380   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
2381     SignalException(Trap, instruction_0);
2382 }
2383
2384
2385 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
2386 "teqi r<RS>, <IMMEDIATE>"
2387 *mipsII:
2388 *mipsIII:
2389 *mipsIV:
2390 *vr4100:
2391 *vr5000:
2392 {
2393   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
2394     SignalException(Trap, instruction_0);
2395 }
2396
2397
2398 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
2399 "tge r<RS>, r<RT>"
2400 *mipsII:
2401 *mipsIII:
2402 *mipsIV:
2403 *vr4100:
2404 *vr5000:
2405 {
2406   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
2407     SignalException(Trap, instruction_0);
2408 }
2409
2410
2411 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
2412 "tgei r<RS>, <IMMEDIATE>"
2413 *mipsII:
2414 *mipsIII:
2415 *mipsIV:
2416 *vr4100:
2417 *vr5000:
2418 {
2419   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
2420     SignalException(Trap, instruction_0);
2421 }
2422
2423
2424 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
2425 "tgeiu r<RS>, <IMMEDIATE>"
2426 *mipsII:
2427 *mipsIII:
2428 *mipsIV:
2429 *vr4100:
2430 *vr5000:
2431 {
2432   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
2433     SignalException(Trap, instruction_0);
2434 }
2435
2436
2437 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
2438 "tgeu r<RS>, r<RT>"
2439 *mipsII:
2440 *mipsIII:
2441 *mipsIV:
2442 *vr4100:
2443 *vr5000:
2444 {
2445   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
2446     SignalException(Trap, instruction_0);
2447 }
2448
2449
2450 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
2451 "tlt r<RS>, r<RT>"
2452 *mipsII:
2453 *mipsIII:
2454 *mipsIV:
2455 *vr4100:
2456 *vr5000:
2457 {
2458   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
2459     SignalException(Trap, instruction_0);
2460 }
2461
2462
2463 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
2464 "tlti r<RS>, <IMMEDIATE>"
2465 *mipsII:
2466 *mipsIII:
2467 *mipsIV:
2468 *vr4100:
2469 *vr5000:
2470 {
2471   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
2472     SignalException(Trap, instruction_0);
2473 }
2474
2475
2476 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
2477 "tltiu r<RS>, <IMMEDIATE>"
2478 *mipsII:
2479 *mipsIII:
2480 *mipsIV:
2481 *vr4100:
2482 *vr5000:
2483 {
2484   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
2485     SignalException(Trap, instruction_0);
2486 }
2487
2488
2489 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
2490 "tltu r<RS>, r<RT>"
2491 *mipsII:
2492 *mipsIII:
2493 *mipsIV:
2494 *vr4100:
2495 *vr5000:
2496 {
2497   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
2498     SignalException(Trap, instruction_0);
2499 }
2500
2501
2502 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
2503 "tne r<RS>, r<RT>"
2504 *mipsII:
2505 *mipsIII:
2506 *mipsIV:
2507 *vr4100:
2508 *vr5000:
2509 {
2510   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
2511     SignalException(Trap, instruction_0);
2512 }
2513
2514
2515 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
2516 "tne r<RS>, <IMMEDIATE>"
2517 *mipsII:
2518 *mipsIII:
2519 *mipsIV:
2520 *vr4100:
2521 *vr5000:
2522 {
2523   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
2524     SignalException(Trap, instruction_0);
2525 }
2526
2527
2528 :function:::void:do_xor:int rs, int rt, int rd
2529 {
2530   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2531   GPR[rd] = GPR[rs] ^ GPR[rt];
2532   TRACE_ALU_RESULT (GPR[rd]);
2533 }
2534
2535 000000,5.RS,5.RT,5.RD,00000100110:SPECIAL:32::XOR
2536 "xor r<RD>, r<RS>, r<RT>"
2537 *mipsI,mipsII,mipsIII,mipsIV:
2538 *vr4100:
2539 *vr5000:
2540 *r3900:
2541 {
2542   do_xor (SD_, RS, RT, RD);
2543 }
2544
2545
2546 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
2547 {
2548   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2549   GPR[rt] = GPR[rs] ^ immediate;
2550   TRACE_ALU_RESULT (GPR[rt]);
2551 }
2552
2553 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
2554 "xori r<RT>, r<RS>, <IMMEDIATE>"
2555 *mipsI,mipsII,mipsIII,mipsIV:
2556 *vr4100:
2557 *vr5000:
2558 *r3900:
2559 {
2560   do_xori (SD_, RS, RT, IMMEDIATE);
2561 }
2562
2563 \f
2564 //
2565 // MIPS Architecture:
2566 //
2567 //        FPU Instruction Set (COP1 & COP1X)
2568 //
2569
2570
2571 :%s::::FMT:int fmt
2572 {
2573   switch (fmt)
2574     {
2575     case fmt_single: return "s";
2576     case fmt_double: return "d";
2577     case fmt_word: return "w";
2578     case fmt_long: return "l";
2579     default: return "?";
2580     }
2581 }
2582
2583 :%s::::X:int x
2584 {
2585   switch (x)
2586     {
2587     case 0: return "f";
2588     case 1: return "t";
2589     default: return "?";
2590     }
2591 }
2592
2593 :%s::::TF:int tf
2594 {
2595   if (tf)
2596     return "t";
2597   else
2598     return "f";
2599 }
2600
2601 :%s::::ND:int nd
2602 {
2603   if (nd)
2604     return "l";
2605   else
2606     return "";
2607 }
2608
2609 :%s::::COND:int cond
2610 {
2611   switch (cond)
2612     {
2613     case 00: return "f";
2614     case 01: return "un";
2615     case 02: return "eq";
2616     case 03: return "ueq";
2617     case 04: return "olt";
2618     case 05: return "ult";
2619     case 06: return "ole";
2620     case 07: return "ule";
2621     case 010: return "sf";
2622     case 011: return "ngle";
2623     case 012: return "seq";
2624     case 013: return "ngl";
2625     case 014: return "lt";
2626     case 015: return "nge";
2627     case 016: return "le";
2628     case 017: return "ngt";
2629     default: return "?";
2630     }
2631 }
2632
2633
2634 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
2635 "abs.%s<FMT> f<FD>, f<FS>"
2636 *mipsI,mipsII,mipsIII,mipsIV:
2637 *vr4100:
2638 *vr5000:
2639 *r3900:
2640 {
2641   unsigned32 instruction = instruction_0;
2642   int destreg = ((instruction >> 6) & 0x0000001F);
2643   int fs = ((instruction >> 11) & 0x0000001F);
2644   int format = ((instruction >> 21) & 0x00000007);
2645   {
2646     if ((format != fmt_single) && (format != fmt_double))
2647       SignalException(ReservedInstruction,instruction);
2648     else
2649       StoreFPR(destreg,format,AbsoluteValue(ValueFPR(fs,format),format));
2650   }
2651 }
2652
2653
2654
2655 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
2656 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
2657 *mipsI,mipsII,mipsIII,mipsIV:
2658 *vr4100:
2659 *vr5000:
2660 *r3900:
2661 {
2662   unsigned32 instruction = instruction_0;
2663   int destreg = ((instruction >> 6) & 0x0000001F);
2664   int fs = ((instruction >> 11) & 0x0000001F);
2665   int ft = ((instruction >> 16) & 0x0000001F);
2666   int format = ((instruction >> 21) & 0x00000007);
2667   {
2668     if ((format != fmt_single) && (format != fmt_double))
2669       SignalException(ReservedInstruction, instruction);
2670     else
2671       StoreFPR(destreg,format,Add(ValueFPR(fs,format),ValueFPR(ft,format),format));
2672   }
2673 }
2674
2675
2676
2677 // BC1F
2678 // BC1FL
2679 // BC1T
2680 // BC1TL
2681
2682 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
2683 "bc1%s<TF>%s<ND> <OFFSET>"
2684 *mipsI,mipsII,mipsIII:
2685 {
2686   check_branch_bug ();
2687   TRACE_BRANCH_INPUT (PREVCOC1());
2688   if (PREVCOC1() == TF)
2689     {
2690       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2691       TRACE_BRANCH_RESULT (dest);
2692       mark_branch_bug (dest);
2693       DELAY_SLOT (dest);
2694     }
2695   else if (ND)
2696     {
2697       TRACE_BRANCH_RESULT (0);
2698       NULLIFY_NEXT_INSTRUCTION ();
2699     }
2700   else
2701     {
2702       TRACE_BRANCH_RESULT (NIA);
2703     }
2704 }
2705
2706 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
2707 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
2708 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
2709 *mipsIV:
2710 *vr5000:
2711 #*vr4100:
2712 *r3900:
2713 {
2714   check_branch_bug ();
2715   if (GETFCC(CC) == TF)
2716     {
2717       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
2718       mark_branch_bug (dest);
2719       DELAY_SLOT (dest);
2720     }
2721   else if (ND)
2722     {
2723       NULLIFY_NEXT_INSTRUCTION ();
2724     }
2725 }
2726
2727
2728
2729
2730
2731
2732 // C.EQ.S
2733 // C.EQ.D
2734 // ...
2735
2736 :function:::void:do_c_cond_fmt:int fmt, int ft, int fs, int cc, int cond, instruction_word insn
2737 {
2738   if ((fmt != fmt_single) && (fmt != fmt_double))
2739     SignalException (ReservedInstruction, insn);
2740   else
2741     {
2742       int less;
2743       int equal;
2744       int unordered;
2745       int condition;
2746       unsigned64 ofs = ValueFPR (fs, fmt);
2747       unsigned64 oft = ValueFPR (ft, fmt);
2748       if (NaN (ofs, fmt) || NaN (oft, fmt))
2749         {
2750           if (FCSR & FP_ENABLE (IO))
2751             {
2752               FCSR |= FP_CAUSE (IO);
2753               SignalExceptionFPE ();
2754             }
2755           less = 0;
2756           equal = 0;
2757           unordered = 1;
2758         }
2759       else
2760         {
2761           less = Less (ofs, oft, fmt);
2762           equal = Equal (ofs, oft, fmt);
2763           unordered = 0;
2764         }
2765       condition = (((cond & (1 << 2)) && less)
2766                    || ((cond & (1 << 1)) && equal)
2767                    || ((cond & (1 << 0)) && unordered));
2768       SETFCC (cc, condition);
2769     }
2770 }
2771
2772 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32::C.cond.fmta
2773 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
2774 *mipsI,mipsII,mipsIII:
2775 {
2776   do_c_cond_fmt (SD_, FMT, FT, FS, 0, COND, instruction_0);
2777 }
2778
2779 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32::C.cond.fmtb
2780 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
2781 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
2782 *mipsIV:
2783 *vr4100:
2784 *vr5000:
2785 *r3900:
2786 {
2787   do_c_cond_fmt (SD_, FMT, FT, FS, CC, COND, instruction_0);
2788 }
2789
2790
2791 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64::CEIL.L.fmt
2792 "ceil.l.%s<FMT> f<FD>, f<FS>"
2793 *mipsIII:
2794 *mipsIV:
2795 *vr4100:
2796 *vr5000:
2797 *r3900:
2798 {
2799   unsigned32 instruction = instruction_0;
2800   int destreg = ((instruction >> 6) & 0x0000001F);
2801   int fs = ((instruction >> 11) & 0x0000001F);
2802   int format = ((instruction >> 21) & 0x00000007);
2803   {
2804     if ((format != fmt_single) && (format != fmt_double))
2805       SignalException(ReservedInstruction,instruction);
2806     else
2807       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_long));
2808   }
2809 }
2810
2811
2812 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32::CEIL.W
2813 *mipsII:
2814 *mipsIII:
2815 *mipsIV:
2816 *vr4100:
2817 *vr5000:
2818 *r3900:
2819 {
2820   unsigned32 instruction = instruction_0;
2821   int destreg = ((instruction >> 6) & 0x0000001F);
2822   int fs = ((instruction >> 11) & 0x0000001F);
2823   int format = ((instruction >> 21) & 0x00000007);
2824   {
2825   if ((format != fmt_single) && (format != fmt_double))
2826    SignalException(ReservedInstruction,instruction);
2827   else
2828    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOPINF,ValueFPR(fs,format),format,fmt_word));
2829   }
2830 }
2831
2832
2833 // CFC1
2834 // CTC1
2835 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sa:32::CxC1
2836 "c%s<X>c1 r<RT>, f<FS>"
2837 *mipsI:
2838 *mipsII:
2839 *mipsIII:
2840 {
2841   if (X)
2842     {
2843       if (FS == 0)
2844         PENDING_FILL((FS + FCR0IDX),VL4_8(GPR[RT]));
2845       else if (FS == 31)
2846         PENDING_FILL((FS + FCR31IDX),VL4_8(GPR[RT]));
2847       /* else NOP */
2848       PENDING_FILL(COCIDX,0); /* special case */
2849     }
2850   else
2851     { /* control from */
2852       if (FS == 0)
2853         PENDING_FILL(RT,SIGNEXTEND(FCR0,32));
2854       else if (FS == 31)
2855         PENDING_FILL(RT,SIGNEXTEND(FCR31,32));
2856       /* else NOP */
2857     }
2858 }
2859 010001,00,X,10,5.RT,5.FS,00000000000:COP1Sb:32::CxC1
2860 "c%s<X>c1 r<RT>, f<FS>"
2861 *mipsIV:
2862 *vr4100:
2863 *vr5000:
2864 *r3900:
2865 {
2866   if (X)
2867     {
2868       /* control to */
2869       TRACE_ALU_INPUT1 (GPR[RT]);
2870       if (FS == 0)
2871         {
2872           FCR0 = VL4_8(GPR[RT]);
2873           TRACE_ALU_RESULT (FCR0);
2874         }
2875       else if (FS == 31)
2876         {
2877           FCR31 = VL4_8(GPR[RT]);
2878           SETFCC(0,((FCR31 & (1 << 23)) ? 1 : 0));
2879           TRACE_ALU_RESULT (FCR31);
2880         }
2881       else
2882         {
2883           TRACE_ALU_RESULT0 ();
2884         }
2885       /* else NOP */
2886     }
2887   else
2888     { /* control from */
2889       if (FS == 0)
2890         {
2891           TRACE_ALU_INPUT1 (FCR0);
2892           GPR[RT] = SIGNEXTEND (FCR0, 32);
2893         }
2894       else if (FS == 31)
2895         {
2896           TRACE_ALU_INPUT1 (FCR31);
2897           GPR[RT] = SIGNEXTEND (FCR31, 32);
2898         }
2899       TRACE_ALU_RESULT (GPR[RT]);
2900       /* else NOP */
2901     }
2902 }
2903
2904
2905 //
2906 // FIXME: Does not correctly differentiate between mips*
2907 //
2908 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32::CVT.D.fmt
2909 "cvt.d.%s<FMT> f<FD>, f<FS>"
2910 *mipsI,mipsII,mipsIII,mipsIV:
2911 *vr4100:
2912 *vr5000:
2913 *r3900:
2914 {
2915   unsigned32 instruction = instruction_0;
2916   int destreg = ((instruction >> 6) & 0x0000001F);
2917   int fs = ((instruction >> 11) & 0x0000001F);
2918   int format = ((instruction >> 21) & 0x00000007);
2919   {
2920     if ((format == fmt_double) | 0)
2921       SignalException(ReservedInstruction,instruction);
2922     else
2923       StoreFPR(destreg,fmt_double,Convert(GETRM(),ValueFPR(fs,format),format,fmt_double));
2924   }
2925 }
2926
2927
2928 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64::CVT.L.fmt
2929 "cvt.l.%s<FMT> f<FD>, f<FS>"
2930 *mipsIII:
2931 *mipsIV:
2932 *vr4100:
2933 *vr5000:
2934 *r3900:
2935 {
2936   unsigned32 instruction = instruction_0;
2937   int destreg = ((instruction >> 6) & 0x0000001F);
2938   int fs = ((instruction >> 11) & 0x0000001F);
2939   int format = ((instruction >> 21) & 0x00000007);
2940   {
2941     if ((format == fmt_long) | ((format == fmt_long) || (format == fmt_word)))
2942       SignalException(ReservedInstruction,instruction);
2943     else
2944       StoreFPR(destreg,fmt_long,Convert(GETRM(),ValueFPR(fs,format),format,fmt_long));
2945   }
2946 }
2947
2948
2949 //
2950 // FIXME: Does not correctly differentiate between mips*
2951 //
2952 010001,10,3.FMT,00000,5.FS,5.FD,100000:COP1:32::CVT.S.fmt
2953 "cvt.s.%s<FMT> f<FD>, f<FS>"
2954 *mipsI,mipsII,mipsIII,mipsIV:
2955 *vr4100:
2956 *vr5000:
2957 *r3900:
2958 {
2959   unsigned32 instruction = instruction_0;
2960   int destreg = ((instruction >> 6) & 0x0000001F);
2961   int fs = ((instruction >> 11) & 0x0000001F);
2962   int format = ((instruction >> 21) & 0x00000007);
2963   {
2964     if ((format == fmt_single) | 0)
2965       SignalException(ReservedInstruction,instruction);
2966     else
2967       StoreFPR(destreg,fmt_single,Convert(GETRM(),ValueFPR(fs,format),format,fmt_single));
2968   }
2969 }
2970
2971
2972 010001,10,3.FMT,00000,5.FS,5.FD,100100:COP1:32::CVT.W.fmt
2973 "cvt.w.%s<FMT> f<FD>, f<FS>"
2974 *mipsI,mipsII,mipsIII,mipsIV:
2975 *vr4100:
2976 *vr5000:
2977 *r3900:
2978 {
2979   unsigned32 instruction = instruction_0;
2980   int destreg = ((instruction >> 6) & 0x0000001F);
2981   int fs = ((instruction >> 11) & 0x0000001F);
2982   int format = ((instruction >> 21) & 0x00000007);
2983   {
2984     if ((format == fmt_word) | ((format == fmt_long) || (format == fmt_word)))
2985       SignalException(ReservedInstruction,instruction);
2986     else
2987       StoreFPR(destreg,fmt_word,Convert(GETRM(),ValueFPR(fs,format),format,fmt_word));
2988   }
2989 }
2990
2991
2992 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32::DIV.fmt
2993 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
2994 *mipsI,mipsII,mipsIII,mipsIV:
2995 *vr4100:
2996 *vr5000:
2997 *r3900:
2998 {
2999   unsigned32 instruction = instruction_0;
3000   int destreg = ((instruction >> 6) & 0x0000001F);
3001   int fs = ((instruction >> 11) & 0x0000001F);
3002   int ft = ((instruction >> 16) & 0x0000001F);
3003   int format = ((instruction >> 21) & 0x00000007);
3004   {
3005     if ((format != fmt_single) && (format != fmt_double))
3006       SignalException(ReservedInstruction,instruction);
3007     else
3008       StoreFPR(destreg,format,Divide(ValueFPR(fs,format),ValueFPR(ft,format),format));
3009   }
3010 }
3011
3012
3013 // DMFC1
3014 // DMTC1
3015 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sa:64::DMxC1
3016 "dm%s<X>c1 r<RT>, f<FS>"
3017 *mipsIII:
3018 {
3019   if (X)
3020     {
3021       if (SizeFGR() == 64)
3022         PENDING_FILL((FS + FGRIDX),GPR[RT]);
3023       else if ((FS & 0x1) == 0)
3024         {
3025           PENDING_FILL(((FS + 1) + FGRIDX),VH4_8(GPR[RT]));
3026           PENDING_FILL((FS + FGRIDX),VL4_8(GPR[RT]));
3027         }
3028     }
3029   else
3030     {
3031       if (SizeFGR() == 64)
3032         PENDING_FILL(RT,FGR[FS]);
3033       else if ((FS & 0x1) == 0)
3034         PENDING_FILL(RT,(SET64HI(FGR[FS+1]) | FGR[FS]));
3035       else
3036         PENDING_FILL(RT,SET64HI(0xDEADC0DE) | 0xBAD0BAD0);
3037     }
3038 }
3039 010001,00,X,01,5.RT,5.FS,00000000000:COP1Sb:64::DMxC1
3040 "dm%s<X>c1 r<RT>, f<FS>"
3041 *mipsIV:
3042 *vr4100:
3043 *vr5000:
3044 *r3900:
3045 {
3046   if (X)
3047     {
3048       if (SizeFGR() == 64)
3049         StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
3050       else if ((FS & 0x1) == 0)
3051         StoreFPR (FS, fmt_uninterpreted_64, SET64HI (FGR[FS+1]) | FGR[FS]);
3052     }
3053   else
3054     {
3055       if (SizeFGR() == 64)
3056         GPR[RT] = FGR[FS];
3057       else if ((FS & 0x1) == 0)
3058         GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
3059       else
3060         GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
3061     }
3062 }
3063
3064
3065 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64::FLOOR.L.fmt
3066 "floor.l.%s<FMT> f<FD>, f<FS>"
3067 *mipsIII:
3068 *mipsIV:
3069 *vr4100:
3070 *vr5000:
3071 *r3900:
3072 {
3073   unsigned32 instruction = instruction_0;
3074   int destreg = ((instruction >> 6) & 0x0000001F);
3075   int fs = ((instruction >> 11) & 0x0000001F);
3076   int format = ((instruction >> 21) & 0x00000007);
3077   {
3078     if ((format != fmt_single) && (format != fmt_double))
3079       SignalException(ReservedInstruction,instruction);
3080     else
3081       StoreFPR(destreg,fmt_long,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_long));
3082   }
3083 }
3084
3085
3086 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32::FLOOR.W.fmt
3087 "floor.w.%s<FMT> f<FD>, f<FS>"
3088 *mipsII:
3089 *mipsIII:
3090 *mipsIV:
3091 *vr4100:
3092 *vr5000:
3093 *r3900:
3094 {
3095   unsigned32 instruction = instruction_0;
3096   int destreg = ((instruction >> 6) & 0x0000001F);
3097   int fs = ((instruction >> 11) & 0x0000001F);
3098   int format = ((instruction >> 21) & 0x00000007);
3099   {
3100     if ((format != fmt_single) && (format != fmt_double))
3101       SignalException(ReservedInstruction,instruction);
3102     else
3103       StoreFPR(destreg,fmt_word,Convert(FP_RM_TOMINF,ValueFPR(fs,format),format,fmt_word));
3104   }
3105 }
3106
3107
3108 110101,5.BASE,5.FT,16.OFFSET:COP1:64::LDC1
3109 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
3110 *mipsII:
3111 *mipsIII:
3112 *mipsIV:
3113 *vr4100:
3114 *vr5000:
3115 *r3900:
3116 {
3117   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
3118 }
3119
3120
3121 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64::LDXC1
3122 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
3123 *mipsIV:
3124 *vr5000:
3125 {
3126   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
3127 }
3128
3129
3130
3131 110001,5.BASE,5.FT,16.OFFSET:COP1:32::LWC1
3132 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
3133 *mipsI,mipsII,mipsIII,mipsIV:
3134 *vr4100:
3135 *vr5000:
3136 *r3900:
3137 {
3138   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
3139 }
3140
3141
3142 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:32::LWXC1
3143 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
3144 *mipsIV:
3145 *vr5000:
3146 {
3147   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
3148 }
3149
3150
3151
3152 //
3153 // FIXME: Not correct for mips*
3154 //
3155 010011,5.FR,5.FT,5.FS,5.FD,100,001:COP1X:32,f::MADD.D
3156 "madd.d f<FD>, f<FR>, f<FS>, f<FT>"
3157 *mipsIV:
3158 *vr5000:
3159 {
3160   unsigned32 instruction = instruction_0;
3161   int destreg = ((instruction >> 6) & 0x0000001F);
3162   int fs = ((instruction >> 11) & 0x0000001F);
3163   int ft = ((instruction >> 16) & 0x0000001F);
3164   int fr = ((instruction >> 21) & 0x0000001F);
3165   {
3166     StoreFPR(destreg,fmt_double,Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3167   }
3168 }
3169
3170
3171 010011,5.FR,5.FT,5.FS,5.FD,100,000:COP1X:32,f::MADD.S
3172 "madd.s f<FD>, f<FR>, f<FS>, f<FT>"
3173 *mipsIV:
3174 *vr5000:
3175 {
3176   unsigned32 instruction = instruction_0;
3177   int destreg = ((instruction >> 6) & 0x0000001F);
3178   int fs = ((instruction >> 11) & 0x0000001F);
3179   int ft = ((instruction >> 16) & 0x0000001F);
3180   int fr = ((instruction >> 21) & 0x0000001F);
3181   {
3182     StoreFPR(destreg,fmt_single,Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3183   }
3184 }
3185
3186
3187 // MFC1
3188 // MTC1
3189 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sa:32::MxC1
3190 "m%s<X>c1 r<RT>, f<FS>"
3191 *mipsI:
3192 *mipsII:
3193 *mipsIII:
3194 {
3195   if (X)
3196     { /*MTC1*/
3197       if (SizeFGR() == 64)
3198         PENDING_FILL ((FS + FGRIDX), (SET64HI(0xDEADC0DE) | VL4_8(GPR[RT])));
3199       else
3200         PENDING_FILL ((FS + FGRIDX), VL4_8(GPR[RT]));
3201     }
3202   else /*MFC1*/
3203     PENDING_FILL (RT, SIGNEXTEND(FGR[FS],32));
3204 }
3205 010001,00,X,00,5.RT,5.FS,00000000000:COP1Sb:32::MxC1
3206 "m%s<X>c1 r<RT>, f<FS>"
3207 *mipsIV:
3208 *vr4100:
3209 *vr5000:
3210 *r3900:
3211 {
3212   int fs = FS;
3213   if (X)
3214     /*MTC1*/
3215     StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
3216   else /*MFC1*/
3217     GPR[RT] = SIGNEXTEND(FGR[FS],32);
3218 }
3219
3220
3221 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32::MOV.fmt
3222 "mov.%s<FMT> f<FD>, f<FS>"
3223 *mipsI,mipsII,mipsIII,mipsIV:
3224 *vr4100:
3225 *vr5000:
3226 *r3900:
3227 {
3228   unsigned32 instruction = instruction_0;
3229   int destreg = ((instruction >> 6) & 0x0000001F);
3230   int fs = ((instruction >> 11) & 0x0000001F);
3231   int format = ((instruction >> 21) & 0x00000007);
3232   {
3233     StoreFPR(destreg,format,ValueFPR(fs,format));
3234   }
3235 }
3236
3237
3238 // MOVF
3239 000000,5.RS,3.CC,0,1.TF,5.RD,00000000001:SPECIAL:32::MOVtf
3240 "mov%s<TF> r<RD>, r<RS>, <CC>"
3241 *mipsIV:
3242 *vr5000:
3243 {
3244   if (GETFCC(CC) == TF)
3245     GPR[RD] = GPR[RS];
3246 }
3247
3248
3249 // MOVF.fmt
3250 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32::MOVtf.fmt
3251 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
3252 *mipsIV:
3253 *vr5000:
3254 {
3255   unsigned32 instruction = instruction_0;
3256   int format = ((instruction >> 21) & 0x00000007);
3257   {
3258    if (GETFCC(CC) == TF)
3259      StoreFPR (FD, format, ValueFPR (FS, format));
3260    else
3261      StoreFPR (FD, format, ValueFPR (FD, format));
3262   }
3263 }
3264
3265
3266 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32::MOVN.fmt
3267 *mipsIV:
3268 *vr5000:
3269 {
3270   unsigned32 instruction = instruction_0;
3271   int destreg = ((instruction >> 6) & 0x0000001F);
3272   int fs = ((instruction >> 11) & 0x0000001F);
3273   int format = ((instruction >> 21) & 0x00000007);
3274   {
3275     StoreFPR(destreg,format,ValueFPR(fs,format));
3276   }
3277 }
3278
3279
3280 // MOVT see MOVtf
3281
3282
3283 // MOVT.fmt see MOVtf.fmt
3284
3285
3286
3287 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32::MOVZ.fmt
3288 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
3289 *mipsIV:
3290 *vr5000:
3291 {
3292   unsigned32 instruction = instruction_0;
3293   int destreg = ((instruction >> 6) & 0x0000001F);
3294   int fs = ((instruction >> 11) & 0x0000001F);
3295   int format = ((instruction >> 21) & 0x00000007);
3296   {
3297    StoreFPR(destreg,format,ValueFPR(fs,format));
3298   }
3299 }
3300
3301
3302 // MSUB.fmt
3303 010011,5.FR,5.FT,5.FS,5.FD,101,001:COP1X:32::MSUB.D
3304 "msub.d f<FD>, f<FR>, f<FS>, f<FT>"
3305 *mipsIV:
3306 *vr5000:
3307 {
3308   unsigned32 instruction = instruction_0;
3309   int destreg = ((instruction >> 6) & 0x0000001F);
3310   int fs = ((instruction >> 11) & 0x0000001F);
3311   int ft = ((instruction >> 16) & 0x0000001F);
3312   int fr = ((instruction >> 21) & 0x0000001F);
3313   {
3314     StoreFPR(destreg,fmt_double,Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double));
3315   }
3316 }
3317
3318
3319 // MSUB.fmt
3320 010011,5.FR,5.FT,5.FS,5.FD,101000:COP1X:32::MSUB.S
3321 "msub.s f<FD>, f<FR>, f<FS>, f<FT>"
3322 *mipsIV:
3323 *vr5000:
3324 {
3325   unsigned32 instruction = instruction_0;
3326   int destreg = ((instruction >> 6) & 0x0000001F);
3327   int fs = ((instruction >> 11) & 0x0000001F);
3328   int ft = ((instruction >> 16) & 0x0000001F);
3329   int fr = ((instruction >> 21) & 0x0000001F);
3330   {
3331    StoreFPR(destreg,fmt_single,Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single));
3332   }
3333 }
3334
3335
3336 // MTC1 see MxC1
3337
3338
3339 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32::MUL.fmt
3340 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
3341 *mipsI,mipsII,mipsIII,mipsIV:
3342 *vr4100:
3343 *vr5000:
3344 *r3900:
3345 {
3346   unsigned32 instruction = instruction_0;
3347   int destreg = ((instruction >> 6) & 0x0000001F);
3348   int fs = ((instruction >> 11) & 0x0000001F);
3349   int ft = ((instruction >> 16) & 0x0000001F);
3350   int format = ((instruction >> 21) & 0x00000007);
3351   {
3352     if ((format != fmt_single) && (format != fmt_double))
3353       SignalException(ReservedInstruction,instruction);
3354     else
3355       StoreFPR(destreg,format,Multiply(ValueFPR(fs,format),ValueFPR(ft,format),format));
3356   }
3357 }
3358
3359
3360 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32::NEG.fmt
3361 "neg.%s<FMT> f<FD>, f<FS>"
3362 *mipsI,mipsII,mipsIII,mipsIV:
3363 *vr4100:
3364 *vr5000:
3365 *r3900:
3366 {
3367   unsigned32 instruction = instruction_0;
3368   int destreg = ((instruction >> 6) & 0x0000001F);
3369   int fs = ((instruction >> 11) & 0x0000001F);
3370   int format = ((instruction >> 21) & 0x00000007);
3371   {
3372     if ((format != fmt_single) && (format != fmt_double))
3373       SignalException(ReservedInstruction,instruction);
3374     else
3375       StoreFPR(destreg,format,Negate(ValueFPR(fs,format),format));
3376   }
3377 }
3378
3379
3380 // NMADD.fmt
3381 010011,5.FR,5.FT,5.FS,5.FD,110001:COP1X:32::NMADD.D
3382 "nmadd.d f<FD>, f<FR>, f<FS>, f<FT>"
3383 *mipsIV:
3384 *vr5000:
3385 {
3386   unsigned32 instruction = instruction_0;
3387   int destreg = ((instruction >> 6) & 0x0000001F);
3388   int fs = ((instruction >> 11) & 0x0000001F);
3389   int ft = ((instruction >> 16) & 0x0000001F);
3390   int fr = ((instruction >> 21) & 0x0000001F);
3391   {
3392    StoreFPR(destreg,fmt_double,Negate(Add(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3393   }
3394 }
3395
3396
3397 // NMADD.fmt
3398 010011,5.FR,5.FT,5.FS,5.FD,110000:COP1X:32::NMADD.S
3399 "nmadd.s f<FD>, f<FR>, f<FS>, f<FT>"
3400 *mipsIV:
3401 *vr5000:
3402 {
3403   unsigned32 instruction = instruction_0;
3404   int destreg = ((instruction >> 6) & 0x0000001F);
3405   int fs = ((instruction >> 11) & 0x0000001F);
3406   int ft = ((instruction >> 16) & 0x0000001F);
3407   int fr = ((instruction >> 21) & 0x0000001F);
3408   {
3409    StoreFPR(destreg,fmt_single,Negate(Add(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3410   }
3411 }
3412
3413
3414 // NMSUB.fmt
3415 010011,5.FR,5.FT,5.FS,5.FD,111001:COP1X:32::NMSUB.D
3416 "nmsub.d f<FD>, f<FR>, f<FS>, f<FT>"
3417 *mipsIV:
3418 *vr5000:
3419 {
3420   unsigned32 instruction = instruction_0;
3421   int destreg = ((instruction >> 6) & 0x0000001F);
3422   int fs = ((instruction >> 11) & 0x0000001F);
3423   int ft = ((instruction >> 16) & 0x0000001F);
3424   int fr = ((instruction >> 21) & 0x0000001F);
3425   {
3426    StoreFPR(destreg,fmt_double,Negate(Sub(Multiply(ValueFPR(fs,fmt_double),ValueFPR(ft,fmt_double),fmt_double),ValueFPR(fr,fmt_double),fmt_double),fmt_double));
3427   }
3428 }
3429
3430
3431 // NMSUB.fmt
3432 010011,5.FR,5.FT,5.FS,5.FD,111000:COP1X:32::NMSUB.S
3433 "nmsub.s f<FD>, f<FR>, f<FS>, f<FT>"
3434 *mipsIV:
3435 *vr5000:
3436 {
3437   unsigned32 instruction = instruction_0;
3438   int destreg = ((instruction >> 6) & 0x0000001F);
3439   int fs = ((instruction >> 11) & 0x0000001F);
3440   int ft = ((instruction >> 16) & 0x0000001F);
3441   int fr = ((instruction >> 21) & 0x0000001F);
3442   {
3443     StoreFPR(destreg,fmt_single,Negate(Sub(Multiply(ValueFPR(fs,fmt_single),ValueFPR(ft,fmt_single),fmt_single),ValueFPR(fr,fmt_single),fmt_single),fmt_single));
3444   }
3445 }
3446
3447
3448 010011,5.BASE,5.INDEX,5.HINT,00000001111:COP1X:32::PREFX
3449 "prefx <HINT>, r<INDEX>(r<BASE>)"
3450 *mipsIV:
3451 *vr5000:
3452 {
3453   unsigned32 instruction = instruction_0;
3454   int fs = ((instruction >> 11) & 0x0000001F);
3455   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3456   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3457   {
3458     address_word vaddr = ((unsigned64)op1 + (unsigned64)op2);
3459     address_word paddr;
3460     int uncached;
3461     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3462       Prefetch(uncached,paddr,vaddr,isDATA,fs);
3463   }
3464 }
3465
3466 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32::RECIP.fmt
3467 *mipsIV:
3468 "recip.%s<FMT> f<FD>, f<FS>"
3469 *vr5000:
3470 {
3471   unsigned32 instruction = instruction_0;
3472   int destreg = ((instruction >> 6) & 0x0000001F);
3473   int fs = ((instruction >> 11) & 0x0000001F);
3474   int format = ((instruction >> 21) & 0x00000007);
3475   {
3476   if ((format != fmt_single) && (format != fmt_double))
3477    SignalException(ReservedInstruction,instruction);
3478   else
3479    StoreFPR(destreg,format,Recip(ValueFPR(fs,format),format));
3480   }
3481 }
3482
3483
3484 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64::ROUND.L.fmt
3485 "round.l.%s<FMT> f<FD>, f<FS>"
3486 *mipsIII:
3487 *mipsIV:
3488 *vr4100:
3489 *vr5000:
3490 *r3900:
3491 {
3492   unsigned32 instruction = instruction_0;
3493   int destreg = ((instruction >> 6) & 0x0000001F);
3494   int fs = ((instruction >> 11) & 0x0000001F);
3495   int format = ((instruction >> 21) & 0x00000007);
3496   {
3497     if ((format != fmt_single) && (format != fmt_double))
3498       SignalException(ReservedInstruction,instruction);
3499     else
3500       StoreFPR(destreg,fmt_long,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_long));
3501   }
3502 }
3503
3504
3505 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32::ROUND.W.fmt
3506 "round.w.%s<FMT> f<FD>, f<FS>"
3507 *mipsII:
3508 *mipsIII:
3509 *mipsIV:
3510 *vr4100:
3511 *vr5000:
3512 *r3900:
3513 {
3514   unsigned32 instruction = instruction_0;
3515   int destreg = ((instruction >> 6) & 0x0000001F);
3516   int fs = ((instruction >> 11) & 0x0000001F);
3517   int format = ((instruction >> 21) & 0x00000007);
3518   {
3519   if ((format != fmt_single) && (format != fmt_double))
3520    SignalException(ReservedInstruction,instruction);
3521   else
3522    StoreFPR(destreg,fmt_word,Convert(FP_RM_NEAREST,ValueFPR(fs,format),format,fmt_word));
3523   }
3524 }
3525
3526
3527 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32::RSQRT.fmt
3528 *mipsIV:
3529 "rsqrt.%s<FMT> f<FD>, f<FS>"
3530 *vr5000:
3531 {
3532   unsigned32 instruction = instruction_0;
3533   int destreg = ((instruction >> 6) & 0x0000001F);
3534   int fs = ((instruction >> 11) & 0x0000001F);
3535   int format = ((instruction >> 21) & 0x00000007);
3536   {
3537   if ((format != fmt_single) && (format != fmt_double))
3538    SignalException(ReservedInstruction,instruction);
3539   else
3540    StoreFPR(destreg,format,Recip(SquareRoot(ValueFPR(fs,format),format),format));
3541   }
3542 }
3543
3544
3545 111101,5.BASE,5.FT,16.OFFSET:COP1:64::SDC1
3546 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
3547 *mipsII:
3548 *mipsIII:
3549 *mipsIV:
3550 *vr4100:
3551 *vr5000:
3552 *r3900:
3553 {
3554   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
3555 }
3556
3557
3558 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64::SDXC1
3559 "ldxc1 f<FS>, r<INDEX>(r<BASE>)"
3560 *mipsIV:
3561 *vr5000:
3562 {
3563   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
3564 }
3565
3566
3567 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32::SQRT.fmt
3568 "sqrt.%s<FMT> f<FD>, f<FS>"
3569 *mipsII:
3570 *mipsIII:
3571 *mipsIV:
3572 *vr4100:
3573 *vr5000:
3574 *r3900:
3575 {
3576   unsigned32 instruction = instruction_0;
3577   int destreg = ((instruction >> 6) & 0x0000001F);
3578   int fs = ((instruction >> 11) & 0x0000001F);
3579   int format = ((instruction >> 21) & 0x00000007);
3580   {
3581     if ((format != fmt_single) && (format != fmt_double))
3582       SignalException(ReservedInstruction,instruction);
3583     else
3584       StoreFPR(destreg,format,(SquareRoot(ValueFPR(fs,format),format)));
3585   }
3586 }
3587
3588
3589 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32::SUB.fmt
3590 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
3591 *mipsI,mipsII,mipsIII,mipsIV:
3592 *vr4100:
3593 *vr5000:
3594 *r3900:
3595 {
3596   unsigned32 instruction = instruction_0;
3597   int destreg = ((instruction >> 6) & 0x0000001F);
3598   int fs = ((instruction >> 11) & 0x0000001F);
3599   int ft = ((instruction >> 16) & 0x0000001F);
3600   int format = ((instruction >> 21) & 0x00000007);
3601   {
3602     if ((format != fmt_single) && (format != fmt_double))
3603       SignalException(ReservedInstruction,instruction);
3604     else
3605       StoreFPR(destreg,format,Sub(ValueFPR(fs,format),ValueFPR(ft,format),format));
3606   }
3607 }
3608
3609
3610
3611 111001,5.BASE,5.FT,16.OFFSET:COP1:32::SWC1
3612 "swc1 f<FT>, <OFFSET>(r<BASE>)"
3613 *mipsI,mipsII,mipsIII,mipsIV:
3614 *vr4100:
3615 *vr5000:
3616 *r3900:
3617 {
3618   unsigned32 instruction = instruction_0;
3619   signed_word offset = EXTEND16 (OFFSET);
3620   int destreg UNUSED = ((instruction >> 16) & 0x0000001F);
3621   signed_word op1 UNUSED = GPR[((instruction >> 21) & 0x0000001F)];
3622   {
3623     address_word vaddr = ((uword64)op1 + offset);
3624     address_word paddr;
3625     int uncached;
3626     if ((vaddr & 3) != 0)
3627       {
3628         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
3629       }
3630     else
3631       {
3632         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3633           {
3634             uword64 memval = 0;
3635             uword64 memval1 = 0;
3636             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3637             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
3638             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
3639             unsigned int byte;
3640             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3641             byte = ((vaddr & mask) ^ bigendiancpu);
3642             memval = (((uword64)COP_SW(((instruction >> 26) & 0x3),destreg)) << (8 * byte));
3643             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3644           }
3645       }
3646   }
3647 }
3648
3649
3650 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32::SWXC1
3651 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
3652 *mipsIV:
3653 *vr5000:
3654 {
3655   unsigned32 instruction = instruction_0;
3656   int fs = ((instruction >> 11) & 0x0000001F);
3657   signed_word op2 = GPR[((instruction >> 16) & 0x0000001F)];
3658   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3659   {
3660    address_word vaddr = ((unsigned64)op1 + op2);
3661    address_word paddr;
3662    int uncached;
3663    if ((vaddr & 3) != 0)
3664      {
3665        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3666      }
3667    else
3668    {
3669     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3670     {
3671      unsigned64 memval = 0;
3672      unsigned64 memval1 = 0;
3673      unsigned64 mask = 0x7;
3674      unsigned int byte;
3675      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3676      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3677      memval = (((unsigned64)COP_SW(1,fs)) << (8 * byte));
3678       {
3679        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3680       }
3681     }
3682    }
3683   }
3684 }
3685
3686
3687 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64::TRUNC.L.fmt
3688 "trunc.l.%s<FMT> f<FD>, f<FS>"
3689 *mipsIII:
3690 *mipsIV:
3691 *vr4100:
3692 *vr5000:
3693 *r3900:
3694 {
3695   unsigned32 instruction = instruction_0;
3696   int destreg = ((instruction >> 6) & 0x0000001F);
3697   int fs = ((instruction >> 11) & 0x0000001F);
3698   int format = ((instruction >> 21) & 0x00000007);
3699   {
3700   if ((format != fmt_single) && (format != fmt_double))
3701    SignalException(ReservedInstruction,instruction);
3702   else
3703    StoreFPR(destreg,fmt_long,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_long));
3704   }
3705 }
3706
3707
3708 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32::TRUNC.W
3709 "trunc.w.%s<FMT> f<FD>, f<FS>"
3710 *mipsII:
3711 *mipsIII:
3712 *mipsIV:
3713 *vr4100:
3714 *vr5000:
3715 *r3900:
3716 {
3717   unsigned32 instruction = instruction_0;
3718   int destreg = ((instruction >> 6) & 0x0000001F);
3719   int fs = ((instruction >> 11) & 0x0000001F);
3720   int format = ((instruction >> 21) & 0x00000007);
3721   {
3722   if ((format != fmt_single) && (format != fmt_double))
3723    SignalException(ReservedInstruction,instruction);
3724   else
3725    StoreFPR(destreg,fmt_word,Convert(FP_RM_TOZERO,ValueFPR(fs,format),format,fmt_word));
3726   }
3727 }
3728
3729 \f
3730 //
3731 // MIPS Architecture:
3732 //
3733 //        System Control Instruction Set (COP0)
3734 //
3735
3736
3737 010000,01000,00000,16.OFFSET:COP0:32::BC0F
3738 "bc0f <OFFSET>"
3739 *mipsI,mipsII,mipsIII,mipsIV:
3740 *vr4100:
3741 *vr5000:
3742
3743 010000,01000,00000,16.OFFSET:COP0:32::BC0F
3744 "bc0f <OFFSET>"
3745 // stub needed for eCos as tx39 hardware bug workaround
3746 *r3900:
3747 {
3748   /* do nothing */
3749 }
3750
3751
3752 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
3753 "bc0fl <OFFSET>"
3754 *mipsI,mipsII,mipsIII,mipsIV:
3755 *vr4100:
3756 *vr5000:
3757
3758
3759 010000,01000,00001,16.OFFSET:COP0:32::BC0T
3760 "bc0t <OFFSET>"
3761 *mipsI,mipsII,mipsIII,mipsIV:
3762 *vr4100:
3763
3764
3765 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
3766 "bc0tl <OFFSET>"
3767 *mipsI,mipsII,mipsIII,mipsIV:
3768 *vr4100:
3769 *vr5000:
3770
3771
3772 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
3773 *mipsIII:
3774 *mipsIV:
3775 *vr4100:
3776 *vr5000:
3777 *r3900:
3778 {
3779   unsigned32 instruction = instruction_0;
3780   signed_word offset = SIGNEXTEND((signed_word)((instruction >> 0) & 0x0000FFFF),16);
3781   int hint = ((instruction >> 16) & 0x0000001F);
3782   signed_word op1 = GPR[((instruction >> 21) & 0x0000001F)];
3783   {
3784     address_word vaddr = (op1 + offset);
3785     address_word paddr;
3786     int uncached;
3787     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3788       CacheOp(hint,vaddr,paddr,instruction);
3789   }
3790 }
3791
3792
3793 010000,10000,000000000000000,111001:COP0:32::DI
3794 "di"
3795 *mipsI,mipsII,mipsIII,mipsIV:
3796 *vr4100:
3797 *vr5000:
3798
3799
3800 010000,00001,5.RT,5.RD,000,0000,0000:COP0:64::DMFC0
3801 "dmfc0 r<RT>, r<RD>"
3802 *mipsIII,mipsIV:
3803 {
3804   DecodeCoproc (instruction_0);
3805 }
3806
3807
3808 010000,00101,5.RT,5.RD,000,0000,0000:COP0:64::DMTC0
3809 "dmtc0 r<RT>, r<RD>"
3810 *mipsIII,mipsIV:
3811 {
3812   DecodeCoproc (instruction_0);
3813 }
3814
3815
3816 010000,10000,000000000000000,111000:COP0:32::EI
3817 "ei"
3818 *mipsI,mipsII,mipsIII,mipsIV:
3819 *vr4100:
3820 *vr5000:
3821
3822
3823 010000,10000,000000000000000,011000:COP0:32::ERET
3824 "eret"
3825 *mipsIII:
3826 *mipsIV:
3827 *vr4100:
3828 *vr5000:
3829 {
3830   if (SR & status_ERL)
3831     {
3832       /* Oops, not yet available */
3833       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
3834       NIA = EPC;
3835       SR &= ~status_ERL;
3836     }
3837   else
3838     {
3839       NIA = EPC;
3840       SR &= ~status_EXL;
3841     }
3842 }
3843
3844
3845 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
3846 "mfc0 r<RT>, r<RD> # <REGX>"
3847 *mipsI,mipsII,mipsIII,mipsIV:
3848 *r3900:
3849 *vr4100:
3850 *vr5000:
3851 {
3852   TRACE_ALU_INPUT0 ();
3853   DecodeCoproc (instruction_0);
3854   TRACE_ALU_RESULT (GPR[RT]);
3855 }
3856
3857 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
3858 "mtc0 r<RT>, r<RD> # <REGX>"
3859 *mipsI,mipsII,mipsIII,mipsIV:
3860 *r3900:
3861 *vr4100:
3862 *vr5000:
3863 {
3864   DecodeCoproc (instruction_0);
3865 }
3866
3867
3868 010000,10000,000000000000000,010000:COP0:32::RFE
3869 "rfe"
3870 *mipsI,mipsII,mipsIII,mipsIV:
3871 *r3900:
3872 *vr4100:
3873 *vr5000:
3874 {
3875   DecodeCoproc (instruction_0);
3876 }
3877
3878
3879 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
3880 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
3881 *mipsI,mipsII,mipsIII,mipsIV:
3882 *vr4100:
3883 *r3900:
3884 {
3885   DecodeCoproc (instruction_0);
3886 }
3887
3888
3889
3890 010000,10000,000000000000000,001000:COP0:32::TLBP
3891 "tlbp"
3892 *mipsI,mipsII,mipsIII,mipsIV:
3893 *vr4100:
3894 *vr5000:
3895
3896
3897 010000,10000,000000000000000,000001:COP0:32::TLBR
3898 "tlbr"
3899 *mipsI,mipsII,mipsIII,mipsIV:
3900 *vr4100:
3901 *vr5000:
3902
3903
3904 010000,10000,000000000000000,000010:COP0:32::TLBWI
3905 "tlbwi"
3906 *mipsI,mipsII,mipsIII,mipsIV:
3907 *vr4100:
3908 *vr5000:
3909
3910
3911 010000,10000,000000000000000,000110:COP0:32::TLBWR
3912 "tlbwr"
3913 *mipsI,mipsII,mipsIII,mipsIV:
3914 *vr4100:
3915 *vr5000:
3916
3917 \f
3918 :include:::m16.igen
3919 :include:::tx.igen
3920 :include:::vr.igen
3921 \f