sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips16e:mips16e:               // m16e.igen
  72 :model:::mips3d:mips3d:                 // mips3d.igen
  73 :model:::mdmx:mdmx:                     // mdmx.igen
  74 :model:::dsp:dsp:                       // dsp.igen
  75 :model:::dsp2:dsp2:                     // dsp2.igen
  76 :model:::smartmips:smartmips:           // smartmips.igen
  77
  78 //  Vendor Extensions
  79 //
  80 //  Instructions specific to these extensions are in separate .igen files.
  81 //  Extensions add instructions on to a base ISA.
  82 :model:::sb1:sb1:                       // sb1.igen
  83
  84
  85 // Pseudo instructions known by IGEN
  86 :internal::::illegal:
  87 {
  88   SignalException (ReservedInstruction, 0);
  89 }
  90
  91
  92 // Pseudo instructions known by interp.c
  93 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  94 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  95 "rsvd <OP>"
  96 {
  97   SignalException (ReservedInstruction, instruction_0);
  98 }
  99
 100
 101
 102 // Helper:
 103 //
 104 // Simulate a 32 bit delayslot instruction
 105 //
 106
 107 :function:::address_word:delayslot32:address_word target
 108 {
 109   instruction_word delay_insn;
 110   sim_events_slip (SD, 1);
 111   DSPC = CIA;
 112   CIA = CIA + 4; /* NOTE not mips16 */
 113   STATE |= simDELAYSLOT;
 114   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 115   ENGINE_ISSUE_PREFIX_HOOK();
 116   idecode_issue (CPU_, delay_insn, (CIA));
 117   STATE &= ~simDELAYSLOT;
 118   return target;
 119 }
 120
 121 :function:::address_word:nullify_next_insn32:
 122 {
 123   sim_events_slip (SD, 1);
 124   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 125   return CIA + 8;
 126 }
 127
 128
 129 // Helper:
 130 //
 131 // Calculate an effective address given a base and an offset.
 132 //
 133
 134 :function:::address_word:loadstore_ea:address_word base, address_word offset
 135 *mipsI:
 136 *mipsII:
 137 *mipsIII:
 138 *mipsIV:
 139 *mipsV:
 140 *mips32:
 141 *mips32r2:
 142 *vr4100:
 143 *vr5000:
 144 *r3900:
 145 {
 146   return base + offset;
 147 }
 148
 149 :function:::address_word:loadstore_ea:address_word base, address_word offset
 150 *mips64:
 151 *mips64r2:
 152 {
 153 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 154   /* If in user mode and UX is not set, use 32-bit compatibility effective
 155      address computations as defined in the MIPS64 Architecture for
 156      Programmers Volume III, Revision 0.95, section 4.9.  */
 157   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 158       == (ksu_user << status_KSU_shift))
 159     return (address_word)((signed32)base + (signed32)offset);
 160 #endif
 161   return base + offset;
 162 }
 163
 164
 165 // Helper:
 166 //
 167 // Check that a 32-bit register value is properly sign-extended.
 168 // (See NotWordValue in ISA spec.)
 169 //
 170
 171 :function:::int:not_word_value:unsigned_word value
 172 *mipsI:
 173 *mipsII:
 174 *mipsIII:
 175 *mipsIV:
 176 *mipsV:
 177 *vr4100:
 178 *vr5000:
 179 *r3900:
 180 *mips32:
 181 *mips32r2:
 182 *mips64:
 183 *mips64r2:
 184 {
 185 #if WITH_TARGET_WORD_BITSIZE == 64
 186   return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
 187 #else
 188   return 0;
 189 #endif
 190 }
 191
 192 // Helper:
 193 //
 194 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 195 // theoretically portable code which invokes non-portable behaviour from
 196 // running with no indication of the portability issue.
 197 // (See definition of UNPREDICTABLE in ISA spec.)
 198 //
 199
 200 :function:::void:unpredictable:
 201 *mipsI:
 202 *mipsII:
 203 *mipsIII:
 204 *mipsIV:
 205 *mipsV:
 206 *vr4100:
 207 *vr5000:
 208 *r3900:
 209 {
 210 }
 211
 212 :function:::void:unpredictable:
 213 *mips32:
 214 *mips32r2:
 215 *mips64:
 216 *mips64r2:
 217 {
 218   unpredictable_action (CPU, CIA);
 219 }
 220
 221
 222 // Helpers:
 223 //
 224 // Check that an access to a HI/LO register meets timing requirements
 225 //
 226 // In all MIPS ISAs,
 227 //
 228 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 229 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 230 //
 231 // The following restrictions exist for MIPS I - MIPS III:
 232 //
 233 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 234 //      in between makes MF UNPREDICTABLE. (2)
 235 //
 236 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 237 //      in between makes MF UNPREDICTABLE. (3)
 238 //
 239 // On the r3900, restriction (2) is not present, and restriction (3) is not
 240 // present for multiplication.
 241 //
 242 // Unfortunately, there seems to be some confusion about whether the last
 243 // two restrictions should apply to "MIPS IV" as well.  One edition of
 244 // the MIPS IV ISA says they do, but references in later ISA documents
 245 // suggest they don't.
 246 //
 247 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 248 // these restrictions, while others, like the VR5500, don't.  To accomodate
 249 // such differences, the MIPS IV and MIPS V version of these helper functions
 250 // use auxillary routines to determine whether the restriction applies.
 251
 252 // check_mf_cycles:
 253 //
 254 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 255 // to check for restrictions (2) and (3) above.
 256 //
 257 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 258 {
 259   if (history->mf.timestamp + 3 > time)
 260     {
 261       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 262                         itable[MY_INDEX].name,
 263                         new, (long) CIA,
 264                         (long) history->mf.cia);
 265       return 0;
 266     }
 267   return 1;
 268 }
 269
 270
 271 // check_mt_hilo:
 272 //
 273 // Check for restriction (2) above (for ISAs/processors that have it),
 274 // and record timestamps for restriction (1) above.
 275 //
 276 :function:::int:check_mt_hilo:hilo_history *history
 277 *mipsI:
 278 *mipsII:
 279 *mipsIII:
 280 *vr4100:
 281 *vr5000:
 282 {
 283   signed64 time = sim_events_time (SD);
 284   int ok = check_mf_cycles (SD_, history, time, "MT");
 285   history->mt.timestamp = time;
 286   history->mt.cia = CIA;
 287   return ok;
 288 }
 289
 290 :function:::int:check_mt_hilo:hilo_history *history
 291 *mipsIV:
 292 *mipsV:
 293 {
 294   signed64 time = sim_events_time (SD);
 295   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 296             || check_mf_cycles (SD_, history, time, "MT"));
 297   history->mt.timestamp = time;
 298   history->mt.cia = CIA;
 299   return ok;
 300 }
 301
 302 :function:::int:check_mt_hilo:hilo_history *history
 303 *mips32:
 304 *mips32r2:
 305 *mips64:
 306 *mips64r2:
 307 *r3900:
 308 {
 309   signed64 time = sim_events_time (SD);
 310   history->mt.timestamp = time;
 311   history->mt.cia = CIA;
 312   return 1;
 313 }
 314
 315
 316 // check_mf_hilo:
 317 //
 318 // Check for restriction (1) above, and record timestamps for
 319 // restriction (2) and (3) above.
 320 //
 321 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 322 *mipsI:
 323 *mipsII:
 324 *mipsIII:
 325 *mipsIV:
 326 *mipsV:
 327 *mips32:
 328 *mips32r2:
 329 *mips64:
 330 *mips64r2:
 331 *vr4100:
 332 *vr5000:
 333 *r3900:
 334 {
 335   signed64 time = sim_events_time (SD);
 336   int ok = 1;
 337   if (peer != NULL
 338       && peer->mt.timestamp > history->op.timestamp
 339       && history->mt.timestamp < history->op.timestamp
 340       && ! (history->mf.timestamp > history->op.timestamp
 341             && history->mf.timestamp < peer->mt.timestamp)
 342       && ! (peer->mf.timestamp > history->op.timestamp
 343             && peer->mf.timestamp < peer->mt.timestamp))
 344     {
 345       /* The peer has been written to since the last OP yet we have
 346          not */
 347       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 348                         itable[MY_INDEX].name,
 349                         (long) CIA,
 350                         (long) history->op.cia,
 351                         (long) peer->mt.cia);
 352       ok = 0;
 353     }
 354   history->mf.timestamp = time;
 355   history->mf.cia = CIA;
 356   return ok;
 357 }
 358
 359
 360
 361 // check_mult_hilo:
 362 //
 363 // Check for restriction (3) above (for ISAs/processors that have it)
 364 // for MULT ops, and record timestamps for restriction (1) above.
 365 //
 366 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 367 *mipsI:
 368 *mipsII:
 369 *mipsIII:
 370 *vr4100:
 371 *vr5000:
 372 {
 373   signed64 time = sim_events_time (SD);
 374   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 375             && check_mf_cycles (SD_, lo, time, "OP"));
 376   hi->op.timestamp = time;
 377   lo->op.timestamp = time;
 378   hi->op.cia = CIA;
 379   lo->op.cia = CIA;
 380   return ok;
 381 }
 382
 383 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 384 *mipsIV:
 385 *mipsV:
 386 {
 387   signed64 time = sim_events_time (SD);
 388   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 389             || (check_mf_cycles (SD_, hi, time, "OP")
 390                 && check_mf_cycles (SD_, lo, time, "OP")));
 391   hi->op.timestamp = time;
 392   lo->op.timestamp = time;
 393   hi->op.cia = CIA;
 394   lo->op.cia = CIA;
 395   return ok;
 396 }
 397
 398 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 399 *mips32:
 400 *mips32r2:
 401 *mips64:
 402 *mips64r2:
 403 *r3900:
 404 {
 405   /* FIXME: could record the fact that a stall occured if we want */
 406   signed64 time = sim_events_time (SD);
 407   hi->op.timestamp = time;
 408   lo->op.timestamp = time;
 409   hi->op.cia = CIA;
 410   lo->op.cia = CIA;
 411   return 1;
 412 }
 413
 414
 415 // check_div_hilo:
 416 //
 417 // Check for restriction (3) above (for ISAs/processors that have it)
 418 // for DIV ops, and record timestamps for restriction (1) above.
 419 //
 420 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 421 *mipsI:
 422 *mipsII:
 423 *mipsIII:
 424 *vr4100:
 425 *vr5000:
 426 *r3900:
 427 {
 428   signed64 time = sim_events_time (SD);
 429   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 430             && check_mf_cycles (SD_, lo, time, "OP"));
 431   hi->op.timestamp = time;
 432   lo->op.timestamp = time;
 433   hi->op.cia = CIA;
 434   lo->op.cia = CIA;
 435   return ok;
 436 }
 437
 438 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 439 *mipsIV:
 440 *mipsV:
 441 {
 442   signed64 time = sim_events_time (SD);
 443   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 444             || (check_mf_cycles (SD_, hi, time, "OP")
 445                 && check_mf_cycles (SD_, lo, time, "OP")));
 446   hi->op.timestamp = time;
 447   lo->op.timestamp = time;
 448   hi->op.cia = CIA;
 449   lo->op.cia = CIA;
 450   return ok;
 451 }
 452
 453 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 454 *mips32:
 455 *mips32r2:
 456 *mips64:
 457 *mips64r2:
 458 {
 459   signed64 time = sim_events_time (SD);
 460   hi->op.timestamp = time;
 461   lo->op.timestamp = time;
 462   hi->op.cia = CIA;
 463   lo->op.cia = CIA;
 464   return 1;
 465 }
 466
 467
 468 // Helper:
 469 //
 470 // Check that the 64-bit instruction can currently be used, and signal
 471 // a ReservedInstruction exception if not.
 472 //
 473
 474 :function:::void:check_u64:instruction_word insn
 475 *mipsIII:
 476 *mipsIV:
 477 *mipsV:
 478 *vr4100:
 479 *vr5000:
 480 *vr5400:
 481 *vr5500:
 482 {
 483   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 484 }
 485
 486 :function:::void:check_u64:instruction_word insn
 487 *mips16e:
 488 *mips64:
 489 *mips64r2:
 490 {
 491 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 492   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 493     SignalException (ReservedInstruction, insn);
 494 #endif
 495 }
 496
 497
 498
 499 //
 500 // MIPS Architecture:
 501 //
 502 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 503 //
 504
 505
 506
 507 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 508 "add r<RD>, r<RS>, r<RT>"
 509 *mipsI:
 510 *mipsII:
 511 *mipsIII:
 512 *mipsIV:
 513 *mipsV:
 514 *mips32:
 515 *mips32r2:
 516 *mips64:
 517 *mips64r2:
 518 *vr4100:
 519 *vr5000:
 520 *r3900:
 521 {
 522   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 523     Unpredictable ();
 524   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 525   {
 526     ALU32_BEGIN (GPR[RS]);
 527     ALU32_ADD (GPR[RT]);
 528     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 529   }
 530   TRACE_ALU_RESULT (GPR[RD]);
 531 }
 532
 533
 534
 535 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 536 "addi r<RT>, r<RS>, <IMMEDIATE>"
 537 *mipsI:
 538 *mipsII:
 539 *mipsIII:
 540 *mipsIV:
 541 *mipsV:
 542 *mips32:
 543 *mips32r2:
 544 *mips64:
 545 *mips64r2:
 546 *vr4100:
 547 *vr5000:
 548 *r3900:
 549 {
 550   if (NotWordValue (GPR[RS]))
 551     Unpredictable ();
 552   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 553   {
 554     ALU32_BEGIN (GPR[RS]);
 555     ALU32_ADD (EXTEND16 (IMMEDIATE));
 556     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 557   }
 558   TRACE_ALU_RESULT (GPR[RT]);
 559 }
 560
 561
 562
 563 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 564 {
 565   if (NotWordValue (GPR[rs]))
 566     Unpredictable ();
 567   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 568   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 569   TRACE_ALU_RESULT (GPR[rt]);
 570 }
 571
 572 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 573 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 574 *mipsI:
 575 *mipsII:
 576 *mipsIII:
 577 *mipsIV:
 578 *mipsV:
 579 *mips32:
 580 *mips32r2:
 581 *mips64:
 582 *mips64r2:
 583 *vr4100:
 584 *vr5000:
 585 *r3900:
 586 {
 587   do_addiu (SD_, RS, RT, IMMEDIATE);
 588 }
 589
 590
 591
 592 :function:::void:do_addu:int rs, int rt, int rd
 593 {
 594   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 595     Unpredictable ();
 596   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 597   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 598   TRACE_ALU_RESULT (GPR[rd]);
 599 }
 600
 601 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 602 "addu r<RD>, r<RS>, r<RT>"
 603 *mipsI:
 604 *mipsII:
 605 *mipsIII:
 606 *mipsIV:
 607 *mipsV:
 608 *mips32:
 609 *mips32r2:
 610 *mips64:
 611 *mips64r2:
 612 *vr4100:
 613 *vr5000:
 614 *r3900:
 615 {
 616   do_addu (SD_, RS, RT, RD);
 617 }
 618
 619
 620
 621 :function:::void:do_and:int rs, int rt, int rd
 622 {
 623   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 624   GPR[rd] = GPR[rs] & GPR[rt];
 625   TRACE_ALU_RESULT (GPR[rd]);
 626 }
 627
 628 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 629 "and r<RD>, r<RS>, r<RT>"
 630 *mipsI:
 631 *mipsII:
 632 *mipsIII:
 633 *mipsIV:
 634 *mipsV:
 635 *mips32:
 636 *mips32r2:
 637 *mips64:
 638 *mips64r2:
 639 *vr4100:
 640 *vr5000:
 641 *r3900:
 642 {
 643   do_and (SD_, RS, RT, RD);
 644 }
 645
 646
 647
 648 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 649 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 650 *mipsI:
 651 *mipsII:
 652 *mipsIII:
 653 *mipsIV:
 654 *mipsV:
 655 *mips32:
 656 *mips32r2:
 657 *mips64:
 658 *mips64r2:
 659 *vr4100:
 660 *vr5000:
 661 *r3900:
 662 {
 663   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 664   GPR[RT] = GPR[RS] & IMMEDIATE;
 665   TRACE_ALU_RESULT (GPR[RT]);
 666 }
 667
 668
 669
 670 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 671 "beq r<RS>, r<RT>, <OFFSET>"
 672 *mipsI:
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *mipsV:
 677 *mips32:
 678 *mips32r2:
 679 *mips64:
 680 *mips64r2:
 681 *vr4100:
 682 *vr5000:
 683 *r3900:
 684 {
 685   address_word offset = EXTEND16 (OFFSET) << 2;
 686   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 687     {
 688       DELAY_SLOT (NIA + offset);
 689     }
 690 }
 691
 692
 693
 694 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 695 "beql r<RS>, r<RT>, <OFFSET>"
 696 *mipsII:
 697 *mipsIII:
 698 *mipsIV:
 699 *mipsV:
 700 *mips32:
 701 *mips32r2:
 702 *mips64:
 703 *mips64r2:
 704 *vr4100:
 705 *vr5000:
 706 *r3900:
 707 {
 708   address_word offset = EXTEND16 (OFFSET) << 2;
 709   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 710     {
 711       DELAY_SLOT (NIA + offset);
 712     }
 713   else
 714     NULLIFY_NEXT_INSTRUCTION ();
 715 }
 716
 717
 718
 719 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 720 "bgez r<RS>, <OFFSET>"
 721 *mipsI:
 722 *mipsII:
 723 *mipsIII:
 724 *mipsIV:
 725 *mipsV:
 726 *mips32:
 727 *mips32r2:
 728 *mips64:
 729 *mips64r2:
 730 *vr4100:
 731 *vr5000:
 732 *r3900:
 733 {
 734   address_word offset = EXTEND16 (OFFSET) << 2;
 735   if ((signed_word) GPR[RS] >= 0)
 736     {
 737       DELAY_SLOT (NIA + offset);
 738     }
 739 }
 740
 741
 742
 743 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 744 "bgezal r<RS>, <OFFSET>"
 745 *mipsI:
 746 *mipsII:
 747 *mipsIII:
 748 *mipsIV:
 749 *mipsV:
 750 *mips32:
 751 *mips32r2:
 752 *mips64:
 753 *mips64r2:
 754 *vr4100:
 755 *vr5000:
 756 *r3900:
 757 {
 758   address_word offset = EXTEND16 (OFFSET) << 2;
 759   if (RS == 31)
 760     Unpredictable ();
 761   RA = (CIA + 8);
 762   if ((signed_word) GPR[RS] >= 0)
 763     {
 764       DELAY_SLOT (NIA + offset);
 765     }
 766 }
 767
 768
 769
 770 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 771 "bgezall r<RS>, <OFFSET>"
 772 *mipsII:
 773 *mipsIII:
 774 *mipsIV:
 775 *mipsV:
 776 *mips32:
 777 *mips32r2:
 778 *mips64:
 779 *mips64r2:
 780 *vr4100:
 781 *vr5000:
 782 *r3900:
 783 {
 784   address_word offset = EXTEND16 (OFFSET) << 2;
 785   if (RS == 31)
 786     Unpredictable ();
 787   RA = (CIA + 8);
 788   /* NOTE: The branch occurs AFTER the next instruction has been
 789      executed */
 790   if ((signed_word) GPR[RS] >= 0)
 791     {
 792       DELAY_SLOT (NIA + offset);
 793     }
 794   else
 795     NULLIFY_NEXT_INSTRUCTION ();
 796 }
 797
 798
 799
 800 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 801 "bgezl r<RS>, <OFFSET>"
 802 *mipsII:
 803 *mipsIII:
 804 *mipsIV:
 805 *mipsV:
 806 *mips32:
 807 *mips32r2:
 808 *mips64:
 809 *mips64r2:
 810 *vr4100:
 811 *vr5000:
 812 *r3900:
 813 {
 814   address_word offset = EXTEND16 (OFFSET) << 2;
 815   if ((signed_word) GPR[RS] >= 0)
 816     {
 817       DELAY_SLOT (NIA + offset);
 818     }
 819   else
 820     NULLIFY_NEXT_INSTRUCTION ();
 821 }
 822
 823
 824
 825 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 826 "bgtz r<RS>, <OFFSET>"
 827 *mipsI:
 828 *mipsII:
 829 *mipsIII:
 830 *mipsIV:
 831 *mipsV:
 832 *mips32:
 833 *mips32r2:
 834 *mips64:
 835 *mips64r2:
 836 *vr4100:
 837 *vr5000:
 838 *r3900:
 839 {
 840   address_word offset = EXTEND16 (OFFSET) << 2;
 841   if ((signed_word) GPR[RS] > 0)
 842     {
 843       DELAY_SLOT (NIA + offset);
 844     }
 845 }
 846
 847
 848
 849 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 850 "bgtzl r<RS>, <OFFSET>"
 851 *mipsII:
 852 *mipsIII:
 853 *mipsIV:
 854 *mipsV:
 855 *mips32:
 856 *mips32r2:
 857 *mips64:
 858 *mips64r2:
 859 *vr4100:
 860 *vr5000:
 861 *r3900:
 862 {
 863   address_word offset = EXTEND16 (OFFSET) << 2;
 864   /* NOTE: The branch occurs AFTER the next instruction has been
 865      executed */
 866   if ((signed_word) GPR[RS] > 0)
 867     {
 868       DELAY_SLOT (NIA + offset);
 869     }
 870   else
 871     NULLIFY_NEXT_INSTRUCTION ();
 872 }
 873
 874
 875
 876 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 877 "blez r<RS>, <OFFSET>"
 878 *mipsI:
 879 *mipsII:
 880 *mipsIII:
 881 *mipsIV:
 882 *mipsV:
 883 *mips32:
 884 *mips32r2:
 885 *mips64:
 886 *mips64r2:
 887 *vr4100:
 888 *vr5000:
 889 *r3900:
 890 {
 891   address_word offset = EXTEND16 (OFFSET) << 2;
 892   /* NOTE: The branch occurs AFTER the next instruction has been
 893      executed */
 894   if ((signed_word) GPR[RS] <= 0)
 895     {
 896       DELAY_SLOT (NIA + offset);
 897     }
 898 }
 899
 900
 901
 902 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 903 "bgezl r<RS>, <OFFSET>"
 904 *mipsII:
 905 *mipsIII:
 906 *mipsIV:
 907 *mipsV:
 908 *mips32:
 909 *mips32r2:
 910 *mips64:
 911 *mips64r2:
 912 *vr4100:
 913 *vr5000:
 914 *r3900:
 915 {
 916   address_word offset = EXTEND16 (OFFSET) << 2;
 917   if ((signed_word) GPR[RS] <= 0)
 918     {
 919       DELAY_SLOT (NIA + offset);
 920     }
 921   else
 922     NULLIFY_NEXT_INSTRUCTION ();
 923 }
 924
 925
 926
 927 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 928 "bltz r<RS>, <OFFSET>"
 929 *mipsI:
 930 *mipsII:
 931 *mipsIII:
 932 *mipsIV:
 933 *mipsV:
 934 *mips32:
 935 *mips32r2:
 936 *mips64:
 937 *mips64r2:
 938 *vr4100:
 939 *vr5000:
 940 *r3900:
 941 {
 942   address_word offset = EXTEND16 (OFFSET) << 2;
 943   if ((signed_word) GPR[RS] < 0)
 944     {
 945       DELAY_SLOT (NIA + offset);
 946     }
 947 }
 948
 949
 950
 951 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 952 "bltzal r<RS>, <OFFSET>"
 953 *mipsI:
 954 *mipsII:
 955 *mipsIII:
 956 *mipsIV:
 957 *mipsV:
 958 *mips32:
 959 *mips32r2:
 960 *mips64:
 961 *mips64r2:
 962 *vr4100:
 963 *vr5000:
 964 *r3900:
 965 {
 966   address_word offset = EXTEND16 (OFFSET) << 2;
 967   if (RS == 31)
 968     Unpredictable ();
 969   RA = (CIA + 8);
 970   /* NOTE: The branch occurs AFTER the next instruction has been
 971      executed */
 972   if ((signed_word) GPR[RS] < 0)
 973     {
 974       DELAY_SLOT (NIA + offset);
 975     }
 976 }
 977
 978
 979
 980 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 981 "bltzall r<RS>, <OFFSET>"
 982 *mipsII:
 983 *mipsIII:
 984 *mipsIV:
 985 *mipsV:
 986 *mips32:
 987 *mips32r2:
 988 *mips64:
 989 *mips64r2:
 990 *vr4100:
 991 *vr5000:
 992 *r3900:
 993 {
 994   address_word offset = EXTEND16 (OFFSET) << 2;
 995   if (RS == 31)
 996     Unpredictable ();
 997   RA = (CIA + 8);
 998   if ((signed_word) GPR[RS] < 0)
 999     {
1000       DELAY_SLOT (NIA + offset);
1001     }
1002   else
1003     NULLIFY_NEXT_INSTRUCTION ();
1004 }
1005
1006
1007
1008 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1009 "bltzl r<RS>, <OFFSET>"
1010 *mipsII:
1011 *mipsIII:
1012 *mipsIV:
1013 *mipsV:
1014 *mips32:
1015 *mips32r2:
1016 *mips64:
1017 *mips64r2:
1018 *vr4100:
1019 *vr5000:
1020 *r3900:
1021 {
1022   address_word offset = EXTEND16 (OFFSET) << 2;
1023   /* NOTE: The branch occurs AFTER the next instruction has been
1024      executed */
1025   if ((signed_word) GPR[RS] < 0)
1026     {
1027       DELAY_SLOT (NIA + offset);
1028     }
1029   else
1030     NULLIFY_NEXT_INSTRUCTION ();
1031 }
1032
1033
1034
1035 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1036 "bne r<RS>, r<RT>, <OFFSET>"
1037 *mipsI:
1038 *mipsII:
1039 *mipsIII:
1040 *mipsIV:
1041 *mipsV:
1042 *mips32:
1043 *mips32r2:
1044 *mips64:
1045 *mips64r2:
1046 *vr4100:
1047 *vr5000:
1048 *r3900:
1049 {
1050   address_word offset = EXTEND16 (OFFSET) << 2;
1051   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1052     {
1053       DELAY_SLOT (NIA + offset);
1054     }
1055 }
1056
1057
1058
1059 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1060 "bnel r<RS>, r<RT>, <OFFSET>"
1061 *mipsII:
1062 *mipsIII:
1063 *mipsIV:
1064 *mipsV:
1065 *mips32:
1066 *mips32r2:
1067 *mips64:
1068 *mips64r2:
1069 *vr4100:
1070 *vr5000:
1071 *r3900:
1072 {
1073   address_word offset = EXTEND16 (OFFSET) << 2;
1074   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1075     {
1076       DELAY_SLOT (NIA + offset);
1077     }
1078   else
1079     NULLIFY_NEXT_INSTRUCTION ();
1080 }
1081
1082
1083
1084 000000,20.CODE,001101:SPECIAL:32::BREAK
1085 "break %#lx<CODE>"
1086 *mipsI:
1087 *mipsII:
1088 *mipsIII:
1089 *mipsIV:
1090 *mipsV:
1091 *mips32:
1092 *mips32r2:
1093 *mips64:
1094 *mips64r2:
1095 *vr4100:
1096 *vr5000:
1097 *r3900:
1098 {
1099   /* Check for some break instruction which are reserved for use by the simulator.  */
1100   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1101   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1102       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1103     {
1104       sim_engine_halt (SD, CPU, NULL, cia,
1105                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1106     }
1107   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1108            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1109     {
1110       if (STATE & simDELAYSLOT)
1111         PC = cia - 4; /* reference the branch instruction */
1112       else
1113         PC = cia;
1114       SignalException (BreakPoint, instruction_0);
1115     }
1116
1117   else
1118     {
1119       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1120          the exception. */
1121       SignalException (BreakPoint, instruction_0);
1122     }
1123 }
1124
1125
1126
1127 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1128 "clo r<RD>, r<RS>"
1129 *mips32:
1130 *mips32r2:
1131 *mips64:
1132 *mips64r2:
1133 *vr5500:
1134 {
1135   unsigned32 temp = GPR[RS];
1136   unsigned32 i, mask;
1137   if (RT != RD)
1138     Unpredictable ();
1139   if (NotWordValue (GPR[RS]))
1140     Unpredictable ();
1141   TRACE_ALU_INPUT1 (GPR[RS]);
1142   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1143     {
1144       if ((temp & mask) == 0)
1145         break;
1146       mask >>= 1;
1147     }
1148   GPR[RD] = EXTEND32 (i);
1149   TRACE_ALU_RESULT (GPR[RD]);
1150 }
1151
1152
1153
1154 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1155 "clz r<RD>, r<RS>"
1156 *mips32:
1157 *mips32r2:
1158 *mips64:
1159 *mips64r2:
1160 *vr5500:
1161 {
1162   unsigned32 temp = GPR[RS];
1163   unsigned32 i, mask;
1164   if (RT != RD)
1165     Unpredictable ();
1166   if (NotWordValue (GPR[RS]))
1167     Unpredictable ();
1168   TRACE_ALU_INPUT1 (GPR[RS]);
1169   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1170     {
1171       if ((temp & mask) != 0)
1172         break;
1173       mask >>= 1;
1174     }
1175   GPR[RD] = EXTEND32 (i);
1176   TRACE_ALU_RESULT (GPR[RD]);
1177 }
1178
1179
1180
1181 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1182 "dadd r<RD>, r<RS>, r<RT>"
1183 *mipsIII:
1184 *mipsIV:
1185 *mipsV:
1186 *mips64:
1187 *mips64r2:
1188 *vr4100:
1189 *vr5000:
1190 {
1191   check_u64 (SD_, instruction_0);
1192   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1193   {
1194     ALU64_BEGIN (GPR[RS]);
1195     ALU64_ADD (GPR[RT]);
1196     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1197   }
1198   TRACE_ALU_RESULT (GPR[RD]);
1199 }
1200
1201
1202
1203 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1204 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1205 *mipsIII:
1206 *mipsIV:
1207 *mipsV:
1208 *mips64:
1209 *mips64r2:
1210 *vr4100:
1211 *vr5000:
1212 {
1213   check_u64 (SD_, instruction_0);
1214   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1215   {
1216     ALU64_BEGIN (GPR[RS]);
1217     ALU64_ADD (EXTEND16 (IMMEDIATE));
1218     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1219   }
1220   TRACE_ALU_RESULT (GPR[RT]);
1221 }
1222
1223
1224
1225 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1226 {
1227   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1228   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1229   TRACE_ALU_RESULT (GPR[rt]);
1230 }
1231
1232 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1233 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1234 *mipsIII:
1235 *mipsIV:
1236 *mipsV:
1237 *mips64:
1238 *mips64r2:
1239 *vr4100:
1240 *vr5000:
1241 {
1242   check_u64 (SD_, instruction_0);
1243   do_daddiu (SD_, RS, RT, IMMEDIATE);
1244 }
1245
1246
1247
1248 :function:::void:do_daddu:int rs, int rt, int rd
1249 {
1250   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1251   GPR[rd] = GPR[rs] + GPR[rt];
1252   TRACE_ALU_RESULT (GPR[rd]);
1253 }
1254
1255 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1256 "daddu r<RD>, r<RS>, r<RT>"
1257 *mipsIII:
1258 *mipsIV:
1259 *mipsV:
1260 *mips64:
1261 *mips64r2:
1262 *vr4100:
1263 *vr5000:
1264 {
1265   check_u64 (SD_, instruction_0);
1266   do_daddu (SD_, RS, RT, RD);
1267 }
1268
1269
1270
1271 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1272 "dclo r<RD>, r<RS>"
1273 *mips64:
1274 *mips64r2:
1275 *vr5500:
1276 {
1277   unsigned64 temp = GPR[RS];
1278   unsigned32 i;
1279   unsigned64 mask;
1280   check_u64 (SD_, instruction_0);
1281   if (RT != RD)
1282     Unpredictable ();
1283   TRACE_ALU_INPUT1 (GPR[RS]);
1284   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1285     {
1286       if ((temp & mask) == 0)
1287         break;
1288       mask >>= 1;
1289     }
1290   GPR[RD] = EXTEND32 (i);
1291   TRACE_ALU_RESULT (GPR[RD]);
1292 }
1293
1294
1295
1296 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1297 "dclz r<RD>, r<RS>"
1298 *mips64:
1299 *mips64r2:
1300 *vr5500:
1301 {
1302   unsigned64 temp = GPR[RS];
1303   unsigned32 i;
1304   unsigned64 mask;
1305   check_u64 (SD_, instruction_0);
1306   if (RT != RD)
1307     Unpredictable ();
1308   TRACE_ALU_INPUT1 (GPR[RS]);
1309   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1310     {
1311       if ((temp & mask) != 0)
1312         break;
1313       mask >>= 1;
1314     }
1315   GPR[RD] = EXTEND32 (i);
1316   TRACE_ALU_RESULT (GPR[RD]);
1317 }
1318
1319
1320
1321 :function:::void:do_ddiv:int rs, int rt
1322 {
1323   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1324   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1325   {
1326     signed64 n = GPR[rs];
1327     signed64 d = GPR[rt];
1328     signed64 hi;
1329     signed64 lo;
1330     if (d == 0)
1331       {
1332         lo = SIGNED64 (0x8000000000000000);
1333         hi = 0;
1334       }
1335     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1336       {
1337         lo = SIGNED64 (0x8000000000000000);
1338         hi = 0;
1339       }
1340     else
1341       {
1342         lo = (n / d);
1343         hi = (n % d);
1344       }
1345     HI = hi;
1346     LO = lo;
1347   }
1348   TRACE_ALU_RESULT2 (HI, LO);
1349 }
1350
1351 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1352 "ddiv r<RS>, r<RT>"
1353 *mipsIII:
1354 *mipsIV:
1355 *mipsV:
1356 *mips64:
1357 *mips64r2:
1358 *vr4100:
1359 *vr5000:
1360 {
1361   check_u64 (SD_, instruction_0);
1362   do_ddiv (SD_, RS, RT);
1363 }
1364
1365
1366
1367 :function:::void:do_ddivu:int rs, int rt
1368 {
1369   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1370   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1371   {
1372     unsigned64 n = GPR[rs];
1373     unsigned64 d = GPR[rt];
1374     unsigned64 hi;
1375     unsigned64 lo;
1376     if (d == 0)
1377       {
1378         lo = SIGNED64 (0x8000000000000000);
1379         hi = 0;
1380       }
1381     else
1382       {
1383         lo = (n / d);
1384         hi = (n % d);
1385       }
1386     HI = hi;
1387     LO = lo;
1388   }
1389   TRACE_ALU_RESULT2 (HI, LO);
1390 }
1391
1392 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1393 "ddivu r<RS>, r<RT>"
1394 *mipsIII:
1395 *mipsIV:
1396 *mipsV:
1397 *mips64:
1398 *mips64r2:
1399 *vr4100:
1400 *vr5000:
1401 {
1402   check_u64 (SD_, instruction_0);
1403   do_ddivu (SD_, RS, RT);
1404 }
1405
1406 :function:::void:do_div:int rs, int rt
1407 {
1408   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1409   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1410   {
1411     signed32 n = GPR[rs];
1412     signed32 d = GPR[rt];
1413     if (d == 0)
1414       {
1415         LO = EXTEND32 (0x80000000);
1416         HI = EXTEND32 (0);
1417       }
1418     else if (n == SIGNED32 (0x80000000) && d == -1)
1419       {
1420         LO = EXTEND32 (0x80000000);
1421         HI = EXTEND32 (0);
1422       }
1423     else
1424       {
1425         LO = EXTEND32 (n / d);
1426         HI = EXTEND32 (n % d);
1427       }
1428   }
1429   TRACE_ALU_RESULT2 (HI, LO);
1430 }
1431
1432 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1433 "div r<RS>, r<RT>"
1434 *mipsI:
1435 *mipsII:
1436 *mipsIII:
1437 *mipsIV:
1438 *mipsV:
1439 *mips32:
1440 *mips32r2:
1441 *mips64:
1442 *mips64r2:
1443 *vr4100:
1444 *vr5000:
1445 *r3900:
1446 {
1447   do_div (SD_, RS, RT);
1448 }
1449
1450
1451
1452 :function:::void:do_divu:int rs, int rt
1453 {
1454   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1455   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1456   {
1457     unsigned32 n = GPR[rs];
1458     unsigned32 d = GPR[rt];
1459     if (d == 0)
1460       {
1461         LO = EXTEND32 (0x80000000);
1462         HI = EXTEND32 (0);
1463       }
1464     else
1465       {
1466         LO = EXTEND32 (n / d);
1467         HI = EXTEND32 (n % d);
1468       }
1469   }
1470   TRACE_ALU_RESULT2 (HI, LO);
1471 }
1472
1473 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1474 "divu r<RS>, r<RT>"
1475 *mipsI:
1476 *mipsII:
1477 *mipsIII:
1478 *mipsIV:
1479 *mipsV:
1480 *mips32:
1481 *mips32r2:
1482 *mips64:
1483 *mips64r2:
1484 *vr4100:
1485 *vr5000:
1486 *r3900:
1487 {
1488   do_divu (SD_, RS, RT);
1489 }
1490
1491
1492 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1493 {
1494   unsigned64 lo;
1495   unsigned64 hi;
1496   unsigned64 m00;
1497   unsigned64 m01;
1498   unsigned64 m10;
1499   unsigned64 m11;
1500   unsigned64 mid;
1501   int sign;
1502   unsigned64 op1 = GPR[rs];
1503   unsigned64 op2 = GPR[rt];
1504   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1505   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1506   /* make signed multiply unsigned */
1507   sign = 0;
1508   if (signed_p)
1509     {
1510       if ((signed64) op1 < 0)
1511         {
1512           op1 = - op1;
1513           ++sign;
1514         }
1515       if ((signed64) op2 < 0)
1516         {
1517           op2 = - op2;
1518           ++sign;
1519         }
1520     }
1521   /* multiply out the 4 sub products */
1522   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1523   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1524   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1525   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1526   /* add the products */
1527   mid = ((unsigned64) VH4_8 (m00)
1528          + (unsigned64) VL4_8 (m10)
1529          + (unsigned64) VL4_8 (m01));
1530   lo = U8_4 (mid, m00);
1531   hi = (m11
1532         + (unsigned64) VH4_8 (mid)
1533         + (unsigned64) VH4_8 (m01)
1534         + (unsigned64) VH4_8 (m10));
1535   /* fix the sign */
1536   if (sign & 1)
1537     {
1538       lo = -lo;
1539       if (lo == 0)
1540         hi = -hi;
1541       else
1542         hi = -hi - 1;
1543     }
1544   /* save the result HI/LO (and a gpr) */
1545   LO = lo;
1546   HI = hi;
1547   if (rd != 0)
1548     GPR[rd] = lo;
1549   TRACE_ALU_RESULT2 (HI, LO);
1550 }
1551
1552 :function:::void:do_dmult:int rs, int rt, int rd
1553 {
1554   do_dmultx (SD_, rs, rt, rd, 1);
1555 }
1556
1557 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1558 "dmult r<RS>, r<RT>"
1559 *mipsIII:
1560 *mipsIV:
1561 *mipsV:
1562 *mips64:
1563 *mips64r2:
1564 *vr4100:
1565 {
1566   check_u64 (SD_, instruction_0);
1567   do_dmult (SD_, RS, RT, 0);
1568 }
1569
1570 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1571 "dmult r<RS>, r<RT>":RD == 0
1572 "dmult r<RD>, r<RS>, r<RT>"
1573 *vr5000:
1574 {
1575   check_u64 (SD_, instruction_0);
1576   do_dmult (SD_, RS, RT, RD);
1577 }
1578
1579
1580
1581 :function:::void:do_dmultu:int rs, int rt, int rd
1582 {
1583   do_dmultx (SD_, rs, rt, rd, 0);
1584 }
1585
1586 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1587 "dmultu r<RS>, r<RT>"
1588 *mipsIII:
1589 *mipsIV:
1590 *mipsV:
1591 *mips64:
1592 *mips64r2:
1593 *vr4100:
1594 {
1595   check_u64 (SD_, instruction_0);
1596   do_dmultu (SD_, RS, RT, 0);
1597 }
1598
1599 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1600 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1601 "dmultu r<RS>, r<RT>"
1602 *vr5000:
1603 {
1604   check_u64 (SD_, instruction_0);
1605   do_dmultu (SD_, RS, RT, RD);
1606 }
1607
1608
1609 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1610 {
1611   unsigned64 result;
1612
1613   y &= 63;
1614   TRACE_ALU_INPUT2 (x, y);
1615   result = ROTR64 (x, y);
1616   TRACE_ALU_RESULT (result);
1617   return result;
1618 }
1619
1620 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1621 "dror r<RD>, r<RT>, <SHIFT>"
1622 *mips64r2:
1623 *vr5400:
1624 *vr5500:
1625 {
1626   check_u64 (SD_, instruction_0);
1627   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1628 }
1629
1630 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1631 "dror32 r<RD>, r<RT>, <SHIFT>"
1632 *mips64r2:
1633 *vr5400:
1634 *vr5500:
1635 {
1636   check_u64 (SD_, instruction_0);
1637   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1638 }
1639
1640 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1641 "drorv r<RD>, r<RT>, r<RS>"
1642 *mips64r2:
1643 *vr5400:
1644 *vr5500:
1645 {
1646   check_u64 (SD_, instruction_0);
1647   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1648 }
1649
1650
1651 :function:::void:do_dsll:int rt, int rd, int shift
1652 {
1653   TRACE_ALU_INPUT2 (GPR[rt], shift);
1654   GPR[rd] = GPR[rt] << shift;
1655   TRACE_ALU_RESULT (GPR[rd]);
1656 }
1657
1658 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1659 "dsll r<RD>, r<RT>, <SHIFT>"
1660 *mipsIII:
1661 *mipsIV:
1662 *mipsV:
1663 *mips64:
1664 *mips64r2:
1665 *vr4100:
1666 *vr5000:
1667 {
1668   check_u64 (SD_, instruction_0);
1669   do_dsll (SD_, RT, RD, SHIFT);
1670 }
1671
1672
1673 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1674 "dsll32 r<RD>, r<RT>, <SHIFT>"
1675 *mipsIII:
1676 *mipsIV:
1677 *mipsV:
1678 *mips64:
1679 *mips64r2:
1680 *vr4100:
1681 *vr5000:
1682 {
1683   int s = 32 + SHIFT;
1684   check_u64 (SD_, instruction_0);
1685   TRACE_ALU_INPUT2 (GPR[RT], s);
1686   GPR[RD] = GPR[RT] << s;
1687   TRACE_ALU_RESULT (GPR[RD]);
1688 }
1689
1690 :function:::void:do_dsllv:int rs, int rt, int rd
1691 {
1692   int s = MASKED64 (GPR[rs], 5, 0);
1693   TRACE_ALU_INPUT2 (GPR[rt], s);
1694   GPR[rd] = GPR[rt] << s;
1695   TRACE_ALU_RESULT (GPR[rd]);
1696 }
1697
1698 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1699 "dsllv r<RD>, r<RT>, r<RS>"
1700 *mipsIII:
1701 *mipsIV:
1702 *mipsV:
1703 *mips64:
1704 *mips64r2:
1705 *vr4100:
1706 *vr5000:
1707 {
1708   check_u64 (SD_, instruction_0);
1709   do_dsllv (SD_, RS, RT, RD);
1710 }
1711
1712 :function:::void:do_dsra:int rt, int rd, int shift
1713 {
1714   TRACE_ALU_INPUT2 (GPR[rt], shift);
1715   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1716   TRACE_ALU_RESULT (GPR[rd]);
1717 }
1718
1719
1720 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1721 "dsra r<RD>, r<RT>, <SHIFT>"
1722 *mipsIII:
1723 *mipsIV:
1724 *mipsV:
1725 *mips64:
1726 *mips64r2:
1727 *vr4100:
1728 *vr5000:
1729 {
1730   check_u64 (SD_, instruction_0);
1731   do_dsra (SD_, RT, RD, SHIFT);
1732 }
1733
1734
1735 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1736 "dsra32 r<RD>, r<RT>, <SHIFT>"
1737 *mipsIII:
1738 *mipsIV:
1739 *mipsV:
1740 *mips64:
1741 *mips64r2:
1742 *vr4100:
1743 *vr5000:
1744 {
1745   int s = 32 + SHIFT;
1746   check_u64 (SD_, instruction_0);
1747   TRACE_ALU_INPUT2 (GPR[RT], s);
1748   GPR[RD] = ((signed64) GPR[RT]) >> s;
1749   TRACE_ALU_RESULT (GPR[RD]);
1750 }
1751
1752
1753 :function:::void:do_dsrav:int rs, int rt, int rd
1754 {
1755   int s = MASKED64 (GPR[rs], 5, 0);
1756   TRACE_ALU_INPUT2 (GPR[rt], s);
1757   GPR[rd] = ((signed64) GPR[rt]) >> s;
1758   TRACE_ALU_RESULT (GPR[rd]);
1759 }
1760
1761 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1762 "dsrav r<RD>, r<RT>, r<RS>"
1763 *mipsIII:
1764 *mipsIV:
1765 *mipsV:
1766 *mips64:
1767 *mips64r2:
1768 *vr4100:
1769 *vr5000:
1770 {
1771   check_u64 (SD_, instruction_0);
1772   do_dsrav (SD_, RS, RT, RD);
1773 }
1774
1775 :function:::void:do_dsrl:int rt, int rd, int shift
1776 {
1777   TRACE_ALU_INPUT2 (GPR[rt], shift);
1778   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1779   TRACE_ALU_RESULT (GPR[rd]);
1780 }
1781
1782
1783 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1784 "dsrl r<RD>, r<RT>, <SHIFT>"
1785 *mipsIII:
1786 *mipsIV:
1787 *mipsV:
1788 *mips64:
1789 *mips64r2:
1790 *vr4100:
1791 *vr5000:
1792 {
1793   check_u64 (SD_, instruction_0);
1794   do_dsrl (SD_, RT, RD, SHIFT);
1795 }
1796
1797
1798 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1799 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1800 *mipsIII:
1801 *mipsIV:
1802 *mipsV:
1803 *mips64:
1804 *mips64r2:
1805 *vr4100:
1806 *vr5000:
1807 {
1808   int s = 32 + SHIFT;
1809   check_u64 (SD_, instruction_0);
1810   TRACE_ALU_INPUT2 (GPR[RT], s);
1811   GPR[RD] = (unsigned64) GPR[RT] >> s;
1812   TRACE_ALU_RESULT (GPR[RD]);
1813 }
1814
1815
1816 :function:::void:do_dsrlv:int rs, int rt, int rd
1817 {
1818   int s = MASKED64 (GPR[rs], 5, 0);
1819   TRACE_ALU_INPUT2 (GPR[rt], s);
1820   GPR[rd] = (unsigned64) GPR[rt] >> s;
1821   TRACE_ALU_RESULT (GPR[rd]);
1822 }
1823
1824
1825
1826 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1827 "dsrlv r<RD>, r<RT>, r<RS>"
1828 *mipsIII:
1829 *mipsIV:
1830 *mipsV:
1831 *mips64:
1832 *mips64r2:
1833 *vr4100:
1834 *vr5000:
1835 {
1836   check_u64 (SD_, instruction_0);
1837   do_dsrlv (SD_, RS, RT, RD);
1838 }
1839
1840
1841 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1842 "dsub r<RD>, r<RS>, r<RT>"
1843 *mipsIII:
1844 *mipsIV:
1845 *mipsV:
1846 *mips64:
1847 *mips64r2:
1848 *vr4100:
1849 *vr5000:
1850 {
1851   check_u64 (SD_, instruction_0);
1852   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1853   {
1854     ALU64_BEGIN (GPR[RS]);
1855     ALU64_SUB (GPR[RT]);
1856     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1857   }
1858   TRACE_ALU_RESULT (GPR[RD]);
1859 }
1860
1861
1862 :function:::void:do_dsubu:int rs, int rt, int rd
1863 {
1864   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1865   GPR[rd] = GPR[rs] - GPR[rt];
1866   TRACE_ALU_RESULT (GPR[rd]);
1867 }
1868
1869 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1870 "dsubu r<RD>, r<RS>, r<RT>"
1871 *mipsIII:
1872 *mipsIV:
1873 *mipsV:
1874 *mips64:
1875 *mips64r2:
1876 *vr4100:
1877 *vr5000:
1878 {
1879   check_u64 (SD_, instruction_0);
1880   do_dsubu (SD_, RS, RT, RD);
1881 }
1882
1883
1884 000010,26.INSTR_INDEX:NORMAL:32::J
1885 "j <INSTR_INDEX>"
1886 *mipsI:
1887 *mipsII:
1888 *mipsIII:
1889 *mipsIV:
1890 *mipsV:
1891 *mips32:
1892 *mips32r2:
1893 *mips64:
1894 *mips64r2:
1895 *vr4100:
1896 *vr5000:
1897 *r3900:
1898 {
1899   /* NOTE: The region used is that of the delay slot NIA and NOT the
1900      current instruction */
1901   address_word region = (NIA & MASK (63, 28));
1902   DELAY_SLOT (region | (INSTR_INDEX << 2));
1903 }
1904
1905
1906 000011,26.INSTR_INDEX:NORMAL:32::JAL
1907 "jal <INSTR_INDEX>"
1908 *mipsI:
1909 *mipsII:
1910 *mipsIII:
1911 *mipsIV:
1912 *mipsV:
1913 *mips32:
1914 *mips32r2:
1915 *mips64:
1916 *mips64r2:
1917 *vr4100:
1918 *vr5000:
1919 *r3900:
1920 {
1921   /* NOTE: The region used is that of the delay slot and NOT the
1922      current instruction */
1923   address_word region = (NIA & MASK (63, 28));
1924   GPR[31] = CIA + 8;
1925   DELAY_SLOT (region | (INSTR_INDEX << 2));
1926 }
1927
1928 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1929 "jalr r<RS>":RD == 31
1930 "jalr r<RD>, r<RS>"
1931 *mipsI:
1932 *mipsII:
1933 *mipsIII:
1934 *mipsIV:
1935 *mipsV:
1936 *mips32:
1937 *mips32r2:
1938 *mips64:
1939 *mips64r2:
1940 *vr4100:
1941 *vr5000:
1942 *r3900:
1943 {
1944   address_word temp = GPR[RS];
1945   GPR[RD] = CIA + 8;
1946   DELAY_SLOT (temp);
1947 }
1948
1949 000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
1950 "jalr.hb r<RS>":RD == 31
1951 "jalr.hb r<RD>, r<RS>"
1952 *mips32r2:
1953 *mips64r2:
1954 {
1955   address_word temp = GPR[RS];
1956   GPR[RD] = CIA + 8;
1957   DELAY_SLOT (temp);
1958 }
1959
1960 000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
1961 "jr r<RS>"
1962 *mipsI:
1963 *mipsII:
1964 *mipsIII:
1965 *mipsIV:
1966 *mipsV:
1967 *mips32:
1968 *mips32r2:
1969 *mips64:
1970 *mips64r2:
1971 *vr4100:
1972 *vr5000:
1973 *r3900:
1974 {
1975   DELAY_SLOT (GPR[RS]);
1976 }
1977
1978 000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
1979 "jr.hb r<RS>"
1980 *mips32r2:
1981 *mips64r2:
1982 {
1983   DELAY_SLOT (GPR[RS]);
1984 }
1985
1986 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1987 {
1988   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1989   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1990   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1991   unsigned int byte;
1992   address_word paddr;
1993   int uncached;
1994   unsigned64 memval;
1995   address_word vaddr;
1996
1997   vaddr = loadstore_ea (SD_, base, offset);
1998   if ((vaddr & access) != 0)
1999     {
2000       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
2001     }
2002   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2003   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2004   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2005   byte = ((vaddr & mask) ^ bigendiancpu);
2006   return (memval >> (8 * byte));
2007 }
2008
2009 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2010 {
2011   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2012   address_word reverseendian = (ReverseEndian ? -1 : 0);
2013   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2014   unsigned int byte;
2015   unsigned int word;
2016   address_word paddr;
2017   int uncached;
2018   unsigned64 memval;
2019   address_word vaddr;
2020   int nr_lhs_bits;
2021   int nr_rhs_bits;
2022   unsigned_word lhs_mask;
2023   unsigned_word temp;
2024
2025   vaddr = loadstore_ea (SD_, base, offset);
2026   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2027   paddr = (paddr ^ (reverseendian & mask));
2028   if (BigEndianMem == 0)
2029     paddr = paddr & ~access;
2030
2031   /* compute where within the word/mem we are */
2032   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2033   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2034   nr_lhs_bits = 8 * byte + 8;
2035   nr_rhs_bits = 8 * access - 8 * byte;
2036   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2037
2038   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2039            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2040            (long) ((unsigned64) paddr >> 32), (long) paddr,
2041            word, byte, nr_lhs_bits, nr_rhs_bits); */
2042
2043   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2044   if (word == 0)
2045     {
2046       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2047       temp = (memval << nr_rhs_bits);
2048     }
2049   else
2050     {
2051       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2052       temp = (memval >> nr_lhs_bits);
2053     }
2054   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2055   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2056
2057   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2058            (long) ((unsigned64) memval >> 32), (long) memval,
2059            (long) ((unsigned64) temp >> 32), (long) temp,
2060            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2061            (long) (rt >> 32), (long) rt); */
2062   return rt;
2063 }
2064
2065 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2066 {
2067   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2068   address_word reverseendian = (ReverseEndian ? -1 : 0);
2069   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2070   unsigned int byte;
2071   address_word paddr;
2072   int uncached;
2073   unsigned64 memval;
2074   address_word vaddr;
2075
2076   vaddr = loadstore_ea (SD_, base, offset);
2077   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2078   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2079   paddr = (paddr ^ (reverseendian & mask));
2080   if (BigEndianMem != 0)
2081     paddr = paddr & ~access;
2082   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2083   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2084   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2085   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2086      (long) paddr, byte, (long) paddr, (long) memval); */
2087   {
2088     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2089     rt &= ~screen;
2090     rt |= (memval >> (8 * byte)) & screen;
2091   }
2092   return rt;
2093 }
2094
2095
2096 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2097 "lb r<RT>, <OFFSET>(r<BASE>)"
2098 *mipsI:
2099 *mipsII:
2100 *mipsIII:
2101 *mipsIV:
2102 *mipsV:
2103 *mips32:
2104 *mips32r2:
2105 *mips64:
2106 *mips64r2:
2107 *vr4100:
2108 *vr5000:
2109 *r3900:
2110 {
2111   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2112 }
2113
2114
2115 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2116 "lbu r<RT>, <OFFSET>(r<BASE>)"
2117 *mipsI:
2118 *mipsII:
2119 *mipsIII:
2120 *mipsIV:
2121 *mipsV:
2122 *mips32:
2123 *mips32r2:
2124 *mips64:
2125 *mips64r2:
2126 *vr4100:
2127 *vr5000:
2128 *r3900:
2129 {
2130   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2131 }
2132
2133
2134 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2135 "ld r<RT>, <OFFSET>(r<BASE>)"
2136 *mipsIII:
2137 *mipsIV:
2138 *mipsV:
2139 *mips64:
2140 *mips64r2:
2141 *vr4100:
2142 *vr5000:
2143 {
2144   check_u64 (SD_, instruction_0);
2145   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2146 }
2147
2148
2149 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2150 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2151 *mipsII:
2152 *mipsIII:
2153 *mipsIV:
2154 *mipsV:
2155 *mips32:
2156 *mips32r2:
2157 *mips64:
2158 *mips64r2:
2159 *vr4100:
2160 *vr5000:
2161 *r3900:
2162 {
2163   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2164 }
2165
2166
2167
2168
2169 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2170 "ldl r<RT>, <OFFSET>(r<BASE>)"
2171 *mipsIII:
2172 *mipsIV:
2173 *mipsV:
2174 *mips64:
2175 *mips64r2:
2176 *vr4100:
2177 *vr5000:
2178 {
2179   check_u64 (SD_, instruction_0);
2180   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2181 }
2182
2183
2184 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2185 "ldr r<RT>, <OFFSET>(r<BASE>)"
2186 *mipsIII:
2187 *mipsIV:
2188 *mipsV:
2189 *mips64:
2190 *mips64r2:
2191 *vr4100:
2192 *vr5000:
2193 {
2194   check_u64 (SD_, instruction_0);
2195   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2196 }
2197
2198
2199 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2200 "lh r<RT>, <OFFSET>(r<BASE>)"
2201 *mipsI:
2202 *mipsII:
2203 *mipsIII:
2204 *mipsIV:
2205 *mipsV:
2206 *mips32:
2207 *mips32r2:
2208 *mips64:
2209 *mips64r2:
2210 *vr4100:
2211 *vr5000:
2212 *r3900:
2213 {
2214   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2215 }
2216
2217
2218 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2219 "lhu r<RT>, <OFFSET>(r<BASE>)"
2220 *mipsI:
2221 *mipsII:
2222 *mipsIII:
2223 *mipsIV:
2224 *mipsV:
2225 *mips32:
2226 *mips32r2:
2227 *mips64:
2228 *mips64r2:
2229 *vr4100:
2230 *vr5000:
2231 *r3900:
2232 {
2233   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2234 }
2235
2236
2237 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2238 "ll r<RT>, <OFFSET>(r<BASE>)"
2239 *mipsII:
2240 *mipsIII:
2241 *mipsIV:
2242 *mipsV:
2243 *mips32:
2244 *mips32r2:
2245 *mips64:
2246 *mips64r2:
2247 *vr4100:
2248 *vr5000:
2249 {
2250   address_word base = GPR[BASE];
2251   address_word offset = EXTEND16 (OFFSET);
2252   {
2253     address_word vaddr = loadstore_ea (SD_, base, offset);
2254     address_word paddr;
2255     int uncached;
2256     if ((vaddr & 3) != 0)
2257       {
2258         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2259       }
2260     else
2261       {
2262         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2263           {
2264             unsigned64 memval = 0;
2265             unsigned64 memval1 = 0;
2266             unsigned64 mask = 0x7;
2267             unsigned int shift = 2;
2268             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2269             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2270             unsigned int byte;
2271             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2272             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2273             byte = ((vaddr & mask) ^ (bigend << shift));
2274             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2275             LLBIT = 1;
2276           }
2277       }
2278   }
2279 }
2280
2281
2282 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2283 "lld r<RT>, <OFFSET>(r<BASE>)"
2284 *mipsIII:
2285 *mipsIV:
2286 *mipsV:
2287 *mips64:
2288 *mips64r2:
2289 *vr4100:
2290 *vr5000:
2291 {
2292   address_word base = GPR[BASE];
2293   address_word offset = EXTEND16 (OFFSET);
2294   check_u64 (SD_, instruction_0);
2295   {
2296     address_word vaddr = loadstore_ea (SD_, base, offset);
2297     address_word paddr;
2298     int uncached;
2299     if ((vaddr & 7) != 0)
2300       {
2301         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2302       }
2303     else
2304       {
2305         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2306           {
2307             unsigned64 memval = 0;
2308             unsigned64 memval1 = 0;
2309             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2310             GPR[RT] = memval;
2311             LLBIT = 1;
2312           }
2313       }
2314   }
2315 }
2316
2317
2318 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2319 "lui r<RT>, %#lx<IMMEDIATE>"
2320 *mipsI:
2321 *mipsII:
2322 *mipsIII:
2323 *mipsIV:
2324 *mipsV:
2325 *mips32:
2326 *mips32r2:
2327 *mips64:
2328 *mips64r2:
2329 *vr4100:
2330 *vr5000:
2331 *r3900:
2332 {
2333   TRACE_ALU_INPUT1 (IMMEDIATE);
2334   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2335   TRACE_ALU_RESULT (GPR[RT]);
2336 }
2337
2338
2339 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2340 "lw r<RT>, <OFFSET>(r<BASE>)"
2341 *mipsI:
2342 *mipsII:
2343 *mipsIII:
2344 *mipsIV:
2345 *mipsV:
2346 *mips32:
2347 *mips32r2:
2348 *mips64:
2349 *mips64r2:
2350 *vr4100:
2351 *vr5000:
2352 *r3900:
2353 {
2354   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2355 }
2356
2357
2358 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2359 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2360 *mipsI:
2361 *mipsII:
2362 *mipsIII:
2363 *mipsIV:
2364 *mipsV:
2365 *mips32:
2366 *mips32r2:
2367 *mips64:
2368 *mips64r2:
2369 *vr4100:
2370 *vr5000:
2371 *r3900:
2372 {
2373   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2374 }
2375
2376
2377 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2378 "lwl r<RT>, <OFFSET>(r<BASE>)"
2379 *mipsI:
2380 *mipsII:
2381 *mipsIII:
2382 *mipsIV:
2383 *mipsV:
2384 *mips32:
2385 *mips32r2:
2386 *mips64:
2387 *mips64r2:
2388 *vr4100:
2389 *vr5000:
2390 *r3900:
2391 {
2392   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2393 }
2394
2395
2396 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2397 "lwr r<RT>, <OFFSET>(r<BASE>)"
2398 *mipsI:
2399 *mipsII:
2400 *mipsIII:
2401 *mipsIV:
2402 *mipsV:
2403 *mips32:
2404 *mips32r2:
2405 *mips64:
2406 *mips64r2:
2407 *vr4100:
2408 *vr5000:
2409 *r3900:
2410 {
2411   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2412 }
2413
2414
2415 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2416 "lwu r<RT>, <OFFSET>(r<BASE>)"
2417 *mipsIII:
2418 *mipsIV:
2419 *mipsV:
2420 *mips64:
2421 *mips64r2:
2422 *vr4100:
2423 *vr5000:
2424 {
2425   check_u64 (SD_, instruction_0);
2426   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2427 }
2428
2429
2430
2431 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2432 "madd r<RS>, r<RT>"
2433 *mips32:
2434 *mips64:
2435 *vr5500:
2436 {
2437   signed64 temp;
2438   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2439   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2440     Unpredictable ();
2441   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2442   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2443           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2444   LO = EXTEND32 (temp);
2445   HI = EXTEND32 (VH4_8 (temp));
2446   TRACE_ALU_RESULT2 (HI, LO);
2447 }
2448
2449
2450 011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
2451 "madd r<RS>, r<RT>":AC == 0
2452 "madd ac<AC>, r<RS>, r<RT>"
2453 *mips32r2:
2454 *mips64r2:
2455 *dsp2:
2456 {
2457   signed64 temp;
2458   if (AC == 0)
2459     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2460   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2461     Unpredictable ();
2462   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2463   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2464           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2465   DSPLO(AC) = EXTEND32 (temp);
2466   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2467   if (AC == 0)
2468     TRACE_ALU_RESULT2 (HI, LO);
2469 }
2470
2471
2472 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2473 "maddu r<RS>, r<RT>"
2474 *mips32:
2475 *mips64:
2476 *vr5500:
2477 {
2478   unsigned64 temp;
2479   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2480   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2481     Unpredictable ();
2482   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2483   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2484           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2485   ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
2486   LO = EXTEND32 (temp);
2487   HI = EXTEND32 (VH4_8 (temp));
2488   TRACE_ALU_RESULT2 (HI, LO);
2489 }
2490
2491
2492 011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
2493 "maddu r<RS>, r<RT>":AC == 0
2494 "maddu ac<AC>, r<RS>, r<RT>"
2495 *mips32r2:
2496 *mips64r2:
2497 *dsp2:
2498 {
2499   unsigned64 temp;
2500   if (AC == 0)
2501     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2502   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2503     Unpredictable ();
2504   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2505   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2506           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2507   if (AC == 0)
2508     ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
2509   DSPLO(AC) = EXTEND32 (temp);
2510   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2511   if (AC == 0)
2512     TRACE_ALU_RESULT2 (HI, LO);
2513 }
2514
2515
2516 :function:::void:do_mfhi:int rd
2517 {
2518   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2519   TRACE_ALU_INPUT1 (HI);
2520   GPR[rd] = HI;
2521   TRACE_ALU_RESULT (GPR[rd]);
2522 }
2523
2524 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2525 "mfhi r<RD>"
2526 *mipsI:
2527 *mipsII:
2528 *mipsIII:
2529 *mipsIV:
2530 *mipsV:
2531 *vr4100:
2532 *vr5000:
2533 *r3900:
2534 {
2535   do_mfhi (SD_, RD);
2536 }
2537
2538
2539 000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
2540 "mfhi r<RD>":AC == 0
2541 "mfhi r<RD>, ac<AC>"
2542 *mips32r2:
2543 *mips64r2:
2544 *dsp:
2545 {
2546   if (AC == 0)
2547     do_mfhi (SD_, RD);
2548   else
2549     GPR[RD] = DSPHI(AC);
2550 }
2551
2552
2553 :function:::void:do_mflo:int rd
2554 {
2555   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2556   TRACE_ALU_INPUT1 (LO);
2557   GPR[rd] = LO;
2558   TRACE_ALU_RESULT (GPR[rd]);
2559 }
2560
2561 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2562 "mflo r<RD>"
2563 *mipsI:
2564 *mipsII:
2565 *mipsIII:
2566 *mipsIV:
2567 *mipsV:
2568 *vr4100:
2569 *vr5000:
2570 *r3900:
2571 {
2572   do_mflo (SD_, RD);
2573 }
2574
2575
2576 000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
2577 "mflo r<RD>":AC == 0
2578 "mflo r<RD>, ac<AC>"
2579 *mips32r2:
2580 *mips64r2:
2581 *dsp:
2582 {
2583   if (AC == 0)
2584     do_mflo (SD_, RD);
2585   else
2586     GPR[RD] = DSPLO(AC);
2587 }
2588
2589
2590 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2591 "movn r<RD>, r<RS>, r<RT>"
2592 *mipsIV:
2593 *mipsV:
2594 *mips32:
2595 *mips32r2:
2596 *mips64:
2597 *mips64r2:
2598 *vr5000:
2599 {
2600   if (GPR[RT] != 0)
2601     {
2602       GPR[RD] = GPR[RS];
2603       TRACE_ALU_RESULT (GPR[RD]);
2604     }
2605 }
2606
2607
2608
2609 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2610 "movz r<RD>, r<RS>, r<RT>"
2611 *mipsIV:
2612 *mipsV:
2613 *mips32:
2614 *mips32r2:
2615 *mips64:
2616 *mips64r2:
2617 *vr5000:
2618 {
2619   if (GPR[RT] == 0)
2620     {
2621       GPR[RD] = GPR[RS];
2622       TRACE_ALU_RESULT (GPR[RD]);
2623     }
2624 }
2625
2626
2627
2628 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2629 "msub r<RS>, r<RT>"
2630 *mips32:
2631 *mips64:
2632 *vr5500:
2633 {
2634   signed64 temp;
2635   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2636   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2637     Unpredictable ();
2638   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2639   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2640           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2641   LO = EXTEND32 (temp);
2642   HI = EXTEND32 (VH4_8 (temp));
2643   TRACE_ALU_RESULT2 (HI, LO);
2644 }
2645
2646
2647 011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
2648 "msub r<RS>, r<RT>":AC == 0
2649 "msub ac<AC>, r<RS>, r<RT>"
2650 *mips32r2:
2651 *mips64r2:
2652 *dsp2:
2653 {
2654   signed64 temp;
2655   if (AC == 0)
2656     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2657   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2658     Unpredictable ();
2659   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2660   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2661           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2662   DSPLO(AC) = EXTEND32 (temp);
2663   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2664   if (AC == 0)
2665     TRACE_ALU_RESULT2 (HI, LO);
2666 }
2667
2668
2669 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2670 "msubu r<RS>, r<RT>"
2671 *mips32:
2672 *mips64:
2673 *vr5500:
2674 {
2675   unsigned64 temp;
2676   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2677   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2678     Unpredictable ();
2679   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2680   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2681           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2682   LO = EXTEND32 (temp);
2683   HI = EXTEND32 (VH4_8 (temp));
2684   TRACE_ALU_RESULT2 (HI, LO);
2685 }
2686
2687
2688 011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
2689 "msubu r<RS>, r<RT>":AC == 0
2690 "msubu ac<AC>, r<RS>, r<RT>"
2691 *mips32r2:
2692 *mips64r2:
2693 *dsp2:
2694 {
2695   unsigned64 temp;
2696   if (AC == 0)
2697     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2698   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2699     Unpredictable ();
2700   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2701   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2702           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2703   DSPLO(AC) = EXTEND32 (temp);
2704   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2705   if (AC == 0)
2706     TRACE_ALU_RESULT2 (HI, LO);
2707 }
2708
2709
2710 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2711 "mthi r<RS>"
2712 *mipsI:
2713 *mipsII:
2714 *mipsIII:
2715 *mipsIV:
2716 *mipsV:
2717 *vr4100:
2718 *vr5000:
2719 *r3900:
2720 {
2721   check_mt_hilo (SD_, HIHISTORY);
2722   HI = GPR[RS];
2723 }
2724
2725
2726 000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
2727 "mthi r<RS>":AC == 0
2728 "mthi r<RS>, ac<AC>"
2729 *mips32r2:
2730 *mips64r2:
2731 *dsp:
2732 {
2733   if (AC == 0)
2734     check_mt_hilo (SD_, HIHISTORY);
2735   DSPHI(AC) = GPR[RS];
2736 }
2737
2738
2739 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2740 "mtlo r<RS>"
2741 *mipsI:
2742 *mipsII:
2743 *mipsIII:
2744 *mipsIV:
2745 *mipsV:
2746 *vr4100:
2747 *vr5000:
2748 *r3900:
2749 {
2750   check_mt_hilo (SD_, LOHISTORY);
2751   LO = GPR[RS];
2752 }
2753
2754
2755 000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
2756 "mtlo r<RS>":AC == 0
2757 "mtlo r<RS>, ac<AC>"
2758 *mips32r2:
2759 *mips64r2:
2760 *dsp:
2761 {
2762   if (AC == 0)
2763     check_mt_hilo (SD_, LOHISTORY);
2764   DSPLO(AC) = GPR[RS];
2765 }
2766
2767
2768 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2769 "mul r<RD>, r<RS>, r<RT>"
2770 *mips32:
2771 *mips32r2:
2772 *mips64:
2773 *mips64r2:
2774 *vr5500:
2775 {
2776   signed64 prod;
2777   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2778     Unpredictable ();
2779   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2780   prod = (((signed64)(signed32) GPR[RS])
2781           * ((signed64)(signed32) GPR[RT]));
2782   GPR[RD] = EXTEND32 (VL4_8 (prod));
2783   TRACE_ALU_RESULT (GPR[RD]);
2784 }
2785
2786
2787
2788 :function:::void:do_mult:int rs, int rt, int rd
2789 {
2790   signed64 prod;
2791   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2792   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2793     Unpredictable ();
2794   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2795   prod = (((signed64)(signed32) GPR[rs])
2796           * ((signed64)(signed32) GPR[rt]));
2797   LO = EXTEND32 (VL4_8 (prod));
2798   HI = EXTEND32 (VH4_8 (prod));
2799   ACX = 0;  /* SmartMIPS */
2800   if (rd != 0)
2801     GPR[rd] = LO;
2802   TRACE_ALU_RESULT2 (HI, LO);
2803 }
2804
2805 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2806 "mult r<RS>, r<RT>"
2807 *mipsI:
2808 *mipsII:
2809 *mipsIII:
2810 *mipsIV:
2811 *mipsV:
2812 *mips32:
2813 *mips64:
2814 *vr4100:
2815 {
2816   do_mult (SD_, RS, RT, 0);
2817 }
2818
2819
2820 000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
2821 "mult r<RS>, r<RT>":AC == 0
2822 "mult ac<AC>, r<RS>, r<RT>"
2823 *mips32r2:
2824 *mips64r2:
2825 *dsp2:
2826 {
2827   signed64 prod;
2828   if (AC == 0)
2829     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2830   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2831     Unpredictable ();
2832   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2833   prod = ((signed64)(signed32) GPR[RS])
2834           * ((signed64)(signed32) GPR[RT]);
2835   DSPLO(AC) = EXTEND32 (VL4_8 (prod));
2836   DSPHI(AC) = EXTEND32 (VH4_8 (prod));
2837   if (AC == 0)
2838     {
2839       ACX = 0;  /* SmartMIPS */
2840       TRACE_ALU_RESULT2 (HI, LO);
2841     }
2842 }
2843
2844
2845 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2846 "mult r<RS>, r<RT>":RD == 0
2847 "mult r<RD>, r<RS>, r<RT>"
2848 *vr5000:
2849 *r3900:
2850 {
2851   do_mult (SD_, RS, RT, RD);
2852 }
2853
2854
2855 :function:::void:do_multu:int rs, int rt, int rd
2856 {
2857   unsigned64 prod;
2858   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2859   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2860     Unpredictable ();
2861   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2862   prod = (((unsigned64)(unsigned32) GPR[rs])
2863           * ((unsigned64)(unsigned32) GPR[rt]));
2864   LO = EXTEND32 (VL4_8 (prod));
2865   HI = EXTEND32 (VH4_8 (prod));
2866   if (rd != 0)
2867     GPR[rd] = LO;
2868   TRACE_ALU_RESULT2 (HI, LO);
2869 }
2870
2871 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2872 "multu r<RS>, r<RT>"
2873 *mipsI:
2874 *mipsII:
2875 *mipsIII:
2876 *mipsIV:
2877 *mipsV:
2878 *mips32:
2879 *mips64:
2880 *vr4100:
2881 {
2882   do_multu (SD_, RS, RT, 0);
2883 }
2884
2885
2886 000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
2887 "multu r<RS>, r<RT>":AC == 0
2888 "multu r<RS>, r<RT>"
2889 *mips32r2:
2890 *mips64r2:
2891 *dsp2:
2892 {
2893   unsigned64 prod;
2894   if (AC == 0)
2895     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2896   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2897     Unpredictable ();
2898   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2899   prod = ((unsigned64)(unsigned32) GPR[RS])
2900           * ((unsigned64)(unsigned32) GPR[RT]);
2901   DSPLO(AC) = EXTEND32 (VL4_8 (prod));
2902   DSPHI(AC) = EXTEND32 (VH4_8 (prod));
2903   if (AC == 0)
2904     TRACE_ALU_RESULT2 (HI, LO);
2905 }
2906
2907
2908 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2909 "multu r<RS>, r<RT>":RD == 0
2910 "multu r<RD>, r<RS>, r<RT>"
2911 *vr5000:
2912 *r3900:
2913 {
2914   do_multu (SD_, RS, RT, RD);
2915 }
2916
2917
2918 :function:::void:do_nor:int rs, int rt, int rd
2919 {
2920   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2921   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2922   TRACE_ALU_RESULT (GPR[rd]);
2923 }
2924
2925 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2926 "nor r<RD>, r<RS>, r<RT>"
2927 *mipsI:
2928 *mipsII:
2929 *mipsIII:
2930 *mipsIV:
2931 *mipsV:
2932 *mips32:
2933 *mips32r2:
2934 *mips64:
2935 *mips64r2:
2936 *vr4100:
2937 *vr5000:
2938 *r3900:
2939 {
2940   do_nor (SD_, RS, RT, RD);
2941 }
2942
2943
2944 :function:::void:do_or:int rs, int rt, int rd
2945 {
2946   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2947   GPR[rd] = (GPR[rs] | GPR[rt]);
2948   TRACE_ALU_RESULT (GPR[rd]);
2949 }
2950
2951 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2952 "or r<RD>, r<RS>, r<RT>"
2953 *mipsI:
2954 *mipsII:
2955 *mipsIII:
2956 *mipsIV:
2957 *mipsV:
2958 *mips32:
2959 *mips32r2:
2960 *mips64:
2961 *mips64r2:
2962 *vr4100:
2963 *vr5000:
2964 *r3900:
2965 {
2966   do_or (SD_, RS, RT, RD);
2967 }
2968
2969
2970
2971 :function:::void:do_ori:int rs, int rt, unsigned immediate
2972 {
2973   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2974   GPR[rt] = (GPR[rs] | immediate);
2975   TRACE_ALU_RESULT (GPR[rt]);
2976 }
2977
2978 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2979 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2980 *mipsI:
2981 *mipsII:
2982 *mipsIII:
2983 *mipsIV:
2984 *mipsV:
2985 *mips32:
2986 *mips32r2:
2987 *mips64:
2988 *mips64r2:
2989 *vr4100:
2990 *vr5000:
2991 *r3900:
2992 {
2993   do_ori (SD_, RS, RT, IMMEDIATE);
2994 }
2995
2996
2997 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2998 "pref <HINT>, <OFFSET>(r<BASE>)"
2999 *mipsIV:
3000 *mipsV:
3001 *mips32:
3002 *mips32r2:
3003 *mips64:
3004 *mips64r2:
3005 *vr5000:
3006 {
3007   address_word base = GPR[BASE];
3008   address_word offset = EXTEND16 (OFFSET);
3009   {
3010     address_word vaddr = loadstore_ea (SD_, base, offset);
3011     address_word paddr;
3012     int uncached;
3013     {
3014       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3015         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3016     }
3017   }
3018 }
3019
3020
3021 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
3022 {
3023   unsigned64 result;
3024
3025   y &= 31;
3026   TRACE_ALU_INPUT2 (x, y);
3027   result = EXTEND32 (ROTR32 (x, y));
3028   TRACE_ALU_RESULT (result);
3029   return result;
3030 }
3031
3032 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
3033 "ror r<RD>, r<RT>, <SHIFT>"
3034 *mips32r2:
3035 *mips64r2:
3036 *smartmips:
3037 *vr5400:
3038 *vr5500:
3039 {
3040   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
3041 }
3042
3043 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
3044 "rorv r<RD>, r<RT>, r<RS>"
3045 *mips32r2:
3046 *mips64r2:
3047 *smartmips:
3048 *vr5400:
3049 *vr5500:
3050 {
3051   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
3052 }
3053
3054
3055 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3056 {
3057   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3058   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3059   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3060   unsigned int byte;
3061   address_word paddr;
3062   int uncached;
3063   unsigned64 memval;
3064   address_word vaddr;
3065
3066   vaddr = loadstore_ea (SD_, base, offset);
3067   if ((vaddr & access) != 0)
3068     {
3069       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
3070     }
3071   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3072   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3073   byte = ((vaddr & mask) ^ bigendiancpu);
3074   memval = (word << (8 * byte));
3075   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3076 }
3077
3078 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3079 {
3080   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3081   address_word reverseendian = (ReverseEndian ? -1 : 0);
3082   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3083   unsigned int byte;
3084   unsigned int word;
3085   address_word paddr;
3086   int uncached;
3087   unsigned64 memval;
3088   address_word vaddr;
3089   int nr_lhs_bits;
3090   int nr_rhs_bits;
3091
3092   vaddr = loadstore_ea (SD_, base, offset);
3093   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3094   paddr = (paddr ^ (reverseendian & mask));
3095   if (BigEndianMem == 0)
3096     paddr = paddr & ~access;
3097
3098   /* compute where within the word/mem we are */
3099   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3100   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3101   nr_lhs_bits = 8 * byte + 8;
3102   nr_rhs_bits = 8 * access - 8 * byte;
3103   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3104   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3105            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3106            (long) ((unsigned64) paddr >> 32), (long) paddr,
3107            word, byte, nr_lhs_bits, nr_rhs_bits); */
3108
3109   if (word == 0)
3110     {
3111       memval = (rt >> nr_rhs_bits);
3112     }
3113   else
3114     {
3115       memval = (rt << nr_lhs_bits);
3116     }
3117   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3118            (long) ((unsigned64) rt >> 32), (long) rt,
3119            (long) ((unsigned64) memval >> 32), (long) memval); */
3120   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3121 }
3122
3123 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3124 {
3125   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3126   address_word reverseendian = (ReverseEndian ? -1 : 0);
3127   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3128   unsigned int byte;
3129   address_word paddr;
3130   int uncached;
3131   unsigned64 memval;
3132   address_word vaddr;
3133
3134   vaddr = loadstore_ea (SD_, base, offset);
3135   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3136   paddr = (paddr ^ (reverseendian & mask));
3137   if (BigEndianMem != 0)
3138     paddr &= ~access;
3139   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3140   memval = (rt << (byte * 8));
3141   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3142 }
3143
3144
3145 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3146 "sb r<RT>, <OFFSET>(r<BASE>)"
3147 *mipsI:
3148 *mipsII:
3149 *mipsIII:
3150 *mipsIV:
3151 *mipsV:
3152 *mips32:
3153 *mips32r2:
3154 *mips64:
3155 *mips64r2:
3156 *vr4100:
3157 *vr5000:
3158 *r3900:
3159 {
3160   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3161 }
3162
3163
3164 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3165 "sc r<RT>, <OFFSET>(r<BASE>)"
3166 *mipsII:
3167 *mipsIII:
3168 *mipsIV:
3169 *mipsV:
3170 *mips32:
3171 *mips32r2:
3172 *mips64:
3173 *mips64r2:
3174 *vr4100:
3175 *vr5000:
3176 {
3177   unsigned32 instruction = instruction_0;
3178   address_word base = GPR[BASE];
3179   address_word offset = EXTEND16 (OFFSET);
3180   {
3181     address_word vaddr = loadstore_ea (SD_, base, offset);
3182     address_word paddr;
3183     int uncached;
3184     if ((vaddr & 3) != 0)
3185       {
3186         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3187       }
3188     else
3189       {
3190         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3191           {
3192             unsigned64 memval = 0;
3193             unsigned64 memval1 = 0;
3194             unsigned64 mask = 0x7;
3195             unsigned int byte;
3196             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3197             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3198             memval = ((unsigned64) GPR[RT] << (8 * byte));
3199             if (LLBIT)
3200               {
3201                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3202               }
3203             GPR[RT] = LLBIT;
3204           }
3205       }
3206   }
3207 }
3208
3209
3210 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3211 "scd r<RT>, <OFFSET>(r<BASE>)"
3212 *mipsIII:
3213 *mipsIV:
3214 *mipsV:
3215 *mips64:
3216 *mips64r2:
3217 *vr4100:
3218 *vr5000:
3219 {
3220   address_word base = GPR[BASE];
3221   address_word offset = EXTEND16 (OFFSET);
3222   check_u64 (SD_, instruction_0);
3223   {
3224     address_word vaddr = loadstore_ea (SD_, base, offset);
3225     address_word paddr;
3226     int uncached;
3227     if ((vaddr & 7) != 0)
3228       {
3229         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3230       }
3231     else
3232       {
3233         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3234           {
3235             unsigned64 memval = 0;
3236             unsigned64 memval1 = 0;
3237             memval = GPR[RT];
3238             if (LLBIT)
3239               {
3240                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3241               }
3242             GPR[RT] = LLBIT;
3243           }
3244       }
3245   }
3246 }
3247
3248
3249 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3250 "sd r<RT>, <OFFSET>(r<BASE>)"
3251 *mipsIII:
3252 *mipsIV:
3253 *mipsV:
3254 *mips64:
3255 *mips64r2:
3256 *vr4100:
3257 *vr5000:
3258 {
3259   check_u64 (SD_, instruction_0);
3260   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3261 }
3262
3263
3264 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3265 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3266 *mipsII:
3267 *mipsIII:
3268 *mipsIV:
3269 *mipsV:
3270 *mips32:
3271 *mips32r2:
3272 *mips64:
3273 *mips64r2:
3274 *vr4100:
3275 *vr5000:
3276 {
3277   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3278 }
3279
3280
3281 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3282 "sdl r<RT>, <OFFSET>(r<BASE>)"
3283 *mipsIII:
3284 *mipsIV:
3285 *mipsV:
3286 *mips64:
3287 *mips64r2:
3288 *vr4100:
3289 *vr5000:
3290 {
3291   check_u64 (SD_, instruction_0);
3292   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3293 }
3294
3295
3296 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3297 "sdr r<RT>, <OFFSET>(r<BASE>)"
3298 *mipsIII:
3299 *mipsIV:
3300 *mipsV:
3301 *mips64:
3302 *mips64r2:
3303 *vr4100:
3304 *vr5000:
3305 {
3306   check_u64 (SD_, instruction_0);
3307   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3308 }
3309
3310
3311
3312 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3313 "sh r<RT>, <OFFSET>(r<BASE>)"
3314 *mipsI:
3315 *mipsII:
3316 *mipsIII:
3317 *mipsIV:
3318 *mipsV:
3319 *mips32:
3320 *mips32r2:
3321 *mips64:
3322 *mips64r2:
3323 *vr4100:
3324 *vr5000:
3325 *r3900:
3326 {
3327   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3328 }
3329
3330
3331 :function:::void:do_sll:int rt, int rd, int shift
3332 {
3333   unsigned32 temp = (GPR[rt] << shift);
3334   TRACE_ALU_INPUT2 (GPR[rt], shift);
3335   GPR[rd] = EXTEND32 (temp);
3336   TRACE_ALU_RESULT (GPR[rd]);
3337 }
3338
3339 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3340 "nop":RD == 0 && RT == 0 && SHIFT == 0
3341 "sll r<RD>, r<RT>, <SHIFT>"
3342 *mipsI:
3343 *mipsII:
3344 *mipsIII:
3345 *mipsIV:
3346 *mipsV:
3347 *vr4100:
3348 *vr5000:
3349 *r3900:
3350 {
3351   /* Skip shift for NOP, so that there won't be lots of extraneous
3352      trace output.  */
3353   if (RD != 0 || RT != 0 || SHIFT != 0)
3354     do_sll (SD_, RT, RD, SHIFT);
3355 }
3356
3357 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3358 "nop":RD == 0 && RT == 0 && SHIFT == 0
3359 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3360 "sll r<RD>, r<RT>, <SHIFT>"
3361 *mips32:
3362 *mips32r2:
3363 *mips64:
3364 *mips64r2:
3365 {
3366   /* Skip shift for NOP and SSNOP, so that there won't be lots of
3367      extraneous trace output.  */
3368   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3369     do_sll (SD_, RT, RD, SHIFT);
3370 }
3371
3372
3373 :function:::void:do_sllv:int rs, int rt, int rd
3374 {
3375   int s = MASKED (GPR[rs], 4, 0);
3376   unsigned32 temp = (GPR[rt] << s);
3377   TRACE_ALU_INPUT2 (GPR[rt], s);
3378   GPR[rd] = EXTEND32 (temp);
3379   TRACE_ALU_RESULT (GPR[rd]);
3380 }
3381
3382 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3383 "sllv r<RD>, r<RT>, r<RS>"
3384 *mipsI:
3385 *mipsII:
3386 *mipsIII:
3387 *mipsIV:
3388 *mipsV:
3389 *mips32:
3390 *mips32r2:
3391 *mips64:
3392 *mips64r2:
3393 *vr4100:
3394 *vr5000:
3395 *r3900:
3396 {
3397   do_sllv (SD_, RS, RT, RD);
3398 }
3399
3400
3401 :function:::void:do_slt:int rs, int rt, int rd
3402 {
3403   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3404   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3405   TRACE_ALU_RESULT (GPR[rd]);
3406 }
3407
3408 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3409 "slt r<RD>, r<RS>, r<RT>"
3410 *mipsI:
3411 *mipsII:
3412 *mipsIII:
3413 *mipsIV:
3414 *mipsV:
3415 *mips32:
3416 *mips32r2:
3417 *mips64:
3418 *mips64r2:
3419 *vr4100:
3420 *vr5000:
3421 *r3900:
3422 {
3423   do_slt (SD_, RS, RT, RD);
3424 }
3425
3426
3427 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3428 {
3429   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3430   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3431   TRACE_ALU_RESULT (GPR[rt]);
3432 }
3433
3434 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3435 "slti r<RT>, r<RS>, <IMMEDIATE>"
3436 *mipsI:
3437 *mipsII:
3438 *mipsIII:
3439 *mipsIV:
3440 *mipsV:
3441 *mips32:
3442 *mips32r2:
3443 *mips64:
3444 *mips64r2:
3445 *vr4100:
3446 *vr5000:
3447 *r3900:
3448 {
3449   do_slti (SD_, RS, RT, IMMEDIATE);
3450 }
3451
3452
3453 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3454 {
3455   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3456   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3457   TRACE_ALU_RESULT (GPR[rt]);
3458 }
3459
3460 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3461 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3462 *mipsI:
3463 *mipsII:
3464 *mipsIII:
3465 *mipsIV:
3466 *mipsV:
3467 *mips32:
3468 *mips32r2:
3469 *mips64:
3470 *mips64r2:
3471 *vr4100:
3472 *vr5000:
3473 *r3900:
3474 {
3475   do_sltiu (SD_, RS, RT, IMMEDIATE);
3476 }
3477
3478
3479
3480 :function:::void:do_sltu:int rs, int rt, int rd
3481 {
3482   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3483   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3484   TRACE_ALU_RESULT (GPR[rd]);
3485 }
3486
3487 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3488 "sltu r<RD>, r<RS>, r<RT>"
3489 *mipsI:
3490 *mipsII:
3491 *mipsIII:
3492 *mipsIV:
3493 *mipsV:
3494 *mips32:
3495 *mips32r2:
3496 *mips64:
3497 *mips64r2:
3498 *vr4100:
3499 *vr5000:
3500 *r3900:
3501 {
3502   do_sltu (SD_, RS, RT, RD);
3503 }
3504
3505
3506 :function:::void:do_sra:int rt, int rd, int shift
3507 {
3508   signed32 temp = (signed32) GPR[rt] >> shift;
3509   if (NotWordValue (GPR[rt]))
3510     Unpredictable ();
3511   TRACE_ALU_INPUT2 (GPR[rt], shift);
3512   GPR[rd] = EXTEND32 (temp);
3513   TRACE_ALU_RESULT (GPR[rd]);
3514 }
3515
3516 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3517 "sra r<RD>, r<RT>, <SHIFT>"
3518 *mipsI:
3519 *mipsII:
3520 *mipsIII:
3521 *mipsIV:
3522 *mipsV:
3523 *mips32:
3524 *mips32r2:
3525 *mips64:
3526 *mips64r2:
3527 *vr4100:
3528 *vr5000:
3529 *r3900:
3530 {
3531   do_sra (SD_, RT, RD, SHIFT);
3532 }
3533
3534
3535
3536 :function:::void:do_srav:int rs, int rt, int rd
3537 {
3538   int s = MASKED (GPR[rs], 4, 0);
3539   signed32 temp = (signed32) GPR[rt] >> s;
3540   if (NotWordValue (GPR[rt]))
3541     Unpredictable ();
3542   TRACE_ALU_INPUT2 (GPR[rt], s);
3543   GPR[rd] = EXTEND32 (temp);
3544   TRACE_ALU_RESULT (GPR[rd]);
3545 }
3546
3547 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3548 "srav r<RD>, r<RT>, r<RS>"
3549 *mipsI:
3550 *mipsII:
3551 *mipsIII:
3552 *mipsIV:
3553 *mipsV:
3554 *mips32:
3555 *mips32r2:
3556 *mips64:
3557 *mips64r2:
3558 *vr4100:
3559 *vr5000:
3560 *r3900:
3561 {
3562   do_srav (SD_, RS, RT, RD);
3563 }
3564
3565
3566
3567 :function:::void:do_srl:int rt, int rd, int shift
3568 {
3569   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3570   if (NotWordValue (GPR[rt]))
3571     Unpredictable ();
3572   TRACE_ALU_INPUT2 (GPR[rt], shift);
3573   GPR[rd] = EXTEND32 (temp);
3574   TRACE_ALU_RESULT (GPR[rd]);
3575 }
3576
3577 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3578 "srl r<RD>, r<RT>, <SHIFT>"
3579 *mipsI:
3580 *mipsII:
3581 *mipsIII:
3582 *mipsIV:
3583 *mipsV:
3584 *mips32:
3585 *mips32r2:
3586 *mips64:
3587 *mips64r2:
3588 *vr4100:
3589 *vr5000:
3590 *r3900:
3591 {
3592   do_srl (SD_, RT, RD, SHIFT);
3593 }
3594
3595
3596 :function:::void:do_srlv:int rs, int rt, int rd
3597 {
3598   int s = MASKED (GPR[rs], 4, 0);
3599   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3600   if (NotWordValue (GPR[rt]))
3601     Unpredictable ();
3602   TRACE_ALU_INPUT2 (GPR[rt], s);
3603   GPR[rd] = EXTEND32 (temp);
3604   TRACE_ALU_RESULT (GPR[rd]);
3605 }
3606
3607 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3608 "srlv r<RD>, r<RT>, r<RS>"
3609 *mipsI:
3610 *mipsII:
3611 *mipsIII:
3612 *mipsIV:
3613 *mipsV:
3614 *mips32:
3615 *mips32r2:
3616 *mips64:
3617 *mips64r2:
3618 *vr4100:
3619 *vr5000:
3620 *r3900:
3621 {
3622   do_srlv (SD_, RS, RT, RD);
3623 }
3624
3625
3626 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3627 "sub r<RD>, r<RS>, r<RT>"
3628 *mipsI:
3629 *mipsII:
3630 *mipsIII:
3631 *mipsIV:
3632 *mipsV:
3633 *mips32:
3634 *mips32r2:
3635 *mips64:
3636 *mips64r2:
3637 *vr4100:
3638 *vr5000:
3639 *r3900:
3640 {
3641   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3642     Unpredictable ();
3643   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3644   {
3645     ALU32_BEGIN (GPR[RS]);
3646     ALU32_SUB (GPR[RT]);
3647     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3648   }
3649   TRACE_ALU_RESULT (GPR[RD]);
3650 }
3651
3652
3653 :function:::void:do_subu:int rs, int rt, int rd
3654 {
3655   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3656     Unpredictable ();
3657   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3658   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3659   TRACE_ALU_RESULT (GPR[rd]);
3660 }
3661
3662 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3663 "subu r<RD>, r<RS>, r<RT>"
3664 *mipsI:
3665 *mipsII:
3666 *mipsIII:
3667 *mipsIV:
3668 *mipsV:
3669 *mips32:
3670 *mips32r2:
3671 *mips64:
3672 *mips64r2:
3673 *vr4100:
3674 *vr5000:
3675 *r3900:
3676 {
3677   do_subu (SD_, RS, RT, RD);
3678 }
3679
3680
3681 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3682 "sw r<RT>, <OFFSET>(r<BASE>)"
3683 *mipsI:
3684 *mipsII:
3685 *mipsIII:
3686 *mipsIV:
3687 *mipsV:
3688 *mips32:
3689 *mips32r2:
3690 *mips64:
3691 *mips64r2:
3692 *vr4100:
3693 *r3900:
3694 *vr5000:
3695 {
3696   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3697 }
3698
3699
3700 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3701 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3702 *mipsI:
3703 *mipsII:
3704 *mipsIII:
3705 *mipsIV:
3706 *mipsV:
3707 *mips32:
3708 *mips32r2:
3709 *mips64:
3710 *mips64r2:
3711 *vr4100:
3712 *vr5000:
3713 *r3900:
3714 {
3715   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3716 }
3717
3718
3719 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3720 "swl r<RT>, <OFFSET>(r<BASE>)"
3721 *mipsI:
3722 *mipsII:
3723 *mipsIII:
3724 *mipsIV:
3725 *mipsV:
3726 *mips32:
3727 *mips32r2:
3728 *mips64:
3729 *mips64r2:
3730 *vr4100:
3731 *vr5000:
3732 *r3900:
3733 {
3734   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3735 }
3736
3737
3738 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3739 "swr r<RT>, <OFFSET>(r<BASE>)"
3740 *mipsI:
3741 *mipsII:
3742 *mipsIII:
3743 *mipsIV:
3744 *mipsV:
3745 *mips32:
3746 *mips32r2:
3747 *mips64:
3748 *mips64r2:
3749 *vr4100:
3750 *vr5000:
3751 *r3900:
3752 {
3753   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3754 }
3755
3756
3757 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3758 "sync":STYPE == 0
3759 "sync <STYPE>"
3760 *mipsII:
3761 *mipsIII:
3762 *mipsIV:
3763 *mipsV:
3764 *mips32:
3765 *mips32r2:
3766 *mips64:
3767 *mips64r2:
3768 *vr4100:
3769 *vr5000:
3770 *r3900:
3771 {
3772   SyncOperation (STYPE);
3773 }
3774
3775
3776 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3777 "syscall %#lx<CODE>"
3778 *mipsI:
3779 *mipsII:
3780 *mipsIII:
3781 *mipsIV:
3782 *mipsV:
3783 *mips32:
3784 *mips32r2:
3785 *mips64:
3786 *mips64r2:
3787 *vr4100:
3788 *vr5000:
3789 *r3900:
3790 {
3791   SignalException (SystemCall, instruction_0);
3792 }
3793
3794
3795 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3796 "teq r<RS>, r<RT>"
3797 *mipsII:
3798 *mipsIII:
3799 *mipsIV:
3800 *mipsV:
3801 *mips32:
3802 *mips32r2:
3803 *mips64:
3804 *mips64r2:
3805 *vr4100:
3806 *vr5000:
3807 {
3808   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3809     SignalException (Trap, instruction_0);
3810 }
3811
3812
3813 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3814 "teqi r<RS>, <IMMEDIATE>"
3815 *mipsII:
3816 *mipsIII:
3817 *mipsIV:
3818 *mipsV:
3819 *mips32:
3820 *mips32r2:
3821 *mips64:
3822 *mips64r2:
3823 *vr4100:
3824 *vr5000:
3825 {
3826   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3827     SignalException (Trap, instruction_0);
3828 }
3829
3830
3831 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3832 "tge r<RS>, r<RT>"
3833 *mipsII:
3834 *mipsIII:
3835 *mipsIV:
3836 *mipsV:
3837 *mips32:
3838 *mips32r2:
3839 *mips64:
3840 *mips64r2:
3841 *vr4100:
3842 *vr5000:
3843 {
3844   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3845     SignalException (Trap, instruction_0);
3846 }
3847
3848
3849 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3850 "tgei r<RS>, <IMMEDIATE>"
3851 *mipsII:
3852 *mipsIII:
3853 *mipsIV:
3854 *mipsV:
3855 *mips32:
3856 *mips32r2:
3857 *mips64:
3858 *mips64r2:
3859 *vr4100:
3860 *vr5000:
3861 {
3862   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3863     SignalException (Trap, instruction_0);
3864 }
3865
3866
3867 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3868 "tgeiu r<RS>, <IMMEDIATE>"
3869 *mipsII:
3870 *mipsIII:
3871 *mipsIV:
3872 *mipsV:
3873 *mips32:
3874 *mips32r2:
3875 *mips64:
3876 *mips64r2:
3877 *vr4100:
3878 *vr5000:
3879 {
3880   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3881     SignalException (Trap, instruction_0);
3882 }
3883
3884
3885 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3886 "tgeu r<RS>, r<RT>"
3887 *mipsII:
3888 *mipsIII:
3889 *mipsIV:
3890 *mipsV:
3891 *mips32:
3892 *mips32r2:
3893 *mips64:
3894 *mips64r2:
3895 *vr4100:
3896 *vr5000:
3897 {
3898   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3899     SignalException (Trap, instruction_0);
3900 }
3901
3902
3903 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3904 "tlt r<RS>, r<RT>"
3905 *mipsII:
3906 *mipsIII:
3907 *mipsIV:
3908 *mipsV:
3909 *mips32:
3910 *mips32r2:
3911 *mips64:
3912 *mips64r2:
3913 *vr4100:
3914 *vr5000:
3915 {
3916   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3917     SignalException (Trap, instruction_0);
3918 }
3919
3920
3921 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3922 "tlti r<RS>, <IMMEDIATE>"
3923 *mipsII:
3924 *mipsIII:
3925 *mipsIV:
3926 *mipsV:
3927 *mips32:
3928 *mips32r2:
3929 *mips64:
3930 *mips64r2:
3931 *vr4100:
3932 *vr5000:
3933 {
3934   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3935     SignalException (Trap, instruction_0);
3936 }
3937
3938
3939 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3940 "tltiu r<RS>, <IMMEDIATE>"
3941 *mipsII:
3942 *mipsIII:
3943 *mipsIV:
3944 *mipsV:
3945 *mips32:
3946 *mips32r2:
3947 *mips64:
3948 *mips64r2:
3949 *vr4100:
3950 *vr5000:
3951 {
3952   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3953     SignalException (Trap, instruction_0);
3954 }
3955
3956
3957 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3958 "tltu r<RS>, r<RT>"
3959 *mipsII:
3960 *mipsIII:
3961 *mipsIV:
3962 *mipsV:
3963 *mips32:
3964 *mips32r2:
3965 *mips64:
3966 *mips64r2:
3967 *vr4100:
3968 *vr5000:
3969 {
3970   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3971     SignalException (Trap, instruction_0);
3972 }
3973
3974
3975 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3976 "tne r<RS>, r<RT>"
3977 *mipsII:
3978 *mipsIII:
3979 *mipsIV:
3980 *mipsV:
3981 *mips32:
3982 *mips32r2:
3983 *mips64:
3984 *mips64r2:
3985 *vr4100:
3986 *vr5000:
3987 {
3988   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3989     SignalException (Trap, instruction_0);
3990 }
3991
3992
3993 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3994 "tnei r<RS>, <IMMEDIATE>"
3995 *mipsII:
3996 *mipsIII:
3997 *mipsIV:
3998 *mipsV:
3999 *mips32:
4000 *mips32r2:
4001 *mips64:
4002 *mips64r2:
4003 *vr4100:
4004 *vr5000:
4005 {
4006   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
4007     SignalException (Trap, instruction_0);
4008 }
4009
4010
4011 :function:::void:do_xor:int rs, int rt, int rd
4012 {
4013   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4014   GPR[rd] = GPR[rs] ^ GPR[rt];
4015   TRACE_ALU_RESULT (GPR[rd]);
4016 }
4017
4018 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
4019 "xor r<RD>, r<RS>, r<RT>"
4020 *mipsI:
4021 *mipsII:
4022 *mipsIII:
4023 *mipsIV:
4024 *mipsV:
4025 *mips32:
4026 *mips32r2:
4027 *mips64:
4028 *mips64r2:
4029 *vr4100:
4030 *vr5000:
4031 *r3900:
4032 {
4033   do_xor (SD_, RS, RT, RD);
4034 }
4035
4036
4037 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4038 {
4039   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4040   GPR[rt] = GPR[rs] ^ immediate;
4041   TRACE_ALU_RESULT (GPR[rt]);
4042 }
4043
4044 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4045 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
4046 *mipsI:
4047 *mipsII:
4048 *mipsIII:
4049 *mipsIV:
4050 *mipsV:
4051 *mips32:
4052 *mips32r2:
4053 *mips64:
4054 *mips64r2:
4055 *vr4100:
4056 *vr5000:
4057 *r3900:
4058 {
4059   do_xori (SD_, RS, RT, IMMEDIATE);
4060 }
4061
4062 \f
4063 //
4064 // MIPS Architecture:
4065 //
4066 //        FPU Instruction Set (COP1 & COP1X)
4067 //
4068
4069
4070 :%s::::FMT:int fmt
4071 {
4072   switch (fmt)
4073     {
4074     case fmt_single: return "s";
4075     case fmt_double: return "d";
4076     case fmt_word: return "w";
4077     case fmt_long: return "l";
4078     case fmt_ps: return "ps";
4079     default: return "?";
4080     }
4081 }
4082
4083 :%s::::TF:int tf
4084 {
4085   if (tf)
4086     return "t";
4087   else
4088     return "f";
4089 }
4090
4091 :%s::::ND:int nd
4092 {
4093   if (nd)
4094     return "l";
4095   else
4096     return "";
4097 }
4098
4099 :%s::::COND:int cond
4100 {
4101   switch (cond)
4102     {
4103     case 00: return "f";
4104     case 01: return "un";
4105     case 02: return "eq";
4106     case 03: return "ueq";
4107     case 04: return "olt";
4108     case 05: return "ult";
4109     case 06: return "ole";
4110     case 07: return "ule";
4111     case 010: return "sf";
4112     case 011: return "ngle";
4113     case 012: return "seq";
4114     case 013: return "ngl";
4115     case 014: return "lt";
4116     case 015: return "nge";
4117     case 016: return "le";
4118     case 017: return "ngt";
4119     default: return "?";
4120     }
4121 }
4122
4123
4124 // Helpers:
4125 //
4126 // Check that the given FPU format is usable, and signal a
4127 // ReservedInstruction exception if not.
4128 //
4129
4130 // check_fmt_p checks that the format is single, double, or paired single.
4131 :function:::void:check_fmt_p:int fmt, instruction_word insn
4132 *mipsI:
4133 *mipsII:
4134 *mipsIII:
4135 *mipsIV:
4136 *mips32:
4137 *mips32r2:
4138 *vr4100:
4139 *vr5000:
4140 *r3900:
4141 {
4142   /* None of these ISAs support Paired Single, so just fall back to
4143      the single/double check.  */
4144   if ((fmt != fmt_single) && (fmt != fmt_double))
4145     SignalException (ReservedInstruction, insn);
4146 }
4147
4148 :function:::void:check_fmt_p:int fmt, instruction_word insn
4149 *mipsV:
4150 *mips64:
4151 *mips64r2:
4152 {
4153   if ((fmt != fmt_single) && (fmt != fmt_double)
4154       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
4155     SignalException (ReservedInstruction, insn);
4156 }
4157
4158
4159 // Helper:
4160 //
4161 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
4162 // exception if not.
4163 //
4164
4165 :function:::void:check_fpu:
4166 *mipsI:
4167 *mipsII:
4168 *mipsIII:
4169 *mipsIV:
4170 *mipsV:
4171 *mips32:
4172 *mips32r2:
4173 *mips64:
4174 *mips64r2:
4175 *vr4100:
4176 *vr5000:
4177 *r3900:
4178 {
4179   if (! COP_Usable (1))
4180     SignalExceptionCoProcessorUnusable (1);
4181 }
4182
4183
4184 // Helper:
4185 //
4186 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4187 // or MIPS32.  do_load cannot be used instead because it returns an
4188 // unsigned_word, which is limited to the size of the machine's registers.
4189 //
4190
4191 :function:::unsigned64:do_load_double:address_word base, address_word offset
4192 *mipsII:
4193 *mips32:
4194 *mips32r2:
4195 {
4196   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4197   address_word vaddr;
4198   address_word paddr;
4199   int uncached;
4200   unsigned64 memval;
4201   unsigned64 v;
4202
4203   vaddr = loadstore_ea (SD_, base, offset);
4204   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4205     {
4206       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4207                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4208                        sim_core_unaligned_signal);
4209     }
4210   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4211                       isREAL);
4212   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4213               isDATA, isREAL);
4214   v = (unsigned64)memval;
4215   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4216               isDATA, isREAL);
4217   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4218 }
4219
4220
4221 // Helper:
4222 //
4223 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4224 // or MIPS32.  do_load cannot be used instead because it returns an
4225 // unsigned_word, which is limited to the size of the machine's registers.
4226 //
4227
4228 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4229 *mipsII:
4230 *mips32:
4231 *mips32r2:
4232 {
4233   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4234   address_word vaddr;
4235   address_word paddr;
4236   int uncached;
4237   unsigned64 memval;
4238
4239   vaddr = loadstore_ea (SD_, base, offset);
4240   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4241     {
4242       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4243                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4244                        sim_core_unaligned_signal);
4245     }
4246   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4247                       isREAL);
4248   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4249   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4250                isREAL);
4251   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4252   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4253                isREAL);
4254 }
4255
4256
4257 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4258 "abs.%s<FMT> f<FD>, f<FS>"
4259 *mipsI:
4260 *mipsII:
4261 *mipsIII:
4262 *mipsIV:
4263 *mipsV:
4264 *mips32:
4265 *mips32r2:
4266 *mips64:
4267 *mips64r2:
4268 *vr4100:
4269 *vr5000:
4270 *r3900:
4271 {
4272   int fmt = FMT;
4273   check_fpu (SD_);
4274   check_fmt_p (SD_, fmt, instruction_0);
4275   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4276 }
4277
4278
4279
4280 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4281 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4282 *mipsI:
4283 *mipsII:
4284 *mipsIII:
4285 *mipsIV:
4286 *mipsV:
4287 *mips32:
4288 *mips32r2:
4289 *mips64:
4290 *mips64r2:
4291 *vr4100:
4292 *vr5000:
4293 *r3900:
4294 {
4295   int fmt = FMT;
4296   check_fpu (SD_);
4297   check_fmt_p (SD_, fmt, instruction_0);
4298   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4299 }
4300
4301
4302 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4303 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4304 *mipsV:
4305 *mips64:
4306 *mips64r2:
4307 {
4308   unsigned64 fs;
4309   unsigned64 ft;
4310   unsigned64 fd;
4311   check_fpu (SD_);
4312   check_u64 (SD_, instruction_0);
4313   fs = ValueFPR (FS, fmt_ps);
4314   if ((GPR[RS] & 0x3) != 0)
4315     Unpredictable ();
4316   if ((GPR[RS] & 0x4) == 0)
4317     fd = fs;
4318   else
4319     {
4320       ft = ValueFPR (FT, fmt_ps);
4321       if (BigEndianCPU)
4322         fd = PackPS (PSLower (fs), PSUpper (ft));
4323       else
4324         fd = PackPS (PSLower (ft), PSUpper (fs));
4325     }
4326   StoreFPR (FD, fmt_ps, fd);
4327 }
4328
4329
4330 // BC1F
4331 // BC1FL
4332 // BC1T
4333 // BC1TL
4334
4335 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4336 "bc1%s<TF>%s<ND> <OFFSET>"
4337 *mipsI:
4338 *mipsII:
4339 *mipsIII:
4340 {
4341   check_fpu (SD_);
4342   TRACE_BRANCH_INPUT (PREVCOC1());
4343   if (PREVCOC1() == TF)
4344     {
4345       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4346       TRACE_BRANCH_RESULT (dest);
4347       DELAY_SLOT (dest);
4348     }
4349   else if (ND)
4350     {
4351       TRACE_BRANCH_RESULT (0);
4352       NULLIFY_NEXT_INSTRUCTION ();
4353     }
4354   else
4355     {
4356       TRACE_BRANCH_RESULT (NIA);
4357     }
4358 }
4359
4360 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4361 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4362 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4363 *mipsIV:
4364 *mipsV:
4365 *mips32:
4366 *mips32r2:
4367 *mips64:
4368 *mips64r2:
4369 #*vr4100:
4370 *vr5000:
4371 *r3900:
4372 {
4373   check_fpu (SD_);
4374   if (GETFCC(CC) == TF)
4375     {
4376       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4377       DELAY_SLOT (dest);
4378     }
4379   else if (ND)
4380     {
4381       NULLIFY_NEXT_INSTRUCTION ();
4382     }
4383 }
4384
4385
4386 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4387 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4388 *mipsI:
4389 *mipsII:
4390 *mipsIII:
4391 {
4392   int fmt = FMT;
4393   check_fpu (SD_);
4394   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4395   TRACE_ALU_RESULT (ValueFCR (31));
4396 }
4397
4398 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4399 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4400 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4401 *mipsIV:
4402 *mipsV:
4403 *mips32:
4404 *mips32r2:
4405 *mips64:
4406 *mips64r2:
4407 *vr4100:
4408 *vr5000:
4409 *r3900:
4410 {
4411   int fmt = FMT;
4412   check_fpu (SD_);
4413   check_fmt_p (SD_, fmt, instruction_0);
4414   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4415   TRACE_ALU_RESULT (ValueFCR (31));
4416 }
4417
4418
4419 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4420 "ceil.l.%s<FMT> f<FD>, f<FS>"
4421 *mipsIII:
4422 *mipsIV:
4423 *mipsV:
4424 *mips64:
4425 *mips64r2:
4426 *vr4100:
4427 *vr5000:
4428 *r3900:
4429 {
4430   int fmt = FMT;
4431   check_fpu (SD_);
4432   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4433             fmt_long));
4434 }
4435
4436
4437 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4438 "ceil.w.%s<FMT> f<FD>, f<FS>"
4439 *mipsII:
4440 *mipsIII:
4441 *mipsIV:
4442 *mipsV:
4443 *mips32:
4444 *mips32r2:
4445 *mips64:
4446 *mips64r2:
4447 *vr4100:
4448 *vr5000:
4449 *r3900:
4450 {
4451   int fmt = FMT;
4452   check_fpu (SD_);
4453   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4454             fmt_word));
4455 }
4456
4457
4458 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4459 "cfc1 r<RT>, f<FS>"
4460 *mipsI:
4461 *mipsII:
4462 *mipsIII:
4463 {
4464   check_fpu (SD_);
4465   if (FS == 0)
4466     PENDING_FILL (RT, EXTEND32 (FCR0));
4467   else if (FS == 31)
4468     PENDING_FILL (RT, EXTEND32 (FCR31));
4469   /* else NOP */
4470 }
4471
4472 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4473 "cfc1 r<RT>, f<FS>"
4474 *mipsIV:
4475 *vr4100:
4476 *vr5000:
4477 *r3900:
4478 {
4479   check_fpu (SD_);
4480   if (FS == 0 || FS == 31)
4481     {
4482       unsigned_word  fcr = ValueFCR (FS);
4483       TRACE_ALU_INPUT1 (fcr);
4484       GPR[RT] = fcr;
4485     }
4486   /* else NOP */
4487   TRACE_ALU_RESULT (GPR[RT]);
4488 }
4489
4490 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4491 "cfc1 r<RT>, f<FS>"
4492 *mipsV:
4493 *mips32:
4494 *mips32r2:
4495 *mips64:
4496 *mips64r2:
4497 {
4498   check_fpu (SD_);
4499   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4500     {
4501       unsigned_word  fcr = ValueFCR (FS);
4502       TRACE_ALU_INPUT1 (fcr);
4503       GPR[RT] = fcr;
4504     }
4505   /* else NOP */
4506   TRACE_ALU_RESULT (GPR[RT]);
4507 }
4508
4509 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4510 "ctc1 r<RT>, f<FS>"
4511 *mipsI:
4512 *mipsII:
4513 *mipsIII:
4514 {
4515   check_fpu (SD_);
4516   if (FS == 31)
4517     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4518   /* else NOP */
4519 }
4520
4521 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4522 "ctc1 r<RT>, f<FS>"
4523 *mipsIV:
4524 *vr4100:
4525 *vr5000:
4526 *r3900:
4527 {
4528   check_fpu (SD_);
4529   TRACE_ALU_INPUT1 (GPR[RT]);
4530   if (FS == 31)
4531     StoreFCR (FS, GPR[RT]);
4532   /* else NOP */
4533 }
4534
4535 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4536 "ctc1 r<RT>, f<FS>"
4537 *mipsV:
4538 *mips32:
4539 *mips32r2:
4540 *mips64:
4541 *mips64r2:
4542 {
4543   check_fpu (SD_);
4544   TRACE_ALU_INPUT1 (GPR[RT]);
4545   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4546       StoreFCR (FS, GPR[RT]);
4547   /* else NOP */
4548 }
4549
4550
4551 //
4552 // FIXME: Does not correctly differentiate between mips*
4553 //
4554 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4555 "cvt.d.%s<FMT> f<FD>, f<FS>"
4556 *mipsI:
4557 *mipsII:
4558 *mipsIII:
4559 *mipsIV:
4560 *mipsV:
4561 *mips32:
4562 *mips32r2:
4563 *mips64:
4564 *mips64r2:
4565 *vr4100:
4566 *vr5000:
4567 *r3900:
4568 {
4569   int fmt = FMT;
4570   check_fpu (SD_);
4571   if ((fmt == fmt_double) | 0)
4572     SignalException (ReservedInstruction, instruction_0);
4573   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4574             fmt_double));
4575 }
4576
4577
4578 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4579 "cvt.l.%s<FMT> f<FD>, f<FS>"
4580 *mipsIII:
4581 *mipsIV:
4582 *mipsV:
4583 *mips64:
4584 *mips64r2:
4585 *vr4100:
4586 *vr5000:
4587 *r3900:
4588 {
4589   int fmt = FMT;
4590   check_fpu (SD_);
4591   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4592     SignalException (ReservedInstruction, instruction_0);
4593   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4594             fmt_long));
4595 }
4596
4597
4598 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4599 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4600 *mipsV:
4601 *mips64:
4602 *mips64r2:
4603 {
4604   check_fpu (SD_);
4605   check_u64 (SD_, instruction_0);
4606   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4607                                 ValueFPR (FT, fmt_single)));
4608 }
4609
4610
4611 //
4612 // FIXME: Does not correctly differentiate between mips*
4613 //
4614 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4615 "cvt.s.%s<FMT> f<FD>, f<FS>"
4616 *mipsI:
4617 *mipsII:
4618 *mipsIII:
4619 *mipsIV:
4620 *mipsV:
4621 *mips32:
4622 *mips32r2:
4623 *mips64:
4624 *mips64r2:
4625 *vr4100:
4626 *vr5000:
4627 *r3900:
4628 {
4629   int fmt = FMT;
4630   check_fpu (SD_);
4631   if ((fmt == fmt_single) | 0)
4632     SignalException (ReservedInstruction, instruction_0);
4633   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4634             fmt_single));
4635 }
4636
4637
4638 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4639 "cvt.s.pl f<FD>, f<FS>"
4640 *mipsV:
4641 *mips64:
4642 *mips64r2:
4643 {
4644   check_fpu (SD_);
4645   check_u64 (SD_, instruction_0);
4646   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4647 }
4648
4649
4650 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4651 "cvt.s.pu f<FD>, f<FS>"
4652 *mipsV:
4653 *mips64:
4654 *mips64r2:
4655 {
4656   check_fpu (SD_);
4657   check_u64 (SD_, instruction_0);
4658   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4659 }
4660
4661
4662 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4663 "cvt.w.%s<FMT> f<FD>, f<FS>"
4664 *mipsI:
4665 *mipsII:
4666 *mipsIII:
4667 *mipsIV:
4668 *mipsV:
4669 *mips32:
4670 *mips32r2:
4671 *mips64:
4672 *mips64r2:
4673 *vr4100:
4674 *vr5000:
4675 *r3900:
4676 {
4677   int fmt = FMT;
4678   check_fpu (SD_);
4679   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4680     SignalException (ReservedInstruction, instruction_0);
4681   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4682             fmt_word));
4683 }
4684
4685
4686 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4687 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4688 *mipsI:
4689 *mipsII:
4690 *mipsIII:
4691 *mipsIV:
4692 *mipsV:
4693 *mips32:
4694 *mips32r2:
4695 *mips64:
4696 *mips64r2:
4697 *vr4100:
4698 *vr5000:
4699 *r3900:
4700 {
4701   int fmt = FMT;
4702   check_fpu (SD_);
4703   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4704 }
4705
4706
4707 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4708 "dmfc1 r<RT>, f<FS>"
4709 *mipsIII:
4710 {
4711   unsigned64 v;
4712   check_fpu (SD_);
4713   check_u64 (SD_, instruction_0);
4714   if (SizeFGR () == 64)
4715     v = FGR[FS];
4716   else if ((FS & 0x1) == 0)
4717     v = SET64HI (FGR[FS+1]) | FGR[FS];
4718   else
4719     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4720   PENDING_FILL (RT, v);
4721   TRACE_ALU_RESULT (v);
4722 }
4723
4724 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4725 "dmfc1 r<RT>, f<FS>"
4726 *mipsIV:
4727 *mipsV:
4728 *mips64:
4729 *mips64r2:
4730 *vr4100:
4731 *vr5000:
4732 *r3900:
4733 {
4734   check_fpu (SD_);
4735   check_u64 (SD_, instruction_0);
4736   if (SizeFGR () == 64)
4737     GPR[RT] = FGR[FS];
4738   else if ((FS & 0x1) == 0)
4739     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4740   else
4741     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4742   TRACE_ALU_RESULT (GPR[RT]);
4743 }
4744
4745
4746 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4747 "dmtc1 r<RT>, f<FS>"
4748 *mipsIII:
4749 {
4750   unsigned64 v;
4751   check_fpu (SD_);
4752   check_u64 (SD_, instruction_0);
4753   if (SizeFGR () == 64)
4754     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4755   else if ((FS & 0x1) == 0)
4756     {
4757       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4758       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4759     }
4760   else
4761     Unpredictable ();
4762   TRACE_FP_RESULT (GPR[RT]);
4763 }
4764
4765 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4766 "dmtc1 r<RT>, f<FS>"
4767 *mipsIV:
4768 *mipsV:
4769 *mips64:
4770 *mips64r2:
4771 *vr4100:
4772 *vr5000:
4773 *r3900:
4774 {
4775   check_fpu (SD_);
4776   check_u64 (SD_, instruction_0);
4777   if (SizeFGR () == 64)
4778     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4779   else if ((FS & 0x1) == 0)
4780     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4781   else
4782     Unpredictable ();
4783 }
4784
4785
4786 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4787 "floor.l.%s<FMT> f<FD>, f<FS>"
4788 *mipsIII:
4789 *mipsIV:
4790 *mipsV:
4791 *mips64:
4792 *mips64r2:
4793 *vr4100:
4794 *vr5000:
4795 *r3900:
4796 {
4797   int fmt = FMT;
4798   check_fpu (SD_);
4799   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4800             fmt_long));
4801 }
4802
4803
4804 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4805 "floor.w.%s<FMT> f<FD>, f<FS>"
4806 *mipsII:
4807 *mipsIII:
4808 *mipsIV:
4809 *mipsV:
4810 *mips32:
4811 *mips32r2:
4812 *mips64:
4813 *mips64r2:
4814 *vr4100:
4815 *vr5000:
4816 *r3900:
4817 {
4818   int fmt = FMT;
4819   check_fpu (SD_);
4820   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4821             fmt_word));
4822 }
4823
4824
4825 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4826 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4827 *mipsII:
4828 *mips32:
4829 *mips32r2:
4830 {
4831   check_fpu (SD_);
4832   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4833 }
4834
4835
4836 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4837 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4838 *mipsIII:
4839 *mipsIV:
4840 *mipsV:
4841 *mips64:
4842 *mips64r2:
4843 *vr4100:
4844 *vr5000:
4845 *r3900:
4846 {
4847   check_fpu (SD_);
4848   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4849 }
4850
4851
4852 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4853 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4854 *mipsIV:
4855 *mipsV:
4856 *mips64:
4857 *mips64r2:
4858 *vr5000:
4859 {
4860   check_fpu (SD_);
4861   check_u64 (SD_, instruction_0);
4862   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4863 }
4864
4865
4866 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4867 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4868 *mipsV:
4869 *mips64:
4870 *mips64r2:
4871 {
4872   address_word base = GPR[BASE];
4873   address_word index = GPR[INDEX];
4874   address_word vaddr = base + index;
4875   check_fpu (SD_);
4876   check_u64 (SD_, instruction_0);
4877   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4878   if ((vaddr & 0x7) != 0)
4879     index -= (vaddr & 0x7);
4880   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4881 }
4882
4883
4884 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4885 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4886 *mipsI:
4887 *mipsII:
4888 *mipsIII:
4889 *mipsIV:
4890 *mipsV:
4891 *mips32:
4892 *mips32r2:
4893 *mips64:
4894 *mips64r2:
4895 *vr4100:
4896 *vr5000:
4897 *r3900:
4898 {
4899   check_fpu (SD_);
4900   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4901 }
4902
4903
4904 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4905 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4906 *mipsIV:
4907 *mipsV:
4908 *mips64:
4909 *mips64r2:
4910 *vr5000:
4911 {
4912   check_fpu (SD_);
4913   check_u64 (SD_, instruction_0);
4914   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4915 }
4916
4917
4918
4919 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4920 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4921 *mipsIV:
4922 *mipsV:
4923 *mips64:
4924 *mips64r2:
4925 *vr5000:
4926 {
4927   int fmt = FMT;
4928   check_fpu (SD_);
4929   check_u64 (SD_, instruction_0);
4930   check_fmt_p (SD_, fmt, instruction_0);
4931   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4932                                   ValueFPR (FR, fmt), fmt));
4933 }
4934
4935
4936 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4937 "mfc1 r<RT>, f<FS>"
4938 *mipsI:
4939 *mipsII:
4940 *mipsIII:
4941 {
4942   unsigned64 v;
4943   check_fpu (SD_);
4944   v = EXTEND32 (FGR[FS]);
4945   PENDING_FILL (RT, v);
4946   TRACE_ALU_RESULT (v);
4947 }
4948
4949 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4950 "mfc1 r<RT>, f<FS>"
4951 *mipsIV:
4952 *mipsV:
4953 *mips32:
4954 *mips32r2:
4955 *mips64:
4956 *mips64r2:
4957 *vr4100:
4958 *vr5000:
4959 *r3900:
4960 {
4961   check_fpu (SD_);
4962   GPR[RT] = EXTEND32 (FGR[FS]);
4963   TRACE_ALU_RESULT (GPR[RT]);
4964 }
4965
4966
4967 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4968 "mov.%s<FMT> f<FD>, f<FS>"
4969 *mipsI:
4970 *mipsII:
4971 *mipsIII:
4972 *mipsIV:
4973 *mipsV:
4974 *mips32:
4975 *mips32r2:
4976 *mips64:
4977 *mips64r2:
4978 *vr4100:
4979 *vr5000:
4980 *r3900:
4981 {
4982   int fmt = FMT;
4983   check_fpu (SD_);
4984   check_fmt_p (SD_, fmt, instruction_0);
4985   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4986 }
4987
4988
4989 // MOVF
4990 // MOVT
4991 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4992 "mov%s<TF> r<RD>, r<RS>, <CC>"
4993 *mipsIV:
4994 *mipsV:
4995 *mips32:
4996 *mips32r2:
4997 *mips64:
4998 *mips64r2:
4999 *vr5000:
5000 {
5001   check_fpu (SD_);
5002   if (GETFCC(CC) == TF)
5003     GPR[RD] = GPR[RS];
5004 }
5005
5006
5007 // MOVF.fmt
5008 // MOVT.fmt
5009 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
5010 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5011 *mipsIV:
5012 *mipsV:
5013 *mips32:
5014 *mips32r2:
5015 *mips64:
5016 *mips64r2:
5017 *vr5000:
5018 {
5019   int fmt = FMT;
5020   check_fpu (SD_);
5021   if (fmt != fmt_ps)
5022     {
5023       if (GETFCC(CC) == TF)
5024         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
5025       else
5026         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
5027     }
5028   else
5029     {
5030       unsigned64 fd;
5031       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
5032                                       fmt_ps)),
5033                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
5034                                       fmt_ps)));
5035       StoreFPR (FD, fmt_ps, fd);
5036     }
5037 }
5038
5039
5040 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
5041 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
5042 *mipsIV:
5043 *mipsV:
5044 *mips32:
5045 *mips32r2:
5046 *mips64:
5047 *mips64r2:
5048 *vr5000:
5049 {
5050   check_fpu (SD_);
5051   if (GPR[RT] != 0)
5052     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
5053   else
5054     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
5055 }
5056
5057
5058 // MOVT see MOVtf
5059
5060
5061 // MOVT.fmt see MOVtf.fmt
5062
5063
5064
5065 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
5066 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5067 *mipsIV:
5068 *mipsV:
5069 *mips32:
5070 *mips32r2:
5071 *mips64:
5072 *mips64r2:
5073 *vr5000:
5074 {
5075   check_fpu (SD_);
5076   if (GPR[RT] == 0)
5077     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
5078   else
5079     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
5080 }
5081
5082
5083 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
5084 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5085 *mipsIV:
5086 *mipsV:
5087 *mips64:
5088 *mips64r2:
5089 *vr5000:
5090 {
5091   int fmt = FMT;
5092   check_fpu (SD_);
5093   check_u64 (SD_, instruction_0);
5094   check_fmt_p (SD_, fmt, instruction_0);
5095   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5096                                   ValueFPR (FR, fmt), fmt));
5097 }
5098
5099
5100 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
5101 "mtc1 r<RT>, f<FS>"
5102 *mipsI:
5103 *mipsII:
5104 *mipsIII:
5105 {
5106   check_fpu (SD_);
5107   if (SizeFGR () == 64)
5108     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
5109   else
5110     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5111   TRACE_FP_RESULT (GPR[RT]);
5112 }
5113
5114 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
5115 "mtc1 r<RT>, f<FS>"
5116 *mipsIV:
5117 *mipsV:
5118 *mips32:
5119 *mips32r2:
5120 *mips64:
5121 *mips64r2:
5122 *vr4100:
5123 *vr5000:
5124 *r3900:
5125 {
5126   check_fpu (SD_);
5127   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
5128 }
5129
5130
5131 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
5132 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5133 *mipsI:
5134 *mipsII:
5135 *mipsIII:
5136 *mipsIV:
5137 *mipsV:
5138 *mips32:
5139 *mips32r2:
5140 *mips64:
5141 *mips64r2:
5142 *vr4100:
5143 *vr5000:
5144 *r3900:
5145 {
5146   int fmt = FMT;
5147   check_fpu (SD_);
5148   check_fmt_p (SD_, fmt, instruction_0);
5149   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5150 }
5151
5152
5153 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
5154 "neg.%s<FMT> f<FD>, f<FS>"
5155 *mipsI:
5156 *mipsII:
5157 *mipsIII:
5158 *mipsIV:
5159 *mipsV:
5160 *mips32:
5161 *mips32r2:
5162 *mips64:
5163 *mips64r2:
5164 *vr4100:
5165 *vr5000:
5166 *r3900:
5167 {
5168   int fmt = FMT;
5169   check_fpu (SD_);
5170   check_fmt_p (SD_, fmt, instruction_0);
5171   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
5172 }
5173
5174
5175 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
5176 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5177 *mipsIV:
5178 *mipsV:
5179 *mips64:
5180 *mips64r2:
5181 *vr5000:
5182 {
5183   int fmt = FMT;
5184   check_fpu (SD_);
5185   check_u64 (SD_, instruction_0);
5186   check_fmt_p (SD_, fmt, instruction_0);
5187   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5188                                      ValueFPR (FR, fmt), fmt));
5189 }
5190
5191
5192 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5193 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5194 *mipsIV:
5195 *mipsV:
5196 *mips64:
5197 *mips64r2:
5198 *vr5000:
5199 {
5200   int fmt = FMT;
5201   check_fpu (SD_);
5202   check_u64 (SD_, instruction_0);
5203   check_fmt_p (SD_, fmt, instruction_0);
5204   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5205                                      ValueFPR (FR, fmt), fmt));
5206 }
5207
5208
5209 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5210 "pll.ps f<FD>, f<FS>, f<FT>"
5211 *mipsV:
5212 *mips64:
5213 *mips64r2:
5214 {
5215   check_fpu (SD_);
5216   check_u64 (SD_, instruction_0);
5217   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5218                                 PSLower (ValueFPR (FT, fmt_ps))));
5219 }
5220
5221
5222 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5223 "plu.ps f<FD>, f<FS>, f<FT>"
5224 *mipsV:
5225 *mips64:
5226 *mips64r2:
5227 {
5228   check_fpu (SD_);
5229   check_u64 (SD_, instruction_0);
5230   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5231                                 PSUpper (ValueFPR (FT, fmt_ps))));
5232 }
5233
5234
5235 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5236 "prefx <HINT>, r<INDEX>(r<BASE>)"
5237 *mipsIV:
5238 *mipsV:
5239 *mips64:
5240 *mips64r2:
5241 *vr5000:
5242 {
5243   address_word base = GPR[BASE];
5244   address_word index = GPR[INDEX];
5245   {
5246     address_word vaddr = loadstore_ea (SD_, base, index);
5247     address_word paddr;
5248     int uncached;
5249     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5250       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5251   }
5252 }
5253
5254
5255 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5256 "pul.ps f<FD>, f<FS>, f<FT>"
5257 *mipsV:
5258 *mips64:
5259 *mips64r2:
5260 {
5261   check_fpu (SD_);
5262   check_u64 (SD_, instruction_0);
5263   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5264                                 PSLower (ValueFPR (FT, fmt_ps))));
5265 }
5266
5267
5268 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5269 "puu.ps f<FD>, f<FS>, f<FT>"
5270 *mipsV:
5271 *mips64:
5272 *mips64r2:
5273 {
5274   check_fpu (SD_);
5275   check_u64 (SD_, instruction_0);
5276   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5277                                 PSUpper (ValueFPR (FT, fmt_ps))));
5278 }
5279
5280
5281 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5282 "recip.%s<FMT> f<FD>, f<FS>"
5283 *mipsIV:
5284 *mipsV:
5285 *mips64:
5286 *mips64r2:
5287 *vr5000:
5288 {
5289   int fmt = FMT;
5290   check_fpu (SD_);
5291   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5292 }
5293
5294
5295 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5296 "round.l.%s<FMT> f<FD>, f<FS>"
5297 *mipsIII:
5298 *mipsIV:
5299 *mipsV:
5300 *mips64:
5301 *mips64r2:
5302 *vr4100:
5303 *vr5000:
5304 *r3900:
5305 {
5306   int fmt = FMT;
5307   check_fpu (SD_);
5308   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5309             fmt_long));
5310 }
5311
5312
5313 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5314 "round.w.%s<FMT> f<FD>, f<FS>"
5315 *mipsII:
5316 *mipsIII:
5317 *mipsIV:
5318 *mipsV:
5319 *mips32:
5320 *mips32r2:
5321 *mips64:
5322 *mips64r2:
5323 *vr4100:
5324 *vr5000:
5325 *r3900:
5326 {
5327   int fmt = FMT;
5328   check_fpu (SD_);
5329   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5330             fmt_word));
5331 }
5332
5333
5334 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5335 "rsqrt.%s<FMT> f<FD>, f<FS>"
5336 *mipsIV:
5337 *mipsV:
5338 *mips64:
5339 *mips64r2:
5340 *vr5000:
5341 {
5342   int fmt = FMT;
5343   check_fpu (SD_);
5344   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5345 }
5346
5347
5348 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5349 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5350 *mipsII:
5351 *mips32:
5352 *mips32r2:
5353 {
5354   check_fpu (SD_);
5355   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5356 }
5357
5358
5359 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5360 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5361 *mipsIII:
5362 *mipsIV:
5363 *mipsV:
5364 *mips64:
5365 *mips64r2:
5366 *vr4100:
5367 *vr5000:
5368 *r3900:
5369 {
5370   check_fpu (SD_);
5371   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5372 }
5373
5374
5375 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5376 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5377 *mipsIV:
5378 *mipsV:
5379 *mips64:
5380 *mips64r2:
5381 *vr5000:
5382 {
5383   check_fpu (SD_);
5384   check_u64 (SD_, instruction_0);
5385   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5386 }
5387
5388
5389 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5390 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5391 *mipsV:
5392 *mips64:
5393 *mips64r2:
5394 {
5395   unsigned64 v;
5396   address_word base = GPR[BASE];
5397   address_word index = GPR[INDEX];
5398   address_word vaddr = base + index;
5399   check_fpu (SD_);
5400   check_u64 (SD_, instruction_0);
5401   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
5402   if ((vaddr & 0x7) != 0)
5403     index -= (vaddr & 0x7);
5404   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5405 }
5406
5407
5408 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5409 "sqrt.%s<FMT> f<FD>, f<FS>"
5410 *mipsII:
5411 *mipsIII:
5412 *mipsIV:
5413 *mipsV:
5414 *mips32:
5415 *mips32r2:
5416 *mips64:
5417 *mips64r2:
5418 *vr4100:
5419 *vr5000:
5420 *r3900:
5421 {
5422   int fmt = FMT;
5423   check_fpu (SD_);
5424   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
5425 }
5426
5427
5428 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5429 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5430 *mipsI:
5431 *mipsII:
5432 *mipsIII:
5433 *mipsIV:
5434 *mipsV:
5435 *mips32:
5436 *mips32r2:
5437 *mips64:
5438 *mips64r2:
5439 *vr4100:
5440 *vr5000:
5441 *r3900:
5442 {
5443   int fmt = FMT;
5444   check_fpu (SD_);
5445   check_fmt_p (SD_, fmt, instruction_0);
5446   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5447 }
5448
5449
5450
5451 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5452 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5453 *mipsI:
5454 *mipsII:
5455 *mipsIII:
5456 *mipsIV:
5457 *mipsV:
5458 *mips32:
5459 *mips32r2:
5460 *mips64:
5461 *mips64r2:
5462 *vr4100:
5463 *vr5000:
5464 *r3900:
5465 {
5466   address_word base = GPR[BASE];
5467   address_word offset = EXTEND16 (OFFSET);
5468   check_fpu (SD_);
5469   {
5470     address_word vaddr = loadstore_ea (SD_, base, offset);
5471     address_word paddr;
5472     int uncached;
5473     if ((vaddr & 3) != 0)
5474       {
5475         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5476       }
5477     else
5478       {
5479         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5480           {
5481             uword64 memval = 0;
5482             uword64 memval1 = 0;
5483             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5484             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5485             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5486             unsigned int byte;
5487             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5488             byte = ((vaddr & mask) ^ bigendiancpu);
5489             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5490             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5491           }
5492       }
5493   }
5494 }
5495
5496
5497 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5498 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5499 *mipsIV:
5500 *mipsV:
5501 *mips64:
5502 *mips64r2:
5503 *vr5000:
5504 {
5505
5506   address_word base = GPR[BASE];
5507   address_word index = GPR[INDEX];
5508   check_fpu (SD_);
5509   check_u64 (SD_, instruction_0);
5510   {
5511    address_word vaddr = loadstore_ea (SD_, base, index);
5512    address_word paddr;
5513    int uncached;
5514    if ((vaddr & 3) != 0)
5515      {
5516        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5517      }
5518    else
5519    {
5520     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5521     {
5522      unsigned64 memval = 0;
5523      unsigned64 memval1 = 0;
5524      unsigned64 mask = 0x7;
5525      unsigned int byte;
5526      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5527      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5528      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5529       {
5530        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5531       }
5532     }
5533    }
5534   }
5535 }
5536
5537
5538 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5539 "trunc.l.%s<FMT> f<FD>, f<FS>"
5540 *mipsIII:
5541 *mipsIV:
5542 *mipsV:
5543 *mips64:
5544 *mips64r2:
5545 *vr4100:
5546 *vr5000:
5547 *r3900:
5548 {
5549   int fmt = FMT;
5550   check_fpu (SD_);
5551   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5552             fmt_long));
5553 }
5554
5555
5556 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5557 "trunc.w.%s<FMT> f<FD>, f<FS>"
5558 *mipsII:
5559 *mipsIII:
5560 *mipsIV:
5561 *mipsV:
5562 *mips32:
5563 *mips32r2:
5564 *mips64:
5565 *mips64r2:
5566 *vr4100:
5567 *vr5000:
5568 *r3900:
5569 {
5570   int fmt = FMT;
5571   check_fpu (SD_);
5572   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5573             fmt_word));
5574 }
5575
5576 \f
5577 //
5578 // MIPS Architecture:
5579 //
5580 //        System Control Instruction Set (COP0)
5581 //
5582
5583
5584 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5585 "bc0f <OFFSET>"
5586 *mipsI:
5587 *mipsII:
5588 *mipsIII:
5589 *mipsIV:
5590 *mipsV:
5591 *mips32:
5592 *mips32r2:
5593 *mips64:
5594 *mips64r2:
5595 *vr4100:
5596 *vr5000:
5597
5598 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5599 "bc0f <OFFSET>"
5600 // stub needed for eCos as tx39 hardware bug workaround
5601 *r3900:
5602 {
5603   /* do nothing */
5604 }
5605
5606
5607 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5608 "bc0fl <OFFSET>"
5609 *mipsI:
5610 *mipsII:
5611 *mipsIII:
5612 *mipsIV:
5613 *mipsV:
5614 *mips32:
5615 *mips32r2:
5616 *mips64:
5617 *mips64r2:
5618 *vr4100:
5619 *vr5000:
5620
5621
5622 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5623 "bc0t <OFFSET>"
5624 *mipsI:
5625 *mipsII:
5626 *mipsIII:
5627 *mipsIV:
5628 *mipsV:
5629 *mips32:
5630 *mips32r2:
5631 *mips64:
5632 *mips64r2:
5633 *vr4100:
5634
5635
5636 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5637 "bc0tl <OFFSET>"
5638 *mipsI:
5639 *mipsII:
5640 *mipsIII:
5641 *mipsIV:
5642 *mipsV:
5643 *mips32:
5644 *mips32r2:
5645 *mips64:
5646 *mips64r2:
5647 *vr4100:
5648 *vr5000:
5649
5650
5651 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5652 "cache <OP>, <OFFSET>(r<BASE>)"
5653 *mipsIII:
5654 *mipsIV:
5655 *mipsV:
5656 *mips32:
5657 *mips32r2:
5658 *mips64:
5659 *mips64r2:
5660 *vr4100:
5661 *vr5000:
5662 *r3900:
5663 {
5664   address_word base = GPR[BASE];
5665   address_word offset = EXTEND16 (OFFSET);
5666   {
5667     address_word vaddr = loadstore_ea (SD_, base, offset);
5668     address_word paddr;
5669     int uncached;
5670     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5671       CacheOp(OP,vaddr,paddr,instruction_0);
5672   }
5673 }
5674
5675
5676 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5677 "dmfc0 r<RT>, r<RD>"
5678 *mipsIII:
5679 *mipsIV:
5680 *mipsV:
5681 *mips64:
5682 *mips64r2:
5683 {
5684   check_u64 (SD_, instruction_0);
5685   DecodeCoproc (instruction_0);
5686 }
5687
5688
5689 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5690 "dmtc0 r<RT>, r<RD>"
5691 *mipsIII:
5692 *mipsIV:
5693 *mipsV:
5694 *mips64:
5695 *mips64r2:
5696 {
5697   check_u64 (SD_, instruction_0);
5698   DecodeCoproc (instruction_0);
5699 }
5700
5701
5702 010000,1,0000000000000000000,011000:COP0:32::ERET
5703 "eret"
5704 *mipsIII:
5705 *mipsIV:
5706 *mipsV:
5707 *mips32:
5708 *mips32r2:
5709 *mips64:
5710 *mips64r2:
5711 *vr4100:
5712 *vr5000:
5713 {
5714   if (SR & status_ERL)
5715     {
5716       /* Oops, not yet available */
5717       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5718       NIA = EPC;
5719       SR &= ~status_ERL;
5720     }
5721   else
5722     {
5723       NIA = EPC;
5724       SR &= ~status_EXL;
5725     }
5726 }
5727
5728
5729 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5730 "mfc0 r<RT>, r<RD> # <REGX>"
5731 *mipsI:
5732 *mipsII:
5733 *mipsIII:
5734 *mipsIV:
5735 *mipsV:
5736 *mips32:
5737 *mips32r2:
5738 *mips64:
5739 *mips64r2:
5740 *vr4100:
5741 *vr5000:
5742 *r3900:
5743 {
5744   TRACE_ALU_INPUT0 ();
5745   DecodeCoproc (instruction_0);
5746   TRACE_ALU_RESULT (GPR[RT]);
5747 }
5748
5749 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5750 "mtc0 r<RT>, r<RD> # <REGX>"
5751 *mipsI:
5752 *mipsII:
5753 *mipsIII:
5754 *mipsIV:
5755 *mipsV:
5756 *mips32:
5757 *mips32r2:
5758 *mips64:
5759 *mips64r2:
5760 *vr4100:
5761 *vr5000:
5762 *r3900:
5763 {
5764   DecodeCoproc (instruction_0);
5765 }
5766
5767
5768 010000,1,0000000000000000000,010000:COP0:32::RFE
5769 "rfe"
5770 *mipsI:
5771 *mipsII:
5772 *mipsIII:
5773 *mipsIV:
5774 *mipsV:
5775 *vr4100:
5776 *vr5000:
5777 *r3900:
5778 {
5779   DecodeCoproc (instruction_0);
5780 }
5781
5782
5783 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5784 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5785 *mipsI:
5786 *mipsII:
5787 *mipsIII:
5788 *mipsIV:
5789 *mipsV:
5790 *mips32:
5791 *mips32r2:
5792 *mips64:
5793 *mips64r2:
5794 *vr4100:
5795 *r3900:
5796 {
5797   DecodeCoproc (instruction_0);
5798 }
5799
5800
5801
5802 010000,1,0000000000000000000,001000:COP0:32::TLBP
5803 "tlbp"
5804 *mipsI:
5805 *mipsII:
5806 *mipsIII:
5807 *mipsIV:
5808 *mipsV:
5809 *mips32:
5810 *mips32r2:
5811 *mips64:
5812 *mips64r2:
5813 *vr4100:
5814 *vr5000:
5815
5816
5817 010000,1,0000000000000000000,000001:COP0:32::TLBR
5818 "tlbr"
5819 *mipsI:
5820 *mipsII:
5821 *mipsIII:
5822 *mipsIV:
5823 *mipsV:
5824 *mips32:
5825 *mips32r2:
5826 *mips64:
5827 *mips64r2:
5828 *vr4100:
5829 *vr5000:
5830
5831
5832 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5833 "tlbwi"
5834 *mipsI:
5835 *mipsII:
5836 *mipsIII:
5837 *mipsIV:
5838 *mipsV:
5839 *mips32:
5840 *mips32r2:
5841 *mips64:
5842 *mips64r2:
5843 *vr4100:
5844 *vr5000:
5845
5846
5847 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5848 "tlbwr"
5849 *mipsI:
5850 *mipsII:
5851 *mipsIII:
5852 *mipsIV:
5853 *mipsV:
5854 *mips32:
5855 *mips32r2:
5856 *mips64:
5857 *mips64r2:
5858 *vr4100:
5859 *vr5000:
5860
5861
5862 :include:::mips3264r2.igen
5863 :include:::m16.igen
5864 :include:::m16e.igen
5865 :include:::mdmx.igen
5866 :include:::mips3d.igen
5867 :include:::sb1.igen
5868 :include:::tx.igen
5869 :include:::vr.igen
5870 :include:::dsp.igen
5871 :include:::dsp2.igen
5872 :include:::smartmips.igen
5873