sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips64:mipsisa64:
  49
  50 //  Vendor ISAs:
  51 //
  52 //  Standard MIPS ISA instructions used for these models are listed here,
  53 //  as are functions needed by those standard instructions.  Instructions
  54 //  which are model-dependent and which are not in the standard MIPS ISAs
  55 //  (or which pre-date or use different encodings than the standard
  56 //  instructions) are (for the most part) in separate .igen files.
  57 :model:::vr4100:mips4100:               // vr.igen
  58 :model:::vr4120:mips4120:
  59 :model:::vr5000:mips5000:
  60 :model:::vr5400:mips5400:
  61 :model:::vr5500:mips5500:
  62 :model:::r3900:mips3900:                // tx.igen
  63
  64 //  MIPS Application Specific Extensions (ASEs)
  65 //
  66 //  Instructions for the ASEs are in separate .igen files.
  67 //  ASEs add instructions on to a base ISA.
  68 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  69 :model:::mips3d:mips3d:                 // mips3d.igen
  70 :model:::mdmx:mdmx:                     // mdmx.igen
  71
  72 //  Vendor Extensions
  73 //
  74 //  Instructions specific to these extensions are in separate .igen files.
  75 //  Extensions add instructions on to a base ISA.
  76 :model:::sb1:sb1:                       // sb1.igen
  77
  78
  79 // Pseudo instructions known by IGEN
  80 :internal::::illegal:
  81 {
  82   SignalException (ReservedInstruction, 0);
  83 }
  84
  85
  86 // Pseudo instructions known by interp.c
  87 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  88 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  89 "rsvd <OP>"
  90 {
  91   SignalException (ReservedInstruction, instruction_0);
  92 }
  93
  94
  95
  96 // Helper:
  97 //
  98 // Simulate a 32 bit delayslot instruction
  99 //
 100
 101 :function:::address_word:delayslot32:address_word target
 102 {
 103   instruction_word delay_insn;
 104   sim_events_slip (SD, 1);
 105   DSPC = CIA;
 106   CIA = CIA + 4; /* NOTE not mips16 */
 107   STATE |= simDELAYSLOT;
 108   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 109   ENGINE_ISSUE_PREFIX_HOOK();
 110   idecode_issue (CPU_, delay_insn, (CIA));
 111   STATE &= ~simDELAYSLOT;
 112   return target;
 113 }
 114
 115 :function:::address_word:nullify_next_insn32:
 116 {
 117   sim_events_slip (SD, 1);
 118   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 119   return CIA + 8;
 120 }
 121
 122
 123 // Helper:
 124 //
 125 // Calculate an effective address given a base and an offset.
 126 //
 127
 128 :function:::address_word:loadstore_ea:address_word base, address_word offset
 129 *mipsI:
 130 *mipsII:
 131 *mipsIII:
 132 *mipsIV:
 133 *mipsV:
 134 *mips32:
 135 *vr4100:
 136 *vr5000:
 137 *r3900:
 138 {
 139   return base + offset;
 140 }
 141
 142 :function:::address_word:loadstore_ea:address_word base, address_word offset
 143 *mips64:
 144 {
 145 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 146   /* If in user mode and UX is not set, use 32-bit compatibility effective
 147      address computations as defined in the MIPS64 Architecture for
 148      Programmers Volume III, Revision 0.95, section 4.9.  */
 149   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 150       == (ksu_user << status_KSU_shift))
 151     return (address_word)((signed32)base + (signed32)offset);
 152 #endif
 153   return base + offset;
 154 }
 155
 156
 157 // Helper:
 158 //
 159 // Check that a 32-bit register value is properly sign-extended.
 160 // (See NotWordValue in ISA spec.)
 161 //
 162
 163 :function:::int:not_word_value:unsigned_word value
 164 *mipsI:
 165 *mipsII:
 166 *mipsIII:
 167 *mipsIV:
 168 *mipsV:
 169 *vr4100:
 170 *vr5000:
 171 *r3900:
 172 {
 173   /* For historical simulator compatibility (until documentation is
 174      found that makes these operations unpredictable on some of these
 175      architectures), this check never returns true.  */
 176   return 0;
 177 }
 178
 179 :function:::int:not_word_value:unsigned_word value
 180 *mips32:
 181 {
 182   /* On MIPS32, since registers are 32-bits, there's no check to be done.  */
 183   return 0;
 184 }
 185
 186 :function:::int:not_word_value:unsigned_word value
 187 *mips64:
 188 {
 189   return ((value >> 32) != (value & 0x80000000 ? 0xFFFFFFFF : 0));
 190 }
 191
 192
 193 // Helper:
 194 //
 195 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 196 // theoretically portable code which invokes non-portable behaviour from
 197 // running with no indication of the portability issue.
 198 // (See definition of UNPREDICTABLE in ISA spec.)
 199 //
 200
 201 :function:::void:unpredictable:
 202 *mipsI:
 203 *mipsII:
 204 *mipsIII:
 205 *mipsIV:
 206 *mipsV:
 207 *vr4100:
 208 *vr5000:
 209 *r3900:
 210 {
 211 }
 212
 213 :function:::void:unpredictable:
 214 *mips32:
 215 *mips64:
 216 {
 217   unpredictable_action (CPU, CIA);
 218 }
 219
 220
 221 // Helpers:
 222 //
 223 // Check that an access to a HI/LO register meets timing requirements
 224 //
 225 // In all MIPS ISAs,
 226 //
 227 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 228 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 229 //
 230 // The following restrictions exist for MIPS I - MIPS III:
 231 //
 232 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 233 //      in between makes MF UNPREDICTABLE. (2)
 234 //
 235 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 236 //      in between makes MF UNPREDICTABLE. (3)
 237 //
 238 // On the r3900, restriction (2) is not present, and restriction (3) is not
 239 // present for multiplication.
 240 //
 241 // For now this code is paranoid.  Historically the simulator
 242 // enforced restrictions (2) and (3) for more ISAs and CPU types than
 243 // necessary.  Unfortunately, at least some MIPS IV and later parts'
 244 // documentation describes them as having these hazards (e.g. vr5000),
 245 // so they can't be removed for at leats MIPS IV.  MIPS V hasn't been
 246 // checked (since there are no known hardware implementations).
 247 //
 248
 249 // check_mf_cycles:
 250 //
 251 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 252 // to check for restrictions (2) and (3) above.
 253 //
 254 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 255 {
 256   if (history->mf.timestamp + 3 > time)
 257     {
 258       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 259                         itable[MY_INDEX].name,
 260                         new, (long) CIA,
 261                         (long) history->mf.cia);
 262       return 0;
 263     }
 264   return 1;
 265 }
 266
 267
 268 // check_mt_hilo:
 269 //
 270 // Check for restriction (2) above (for ISAs/processors that have it),
 271 // and record timestamps for restriction (1) above.
 272 //
 273 :function:::int:check_mt_hilo:hilo_history *history
 274 *mipsI:
 275 *mipsII:
 276 *mipsIII:
 277 *mipsIV:
 278 *mipsV:
 279 *vr4100:
 280 *vr5000:
 281 {
 282   signed64 time = sim_events_time (SD);
 283   int ok = check_mf_cycles (SD_, history, time, "MT");
 284   history->mt.timestamp = time;
 285   history->mt.cia = CIA;
 286   return ok;
 287 }
 288
 289 :function:::int:check_mt_hilo:hilo_history *history
 290 *mips32:
 291 *mips64:
 292 *r3900:
 293 {
 294   signed64 time = sim_events_time (SD);
 295   history->mt.timestamp = time;
 296   history->mt.cia = CIA;
 297   return 1;
 298 }
 299
 300
 301 // check_mf_hilo:
 302 //
 303 // Check for restriction (1) above, and record timestamps for
 304 // restriction (2) and (3) above.
 305 //
 306 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 307 *mipsI:
 308 *mipsII:
 309 *mipsIII:
 310 *mipsIV:
 311 *mipsV:
 312 *mips32:
 313 *mips64:
 314 *vr4100:
 315 *vr5000:
 316 *r3900:
 317 {
 318   signed64 time = sim_events_time (SD);
 319   int ok = 1;
 320   if (peer != NULL
 321       && peer->mt.timestamp > history->op.timestamp
 322       && history->mt.timestamp < history->op.timestamp
 323       && ! (history->mf.timestamp > history->op.timestamp
 324             && history->mf.timestamp < peer->mt.timestamp)
 325       && ! (peer->mf.timestamp > history->op.timestamp
 326             && peer->mf.timestamp < peer->mt.timestamp))
 327     {
 328       /* The peer has been written to since the last OP yet we have
 329          not */
 330       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 331                         itable[MY_INDEX].name,
 332                         (long) CIA,
 333                         (long) history->op.cia,
 334                         (long) peer->mt.cia);
 335       ok = 0;
 336     }
 337   history->mf.timestamp = time;
 338   history->mf.cia = CIA;
 339   return ok;
 340 }
 341
 342
 343
 344 // check_mult_hilo:
 345 //
 346 // Check for restriction (3) above (for ISAs/processors that have it)
 347 // for MULT ops, and record timestamps for restriction (1) above.
 348 //
 349 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 350 *mipsI:
 351 *mipsII:
 352 *mipsIII:
 353 *mipsIV:
 354 *mipsV:
 355 *vr4100:
 356 *vr5000:
 357 {
 358   signed64 time = sim_events_time (SD);
 359   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 360             && check_mf_cycles (SD_, lo, time, "OP"));
 361   hi->op.timestamp = time;
 362   lo->op.timestamp = time;
 363   hi->op.cia = CIA;
 364   lo->op.cia = CIA;
 365   return ok;
 366 }
 367
 368 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 369 *mips32:
 370 *mips64:
 371 *r3900:
 372 {
 373   /* FIXME: could record the fact that a stall occured if we want */
 374   signed64 time = sim_events_time (SD);
 375   hi->op.timestamp = time;
 376   lo->op.timestamp = time;
 377   hi->op.cia = CIA;
 378   lo->op.cia = CIA;
 379   return 1;
 380 }
 381
 382
 383 // check_div_hilo:
 384 //
 385 // Check for restriction (3) above (for ISAs/processors that have it)
 386 // for DIV ops, and record timestamps for restriction (1) above.
 387 //
 388 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 389 *mipsI:
 390 *mipsII:
 391 *mipsIII:
 392 *mipsIV:
 393 *mipsV:
 394 *vr4100:
 395 *vr5000:
 396 *r3900:
 397 {
 398   signed64 time = sim_events_time (SD);
 399   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 400             && check_mf_cycles (SD_, lo, time, "OP"));
 401   hi->op.timestamp = time;
 402   lo->op.timestamp = time;
 403   hi->op.cia = CIA;
 404   lo->op.cia = CIA;
 405   return ok;
 406 }
 407
 408 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 409 *mips32:
 410 *mips64:
 411 {
 412   signed64 time = sim_events_time (SD);
 413   hi->op.timestamp = time;
 414   lo->op.timestamp = time;
 415   hi->op.cia = CIA;
 416   lo->op.cia = CIA;
 417   return 1;
 418 }
 419
 420
 421 // Helper:
 422 //
 423 // Check that the 64-bit instruction can currently be used, and signal
 424 // a ReservedInstruction exception if not.
 425 //
 426
 427 :function:::void:check_u64:instruction_word insn
 428 *mipsIII:
 429 *mipsIV:
 430 *mipsV:
 431 *vr4100:
 432 *vr5000:
 433 {
 434   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 435 }
 436
 437 :function:::void:check_u64:instruction_word insn
 438 *mips64:
 439 {
 440 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 441   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 442     SignalException (ReservedInstruction, insn);
 443 #endif
 444 }
 445
 446
 447
 448 //
 449 // MIPS Architecture:
 450 //
 451 //        CPU Instruction Set (mipsI - mipsV, mips32, mips64)
 452 //
 453
 454
 455
 456 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 457 "add r<RD>, r<RS>, r<RT>"
 458 *mipsI:
 459 *mipsII:
 460 *mipsIII:
 461 *mipsIV:
 462 *mipsV:
 463 *mips32:
 464 *mips64:
 465 *vr4100:
 466 *vr5000:
 467 *r3900:
 468 {
 469   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 470     Unpredictable ();
 471   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 472   {
 473     ALU32_BEGIN (GPR[RS]);
 474     ALU32_ADD (GPR[RT]);
 475     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 476   }
 477   TRACE_ALU_RESULT (GPR[RD]);
 478 }
 479
 480
 481
 482 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 483 "addi r<RT>, r<RS>, <IMMEDIATE>"
 484 *mipsI:
 485 *mipsII:
 486 *mipsIII:
 487 *mipsIV:
 488 *mipsV:
 489 *mips32:
 490 *mips64:
 491 *vr4100:
 492 *vr5000:
 493 *r3900:
 494 {
 495   if (NotWordValue (GPR[RS]))
 496     Unpredictable ();
 497   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 498   {
 499     ALU32_BEGIN (GPR[RS]);
 500     ALU32_ADD (EXTEND16 (IMMEDIATE));
 501     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 502   }
 503   TRACE_ALU_RESULT (GPR[RT]);
 504 }
 505
 506
 507
 508 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 509 {
 510   if (NotWordValue (GPR[rs]))
 511     Unpredictable ();
 512   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 513   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 514   TRACE_ALU_RESULT (GPR[rt]);
 515 }
 516
 517 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 518 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 519 *mipsI:
 520 *mipsII:
 521 *mipsIII:
 522 *mipsIV:
 523 *mipsV:
 524 *mips32:
 525 *mips64:
 526 *vr4100:
 527 *vr5000:
 528 *r3900:
 529 {
 530   do_addiu (SD_, RS, RT, IMMEDIATE);
 531 }
 532
 533
 534
 535 :function:::void:do_addu:int rs, int rt, int rd
 536 {
 537   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 538     Unpredictable ();
 539   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 540   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 541   TRACE_ALU_RESULT (GPR[rd]);
 542 }
 543
 544 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 545 "addu r<RD>, r<RS>, r<RT>"
 546 *mipsI:
 547 *mipsII:
 548 *mipsIII:
 549 *mipsIV:
 550 *mipsV:
 551 *mips32:
 552 *mips64:
 553 *vr4100:
 554 *vr5000:
 555 *r3900:
 556 {
 557   do_addu (SD_, RS, RT, RD);
 558 }
 559
 560
 561
 562 :function:::void:do_and:int rs, int rt, int rd
 563 {
 564   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 565   GPR[rd] = GPR[rs] & GPR[rt];
 566   TRACE_ALU_RESULT (GPR[rd]);
 567 }
 568
 569 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 570 "and r<RD>, r<RS>, r<RT>"
 571 *mipsI:
 572 *mipsII:
 573 *mipsIII:
 574 *mipsIV:
 575 *mipsV:
 576 *mips32:
 577 *mips64:
 578 *vr4100:
 579 *vr5000:
 580 *r3900:
 581 {
 582   do_and (SD_, RS, RT, RD);
 583 }
 584
 585
 586
 587 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 588 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 589 *mipsI:
 590 *mipsII:
 591 *mipsIII:
 592 *mipsIV:
 593 *mipsV:
 594 *mips32:
 595 *mips64:
 596 *vr4100:
 597 *vr5000:
 598 *r3900:
 599 {
 600   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 601   GPR[RT] = GPR[RS] & IMMEDIATE;
 602   TRACE_ALU_RESULT (GPR[RT]);
 603 }
 604
 605
 606
 607 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 608 "beq r<RS>, r<RT>, <OFFSET>"
 609 *mipsI:
 610 *mipsII:
 611 *mipsIII:
 612 *mipsIV:
 613 *mipsV:
 614 *mips32:
 615 *mips64:
 616 *vr4100:
 617 *vr5000:
 618 *r3900:
 619 {
 620   address_word offset = EXTEND16 (OFFSET) << 2;
 621   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 622     {
 623       DELAY_SLOT (NIA + offset);
 624     }
 625 }
 626
 627
 628
 629 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 630 "beql r<RS>, r<RT>, <OFFSET>"
 631 *mipsII:
 632 *mipsIII:
 633 *mipsIV:
 634 *mipsV:
 635 *mips32:
 636 *mips64:
 637 *vr4100:
 638 *vr5000:
 639 *r3900:
 640 {
 641   address_word offset = EXTEND16 (OFFSET) << 2;
 642   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 643     {
 644       DELAY_SLOT (NIA + offset);
 645     }
 646   else
 647     NULLIFY_NEXT_INSTRUCTION ();
 648 }
 649
 650
 651
 652 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 653 "bgez r<RS>, <OFFSET>"
 654 *mipsI:
 655 *mipsII:
 656 *mipsIII:
 657 *mipsIV:
 658 *mipsV:
 659 *mips32:
 660 *mips64:
 661 *vr4100:
 662 *vr5000:
 663 *r3900:
 664 {
 665   address_word offset = EXTEND16 (OFFSET) << 2;
 666   if ((signed_word) GPR[RS] >= 0)
 667     {
 668       DELAY_SLOT (NIA + offset);
 669     }
 670 }
 671
 672
 673
 674 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 675 "bgezal r<RS>, <OFFSET>"
 676 *mipsI:
 677 *mipsII:
 678 *mipsIII:
 679 *mipsIV:
 680 *mipsV:
 681 *mips32:
 682 *mips64:
 683 *vr4100:
 684 *vr5000:
 685 *r3900:
 686 {
 687   address_word offset = EXTEND16 (OFFSET) << 2;
 688   if (RS == 31)
 689     Unpredictable ();
 690   RA = (CIA + 8);
 691   if ((signed_word) GPR[RS] >= 0)
 692     {
 693       DELAY_SLOT (NIA + offset);
 694     }
 695 }
 696
 697
 698
 699 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 700 "bgezall r<RS>, <OFFSET>"
 701 *mipsII:
 702 *mipsIII:
 703 *mipsIV:
 704 *mipsV:
 705 *mips32:
 706 *mips64:
 707 *vr4100:
 708 *vr5000:
 709 *r3900:
 710 {
 711   address_word offset = EXTEND16 (OFFSET) << 2;
 712   if (RS == 31)
 713     Unpredictable ();
 714   RA = (CIA + 8);
 715   /* NOTE: The branch occurs AFTER the next instruction has been
 716      executed */
 717   if ((signed_word) GPR[RS] >= 0)
 718     {
 719       DELAY_SLOT (NIA + offset);
 720     }
 721   else
 722     NULLIFY_NEXT_INSTRUCTION ();
 723 }
 724
 725
 726
 727 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 728 "bgezl r<RS>, <OFFSET>"
 729 *mipsII:
 730 *mipsIII:
 731 *mipsIV:
 732 *mipsV:
 733 *mips32:
 734 *mips64:
 735 *vr4100:
 736 *vr5000:
 737 *r3900:
 738 {
 739   address_word offset = EXTEND16 (OFFSET) << 2;
 740   if ((signed_word) GPR[RS] >= 0)
 741     {
 742       DELAY_SLOT (NIA + offset);
 743     }
 744   else
 745     NULLIFY_NEXT_INSTRUCTION ();
 746 }
 747
 748
 749
 750 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 751 "bgtz r<RS>, <OFFSET>"
 752 *mipsI:
 753 *mipsII:
 754 *mipsIII:
 755 *mipsIV:
 756 *mipsV:
 757 *mips32:
 758 *mips64:
 759 *vr4100:
 760 *vr5000:
 761 *r3900:
 762 {
 763   address_word offset = EXTEND16 (OFFSET) << 2;
 764   if ((signed_word) GPR[RS] > 0)
 765     {
 766       DELAY_SLOT (NIA + offset);
 767     }
 768 }
 769
 770
 771
 772 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 773 "bgtzl r<RS>, <OFFSET>"
 774 *mipsII:
 775 *mipsIII:
 776 *mipsIV:
 777 *mipsV:
 778 *mips32:
 779 *mips64:
 780 *vr4100:
 781 *vr5000:
 782 *r3900:
 783 {
 784   address_word offset = EXTEND16 (OFFSET) << 2;
 785   /* NOTE: The branch occurs AFTER the next instruction has been
 786      executed */
 787   if ((signed_word) GPR[RS] > 0)
 788     {
 789       DELAY_SLOT (NIA + offset);
 790     }
 791   else
 792     NULLIFY_NEXT_INSTRUCTION ();
 793 }
 794
 795
 796
 797 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 798 "blez r<RS>, <OFFSET>"
 799 *mipsI:
 800 *mipsII:
 801 *mipsIII:
 802 *mipsIV:
 803 *mipsV:
 804 *mips32:
 805 *mips64:
 806 *vr4100:
 807 *vr5000:
 808 *r3900:
 809 {
 810   address_word offset = EXTEND16 (OFFSET) << 2;
 811   /* NOTE: The branch occurs AFTER the next instruction has been
 812      executed */
 813   if ((signed_word) GPR[RS] <= 0)
 814     {
 815       DELAY_SLOT (NIA + offset);
 816     }
 817 }
 818
 819
 820
 821 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 822 "bgezl r<RS>, <OFFSET>"
 823 *mipsII:
 824 *mipsIII:
 825 *mipsIV:
 826 *mipsV:
 827 *mips32:
 828 *mips64:
 829 *vr4100:
 830 *vr5000:
 831 *r3900:
 832 {
 833   address_word offset = EXTEND16 (OFFSET) << 2;
 834   if ((signed_word) GPR[RS] <= 0)
 835     {
 836       DELAY_SLOT (NIA + offset);
 837     }
 838   else
 839     NULLIFY_NEXT_INSTRUCTION ();
 840 }
 841
 842
 843
 844 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 845 "bltz r<RS>, <OFFSET>"
 846 *mipsI:
 847 *mipsII:
 848 *mipsIII:
 849 *mipsIV:
 850 *mipsV:
 851 *mips32:
 852 *mips64:
 853 *vr4100:
 854 *vr5000:
 855 *r3900:
 856 {
 857   address_word offset = EXTEND16 (OFFSET) << 2;
 858   if ((signed_word) GPR[RS] < 0)
 859     {
 860       DELAY_SLOT (NIA + offset);
 861     }
 862 }
 863
 864
 865
 866 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 867 "bltzal r<RS>, <OFFSET>"
 868 *mipsI:
 869 *mipsII:
 870 *mipsIII:
 871 *mipsIV:
 872 *mipsV:
 873 *mips32:
 874 *mips64:
 875 *vr4100:
 876 *vr5000:
 877 *r3900:
 878 {
 879   address_word offset = EXTEND16 (OFFSET) << 2;
 880   if (RS == 31)
 881     Unpredictable ();
 882   RA = (CIA + 8);
 883   /* NOTE: The branch occurs AFTER the next instruction has been
 884      executed */
 885   if ((signed_word) GPR[RS] < 0)
 886     {
 887       DELAY_SLOT (NIA + offset);
 888     }
 889 }
 890
 891
 892
 893 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 894 "bltzall r<RS>, <OFFSET>"
 895 *mipsII:
 896 *mipsIII:
 897 *mipsIV:
 898 *mipsV:
 899 *mips32:
 900 *mips64:
 901 *vr4100:
 902 *vr5000:
 903 *r3900:
 904 {
 905   address_word offset = EXTEND16 (OFFSET) << 2;
 906   if (RS == 31)
 907     Unpredictable ();
 908   RA = (CIA + 8);
 909   if ((signed_word) GPR[RS] < 0)
 910     {
 911       DELAY_SLOT (NIA + offset);
 912     }
 913   else
 914     NULLIFY_NEXT_INSTRUCTION ();
 915 }
 916
 917
 918
 919 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
 920 "bltzl r<RS>, <OFFSET>"
 921 *mipsII:
 922 *mipsIII:
 923 *mipsIV:
 924 *mipsV:
 925 *mips32:
 926 *mips64:
 927 *vr4100:
 928 *vr5000:
 929 *r3900:
 930 {
 931   address_word offset = EXTEND16 (OFFSET) << 2;
 932   /* NOTE: The branch occurs AFTER the next instruction has been
 933      executed */
 934   if ((signed_word) GPR[RS] < 0)
 935     {
 936       DELAY_SLOT (NIA + offset);
 937     }
 938   else
 939     NULLIFY_NEXT_INSTRUCTION ();
 940 }
 941
 942
 943
 944 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
 945 "bne r<RS>, r<RT>, <OFFSET>"
 946 *mipsI:
 947 *mipsII:
 948 *mipsIII:
 949 *mipsIV:
 950 *mipsV:
 951 *mips32:
 952 *mips64:
 953 *vr4100:
 954 *vr5000:
 955 *r3900:
 956 {
 957   address_word offset = EXTEND16 (OFFSET) << 2;
 958   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 959     {
 960       DELAY_SLOT (NIA + offset);
 961     }
 962 }
 963
 964
 965
 966 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
 967 "bnel r<RS>, r<RT>, <OFFSET>"
 968 *mipsII:
 969 *mipsIII:
 970 *mipsIV:
 971 *mipsV:
 972 *mips32:
 973 *mips64:
 974 *vr4100:
 975 *vr5000:
 976 *r3900:
 977 {
 978   address_word offset = EXTEND16 (OFFSET) << 2;
 979   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
 980     {
 981       DELAY_SLOT (NIA + offset);
 982     }
 983   else
 984     NULLIFY_NEXT_INSTRUCTION ();
 985 }
 986
 987
 988
 989 000000,20.CODE,001101:SPECIAL:32::BREAK
 990 "break %#lx<CODE>"
 991 *mipsI:
 992 *mipsII:
 993 *mipsIII:
 994 *mipsIV:
 995 *mipsV:
 996 *mips32:
 997 *mips64:
 998 *vr4100:
 999 *vr5000:
1000 *r3900:
1001 {
1002   /* Check for some break instruction which are reserved for use by the simulator.  */
1003   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1004   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1005       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1006     {
1007       sim_engine_halt (SD, CPU, NULL, cia,
1008                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1009     }
1010   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1011            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1012     {
1013       if (STATE & simDELAYSLOT)
1014         PC = cia - 4; /* reference the branch instruction */
1015       else
1016         PC = cia;
1017       SignalException (BreakPoint, instruction_0);
1018     }
1019
1020   else
1021     {
1022       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1023          the exception. */
1024       SignalException (BreakPoint, instruction_0);
1025     }
1026 }
1027
1028
1029
1030 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1031 "clo r<RD>, r<RS>"
1032 *mips32:
1033 *mips64:
1034 *vr5500:
1035 {
1036   unsigned32 temp = GPR[RS];
1037   unsigned32 i, mask;
1038   if (RT != RD)
1039     Unpredictable ();
1040   if (NotWordValue (GPR[RS]))
1041     Unpredictable ();
1042   TRACE_ALU_INPUT1 (GPR[RS]);
1043   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1044     {
1045       if ((temp & mask) == 0)
1046         break;
1047       mask >>= 1;
1048     }
1049   GPR[RD] = EXTEND32 (i);
1050   TRACE_ALU_RESULT (GPR[RD]);
1051 }
1052
1053
1054
1055 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1056 "clz r<RD>, r<RS>"
1057 *mips32:
1058 *mips64:
1059 *vr5500:
1060 {
1061   unsigned32 temp = GPR[RS];
1062   unsigned32 i, mask;
1063   if (RT != RD)
1064     Unpredictable ();
1065   if (NotWordValue (GPR[RS]))
1066     Unpredictable ();
1067   TRACE_ALU_INPUT1 (GPR[RS]);
1068   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1069     {
1070       if ((temp & mask) != 0)
1071         break;
1072       mask >>= 1;
1073     }
1074   GPR[RD] = EXTEND32 (i);
1075   TRACE_ALU_RESULT (GPR[RD]);
1076 }
1077
1078
1079
1080 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1081 "dadd r<RD>, r<RS>, r<RT>"
1082 *mipsIII:
1083 *mipsIV:
1084 *mipsV:
1085 *mips64:
1086 *vr4100:
1087 *vr5000:
1088 {
1089   check_u64 (SD_, instruction_0);
1090   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1091   {
1092     ALU64_BEGIN (GPR[RS]);
1093     ALU64_ADD (GPR[RT]);
1094     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1095   }
1096   TRACE_ALU_RESULT (GPR[RD]);
1097 }
1098
1099
1100
1101 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1102 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1103 *mipsIII:
1104 *mipsIV:
1105 *mipsV:
1106 *mips64:
1107 *vr4100:
1108 *vr5000:
1109 {
1110   check_u64 (SD_, instruction_0);
1111   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1112   {
1113     ALU64_BEGIN (GPR[RS]);
1114     ALU64_ADD (EXTEND16 (IMMEDIATE));
1115     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1116   }
1117   TRACE_ALU_RESULT (GPR[RT]);
1118 }
1119
1120
1121
1122 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1123 {
1124   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1125   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1126   TRACE_ALU_RESULT (GPR[rt]);
1127 }
1128
1129 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1130 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1131 *mipsIII:
1132 *mipsIV:
1133 *mipsV:
1134 *mips64:
1135 *vr4100:
1136 *vr5000:
1137 {
1138   check_u64 (SD_, instruction_0);
1139   do_daddiu (SD_, RS, RT, IMMEDIATE);
1140 }
1141
1142
1143
1144 :function:::void:do_daddu:int rs, int rt, int rd
1145 {
1146   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1147   GPR[rd] = GPR[rs] + GPR[rt];
1148   TRACE_ALU_RESULT (GPR[rd]);
1149 }
1150
1151 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1152 "daddu r<RD>, r<RS>, r<RT>"
1153 *mipsIII:
1154 *mipsIV:
1155 *mipsV:
1156 *mips64:
1157 *vr4100:
1158 *vr5000:
1159 {
1160   check_u64 (SD_, instruction_0);
1161   do_daddu (SD_, RS, RT, RD);
1162 }
1163
1164
1165
1166 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1167 "dclo r<RD>, r<RS>"
1168 *mips64:
1169 *vr5500:
1170 {
1171   unsigned64 temp = GPR[RS];
1172   unsigned32 i;
1173   unsigned64 mask;
1174   check_u64 (SD_, instruction_0);
1175   if (RT != RD)
1176     Unpredictable ();
1177   TRACE_ALU_INPUT1 (GPR[RS]);
1178   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1179     {
1180       if ((temp & mask) == 0)
1181         break;
1182       mask >>= 1;
1183     }
1184   GPR[RD] = EXTEND32 (i);
1185   TRACE_ALU_RESULT (GPR[RD]);
1186 }
1187
1188
1189
1190 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1191 "dclz r<RD>, r<RS>"
1192 *mips64:
1193 *vr5500:
1194 {
1195   unsigned64 temp = GPR[RS];
1196   unsigned32 i;
1197   unsigned64 mask;
1198   check_u64 (SD_, instruction_0);
1199   if (RT != RD)
1200     Unpredictable ();
1201   TRACE_ALU_INPUT1 (GPR[RS]);
1202   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1203     {
1204       if ((temp & mask) != 0)
1205         break;
1206       mask >>= 1;
1207     }
1208   GPR[RD] = EXTEND32 (i);
1209   TRACE_ALU_RESULT (GPR[RD]);
1210 }
1211
1212
1213
1214 :function:::void:do_ddiv:int rs, int rt
1215 {
1216   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1217   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1218   {
1219     signed64 n = GPR[rs];
1220     signed64 d = GPR[rt];
1221     signed64 hi;
1222     signed64 lo;
1223     if (d == 0)
1224       {
1225         lo = SIGNED64 (0x8000000000000000);
1226         hi = 0;
1227       }
1228     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1229       {
1230         lo = SIGNED64 (0x8000000000000000);
1231         hi = 0;
1232       }
1233     else
1234       {
1235         lo = (n / d);
1236         hi = (n % d);
1237       }
1238     HI = hi;
1239     LO = lo;
1240   }
1241   TRACE_ALU_RESULT2 (HI, LO);
1242 }
1243
1244 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1245 "ddiv r<RS>, r<RT>"
1246 *mipsIII:
1247 *mipsIV:
1248 *mipsV:
1249 *mips64:
1250 *vr4100:
1251 *vr5000:
1252 {
1253   check_u64 (SD_, instruction_0);
1254   do_ddiv (SD_, RS, RT);
1255 }
1256
1257
1258
1259 :function:::void:do_ddivu:int rs, int rt
1260 {
1261   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1262   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1263   {
1264     unsigned64 n = GPR[rs];
1265     unsigned64 d = GPR[rt];
1266     unsigned64 hi;
1267     unsigned64 lo;
1268     if (d == 0)
1269       {
1270         lo = SIGNED64 (0x8000000000000000);
1271         hi = 0;
1272       }
1273     else
1274       {
1275         lo = (n / d);
1276         hi = (n % d);
1277       }
1278     HI = hi;
1279     LO = lo;
1280   }
1281   TRACE_ALU_RESULT2 (HI, LO);
1282 }
1283
1284 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1285 "ddivu r<RS>, r<RT>"
1286 *mipsIII:
1287 *mipsIV:
1288 *mipsV:
1289 *mips64:
1290 *vr4100:
1291 *vr5000:
1292 {
1293   check_u64 (SD_, instruction_0);
1294   do_ddivu (SD_, RS, RT);
1295 }
1296
1297
1298
1299 :function:::void:do_div:int rs, int rt
1300 {
1301   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1302   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1303   {
1304     signed32 n = GPR[rs];
1305     signed32 d = GPR[rt];
1306     if (d == 0)
1307       {
1308         LO = EXTEND32 (0x80000000);
1309         HI = EXTEND32 (0);
1310       }
1311     else if (n == SIGNED32 (0x80000000) && d == -1)
1312       {
1313         LO = EXTEND32 (0x80000000);
1314         HI = EXTEND32 (0);
1315       }
1316     else
1317       {
1318         LO = EXTEND32 (n / d);
1319         HI = EXTEND32 (n % d);
1320       }
1321   }
1322   TRACE_ALU_RESULT2 (HI, LO);
1323 }
1324
1325 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1326 "div r<RS>, r<RT>"
1327 *mipsI:
1328 *mipsII:
1329 *mipsIII:
1330 *mipsIV:
1331 *mipsV:
1332 *mips32:
1333 *mips64:
1334 *vr4100:
1335 *vr5000:
1336 *r3900:
1337 {
1338   do_div (SD_, RS, RT);
1339 }
1340
1341
1342
1343 :function:::void:do_divu:int rs, int rt
1344 {
1345   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1346   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1347   {
1348     unsigned32 n = GPR[rs];
1349     unsigned32 d = GPR[rt];
1350     if (d == 0)
1351       {
1352         LO = EXTEND32 (0x80000000);
1353         HI = EXTEND32 (0);
1354       }
1355     else
1356       {
1357         LO = EXTEND32 (n / d);
1358         HI = EXTEND32 (n % d);
1359       }
1360   }
1361   TRACE_ALU_RESULT2 (HI, LO);
1362 }
1363
1364 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1365 "divu r<RS>, r<RT>"
1366 *mipsI:
1367 *mipsII:
1368 *mipsIII:
1369 *mipsIV:
1370 *mipsV:
1371 *mips32:
1372 *mips64:
1373 *vr4100:
1374 *vr5000:
1375 *r3900:
1376 {
1377   do_divu (SD_, RS, RT);
1378 }
1379
1380
1381
1382 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1383 {
1384   unsigned64 lo;
1385   unsigned64 hi;
1386   unsigned64 m00;
1387   unsigned64 m01;
1388   unsigned64 m10;
1389   unsigned64 m11;
1390   unsigned64 mid;
1391   int sign;
1392   unsigned64 op1 = GPR[rs];
1393   unsigned64 op2 = GPR[rt];
1394   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1395   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1396   /* make signed multiply unsigned */
1397   sign = 0;
1398   if (signed_p)
1399     {
1400       if ((signed64) op1 < 0)
1401         {
1402           op1 = - op1;
1403           ++sign;
1404         }
1405       if ((signed64) op2 < 0)
1406         {
1407           op2 = - op2;
1408           ++sign;
1409         }
1410     }
1411   /* multiply out the 4 sub products */
1412   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1413   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1414   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1415   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1416   /* add the products */
1417   mid = ((unsigned64) VH4_8 (m00)
1418          + (unsigned64) VL4_8 (m10)
1419          + (unsigned64) VL4_8 (m01));
1420   lo = U8_4 (mid, m00);
1421   hi = (m11
1422         + (unsigned64) VH4_8 (mid)
1423         + (unsigned64) VH4_8 (m01)
1424         + (unsigned64) VH4_8 (m10));
1425   /* fix the sign */
1426   if (sign & 1)
1427     {
1428       lo = -lo;
1429       if (lo == 0)
1430         hi = -hi;
1431       else
1432         hi = -hi - 1;
1433     }
1434   /* save the result HI/LO (and a gpr) */
1435   LO = lo;
1436   HI = hi;
1437   if (rd != 0)
1438     GPR[rd] = lo;
1439   TRACE_ALU_RESULT2 (HI, LO);
1440 }
1441
1442 :function:::void:do_dmult:int rs, int rt, int rd
1443 {
1444   do_dmultx (SD_, rs, rt, rd, 1);
1445 }
1446
1447 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1448 "dmult r<RS>, r<RT>"
1449 *mipsIII:
1450 *mipsIV:
1451 *mipsV:
1452 *mips64:
1453 *vr4100:
1454 {
1455   check_u64 (SD_, instruction_0);
1456   do_dmult (SD_, RS, RT, 0);
1457 }
1458
1459 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1460 "dmult r<RS>, r<RT>":RD == 0
1461 "dmult r<RD>, r<RS>, r<RT>"
1462 *vr5000:
1463 {
1464   check_u64 (SD_, instruction_0);
1465   do_dmult (SD_, RS, RT, RD);
1466 }
1467
1468
1469
1470 :function:::void:do_dmultu:int rs, int rt, int rd
1471 {
1472   do_dmultx (SD_, rs, rt, rd, 0);
1473 }
1474
1475 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1476 "dmultu r<RS>, r<RT>"
1477 *mipsIII:
1478 *mipsIV:
1479 *mipsV:
1480 *mips64:
1481 *vr4100:
1482 {
1483   check_u64 (SD_, instruction_0);
1484   do_dmultu (SD_, RS, RT, 0);
1485 }
1486
1487 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1488 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1489 "dmultu r<RS>, r<RT>"
1490 *vr5000:
1491 {
1492   check_u64 (SD_, instruction_0);
1493   do_dmultu (SD_, RS, RT, RD);
1494 }
1495
1496 :function:::void:do_dsll:int rt, int rd, int shift
1497 {
1498   TRACE_ALU_INPUT2 (GPR[rt], shift);
1499   GPR[rd] = GPR[rt] << shift;
1500   TRACE_ALU_RESULT (GPR[rd]);
1501 }
1502
1503 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1504 "dsll r<RD>, r<RT>, <SHIFT>"
1505 *mipsIII:
1506 *mipsIV:
1507 *mipsV:
1508 *mips64:
1509 *vr4100:
1510 *vr5000:
1511 {
1512   check_u64 (SD_, instruction_0);
1513   do_dsll (SD_, RT, RD, SHIFT);
1514 }
1515
1516
1517 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1518 "dsll32 r<RD>, r<RT>, <SHIFT>"
1519 *mipsIII:
1520 *mipsIV:
1521 *mipsV:
1522 *mips64:
1523 *vr4100:
1524 *vr5000:
1525 {
1526   int s = 32 + SHIFT;
1527   check_u64 (SD_, instruction_0);
1528   TRACE_ALU_INPUT2 (GPR[RT], s);
1529   GPR[RD] = GPR[RT] << s;
1530   TRACE_ALU_RESULT (GPR[RD]);
1531 }
1532
1533 :function:::void:do_dsllv:int rs, int rt, int rd
1534 {
1535   int s = MASKED64 (GPR[rs], 5, 0);
1536   TRACE_ALU_INPUT2 (GPR[rt], s);
1537   GPR[rd] = GPR[rt] << s;
1538   TRACE_ALU_RESULT (GPR[rd]);
1539 }
1540
1541 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1542 "dsllv r<RD>, r<RT>, r<RS>"
1543 *mipsIII:
1544 *mipsIV:
1545 *mipsV:
1546 *mips64:
1547 *vr4100:
1548 *vr5000:
1549 {
1550   check_u64 (SD_, instruction_0);
1551   do_dsllv (SD_, RS, RT, RD);
1552 }
1553
1554 :function:::void:do_dsra:int rt, int rd, int shift
1555 {
1556   TRACE_ALU_INPUT2 (GPR[rt], shift);
1557   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1558   TRACE_ALU_RESULT (GPR[rd]);
1559 }
1560
1561
1562 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1563 "dsra r<RD>, r<RT>, <SHIFT>"
1564 *mipsIII:
1565 *mipsIV:
1566 *mipsV:
1567 *mips64:
1568 *vr4100:
1569 *vr5000:
1570 {
1571   check_u64 (SD_, instruction_0);
1572   do_dsra (SD_, RT, RD, SHIFT);
1573 }
1574
1575
1576 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1577 "dsra32 r<RD>, r<RT>, <SHIFT>"
1578 *mipsIII:
1579 *mipsIV:
1580 *mipsV:
1581 *mips64:
1582 *vr4100:
1583 *vr5000:
1584 {
1585   int s = 32 + SHIFT;
1586   check_u64 (SD_, instruction_0);
1587   TRACE_ALU_INPUT2 (GPR[RT], s);
1588   GPR[RD] = ((signed64) GPR[RT]) >> s;
1589   TRACE_ALU_RESULT (GPR[RD]);
1590 }
1591
1592
1593 :function:::void:do_dsrav:int rs, int rt, int rd
1594 {
1595   int s = MASKED64 (GPR[rs], 5, 0);
1596   TRACE_ALU_INPUT2 (GPR[rt], s);
1597   GPR[rd] = ((signed64) GPR[rt]) >> s;
1598   TRACE_ALU_RESULT (GPR[rd]);
1599 }
1600
1601 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1602 "dsrav r<RD>, r<RT>, r<RS>"
1603 *mipsIII:
1604 *mipsIV:
1605 *mipsV:
1606 *mips64:
1607 *vr4100:
1608 *vr5000:
1609 {
1610   check_u64 (SD_, instruction_0);
1611   do_dsrav (SD_, RS, RT, RD);
1612 }
1613
1614 :function:::void:do_dsrl:int rt, int rd, int shift
1615 {
1616   TRACE_ALU_INPUT2 (GPR[rt], shift);
1617   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1618   TRACE_ALU_RESULT (GPR[rd]);
1619 }
1620
1621
1622 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1623 "dsrl r<RD>, r<RT>, <SHIFT>"
1624 *mipsIII:
1625 *mipsIV:
1626 *mipsV:
1627 *mips64:
1628 *vr4100:
1629 *vr5000:
1630 {
1631   check_u64 (SD_, instruction_0);
1632   do_dsrl (SD_, RT, RD, SHIFT);
1633 }
1634
1635
1636 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1637 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1638 *mipsIII:
1639 *mipsIV:
1640 *mipsV:
1641 *mips64:
1642 *vr4100:
1643 *vr5000:
1644 {
1645   int s = 32 + SHIFT;
1646   check_u64 (SD_, instruction_0);
1647   TRACE_ALU_INPUT2 (GPR[RT], s);
1648   GPR[RD] = (unsigned64) GPR[RT] >> s;
1649   TRACE_ALU_RESULT (GPR[RD]);
1650 }
1651
1652
1653 :function:::void:do_dsrlv:int rs, int rt, int rd
1654 {
1655   int s = MASKED64 (GPR[rs], 5, 0);
1656   TRACE_ALU_INPUT2 (GPR[rt], s);
1657   GPR[rd] = (unsigned64) GPR[rt] >> s;
1658   TRACE_ALU_RESULT (GPR[rd]);
1659 }
1660
1661
1662
1663 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1664 "dsrlv r<RD>, r<RT>, r<RS>"
1665 *mipsIII:
1666 *mipsIV:
1667 *mipsV:
1668 *mips64:
1669 *vr4100:
1670 *vr5000:
1671 {
1672   check_u64 (SD_, instruction_0);
1673   do_dsrlv (SD_, RS, RT, RD);
1674 }
1675
1676
1677 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1678 "dsub r<RD>, r<RS>, r<RT>"
1679 *mipsIII:
1680 *mipsIV:
1681 *mipsV:
1682 *mips64:
1683 *vr4100:
1684 *vr5000:
1685 {
1686   check_u64 (SD_, instruction_0);
1687   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1688   {
1689     ALU64_BEGIN (GPR[RS]);
1690     ALU64_SUB (GPR[RT]);
1691     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1692   }
1693   TRACE_ALU_RESULT (GPR[RD]);
1694 }
1695
1696
1697 :function:::void:do_dsubu:int rs, int rt, int rd
1698 {
1699   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1700   GPR[rd] = GPR[rs] - GPR[rt];
1701   TRACE_ALU_RESULT (GPR[rd]);
1702 }
1703
1704 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1705 "dsubu r<RD>, r<RS>, r<RT>"
1706 *mipsIII:
1707 *mipsIV:
1708 *mipsV:
1709 *mips64:
1710 *vr4100:
1711 *vr5000:
1712 {
1713   check_u64 (SD_, instruction_0);
1714   do_dsubu (SD_, RS, RT, RD);
1715 }
1716
1717
1718 000010,26.INSTR_INDEX:NORMAL:32::J
1719 "j <INSTR_INDEX>"
1720 *mipsI:
1721 *mipsII:
1722 *mipsIII:
1723 *mipsIV:
1724 *mipsV:
1725 *mips32:
1726 *mips64:
1727 *vr4100:
1728 *vr5000:
1729 *r3900:
1730 {
1731   /* NOTE: The region used is that of the delay slot NIA and NOT the
1732      current instruction */
1733   address_word region = (NIA & MASK (63, 28));
1734   DELAY_SLOT (region | (INSTR_INDEX << 2));
1735 }
1736
1737
1738 000011,26.INSTR_INDEX:NORMAL:32::JAL
1739 "jal <INSTR_INDEX>"
1740 *mipsI:
1741 *mipsII:
1742 *mipsIII:
1743 *mipsIV:
1744 *mipsV:
1745 *mips32:
1746 *mips64:
1747 *vr4100:
1748 *vr5000:
1749 *r3900:
1750 {
1751   /* NOTE: The region used is that of the delay slot and NOT the
1752      current instruction */
1753   address_word region = (NIA & MASK (63, 28));
1754   GPR[31] = CIA + 8;
1755   DELAY_SLOT (region | (INSTR_INDEX << 2));
1756 }
1757
1758 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1759 "jalr r<RS>":RD == 31
1760 "jalr r<RD>, r<RS>"
1761 *mipsI:
1762 *mipsII:
1763 *mipsIII:
1764 *mipsIV:
1765 *mipsV:
1766 *mips32:
1767 *mips64:
1768 *vr4100:
1769 *vr5000:
1770 *r3900:
1771 {
1772   address_word temp = GPR[RS];
1773   GPR[RD] = CIA + 8;
1774   DELAY_SLOT (temp);
1775 }
1776
1777
1778 000000,5.RS,000000000000000,001000:SPECIAL:32::JR
1779 "jr r<RS>"
1780 *mipsI:
1781 *mipsII:
1782 *mipsIII:
1783 *mipsIV:
1784 *mipsV:
1785 *mips32:
1786 *mips64:
1787 *vr4100:
1788 *vr5000:
1789 *r3900:
1790 {
1791   DELAY_SLOT (GPR[RS]);
1792 }
1793
1794
1795 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1796 {
1797   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1798   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1799   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1800   unsigned int byte;
1801   address_word paddr;
1802   int uncached;
1803   unsigned64 memval;
1804   address_word vaddr;
1805
1806   vaddr = loadstore_ea (SD_, base, offset);
1807   if ((vaddr & access) != 0)
1808     {
1809       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
1810     }
1811   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1812   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
1813   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
1814   byte = ((vaddr & mask) ^ bigendiancpu);
1815   return (memval >> (8 * byte));
1816 }
1817
1818 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
1819 {
1820   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1821   address_word reverseendian = (ReverseEndian ? -1 : 0);
1822   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1823   unsigned int byte;
1824   unsigned int word;
1825   address_word paddr;
1826   int uncached;
1827   unsigned64 memval;
1828   address_word vaddr;
1829   int nr_lhs_bits;
1830   int nr_rhs_bits;
1831   unsigned_word lhs_mask;
1832   unsigned_word temp;
1833
1834   vaddr = loadstore_ea (SD_, base, offset);
1835   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1836   paddr = (paddr ^ (reverseendian & mask));
1837   if (BigEndianMem == 0)
1838     paddr = paddr & ~access;
1839
1840   /* compute where within the word/mem we are */
1841   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
1842   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
1843   nr_lhs_bits = 8 * byte + 8;
1844   nr_rhs_bits = 8 * access - 8 * byte;
1845   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
1846
1847   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
1848            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
1849            (long) ((unsigned64) paddr >> 32), (long) paddr,
1850            word, byte, nr_lhs_bits, nr_rhs_bits); */
1851
1852   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
1853   if (word == 0)
1854     {
1855       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
1856       temp = (memval << nr_rhs_bits);
1857     }
1858   else
1859     {
1860       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
1861       temp = (memval >> nr_lhs_bits);
1862     }
1863   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
1864   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
1865
1866   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
1867            (long) ((unsigned64) memval >> 32), (long) memval,
1868            (long) ((unsigned64) temp >> 32), (long) temp,
1869            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
1870            (long) (rt >> 32), (long) rt); */
1871   return rt;
1872 }
1873
1874 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
1875 {
1876   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1877   address_word reverseendian = (ReverseEndian ? -1 : 0);
1878   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
1879   unsigned int byte;
1880   address_word paddr;
1881   int uncached;
1882   unsigned64 memval;
1883   address_word vaddr;
1884
1885   vaddr = loadstore_ea (SD_, base, offset);
1886   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
1887   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
1888   paddr = (paddr ^ (reverseendian & mask));
1889   if (BigEndianMem != 0)
1890     paddr = paddr & ~access;
1891   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
1892   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
1893   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
1894   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
1895      (long) paddr, byte, (long) paddr, (long) memval); */
1896   {
1897     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
1898     rt &= ~screen;
1899     rt |= (memval >> (8 * byte)) & screen;
1900   }
1901   return rt;
1902 }
1903
1904
1905 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
1906 "lb r<RT>, <OFFSET>(r<BASE>)"
1907 *mipsI:
1908 *mipsII:
1909 *mipsIII:
1910 *mipsIV:
1911 *mipsV:
1912 *mips32:
1913 *mips64:
1914 *vr4100:
1915 *vr5000:
1916 *r3900:
1917 {
1918   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
1919 }
1920
1921
1922 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
1923 "lbu r<RT>, <OFFSET>(r<BASE>)"
1924 *mipsI:
1925 *mipsII:
1926 *mipsIII:
1927 *mipsIV:
1928 *mipsV:
1929 *mips32:
1930 *mips64:
1931 *vr4100:
1932 *vr5000:
1933 *r3900:
1934 {
1935   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
1936 }
1937
1938
1939 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
1940 "ld r<RT>, <OFFSET>(r<BASE>)"
1941 *mipsIII:
1942 *mipsIV:
1943 *mipsV:
1944 *mips64:
1945 *vr4100:
1946 *vr5000:
1947 {
1948   check_u64 (SD_, instruction_0);
1949   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1950 }
1951
1952
1953 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
1954 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
1955 *mipsII:
1956 *mipsIII:
1957 *mipsIV:
1958 *mipsV:
1959 *mips32:
1960 *mips64:
1961 *vr4100:
1962 *vr5000:
1963 *r3900:
1964 {
1965   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
1966 }
1967
1968
1969
1970
1971 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
1972 "ldl r<RT>, <OFFSET>(r<BASE>)"
1973 *mipsIII:
1974 *mipsIV:
1975 *mipsV:
1976 *mips64:
1977 *vr4100:
1978 *vr5000:
1979 {
1980   check_u64 (SD_, instruction_0);
1981   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1982 }
1983
1984
1985 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
1986 "ldr r<RT>, <OFFSET>(r<BASE>)"
1987 *mipsIII:
1988 *mipsIV:
1989 *mipsV:
1990 *mips64:
1991 *vr4100:
1992 *vr5000:
1993 {
1994   check_u64 (SD_, instruction_0);
1995   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
1996 }
1997
1998
1999 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2000 "lh r<RT>, <OFFSET>(r<BASE>)"
2001 *mipsI:
2002 *mipsII:
2003 *mipsIII:
2004 *mipsIV:
2005 *mipsV:
2006 *mips32:
2007 *mips64:
2008 *vr4100:
2009 *vr5000:
2010 *r3900:
2011 {
2012   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2013 }
2014
2015
2016 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2017 "lhu r<RT>, <OFFSET>(r<BASE>)"
2018 *mipsI:
2019 *mipsII:
2020 *mipsIII:
2021 *mipsIV:
2022 *mipsV:
2023 *mips32:
2024 *mips64:
2025 *vr4100:
2026 *vr5000:
2027 *r3900:
2028 {
2029   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2030 }
2031
2032
2033 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2034 "ll r<RT>, <OFFSET>(r<BASE>)"
2035 *mipsII:
2036 *mipsIII:
2037 *mipsIV:
2038 *mipsV:
2039 *mips32:
2040 *mips64:
2041 *vr4100:
2042 *vr5000:
2043 {
2044   address_word base = GPR[BASE];
2045   address_word offset = EXTEND16 (OFFSET);
2046   {
2047     address_word vaddr = loadstore_ea (SD_, base, offset);
2048     address_word paddr;
2049     int uncached;
2050     if ((vaddr & 3) != 0)
2051       {
2052         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2053       }
2054     else
2055       {
2056         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2057           {
2058             unsigned64 memval = 0;
2059             unsigned64 memval1 = 0;
2060             unsigned64 mask = 0x7;
2061             unsigned int shift = 2;
2062             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2063             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2064             unsigned int byte;
2065             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2066             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2067             byte = ((vaddr & mask) ^ (bigend << shift));
2068             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2069             LLBIT = 1;
2070           }
2071       }
2072   }
2073 }
2074
2075
2076 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2077 "lld r<RT>, <OFFSET>(r<BASE>)"
2078 *mipsIII:
2079 *mipsIV:
2080 *mipsV:
2081 *mips64:
2082 *vr4100:
2083 *vr5000:
2084 {
2085   address_word base = GPR[BASE];
2086   address_word offset = EXTEND16 (OFFSET);
2087   check_u64 (SD_, instruction_0);
2088   {
2089     address_word vaddr = loadstore_ea (SD_, base, offset);
2090     address_word paddr;
2091     int uncached;
2092     if ((vaddr & 7) != 0)
2093       {
2094         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2095       }
2096     else
2097       {
2098         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2099           {
2100             unsigned64 memval = 0;
2101             unsigned64 memval1 = 0;
2102             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2103             GPR[RT] = memval;
2104             LLBIT = 1;
2105           }
2106       }
2107   }
2108 }
2109
2110
2111 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2112 "lui r<RT>, %#lx<IMMEDIATE>"
2113 *mipsI:
2114 *mipsII:
2115 *mipsIII:
2116 *mipsIV:
2117 *mipsV:
2118 *mips32:
2119 *mips64:
2120 *vr4100:
2121 *vr5000:
2122 *r3900:
2123 {
2124   TRACE_ALU_INPUT1 (IMMEDIATE);
2125   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2126   TRACE_ALU_RESULT (GPR[RT]);
2127 }
2128
2129
2130 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2131 "lw r<RT>, <OFFSET>(r<BASE>)"
2132 *mipsI:
2133 *mipsII:
2134 *mipsIII:
2135 *mipsIV:
2136 *mipsV:
2137 *mips32:
2138 *mips64:
2139 *vr4100:
2140 *vr5000:
2141 *r3900:
2142 {
2143   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2144 }
2145
2146
2147 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2148 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2149 *mipsI:
2150 *mipsII:
2151 *mipsIII:
2152 *mipsIV:
2153 *mipsV:
2154 *mips32:
2155 *mips64:
2156 *vr4100:
2157 *vr5000:
2158 *r3900:
2159 {
2160   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2161 }
2162
2163
2164 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2165 "lwl r<RT>, <OFFSET>(r<BASE>)"
2166 *mipsI:
2167 *mipsII:
2168 *mipsIII:
2169 *mipsIV:
2170 *mipsV:
2171 *mips32:
2172 *mips64:
2173 *vr4100:
2174 *vr5000:
2175 *r3900:
2176 {
2177   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2178 }
2179
2180
2181 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2182 "lwr r<RT>, <OFFSET>(r<BASE>)"
2183 *mipsI:
2184 *mipsII:
2185 *mipsIII:
2186 *mipsIV:
2187 *mipsV:
2188 *mips32:
2189 *mips64:
2190 *vr4100:
2191 *vr5000:
2192 *r3900:
2193 {
2194   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2195 }
2196
2197
2198 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2199 "lwu r<RT>, <OFFSET>(r<BASE>)"
2200 *mipsIII:
2201 *mipsIV:
2202 *mipsV:
2203 *mips64:
2204 *vr4100:
2205 *vr5000:
2206 {
2207   check_u64 (SD_, instruction_0);
2208   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2209 }
2210
2211
2212
2213 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2214 "madd r<RS>, r<RT>"
2215 *mips32:
2216 *mips64:
2217 *vr5500:
2218 {
2219   signed64 temp;
2220   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2221   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2222     Unpredictable ();
2223   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2224   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2225           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2226   LO = EXTEND32 (temp);
2227   HI = EXTEND32 (VH4_8 (temp));
2228   TRACE_ALU_RESULT2 (HI, LO);
2229 }
2230
2231
2232
2233 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2234 "maddu r<RS>, r<RT>"
2235 *mips32:
2236 *mips64:
2237 *vr5500:
2238 {
2239   unsigned64 temp;
2240   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2241   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2242     Unpredictable ();
2243   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2244   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2245           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2246   LO = EXTEND32 (temp);
2247   HI = EXTEND32 (VH4_8 (temp));
2248   TRACE_ALU_RESULT2 (HI, LO);
2249 }
2250
2251
2252 :function:::void:do_mfhi:int rd
2253 {
2254   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2255   TRACE_ALU_INPUT1 (HI);
2256   GPR[rd] = HI;
2257   TRACE_ALU_RESULT (GPR[rd]);
2258 }
2259
2260 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2261 "mfhi r<RD>"
2262 *mipsI:
2263 *mipsII:
2264 *mipsIII:
2265 *mipsIV:
2266 *mipsV:
2267 *mips32:
2268 *mips64:
2269 *vr4100:
2270 *vr5000:
2271 *r3900:
2272 {
2273   do_mfhi (SD_, RD);
2274 }
2275
2276
2277
2278 :function:::void:do_mflo:int rd
2279 {
2280   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2281   TRACE_ALU_INPUT1 (LO);
2282   GPR[rd] = LO;
2283   TRACE_ALU_RESULT (GPR[rd]);
2284 }
2285
2286 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2287 "mflo r<RD>"
2288 *mipsI:
2289 *mipsII:
2290 *mipsIII:
2291 *mipsIV:
2292 *mipsV:
2293 *mips32:
2294 *mips64:
2295 *vr4100:
2296 *vr5000:
2297 *r3900:
2298 {
2299   do_mflo (SD_, RD);
2300 }
2301
2302
2303
2304 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2305 "movn r<RD>, r<RS>, r<RT>"
2306 *mipsIV:
2307 *mipsV:
2308 *mips32:
2309 *mips64:
2310 *vr5000:
2311 {
2312   if (GPR[RT] != 0)
2313     {
2314       GPR[RD] = GPR[RS];
2315       TRACE_ALU_RESULT (GPR[RD]);
2316     }
2317 }
2318
2319
2320
2321 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2322 "movz r<RD>, r<RS>, r<RT>"
2323 *mipsIV:
2324 *mipsV:
2325 *mips32:
2326 *mips64:
2327 *vr5000:
2328 {
2329   if (GPR[RT] == 0)
2330     {
2331       GPR[RD] = GPR[RS];
2332       TRACE_ALU_RESULT (GPR[RD]);
2333     }
2334 }
2335
2336
2337
2338 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2339 "msub r<RS>, r<RT>"
2340 *mips32:
2341 *mips64:
2342 *vr5500:
2343 {
2344   signed64 temp;
2345   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2346   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2347     Unpredictable ();
2348   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2349   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2350           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2351   LO = EXTEND32 (temp);
2352   HI = EXTEND32 (VH4_8 (temp));
2353   TRACE_ALU_RESULT2 (HI, LO);
2354 }
2355
2356
2357
2358 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2359 "msubu r<RS>, r<RT>"
2360 *mips32:
2361 *mips64:
2362 *vr5500:
2363 {
2364   unsigned64 temp;
2365   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2366   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2367     Unpredictable ();
2368   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2369   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2370           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2371   LO = EXTEND32 (temp);
2372   HI = EXTEND32 (VH4_8 (temp));
2373   TRACE_ALU_RESULT2 (HI, LO);
2374 }
2375
2376
2377
2378 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2379 "mthi r<RS>"
2380 *mipsI:
2381 *mipsII:
2382 *mipsIII:
2383 *mipsIV:
2384 *mipsV:
2385 *mips32:
2386 *mips64:
2387 *vr4100:
2388 *vr5000:
2389 *r3900:
2390 {
2391   check_mt_hilo (SD_, HIHISTORY);
2392   HI = GPR[RS];
2393 }
2394
2395
2396
2397 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2398 "mtlo r<RS>"
2399 *mipsI:
2400 *mipsII:
2401 *mipsIII:
2402 *mipsIV:
2403 *mipsV:
2404 *mips32:
2405 *mips64:
2406 *vr4100:
2407 *vr5000:
2408 *r3900:
2409 {
2410   check_mt_hilo (SD_, LOHISTORY);
2411   LO = GPR[RS];
2412 }
2413
2414
2415
2416 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2417 "mul r<RD>, r<RS>, r<RT>"
2418 *mips32:
2419 *mips64:
2420 *vr5500:
2421 {
2422   signed64 prod;
2423   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2424     Unpredictable ();
2425   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2426   prod = (((signed64)(signed32) GPR[RS])
2427           * ((signed64)(signed32) GPR[RT]));
2428   GPR[RD] = EXTEND32 (VL4_8 (prod));
2429   TRACE_ALU_RESULT (GPR[RD]);
2430 }
2431
2432
2433
2434 :function:::void:do_mult:int rs, int rt, int rd
2435 {
2436   signed64 prod;
2437   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2438   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2439     Unpredictable ();
2440   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2441   prod = (((signed64)(signed32) GPR[rs])
2442           * ((signed64)(signed32) GPR[rt]));
2443   LO = EXTEND32 (VL4_8 (prod));
2444   HI = EXTEND32 (VH4_8 (prod));
2445   if (rd != 0)
2446     GPR[rd] = LO;
2447   TRACE_ALU_RESULT2 (HI, LO);
2448 }
2449
2450 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2451 "mult r<RS>, r<RT>"
2452 *mipsI:
2453 *mipsII:
2454 *mipsIII:
2455 *mipsIV:
2456 *mipsV:
2457 *mips32:
2458 *mips64:
2459 *vr4100:
2460 {
2461   do_mult (SD_, RS, RT, 0);
2462 }
2463
2464
2465 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2466 "mult r<RS>, r<RT>":RD == 0
2467 "mult r<RD>, r<RS>, r<RT>"
2468 *vr5000:
2469 *r3900:
2470 {
2471   do_mult (SD_, RS, RT, RD);
2472 }
2473
2474
2475 :function:::void:do_multu:int rs, int rt, int rd
2476 {
2477   unsigned64 prod;
2478   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2479   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2480     Unpredictable ();
2481   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2482   prod = (((unsigned64)(unsigned32) GPR[rs])
2483           * ((unsigned64)(unsigned32) GPR[rt]));
2484   LO = EXTEND32 (VL4_8 (prod));
2485   HI = EXTEND32 (VH4_8 (prod));
2486   if (rd != 0)
2487     GPR[rd] = LO;
2488   TRACE_ALU_RESULT2 (HI, LO);
2489 }
2490
2491 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2492 "multu r<RS>, r<RT>"
2493 *mipsI:
2494 *mipsII:
2495 *mipsIII:
2496 *mipsIV:
2497 *mipsV:
2498 *mips32:
2499 *mips64:
2500 *vr4100:
2501 {
2502   do_multu (SD_, RS, RT, 0);
2503 }
2504
2505 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2506 "multu r<RS>, r<RT>":RD == 0
2507 "multu r<RD>, r<RS>, r<RT>"
2508 *vr5000:
2509 *r3900:
2510 {
2511   do_multu (SD_, RS, RT, RD);
2512 }
2513
2514
2515 :function:::void:do_nor:int rs, int rt, int rd
2516 {
2517   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2518   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2519   TRACE_ALU_RESULT (GPR[rd]);
2520 }
2521
2522 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2523 "nor r<RD>, r<RS>, r<RT>"
2524 *mipsI:
2525 *mipsII:
2526 *mipsIII:
2527 *mipsIV:
2528 *mipsV:
2529 *mips32:
2530 *mips64:
2531 *vr4100:
2532 *vr5000:
2533 *r3900:
2534 {
2535   do_nor (SD_, RS, RT, RD);
2536 }
2537
2538
2539 :function:::void:do_or:int rs, int rt, int rd
2540 {
2541   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2542   GPR[rd] = (GPR[rs] | GPR[rt]);
2543   TRACE_ALU_RESULT (GPR[rd]);
2544 }
2545
2546 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2547 "or r<RD>, r<RS>, r<RT>"
2548 *mipsI:
2549 *mipsII:
2550 *mipsIII:
2551 *mipsIV:
2552 *mipsV:
2553 *mips32:
2554 *mips64:
2555 *vr4100:
2556 *vr5000:
2557 *r3900:
2558 {
2559   do_or (SD_, RS, RT, RD);
2560 }
2561
2562
2563
2564 :function:::void:do_ori:int rs, int rt, unsigned immediate
2565 {
2566   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2567   GPR[rt] = (GPR[rs] | immediate);
2568   TRACE_ALU_RESULT (GPR[rt]);
2569 }
2570
2571 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2572 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2573 *mipsI:
2574 *mipsII:
2575 *mipsIII:
2576 *mipsIV:
2577 *mipsV:
2578 *mips32:
2579 *mips64:
2580 *vr4100:
2581 *vr5000:
2582 *r3900:
2583 {
2584   do_ori (SD_, RS, RT, IMMEDIATE);
2585 }
2586
2587
2588 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
2589 "pref <HINT>, <OFFSET>(r<BASE>)"
2590 *mipsIV:
2591 *mipsV:
2592 *mips32:
2593 *mips64:
2594 *vr5000:
2595 {
2596   address_word base = GPR[BASE];
2597   address_word offset = EXTEND16 (OFFSET);
2598   {
2599     address_word vaddr = loadstore_ea (SD_, base, offset);
2600     address_word paddr;
2601     int uncached;
2602     {
2603       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2604         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
2605     }
2606   }
2607 }
2608
2609
2610 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
2611 {
2612   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2613   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
2614   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
2615   unsigned int byte;
2616   address_word paddr;
2617   int uncached;
2618   unsigned64 memval;
2619   address_word vaddr;
2620
2621   vaddr = loadstore_ea (SD_, base, offset);
2622   if ((vaddr & access) != 0)
2623     {
2624       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
2625     }
2626   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2627   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2628   byte = ((vaddr & mask) ^ bigendiancpu);
2629   memval = (word << (8 * byte));
2630   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
2631 }
2632
2633 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2634 {
2635   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2636   address_word reverseendian = (ReverseEndian ? -1 : 0);
2637   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2638   unsigned int byte;
2639   unsigned int word;
2640   address_word paddr;
2641   int uncached;
2642   unsigned64 memval;
2643   address_word vaddr;
2644   int nr_lhs_bits;
2645   int nr_rhs_bits;
2646
2647   vaddr = loadstore_ea (SD_, base, offset);
2648   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2649   paddr = (paddr ^ (reverseendian & mask));
2650   if (BigEndianMem == 0)
2651     paddr = paddr & ~access;
2652
2653   /* compute where within the word/mem we are */
2654   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2655   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2656   nr_lhs_bits = 8 * byte + 8;
2657   nr_rhs_bits = 8 * access - 8 * byte;
2658   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2659   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2660            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2661            (long) ((unsigned64) paddr >> 32), (long) paddr,
2662            word, byte, nr_lhs_bits, nr_rhs_bits); */
2663
2664   if (word == 0)
2665     {
2666       memval = (rt >> nr_rhs_bits);
2667     }
2668   else
2669     {
2670       memval = (rt << nr_lhs_bits);
2671     }
2672   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
2673            (long) ((unsigned64) rt >> 32), (long) rt,
2674            (long) ((unsigned64) memval >> 32), (long) memval); */
2675   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
2676 }
2677
2678 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2679 {
2680   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2681   address_word reverseendian = (ReverseEndian ? -1 : 0);
2682   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2683   unsigned int byte;
2684   address_word paddr;
2685   int uncached;
2686   unsigned64 memval;
2687   address_word vaddr;
2688
2689   vaddr = loadstore_ea (SD_, base, offset);
2690   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
2691   paddr = (paddr ^ (reverseendian & mask));
2692   if (BigEndianMem != 0)
2693     paddr &= ~access;
2694   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2695   memval = (rt << (byte * 8));
2696   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
2697 }
2698
2699
2700 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
2701 "sb r<RT>, <OFFSET>(r<BASE>)"
2702 *mipsI:
2703 *mipsII:
2704 *mipsIII:
2705 *mipsIV:
2706 *mipsV:
2707 *mips32:
2708 *mips64:
2709 *vr4100:
2710 *vr5000:
2711 *r3900:
2712 {
2713   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2714 }
2715
2716
2717 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
2718 "sc r<RT>, <OFFSET>(r<BASE>)"
2719 *mipsII:
2720 *mipsIII:
2721 *mipsIV:
2722 *mipsV:
2723 *mips32:
2724 *mips64:
2725 *vr4100:
2726 *vr5000:
2727 {
2728   unsigned32 instruction = instruction_0;
2729   address_word base = GPR[BASE];
2730   address_word offset = EXTEND16 (OFFSET);
2731   {
2732     address_word vaddr = loadstore_ea (SD_, base, offset);
2733     address_word paddr;
2734     int uncached;
2735     if ((vaddr & 3) != 0)
2736       {
2737         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
2738       }
2739     else
2740       {
2741         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2742           {
2743             unsigned64 memval = 0;
2744             unsigned64 memval1 = 0;
2745             unsigned64 mask = 0x7;
2746             unsigned int byte;
2747             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
2748             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
2749             memval = ((unsigned64) GPR[RT] << (8 * byte));
2750             if (LLBIT)
2751               {
2752                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
2753               }
2754             GPR[RT] = LLBIT;
2755           }
2756       }
2757   }
2758 }
2759
2760
2761 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
2762 "scd r<RT>, <OFFSET>(r<BASE>)"
2763 *mipsIII:
2764 *mipsIV:
2765 *mipsV:
2766 *mips64:
2767 *vr4100:
2768 *vr5000:
2769 {
2770   address_word base = GPR[BASE];
2771   address_word offset = EXTEND16 (OFFSET);
2772   check_u64 (SD_, instruction_0);
2773   {
2774     address_word vaddr = loadstore_ea (SD_, base, offset);
2775     address_word paddr;
2776     int uncached;
2777     if ((vaddr & 7) != 0)
2778       {
2779         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
2780       }
2781     else
2782       {
2783         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
2784           {
2785             unsigned64 memval = 0;
2786             unsigned64 memval1 = 0;
2787             memval = GPR[RT];
2788             if (LLBIT)
2789               {
2790                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
2791               }
2792             GPR[RT] = LLBIT;
2793           }
2794       }
2795   }
2796 }
2797
2798
2799 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
2800 "sd r<RT>, <OFFSET>(r<BASE>)"
2801 *mipsIII:
2802 *mipsIV:
2803 *mipsV:
2804 *mips64:
2805 *vr4100:
2806 *vr5000:
2807 {
2808   check_u64 (SD_, instruction_0);
2809   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2810 }
2811
2812
2813 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
2814 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2815 *mipsII:
2816 *mipsIII:
2817 *mipsIV:
2818 *mipsV:
2819 *mips32:
2820 *mips64:
2821 *vr4100:
2822 *vr5000:
2823 {
2824   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
2825 }
2826
2827
2828 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
2829 "sdl r<RT>, <OFFSET>(r<BASE>)"
2830 *mipsIII:
2831 *mipsIV:
2832 *mipsV:
2833 *mips64:
2834 *vr4100:
2835 *vr5000:
2836 {
2837   check_u64 (SD_, instruction_0);
2838   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2839 }
2840
2841
2842 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
2843 "sdr r<RT>, <OFFSET>(r<BASE>)"
2844 *mipsIII:
2845 *mipsIV:
2846 *mipsV:
2847 *mips64:
2848 *vr4100:
2849 *vr5000:
2850 {
2851   check_u64 (SD_, instruction_0);
2852   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2853 }
2854
2855
2856 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
2857 "sh r<RT>, <OFFSET>(r<BASE>)"
2858 *mipsI:
2859 *mipsII:
2860 *mipsIII:
2861 *mipsIV:
2862 *mipsV:
2863 *mips32:
2864 *mips64:
2865 *vr4100:
2866 *vr5000:
2867 *r3900:
2868 {
2869   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2870 }
2871
2872
2873 :function:::void:do_sll:int rt, int rd, int shift
2874 {
2875   unsigned32 temp = (GPR[rt] << shift);
2876   TRACE_ALU_INPUT2 (GPR[rt], shift);
2877   GPR[rd] = EXTEND32 (temp);
2878   TRACE_ALU_RESULT (GPR[rd]);
2879 }
2880
2881 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
2882 "nop":RD == 0 && RT == 0 && SHIFT == 0
2883 "sll r<RD>, r<RT>, <SHIFT>"
2884 *mipsI:
2885 *mipsII:
2886 *mipsIII:
2887 *mipsIV:
2888 *mipsV:
2889 *vr4100:
2890 *vr5000:
2891 *r3900:
2892 {
2893   /* Skip shift for NOP, so that there won't be lots of extraneous
2894      trace output.  */
2895   if (RD != 0 || RT != 0 || SHIFT != 0)
2896     do_sll (SD_, RT, RD, SHIFT);
2897 }
2898
2899 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
2900 "nop":RD == 0 && RT == 0 && SHIFT == 0
2901 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
2902 "sll r<RD>, r<RT>, <SHIFT>"
2903 *mips32:
2904 *mips64:
2905 {
2906   /* Skip shift for NOP and SSNOP, so that there won't be lots of
2907      extraneous trace output.  */
2908   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
2909     do_sll (SD_, RT, RD, SHIFT);
2910 }
2911
2912
2913 :function:::void:do_sllv:int rs, int rt, int rd
2914 {
2915   int s = MASKED (GPR[rs], 4, 0);
2916   unsigned32 temp = (GPR[rt] << s);
2917   TRACE_ALU_INPUT2 (GPR[rt], s);
2918   GPR[rd] = EXTEND32 (temp);
2919   TRACE_ALU_RESULT (GPR[rd]);
2920 }
2921
2922 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
2923 "sllv r<RD>, r<RT>, r<RS>"
2924 *mipsI:
2925 *mipsII:
2926 *mipsIII:
2927 *mipsIV:
2928 *mipsV:
2929 *mips32:
2930 *mips64:
2931 *vr4100:
2932 *vr5000:
2933 *r3900:
2934 {
2935   do_sllv (SD_, RS, RT, RD);
2936 }
2937
2938
2939 :function:::void:do_slt:int rs, int rt, int rd
2940 {
2941   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2942   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
2943   TRACE_ALU_RESULT (GPR[rd]);
2944 }
2945
2946 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
2947 "slt r<RD>, r<RS>, r<RT>"
2948 *mipsI:
2949 *mipsII:
2950 *mipsIII:
2951 *mipsIV:
2952 *mipsV:
2953 *mips32:
2954 *mips64:
2955 *vr4100:
2956 *vr5000:
2957 *r3900:
2958 {
2959   do_slt (SD_, RS, RT, RD);
2960 }
2961
2962
2963 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
2964 {
2965   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2966   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
2967   TRACE_ALU_RESULT (GPR[rt]);
2968 }
2969
2970 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
2971 "slti r<RT>, r<RS>, <IMMEDIATE>"
2972 *mipsI:
2973 *mipsII:
2974 *mipsIII:
2975 *mipsIV:
2976 *mipsV:
2977 *mips32:
2978 *mips64:
2979 *vr4100:
2980 *vr5000:
2981 *r3900:
2982 {
2983   do_slti (SD_, RS, RT, IMMEDIATE);
2984 }
2985
2986
2987 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
2988 {
2989   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
2990   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
2991   TRACE_ALU_RESULT (GPR[rt]);
2992 }
2993
2994 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
2995 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
2996 *mipsI:
2997 *mipsII:
2998 *mipsIII:
2999 *mipsIV:
3000 *mipsV:
3001 *mips32:
3002 *mips64:
3003 *vr4100:
3004 *vr5000:
3005 *r3900:
3006 {
3007   do_sltiu (SD_, RS, RT, IMMEDIATE);
3008 }
3009
3010
3011
3012 :function:::void:do_sltu:int rs, int rt, int rd
3013 {
3014   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3015   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3016   TRACE_ALU_RESULT (GPR[rd]);
3017 }
3018
3019 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3020 "sltu r<RD>, r<RS>, r<RT>"
3021 *mipsI:
3022 *mipsII:
3023 *mipsIII:
3024 *mipsIV:
3025 *mipsV:
3026 *mips32:
3027 *mips64:
3028 *vr4100:
3029 *vr5000:
3030 *r3900:
3031 {
3032   do_sltu (SD_, RS, RT, RD);
3033 }
3034
3035
3036 :function:::void:do_sra:int rt, int rd, int shift
3037 {
3038   signed32 temp = (signed32) GPR[rt] >> shift;
3039   if (NotWordValue (GPR[rt]))
3040     Unpredictable ();
3041   TRACE_ALU_INPUT2 (GPR[rt], shift);
3042   GPR[rd] = EXTEND32 (temp);
3043   TRACE_ALU_RESULT (GPR[rd]);
3044 }
3045
3046 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3047 "sra r<RD>, r<RT>, <SHIFT>"
3048 *mipsI:
3049 *mipsII:
3050 *mipsIII:
3051 *mipsIV:
3052 *mipsV:
3053 *mips32:
3054 *mips64:
3055 *vr4100:
3056 *vr5000:
3057 *r3900:
3058 {
3059   do_sra (SD_, RT, RD, SHIFT);
3060 }
3061
3062
3063
3064 :function:::void:do_srav:int rs, int rt, int rd
3065 {
3066   int s = MASKED (GPR[rs], 4, 0);
3067   signed32 temp = (signed32) GPR[rt] >> s;
3068   if (NotWordValue (GPR[rt]))
3069     Unpredictable ();
3070   TRACE_ALU_INPUT2 (GPR[rt], s);
3071   GPR[rd] = EXTEND32 (temp);
3072   TRACE_ALU_RESULT (GPR[rd]);
3073 }
3074
3075 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3076 "srav r<RD>, r<RT>, r<RS>"
3077 *mipsI:
3078 *mipsII:
3079 *mipsIII:
3080 *mipsIV:
3081 *mipsV:
3082 *mips32:
3083 *mips64:
3084 *vr4100:
3085 *vr5000:
3086 *r3900:
3087 {
3088   do_srav (SD_, RS, RT, RD);
3089 }
3090
3091
3092
3093 :function:::void:do_srl:int rt, int rd, int shift
3094 {
3095   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3096   if (NotWordValue (GPR[rt]))
3097     Unpredictable ();
3098   TRACE_ALU_INPUT2 (GPR[rt], shift);
3099   GPR[rd] = EXTEND32 (temp);
3100   TRACE_ALU_RESULT (GPR[rd]);
3101 }
3102
3103 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3104 "srl r<RD>, r<RT>, <SHIFT>"
3105 *mipsI:
3106 *mipsII:
3107 *mipsIII:
3108 *mipsIV:
3109 *mipsV:
3110 *mips32:
3111 *mips64:
3112 *vr4100:
3113 *vr5000:
3114 *r3900:
3115 {
3116   do_srl (SD_, RT, RD, SHIFT);
3117 }
3118
3119
3120 :function:::void:do_srlv:int rs, int rt, int rd
3121 {
3122   int s = MASKED (GPR[rs], 4, 0);
3123   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3124   if (NotWordValue (GPR[rt]))
3125     Unpredictable ();
3126   TRACE_ALU_INPUT2 (GPR[rt], s);
3127   GPR[rd] = EXTEND32 (temp);
3128   TRACE_ALU_RESULT (GPR[rd]);
3129 }
3130
3131 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3132 "srlv r<RD>, r<RT>, r<RS>"
3133 *mipsI:
3134 *mipsII:
3135 *mipsIII:
3136 *mipsIV:
3137 *mipsV:
3138 *mips32:
3139 *mips64:
3140 *vr4100:
3141 *vr5000:
3142 *r3900:
3143 {
3144   do_srlv (SD_, RS, RT, RD);
3145 }
3146
3147
3148 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3149 "sub r<RD>, r<RS>, r<RT>"
3150 *mipsI:
3151 *mipsII:
3152 *mipsIII:
3153 *mipsIV:
3154 *mipsV:
3155 *mips32:
3156 *mips64:
3157 *vr4100:
3158 *vr5000:
3159 *r3900:
3160 {
3161   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3162     Unpredictable ();
3163   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3164   {
3165     ALU32_BEGIN (GPR[RS]);
3166     ALU32_SUB (GPR[RT]);
3167     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3168   }
3169   TRACE_ALU_RESULT (GPR[RD]);
3170 }
3171
3172
3173 :function:::void:do_subu:int rs, int rt, int rd
3174 {
3175   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3176     Unpredictable ();
3177   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3178   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3179   TRACE_ALU_RESULT (GPR[rd]);
3180 }
3181
3182 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3183 "subu r<RD>, r<RS>, r<RT>"
3184 *mipsI:
3185 *mipsII:
3186 *mipsIII:
3187 *mipsIV:
3188 *mipsV:
3189 *mips32:
3190 *mips64:
3191 *vr4100:
3192 *vr5000:
3193 *r3900:
3194 {
3195   do_subu (SD_, RS, RT, RD);
3196 }
3197
3198
3199 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3200 "sw r<RT>, <OFFSET>(r<BASE>)"
3201 *mipsI:
3202 *mipsII:
3203 *mipsIII:
3204 *mipsIV:
3205 *mipsV:
3206 *mips32:
3207 *mips64:
3208 *vr4100:
3209 *r3900:
3210 *vr5000:
3211 {
3212   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3213 }
3214
3215
3216 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3217 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3218 *mipsI:
3219 *mipsII:
3220 *mipsIII:
3221 *mipsIV:
3222 *mipsV:
3223 *mips32:
3224 *mips64:
3225 *vr4100:
3226 *vr5000:
3227 *r3900:
3228 {
3229   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3230 }
3231
3232
3233 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3234 "swl r<RT>, <OFFSET>(r<BASE>)"
3235 *mipsI:
3236 *mipsII:
3237 *mipsIII:
3238 *mipsIV:
3239 *mipsV:
3240 *mips32:
3241 *mips64:
3242 *vr4100:
3243 *vr5000:
3244 *r3900:
3245 {
3246   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3247 }
3248
3249
3250 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3251 "swr r<RT>, <OFFSET>(r<BASE>)"
3252 *mipsI:
3253 *mipsII:
3254 *mipsIII:
3255 *mipsIV:
3256 *mipsV:
3257 *mips32:
3258 *mips64:
3259 *vr4100:
3260 *vr5000:
3261 *r3900:
3262 {
3263   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3264 }
3265
3266
3267 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3268 "sync":STYPE == 0
3269 "sync <STYPE>"
3270 *mipsII:
3271 *mipsIII:
3272 *mipsIV:
3273 *mipsV:
3274 *mips32:
3275 *mips64:
3276 *vr4100:
3277 *vr5000:
3278 *r3900:
3279 {
3280   SyncOperation (STYPE);
3281 }
3282
3283
3284 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3285 "syscall %#lx<CODE>"
3286 *mipsI:
3287 *mipsII:
3288 *mipsIII:
3289 *mipsIV:
3290 *mipsV:
3291 *mips32:
3292 *mips64:
3293 *vr4100:
3294 *vr5000:
3295 *r3900:
3296 {
3297   SignalException (SystemCall, instruction_0);
3298 }
3299
3300
3301 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3302 "teq r<RS>, r<RT>"
3303 *mipsII:
3304 *mipsIII:
3305 *mipsIV:
3306 *mipsV:
3307 *mips32:
3308 *mips64:
3309 *vr4100:
3310 *vr5000:
3311 {
3312   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3313     SignalException (Trap, instruction_0);
3314 }
3315
3316
3317 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3318 "teqi r<RS>, <IMMEDIATE>"
3319 *mipsII:
3320 *mipsIII:
3321 *mipsIV:
3322 *mipsV:
3323 *mips32:
3324 *mips64:
3325 *vr4100:
3326 *vr5000:
3327 {
3328   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3329     SignalException (Trap, instruction_0);
3330 }
3331
3332
3333 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3334 "tge r<RS>, r<RT>"
3335 *mipsII:
3336 *mipsIII:
3337 *mipsIV:
3338 *mipsV:
3339 *mips32:
3340 *mips64:
3341 *vr4100:
3342 *vr5000:
3343 {
3344   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3345     SignalException (Trap, instruction_0);
3346 }
3347
3348
3349 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3350 "tgei r<RS>, <IMMEDIATE>"
3351 *mipsII:
3352 *mipsIII:
3353 *mipsIV:
3354 *mipsV:
3355 *mips32:
3356 *mips64:
3357 *vr4100:
3358 *vr5000:
3359 {
3360   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3361     SignalException (Trap, instruction_0);
3362 }
3363
3364
3365 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3366 "tgeiu r<RS>, <IMMEDIATE>"
3367 *mipsII:
3368 *mipsIII:
3369 *mipsIV:
3370 *mipsV:
3371 *mips32:
3372 *mips64:
3373 *vr4100:
3374 *vr5000:
3375 {
3376   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3377     SignalException (Trap, instruction_0);
3378 }
3379
3380
3381 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3382 "tgeu r<RS>, r<RT>"
3383 *mipsII:
3384 *mipsIII:
3385 *mipsIV:
3386 *mipsV:
3387 *mips32:
3388 *mips64:
3389 *vr4100:
3390 *vr5000:
3391 {
3392   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3393     SignalException (Trap, instruction_0);
3394 }
3395
3396
3397 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3398 "tlt r<RS>, r<RT>"
3399 *mipsII:
3400 *mipsIII:
3401 *mipsIV:
3402 *mipsV:
3403 *mips32:
3404 *mips64:
3405 *vr4100:
3406 *vr5000:
3407 {
3408   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3409     SignalException (Trap, instruction_0);
3410 }
3411
3412
3413 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3414 "tlti r<RS>, <IMMEDIATE>"
3415 *mipsII:
3416 *mipsIII:
3417 *mipsIV:
3418 *mipsV:
3419 *mips32:
3420 *mips64:
3421 *vr4100:
3422 *vr5000:
3423 {
3424   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3425     SignalException (Trap, instruction_0);
3426 }
3427
3428
3429 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3430 "tltiu r<RS>, <IMMEDIATE>"
3431 *mipsII:
3432 *mipsIII:
3433 *mipsIV:
3434 *mipsV:
3435 *mips32:
3436 *mips64:
3437 *vr4100:
3438 *vr5000:
3439 {
3440   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3441     SignalException (Trap, instruction_0);
3442 }
3443
3444
3445 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3446 "tltu r<RS>, r<RT>"
3447 *mipsII:
3448 *mipsIII:
3449 *mipsIV:
3450 *mipsV:
3451 *mips32:
3452 *mips64:
3453 *vr4100:
3454 *vr5000:
3455 {
3456   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3457     SignalException (Trap, instruction_0);
3458 }
3459
3460
3461 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3462 "tne r<RS>, r<RT>"
3463 *mipsII:
3464 *mipsIII:
3465 *mipsIV:
3466 *mipsV:
3467 *mips32:
3468 *mips64:
3469 *vr4100:
3470 *vr5000:
3471 {
3472   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3473     SignalException (Trap, instruction_0);
3474 }
3475
3476
3477 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
3478 "tnei r<RS>, <IMMEDIATE>"
3479 *mipsII:
3480 *mipsIII:
3481 *mipsIV:
3482 *mipsV:
3483 *mips32:
3484 *mips64:
3485 *vr4100:
3486 *vr5000:
3487 {
3488   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
3489     SignalException (Trap, instruction_0);
3490 }
3491
3492
3493 :function:::void:do_xor:int rs, int rt, int rd
3494 {
3495   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3496   GPR[rd] = GPR[rs] ^ GPR[rt];
3497   TRACE_ALU_RESULT (GPR[rd]);
3498 }
3499
3500 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
3501 "xor r<RD>, r<RS>, r<RT>"
3502 *mipsI:
3503 *mipsII:
3504 *mipsIII:
3505 *mipsIV:
3506 *mipsV:
3507 *mips32:
3508 *mips64:
3509 *vr4100:
3510 *vr5000:
3511 *r3900:
3512 {
3513   do_xor (SD_, RS, RT, RD);
3514 }
3515
3516
3517 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
3518 {
3519   TRACE_ALU_INPUT2 (GPR[rs], immediate);
3520   GPR[rt] = GPR[rs] ^ immediate;
3521   TRACE_ALU_RESULT (GPR[rt]);
3522 }
3523
3524 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
3525 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
3526 *mipsI:
3527 *mipsII:
3528 *mipsIII:
3529 *mipsIV:
3530 *mipsV:
3531 *mips32:
3532 *mips64:
3533 *vr4100:
3534 *vr5000:
3535 *r3900:
3536 {
3537   do_xori (SD_, RS, RT, IMMEDIATE);
3538 }
3539
3540 \f
3541 //
3542 // MIPS Architecture:
3543 //
3544 //        FPU Instruction Set (COP1 & COP1X)
3545 //
3546
3547
3548 :%s::::FMT:int fmt
3549 {
3550   switch (fmt)
3551     {
3552     case fmt_single: return "s";
3553     case fmt_double: return "d";
3554     case fmt_word: return "w";
3555     case fmt_long: return "l";
3556     case fmt_ps: return "ps";
3557     default: return "?";
3558     }
3559 }
3560
3561 :%s::::TF:int tf
3562 {
3563   if (tf)
3564     return "t";
3565   else
3566     return "f";
3567 }
3568
3569 :%s::::ND:int nd
3570 {
3571   if (nd)
3572     return "l";
3573   else
3574     return "";
3575 }
3576
3577 :%s::::COND:int cond
3578 {
3579   switch (cond)
3580     {
3581     case 00: return "f";
3582     case 01: return "un";
3583     case 02: return "eq";
3584     case 03: return "ueq";
3585     case 04: return "olt";
3586     case 05: return "ult";
3587     case 06: return "ole";
3588     case 07: return "ule";
3589     case 010: return "sf";
3590     case 011: return "ngle";
3591     case 012: return "seq";
3592     case 013: return "ngl";
3593     case 014: return "lt";
3594     case 015: return "nge";
3595     case 016: return "le";
3596     case 017: return "ngt";
3597     default: return "?";
3598     }
3599 }
3600
3601
3602 // Helpers:
3603 //
3604 // Check that the given FPU format is usable, and signal a
3605 // ReservedInstruction exception if not.
3606 //
3607
3608 // check_fmt checks that the format is single or double.
3609 :function:::void:check_fmt:int fmt, instruction_word insn
3610 *mipsI:
3611 *mipsII:
3612 *mipsIII:
3613 *mipsIV:
3614 *mipsV:
3615 *mips32:
3616 *mips64:
3617 *vr4100:
3618 *vr5000:
3619 *r3900:
3620 {
3621   if ((fmt != fmt_single) && (fmt != fmt_double))
3622     SignalException (ReservedInstruction, insn);
3623 }
3624
3625 // check_fmt_p checks that the format is single, double, or paired single.
3626 :function:::void:check_fmt_p:int fmt, instruction_word insn
3627 *mipsI:
3628 *mipsII:
3629 *mipsIII:
3630 *mipsIV:
3631 *mips32:
3632 *vr4100:
3633 *vr5000:
3634 *r3900:
3635 {
3636   /* None of these ISAs support Paired Single, so just fall back to
3637      the single/double check.  */
3638   check_fmt (SD_, fmt, insn);
3639 }
3640
3641 :function:::void:check_fmt_p:int fmt, instruction_word insn
3642 *mipsV:
3643 *mips64:
3644 {
3645   if ((fmt != fmt_single) && (fmt != fmt_double)
3646       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
3647     SignalException (ReservedInstruction, insn);
3648 }
3649
3650
3651 // Helper:
3652 //
3653 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
3654 // exception if not.
3655 //
3656
3657 :function:::void:check_fpu:
3658 *mipsI:
3659 *mipsII:
3660 *mipsIII:
3661 *mipsIV:
3662 *mipsV:
3663 *mips32:
3664 *mips64:
3665 *vr4100:
3666 *vr5000:
3667 *r3900:
3668 {
3669   if (! COP_Usable (1))
3670     SignalExceptionCoProcessorUnusable (1);
3671 }
3672
3673
3674 // Helper:
3675 //
3676 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
3677 // or MIPS32.  do_load cannot be used instead because it returns an
3678 // unsigned_word, which is limited to the size of the machine's registers.
3679 //
3680
3681 :function:::unsigned64:do_load_double:address_word base, address_word offset
3682 *mipsII:
3683 *mips32:
3684 {
3685   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3686   address_word vaddr;
3687   address_word paddr;
3688   int uncached;
3689   unsigned64 memval;
3690   unsigned64 v;
3691
3692   vaddr = loadstore_ea (SD_, base, offset);
3693   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3694     {
3695       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
3696                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
3697                        sim_core_unaligned_signal);
3698     }
3699   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
3700                       isREAL);
3701   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
3702               isDATA, isREAL);
3703   v = (unsigned64)memval;
3704   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
3705               isDATA, isREAL);
3706   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
3707 }
3708
3709
3710 // Helper:
3711 //
3712 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
3713 // or MIPS32.  do_load cannot be used instead because it returns an
3714 // unsigned_word, which is limited to the size of the machine's registers.
3715 //
3716
3717 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
3718 *mipsII:
3719 *mips32:
3720 {
3721   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
3722   address_word vaddr;
3723   address_word paddr;
3724   int uncached;
3725   unsigned64 memval;
3726
3727   vaddr = loadstore_ea (SD_, base, offset);
3728   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
3729     {
3730       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
3731                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
3732                        sim_core_unaligned_signal);
3733     }
3734   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
3735                       isREAL);
3736   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
3737   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
3738                isREAL);
3739   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
3740   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
3741                isREAL);
3742 }
3743
3744
3745 010001,10,3.FMT,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
3746 "abs.%s<FMT> f<FD>, f<FS>"
3747 *mipsI:
3748 *mipsII:
3749 *mipsIII:
3750 *mipsIV:
3751 *mipsV:
3752 *mips32:
3753 *mips64:
3754 *vr4100:
3755 *vr5000:
3756 *r3900:
3757 {
3758   int fmt = FMT;
3759   check_fpu (SD_);
3760   check_fmt_p (SD_, fmt, instruction_0);
3761   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
3762 }
3763
3764
3765
3766 010001,10,3.FMT,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
3767 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
3768 *mipsI:
3769 *mipsII:
3770 *mipsIII:
3771 *mipsIV:
3772 *mipsV:
3773 *mips32:
3774 *mips64:
3775 *vr4100:
3776 *vr5000:
3777 *r3900:
3778 {
3779   int fmt = FMT;
3780   check_fpu (SD_);
3781   check_fmt_p (SD_, fmt, instruction_0);
3782   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
3783 }
3784
3785
3786 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
3787 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
3788 *mipsV:
3789 *mips64:
3790 {
3791   unsigned64 fs;
3792   unsigned64 ft;
3793   unsigned64 fd;
3794   check_fpu (SD_);
3795   check_u64 (SD_, instruction_0);
3796   fs = ValueFPR (FS, fmt_ps);
3797   if ((GPR[RS] & 0x3) != 0)
3798     Unpredictable ();
3799   if ((GPR[RS] & 0x4) == 0)
3800     fd = fs;
3801   else
3802     {
3803       ft = ValueFPR (FT, fmt_ps);
3804       if (BigEndianCPU)
3805         fd = PackPS (PSLower (fs), PSUpper (ft));
3806       else
3807         fd = PackPS (PSLower (ft), PSUpper (fs));
3808     }
3809   StoreFPR (FD, fmt_ps, fd);
3810 }
3811
3812
3813 // BC1F
3814 // BC1FL
3815 // BC1T
3816 // BC1TL
3817
3818 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
3819 "bc1%s<TF>%s<ND> <OFFSET>"
3820 *mipsI:
3821 *mipsII:
3822 *mipsIII:
3823 {
3824   check_fpu (SD_);
3825   TRACE_BRANCH_INPUT (PREVCOC1());
3826   if (PREVCOC1() == TF)
3827     {
3828       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3829       TRACE_BRANCH_RESULT (dest);
3830       DELAY_SLOT (dest);
3831     }
3832   else if (ND)
3833     {
3834       TRACE_BRANCH_RESULT (0);
3835       NULLIFY_NEXT_INSTRUCTION ();
3836     }
3837   else
3838     {
3839       TRACE_BRANCH_RESULT (NIA);
3840     }
3841 }
3842
3843 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
3844 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
3845 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
3846 *mipsIV:
3847 *mipsV:
3848 *mips32:
3849 *mips64:
3850 #*vr4100:
3851 *vr5000:
3852 *r3900:
3853 {
3854   check_fpu (SD_);
3855   if (GETFCC(CC) == TF)
3856     {
3857       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
3858       DELAY_SLOT (dest);
3859     }
3860   else if (ND)
3861     {
3862       NULLIFY_NEXT_INSTRUCTION ();
3863     }
3864 }
3865
3866
3867 010001,10,3.FMT,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
3868 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
3869 *mipsI:
3870 *mipsII:
3871 *mipsIII:
3872 {
3873   int fmt = FMT;
3874   check_fpu (SD_);
3875   check_fmt_p (SD_, fmt, instruction_0);
3876   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
3877   TRACE_ALU_RESULT (ValueFCR (31));
3878 }
3879
3880 010001,10,3.FMT,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
3881 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
3882 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
3883 *mipsIV:
3884 *mipsV:
3885 *mips32:
3886 *mips64:
3887 *vr4100:
3888 *vr5000:
3889 *r3900:
3890 {
3891   int fmt = FMT;
3892   check_fpu (SD_);
3893   check_fmt_p (SD_, fmt, instruction_0);
3894   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
3895   TRACE_ALU_RESULT (ValueFCR (31));
3896 }
3897
3898
3899 010001,10,3.FMT,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
3900 "ceil.l.%s<FMT> f<FD>, f<FS>"
3901 *mipsIII:
3902 *mipsIV:
3903 *mipsV:
3904 *mips64:
3905 *vr4100:
3906 *vr5000:
3907 *r3900:
3908 {
3909   int fmt = FMT;
3910   check_fpu (SD_);
3911   check_fmt (SD_, fmt, instruction_0);
3912   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3913             fmt_long));
3914 }
3915
3916
3917 010001,10,3.FMT,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
3918 "ceil.w.%s<FMT> f<FD>, f<FS>"
3919 *mipsII:
3920 *mipsIII:
3921 *mipsIV:
3922 *mipsV:
3923 *mips32:
3924 *mips64:
3925 *vr4100:
3926 *vr5000:
3927 *r3900:
3928 {
3929   int fmt = FMT;
3930   check_fpu (SD_);
3931   check_fmt (SD_, fmt, instruction_0);
3932   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
3933             fmt_word));
3934 }
3935
3936
3937 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
3938 "cfc1 r<RT>, f<FS>"
3939 *mipsI:
3940 *mipsII:
3941 *mipsIII:
3942 {
3943   check_fpu (SD_);
3944   if (FS == 0)
3945     PENDING_FILL (RT, EXTEND32 (FCR0));
3946   else if (FS == 31)
3947     PENDING_FILL (RT, EXTEND32 (FCR31));
3948   /* else NOP */
3949 }
3950
3951 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
3952 "cfc1 r<RT>, f<FS>"
3953 *mipsIV:
3954 *vr4100:
3955 *vr5000:
3956 *r3900:
3957 {
3958   check_fpu (SD_);
3959   if (FS == 0 || FS == 31)
3960     {
3961       unsigned_word  fcr = ValueFCR (FS);
3962       TRACE_ALU_INPUT1 (fcr);
3963       GPR[RT] = fcr;
3964     }
3965   /* else NOP */
3966   TRACE_ALU_RESULT (GPR[RT]);
3967 }
3968
3969 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
3970 "cfc1 r<RT>, f<FS>"
3971 *mipsV:
3972 *mips32:
3973 *mips64:
3974 {
3975   check_fpu (SD_);
3976   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
3977     {
3978       unsigned_word  fcr = ValueFCR (FS);
3979       TRACE_ALU_INPUT1 (fcr);
3980       GPR[RT] = fcr;
3981     }
3982   /* else NOP */
3983   TRACE_ALU_RESULT (GPR[RT]);
3984 }
3985
3986 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
3987 "ctc1 r<RT>, f<FS>"
3988 *mipsI:
3989 *mipsII:
3990 *mipsIII:
3991 {
3992   check_fpu (SD_);
3993   if (FS == 31)
3994     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
3995   /* else NOP */
3996 }
3997
3998 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
3999 "ctc1 r<RT>, f<FS>"
4000 *mipsIV:
4001 *vr4100:
4002 *vr5000:
4003 *r3900:
4004 {
4005   check_fpu (SD_);
4006   TRACE_ALU_INPUT1 (GPR[RT]);
4007   if (FS == 31)
4008     StoreFCR (FS, GPR[RT]);
4009   /* else NOP */
4010 }
4011
4012 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4013 "ctc1 r<RT>, f<FS>"
4014 *mipsV:
4015 *mips32:
4016 *mips64:
4017 {
4018   check_fpu (SD_);
4019   TRACE_ALU_INPUT1 (GPR[RT]);
4020   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4021       StoreFCR (FS, GPR[RT]);
4022   /* else NOP */
4023 }
4024
4025
4026 //
4027 // FIXME: Does not correctly differentiate between mips*
4028 //
4029 010001,10,3.FMT,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4030 "cvt.d.%s<FMT> f<FD>, f<FS>"
4031 *mipsI:
4032 *mipsII:
4033 *mipsIII:
4034 *mipsIV:
4035 *mipsV:
4036 *mips32:
4037 *mips64:
4038 *vr4100:
4039 *vr5000:
4040 *r3900:
4041 {
4042   int fmt = FMT;
4043   check_fpu (SD_);
4044   if ((fmt == fmt_double) | 0)
4045     SignalException (ReservedInstruction, instruction_0);
4046   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4047             fmt_double));
4048 }
4049
4050
4051 010001,10,3.FMT,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4052 "cvt.l.%s<FMT> f<FD>, f<FS>"
4053 *mipsIII:
4054 *mipsIV:
4055 *mipsV:
4056 *mips64:
4057 *vr4100:
4058 *vr5000:
4059 *r3900:
4060 {
4061   int fmt = FMT;
4062   check_fpu (SD_);
4063   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4064     SignalException (ReservedInstruction, instruction_0);
4065   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4066             fmt_long));
4067 }
4068
4069
4070 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4071 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4072 *mipsV:
4073 *mips64:
4074 {
4075   check_fpu (SD_);
4076   check_u64 (SD_, instruction_0);
4077   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4078                                 ValueFPR (FT, fmt_single)));
4079 }
4080
4081
4082 //
4083 // FIXME: Does not correctly differentiate between mips*
4084 //
4085 010001,10,3.FMT!6,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4086 "cvt.s.%s<FMT> f<FD>, f<FS>"
4087 *mipsI:
4088 *mipsII:
4089 *mipsIII:
4090 *mipsIV:
4091 *mipsV:
4092 *mips32:
4093 *mips64:
4094 *vr4100:
4095 *vr5000:
4096 *r3900:
4097 {
4098   int fmt = FMT;
4099   check_fpu (SD_);
4100   if ((fmt == fmt_single) | 0)
4101     SignalException (ReservedInstruction, instruction_0);
4102   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4103             fmt_single));
4104 }
4105
4106
4107 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4108 "cvt.s.pl f<FD>, f<FS>"
4109 *mipsV:
4110 *mips64:
4111 {
4112   check_fpu (SD_);
4113   check_u64 (SD_, instruction_0);
4114   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4115 }
4116
4117
4118 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4119 "cvt.s.pu f<FD>, f<FS>"
4120 *mipsV:
4121 *mips64:
4122 {
4123   check_fpu (SD_);
4124   check_u64 (SD_, instruction_0);
4125   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4126 }
4127
4128
4129 010001,10,3.FMT!6,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4130 "cvt.w.%s<FMT> f<FD>, f<FS>"
4131 *mipsI:
4132 *mipsII:
4133 *mipsIII:
4134 *mipsIV:
4135 *mipsV:
4136 *mips32:
4137 *mips64:
4138 *vr4100:
4139 *vr5000:
4140 *r3900:
4141 {
4142   int fmt = FMT;
4143   check_fpu (SD_);
4144   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4145     SignalException (ReservedInstruction, instruction_0);
4146   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4147             fmt_word));
4148 }
4149
4150
4151 010001,10,3.FMT,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4152 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4153 *mipsI:
4154 *mipsII:
4155 *mipsIII:
4156 *mipsIV:
4157 *mipsV:
4158 *mips32:
4159 *mips64:
4160 *vr4100:
4161 *vr5000:
4162 *r3900:
4163 {
4164   int fmt = FMT;
4165   check_fpu (SD_);
4166   check_fmt (SD_, fmt, instruction_0);
4167   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4168 }
4169
4170
4171 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4172 "dmfc1 r<RT>, f<FS>"
4173 *mipsIII:
4174 {
4175   unsigned64 v;
4176   check_fpu (SD_);
4177   check_u64 (SD_, instruction_0);
4178   if (SizeFGR () == 64)
4179     v = FGR[FS];
4180   else if ((FS & 0x1) == 0)
4181     v = SET64HI (FGR[FS+1]) | FGR[FS];
4182   else
4183     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4184   PENDING_FILL (RT, v);
4185   TRACE_ALU_RESULT (v);
4186 }
4187
4188 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4189 "dmfc1 r<RT>, f<FS>"
4190 *mipsIV:
4191 *mipsV:
4192 *mips64:
4193 *vr4100:
4194 *vr5000:
4195 *r3900:
4196 {
4197   check_fpu (SD_);
4198   check_u64 (SD_, instruction_0);
4199   if (SizeFGR () == 64)
4200     GPR[RT] = FGR[FS];
4201   else if ((FS & 0x1) == 0)
4202     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4203   else
4204     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4205   TRACE_ALU_RESULT (GPR[RT]);
4206 }
4207
4208
4209 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4210 "dmtc1 r<RT>, f<FS>"
4211 *mipsIII:
4212 {
4213   unsigned64 v;
4214   check_fpu (SD_);
4215   check_u64 (SD_, instruction_0);
4216   if (SizeFGR () == 64)
4217     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4218   else if ((FS & 0x1) == 0)
4219     {
4220       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4221       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4222     }
4223   else
4224     Unpredictable ();
4225   TRACE_FP_RESULT (GPR[RT]);
4226 }
4227
4228 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4229 "dmtc1 r<RT>, f<FS>"
4230 *mipsIV:
4231 *mipsV:
4232 *mips64:
4233 *vr4100:
4234 *vr5000:
4235 *r3900:
4236 {
4237   check_fpu (SD_);
4238   check_u64 (SD_, instruction_0);
4239   if (SizeFGR () == 64)
4240     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4241   else if ((FS & 0x1) == 0)
4242     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4243   else
4244     Unpredictable ();
4245 }
4246
4247
4248 010001,10,3.FMT,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4249 "floor.l.%s<FMT> f<FD>, f<FS>"
4250 *mipsIII:
4251 *mipsIV:
4252 *mipsV:
4253 *mips64:
4254 *vr4100:
4255 *vr5000:
4256 *r3900:
4257 {
4258   int fmt = FMT;
4259   check_fpu (SD_);
4260   check_fmt (SD_, fmt, instruction_0);
4261   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4262             fmt_long));
4263 }
4264
4265
4266 010001,10,3.FMT,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4267 "floor.w.%s<FMT> f<FD>, f<FS>"
4268 *mipsII:
4269 *mipsIII:
4270 *mipsIV:
4271 *mipsV:
4272 *mips32:
4273 *mips64:
4274 *vr4100:
4275 *vr5000:
4276 *r3900:
4277 {
4278   int fmt = FMT;
4279   check_fpu (SD_);
4280   check_fmt (SD_, fmt, instruction_0);
4281   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4282             fmt_word));
4283 }
4284
4285
4286 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4287 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4288 *mipsII:
4289 *mips32:
4290 {
4291   check_fpu (SD_);
4292   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4293 }
4294
4295
4296 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4297 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4298 *mipsIII:
4299 *mipsIV:
4300 *mipsV:
4301 *mips64:
4302 *vr4100:
4303 *vr5000:
4304 *r3900:
4305 {
4306   check_fpu (SD_);
4307   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4308 }
4309
4310
4311 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4312 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4313 *mipsIV:
4314 *mipsV:
4315 *mips64:
4316 *vr5000:
4317 {
4318   check_fpu (SD_);
4319   check_u64 (SD_, instruction_0);
4320   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4321 }
4322
4323
4324 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4325 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4326 *mipsV:
4327 *mips64:
4328 {
4329   address_word base = GPR[BASE];
4330   address_word index = GPR[INDEX];
4331   address_word vaddr = base + index;
4332   check_fpu (SD_);
4333   check_u64 (SD_, instruction_0);
4334   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4335   if ((vaddr & 0x7) != 0)
4336     index -= (vaddr & 0x7);
4337   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4338 }
4339
4340
4341 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4342 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4343 *mipsI:
4344 *mipsII:
4345 *mipsIII:
4346 *mipsIV:
4347 *mipsV:
4348 *mips32:
4349 *mips64:
4350 *vr4100:
4351 *vr5000:
4352 *r3900:
4353 {
4354   check_fpu (SD_);
4355   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4356 }
4357
4358
4359 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4360 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4361 *mipsIV:
4362 *mipsV:
4363 *mips64:
4364 *vr5000:
4365 {
4366   check_fpu (SD_);
4367   check_u64 (SD_, instruction_0);
4368   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4369 }
4370
4371
4372
4373 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT:COP1X:64,f::MADD.fmt
4374 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4375 *mipsIV:
4376 *mipsV:
4377 *mips64:
4378 *vr5000:
4379 {
4380   int fmt = FMT;
4381   check_fpu (SD_);
4382   check_u64 (SD_, instruction_0);
4383   check_fmt_p (SD_, fmt, instruction_0);
4384   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4385                                   ValueFPR (FR, fmt), fmt));
4386 }
4387
4388
4389 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4390 "mfc1 r<RT>, f<FS>"
4391 *mipsI:
4392 *mipsII:
4393 *mipsIII:
4394 {
4395   unsigned64 v;
4396   check_fpu (SD_);
4397   v = EXTEND32 (FGR[FS]);
4398   PENDING_FILL (RT, v);
4399   TRACE_ALU_RESULT (v);
4400 }
4401
4402 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4403 "mfc1 r<RT>, f<FS>"
4404 *mipsIV:
4405 *mipsV:
4406 *mips32:
4407 *mips64:
4408 *vr4100:
4409 *vr5000:
4410 *r3900:
4411 {
4412   check_fpu (SD_);
4413   GPR[RT] = EXTEND32 (FGR[FS]);
4414   TRACE_ALU_RESULT (GPR[RT]);
4415 }
4416
4417
4418 010001,10,3.FMT,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4419 "mov.%s<FMT> f<FD>, f<FS>"
4420 *mipsI:
4421 *mipsII:
4422 *mipsIII:
4423 *mipsIV:
4424 *mipsV:
4425 *mips32:
4426 *mips64:
4427 *vr4100:
4428 *vr5000:
4429 *r3900:
4430 {
4431   int fmt = FMT;
4432   check_fpu (SD_);
4433   check_fmt_p (SD_, fmt, instruction_0);
4434   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4435 }
4436
4437
4438 // MOVF
4439 // MOVT
4440 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
4441 "mov%s<TF> r<RD>, r<RS>, <CC>"
4442 *mipsIV:
4443 *mipsV:
4444 *mips32:
4445 *mips64:
4446 *vr5000:
4447 {
4448   check_fpu (SD_);
4449   if (GETFCC(CC) == TF)
4450     GPR[RD] = GPR[RS];
4451 }
4452
4453
4454 // MOVF.fmt
4455 // MOVT.fmt
4456 010001,10,3.FMT,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
4457 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
4458 *mipsIV:
4459 *mipsV:
4460 *mips32:
4461 *mips64:
4462 *vr5000:
4463 {
4464   int fmt = FMT;
4465   check_fpu (SD_);
4466   if (fmt != fmt_ps)
4467     {
4468       if (GETFCC(CC) == TF)
4469         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
4470       else
4471         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
4472     }
4473   else
4474     {
4475       unsigned64 fd;
4476       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
4477                                       fmt_ps)),
4478                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
4479                                       fmt_ps)));
4480       StoreFPR (FD, fmt_ps, fd);
4481     }
4482 }
4483
4484
4485 010001,10,3.FMT,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
4486 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
4487 *mipsIV:
4488 *mipsV:
4489 *mips32:
4490 *mips64:
4491 *vr5000:
4492 {
4493   check_fpu (SD_);
4494   if (GPR[RT] != 0)
4495     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4496   else
4497     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4498 }
4499
4500
4501 // MOVT see MOVtf
4502
4503
4504 // MOVT.fmt see MOVtf.fmt
4505
4506
4507
4508 010001,10,3.FMT,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
4509 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
4510 *mipsIV:
4511 *mipsV:
4512 *mips32:
4513 *mips64:
4514 *vr5000:
4515 {
4516   check_fpu (SD_);
4517   if (GPR[RT] == 0)
4518     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
4519   else
4520     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
4521 }
4522
4523
4524 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT:COP1X:64,f::MSUB.fmt
4525 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4526 *mipsIV:
4527 *mipsV:
4528 *mips64:
4529 *vr5000:
4530 {
4531   int fmt = FMT;
4532   check_fpu (SD_);
4533   check_u64 (SD_, instruction_0);
4534   check_fmt_p (SD_, fmt, instruction_0);
4535   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4536                                   ValueFPR (FR, fmt), fmt));
4537 }
4538
4539
4540 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
4541 "mtc1 r<RT>, f<FS>"
4542 *mipsI:
4543 *mipsII:
4544 *mipsIII:
4545 {
4546   check_fpu (SD_);
4547   if (SizeFGR () == 64)
4548     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
4549   else
4550     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4551   TRACE_FP_RESULT (GPR[RT]);
4552 }
4553
4554 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
4555 "mtc1 r<RT>, f<FS>"
4556 *mipsIV:
4557 *mipsV:
4558 *mips32:
4559 *mips64:
4560 *vr4100:
4561 *vr5000:
4562 *r3900:
4563 {
4564   check_fpu (SD_);
4565   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
4566 }
4567
4568
4569 010001,10,3.FMT,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
4570 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
4571 *mipsI:
4572 *mipsII:
4573 *mipsIII:
4574 *mipsIV:
4575 *mipsV:
4576 *mips32:
4577 *mips64:
4578 *vr4100:
4579 *vr5000:
4580 *r3900:
4581 {
4582   int fmt = FMT;
4583   check_fpu (SD_);
4584   check_fmt_p (SD_, fmt, instruction_0);
4585   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4586 }
4587
4588
4589 010001,10,3.FMT,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
4590 "neg.%s<FMT> f<FD>, f<FS>"
4591 *mipsI:
4592 *mipsII:
4593 *mipsIII:
4594 *mipsIV:
4595 *mipsV:
4596 *mips32:
4597 *mips64:
4598 *vr4100:
4599 *vr5000:
4600 *r3900:
4601 {
4602   int fmt = FMT;
4603   check_fpu (SD_);
4604   check_fmt_p (SD_, fmt, instruction_0);
4605   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
4606 }
4607
4608
4609 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT:COP1X:64,f::NMADD.fmt
4610 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4611 *mipsIV:
4612 *mipsV:
4613 *mips64:
4614 *vr5000:
4615 {
4616   int fmt = FMT;
4617   check_fpu (SD_);
4618   check_u64 (SD_, instruction_0);
4619   check_fmt_p (SD_, fmt, instruction_0);
4620   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4621                                      ValueFPR (FR, fmt), fmt));
4622 }
4623
4624
4625 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT:COP1X:64,f::NMSUB.fmt
4626 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4627 *mipsIV:
4628 *mipsV:
4629 *mips64:
4630 *vr5000:
4631 {
4632   int fmt = FMT;
4633   check_fpu (SD_);
4634   check_u64 (SD_, instruction_0);
4635   check_fmt_p (SD_, fmt, instruction_0);
4636   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4637                                      ValueFPR (FR, fmt), fmt));
4638 }
4639
4640
4641 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
4642 "pll.ps f<FD>, f<FS>, f<FT>"
4643 *mipsV:
4644 *mips64:
4645 {
4646   check_fpu (SD_);
4647   check_u64 (SD_, instruction_0);
4648   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4649                                 PSLower (ValueFPR (FT, fmt_ps))));
4650 }
4651
4652
4653 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
4654 "plu.ps f<FD>, f<FS>, f<FT>"
4655 *mipsV:
4656 *mips64:
4657 {
4658   check_fpu (SD_);
4659   check_u64 (SD_, instruction_0);
4660   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
4661                                 PSUpper (ValueFPR (FT, fmt_ps))));
4662 }
4663
4664
4665 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
4666 "prefx <HINT>, r<INDEX>(r<BASE>)"
4667 *mipsIV:
4668 *mipsV:
4669 *mips64:
4670 *vr5000:
4671 {
4672   address_word base = GPR[BASE];
4673   address_word index = GPR[INDEX];
4674   {
4675     address_word vaddr = loadstore_ea (SD_, base, index);
4676     address_word paddr;
4677     int uncached;
4678     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
4679       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
4680   }
4681 }
4682
4683
4684 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
4685 "pul.ps f<FD>, f<FS>, f<FT>"
4686 *mipsV:
4687 *mips64:
4688 {
4689   check_fpu (SD_);
4690   check_u64 (SD_, instruction_0);
4691   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4692                                 PSLower (ValueFPR (FT, fmt_ps))));
4693 }
4694
4695
4696 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
4697 "puu.ps f<FD>, f<FS>, f<FT>"
4698 *mipsV:
4699 *mips64:
4700 {
4701   check_fpu (SD_);
4702   check_u64 (SD_, instruction_0);
4703   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
4704                                 PSUpper (ValueFPR (FT, fmt_ps))));
4705 }
4706
4707
4708 010001,10,3.FMT,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
4709 "recip.%s<FMT> f<FD>, f<FS>"
4710 *mipsIV:
4711 *mipsV:
4712 *mips64:
4713 *vr5000:
4714 {
4715   int fmt = FMT;
4716   check_fpu (SD_);
4717   check_fmt (SD_, fmt, instruction_0);
4718   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
4719 }
4720
4721
4722 010001,10,3.FMT,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
4723 "round.l.%s<FMT> f<FD>, f<FS>"
4724 *mipsIII:
4725 *mipsIV:
4726 *mipsV:
4727 *mips64:
4728 *vr4100:
4729 *vr5000:
4730 *r3900:
4731 {
4732   int fmt = FMT;
4733   check_fpu (SD_);
4734   check_fmt (SD_, fmt, instruction_0);
4735   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4736             fmt_long));
4737 }
4738
4739
4740 010001,10,3.FMT,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
4741 "round.w.%s<FMT> f<FD>, f<FS>"
4742 *mipsII:
4743 *mipsIII:
4744 *mipsIV:
4745 *mipsV:
4746 *mips32:
4747 *mips64:
4748 *vr4100:
4749 *vr5000:
4750 *r3900:
4751 {
4752   int fmt = FMT;
4753   check_fpu (SD_);
4754   check_fmt (SD_, fmt, instruction_0);
4755   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
4756             fmt_word));
4757 }
4758
4759
4760 010001,10,3.FMT,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
4761 "rsqrt.%s<FMT> f<FD>, f<FS>"
4762 *mipsIV:
4763 *mipsV:
4764 *mips64:
4765 *vr5000:
4766 {
4767   int fmt = FMT;
4768   check_fpu (SD_);
4769   check_fmt (SD_, fmt, instruction_0);
4770   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
4771 }
4772
4773
4774 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
4775 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4776 *mipsII:
4777 *mips32:
4778 {
4779   check_fpu (SD_);
4780   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4781 }
4782
4783
4784 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
4785 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
4786 *mipsIII:
4787 *mipsIV:
4788 *mipsV:
4789 *mips64:
4790 *vr4100:
4791 *vr5000:
4792 *r3900:
4793 {
4794   check_fpu (SD_);
4795   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
4796 }
4797
4798
4799 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
4800 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
4801 *mipsIV:
4802 *mipsV:
4803 *mips64:
4804 *vr5000:
4805 {
4806   check_fpu (SD_);
4807   check_u64 (SD_, instruction_0);
4808   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
4809 }
4810
4811
4812 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
4813 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
4814 *mipsV:
4815 *mips64:
4816 {
4817   unsigned64 v;
4818   address_word base = GPR[BASE];
4819   address_word index = GPR[INDEX];
4820   address_word vaddr = base + index;
4821   check_fpu (SD_);
4822   check_u64 (SD_, instruction_0);
4823   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4824   if ((vaddr & 0x7) != 0)
4825     index -= (vaddr & 0x7);
4826   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
4827 }
4828
4829
4830 010001,10,3.FMT,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
4831 "sqrt.%s<FMT> f<FD>, f<FS>"
4832 *mipsII:
4833 *mipsIII:
4834 *mipsIV:
4835 *mipsV:
4836 *mips32:
4837 *mips64:
4838 *vr4100:
4839 *vr5000:
4840 *r3900:
4841 {
4842   int fmt = FMT;
4843   check_fpu (SD_);
4844   check_fmt (SD_, fmt, instruction_0);
4845   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
4846 }
4847
4848
4849 010001,10,3.FMT,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
4850 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
4851 *mipsI:
4852 *mipsII:
4853 *mipsIII:
4854 *mipsIV:
4855 *mipsV:
4856 *mips32:
4857 *mips64:
4858 *vr4100:
4859 *vr5000:
4860 *r3900:
4861 {
4862   int fmt = FMT;
4863   check_fpu (SD_);
4864   check_fmt_p (SD_, fmt, instruction_0);
4865   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4866 }
4867
4868
4869
4870 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
4871 "swc1 f<FT>, <OFFSET>(r<BASE>)"
4872 *mipsI:
4873 *mipsII:
4874 *mipsIII:
4875 *mipsIV:
4876 *mipsV:
4877 *mips32:
4878 *mips64:
4879 *vr4100:
4880 *vr5000:
4881 *r3900:
4882 {
4883   address_word base = GPR[BASE];
4884   address_word offset = EXTEND16 (OFFSET);
4885   check_fpu (SD_);
4886   {
4887     address_word vaddr = loadstore_ea (SD_, base, offset);
4888     address_word paddr;
4889     int uncached;
4890     if ((vaddr & 3) != 0)
4891       {
4892         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
4893       }
4894     else
4895       {
4896         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4897           {
4898             uword64 memval = 0;
4899             uword64 memval1 = 0;
4900             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
4901             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
4902             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
4903             unsigned int byte;
4904             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
4905             byte = ((vaddr & mask) ^ bigendiancpu);
4906             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
4907             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4908           }
4909       }
4910   }
4911 }
4912
4913
4914 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
4915 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
4916 *mipsIV:
4917 *mipsV:
4918 *mips64:
4919 *vr5000:
4920 {
4921
4922   address_word base = GPR[BASE];
4923   address_word index = GPR[INDEX];
4924   check_fpu (SD_);
4925   check_u64 (SD_, instruction_0);
4926   {
4927    address_word vaddr = loadstore_ea (SD_, base, index);
4928    address_word paddr;
4929    int uncached;
4930    if ((vaddr & 3) != 0)
4931      {
4932        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
4933      }
4934    else
4935    {
4936     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
4937     {
4938      unsigned64 memval = 0;
4939      unsigned64 memval1 = 0;
4940      unsigned64 mask = 0x7;
4941      unsigned int byte;
4942      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
4943      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
4944      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
4945       {
4946        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
4947       }
4948     }
4949    }
4950   }
4951 }
4952
4953
4954 010001,10,3.FMT,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
4955 "trunc.l.%s<FMT> f<FD>, f<FS>"
4956 *mipsIII:
4957 *mipsIV:
4958 *mipsV:
4959 *mips64:
4960 *vr4100:
4961 *vr5000:
4962 *r3900:
4963 {
4964   int fmt = FMT;
4965   check_fpu (SD_);
4966   check_fmt (SD_, fmt, instruction_0);
4967   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4968             fmt_long));
4969 }
4970
4971
4972 010001,10,3.FMT,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
4973 "trunc.w.%s<FMT> f<FD>, f<FS>"
4974 *mipsII:
4975 *mipsIII:
4976 *mipsIV:
4977 *mipsV:
4978 *mips32:
4979 *mips64:
4980 *vr4100:
4981 *vr5000:
4982 *r3900:
4983 {
4984   int fmt = FMT;
4985   check_fpu (SD_);
4986   check_fmt (SD_, fmt, instruction_0);
4987   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
4988             fmt_word));
4989 }
4990
4991 \f
4992 //
4993 // MIPS Architecture:
4994 //
4995 //        System Control Instruction Set (COP0)
4996 //
4997
4998
4999 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5000 "bc0f <OFFSET>"
5001 *mipsI:
5002 *mipsII:
5003 *mipsIII:
5004 *mipsIV:
5005 *mipsV:
5006 *mips32:
5007 *mips64:
5008 *vr4100:
5009 *vr5000:
5010
5011 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5012 "bc0f <OFFSET>"
5013 // stub needed for eCos as tx39 hardware bug workaround
5014 *r3900:
5015 {
5016   /* do nothing */
5017 }
5018
5019
5020 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5021 "bc0fl <OFFSET>"
5022 *mipsI:
5023 *mipsII:
5024 *mipsIII:
5025 *mipsIV:
5026 *mipsV:
5027 *mips32:
5028 *mips64:
5029 *vr4100:
5030 *vr5000:
5031
5032
5033 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5034 "bc0t <OFFSET>"
5035 *mipsI:
5036 *mipsII:
5037 *mipsIII:
5038 *mipsIV:
5039 *mipsV:
5040 *mips32:
5041 *mips64:
5042 *vr4100:
5043
5044
5045 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5046 "bc0tl <OFFSET>"
5047 *mipsI:
5048 *mipsII:
5049 *mipsIII:
5050 *mipsIV:
5051 *mipsV:
5052 *mips32:
5053 *mips64:
5054 *vr4100:
5055 *vr5000:
5056
5057
5058 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5059 "cache <OP>, <OFFSET>(r<BASE>)"
5060 *mipsIII:
5061 *mipsIV:
5062 *mipsV:
5063 *mips32:
5064 *mips64:
5065 *vr4100:
5066 *vr5000:
5067 *r3900:
5068 {
5069   address_word base = GPR[BASE];
5070   address_word offset = EXTEND16 (OFFSET);
5071   {
5072     address_word vaddr = loadstore_ea (SD_, base, offset);
5073     address_word paddr;
5074     int uncached;
5075     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5076       CacheOp(OP,vaddr,paddr,instruction_0);
5077   }
5078 }
5079
5080
5081 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5082 "dmfc0 r<RT>, r<RD>"
5083 *mipsIII:
5084 *mipsIV:
5085 *mipsV:
5086 *mips64:
5087 {
5088   check_u64 (SD_, instruction_0);
5089   DecodeCoproc (instruction_0);
5090 }
5091
5092
5093 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5094 "dmtc0 r<RT>, r<RD>"
5095 *mipsIII:
5096 *mipsIV:
5097 *mipsV:
5098 *mips64:
5099 {
5100   check_u64 (SD_, instruction_0);
5101   DecodeCoproc (instruction_0);
5102 }
5103
5104
5105 010000,1,0000000000000000000,011000:COP0:32::ERET
5106 "eret"
5107 *mipsIII:
5108 *mipsIV:
5109 *mipsV:
5110 *mips32:
5111 *mips64:
5112 *vr4100:
5113 *vr5000:
5114 {
5115   if (SR & status_ERL)
5116     {
5117       /* Oops, not yet available */
5118       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5119       NIA = EPC;
5120       SR &= ~status_ERL;
5121     }
5122   else
5123     {
5124       NIA = EPC;
5125       SR &= ~status_EXL;
5126     }
5127 }
5128
5129
5130 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5131 "mfc0 r<RT>, r<RD> # <REGX>"
5132 *mipsI:
5133 *mipsII:
5134 *mipsIII:
5135 *mipsIV:
5136 *mipsV:
5137 *mips32:
5138 *mips64:
5139 *vr4100:
5140 *vr5000:
5141 *r3900:
5142 {
5143   TRACE_ALU_INPUT0 ();
5144   DecodeCoproc (instruction_0);
5145   TRACE_ALU_RESULT (GPR[RT]);
5146 }
5147
5148 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5149 "mtc0 r<RT>, r<RD> # <REGX>"
5150 *mipsI:
5151 *mipsII:
5152 *mipsIII:
5153 *mipsIV:
5154 *mipsV:
5155 *mips32:
5156 *mips64:
5157 *vr4100:
5158 *vr5000:
5159 *r3900:
5160 {
5161   DecodeCoproc (instruction_0);
5162 }
5163
5164
5165 010000,1,0000000000000000000,010000:COP0:32::RFE
5166 "rfe"
5167 *mipsI:
5168 *mipsII:
5169 *mipsIII:
5170 *mipsIV:
5171 *mipsV:
5172 *vr4100:
5173 *vr5000:
5174 *r3900:
5175 {
5176   DecodeCoproc (instruction_0);
5177 }
5178
5179
5180 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5181 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5182 *mipsI:
5183 *mipsII:
5184 *mipsIII:
5185 *mipsIV:
5186 *mipsV:
5187 *mips32:
5188 *mips64:
5189 *vr4100:
5190 *r3900:
5191 {
5192   DecodeCoproc (instruction_0);
5193 }
5194
5195
5196
5197 010000,1,0000000000000000000,001000:COP0:32::TLBP
5198 "tlbp"
5199 *mipsI:
5200 *mipsII:
5201 *mipsIII:
5202 *mipsIV:
5203 *mipsV:
5204 *mips32:
5205 *mips64:
5206 *vr4100:
5207 *vr5000:
5208
5209
5210 010000,1,0000000000000000000,000001:COP0:32::TLBR
5211 "tlbr"
5212 *mipsI:
5213 *mipsII:
5214 *mipsIII:
5215 *mipsIV:
5216 *mipsV:
5217 *mips32:
5218 *mips64:
5219 *vr4100:
5220 *vr5000:
5221
5222
5223 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5224 "tlbwi"
5225 *mipsI:
5226 *mipsII:
5227 *mipsIII:
5228 *mipsIV:
5229 *mipsV:
5230 *mips32:
5231 *mips64:
5232 *vr4100:
5233 *vr5000:
5234
5235
5236 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5237 "tlbwr"
5238 *mipsI:
5239 *mipsII:
5240 *mipsIII:
5241 *mipsIV:
5242 *mipsV:
5243 *mips32:
5244 *mips64:
5245 *vr4100:
5246 *vr5000:
5247
5248 \f
5249 :include:::m16.igen
5250 :include:::mdmx.igen
5251 :include:::mips3d.igen
5252 :include:::sb1.igen
5253 :include:::tx.igen
5254 :include:::vr.igen
5255 \f