sim/mips/mips.igen

   1 // -*- C -*-
   2 //
   3 //    <insn> ::=
   4 //        <insn-word> { "+" <insn-word> }
   5 //        ":" <format-name>
   6 //        ":" <filter-flags>
   7 //        ":" <options>
   8 //        ":" <name>
   9 //        <nl>
  10 //        { <insn-model> }
  11 //        { <insn-mnemonic> }
  12 //        <code-block>
  13 //
  14
  15
  16 // IGEN config - mips16
  17 // :option:16::insn-bit-size:16
  18 // :option:16::hi-bit-nr:15
  19 :option:16::insn-specifying-widths:true
  20 :option:16::gen-delayed-branch:false
  21
  22 // IGEN config - mips32/64..
  23 // :option:32::insn-bit-size:32
  24 // :option:32::hi-bit-nr:31
  25 :option:32::insn-specifying-widths:true
  26 :option:32::gen-delayed-branch:false
  27
  28
  29 // Generate separate simulators for each target
  30 // :option:::multi-sim:true
  31
  32
  33 // Models known by this simulator are defined below.
  34 //
  35 // When placing models in the instruction descriptions, please place
  36 // them one per line, in the order given here.
  37
  38 //  MIPS ISAs:
  39 //
  40 //  Instructions and related functions for these models are included in
  41 //  this file.
  42 :model:::mipsI:mips3000:
  43 :model:::mipsII:mips6000:
  44 :model:::mipsIII:mips4000:
  45 :model:::mipsIV:mips8000:
  46 :model:::mipsV:mipsisaV:
  47 :model:::mips32:mipsisa32:
  48 :model:::mips32r2:mipsisa32r2:
  49 :model:::mips64:mipsisa64:
  50 :model:::mips64r2:mipsisa64r2:
  51
  52 //  Vendor ISAs:
  53 //
  54 //  Standard MIPS ISA instructions used for these models are listed here,
  55 //  as are functions needed by those standard instructions.  Instructions
  56 //  which are model-dependent and which are not in the standard MIPS ISAs
  57 //  (or which pre-date or use different encodings than the standard
  58 //  instructions) are (for the most part) in separate .igen files.
  59 :model:::vr4100:mips4100:               // vr.igen
  60 :model:::vr4120:mips4120:
  61 :model:::vr5000:mips5000:
  62 :model:::vr5400:mips5400:
  63 :model:::vr5500:mips5500:
  64 :model:::r3900:mips3900:                // tx.igen
  65
  66 //  MIPS Application Specific Extensions (ASEs)
  67 //
  68 //  Instructions for the ASEs are in separate .igen files.
  69 //  ASEs add instructions on to a base ISA.
  70 :model:::mips16:mips16:                 // m16.igen (and m16.dc)
  71 :model:::mips16e:mips16e:               // m16e.igen
  72 :model:::mips3d:mips3d:                 // mips3d.igen
  73 :model:::mdmx:mdmx:                     // mdmx.igen
  74 :model:::dsp:dsp:                       // dsp.igen
  75 :model:::dsp2:dsp2:                     // dsp2.igen
  76 :model:::smartmips:smartmips:           // smartmips.igen
  77
  78 //  Vendor Extensions
  79 //
  80 //  Instructions specific to these extensions are in separate .igen files.
  81 //  Extensions add instructions on to a base ISA.
  82 :model:::sb1:sb1:                       // sb1.igen
  83
  84
  85 // Pseudo instructions known by IGEN
  86 :internal::::illegal:
  87 {
  88   SignalException (ReservedInstruction, 0);
  89 }
  90
  91
  92 // Pseudo instructions known by interp.c
  93 // For grep - RSVD_INSTRUCTION, RSVD_INSTRUCTION_MASK
  94 000000,5.*,5.*,5.*,5.OP,000101:SPECIAL:32::RSVD
  95 "rsvd <OP>"
  96 {
  97   SignalException (ReservedInstruction, instruction_0);
  98 }
  99
 100
 101
 102 // Helper:
 103 //
 104 // Simulate a 32 bit delayslot instruction
 105 //
 106
 107 :function:::address_word:delayslot32:address_word target
 108 {
 109   instruction_word delay_insn;
 110   sim_events_slip (SD, 1);
 111   DSPC = CIA;
 112   CIA = CIA + 4; /* NOTE not mips16 */
 113   STATE |= simDELAYSLOT;
 114   delay_insn = IMEM32 (CIA); /* NOTE not mips16 */
 115   ENGINE_ISSUE_PREFIX_HOOK();
 116   idecode_issue (CPU_, delay_insn, (CIA));
 117   STATE &= ~simDELAYSLOT;
 118   return target;
 119 }
 120
 121 :function:::address_word:nullify_next_insn32:
 122 {
 123   sim_events_slip (SD, 1);
 124   dotrace (SD, CPU, tracefh, 2, CIA + 4, 4, "load instruction");
 125   return CIA + 8;
 126 }
 127
 128
 129 // Helper:
 130 //
 131 // Calculate an effective address given a base and an offset.
 132 //
 133
 134 :function:::address_word:loadstore_ea:address_word base, address_word offset
 135 *mipsI:
 136 *mipsII:
 137 *mipsIII:
 138 *mipsIV:
 139 *mipsV:
 140 *mips32:
 141 *mips32r2:
 142 *vr4100:
 143 *vr5000:
 144 *r3900:
 145 {
 146   return base + offset;
 147 }
 148
 149 :function:::address_word:loadstore_ea:address_word base, address_word offset
 150 *mips64:
 151 *mips64r2:
 152 {
 153 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 154   /* If in user mode and UX is not set, use 32-bit compatibility effective
 155      address computations as defined in the MIPS64 Architecture for
 156      Programmers Volume III, Revision 0.95, section 4.9.  */
 157   if ((SR & (status_KSU_mask|status_EXL|status_ERL|status_UX))
 158       == (ksu_user << status_KSU_shift))
 159     return (address_word)((signed32)base + (signed32)offset);
 160 #endif
 161   return base + offset;
 162 }
 163
 164
 165 // Helper:
 166 //
 167 // Check that a 32-bit register value is properly sign-extended.
 168 // (See NotWordValue in ISA spec.)
 169 //
 170
 171 :function:::int:not_word_value:unsigned_word value
 172 *mipsI:
 173 *mipsII:
 174 *mipsIII:
 175 *mipsIV:
 176 *mipsV:
 177 *vr4100:
 178 *vr5000:
 179 *r3900:
 180 *mips32:
 181 *mips32r2:
 182 *mips64:
 183 *mips64r2:
 184 {
 185 #if WITH_TARGET_WORD_BITSIZE == 64
 186   return value != (((value & 0xffffffff) ^ 0x80000000) - 0x80000000);
 187 #else
 188   return 0;
 189 #endif
 190 }
 191
 192 // Helper:
 193 //
 194 // Handle UNPREDICTABLE operation behaviour.  The goal here is to prevent
 195 // theoretically portable code which invokes non-portable behaviour from
 196 // running with no indication of the portability issue.
 197 // (See definition of UNPREDICTABLE in ISA spec.)
 198 //
 199
 200 :function:::void:unpredictable:
 201 *mipsI:
 202 *mipsII:
 203 *mipsIII:
 204 *mipsIV:
 205 *mipsV:
 206 *vr4100:
 207 *vr5000:
 208 *r3900:
 209 {
 210 }
 211
 212 :function:::void:unpredictable:
 213 *mips32:
 214 *mips32r2:
 215 *mips64:
 216 *mips64r2:
 217 {
 218   unpredictable_action (CPU, CIA);
 219 }
 220
 221
 222 // Helpers:
 223 //
 224 // Check that an access to a HI/LO register meets timing requirements
 225 //
 226 // In all MIPS ISAs,
 227 //
 228 //      OP {HI and LO} followed by MT{LO or HI} (and not MT{HI or LO})
 229 //      makes subsequent MF{HI or LO} UNPREDICTABLE. (1)
 230 //
 231 // The following restrictions exist for MIPS I - MIPS III:
 232 //
 233 //      MF{HI or LO} followed by MT{HI or LO} w/ less than 2 instructions
 234 //      in between makes MF UNPREDICTABLE. (2)
 235 //
 236 //      MF{HI or LO} followed by OP {HI and LO} w/ less than 2 instructions
 237 //      in between makes MF UNPREDICTABLE. (3)
 238 //
 239 // On the r3900, restriction (2) is not present, and restriction (3) is not
 240 // present for multiplication.
 241 //
 242 // Unfortunately, there seems to be some confusion about whether the last
 243 // two restrictions should apply to "MIPS IV" as well.  One edition of
 244 // the MIPS IV ISA says they do, but references in later ISA documents
 245 // suggest they don't.
 246 //
 247 // In reality, some MIPS IV parts, such as the VR5000 and VR5400, do have
 248 // these restrictions, while others, like the VR5500, don't.  To accomodate
 249 // such differences, the MIPS IV and MIPS V version of these helper functions
 250 // use auxillary routines to determine whether the restriction applies.
 251
 252 // check_mf_cycles:
 253 //
 254 // Helper used by check_mt_hilo, check_mult_hilo, and check_div_hilo
 255 // to check for restrictions (2) and (3) above.
 256 //
 257 :function:::int:check_mf_cycles:hilo_history *history, signed64 time, const char *new
 258 {
 259   if (history->mf.timestamp + 3 > time)
 260     {
 261       sim_engine_abort (SD, CPU, CIA, "HILO: %s: %s at 0x%08lx too close to MF at 0x%08lx\n",
 262                         itable[MY_INDEX].name,
 263                         new, (long) CIA,
 264                         (long) history->mf.cia);
 265       return 0;
 266     }
 267   return 1;
 268 }
 269
 270
 271 // check_mt_hilo:
 272 //
 273 // Check for restriction (2) above (for ISAs/processors that have it),
 274 // and record timestamps for restriction (1) above.
 275 //
 276 :function:::int:check_mt_hilo:hilo_history *history
 277 *mipsI:
 278 *mipsII:
 279 *mipsIII:
 280 *vr4100:
 281 *vr5000:
 282 {
 283   signed64 time = sim_events_time (SD);
 284   int ok = check_mf_cycles (SD_, history, time, "MT");
 285   history->mt.timestamp = time;
 286   history->mt.cia = CIA;
 287   return ok;
 288 }
 289
 290 :function:::int:check_mt_hilo:hilo_history *history
 291 *mipsIV:
 292 *mipsV:
 293 {
 294   signed64 time = sim_events_time (SD);
 295   int ok = (! MIPS_MACH_HAS_MT_HILO_HAZARD (SD)
 296             || check_mf_cycles (SD_, history, time, "MT"));
 297   history->mt.timestamp = time;
 298   history->mt.cia = CIA;
 299   return ok;
 300 }
 301
 302 :function:::int:check_mt_hilo:hilo_history *history
 303 *mips32:
 304 *mips32r2:
 305 *mips64:
 306 *mips64r2:
 307 *r3900:
 308 {
 309   signed64 time = sim_events_time (SD);
 310   history->mt.timestamp = time;
 311   history->mt.cia = CIA;
 312   return 1;
 313 }
 314
 315
 316 // check_mf_hilo:
 317 //
 318 // Check for restriction (1) above, and record timestamps for
 319 // restriction (2) and (3) above.
 320 //
 321 :function:::int:check_mf_hilo:hilo_history *history, hilo_history *peer
 322 *mipsI:
 323 *mipsII:
 324 *mipsIII:
 325 *mipsIV:
 326 *mipsV:
 327 *mips32:
 328 *mips32r2:
 329 *mips64:
 330 *mips64r2:
 331 *vr4100:
 332 *vr5000:
 333 *r3900:
 334 {
 335   signed64 time = sim_events_time (SD);
 336   int ok = 1;
 337   if (peer != NULL
 338       && peer->mt.timestamp > history->op.timestamp
 339       && history->mt.timestamp < history->op.timestamp
 340       && ! (history->mf.timestamp > history->op.timestamp
 341             && history->mf.timestamp < peer->mt.timestamp)
 342       && ! (peer->mf.timestamp > history->op.timestamp
 343             && peer->mf.timestamp < peer->mt.timestamp))
 344     {
 345       /* The peer has been written to since the last OP yet we have
 346          not */
 347       sim_engine_abort (SD, CPU, CIA, "HILO: %s: MF at 0x%08lx following OP at 0x%08lx corrupted by MT at 0x%08lx\n",
 348                         itable[MY_INDEX].name,
 349                         (long) CIA,
 350                         (long) history->op.cia,
 351                         (long) peer->mt.cia);
 352       ok = 0;
 353     }
 354   history->mf.timestamp = time;
 355   history->mf.cia = CIA;
 356   return ok;
 357 }
 358
 359
 360
 361 // check_mult_hilo:
 362 //
 363 // Check for restriction (3) above (for ISAs/processors that have it)
 364 // for MULT ops, and record timestamps for restriction (1) above.
 365 //
 366 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 367 *mipsI:
 368 *mipsII:
 369 *mipsIII:
 370 *vr4100:
 371 *vr5000:
 372 {
 373   signed64 time = sim_events_time (SD);
 374   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 375             && check_mf_cycles (SD_, lo, time, "OP"));
 376   hi->op.timestamp = time;
 377   lo->op.timestamp = time;
 378   hi->op.cia = CIA;
 379   lo->op.cia = CIA;
 380   return ok;
 381 }
 382
 383 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 384 *mipsIV:
 385 *mipsV:
 386 {
 387   signed64 time = sim_events_time (SD);
 388   int ok = (! MIPS_MACH_HAS_MULT_HILO_HAZARD (SD)
 389             || (check_mf_cycles (SD_, hi, time, "OP")
 390                 && check_mf_cycles (SD_, lo, time, "OP")));
 391   hi->op.timestamp = time;
 392   lo->op.timestamp = time;
 393   hi->op.cia = CIA;
 394   lo->op.cia = CIA;
 395   return ok;
 396 }
 397
 398 :function:::int:check_mult_hilo:hilo_history *hi, hilo_history *lo
 399 *mips32:
 400 *mips32r2:
 401 *mips64:
 402 *mips64r2:
 403 *r3900:
 404 {
 405   /* FIXME: could record the fact that a stall occured if we want */
 406   signed64 time = sim_events_time (SD);
 407   hi->op.timestamp = time;
 408   lo->op.timestamp = time;
 409   hi->op.cia = CIA;
 410   lo->op.cia = CIA;
 411   return 1;
 412 }
 413
 414
 415 // check_div_hilo:
 416 //
 417 // Check for restriction (3) above (for ISAs/processors that have it)
 418 // for DIV ops, and record timestamps for restriction (1) above.
 419 //
 420 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 421 *mipsI:
 422 *mipsII:
 423 *mipsIII:
 424 *vr4100:
 425 *vr5000:
 426 *r3900:
 427 {
 428   signed64 time = sim_events_time (SD);
 429   int ok = (check_mf_cycles (SD_, hi, time, "OP")
 430             && check_mf_cycles (SD_, lo, time, "OP"));
 431   hi->op.timestamp = time;
 432   lo->op.timestamp = time;
 433   hi->op.cia = CIA;
 434   lo->op.cia = CIA;
 435   return ok;
 436 }
 437
 438 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 439 *mipsIV:
 440 *mipsV:
 441 {
 442   signed64 time = sim_events_time (SD);
 443   int ok = (! MIPS_MACH_HAS_DIV_HILO_HAZARD (SD)
 444             || (check_mf_cycles (SD_, hi, time, "OP")
 445                 && check_mf_cycles (SD_, lo, time, "OP")));
 446   hi->op.timestamp = time;
 447   lo->op.timestamp = time;
 448   hi->op.cia = CIA;
 449   lo->op.cia = CIA;
 450   return ok;
 451 }
 452
 453 :function:::int:check_div_hilo:hilo_history *hi, hilo_history *lo
 454 *mips32:
 455 *mips32r2:
 456 *mips64:
 457 *mips64r2:
 458 {
 459   signed64 time = sim_events_time (SD);
 460   hi->op.timestamp = time;
 461   lo->op.timestamp = time;
 462   hi->op.cia = CIA;
 463   lo->op.cia = CIA;
 464   return 1;
 465 }
 466
 467
 468 // Helper:
 469 //
 470 // Check that the 64-bit instruction can currently be used, and signal
 471 // a ReservedInstruction exception if not.
 472 //
 473
 474 :function:::void:check_u64:instruction_word insn
 475 *mipsIII:
 476 *mipsIV:
 477 *mipsV:
 478 *vr4100:
 479 *vr5000:
 480 *vr5400:
 481 *vr5500:
 482 {
 483   // The check should be similar to mips64 for any with PX/UX bit equivalents.
 484 }
 485
 486 :function:::void:check_u64:instruction_word insn
 487 *mips16e:
 488 *mips64:
 489 *mips64r2:
 490 {
 491 #if 0 /* XXX FIXME: enable this only after some additional testing.  */
 492   if (UserMode && (SR & (status_UX|status_PX)) == 0)
 493     SignalException (ReservedInstruction, insn);
 494 #endif
 495 }
 496
 497
 498
 499 //
 500 // MIPS Architecture:
 501 //
 502 //        CPU Instruction Set (mipsI - mipsV, mips32/r2, mips64/r2)
 503 //
 504
 505
 506
 507 000000,5.RS,5.RT,5.RD,00000,100000:SPECIAL:32::ADD
 508 "add r<RD>, r<RS>, r<RT>"
 509 *mipsI:
 510 *mipsII:
 511 *mipsIII:
 512 *mipsIV:
 513 *mipsV:
 514 *mips32:
 515 *mips32r2:
 516 *mips64:
 517 *mips64r2:
 518 *vr4100:
 519 *vr5000:
 520 *r3900:
 521 {
 522   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
 523     Unpredictable ();
 524   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
 525   {
 526     ALU32_BEGIN (GPR[RS]);
 527     ALU32_ADD (GPR[RT]);
 528     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
 529   }
 530   TRACE_ALU_RESULT (GPR[RD]);
 531 }
 532
 533
 534
 535 001000,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDI
 536 "addi r<RT>, r<RS>, <IMMEDIATE>"
 537 *mipsI:
 538 *mipsII:
 539 *mipsIII:
 540 *mipsIV:
 541 *mipsV:
 542 *mips32:
 543 *mips32r2:
 544 *mips64:
 545 *mips64r2:
 546 *vr4100:
 547 *vr5000:
 548 *r3900:
 549 {
 550   if (NotWordValue (GPR[RS]))
 551     Unpredictable ();
 552   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
 553   {
 554     ALU32_BEGIN (GPR[RS]);
 555     ALU32_ADD (EXTEND16 (IMMEDIATE));
 556     ALU32_END (GPR[RT]);   /* This checks for overflow.  */
 557   }
 558   TRACE_ALU_RESULT (GPR[RT]);
 559 }
 560
 561
 562
 563 :function:::void:do_addiu:int rs, int rt, unsigned16 immediate
 564 {
 565   if (NotWordValue (GPR[rs]))
 566     Unpredictable ();
 567   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
 568   GPR[rt] = EXTEND32 (GPR[rs] + EXTEND16 (immediate));
 569   TRACE_ALU_RESULT (GPR[rt]);
 570 }
 571
 572 001001,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ADDIU
 573 "addiu r<RT>, r<RS>, <IMMEDIATE>"
 574 *mipsI:
 575 *mipsII:
 576 *mipsIII:
 577 *mipsIV:
 578 *mipsV:
 579 *mips32:
 580 *mips32r2:
 581 *mips64:
 582 *mips64r2:
 583 *vr4100:
 584 *vr5000:
 585 *r3900:
 586 {
 587   do_addiu (SD_, RS, RT, IMMEDIATE);
 588 }
 589
 590
 591
 592 :function:::void:do_addu:int rs, int rt, int rd
 593 {
 594   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
 595     Unpredictable ();
 596   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 597   GPR[rd] = EXTEND32 (GPR[rs] + GPR[rt]);
 598   TRACE_ALU_RESULT (GPR[rd]);
 599 }
 600
 601 000000,5.RS,5.RT,5.RD,00000,100001:SPECIAL:32::ADDU
 602 "addu r<RD>, r<RS>, r<RT>"
 603 *mipsI:
 604 *mipsII:
 605 *mipsIII:
 606 *mipsIV:
 607 *mipsV:
 608 *mips32:
 609 *mips32r2:
 610 *mips64:
 611 *mips64r2:
 612 *vr4100:
 613 *vr5000:
 614 *r3900:
 615 {
 616   do_addu (SD_, RS, RT, RD);
 617 }
 618
 619
 620
 621 :function:::void:do_and:int rs, int rt, int rd
 622 {
 623   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
 624   GPR[rd] = GPR[rs] & GPR[rt];
 625   TRACE_ALU_RESULT (GPR[rd]);
 626 }
 627
 628 000000,5.RS,5.RT,5.RD,00000,100100:SPECIAL:32::AND
 629 "and r<RD>, r<RS>, r<RT>"
 630 *mipsI:
 631 *mipsII:
 632 *mipsIII:
 633 *mipsIV:
 634 *mipsV:
 635 *mips32:
 636 *mips32r2:
 637 *mips64:
 638 *mips64r2:
 639 *vr4100:
 640 *vr5000:
 641 *r3900:
 642 {
 643   do_and (SD_, RS, RT, RD);
 644 }
 645
 646
 647
 648 001100,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ANDI
 649 "andi r<RT>, r<RS>, %#lx<IMMEDIATE>"
 650 *mipsI:
 651 *mipsII:
 652 *mipsIII:
 653 *mipsIV:
 654 *mipsV:
 655 *mips32:
 656 *mips32r2:
 657 *mips64:
 658 *mips64r2:
 659 *vr4100:
 660 *vr5000:
 661 *r3900:
 662 {
 663   TRACE_ALU_INPUT2 (GPR[RS], IMMEDIATE);
 664   GPR[RT] = GPR[RS] & IMMEDIATE;
 665   TRACE_ALU_RESULT (GPR[RT]);
 666 }
 667
 668
 669
 670 000100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQ
 671 "beq r<RS>, r<RT>, <OFFSET>"
 672 *mipsI:
 673 *mipsII:
 674 *mipsIII:
 675 *mipsIV:
 676 *mipsV:
 677 *mips32:
 678 *mips32r2:
 679 *mips64:
 680 *mips64r2:
 681 *vr4100:
 682 *vr5000:
 683 *r3900:
 684 {
 685   address_word offset = EXTEND16 (OFFSET) << 2;
 686   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 687     {
 688       DELAY_SLOT (NIA + offset);
 689     }
 690 }
 691
 692
 693
 694 010100,5.RS,5.RT,16.OFFSET:NORMAL:32::BEQL
 695 "beql r<RS>, r<RT>, <OFFSET>"
 696 *mipsII:
 697 *mipsIII:
 698 *mipsIV:
 699 *mipsV:
 700 *mips32:
 701 *mips32r2:
 702 *mips64:
 703 *mips64r2:
 704 *vr4100:
 705 *vr5000:
 706 *r3900:
 707 {
 708   address_word offset = EXTEND16 (OFFSET) << 2;
 709   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
 710     {
 711       DELAY_SLOT (NIA + offset);
 712     }
 713   else
 714     NULLIFY_NEXT_INSTRUCTION ();
 715 }
 716
 717
 718
 719 000001,5.RS,00001,16.OFFSET:REGIMM:32::BGEZ
 720 "bgez r<RS>, <OFFSET>"
 721 *mipsI:
 722 *mipsII:
 723 *mipsIII:
 724 *mipsIV:
 725 *mipsV:
 726 *mips32:
 727 *mips32r2:
 728 *mips64:
 729 *mips64r2:
 730 *vr4100:
 731 *vr5000:
 732 *r3900:
 733 {
 734   address_word offset = EXTEND16 (OFFSET) << 2;
 735   if ((signed_word) GPR[RS] >= 0)
 736     {
 737       DELAY_SLOT (NIA + offset);
 738     }
 739 }
 740
 741
 742
 743 000001,5.RS!31,10001,16.OFFSET:REGIMM:32::BGEZAL
 744 "bgezal r<RS>, <OFFSET>"
 745 *mipsI:
 746 *mipsII:
 747 *mipsIII:
 748 *mipsIV:
 749 *mipsV:
 750 *mips32:
 751 *mips32r2:
 752 *mips64:
 753 *mips64r2:
 754 *vr4100:
 755 *vr5000:
 756 *r3900:
 757 {
 758   address_word offset = EXTEND16 (OFFSET) << 2;
 759   if (RS == 31)
 760     Unpredictable ();
 761   RA = (CIA + 8);
 762   if ((signed_word) GPR[RS] >= 0)
 763     {
 764       DELAY_SLOT (NIA + offset);
 765     }
 766 }
 767
 768
 769
 770 000001,5.RS!31,10011,16.OFFSET:REGIMM:32::BGEZALL
 771 "bgezall r<RS>, <OFFSET>"
 772 *mipsII:
 773 *mipsIII:
 774 *mipsIV:
 775 *mipsV:
 776 *mips32:
 777 *mips32r2:
 778 *mips64:
 779 *mips64r2:
 780 *vr4100:
 781 *vr5000:
 782 *r3900:
 783 {
 784   address_word offset = EXTEND16 (OFFSET) << 2;
 785   if (RS == 31)
 786     Unpredictable ();
 787   RA = (CIA + 8);
 788   /* NOTE: The branch occurs AFTER the next instruction has been
 789      executed */
 790   if ((signed_word) GPR[RS] >= 0)
 791     {
 792       DELAY_SLOT (NIA + offset);
 793     }
 794   else
 795     NULLIFY_NEXT_INSTRUCTION ();
 796 }
 797
 798
 799
 800 000001,5.RS,00011,16.OFFSET:REGIMM:32::BGEZL
 801 "bgezl r<RS>, <OFFSET>"
 802 *mipsII:
 803 *mipsIII:
 804 *mipsIV:
 805 *mipsV:
 806 *mips32:
 807 *mips32r2:
 808 *mips64:
 809 *mips64r2:
 810 *vr4100:
 811 *vr5000:
 812 *r3900:
 813 {
 814   address_word offset = EXTEND16 (OFFSET) << 2;
 815   if ((signed_word) GPR[RS] >= 0)
 816     {
 817       DELAY_SLOT (NIA + offset);
 818     }
 819   else
 820     NULLIFY_NEXT_INSTRUCTION ();
 821 }
 822
 823
 824
 825 000111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZ
 826 "bgtz r<RS>, <OFFSET>"
 827 *mipsI:
 828 *mipsII:
 829 *mipsIII:
 830 *mipsIV:
 831 *mipsV:
 832 *mips32:
 833 *mips32r2:
 834 *mips64:
 835 *mips64r2:
 836 *vr4100:
 837 *vr5000:
 838 *r3900:
 839 {
 840   address_word offset = EXTEND16 (OFFSET) << 2;
 841   if ((signed_word) GPR[RS] > 0)
 842     {
 843       DELAY_SLOT (NIA + offset);
 844     }
 845 }
 846
 847
 848
 849 010111,5.RS,00000,16.OFFSET:NORMAL:32::BGTZL
 850 "bgtzl r<RS>, <OFFSET>"
 851 *mipsII:
 852 *mipsIII:
 853 *mipsIV:
 854 *mipsV:
 855 *mips32:
 856 *mips32r2:
 857 *mips64:
 858 *mips64r2:
 859 *vr4100:
 860 *vr5000:
 861 *r3900:
 862 {
 863   address_word offset = EXTEND16 (OFFSET) << 2;
 864   /* NOTE: The branch occurs AFTER the next instruction has been
 865      executed */
 866   if ((signed_word) GPR[RS] > 0)
 867     {
 868       DELAY_SLOT (NIA + offset);
 869     }
 870   else
 871     NULLIFY_NEXT_INSTRUCTION ();
 872 }
 873
 874
 875
 876 000110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZ
 877 "blez r<RS>, <OFFSET>"
 878 *mipsI:
 879 *mipsII:
 880 *mipsIII:
 881 *mipsIV:
 882 *mipsV:
 883 *mips32:
 884 *mips32r2:
 885 *mips64:
 886 *mips64r2:
 887 *vr4100:
 888 *vr5000:
 889 *r3900:
 890 {
 891   address_word offset = EXTEND16 (OFFSET) << 2;
 892   /* NOTE: The branch occurs AFTER the next instruction has been
 893      executed */
 894   if ((signed_word) GPR[RS] <= 0)
 895     {
 896       DELAY_SLOT (NIA + offset);
 897     }
 898 }
 899
 900
 901
 902 010110,5.RS,00000,16.OFFSET:NORMAL:32::BLEZL
 903 "bgezl r<RS>, <OFFSET>"
 904 *mipsII:
 905 *mipsIII:
 906 *mipsIV:
 907 *mipsV:
 908 *mips32:
 909 *mips32r2:
 910 *mips64:
 911 *mips64r2:
 912 *vr4100:
 913 *vr5000:
 914 *r3900:
 915 {
 916   address_word offset = EXTEND16 (OFFSET) << 2;
 917   if ((signed_word) GPR[RS] <= 0)
 918     {
 919       DELAY_SLOT (NIA + offset);
 920     }
 921   else
 922     NULLIFY_NEXT_INSTRUCTION ();
 923 }
 924
 925
 926
 927 000001,5.RS,00000,16.OFFSET:REGIMM:32::BLTZ
 928 "bltz r<RS>, <OFFSET>"
 929 *mipsI:
 930 *mipsII:
 931 *mipsIII:
 932 *mipsIV:
 933 *mipsV:
 934 *mips32:
 935 *mips32r2:
 936 *mips64:
 937 *mips64r2:
 938 *vr4100:
 939 *vr5000:
 940 *r3900:
 941 {
 942   address_word offset = EXTEND16 (OFFSET) << 2;
 943   if ((signed_word) GPR[RS] < 0)
 944     {
 945       DELAY_SLOT (NIA + offset);
 946     }
 947 }
 948
 949
 950
 951 000001,5.RS!31,10000,16.OFFSET:REGIMM:32::BLTZAL
 952 "bltzal r<RS>, <OFFSET>"
 953 *mipsI:
 954 *mipsII:
 955 *mipsIII:
 956 *mipsIV:
 957 *mipsV:
 958 *mips32:
 959 *mips32r2:
 960 *mips64:
 961 *mips64r2:
 962 *vr4100:
 963 *vr5000:
 964 *r3900:
 965 {
 966   address_word offset = EXTEND16 (OFFSET) << 2;
 967   if (RS == 31)
 968     Unpredictable ();
 969   RA = (CIA + 8);
 970   /* NOTE: The branch occurs AFTER the next instruction has been
 971      executed */
 972   if ((signed_word) GPR[RS] < 0)
 973     {
 974       DELAY_SLOT (NIA + offset);
 975     }
 976 }
 977
 978
 979
 980 000001,5.RS!31,10010,16.OFFSET:REGIMM:32::BLTZALL
 981 "bltzall r<RS>, <OFFSET>"
 982 *mipsII:
 983 *mipsIII:
 984 *mipsIV:
 985 *mipsV:
 986 *mips32:
 987 *mips32r2:
 988 *mips64:
 989 *mips64r2:
 990 *vr4100:
 991 *vr5000:
 992 *r3900:
 993 {
 994   address_word offset = EXTEND16 (OFFSET) << 2;
 995   if (RS == 31)
 996     Unpredictable ();
 997   RA = (CIA + 8);
 998   if ((signed_word) GPR[RS] < 0)
 999     {
1000       DELAY_SLOT (NIA + offset);
1001     }
1002   else
1003     NULLIFY_NEXT_INSTRUCTION ();
1004 }
1005
1006
1007
1008 000001,5.RS,00010,16.OFFSET:REGIMM:32::BLTZL
1009 "bltzl r<RS>, <OFFSET>"
1010 *mipsII:
1011 *mipsIII:
1012 *mipsIV:
1013 *mipsV:
1014 *mips32:
1015 *mips32r2:
1016 *mips64:
1017 *mips64r2:
1018 *vr4100:
1019 *vr5000:
1020 *r3900:
1021 {
1022   address_word offset = EXTEND16 (OFFSET) << 2;
1023   /* NOTE: The branch occurs AFTER the next instruction has been
1024      executed */
1025   if ((signed_word) GPR[RS] < 0)
1026     {
1027       DELAY_SLOT (NIA + offset);
1028     }
1029   else
1030     NULLIFY_NEXT_INSTRUCTION ();
1031 }
1032
1033
1034
1035 000101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNE
1036 "bne r<RS>, r<RT>, <OFFSET>"
1037 *mipsI:
1038 *mipsII:
1039 *mipsIII:
1040 *mipsIV:
1041 *mipsV:
1042 *mips32:
1043 *mips32r2:
1044 *mips64:
1045 *mips64r2:
1046 *vr4100:
1047 *vr5000:
1048 *r3900:
1049 {
1050   address_word offset = EXTEND16 (OFFSET) << 2;
1051   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1052     {
1053       DELAY_SLOT (NIA + offset);
1054     }
1055 }
1056
1057
1058
1059 010101,5.RS,5.RT,16.OFFSET:NORMAL:32::BNEL
1060 "bnel r<RS>, r<RT>, <OFFSET>"
1061 *mipsII:
1062 *mipsIII:
1063 *mipsIV:
1064 *mipsV:
1065 *mips32:
1066 *mips32r2:
1067 *mips64:
1068 *mips64r2:
1069 *vr4100:
1070 *vr5000:
1071 *r3900:
1072 {
1073   address_word offset = EXTEND16 (OFFSET) << 2;
1074   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
1075     {
1076       DELAY_SLOT (NIA + offset);
1077     }
1078   else
1079     NULLIFY_NEXT_INSTRUCTION ();
1080 }
1081
1082
1083
1084 000000,20.CODE,001101:SPECIAL:32::BREAK
1085 "break %#lx<CODE>"
1086 *mipsI:
1087 *mipsII:
1088 *mipsIII:
1089 *mipsIV:
1090 *mipsV:
1091 *mips32:
1092 *mips32r2:
1093 *mips64:
1094 *mips64r2:
1095 *vr4100:
1096 *vr5000:
1097 *r3900:
1098 {
1099   /* Check for some break instruction which are reserved for use by the simulator.  */
1100   unsigned int break_code = instruction_0 & HALT_INSTRUCTION_MASK;
1101   if (break_code == (HALT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1102       break_code == (HALT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1103     {
1104       sim_engine_halt (SD, CPU, NULL, cia,
1105                        sim_exited, (unsigned int)(A0 & 0xFFFFFFFF));
1106     }
1107   else if (break_code == (BREAKPOINT_INSTRUCTION  & HALT_INSTRUCTION_MASK) ||
1108            break_code == (BREAKPOINT_INSTRUCTION2 & HALT_INSTRUCTION_MASK))
1109     {
1110       if (STATE & simDELAYSLOT)
1111         PC = cia - 4; /* reference the branch instruction */
1112       else
1113         PC = cia;
1114       SignalException (BreakPoint, instruction_0);
1115     }
1116
1117   else
1118     {
1119       /* If we get this far, we're not an instruction reserved by the sim.  Raise
1120          the exception. */
1121       SignalException (BreakPoint, instruction_0);
1122     }
1123 }
1124
1125
1126
1127 011100,5.RS,5.RT,5.RD,00000,100001:SPECIAL2:32::CLO
1128 "clo r<RD>, r<RS>"
1129 *mips32:
1130 *mips32r2:
1131 *mips64:
1132 *mips64r2:
1133 *vr5500:
1134 {
1135   unsigned32 temp = GPR[RS];
1136   unsigned32 i, mask;
1137   if (RT != RD)
1138     Unpredictable ();
1139   if (NotWordValue (GPR[RS]))
1140     Unpredictable ();
1141   TRACE_ALU_INPUT1 (GPR[RS]);
1142   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1143     {
1144       if ((temp & mask) == 0)
1145         break;
1146       mask >>= 1;
1147     }
1148   GPR[RD] = EXTEND32 (i);
1149   TRACE_ALU_RESULT (GPR[RD]);
1150 }
1151
1152
1153
1154 011100,5.RS,5.RT,5.RD,00000,100000:SPECIAL2:32::CLZ
1155 "clz r<RD>, r<RS>"
1156 *mips32:
1157 *mips32r2:
1158 *mips64:
1159 *mips64r2:
1160 *vr5500:
1161 {
1162   unsigned32 temp = GPR[RS];
1163   unsigned32 i, mask;
1164   if (RT != RD)
1165     Unpredictable ();
1166   if (NotWordValue (GPR[RS]))
1167     Unpredictable ();
1168   TRACE_ALU_INPUT1 (GPR[RS]);
1169   for (mask = ((unsigned32)1<<31), i = 0; i < 32; ++i)
1170     {
1171       if ((temp & mask) != 0)
1172         break;
1173       mask >>= 1;
1174     }
1175   GPR[RD] = EXTEND32 (i);
1176   TRACE_ALU_RESULT (GPR[RD]);
1177 }
1178
1179
1180
1181 000000,5.RS,5.RT,5.RD,00000,101100:SPECIAL:64::DADD
1182 "dadd r<RD>, r<RS>, r<RT>"
1183 *mipsIII:
1184 *mipsIV:
1185 *mipsV:
1186 *mips64:
1187 *mips64r2:
1188 *vr4100:
1189 *vr5000:
1190 {
1191   check_u64 (SD_, instruction_0);
1192   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1193   {
1194     ALU64_BEGIN (GPR[RS]);
1195     ALU64_ADD (GPR[RT]);
1196     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1197   }
1198   TRACE_ALU_RESULT (GPR[RD]);
1199 }
1200
1201
1202
1203 011000,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDI
1204 "daddi r<RT>, r<RS>, <IMMEDIATE>"
1205 *mipsIII:
1206 *mipsIV:
1207 *mipsV:
1208 *mips64:
1209 *mips64r2:
1210 *vr4100:
1211 *vr5000:
1212 {
1213   check_u64 (SD_, instruction_0);
1214   TRACE_ALU_INPUT2 (GPR[RS], EXTEND16 (IMMEDIATE));
1215   {
1216     ALU64_BEGIN (GPR[RS]);
1217     ALU64_ADD (EXTEND16 (IMMEDIATE));
1218     ALU64_END (GPR[RT]);   /* This checks for overflow.  */
1219   }
1220   TRACE_ALU_RESULT (GPR[RT]);
1221 }
1222
1223
1224
1225 :function:::void:do_daddiu:int rs, int rt, unsigned16 immediate
1226 {
1227   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
1228   GPR[rt] = GPR[rs] + EXTEND16 (immediate);
1229   TRACE_ALU_RESULT (GPR[rt]);
1230 }
1231
1232 011001,5.RS,5.RT,16.IMMEDIATE:NORMAL:64::DADDIU
1233 "daddiu r<RT>, r<RS>, <IMMEDIATE>"
1234 *mipsIII:
1235 *mipsIV:
1236 *mipsV:
1237 *mips64:
1238 *mips64r2:
1239 *vr4100:
1240 *vr5000:
1241 {
1242   check_u64 (SD_, instruction_0);
1243   do_daddiu (SD_, RS, RT, IMMEDIATE);
1244 }
1245
1246
1247
1248 :function:::void:do_daddu:int rs, int rt, int rd
1249 {
1250   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1251   GPR[rd] = GPR[rs] + GPR[rt];
1252   TRACE_ALU_RESULT (GPR[rd]);
1253 }
1254
1255 000000,5.RS,5.RT,5.RD,00000,101101:SPECIAL:64::DADDU
1256 "daddu r<RD>, r<RS>, r<RT>"
1257 *mipsIII:
1258 *mipsIV:
1259 *mipsV:
1260 *mips64:
1261 *mips64r2:
1262 *vr4100:
1263 *vr5000:
1264 {
1265   check_u64 (SD_, instruction_0);
1266   do_daddu (SD_, RS, RT, RD);
1267 }
1268
1269
1270
1271 011100,5.RS,5.RT,5.RD,00000,100101:SPECIAL2:64::DCLO
1272 "dclo r<RD>, r<RS>"
1273 *mips64:
1274 *mips64r2:
1275 *vr5500:
1276 {
1277   unsigned64 temp = GPR[RS];
1278   unsigned32 i;
1279   unsigned64 mask;
1280   check_u64 (SD_, instruction_0);
1281   if (RT != RD)
1282     Unpredictable ();
1283   TRACE_ALU_INPUT1 (GPR[RS]);
1284   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1285     {
1286       if ((temp & mask) == 0)
1287         break;
1288       mask >>= 1;
1289     }
1290   GPR[RD] = EXTEND32 (i);
1291   TRACE_ALU_RESULT (GPR[RD]);
1292 }
1293
1294
1295
1296 011100,5.RS,5.RT,5.RD,00000,100100:SPECIAL2:64::DCLZ
1297 "dclz r<RD>, r<RS>"
1298 *mips64:
1299 *mips64r2:
1300 *vr5500:
1301 {
1302   unsigned64 temp = GPR[RS];
1303   unsigned32 i;
1304   unsigned64 mask;
1305   check_u64 (SD_, instruction_0);
1306   if (RT != RD)
1307     Unpredictable ();
1308   TRACE_ALU_INPUT1 (GPR[RS]);
1309   for (mask = ((unsigned64)1<<63), i = 0; i < 64; ++i)
1310     {
1311       if ((temp & mask) != 0)
1312         break;
1313       mask >>= 1;
1314     }
1315   GPR[RD] = EXTEND32 (i);
1316   TRACE_ALU_RESULT (GPR[RD]);
1317 }
1318
1319
1320
1321 :function:::void:do_ddiv:int rs, int rt
1322 {
1323   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1324   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1325   {
1326     signed64 n = GPR[rs];
1327     signed64 d = GPR[rt];
1328     signed64 hi;
1329     signed64 lo;
1330     if (d == 0)
1331       {
1332         lo = SIGNED64 (0x8000000000000000);
1333         hi = 0;
1334       }
1335     else if (d == -1 && n == SIGNED64 (0x8000000000000000))
1336       {
1337         lo = SIGNED64 (0x8000000000000000);
1338         hi = 0;
1339       }
1340     else
1341       {
1342         lo = (n / d);
1343         hi = (n % d);
1344       }
1345     HI = hi;
1346     LO = lo;
1347   }
1348   TRACE_ALU_RESULT2 (HI, LO);
1349 }
1350
1351 000000,5.RS,5.RT,0000000000,011110:SPECIAL:64::DDIV
1352 "ddiv r<RS>, r<RT>"
1353 *mipsIII:
1354 *mipsIV:
1355 *mipsV:
1356 *mips64:
1357 *mips64r2:
1358 *vr4100:
1359 *vr5000:
1360 {
1361   check_u64 (SD_, instruction_0);
1362   do_ddiv (SD_, RS, RT);
1363 }
1364
1365
1366
1367 :function:::void:do_ddivu:int rs, int rt
1368 {
1369   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1370   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1371   {
1372     unsigned64 n = GPR[rs];
1373     unsigned64 d = GPR[rt];
1374     unsigned64 hi;
1375     unsigned64 lo;
1376     if (d == 0)
1377       {
1378         lo = SIGNED64 (0x8000000000000000);
1379         hi = 0;
1380       }
1381     else
1382       {
1383         lo = (n / d);
1384         hi = (n % d);
1385       }
1386     HI = hi;
1387     LO = lo;
1388   }
1389   TRACE_ALU_RESULT2 (HI, LO);
1390 }
1391
1392 000000,5.RS,5.RT,0000000000,011111:SPECIAL:64::DDIVU
1393 "ddivu r<RS>, r<RT>"
1394 *mipsIII:
1395 *mipsIV:
1396 *mipsV:
1397 *mips64:
1398 *mips64r2:
1399 *vr4100:
1400 *vr5000:
1401 {
1402   check_u64 (SD_, instruction_0);
1403   do_ddivu (SD_, RS, RT);
1404 }
1405
1406 :function:::void:do_div:int rs, int rt
1407 {
1408   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1409   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1410   {
1411     signed32 n = GPR[rs];
1412     signed32 d = GPR[rt];
1413     if (d == 0)
1414       {
1415         LO = EXTEND32 (0x80000000);
1416         HI = EXTEND32 (0);
1417       }
1418     else if (n == SIGNED32 (0x80000000) && d == -1)
1419       {
1420         LO = EXTEND32 (0x80000000);
1421         HI = EXTEND32 (0);
1422       }
1423     else
1424       {
1425         LO = EXTEND32 (n / d);
1426         HI = EXTEND32 (n % d);
1427       }
1428   }
1429   TRACE_ALU_RESULT2 (HI, LO);
1430 }
1431
1432 000000,5.RS,5.RT,0000000000,011010:SPECIAL:32::DIV
1433 "div r<RS>, r<RT>"
1434 *mipsI:
1435 *mipsII:
1436 *mipsIII:
1437 *mipsIV:
1438 *mipsV:
1439 *mips32:
1440 *mips32r2:
1441 *mips64:
1442 *mips64r2:
1443 *vr4100:
1444 *vr5000:
1445 *r3900:
1446 {
1447   do_div (SD_, RS, RT);
1448 }
1449
1450
1451
1452 :function:::void:do_divu:int rs, int rt
1453 {
1454   check_div_hilo (SD_, HIHISTORY, LOHISTORY);
1455   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1456   {
1457     unsigned32 n = GPR[rs];
1458     unsigned32 d = GPR[rt];
1459     if (d == 0)
1460       {
1461         LO = EXTEND32 (0x80000000);
1462         HI = EXTEND32 (0);
1463       }
1464     else
1465       {
1466         LO = EXTEND32 (n / d);
1467         HI = EXTEND32 (n % d);
1468       }
1469   }
1470   TRACE_ALU_RESULT2 (HI, LO);
1471 }
1472
1473 000000,5.RS,5.RT,0000000000,011011:SPECIAL:32::DIVU
1474 "divu r<RS>, r<RT>"
1475 *mipsI:
1476 *mipsII:
1477 *mipsIII:
1478 *mipsIV:
1479 *mipsV:
1480 *mips32:
1481 *mips32r2:
1482 *mips64:
1483 *mips64r2:
1484 *vr4100:
1485 *vr5000:
1486 *r3900:
1487 {
1488   do_divu (SD_, RS, RT);
1489 }
1490
1491
1492 :function:::void:do_dmultx:int rs, int rt, int rd, int signed_p
1493 {
1494   unsigned64 lo;
1495   unsigned64 hi;
1496   unsigned64 m00;
1497   unsigned64 m01;
1498   unsigned64 m10;
1499   unsigned64 m11;
1500   unsigned64 mid;
1501   int sign;
1502   unsigned64 op1 = GPR[rs];
1503   unsigned64 op2 = GPR[rt];
1504   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
1505   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1506   /* make signed multiply unsigned */
1507   sign = 0;
1508   if (signed_p)
1509     {
1510       if ((signed64) op1 < 0)
1511         {
1512           op1 = - op1;
1513           ++sign;
1514         }
1515       if ((signed64) op2 < 0)
1516         {
1517           op2 = - op2;
1518           ++sign;
1519         }
1520     }
1521   /* multiply out the 4 sub products */
1522   m00 = ((unsigned64) VL4_8 (op1) * (unsigned64) VL4_8 (op2));
1523   m10 = ((unsigned64) VH4_8 (op1) * (unsigned64) VL4_8 (op2));
1524   m01 = ((unsigned64) VL4_8 (op1) * (unsigned64) VH4_8 (op2));
1525   m11 = ((unsigned64) VH4_8 (op1) * (unsigned64) VH4_8 (op2));
1526   /* add the products */
1527   mid = ((unsigned64) VH4_8 (m00)
1528          + (unsigned64) VL4_8 (m10)
1529          + (unsigned64) VL4_8 (m01));
1530   lo = U8_4 (mid, m00);
1531   hi = (m11
1532         + (unsigned64) VH4_8 (mid)
1533         + (unsigned64) VH4_8 (m01)
1534         + (unsigned64) VH4_8 (m10));
1535   /* fix the sign */
1536   if (sign & 1)
1537     {
1538       lo = -lo;
1539       if (lo == 0)
1540         hi = -hi;
1541       else
1542         hi = -hi - 1;
1543     }
1544   /* save the result HI/LO (and a gpr) */
1545   LO = lo;
1546   HI = hi;
1547   if (rd != 0)
1548     GPR[rd] = lo;
1549   TRACE_ALU_RESULT2 (HI, LO);
1550 }
1551
1552 :function:::void:do_dmult:int rs, int rt, int rd
1553 {
1554   do_dmultx (SD_, rs, rt, rd, 1);
1555 }
1556
1557 000000,5.RS,5.RT,0000000000,011100:SPECIAL:64::DMULT
1558 "dmult r<RS>, r<RT>"
1559 *mipsIII:
1560 *mipsIV:
1561 *mipsV:
1562 *mips64:
1563 *mips64r2:
1564 *vr4100:
1565 {
1566   check_u64 (SD_, instruction_0);
1567   do_dmult (SD_, RS, RT, 0);
1568 }
1569
1570 000000,5.RS,5.RT,5.RD,00000,011100:SPECIAL:64::DMULT
1571 "dmult r<RS>, r<RT>":RD == 0
1572 "dmult r<RD>, r<RS>, r<RT>"
1573 *vr5000:
1574 {
1575   check_u64 (SD_, instruction_0);
1576   do_dmult (SD_, RS, RT, RD);
1577 }
1578
1579
1580
1581 :function:::void:do_dmultu:int rs, int rt, int rd
1582 {
1583   do_dmultx (SD_, rs, rt, rd, 0);
1584 }
1585
1586 000000,5.RS,5.RT,0000000000,011101:SPECIAL:64::DMULTU
1587 "dmultu r<RS>, r<RT>"
1588 *mipsIII:
1589 *mipsIV:
1590 *mipsV:
1591 *mips64:
1592 *mips64r2:
1593 *vr4100:
1594 {
1595   check_u64 (SD_, instruction_0);
1596   do_dmultu (SD_, RS, RT, 0);
1597 }
1598
1599 000000,5.RS,5.RT,5.RD,00000,011101:SPECIAL:64::DMULTU
1600 "dmultu r<RD>, r<RS>, r<RT>":RD == 0
1601 "dmultu r<RS>, r<RT>"
1602 *vr5000:
1603 {
1604   check_u64 (SD_, instruction_0);
1605   do_dmultu (SD_, RS, RT, RD);
1606 }
1607
1608
1609 :function:::unsigned64:do_dror:unsigned64 x,unsigned64 y
1610 {
1611   unsigned64 result;
1612
1613   y &= 63;
1614   TRACE_ALU_INPUT2 (x, y);
1615   result = ROTR64 (x, y);
1616   TRACE_ALU_RESULT (result);
1617   return result;
1618 }
1619
1620 000000,00001,5.RT,5.RD,5.SHIFT,111010::64::DROR
1621 "dror r<RD>, r<RT>, <SHIFT>"
1622 *mips64r2:
1623 *vr5400:
1624 *vr5500:
1625 {
1626   check_u64 (SD_, instruction_0);
1627   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT);
1628 }
1629
1630 000000,00001,5.RT,5.RD,5.SHIFT,111110::64::DROR32
1631 "dror32 r<RD>, r<RT>, <SHIFT>"
1632 *mips64r2:
1633 *vr5400:
1634 *vr5500:
1635 {
1636   check_u64 (SD_, instruction_0);
1637   GPR[RD] = do_dror (SD_, GPR[RT], SHIFT + 32);
1638 }
1639
1640 000000,5.RS,5.RT,5.RD,00001,010110::64::DRORV
1641 "drorv r<RD>, r<RT>, r<RS>"
1642 *mips64r2:
1643 *vr5400:
1644 *vr5500:
1645 {
1646   check_u64 (SD_, instruction_0);
1647   GPR[RD] = do_dror (SD_, GPR[RT], GPR[RS]);
1648 }
1649
1650
1651 :function:::void:do_dsll:int rt, int rd, int shift
1652 {
1653   TRACE_ALU_INPUT2 (GPR[rt], shift);
1654   GPR[rd] = GPR[rt] << shift;
1655   TRACE_ALU_RESULT (GPR[rd]);
1656 }
1657
1658 000000,00000,5.RT,5.RD,5.SHIFT,111000:SPECIAL:64::DSLL
1659 "dsll r<RD>, r<RT>, <SHIFT>"
1660 *mipsIII:
1661 *mipsIV:
1662 *mipsV:
1663 *mips64:
1664 *mips64r2:
1665 *vr4100:
1666 *vr5000:
1667 {
1668   check_u64 (SD_, instruction_0);
1669   do_dsll (SD_, RT, RD, SHIFT);
1670 }
1671
1672
1673 000000,00000,5.RT,5.RD,5.SHIFT,111100:SPECIAL:64::DSLL32
1674 "dsll32 r<RD>, r<RT>, <SHIFT>"
1675 *mipsIII:
1676 *mipsIV:
1677 *mipsV:
1678 *mips64:
1679 *mips64r2:
1680 *vr4100:
1681 *vr5000:
1682 {
1683   int s = 32 + SHIFT;
1684   check_u64 (SD_, instruction_0);
1685   TRACE_ALU_INPUT2 (GPR[RT], s);
1686   GPR[RD] = GPR[RT] << s;
1687   TRACE_ALU_RESULT (GPR[RD]);
1688 }
1689
1690 :function:::void:do_dsllv:int rs, int rt, int rd
1691 {
1692   int s = MASKED64 (GPR[rs], 5, 0);
1693   TRACE_ALU_INPUT2 (GPR[rt], s);
1694   GPR[rd] = GPR[rt] << s;
1695   TRACE_ALU_RESULT (GPR[rd]);
1696 }
1697
1698 000000,5.RS,5.RT,5.RD,00000,010100:SPECIAL:64::DSLLV
1699 "dsllv r<RD>, r<RT>, r<RS>"
1700 *mipsIII:
1701 *mipsIV:
1702 *mipsV:
1703 *mips64:
1704 *mips64r2:
1705 *vr4100:
1706 *vr5000:
1707 {
1708   check_u64 (SD_, instruction_0);
1709   do_dsllv (SD_, RS, RT, RD);
1710 }
1711
1712 :function:::void:do_dsra:int rt, int rd, int shift
1713 {
1714   TRACE_ALU_INPUT2 (GPR[rt], shift);
1715   GPR[rd] = ((signed64) GPR[rt]) >> shift;
1716   TRACE_ALU_RESULT (GPR[rd]);
1717 }
1718
1719
1720 000000,00000,5.RT,5.RD,5.SHIFT,111011:SPECIAL:64::DSRA
1721 "dsra r<RD>, r<RT>, <SHIFT>"
1722 *mipsIII:
1723 *mipsIV:
1724 *mipsV:
1725 *mips64:
1726 *mips64r2:
1727 *vr4100:
1728 *vr5000:
1729 {
1730   check_u64 (SD_, instruction_0);
1731   do_dsra (SD_, RT, RD, SHIFT);
1732 }
1733
1734
1735 000000,00000,5.RT,5.RD,5.SHIFT,111111:SPECIAL:64::DSRA32
1736 "dsra32 r<RD>, r<RT>, <SHIFT>"
1737 *mipsIII:
1738 *mipsIV:
1739 *mipsV:
1740 *mips64:
1741 *mips64r2:
1742 *vr4100:
1743 *vr5000:
1744 {
1745   int s = 32 + SHIFT;
1746   check_u64 (SD_, instruction_0);
1747   TRACE_ALU_INPUT2 (GPR[RT], s);
1748   GPR[RD] = ((signed64) GPR[RT]) >> s;
1749   TRACE_ALU_RESULT (GPR[RD]);
1750 }
1751
1752
1753 :function:::void:do_dsrav:int rs, int rt, int rd
1754 {
1755   int s = MASKED64 (GPR[rs], 5, 0);
1756   TRACE_ALU_INPUT2 (GPR[rt], s);
1757   GPR[rd] = ((signed64) GPR[rt]) >> s;
1758   TRACE_ALU_RESULT (GPR[rd]);
1759 }
1760
1761 000000,5.RS,5.RT,5.RD,00000,010111:SPECIAL:64::DSRAV
1762 "dsrav r<RD>, r<RT>, r<RS>"
1763 *mipsIII:
1764 *mipsIV:
1765 *mipsV:
1766 *mips64:
1767 *mips64r2:
1768 *vr4100:
1769 *vr5000:
1770 {
1771   check_u64 (SD_, instruction_0);
1772   do_dsrav (SD_, RS, RT, RD);
1773 }
1774
1775 :function:::void:do_dsrl:int rt, int rd, int shift
1776 {
1777   TRACE_ALU_INPUT2 (GPR[rt], shift);
1778   GPR[rd] = (unsigned64) GPR[rt] >> shift;
1779   TRACE_ALU_RESULT (GPR[rd]);
1780 }
1781
1782
1783 000000,00000,5.RT,5.RD,5.SHIFT,111010:SPECIAL:64::DSRL
1784 "dsrl r<RD>, r<RT>, <SHIFT>"
1785 *mipsIII:
1786 *mipsIV:
1787 *mipsV:
1788 *mips64:
1789 *mips64r2:
1790 *vr4100:
1791 *vr5000:
1792 {
1793   check_u64 (SD_, instruction_0);
1794   do_dsrl (SD_, RT, RD, SHIFT);
1795 }
1796
1797
1798 000000,00000,5.RT,5.RD,5.SHIFT,111110:SPECIAL:64::DSRL32
1799 "dsrl32 r<RD>, r<RT>, <SHIFT>"
1800 *mipsIII:
1801 *mipsIV:
1802 *mipsV:
1803 *mips64:
1804 *mips64r2:
1805 *vr4100:
1806 *vr5000:
1807 {
1808   int s = 32 + SHIFT;
1809   check_u64 (SD_, instruction_0);
1810   TRACE_ALU_INPUT2 (GPR[RT], s);
1811   GPR[RD] = (unsigned64) GPR[RT] >> s;
1812   TRACE_ALU_RESULT (GPR[RD]);
1813 }
1814
1815
1816 :function:::void:do_dsrlv:int rs, int rt, int rd
1817 {
1818   int s = MASKED64 (GPR[rs], 5, 0);
1819   TRACE_ALU_INPUT2 (GPR[rt], s);
1820   GPR[rd] = (unsigned64) GPR[rt] >> s;
1821   TRACE_ALU_RESULT (GPR[rd]);
1822 }
1823
1824
1825
1826 000000,5.RS,5.RT,5.RD,00000,010110:SPECIAL:64::DSRLV
1827 "dsrlv r<RD>, r<RT>, r<RS>"
1828 *mipsIII:
1829 *mipsIV:
1830 *mipsV:
1831 *mips64:
1832 *mips64r2:
1833 *vr4100:
1834 *vr5000:
1835 {
1836   check_u64 (SD_, instruction_0);
1837   do_dsrlv (SD_, RS, RT, RD);
1838 }
1839
1840
1841 000000,5.RS,5.RT,5.RD,00000,101110:SPECIAL:64::DSUB
1842 "dsub r<RD>, r<RS>, r<RT>"
1843 *mipsIII:
1844 *mipsIV:
1845 *mipsV:
1846 *mips64:
1847 *mips64r2:
1848 *vr4100:
1849 *vr5000:
1850 {
1851   check_u64 (SD_, instruction_0);
1852   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
1853   {
1854     ALU64_BEGIN (GPR[RS]);
1855     ALU64_SUB (GPR[RT]);
1856     ALU64_END (GPR[RD]);   /* This checks for overflow.  */
1857   }
1858   TRACE_ALU_RESULT (GPR[RD]);
1859 }
1860
1861
1862 :function:::void:do_dsubu:int rs, int rt, int rd
1863 {
1864   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
1865   GPR[rd] = GPR[rs] - GPR[rt];
1866   TRACE_ALU_RESULT (GPR[rd]);
1867 }
1868
1869 000000,5.RS,5.RT,5.RD,00000,101111:SPECIAL:64::DSUBU
1870 "dsubu r<RD>, r<RS>, r<RT>"
1871 *mipsIII:
1872 *mipsIV:
1873 *mipsV:
1874 *mips64:
1875 *mips64r2:
1876 *vr4100:
1877 *vr5000:
1878 {
1879   check_u64 (SD_, instruction_0);
1880   do_dsubu (SD_, RS, RT, RD);
1881 }
1882
1883
1884 000010,26.INSTR_INDEX:NORMAL:32::J
1885 "j <INSTR_INDEX>"
1886 *mipsI:
1887 *mipsII:
1888 *mipsIII:
1889 *mipsIV:
1890 *mipsV:
1891 *mips32:
1892 *mips32r2:
1893 *mips64:
1894 *mips64r2:
1895 *vr4100:
1896 *vr5000:
1897 *r3900:
1898 {
1899   /* NOTE: The region used is that of the delay slot NIA and NOT the
1900      current instruction */
1901   address_word region = (NIA & MASK (63, 28));
1902   DELAY_SLOT (region | (INSTR_INDEX << 2));
1903 }
1904
1905
1906 000011,26.INSTR_INDEX:NORMAL:32::JAL
1907 "jal <INSTR_INDEX>"
1908 *mipsI:
1909 *mipsII:
1910 *mipsIII:
1911 *mipsIV:
1912 *mipsV:
1913 *mips32:
1914 *mips32r2:
1915 *mips64:
1916 *mips64r2:
1917 *vr4100:
1918 *vr5000:
1919 *r3900:
1920 {
1921   /* NOTE: The region used is that of the delay slot and NOT the
1922      current instruction */
1923   address_word region = (NIA & MASK (63, 28));
1924   GPR[31] = CIA + 8;
1925   DELAY_SLOT (region | (INSTR_INDEX << 2));
1926 }
1927
1928 000000,5.RS,00000,5.RD,00000,001001:SPECIAL:32::JALR
1929 "jalr r<RS>":RD == 31
1930 "jalr r<RD>, r<RS>"
1931 *mipsI:
1932 *mipsII:
1933 *mipsIII:
1934 *mipsIV:
1935 *mipsV:
1936 *mips32:
1937 *mips32r2:
1938 *mips64:
1939 *mips64r2:
1940 *vr4100:
1941 *vr5000:
1942 *r3900:
1943 {
1944   address_word temp = GPR[RS];
1945   GPR[RD] = CIA + 8;
1946   DELAY_SLOT (temp);
1947 }
1948
1949 000000,5.RS,00000,5.RD,10000,001001:SPECIAL:32::JALR_HB
1950 "jalr.hb r<RS>":RD == 31
1951 "jalr.hb r<RD>, r<RS>"
1952 *mips32r2:
1953 *mips64r2:
1954 {
1955   address_word temp = GPR[RS];
1956   GPR[RD] = CIA + 8;
1957   DELAY_SLOT (temp);
1958 }
1959
1960 000000,5.RS,0000000000,00000,001000:SPECIAL:32::JR
1961 "jr r<RS>"
1962 *mipsI:
1963 *mipsII:
1964 *mipsIII:
1965 *mipsIV:
1966 *mipsV:
1967 *mips32:
1968 *mips32r2:
1969 *mips64:
1970 *mips64r2:
1971 *vr4100:
1972 *vr5000:
1973 *r3900:
1974 {
1975   DELAY_SLOT (GPR[RS]);
1976 }
1977
1978 000000,5.RS,0000000000,10000,001000:SPECIAL:32::JR_HB
1979 "jr.hb r<RS>"
1980 *mips32r2:
1981 *mips64r2:
1982 {
1983   DELAY_SLOT (GPR[RS]);
1984 }
1985
1986 :function:::unsigned_word:do_load:unsigned access, address_word base, address_word offset
1987 {
1988   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
1989   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
1990   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
1991   unsigned int byte;
1992   address_word paddr;
1993   int uncached;
1994   unsigned64 memval;
1995   address_word vaddr;
1996
1997   vaddr = loadstore_ea (SD_, base, offset);
1998   if ((vaddr & access) != 0)
1999     {
2000       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map, access+1, vaddr, read_transfer, sim_core_unaligned_signal);
2001     }
2002   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2003   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
2004   LoadMemory (&memval, NULL, uncached, access, paddr, vaddr, isDATA, isREAL);
2005   byte = ((vaddr & mask) ^ bigendiancpu);
2006   return (memval >> (8 * byte));
2007 }
2008
2009 :function:::unsigned_word:do_load_left:unsigned access, address_word base, address_word offset, unsigned_word rt
2010 {
2011   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2012   address_word reverseendian = (ReverseEndian ? -1 : 0);
2013   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2014   unsigned int byte;
2015   unsigned int word;
2016   address_word paddr;
2017   int uncached;
2018   unsigned64 memval;
2019   address_word vaddr;
2020   int nr_lhs_bits;
2021   int nr_rhs_bits;
2022   unsigned_word lhs_mask;
2023   unsigned_word temp;
2024
2025   vaddr = loadstore_ea (SD_, base, offset);
2026   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2027   paddr = (paddr ^ (reverseendian & mask));
2028   if (BigEndianMem == 0)
2029     paddr = paddr & ~access;
2030
2031   /* compute where within the word/mem we are */
2032   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
2033   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
2034   nr_lhs_bits = 8 * byte + 8;
2035   nr_rhs_bits = 8 * access - 8 * byte;
2036   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
2037
2038   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
2039            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
2040            (long) ((unsigned64) paddr >> 32), (long) paddr,
2041            word, byte, nr_lhs_bits, nr_rhs_bits); */
2042
2043   LoadMemory (&memval, NULL, uncached, byte, paddr, vaddr, isDATA, isREAL);
2044   if (word == 0)
2045     {
2046       /* GPR{31..32-NR_LHS_BITS} = memval{NR_LHS_BITS-1..0} */
2047       temp = (memval << nr_rhs_bits);
2048     }
2049   else
2050     {
2051       /* GPR{31..32-NR_LHS_BITS = memval{32+NR_LHS_BITS..32} */
2052       temp = (memval >> nr_lhs_bits);
2053     }
2054   lhs_mask = LSMASK (nr_lhs_bits + nr_rhs_bits - 1, nr_rhs_bits);
2055   rt = (rt & ~lhs_mask) | (temp & lhs_mask);
2056
2057   /* fprintf (stderr, "l[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx & 0x%08lx%08lx -> 0x%08lx%08lx\n",
2058            (long) ((unsigned64) memval >> 32), (long) memval,
2059            (long) ((unsigned64) temp >> 32), (long) temp,
2060            (long) ((unsigned64) lhs_mask >> 32), (long) lhs_mask,
2061            (long) (rt >> 32), (long) rt); */
2062   return rt;
2063 }
2064
2065 :function:::unsigned_word:do_load_right:unsigned access, address_word base, address_word offset, unsigned_word rt
2066 {
2067   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
2068   address_word reverseendian = (ReverseEndian ? -1 : 0);
2069   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
2070   unsigned int byte;
2071   address_word paddr;
2072   int uncached;
2073   unsigned64 memval;
2074   address_word vaddr;
2075
2076   vaddr = loadstore_ea (SD_, base, offset);
2077   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET, isREAL);
2078   /* NOTE: SPEC is wrong, has `BigEndianMem == 0' not `BigEndianMem != 0' */
2079   paddr = (paddr ^ (reverseendian & mask));
2080   if (BigEndianMem != 0)
2081     paddr = paddr & ~access;
2082   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
2083   /* NOTE: SPEC is wrong, had `byte' not `access - byte'.  See SW. */
2084   LoadMemory (&memval, NULL, uncached, access - (access & byte), paddr, vaddr, isDATA, isREAL);
2085   /* printf ("lr: 0x%08lx %d@0x%08lx 0x%08lx\n",
2086      (long) paddr, byte, (long) paddr, (long) memval); */
2087   {
2088     unsigned_word screen = LSMASK (8 * (access - (byte & access) + 1) - 1, 0);
2089     rt &= ~screen;
2090     rt |= (memval >> (8 * byte)) & screen;
2091   }
2092   return rt;
2093 }
2094
2095
2096 100000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LB
2097 "lb r<RT>, <OFFSET>(r<BASE>)"
2098 *mipsI:
2099 *mipsII:
2100 *mipsIII:
2101 *mipsIV:
2102 *mipsV:
2103 *mips32:
2104 *mips32r2:
2105 *mips64:
2106 *mips64r2:
2107 *vr4100:
2108 *vr5000:
2109 *r3900:
2110 {
2111   GPR[RT] = EXTEND8 (do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET)));
2112 }
2113
2114
2115 100100,5.BASE,5.RT,16.OFFSET:NORMAL:32::LBU
2116 "lbu r<RT>, <OFFSET>(r<BASE>)"
2117 *mipsI:
2118 *mipsII:
2119 *mipsIII:
2120 *mipsIV:
2121 *mipsV:
2122 *mips32:
2123 *mips32r2:
2124 *mips64:
2125 *mips64r2:
2126 *vr4100:
2127 *vr5000:
2128 *r3900:
2129 {
2130   GPR[RT] = do_load (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET));
2131 }
2132
2133
2134 110111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LD
2135 "ld r<RT>, <OFFSET>(r<BASE>)"
2136 *mipsIII:
2137 *mipsIV:
2138 *mipsV:
2139 *mips64:
2140 *mips64r2:
2141 *vr4100:
2142 *vr5000:
2143 {
2144   check_u64 (SD_, instruction_0);
2145   GPR[RT] = EXTEND64 (do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2146 }
2147
2148
2149 1101,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDCz
2150 "ldc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2151 *mipsII:
2152 *mipsIII:
2153 *mipsIV:
2154 *mipsV:
2155 *mips32:
2156 *mips32r2:
2157 *mips64:
2158 *mips64r2:
2159 *vr4100:
2160 *vr5000:
2161 *r3900:
2162 {
2163   COP_LD (ZZ, RT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
2164 }
2165
2166
2167
2168
2169 011010,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDL
2170 "ldl r<RT>, <OFFSET>(r<BASE>)"
2171 *mipsIII:
2172 *mipsIV:
2173 *mipsV:
2174 *mips64:
2175 *mips64r2:
2176 *vr4100:
2177 *vr5000:
2178 {
2179   check_u64 (SD_, instruction_0);
2180   GPR[RT] = do_load_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2181 }
2182
2183
2184 011011,5.BASE,5.RT,16.OFFSET:NORMAL:64::LDR
2185 "ldr r<RT>, <OFFSET>(r<BASE>)"
2186 *mipsIII:
2187 *mipsIV:
2188 *mipsV:
2189 *mips64:
2190 *mips64r2:
2191 *vr4100:
2192 *vr5000:
2193 {
2194   check_u64 (SD_, instruction_0);
2195   GPR[RT] = do_load_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
2196 }
2197
2198
2199 100001,5.BASE,5.RT,16.OFFSET:NORMAL:32::LH
2200 "lh r<RT>, <OFFSET>(r<BASE>)"
2201 *mipsI:
2202 *mipsII:
2203 *mipsIII:
2204 *mipsIV:
2205 *mipsV:
2206 *mips32:
2207 *mips32r2:
2208 *mips64:
2209 *mips64r2:
2210 *vr4100:
2211 *vr5000:
2212 *r3900:
2213 {
2214   GPR[RT] = EXTEND16 (do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET)));
2215 }
2216
2217
2218 100101,5.BASE,5.RT,16.OFFSET:NORMAL:32::LHU
2219 "lhu r<RT>, <OFFSET>(r<BASE>)"
2220 *mipsI:
2221 *mipsII:
2222 *mipsIII:
2223 *mipsIV:
2224 *mipsV:
2225 *mips32:
2226 *mips32r2:
2227 *mips64:
2228 *mips64r2:
2229 *vr4100:
2230 *vr5000:
2231 *r3900:
2232 {
2233   GPR[RT] = do_load (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET));
2234 }
2235
2236
2237 110000,5.BASE,5.RT,16.OFFSET:NORMAL:32::LL
2238 "ll r<RT>, <OFFSET>(r<BASE>)"
2239 *mipsII:
2240 *mipsIII:
2241 *mipsIV:
2242 *mipsV:
2243 *mips32:
2244 *mips32r2:
2245 *mips64:
2246 *mips64r2:
2247 *vr4100:
2248 *vr5000:
2249 {
2250   address_word base = GPR[BASE];
2251   address_word offset = EXTEND16 (OFFSET);
2252   {
2253     address_word vaddr = loadstore_ea (SD_, base, offset);
2254     address_word paddr;
2255     int uncached;
2256     if ((vaddr & 3) != 0)
2257       {
2258         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, read_transfer, sim_core_unaligned_signal);
2259       }
2260     else
2261       {
2262         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2263           {
2264             unsigned64 memval = 0;
2265             unsigned64 memval1 = 0;
2266             unsigned64 mask = 0x7;
2267             unsigned int shift = 2;
2268             unsigned int reverse = (ReverseEndian ? (mask >> shift) : 0);
2269             unsigned int bigend = (BigEndianCPU ? (mask >> shift) : 0);
2270             unsigned int byte;
2271             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (reverse << shift)));
2272             LoadMemory(&memval,&memval1,uncached,AccessLength_WORD,paddr,vaddr,isDATA,isREAL);
2273             byte = ((vaddr & mask) ^ (bigend << shift));
2274             GPR[RT] = EXTEND32 (memval >> (8 * byte));
2275             LLBIT = 1;
2276           }
2277       }
2278   }
2279 }
2280
2281
2282 110100,5.BASE,5.RT,16.OFFSET:NORMAL:64::LLD
2283 "lld r<RT>, <OFFSET>(r<BASE>)"
2284 *mipsIII:
2285 *mipsIV:
2286 *mipsV:
2287 *mips64:
2288 *mips64r2:
2289 *vr4100:
2290 *vr5000:
2291 {
2292   address_word base = GPR[BASE];
2293   address_word offset = EXTEND16 (OFFSET);
2294   check_u64 (SD_, instruction_0);
2295   {
2296     address_word vaddr = loadstore_ea (SD_, base, offset);
2297     address_word paddr;
2298     int uncached;
2299     if ((vaddr & 7) != 0)
2300       {
2301         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, read_transfer, sim_core_unaligned_signal);
2302       }
2303     else
2304       {
2305         if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
2306           {
2307             unsigned64 memval = 0;
2308             unsigned64 memval1 = 0;
2309             LoadMemory(&memval,&memval1,uncached,AccessLength_DOUBLEWORD,paddr,vaddr,isDATA,isREAL);
2310             GPR[RT] = memval;
2311             LLBIT = 1;
2312           }
2313       }
2314   }
2315 }
2316
2317
2318 001111,00000,5.RT,16.IMMEDIATE:NORMAL:32::LUI
2319 "lui r<RT>, %#lx<IMMEDIATE>"
2320 *mipsI:
2321 *mipsII:
2322 *mipsIII:
2323 *mipsIV:
2324 *mipsV:
2325 *mips32:
2326 *mips32r2:
2327 *mips64:
2328 *mips64r2:
2329 *vr4100:
2330 *vr5000:
2331 *r3900:
2332 {
2333   TRACE_ALU_INPUT1 (IMMEDIATE);
2334   GPR[RT] = EXTEND32 (IMMEDIATE << 16);
2335   TRACE_ALU_RESULT (GPR[RT]);
2336 }
2337
2338
2339 100011,5.BASE,5.RT,16.OFFSET:NORMAL:32::LW
2340 "lw r<RT>, <OFFSET>(r<BASE>)"
2341 *mipsI:
2342 *mipsII:
2343 *mipsIII:
2344 *mipsIV:
2345 *mipsV:
2346 *mips32:
2347 *mips32r2:
2348 *mips64:
2349 *mips64r2:
2350 *vr4100:
2351 *vr5000:
2352 *r3900:
2353 {
2354   GPR[RT] = EXTEND32 (do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2355 }
2356
2357
2358 1100,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWCz
2359 "lwc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
2360 *mipsI:
2361 *mipsII:
2362 *mipsIII:
2363 *mipsIV:
2364 *mipsV:
2365 *mips32:
2366 *mips32r2:
2367 *mips64:
2368 *mips64r2:
2369 *vr4100:
2370 *vr5000:
2371 *r3900:
2372 {
2373   COP_LW (ZZ, RT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
2374 }
2375
2376
2377 100010,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWL
2378 "lwl r<RT>, <OFFSET>(r<BASE>)"
2379 *mipsI:
2380 *mipsII:
2381 *mipsIII:
2382 *mipsIV:
2383 *mipsV:
2384 *mips32:
2385 *mips32r2:
2386 *mips64:
2387 *mips64r2:
2388 *vr4100:
2389 *vr5000:
2390 *r3900:
2391 {
2392   GPR[RT] = EXTEND32 (do_load_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2393 }
2394
2395
2396 100110,5.BASE,5.RT,16.OFFSET:NORMAL:32::LWR
2397 "lwr r<RT>, <OFFSET>(r<BASE>)"
2398 *mipsI:
2399 *mipsII:
2400 *mipsIII:
2401 *mipsIV:
2402 *mipsV:
2403 *mips32:
2404 *mips32r2:
2405 *mips64:
2406 *mips64r2:
2407 *vr4100:
2408 *vr5000:
2409 *r3900:
2410 {
2411   GPR[RT] = EXTEND32 (do_load_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]));
2412 }
2413
2414
2415 100111,5.BASE,5.RT,16.OFFSET:NORMAL:64::LWU
2416 "lwu r<RT>, <OFFSET>(r<BASE>)"
2417 *mipsIII:
2418 *mipsIV:
2419 *mipsV:
2420 *mips64:
2421 *mips64r2:
2422 *vr4100:
2423 *vr5000:
2424 {
2425   check_u64 (SD_, instruction_0);
2426   GPR[RT] = do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET));
2427 }
2428
2429
2430
2431 011100,5.RS,5.RT,00000,00000,000000:SPECIAL2:32::MADD
2432 "madd r<RS>, r<RT>"
2433 *mips32:
2434 *mips64:
2435 *vr5500:
2436 {
2437   signed64 temp;
2438   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2439   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2440     Unpredictable ();
2441   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2442   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2443           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2444   LO = EXTEND32 (temp);
2445   HI = EXTEND32 (VH4_8 (temp));
2446   TRACE_ALU_RESULT2 (HI, LO);
2447 }
2448
2449
2450 011100,5.RS,5.RT,000,2.AC,00000,000000:SPECIAL2:32::MADD
2451 "madd r<RS>, r<RT>":AC == 0
2452 "madd ac<AC>, r<RS>, r<RT>"
2453 *mips32r2:
2454 *mips64r2:
2455 *dsp2:
2456 {
2457   signed64 temp;
2458   if (AC == 0)
2459     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2460   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2461     Unpredictable ();
2462   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2463   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2464           + ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2465   DSPLO(AC) = EXTEND32 (temp);
2466   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2467   if (AC == 0)
2468     TRACE_ALU_RESULT2 (HI, LO);
2469 }
2470
2471
2472 011100,5.RS,5.RT,00000,00000,000001:SPECIAL2:32::MADDU
2473 "maddu r<RS>, r<RT>"
2474 *mips32:
2475 *mips64:
2476 *vr5500:
2477 {
2478   unsigned64 temp;
2479   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2480   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2481     Unpredictable ();
2482   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2483   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2484           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2485   ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
2486   LO = EXTEND32 (temp);
2487   HI = EXTEND32 (VH4_8 (temp));
2488   TRACE_ALU_RESULT2 (HI, LO);
2489 }
2490
2491
2492 011100,5.RS,5.RT,000,2.AC,00000,000001:SPECIAL2:32::MADDU
2493 "maddu r<RS>, r<RT>":AC == 0
2494 "maddu ac<AC>, r<RS>, r<RT>"
2495 *mips32r2:
2496 *mips64r2:
2497 *dsp2:
2498 {
2499   unsigned64 temp;
2500   if (AC == 0)
2501     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2502   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2503     Unpredictable ();
2504   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2505   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2506           + ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2507   if (AC == 0)
2508     ACX += U8_4 (VL4_8 (HI), VL4_8 (LO)) < temp;  /* SmartMIPS */
2509   DSPLO(AC) = EXTEND32 (temp);
2510   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2511   if (AC == 0)
2512     TRACE_ALU_RESULT2 (HI, LO);
2513 }
2514
2515
2516 :function:::void:do_mfhi:int rd
2517 {
2518   check_mf_hilo (SD_, HIHISTORY, LOHISTORY);
2519   TRACE_ALU_INPUT1 (HI);
2520   GPR[rd] = HI;
2521   TRACE_ALU_RESULT (GPR[rd]);
2522 }
2523
2524 000000,0000000000,5.RD,00000,010000:SPECIAL:32::MFHI
2525 "mfhi r<RD>"
2526 *mipsI:
2527 *mipsII:
2528 *mipsIII:
2529 *mipsIV:
2530 *mipsV:
2531 *vr4100:
2532 *vr5000:
2533 *r3900:
2534 *mips32:
2535 *mips64:
2536 {
2537   do_mfhi (SD_, RD);
2538 }
2539
2540
2541 000000,000,2.AC,00000,5.RD,00000,010000:SPECIAL:32::MFHI
2542 "mfhi r<RD>":AC == 0
2543 "mfhi r<RD>, ac<AC>"
2544 *mips32r2:
2545 *mips64r2:
2546 *dsp:
2547 {
2548   if (AC == 0)
2549     do_mfhi (SD_, RD);
2550   else
2551     GPR[RD] = DSPHI(AC);
2552 }
2553
2554
2555 :function:::void:do_mflo:int rd
2556 {
2557   check_mf_hilo (SD_, LOHISTORY, HIHISTORY);
2558   TRACE_ALU_INPUT1 (LO);
2559   GPR[rd] = LO;
2560   TRACE_ALU_RESULT (GPR[rd]);
2561 }
2562
2563 000000,0000000000,5.RD,00000,010010:SPECIAL:32::MFLO
2564 "mflo r<RD>"
2565 *mipsI:
2566 *mipsII:
2567 *mipsIII:
2568 *mipsIV:
2569 *mipsV:
2570 *vr4100:
2571 *vr5000:
2572 *r3900:
2573 *mips32:
2574 *mips64:
2575 {
2576   do_mflo (SD_, RD);
2577 }
2578
2579
2580 000000,000,2.AC,00000,5.RD,00000,010010:SPECIAL:32::MFLO
2581 "mflo r<RD>":AC == 0
2582 "mflo r<RD>, ac<AC>"
2583 *mips32r2:
2584 *mips64r2:
2585 *dsp:
2586 {
2587   if (AC == 0)
2588     do_mflo (SD_, RD);
2589   else
2590     GPR[RD] = DSPLO(AC);
2591 }
2592
2593
2594 000000,5.RS,5.RT,5.RD,00000,001011:SPECIAL:32::MOVN
2595 "movn r<RD>, r<RS>, r<RT>"
2596 *mipsIV:
2597 *mipsV:
2598 *mips32:
2599 *mips32r2:
2600 *mips64:
2601 *mips64r2:
2602 *vr5000:
2603 {
2604   if (GPR[RT] != 0)
2605     {
2606       GPR[RD] = GPR[RS];
2607       TRACE_ALU_RESULT (GPR[RD]);
2608     }
2609 }
2610
2611
2612
2613 000000,5.RS,5.RT,5.RD,00000,001010:SPECIAL:32::MOVZ
2614 "movz r<RD>, r<RS>, r<RT>"
2615 *mipsIV:
2616 *mipsV:
2617 *mips32:
2618 *mips32r2:
2619 *mips64:
2620 *mips64r2:
2621 *vr5000:
2622 {
2623   if (GPR[RT] == 0)
2624     {
2625       GPR[RD] = GPR[RS];
2626       TRACE_ALU_RESULT (GPR[RD]);
2627     }
2628 }
2629
2630
2631
2632 011100,5.RS,5.RT,00000,00000,000100:SPECIAL2:32::MSUB
2633 "msub r<RS>, r<RT>"
2634 *mips32:
2635 *mips64:
2636 *vr5500:
2637 {
2638   signed64 temp;
2639   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2640   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2641     Unpredictable ();
2642   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2643   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2644           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2645   LO = EXTEND32 (temp);
2646   HI = EXTEND32 (VH4_8 (temp));
2647   TRACE_ALU_RESULT2 (HI, LO);
2648 }
2649
2650
2651 011100,5.RS,5.RT,000,2.AC,00000,000100:SPECIAL2:32::MSUB
2652 "msub r<RS>, r<RT>":AC == 0
2653 "msub ac<AC>, r<RS>, r<RT>"
2654 *mips32r2:
2655 *mips64r2:
2656 *dsp2:
2657 {
2658   signed64 temp;
2659   if (AC == 0)
2660     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2661   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2662     Unpredictable ();
2663   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2664   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2665           - ((signed64) EXTEND32 (GPR[RT]) * (signed64) EXTEND32 (GPR[RS])));
2666   DSPLO(AC) = EXTEND32 (temp);
2667   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2668   if (AC == 0)
2669     TRACE_ALU_RESULT2 (HI, LO);
2670 }
2671
2672
2673 011100,5.RS,5.RT,00000,00000,000101:SPECIAL2:32::MSUBU
2674 "msubu r<RS>, r<RT>"
2675 *mips32:
2676 *mips64:
2677 *vr5500:
2678 {
2679   unsigned64 temp;
2680   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2681   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2682     Unpredictable ();
2683   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2684   temp = (U8_4 (VL4_8 (HI), VL4_8 (LO))
2685           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2686   LO = EXTEND32 (temp);
2687   HI = EXTEND32 (VH4_8 (temp));
2688   TRACE_ALU_RESULT2 (HI, LO);
2689 }
2690
2691
2692 011100,5.RS,5.RT,000,2.AC,00000,000101:SPECIAL2:32::MSUBU
2693 "msubu r<RS>, r<RT>":AC == 0
2694 "msubu ac<AC>, r<RS>, r<RT>"
2695 *mips32r2:
2696 *mips64r2:
2697 *dsp2:
2698 {
2699   unsigned64 temp;
2700   if (AC == 0)
2701     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2702   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2703     Unpredictable ();
2704   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2705   temp = (U8_4 (VL4_8 (DSPHI(AC)), VL4_8 (DSPLO(AC)))
2706           - ((unsigned64) VL4_8 (GPR[RS]) * (unsigned64) VL4_8 (GPR[RT])));
2707   DSPLO(AC) = EXTEND32 (temp);
2708   DSPHI(AC) = EXTEND32 (VH4_8 (temp));
2709   if (AC == 0)
2710     TRACE_ALU_RESULT2 (HI, LO);
2711 }
2712
2713
2714 000000,5.RS,000000000000000,010001:SPECIAL:32::MTHI
2715 "mthi r<RS>"
2716 *mipsI:
2717 *mipsII:
2718 *mipsIII:
2719 *mipsIV:
2720 *mipsV:
2721 *vr4100:
2722 *vr5000:
2723 *r3900:
2724 *mips32:
2725 *mips64:
2726 {
2727   check_mt_hilo (SD_, HIHISTORY);
2728   HI = GPR[RS];
2729 }
2730
2731
2732 000000,5.RS,00000,000,2.AC,00000,010001:SPECIAL:32::MTHI
2733 "mthi r<RS>":AC == 0
2734 "mthi r<RS>, ac<AC>"
2735 *mips32r2:
2736 *mips64r2:
2737 *dsp:
2738 {
2739   if (AC == 0)
2740     check_mt_hilo (SD_, HIHISTORY);
2741   DSPHI(AC) = GPR[RS];
2742 }
2743
2744
2745 000000,5.RS,000000000000000,010011:SPECIAL:32::MTLO
2746 "mtlo r<RS>"
2747 *mipsI:
2748 *mipsII:
2749 *mipsIII:
2750 *mipsIV:
2751 *mipsV:
2752 *vr4100:
2753 *vr5000:
2754 *r3900:
2755 *mips32:
2756 *mips64:
2757 {
2758   check_mt_hilo (SD_, LOHISTORY);
2759   LO = GPR[RS];
2760 }
2761
2762
2763 000000,5.RS,00000,000,2.AC,00000,010011:SPECIAL:32::MTLO
2764 "mtlo r<RS>":AC == 0
2765 "mtlo r<RS>, ac<AC>"
2766 *mips32r2:
2767 *mips64r2:
2768 *dsp:
2769 {
2770   if (AC == 0)
2771     check_mt_hilo (SD_, LOHISTORY);
2772   DSPLO(AC) = GPR[RS];
2773 }
2774
2775
2776 011100,5.RS,5.RT,5.RD,00000,000010:SPECIAL2:32::MUL
2777 "mul r<RD>, r<RS>, r<RT>"
2778 *mips32:
2779 *mips32r2:
2780 *mips64:
2781 *mips64r2:
2782 *vr5500:
2783 {
2784   signed64 prod;
2785   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2786     Unpredictable ();
2787   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2788   prod = (((signed64)(signed32) GPR[RS])
2789           * ((signed64)(signed32) GPR[RT]));
2790   GPR[RD] = EXTEND32 (VL4_8 (prod));
2791   TRACE_ALU_RESULT (GPR[RD]);
2792 }
2793
2794
2795
2796 :function:::void:do_mult:int rs, int rt, int rd
2797 {
2798   signed64 prod;
2799   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2800   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2801     Unpredictable ();
2802   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2803   prod = (((signed64)(signed32) GPR[rs])
2804           * ((signed64)(signed32) GPR[rt]));
2805   LO = EXTEND32 (VL4_8 (prod));
2806   HI = EXTEND32 (VH4_8 (prod));
2807   ACX = 0;  /* SmartMIPS */
2808   if (rd != 0)
2809     GPR[rd] = LO;
2810   TRACE_ALU_RESULT2 (HI, LO);
2811 }
2812
2813 000000,5.RS,5.RT,0000000000,011000:SPECIAL:32::MULT
2814 "mult r<RS>, r<RT>"
2815 *mipsI:
2816 *mipsII:
2817 *mipsIII:
2818 *mipsIV:
2819 *mipsV:
2820 *mips32:
2821 *mips64:
2822 *vr4100:
2823 {
2824   do_mult (SD_, RS, RT, 0);
2825 }
2826
2827
2828 000000,5.RS,5.RT,000,2.AC,00000,011000:SPECIAL:32::MULT
2829 "mult r<RS>, r<RT>":AC == 0
2830 "mult ac<AC>, r<RS>, r<RT>"
2831 *mips32r2:
2832 *mips64r2:
2833 *dsp2:
2834 {
2835   signed64 prod;
2836   if (AC == 0)
2837     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2838   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2839     Unpredictable ();
2840   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2841   prod = ((signed64)(signed32) GPR[RS])
2842           * ((signed64)(signed32) GPR[RT]);
2843   DSPLO(AC) = EXTEND32 (VL4_8 (prod));
2844   DSPHI(AC) = EXTEND32 (VH4_8 (prod));
2845   if (AC == 0)
2846     {
2847       ACX = 0;  /* SmartMIPS */
2848       TRACE_ALU_RESULT2 (HI, LO);
2849     }
2850 }
2851
2852
2853 000000,5.RS,5.RT,5.RD,00000,011000:SPECIAL:32::MULT
2854 "mult r<RS>, r<RT>":RD == 0
2855 "mult r<RD>, r<RS>, r<RT>"
2856 *vr5000:
2857 *r3900:
2858 {
2859   do_mult (SD_, RS, RT, RD);
2860 }
2861
2862
2863 :function:::void:do_multu:int rs, int rt, int rd
2864 {
2865   unsigned64 prod;
2866   check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2867   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
2868     Unpredictable ();
2869   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2870   prod = (((unsigned64)(unsigned32) GPR[rs])
2871           * ((unsigned64)(unsigned32) GPR[rt]));
2872   LO = EXTEND32 (VL4_8 (prod));
2873   HI = EXTEND32 (VH4_8 (prod));
2874   if (rd != 0)
2875     GPR[rd] = LO;
2876   TRACE_ALU_RESULT2 (HI, LO);
2877 }
2878
2879 000000,5.RS,5.RT,0000000000,011001:SPECIAL:32::MULTU
2880 "multu r<RS>, r<RT>"
2881 *mipsI:
2882 *mipsII:
2883 *mipsIII:
2884 *mipsIV:
2885 *mipsV:
2886 *mips32:
2887 *mips64:
2888 *vr4100:
2889 {
2890   do_multu (SD_, RS, RT, 0);
2891 }
2892
2893
2894 000000,5.RS,5.RT,000,2.AC,00000,011001:SPECIAL:32::MULTU
2895 "multu r<RS>, r<RT>":AC == 0
2896 "multu r<RS>, r<RT>"
2897 *mips32r2:
2898 *mips64r2:
2899 *dsp2:
2900 {
2901   unsigned64 prod;
2902   if (AC == 0)
2903     check_mult_hilo (SD_, HIHISTORY, LOHISTORY);
2904   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
2905     Unpredictable ();
2906   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
2907   prod = ((unsigned64)(unsigned32) GPR[RS])
2908           * ((unsigned64)(unsigned32) GPR[RT]);
2909   DSPLO(AC) = EXTEND32 (VL4_8 (prod));
2910   DSPHI(AC) = EXTEND32 (VH4_8 (prod));
2911   if (AC == 0)
2912     TRACE_ALU_RESULT2 (HI, LO);
2913 }
2914
2915
2916 000000,5.RS,5.RT,5.RD,00000,011001:SPECIAL:32::MULTU
2917 "multu r<RS>, r<RT>":RD == 0
2918 "multu r<RD>, r<RS>, r<RT>"
2919 *vr5000:
2920 *r3900:
2921 {
2922   do_multu (SD_, RS, RT, RD);
2923 }
2924
2925
2926 :function:::void:do_nor:int rs, int rt, int rd
2927 {
2928   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2929   GPR[rd] = ~ (GPR[rs] | GPR[rt]);
2930   TRACE_ALU_RESULT (GPR[rd]);
2931 }
2932
2933 000000,5.RS,5.RT,5.RD,00000,100111:SPECIAL:32::NOR
2934 "nor r<RD>, r<RS>, r<RT>"
2935 *mipsI:
2936 *mipsII:
2937 *mipsIII:
2938 *mipsIV:
2939 *mipsV:
2940 *mips32:
2941 *mips32r2:
2942 *mips64:
2943 *mips64r2:
2944 *vr4100:
2945 *vr5000:
2946 *r3900:
2947 {
2948   do_nor (SD_, RS, RT, RD);
2949 }
2950
2951
2952 :function:::void:do_or:int rs, int rt, int rd
2953 {
2954   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
2955   GPR[rd] = (GPR[rs] | GPR[rt]);
2956   TRACE_ALU_RESULT (GPR[rd]);
2957 }
2958
2959 000000,5.RS,5.RT,5.RD,00000,100101:SPECIAL:32::OR
2960 "or r<RD>, r<RS>, r<RT>"
2961 *mipsI:
2962 *mipsII:
2963 *mipsIII:
2964 *mipsIV:
2965 *mipsV:
2966 *mips32:
2967 *mips32r2:
2968 *mips64:
2969 *mips64r2:
2970 *vr4100:
2971 *vr5000:
2972 *r3900:
2973 {
2974   do_or (SD_, RS, RT, RD);
2975 }
2976
2977
2978
2979 :function:::void:do_ori:int rs, int rt, unsigned immediate
2980 {
2981   TRACE_ALU_INPUT2 (GPR[rs], immediate);
2982   GPR[rt] = (GPR[rs] | immediate);
2983   TRACE_ALU_RESULT (GPR[rt]);
2984 }
2985
2986 001101,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::ORI
2987 "ori r<RT>, r<RS>, %#lx<IMMEDIATE>"
2988 *mipsI:
2989 *mipsII:
2990 *mipsIII:
2991 *mipsIV:
2992 *mipsV:
2993 *mips32:
2994 *mips32r2:
2995 *mips64:
2996 *mips64r2:
2997 *vr4100:
2998 *vr5000:
2999 *r3900:
3000 {
3001   do_ori (SD_, RS, RT, IMMEDIATE);
3002 }
3003
3004
3005 110011,5.BASE,5.HINT,16.OFFSET:NORMAL:32::PREF
3006 "pref <HINT>, <OFFSET>(r<BASE>)"
3007 *mipsIV:
3008 *mipsV:
3009 *mips32:
3010 *mips32r2:
3011 *mips64:
3012 *mips64r2:
3013 *vr5000:
3014 {
3015   address_word base = GPR[BASE];
3016   address_word offset = EXTEND16 (OFFSET);
3017   {
3018     address_word vaddr = loadstore_ea (SD_, base, offset);
3019     address_word paddr;
3020     int uncached;
3021     {
3022       if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
3023         Prefetch(uncached,paddr,vaddr,isDATA,HINT);
3024     }
3025   }
3026 }
3027
3028
3029 :function:::unsigned64:do_ror:unsigned32 x,unsigned32 y
3030 {
3031   unsigned64 result;
3032
3033   y &= 31;
3034   TRACE_ALU_INPUT2 (x, y);
3035   result = EXTEND32 (ROTR32 (x, y));
3036   TRACE_ALU_RESULT (result);
3037   return result;
3038 }
3039
3040 000000,00001,5.RT,5.RD,5.SHIFT,000010::32::ROR
3041 "ror r<RD>, r<RT>, <SHIFT>"
3042 *mips32r2:
3043 *mips64r2:
3044 *smartmips:
3045 *vr5400:
3046 *vr5500:
3047 {
3048   GPR[RD] = do_ror (SD_, GPR[RT], SHIFT);
3049 }
3050
3051 000000,5.RS,5.RT,5.RD,00001,000110::32::RORV
3052 "rorv r<RD>, r<RT>, r<RS>"
3053 *mips32r2:
3054 *mips64r2:
3055 *smartmips:
3056 *vr5400:
3057 *vr5500:
3058 {
3059   GPR[RD] = do_ror (SD_, GPR[RT], GPR[RS]);
3060 }
3061
3062
3063 :function:::void:do_store:unsigned access, address_word base, address_word offset, unsigned_word word
3064 {
3065   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3066   address_word reverseendian = (ReverseEndian ? (mask ^ access) : 0);
3067   address_word bigendiancpu = (BigEndianCPU ? (mask ^ access) : 0);
3068   unsigned int byte;
3069   address_word paddr;
3070   int uncached;
3071   unsigned64 memval;
3072   address_word vaddr;
3073
3074   vaddr = loadstore_ea (SD_, base, offset);
3075   if ((vaddr & access) != 0)
3076     {
3077       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map, access+1, vaddr, write_transfer, sim_core_unaligned_signal);
3078     }
3079   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3080   paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
3081   byte = ((vaddr & mask) ^ bigendiancpu);
3082   memval = (word << (8 * byte));
3083   StoreMemory (uncached, access, memval, 0, paddr, vaddr, isREAL);
3084 }
3085
3086 :function:::void:do_store_left:unsigned access, address_word base, address_word offset, unsigned_word rt
3087 {
3088   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3089   address_word reverseendian = (ReverseEndian ? -1 : 0);
3090   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3091   unsigned int byte;
3092   unsigned int word;
3093   address_word paddr;
3094   int uncached;
3095   unsigned64 memval;
3096   address_word vaddr;
3097   int nr_lhs_bits;
3098   int nr_rhs_bits;
3099
3100   vaddr = loadstore_ea (SD_, base, offset);
3101   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3102   paddr = (paddr ^ (reverseendian & mask));
3103   if (BigEndianMem == 0)
3104     paddr = paddr & ~access;
3105
3106   /* compute where within the word/mem we are */
3107   byte = ((vaddr ^ bigendiancpu) & access); /* 0..access */
3108   word = ((vaddr ^ bigendiancpu) & (mask & ~access)) / (access + 1); /* 0..1 */
3109   nr_lhs_bits = 8 * byte + 8;
3110   nr_rhs_bits = 8 * access - 8 * byte;
3111   /* nr_lhs_bits + nr_rhs_bits == 8 * (accesss + 1) */
3112   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx 0x%08lx%08lx %d:%d %d+%d\n",
3113            (long) ((unsigned64) vaddr >> 32), (long) vaddr,
3114            (long) ((unsigned64) paddr >> 32), (long) paddr,
3115            word, byte, nr_lhs_bits, nr_rhs_bits); */
3116
3117   if (word == 0)
3118     {
3119       memval = (rt >> nr_rhs_bits);
3120     }
3121   else
3122     {
3123       memval = (rt << nr_lhs_bits);
3124     }
3125   /* fprintf (stderr, "s[wd]l: 0x%08lx%08lx -> 0x%08lx%08lx\n",
3126            (long) ((unsigned64) rt >> 32), (long) rt,
3127            (long) ((unsigned64) memval >> 32), (long) memval); */
3128   StoreMemory (uncached, byte, memval, 0, paddr, vaddr, isREAL);
3129 }
3130
3131 :function:::void:do_store_right:unsigned access, address_word base, address_word offset, unsigned_word rt
3132 {
3133   address_word mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
3134   address_word reverseendian = (ReverseEndian ? -1 : 0);
3135   address_word bigendiancpu = (BigEndianCPU ? -1 : 0);
3136   unsigned int byte;
3137   address_word paddr;
3138   int uncached;
3139   unsigned64 memval;
3140   address_word vaddr;
3141
3142   vaddr = loadstore_ea (SD_, base, offset);
3143   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET, isREAL);
3144   paddr = (paddr ^ (reverseendian & mask));
3145   if (BigEndianMem != 0)
3146     paddr &= ~access;
3147   byte = ((vaddr & mask) ^ (bigendiancpu & mask));
3148   memval = (rt << (byte * 8));
3149   StoreMemory (uncached, access - (access & byte), memval, 0, paddr, vaddr, isREAL);
3150 }
3151
3152
3153 101000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SB
3154 "sb r<RT>, <OFFSET>(r<BASE>)"
3155 *mipsI:
3156 *mipsII:
3157 *mipsIII:
3158 *mipsIV:
3159 *mipsV:
3160 *mips32:
3161 *mips32r2:
3162 *mips64:
3163 *mips64r2:
3164 *vr4100:
3165 *vr5000:
3166 *r3900:
3167 {
3168   do_store (SD_, AccessLength_BYTE, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3169 }
3170
3171
3172 111000,5.BASE,5.RT,16.OFFSET:NORMAL:32::SC
3173 "sc r<RT>, <OFFSET>(r<BASE>)"
3174 *mipsII:
3175 *mipsIII:
3176 *mipsIV:
3177 *mipsV:
3178 *mips32:
3179 *mips32r2:
3180 *mips64:
3181 *mips64r2:
3182 *vr4100:
3183 *vr5000:
3184 {
3185   unsigned32 instruction = instruction_0;
3186   address_word base = GPR[BASE];
3187   address_word offset = EXTEND16 (OFFSET);
3188   {
3189     address_word vaddr = loadstore_ea (SD_, base, offset);
3190     address_word paddr;
3191     int uncached;
3192     if ((vaddr & 3) != 0)
3193       {
3194         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
3195       }
3196     else
3197       {
3198         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3199           {
3200             unsigned64 memval = 0;
3201             unsigned64 memval1 = 0;
3202             unsigned64 mask = 0x7;
3203             unsigned int byte;
3204             paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
3205             byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
3206             memval = ((unsigned64) GPR[RT] << (8 * byte));
3207             if (LLBIT)
3208               {
3209                 StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
3210               }
3211             GPR[RT] = LLBIT;
3212           }
3213       }
3214   }
3215 }
3216
3217
3218 111100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SCD
3219 "scd r<RT>, <OFFSET>(r<BASE>)"
3220 *mipsIII:
3221 *mipsIV:
3222 *mipsV:
3223 *mips64:
3224 *mips64r2:
3225 *vr4100:
3226 *vr5000:
3227 {
3228   address_word base = GPR[BASE];
3229   address_word offset = EXTEND16 (OFFSET);
3230   check_u64 (SD_, instruction_0);
3231   {
3232     address_word vaddr = loadstore_ea (SD_, base, offset);
3233     address_word paddr;
3234     int uncached;
3235     if ((vaddr & 7) != 0)
3236       {
3237         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 8, vaddr, write_transfer, sim_core_unaligned_signal);
3238       }
3239     else
3240       {
3241         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
3242           {
3243             unsigned64 memval = 0;
3244             unsigned64 memval1 = 0;
3245             memval = GPR[RT];
3246             if (LLBIT)
3247               {
3248                 StoreMemory(uncached,AccessLength_DOUBLEWORD,memval,memval1,paddr,vaddr,isREAL);
3249               }
3250             GPR[RT] = LLBIT;
3251           }
3252       }
3253   }
3254 }
3255
3256
3257 111111,5.BASE,5.RT,16.OFFSET:NORMAL:64::SD
3258 "sd r<RT>, <OFFSET>(r<BASE>)"
3259 *mipsIII:
3260 *mipsIV:
3261 *mipsV:
3262 *mips64:
3263 *mips64r2:
3264 *vr4100:
3265 *vr5000:
3266 {
3267   check_u64 (SD_, instruction_0);
3268   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3269 }
3270
3271
3272 1111,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDCz
3273 "sdc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3274 *mipsII:
3275 *mipsIII:
3276 *mipsIV:
3277 *mipsV:
3278 *mips32:
3279 *mips32r2:
3280 *mips64:
3281 *mips64r2:
3282 *vr4100:
3283 *vr5000:
3284 {
3285   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (ZZ, RT));
3286 }
3287
3288
3289 101100,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDL
3290 "sdl r<RT>, <OFFSET>(r<BASE>)"
3291 *mipsIII:
3292 *mipsIV:
3293 *mipsV:
3294 *mips64:
3295 *mips64r2:
3296 *vr4100:
3297 *vr5000:
3298 {
3299   check_u64 (SD_, instruction_0);
3300   do_store_left (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3301 }
3302
3303
3304 101101,5.BASE,5.RT,16.OFFSET:NORMAL:64::SDR
3305 "sdr r<RT>, <OFFSET>(r<BASE>)"
3306 *mipsIII:
3307 *mipsIV:
3308 *mipsV:
3309 *mips64:
3310 *mips64r2:
3311 *vr4100:
3312 *vr5000:
3313 {
3314   check_u64 (SD_, instruction_0);
3315   do_store_right (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3316 }
3317
3318
3319
3320 101001,5.BASE,5.RT,16.OFFSET:NORMAL:32::SH
3321 "sh r<RT>, <OFFSET>(r<BASE>)"
3322 *mipsI:
3323 *mipsII:
3324 *mipsIII:
3325 *mipsIV:
3326 *mipsV:
3327 *mips32:
3328 *mips32r2:
3329 *mips64:
3330 *mips64r2:
3331 *vr4100:
3332 *vr5000:
3333 *r3900:
3334 {
3335   do_store (SD_, AccessLength_HALFWORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3336 }
3337
3338
3339 :function:::void:do_sll:int rt, int rd, int shift
3340 {
3341   unsigned32 temp = (GPR[rt] << shift);
3342   TRACE_ALU_INPUT2 (GPR[rt], shift);
3343   GPR[rd] = EXTEND32 (temp);
3344   TRACE_ALU_RESULT (GPR[rd]);
3345 }
3346
3347 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLa
3348 "nop":RD == 0 && RT == 0 && SHIFT == 0
3349 "sll r<RD>, r<RT>, <SHIFT>"
3350 *mipsI:
3351 *mipsII:
3352 *mipsIII:
3353 *mipsIV:
3354 *mipsV:
3355 *vr4100:
3356 *vr5000:
3357 *r3900:
3358 {
3359   /* Skip shift for NOP, so that there won't be lots of extraneous
3360      trace output.  */
3361   if (RD != 0 || RT != 0 || SHIFT != 0)
3362     do_sll (SD_, RT, RD, SHIFT);
3363 }
3364
3365 000000,00000,5.RT,5.RD,5.SHIFT,000000:SPECIAL:32::SLLb
3366 "nop":RD == 0 && RT == 0 && SHIFT == 0
3367 "ssnop":RD == 0 && RT == 0 && SHIFT == 1
3368 "sll r<RD>, r<RT>, <SHIFT>"
3369 *mips32:
3370 *mips32r2:
3371 *mips64:
3372 *mips64r2:
3373 {
3374   /* Skip shift for NOP and SSNOP, so that there won't be lots of
3375      extraneous trace output.  */
3376   if (RD != 0 || RT != 0 || (SHIFT != 0 && SHIFT != 1))
3377     do_sll (SD_, RT, RD, SHIFT);
3378 }
3379
3380
3381 :function:::void:do_sllv:int rs, int rt, int rd
3382 {
3383   int s = MASKED (GPR[rs], 4, 0);
3384   unsigned32 temp = (GPR[rt] << s);
3385   TRACE_ALU_INPUT2 (GPR[rt], s);
3386   GPR[rd] = EXTEND32 (temp);
3387   TRACE_ALU_RESULT (GPR[rd]);
3388 }
3389
3390 000000,5.RS,5.RT,5.RD,00000,000100:SPECIAL:32::SLLV
3391 "sllv r<RD>, r<RT>, r<RS>"
3392 *mipsI:
3393 *mipsII:
3394 *mipsIII:
3395 *mipsIV:
3396 *mipsV:
3397 *mips32:
3398 *mips32r2:
3399 *mips64:
3400 *mips64r2:
3401 *vr4100:
3402 *vr5000:
3403 *r3900:
3404 {
3405   do_sllv (SD_, RS, RT, RD);
3406 }
3407
3408
3409 :function:::void:do_slt:int rs, int rt, int rd
3410 {
3411   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3412   GPR[rd] = ((signed_word) GPR[rs] < (signed_word) GPR[rt]);
3413   TRACE_ALU_RESULT (GPR[rd]);
3414 }
3415
3416 000000,5.RS,5.RT,5.RD,00000,101010:SPECIAL:32::SLT
3417 "slt r<RD>, r<RS>, r<RT>"
3418 *mipsI:
3419 *mipsII:
3420 *mipsIII:
3421 *mipsIV:
3422 *mipsV:
3423 *mips32:
3424 *mips32r2:
3425 *mips64:
3426 *mips64r2:
3427 *vr4100:
3428 *vr5000:
3429 *r3900:
3430 {
3431   do_slt (SD_, RS, RT, RD);
3432 }
3433
3434
3435 :function:::void:do_slti:int rs, int rt, unsigned16 immediate
3436 {
3437   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3438   GPR[rt] = ((signed_word) GPR[rs] < (signed_word) EXTEND16 (immediate));
3439   TRACE_ALU_RESULT (GPR[rt]);
3440 }
3441
3442 001010,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTI
3443 "slti r<RT>, r<RS>, <IMMEDIATE>"
3444 *mipsI:
3445 *mipsII:
3446 *mipsIII:
3447 *mipsIV:
3448 *mipsV:
3449 *mips32:
3450 *mips32r2:
3451 *mips64:
3452 *mips64r2:
3453 *vr4100:
3454 *vr5000:
3455 *r3900:
3456 {
3457   do_slti (SD_, RS, RT, IMMEDIATE);
3458 }
3459
3460
3461 :function:::void:do_sltiu:int rs, int rt, unsigned16 immediate
3462 {
3463   TRACE_ALU_INPUT2 (GPR[rs], EXTEND16 (immediate));
3464   GPR[rt] = ((unsigned_word) GPR[rs] < (unsigned_word) EXTEND16 (immediate));
3465   TRACE_ALU_RESULT (GPR[rt]);
3466 }
3467
3468 001011,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::SLTIU
3469 "sltiu r<RT>, r<RS>, <IMMEDIATE>"
3470 *mipsI:
3471 *mipsII:
3472 *mipsIII:
3473 *mipsIV:
3474 *mipsV:
3475 *mips32:
3476 *mips32r2:
3477 *mips64:
3478 *mips64r2:
3479 *vr4100:
3480 *vr5000:
3481 *r3900:
3482 {
3483   do_sltiu (SD_, RS, RT, IMMEDIATE);
3484 }
3485
3486
3487
3488 :function:::void:do_sltu:int rs, int rt, int rd
3489 {
3490   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3491   GPR[rd] = ((unsigned_word) GPR[rs] < (unsigned_word) GPR[rt]);
3492   TRACE_ALU_RESULT (GPR[rd]);
3493 }
3494
3495 000000,5.RS,5.RT,5.RD,00000,101011:SPECIAL:32::SLTU
3496 "sltu r<RD>, r<RS>, r<RT>"
3497 *mipsI:
3498 *mipsII:
3499 *mipsIII:
3500 *mipsIV:
3501 *mipsV:
3502 *mips32:
3503 *mips32r2:
3504 *mips64:
3505 *mips64r2:
3506 *vr4100:
3507 *vr5000:
3508 *r3900:
3509 {
3510   do_sltu (SD_, RS, RT, RD);
3511 }
3512
3513
3514 :function:::void:do_sra:int rt, int rd, int shift
3515 {
3516   signed32 temp = (signed32) GPR[rt] >> shift;
3517   if (NotWordValue (GPR[rt]))
3518     Unpredictable ();
3519   TRACE_ALU_INPUT2 (GPR[rt], shift);
3520   GPR[rd] = EXTEND32 (temp);
3521   TRACE_ALU_RESULT (GPR[rd]);
3522 }
3523
3524 000000,00000,5.RT,5.RD,5.SHIFT,000011:SPECIAL:32::SRA
3525 "sra r<RD>, r<RT>, <SHIFT>"
3526 *mipsI:
3527 *mipsII:
3528 *mipsIII:
3529 *mipsIV:
3530 *mipsV:
3531 *mips32:
3532 *mips32r2:
3533 *mips64:
3534 *mips64r2:
3535 *vr4100:
3536 *vr5000:
3537 *r3900:
3538 {
3539   do_sra (SD_, RT, RD, SHIFT);
3540 }
3541
3542
3543
3544 :function:::void:do_srav:int rs, int rt, int rd
3545 {
3546   int s = MASKED (GPR[rs], 4, 0);
3547   signed32 temp = (signed32) GPR[rt] >> s;
3548   if (NotWordValue (GPR[rt]))
3549     Unpredictable ();
3550   TRACE_ALU_INPUT2 (GPR[rt], s);
3551   GPR[rd] = EXTEND32 (temp);
3552   TRACE_ALU_RESULT (GPR[rd]);
3553 }
3554
3555 000000,5.RS,5.RT,5.RD,00000,000111:SPECIAL:32::SRAV
3556 "srav r<RD>, r<RT>, r<RS>"
3557 *mipsI:
3558 *mipsII:
3559 *mipsIII:
3560 *mipsIV:
3561 *mipsV:
3562 *mips32:
3563 *mips32r2:
3564 *mips64:
3565 *mips64r2:
3566 *vr4100:
3567 *vr5000:
3568 *r3900:
3569 {
3570   do_srav (SD_, RS, RT, RD);
3571 }
3572
3573
3574
3575 :function:::void:do_srl:int rt, int rd, int shift
3576 {
3577   unsigned32 temp = (unsigned32) GPR[rt] >> shift;
3578   if (NotWordValue (GPR[rt]))
3579     Unpredictable ();
3580   TRACE_ALU_INPUT2 (GPR[rt], shift);
3581   GPR[rd] = EXTEND32 (temp);
3582   TRACE_ALU_RESULT (GPR[rd]);
3583 }
3584
3585 000000,00000,5.RT,5.RD,5.SHIFT,000010:SPECIAL:32::SRL
3586 "srl r<RD>, r<RT>, <SHIFT>"
3587 *mipsI:
3588 *mipsII:
3589 *mipsIII:
3590 *mipsIV:
3591 *mipsV:
3592 *mips32:
3593 *mips32r2:
3594 *mips64:
3595 *mips64r2:
3596 *vr4100:
3597 *vr5000:
3598 *r3900:
3599 {
3600   do_srl (SD_, RT, RD, SHIFT);
3601 }
3602
3603
3604 :function:::void:do_srlv:int rs, int rt, int rd
3605 {
3606   int s = MASKED (GPR[rs], 4, 0);
3607   unsigned32 temp = (unsigned32) GPR[rt] >> s;
3608   if (NotWordValue (GPR[rt]))
3609     Unpredictable ();
3610   TRACE_ALU_INPUT2 (GPR[rt], s);
3611   GPR[rd] = EXTEND32 (temp);
3612   TRACE_ALU_RESULT (GPR[rd]);
3613 }
3614
3615 000000,5.RS,5.RT,5.RD,00000,000110:SPECIAL:32::SRLV
3616 "srlv r<RD>, r<RT>, r<RS>"
3617 *mipsI:
3618 *mipsII:
3619 *mipsIII:
3620 *mipsIV:
3621 *mipsV:
3622 *mips32:
3623 *mips32r2:
3624 *mips64:
3625 *mips64r2:
3626 *vr4100:
3627 *vr5000:
3628 *r3900:
3629 {
3630   do_srlv (SD_, RS, RT, RD);
3631 }
3632
3633
3634 000000,5.RS,5.RT,5.RD,00000,100010:SPECIAL:32::SUB
3635 "sub r<RD>, r<RS>, r<RT>"
3636 *mipsI:
3637 *mipsII:
3638 *mipsIII:
3639 *mipsIV:
3640 *mipsV:
3641 *mips32:
3642 *mips32r2:
3643 *mips64:
3644 *mips64r2:
3645 *vr4100:
3646 *vr5000:
3647 *r3900:
3648 {
3649   if (NotWordValue (GPR[RS]) || NotWordValue (GPR[RT]))
3650     Unpredictable ();
3651   TRACE_ALU_INPUT2 (GPR[RS], GPR[RT]);
3652   {
3653     ALU32_BEGIN (GPR[RS]);
3654     ALU32_SUB (GPR[RT]);
3655     ALU32_END (GPR[RD]);   /* This checks for overflow.  */
3656   }
3657   TRACE_ALU_RESULT (GPR[RD]);
3658 }
3659
3660
3661 :function:::void:do_subu:int rs, int rt, int rd
3662 {
3663   if (NotWordValue (GPR[rs]) || NotWordValue (GPR[rt]))
3664     Unpredictable ();
3665   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
3666   GPR[rd] = EXTEND32 (GPR[rs] - GPR[rt]);
3667   TRACE_ALU_RESULT (GPR[rd]);
3668 }
3669
3670 000000,5.RS,5.RT,5.RD,00000,100011:SPECIAL:32::SUBU
3671 "subu r<RD>, r<RS>, r<RT>"
3672 *mipsI:
3673 *mipsII:
3674 *mipsIII:
3675 *mipsIV:
3676 *mipsV:
3677 *mips32:
3678 *mips32r2:
3679 *mips64:
3680 *mips64r2:
3681 *vr4100:
3682 *vr5000:
3683 *r3900:
3684 {
3685   do_subu (SD_, RS, RT, RD);
3686 }
3687
3688
3689 101011,5.BASE,5.RT,16.OFFSET:NORMAL:32::SW
3690 "sw r<RT>, <OFFSET>(r<BASE>)"
3691 *mipsI:
3692 *mipsII:
3693 *mipsIII:
3694 *mipsIV:
3695 *mipsV:
3696 *mips32:
3697 *mips32r2:
3698 *mips64:
3699 *mips64r2:
3700 *vr4100:
3701 *r3900:
3702 *vr5000:
3703 {
3704   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3705 }
3706
3707
3708 1110,ZZ!0!1!3,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWCz
3709 "swc<ZZ> r<RT>, <OFFSET>(r<BASE>)"
3710 *mipsI:
3711 *mipsII:
3712 *mipsIII:
3713 *mipsIV:
3714 *mipsV:
3715 *mips32:
3716 *mips32r2:
3717 *mips64:
3718 *mips64r2:
3719 *vr4100:
3720 *vr5000:
3721 *r3900:
3722 {
3723   do_store (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), COP_SW (ZZ, RT));
3724 }
3725
3726
3727 101010,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWL
3728 "swl r<RT>, <OFFSET>(r<BASE>)"
3729 *mipsI:
3730 *mipsII:
3731 *mipsIII:
3732 *mipsIV:
3733 *mipsV:
3734 *mips32:
3735 *mips32r2:
3736 *mips64:
3737 *mips64r2:
3738 *vr4100:
3739 *vr5000:
3740 *r3900:
3741 {
3742   do_store_left (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3743 }
3744
3745
3746 101110,5.BASE,5.RT,16.OFFSET:NORMAL:32::SWR
3747 "swr r<RT>, <OFFSET>(r<BASE>)"
3748 *mipsI:
3749 *mipsII:
3750 *mipsIII:
3751 *mipsIV:
3752 *mipsV:
3753 *mips32:
3754 *mips32r2:
3755 *mips64:
3756 *mips64r2:
3757 *vr4100:
3758 *vr5000:
3759 *r3900:
3760 {
3761   do_store_right (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET), GPR[RT]);
3762 }
3763
3764
3765 000000,000000000000000,5.STYPE,001111:SPECIAL:32::SYNC
3766 "sync":STYPE == 0
3767 "sync <STYPE>"
3768 *mipsII:
3769 *mipsIII:
3770 *mipsIV:
3771 *mipsV:
3772 *mips32:
3773 *mips32r2:
3774 *mips64:
3775 *mips64r2:
3776 *vr4100:
3777 *vr5000:
3778 *r3900:
3779 {
3780   SyncOperation (STYPE);
3781 }
3782
3783
3784 000000,20.CODE,001100:SPECIAL:32::SYSCALL
3785 "syscall %#lx<CODE>"
3786 *mipsI:
3787 *mipsII:
3788 *mipsIII:
3789 *mipsIV:
3790 *mipsV:
3791 *mips32:
3792 *mips32r2:
3793 *mips64:
3794 *mips64r2:
3795 *vr4100:
3796 *vr5000:
3797 *r3900:
3798 {
3799   SignalException (SystemCall, instruction_0);
3800 }
3801
3802
3803 000000,5.RS,5.RT,10.CODE,110100:SPECIAL:32::TEQ
3804 "teq r<RS>, r<RT>"
3805 *mipsII:
3806 *mipsIII:
3807 *mipsIV:
3808 *mipsV:
3809 *mips32:
3810 *mips32r2:
3811 *mips64:
3812 *mips64r2:
3813 *vr4100:
3814 *vr5000:
3815 {
3816   if ((signed_word) GPR[RS] == (signed_word) GPR[RT])
3817     SignalException (Trap, instruction_0);
3818 }
3819
3820
3821 000001,5.RS,01100,16.IMMEDIATE:REGIMM:32::TEQI
3822 "teqi r<RS>, <IMMEDIATE>"
3823 *mipsII:
3824 *mipsIII:
3825 *mipsIV:
3826 *mipsV:
3827 *mips32:
3828 *mips32r2:
3829 *mips64:
3830 *mips64r2:
3831 *vr4100:
3832 *vr5000:
3833 {
3834   if ((signed_word) GPR[RS] == (signed_word) EXTEND16 (IMMEDIATE))
3835     SignalException (Trap, instruction_0);
3836 }
3837
3838
3839 000000,5.RS,5.RT,10.CODE,110000:SPECIAL:32::TGE
3840 "tge r<RS>, r<RT>"
3841 *mipsII:
3842 *mipsIII:
3843 *mipsIV:
3844 *mipsV:
3845 *mips32:
3846 *mips32r2:
3847 *mips64:
3848 *mips64r2:
3849 *vr4100:
3850 *vr5000:
3851 {
3852   if ((signed_word) GPR[RS] >= (signed_word) GPR[RT])
3853     SignalException (Trap, instruction_0);
3854 }
3855
3856
3857 000001,5.RS,01000,16.IMMEDIATE:REGIMM:32::TGEI
3858 "tgei r<RS>, <IMMEDIATE>"
3859 *mipsII:
3860 *mipsIII:
3861 *mipsIV:
3862 *mipsV:
3863 *mips32:
3864 *mips32r2:
3865 *mips64:
3866 *mips64r2:
3867 *vr4100:
3868 *vr5000:
3869 {
3870   if ((signed_word) GPR[RS] >= (signed_word) EXTEND16 (IMMEDIATE))
3871     SignalException (Trap, instruction_0);
3872 }
3873
3874
3875 000001,5.RS,01001,16.IMMEDIATE:REGIMM:32::TGEIU
3876 "tgeiu r<RS>, <IMMEDIATE>"
3877 *mipsII:
3878 *mipsIII:
3879 *mipsIV:
3880 *mipsV:
3881 *mips32:
3882 *mips32r2:
3883 *mips64:
3884 *mips64r2:
3885 *vr4100:
3886 *vr5000:
3887 {
3888   if ((unsigned_word) GPR[RS] >= (unsigned_word) EXTEND16 (IMMEDIATE))
3889     SignalException (Trap, instruction_0);
3890 }
3891
3892
3893 000000,5.RS,5.RT,10.CODE,110001:SPECIAL:32::TGEU
3894 "tgeu r<RS>, r<RT>"
3895 *mipsII:
3896 *mipsIII:
3897 *mipsIV:
3898 *mipsV:
3899 *mips32:
3900 *mips32r2:
3901 *mips64:
3902 *mips64r2:
3903 *vr4100:
3904 *vr5000:
3905 {
3906   if ((unsigned_word) GPR[RS] >= (unsigned_word) GPR[RT])
3907     SignalException (Trap, instruction_0);
3908 }
3909
3910
3911 000000,5.RS,5.RT,10.CODE,110010:SPECIAL:32::TLT
3912 "tlt r<RS>, r<RT>"
3913 *mipsII:
3914 *mipsIII:
3915 *mipsIV:
3916 *mipsV:
3917 *mips32:
3918 *mips32r2:
3919 *mips64:
3920 *mips64r2:
3921 *vr4100:
3922 *vr5000:
3923 {
3924   if ((signed_word) GPR[RS] < (signed_word) GPR[RT])
3925     SignalException (Trap, instruction_0);
3926 }
3927
3928
3929 000001,5.RS,01010,16.IMMEDIATE:REGIMM:32::TLTI
3930 "tlti r<RS>, <IMMEDIATE>"
3931 *mipsII:
3932 *mipsIII:
3933 *mipsIV:
3934 *mipsV:
3935 *mips32:
3936 *mips32r2:
3937 *mips64:
3938 *mips64r2:
3939 *vr4100:
3940 *vr5000:
3941 {
3942   if ((signed_word) GPR[RS] < (signed_word) EXTEND16 (IMMEDIATE))
3943     SignalException (Trap, instruction_0);
3944 }
3945
3946
3947 000001,5.RS,01011,16.IMMEDIATE:REGIMM:32::TLTIU
3948 "tltiu r<RS>, <IMMEDIATE>"
3949 *mipsII:
3950 *mipsIII:
3951 *mipsIV:
3952 *mipsV:
3953 *mips32:
3954 *mips32r2:
3955 *mips64:
3956 *mips64r2:
3957 *vr4100:
3958 *vr5000:
3959 {
3960   if ((unsigned_word) GPR[RS] < (unsigned_word) EXTEND16 (IMMEDIATE))
3961     SignalException (Trap, instruction_0);
3962 }
3963
3964
3965 000000,5.RS,5.RT,10.CODE,110011:SPECIAL:32::TLTU
3966 "tltu r<RS>, r<RT>"
3967 *mipsII:
3968 *mipsIII:
3969 *mipsIV:
3970 *mipsV:
3971 *mips32:
3972 *mips32r2:
3973 *mips64:
3974 *mips64r2:
3975 *vr4100:
3976 *vr5000:
3977 {
3978   if ((unsigned_word) GPR[RS] < (unsigned_word) GPR[RT])
3979     SignalException (Trap, instruction_0);
3980 }
3981
3982
3983 000000,5.RS,5.RT,10.CODE,110110:SPECIAL:32::TNE
3984 "tne r<RS>, r<RT>"
3985 *mipsII:
3986 *mipsIII:
3987 *mipsIV:
3988 *mipsV:
3989 *mips32:
3990 *mips32r2:
3991 *mips64:
3992 *mips64r2:
3993 *vr4100:
3994 *vr5000:
3995 {
3996   if ((signed_word) GPR[RS] != (signed_word) GPR[RT])
3997     SignalException (Trap, instruction_0);
3998 }
3999
4000
4001 000001,5.RS,01110,16.IMMEDIATE:REGIMM:32::TNEI
4002 "tnei r<RS>, <IMMEDIATE>"
4003 *mipsII:
4004 *mipsIII:
4005 *mipsIV:
4006 *mipsV:
4007 *mips32:
4008 *mips32r2:
4009 *mips64:
4010 *mips64r2:
4011 *vr4100:
4012 *vr5000:
4013 {
4014   if ((signed_word) GPR[RS] != (signed_word) EXTEND16 (IMMEDIATE))
4015     SignalException (Trap, instruction_0);
4016 }
4017
4018
4019 :function:::void:do_xor:int rs, int rt, int rd
4020 {
4021   TRACE_ALU_INPUT2 (GPR[rs], GPR[rt]);
4022   GPR[rd] = GPR[rs] ^ GPR[rt];
4023   TRACE_ALU_RESULT (GPR[rd]);
4024 }
4025
4026 000000,5.RS,5.RT,5.RD,00000,100110:SPECIAL:32::XOR
4027 "xor r<RD>, r<RS>, r<RT>"
4028 *mipsI:
4029 *mipsII:
4030 *mipsIII:
4031 *mipsIV:
4032 *mipsV:
4033 *mips32:
4034 *mips32r2:
4035 *mips64:
4036 *mips64r2:
4037 *vr4100:
4038 *vr5000:
4039 *r3900:
4040 {
4041   do_xor (SD_, RS, RT, RD);
4042 }
4043
4044
4045 :function:::void:do_xori:int rs, int rt, unsigned16 immediate
4046 {
4047   TRACE_ALU_INPUT2 (GPR[rs], immediate);
4048   GPR[rt] = GPR[rs] ^ immediate;
4049   TRACE_ALU_RESULT (GPR[rt]);
4050 }
4051
4052 001110,5.RS,5.RT,16.IMMEDIATE:NORMAL:32::XORI
4053 "xori r<RT>, r<RS>, %#lx<IMMEDIATE>"
4054 *mipsI:
4055 *mipsII:
4056 *mipsIII:
4057 *mipsIV:
4058 *mipsV:
4059 *mips32:
4060 *mips32r2:
4061 *mips64:
4062 *mips64r2:
4063 *vr4100:
4064 *vr5000:
4065 *r3900:
4066 {
4067   do_xori (SD_, RS, RT, IMMEDIATE);
4068 }
4069
4070 \f
4071 //
4072 // MIPS Architecture:
4073 //
4074 //        FPU Instruction Set (COP1 & COP1X)
4075 //
4076
4077
4078 :%s::::FMT:int fmt
4079 {
4080   switch (fmt)
4081     {
4082     case fmt_single: return "s";
4083     case fmt_double: return "d";
4084     case fmt_word: return "w";
4085     case fmt_long: return "l";
4086     case fmt_ps: return "ps";
4087     default: return "?";
4088     }
4089 }
4090
4091 :%s::::TF:int tf
4092 {
4093   if (tf)
4094     return "t";
4095   else
4096     return "f";
4097 }
4098
4099 :%s::::ND:int nd
4100 {
4101   if (nd)
4102     return "l";
4103   else
4104     return "";
4105 }
4106
4107 :%s::::COND:int cond
4108 {
4109   switch (cond)
4110     {
4111     case 00: return "f";
4112     case 01: return "un";
4113     case 02: return "eq";
4114     case 03: return "ueq";
4115     case 04: return "olt";
4116     case 05: return "ult";
4117     case 06: return "ole";
4118     case 07: return "ule";
4119     case 010: return "sf";
4120     case 011: return "ngle";
4121     case 012: return "seq";
4122     case 013: return "ngl";
4123     case 014: return "lt";
4124     case 015: return "nge";
4125     case 016: return "le";
4126     case 017: return "ngt";
4127     default: return "?";
4128     }
4129 }
4130
4131
4132 // Helpers:
4133 //
4134 // Check that the given FPU format is usable, and signal a
4135 // ReservedInstruction exception if not.
4136 //
4137
4138 // check_fmt_p checks that the format is single, double, or paired single.
4139 :function:::void:check_fmt_p:int fmt, instruction_word insn
4140 *mipsI:
4141 *mipsII:
4142 *mipsIII:
4143 *mipsIV:
4144 *mips32:
4145 *mips32r2:
4146 *vr4100:
4147 *vr5000:
4148 *r3900:
4149 {
4150   /* None of these ISAs support Paired Single, so just fall back to
4151      the single/double check.  */
4152   if ((fmt != fmt_single) && (fmt != fmt_double))
4153     SignalException (ReservedInstruction, insn);
4154 }
4155
4156 :function:::void:check_fmt_p:int fmt, instruction_word insn
4157 *mipsV:
4158 *mips64:
4159 *mips64r2:
4160 {
4161   if ((fmt != fmt_single) && (fmt != fmt_double)
4162       && (fmt != fmt_ps || (UserMode && (SR & (status_UX|status_PX)) == 0)))
4163     SignalException (ReservedInstruction, insn);
4164 }
4165
4166
4167 // Helper:
4168 //
4169 // Check that the FPU is currently usable, and signal a CoProcessorUnusable
4170 // exception if not.
4171 //
4172
4173 :function:::void:check_fpu:
4174 *mipsI:
4175 *mipsII:
4176 *mipsIII:
4177 *mipsIV:
4178 *mipsV:
4179 *mips32:
4180 *mips32r2:
4181 *mips64:
4182 *mips64r2:
4183 *vr4100:
4184 *vr5000:
4185 *r3900:
4186 {
4187   if (! COP_Usable (1))
4188     SignalExceptionCoProcessorUnusable (1);
4189 }
4190
4191
4192 // Helper:
4193 //
4194 // Load a double word FP value using 2 32-bit memory cycles a la MIPS II
4195 // or MIPS32.  do_load cannot be used instead because it returns an
4196 // unsigned_word, which is limited to the size of the machine's registers.
4197 //
4198
4199 :function:::unsigned64:do_load_double:address_word base, address_word offset
4200 *mipsII:
4201 *mips32:
4202 *mips32r2:
4203 {
4204   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4205   address_word vaddr;
4206   address_word paddr;
4207   int uncached;
4208   unsigned64 memval;
4209   unsigned64 v;
4210
4211   vaddr = loadstore_ea (SD_, base, offset);
4212   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4213     {
4214       SIM_CORE_SIGNAL (SD, STATE_CPU (SD, 0), cia, read_map,
4215                        AccessLength_DOUBLEWORD + 1, vaddr, read_transfer,
4216                        sim_core_unaligned_signal);
4217     }
4218   AddressTranslation (vaddr, isDATA, isLOAD, &paddr, &uncached, isTARGET,
4219                       isREAL);
4220   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr, vaddr,
4221               isDATA, isREAL);
4222   v = (unsigned64)memval;
4223   LoadMemory (&memval, NULL, uncached, AccessLength_WORD, paddr + 4, vaddr + 4,
4224               isDATA, isREAL);
4225   return (bigendian ? ((v << 32) | memval) : (v | (memval << 32)));
4226 }
4227
4228
4229 // Helper:
4230 //
4231 // Store a double word FP value using 2 32-bit memory cycles a la MIPS II
4232 // or MIPS32.  do_load cannot be used instead because it returns an
4233 // unsigned_word, which is limited to the size of the machine's registers.
4234 //
4235
4236 :function:::void:do_store_double:address_word base, address_word offset, unsigned64 v
4237 *mipsII:
4238 *mips32:
4239 *mips32r2:
4240 {
4241   int bigendian = (BigEndianCPU ? ! ReverseEndian : ReverseEndian);
4242   address_word vaddr;
4243   address_word paddr;
4244   int uncached;
4245   unsigned64 memval;
4246
4247   vaddr = loadstore_ea (SD_, base, offset);
4248   if ((vaddr & AccessLength_DOUBLEWORD) != 0)
4249     {
4250       SIM_CORE_SIGNAL (SD, STATE_CPU(SD, 0), cia, read_map,
4251                        AccessLength_DOUBLEWORD + 1, vaddr, write_transfer,
4252                        sim_core_unaligned_signal);
4253     }
4254   AddressTranslation (vaddr, isDATA, isSTORE, &paddr, &uncached, isTARGET,
4255                       isREAL);
4256   memval = (bigendian ? (v >> 32) : (v & 0xFFFFFFFF));
4257   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr, vaddr,
4258                isREAL);
4259   memval = (bigendian ? (v & 0xFFFFFFFF) : (v >> 32));
4260   StoreMemory (uncached, AccessLength_WORD, memval, 0, paddr + 4, vaddr + 4,
4261                isREAL);
4262 }
4263
4264
4265 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000101:COP1:32,f::ABS.fmt
4266 "abs.%s<FMT> f<FD>, f<FS>"
4267 *mipsI:
4268 *mipsII:
4269 *mipsIII:
4270 *mipsIV:
4271 *mipsV:
4272 *mips32:
4273 *mips32r2:
4274 *mips64:
4275 *mips64r2:
4276 *vr4100:
4277 *vr5000:
4278 *r3900:
4279 {
4280   int fmt = FMT;
4281   check_fpu (SD_);
4282   check_fmt_p (SD_, fmt, instruction_0);
4283   StoreFPR (FD, fmt, AbsoluteValue (ValueFPR (FS, fmt), fmt));
4284 }
4285
4286
4287
4288 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000000:COP1:32,f::ADD.fmt
4289 "add.%s<FMT> f<FD>, f<FS>, f<FT>"
4290 *mipsI:
4291 *mipsII:
4292 *mipsIII:
4293 *mipsIV:
4294 *mipsV:
4295 *mips32:
4296 *mips32r2:
4297 *mips64:
4298 *mips64r2:
4299 *vr4100:
4300 *vr5000:
4301 *r3900:
4302 {
4303   int fmt = FMT;
4304   check_fpu (SD_);
4305   check_fmt_p (SD_, fmt, instruction_0);
4306   StoreFPR (FD, fmt, Add (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4307 }
4308
4309
4310 010011,5.RS,5.FT,5.FS,5.FD,011,110:COP1X:64,f::ALNV.PS
4311 "alnv.ps f<FD>, f<FS>, f<FT>, r<RS>"
4312 *mipsV:
4313 *mips32r2:
4314 *mips64:
4315 *mips64r2:
4316 {
4317   unsigned64 fs;
4318   unsigned64 ft;
4319   unsigned64 fd;
4320   check_fpu (SD_);
4321   check_u64 (SD_, instruction_0);
4322   fs = ValueFPR (FS, fmt_ps);
4323   if ((GPR[RS] & 0x3) != 0)
4324     Unpredictable ();
4325   if ((GPR[RS] & 0x4) == 0)
4326     fd = fs;
4327   else
4328     {
4329       ft = ValueFPR (FT, fmt_ps);
4330       if (BigEndianCPU)
4331         fd = PackPS (PSLower (fs), PSUpper (ft));
4332       else
4333         fd = PackPS (PSLower (ft), PSUpper (fs));
4334     }
4335   StoreFPR (FD, fmt_ps, fd);
4336 }
4337
4338
4339 // BC1F
4340 // BC1FL
4341 // BC1T
4342 // BC1TL
4343
4344 010001,01000,3.0,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1a
4345 "bc1%s<TF>%s<ND> <OFFSET>"
4346 *mipsI:
4347 *mipsII:
4348 *mipsIII:
4349 {
4350   check_fpu (SD_);
4351   TRACE_BRANCH_INPUT (PREVCOC1());
4352   if (PREVCOC1() == TF)
4353     {
4354       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4355       TRACE_BRANCH_RESULT (dest);
4356       DELAY_SLOT (dest);
4357     }
4358   else if (ND)
4359     {
4360       TRACE_BRANCH_RESULT (0);
4361       NULLIFY_NEXT_INSTRUCTION ();
4362     }
4363   else
4364     {
4365       TRACE_BRANCH_RESULT (NIA);
4366     }
4367 }
4368
4369 010001,01000,3.CC,1.ND,1.TF,16.OFFSET:COP1S:32,f::BC1b
4370 "bc1%s<TF>%s<ND> <OFFSET>":CC == 0
4371 "bc1%s<TF>%s<ND> <CC>, <OFFSET>"
4372 *mipsIV:
4373 *mipsV:
4374 *mips32:
4375 *mips32r2:
4376 *mips64:
4377 *mips64r2:
4378 #*vr4100:
4379 *vr5000:
4380 *r3900:
4381 {
4382   check_fpu (SD_);
4383   if (GETFCC(CC) == TF)
4384     {
4385       address_word dest = NIA + (EXTEND16 (OFFSET) << 2);
4386       DELAY_SLOT (dest);
4387     }
4388   else if (ND)
4389     {
4390       NULLIFY_NEXT_INSTRUCTION ();
4391     }
4392 }
4393
4394
4395 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,3.0,00,11,4.COND:COP1:32,f::C.cond.fmta
4396 "c.%s<COND>.%s<FMT> f<FS>, f<FT>"
4397 *mipsI:
4398 *mipsII:
4399 *mipsIII:
4400 {
4401   int fmt = FMT;
4402   check_fpu (SD_);
4403   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, 0);
4404   TRACE_ALU_RESULT (ValueFCR (31));
4405 }
4406
4407 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,3.CC,00,11,4.COND:COP1:32,f::C.cond.fmtb
4408 "c.%s<COND>.%s<FMT> f<FS>, f<FT>":CC == 0
4409 "c.%s<COND>.%s<FMT> <CC>, f<FS>, f<FT>"
4410 *mipsIV:
4411 *mipsV:
4412 *mips32:
4413 *mips32r2:
4414 *mips64:
4415 *mips64r2:
4416 *vr4100:
4417 *vr5000:
4418 *r3900:
4419 {
4420   int fmt = FMT;
4421   check_fpu (SD_);
4422   check_fmt_p (SD_, fmt, instruction_0);
4423   Compare (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt, COND, CC);
4424   TRACE_ALU_RESULT (ValueFCR (31));
4425 }
4426
4427
4428 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001010:COP1:64,f::CEIL.L.fmt
4429 "ceil.l.%s<FMT> f<FD>, f<FS>"
4430 *mipsIII:
4431 *mipsIV:
4432 *mipsV:
4433 *mips32r2:
4434 *mips64:
4435 *mips64r2:
4436 *vr4100:
4437 *vr5000:
4438 *r3900:
4439 {
4440   int fmt = FMT;
4441   check_fpu (SD_);
4442   StoreFPR (FD, fmt_long, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4443             fmt_long));
4444 }
4445
4446
4447 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001110:COP1:32,f::CEIL.W
4448 "ceil.w.%s<FMT> f<FD>, f<FS>"
4449 *mipsII:
4450 *mipsIII:
4451 *mipsIV:
4452 *mipsV:
4453 *mips32:
4454 *mips32r2:
4455 *mips64:
4456 *mips64r2:
4457 *vr4100:
4458 *vr5000:
4459 *r3900:
4460 {
4461   int fmt = FMT;
4462   check_fpu (SD_);
4463   StoreFPR (FD, fmt_word, Convert (FP_RM_TOPINF, ValueFPR (FS, fmt), fmt,
4464             fmt_word));
4465 }
4466
4467
4468 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1a
4469 "cfc1 r<RT>, f<FS>"
4470 *mipsI:
4471 *mipsII:
4472 *mipsIII:
4473 {
4474   check_fpu (SD_);
4475   if (FS == 0)
4476     PENDING_FILL (RT, EXTEND32 (FCR0));
4477   else if (FS == 31)
4478     PENDING_FILL (RT, EXTEND32 (FCR31));
4479   /* else NOP */
4480 }
4481
4482 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1b
4483 "cfc1 r<RT>, f<FS>"
4484 *mipsIV:
4485 *vr4100:
4486 *vr5000:
4487 *r3900:
4488 {
4489   check_fpu (SD_);
4490   if (FS == 0 || FS == 31)
4491     {
4492       unsigned_word  fcr = ValueFCR (FS);
4493       TRACE_ALU_INPUT1 (fcr);
4494       GPR[RT] = fcr;
4495     }
4496   /* else NOP */
4497   TRACE_ALU_RESULT (GPR[RT]);
4498 }
4499
4500 010001,00010,5.RT,5.FS,00000000000:COP1:32,f::CFC1c
4501 "cfc1 r<RT>, f<FS>"
4502 *mipsV:
4503 *mips32:
4504 *mips32r2:
4505 *mips64:
4506 *mips64r2:
4507 {
4508   check_fpu (SD_);
4509   if (FS == 0 || FS == 25 || FS == 26 || FS == 28 || FS == 31)
4510     {
4511       unsigned_word  fcr = ValueFCR (FS);
4512       TRACE_ALU_INPUT1 (fcr);
4513       GPR[RT] = fcr;
4514     }
4515   /* else NOP */
4516   TRACE_ALU_RESULT (GPR[RT]);
4517 }
4518
4519 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1a
4520 "ctc1 r<RT>, f<FS>"
4521 *mipsI:
4522 *mipsII:
4523 *mipsIII:
4524 {
4525   check_fpu (SD_);
4526   if (FS == 31)
4527     PENDING_FILL (FCRCS_REGNUM, VL4_8 (GPR[RT]));
4528   /* else NOP */
4529 }
4530
4531 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1b
4532 "ctc1 r<RT>, f<FS>"
4533 *mipsIV:
4534 *vr4100:
4535 *vr5000:
4536 *r3900:
4537 {
4538   check_fpu (SD_);
4539   TRACE_ALU_INPUT1 (GPR[RT]);
4540   if (FS == 31)
4541     StoreFCR (FS, GPR[RT]);
4542   /* else NOP */
4543 }
4544
4545 010001,00110,5.RT,5.FS,00000000000:COP1:32,f::CTC1c
4546 "ctc1 r<RT>, f<FS>"
4547 *mipsV:
4548 *mips32:
4549 *mips32r2:
4550 *mips64:
4551 *mips64r2:
4552 {
4553   check_fpu (SD_);
4554   TRACE_ALU_INPUT1 (GPR[RT]);
4555   if (FS == 25 || FS == 26 || FS == 28 || FS == 31)
4556       StoreFCR (FS, GPR[RT]);
4557   /* else NOP */
4558 }
4559
4560
4561 //
4562 // FIXME: Does not correctly differentiate between mips*
4563 //
4564 010001,10,3.FMT!1!2!3!6!7,00000,5.FS,5.FD,100001:COP1:32,f::CVT.D.fmt
4565 "cvt.d.%s<FMT> f<FD>, f<FS>"
4566 *mipsI:
4567 *mipsII:
4568 *mipsIII:
4569 *mipsIV:
4570 *mipsV:
4571 *mips32:
4572 *mips32r2:
4573 *mips64:
4574 *mips64r2:
4575 *vr4100:
4576 *vr5000:
4577 *r3900:
4578 {
4579   int fmt = FMT;
4580   check_fpu (SD_);
4581   if ((fmt == fmt_double) | 0)
4582     SignalException (ReservedInstruction, instruction_0);
4583   StoreFPR (FD, fmt_double, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4584             fmt_double));
4585 }
4586
4587
4588 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100101:COP1:64,f::CVT.L.fmt
4589 "cvt.l.%s<FMT> f<FD>, f<FS>"
4590 *mipsIII:
4591 *mipsIV:
4592 *mipsV:
4593 *mips32r2:
4594 *mips64:
4595 *mips64r2:
4596 *vr4100:
4597 *vr5000:
4598 *r3900:
4599 {
4600   int fmt = FMT;
4601   check_fpu (SD_);
4602   if ((fmt == fmt_long) | ((fmt == fmt_long) || (fmt == fmt_word)))
4603     SignalException (ReservedInstruction, instruction_0);
4604   StoreFPR (FD, fmt_long, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4605             fmt_long));
4606 }
4607
4608
4609 010001,10,000,5.FT,5.FS,5.FD,100110:COP1:64,f::CVT.PS.S
4610 "cvt.ps.s f<FD>, f<FS>, f<FT>"
4611 *mipsV:
4612 *mips32r2:
4613 *mips64:
4614 *mips64r2:
4615 {
4616   check_fpu (SD_);
4617   check_u64 (SD_, instruction_0);
4618   StoreFPR (FD, fmt_ps, PackPS (ValueFPR (FS, fmt_single),
4619                                 ValueFPR (FT, fmt_single)));
4620 }
4621
4622
4623 //
4624 // FIXME: Does not correctly differentiate between mips*
4625 //
4626 010001,10,3.FMT!0!2!3!6!7,00000,5.FS,5.FD,100000:COP1:32,f::CVT.S.fmt
4627 "cvt.s.%s<FMT> f<FD>, f<FS>"
4628 *mipsI:
4629 *mipsII:
4630 *mipsIII:
4631 *mipsIV:
4632 *mipsV:
4633 *mips32:
4634 *mips32r2:
4635 *mips64:
4636 *mips64r2:
4637 *vr4100:
4638 *vr5000:
4639 *r3900:
4640 {
4641   int fmt = FMT;
4642   check_fpu (SD_);
4643   if ((fmt == fmt_single) | 0)
4644     SignalException (ReservedInstruction, instruction_0);
4645   StoreFPR (FD, fmt_single, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4646             fmt_single));
4647 }
4648
4649
4650 010001,10,110,00000,5.FS,5.FD,101000:COP1:64,f::CVT.S.PL
4651 "cvt.s.pl f<FD>, f<FS>"
4652 *mipsV:
4653 *mips32r2:
4654 *mips64:
4655 *mips64r2:
4656 {
4657   check_fpu (SD_);
4658   check_u64 (SD_, instruction_0);
4659   StoreFPR (FD, fmt_single, PSLower (ValueFPR (FS, fmt_ps)));
4660 }
4661
4662
4663 010001,10,110,00000,5.FS,5.FD,100000:COP1:64,f::CVT.S.PU
4664 "cvt.s.pu f<FD>, f<FS>"
4665 *mipsV:
4666 *mips32r2:
4667 *mips64:
4668 *mips64r2:
4669 {
4670   check_fpu (SD_);
4671   check_u64 (SD_, instruction_0);
4672   StoreFPR (FD, fmt_single, PSUpper (ValueFPR (FS, fmt_ps)));
4673 }
4674
4675
4676 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,100100:COP1:32,f::CVT.W.fmt
4677 "cvt.w.%s<FMT> f<FD>, f<FS>"
4678 *mipsI:
4679 *mipsII:
4680 *mipsIII:
4681 *mipsIV:
4682 *mipsV:
4683 *mips32:
4684 *mips32r2:
4685 *mips64:
4686 *mips64r2:
4687 *vr4100:
4688 *vr5000:
4689 *r3900:
4690 {
4691   int fmt = FMT;
4692   check_fpu (SD_);
4693   if ((fmt == fmt_word) | ((fmt == fmt_long) || (fmt == fmt_word)))
4694     SignalException (ReservedInstruction, instruction_0);
4695   StoreFPR (FD, fmt_word, Convert (GETRM (), ValueFPR (FS, fmt), fmt,
4696             fmt_word));
4697 }
4698
4699
4700 010001,10,3.FMT!2!3!4!5!6!7,5.FT,5.FS,5.FD,000011:COP1:32,f::DIV.fmt
4701 "div.%s<FMT> f<FD>, f<FS>, f<FT>"
4702 *mipsI:
4703 *mipsII:
4704 *mipsIII:
4705 *mipsIV:
4706 *mipsV:
4707 *mips32:
4708 *mips32r2:
4709 *mips64:
4710 *mips64r2:
4711 *vr4100:
4712 *vr5000:
4713 *r3900:
4714 {
4715   int fmt = FMT;
4716   check_fpu (SD_);
4717   StoreFPR (FD, fmt, Divide (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
4718 }
4719
4720
4721 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1a
4722 "dmfc1 r<RT>, f<FS>"
4723 *mipsIII:
4724 {
4725   unsigned64 v;
4726   check_fpu (SD_);
4727   check_u64 (SD_, instruction_0);
4728   if (SizeFGR () == 64)
4729     v = FGR[FS];
4730   else if ((FS & 0x1) == 0)
4731     v = SET64HI (FGR[FS+1]) | FGR[FS];
4732   else
4733     v = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4734   PENDING_FILL (RT, v);
4735   TRACE_ALU_RESULT (v);
4736 }
4737
4738 010001,00001,5.RT,5.FS,00000000000:COP1:64,f::DMFC1b
4739 "dmfc1 r<RT>, f<FS>"
4740 *mipsIV:
4741 *mipsV:
4742 *mips64:
4743 *mips64r2:
4744 *vr4100:
4745 *vr5000:
4746 *r3900:
4747 {
4748   check_fpu (SD_);
4749   check_u64 (SD_, instruction_0);
4750   if (SizeFGR () == 64)
4751     GPR[RT] = FGR[FS];
4752   else if ((FS & 0x1) == 0)
4753     GPR[RT] = SET64HI (FGR[FS+1]) | FGR[FS];
4754   else
4755     GPR[RT] = SET64HI (0xDEADC0DE) | 0xBAD0BAD0;
4756   TRACE_ALU_RESULT (GPR[RT]);
4757 }
4758
4759
4760 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1a
4761 "dmtc1 r<RT>, f<FS>"
4762 *mipsIII:
4763 {
4764   unsigned64 v;
4765   check_fpu (SD_);
4766   check_u64 (SD_, instruction_0);
4767   if (SizeFGR () == 64)
4768     PENDING_FILL ((FS + FGR_BASE), GPR[RT]);
4769   else if ((FS & 0x1) == 0)
4770     {
4771       PENDING_FILL (((FS + 1) + FGR_BASE), VH4_8 (GPR[RT]));
4772       PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
4773     }
4774   else
4775     Unpredictable ();
4776   TRACE_FP_RESULT (GPR[RT]);
4777 }
4778
4779 010001,00101,5.RT,5.FS,00000000000:COP1:64,f::DMTC1b
4780 "dmtc1 r<RT>, f<FS>"
4781 *mipsIV:
4782 *mipsV:
4783 *mips64:
4784 *mips64r2:
4785 *vr4100:
4786 *vr5000:
4787 *r3900:
4788 {
4789   check_fpu (SD_);
4790   check_u64 (SD_, instruction_0);
4791   if (SizeFGR () == 64)
4792     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4793   else if ((FS & 0x1) == 0)
4794     StoreFPR (FS, fmt_uninterpreted_64, GPR[RT]);
4795   else
4796     Unpredictable ();
4797 }
4798
4799
4800 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001011:COP1:64,f::FLOOR.L.fmt
4801 "floor.l.%s<FMT> f<FD>, f<FS>"
4802 *mipsIII:
4803 *mipsIV:
4804 *mipsV:
4805 *mips32r2:
4806 *mips64:
4807 *mips64r2:
4808 *vr4100:
4809 *vr5000:
4810 *r3900:
4811 {
4812   int fmt = FMT;
4813   check_fpu (SD_);
4814   StoreFPR (FD, fmt_long, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4815             fmt_long));
4816 }
4817
4818
4819 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001111:COP1:32,f::FLOOR.W.fmt
4820 "floor.w.%s<FMT> f<FD>, f<FS>"
4821 *mipsII:
4822 *mipsIII:
4823 *mipsIV:
4824 *mipsV:
4825 *mips32:
4826 *mips32r2:
4827 *mips64:
4828 *mips64r2:
4829 *vr4100:
4830 *vr5000:
4831 *r3900:
4832 {
4833   int fmt = FMT;
4834   check_fpu (SD_);
4835   StoreFPR (FD, fmt_word, Convert (FP_RM_TOMINF, ValueFPR (FS, fmt), fmt,
4836             fmt_word));
4837 }
4838
4839
4840 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1a
4841 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4842 *mipsII:
4843 *mips32:
4844 *mips32r2:
4845 {
4846   check_fpu (SD_);
4847   COP_LD (1, FT, do_load_double (SD_, GPR[BASE], EXTEND16 (OFFSET)));
4848 }
4849
4850
4851 110101,5.BASE,5.FT,16.OFFSET:COP1:32,f::LDC1b
4852 "ldc1 f<FT>, <OFFSET>(r<BASE>)"
4853 *mipsIII:
4854 *mipsIV:
4855 *mipsV:
4856 *mips64:
4857 *mips64r2:
4858 *vr4100:
4859 *vr5000:
4860 *r3900:
4861 {
4862   check_fpu (SD_);
4863   COP_LD (1, FT, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET)));
4864 }
4865
4866
4867 010011,5.BASE,5.INDEX,5.0,5.FD,000001:COP1X:64,f::LDXC1
4868 "ldxc1 f<FD>, r<INDEX>(r<BASE>)"
4869 *mipsIV:
4870 *mipsV:
4871 *mips32r2:
4872 *mips64:
4873 *mips64r2:
4874 *vr5000:
4875 {
4876   check_fpu (SD_);
4877   check_u64 (SD_, instruction_0);
4878   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX]));
4879 }
4880
4881
4882 010011,5.BASE,5.INDEX,5.0,5.FD,000101:COP1X:64,f::LUXC1
4883 "luxc1 f<FD>, r<INDEX>(r<BASE>)"
4884 *mipsV:
4885 *mips32r2:
4886 *mips64:
4887 *mips64r2:
4888 {
4889   address_word base = GPR[BASE];
4890   address_word index = GPR[INDEX];
4891   address_word vaddr = base + index;
4892   check_fpu (SD_);
4893   check_u64 (SD_, instruction_0);
4894   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
4895   if ((vaddr & 0x7) != 0)
4896     index -= (vaddr & 0x7);
4897   COP_LD (1, FD, do_load (SD_, AccessLength_DOUBLEWORD, base, index));
4898 }
4899
4900
4901 110001,5.BASE,5.FT,16.OFFSET:COP1:32,f::LWC1
4902 "lwc1 f<FT>, <OFFSET>(r<BASE>)"
4903 *mipsI:
4904 *mipsII:
4905 *mipsIII:
4906 *mipsIV:
4907 *mipsV:
4908 *mips32:
4909 *mips32r2:
4910 *mips64:
4911 *mips64r2:
4912 *vr4100:
4913 *vr5000:
4914 *r3900:
4915 {
4916   check_fpu (SD_);
4917   COP_LW (1, FT, do_load (SD_, AccessLength_WORD, GPR[BASE], EXTEND16 (OFFSET)));
4918 }
4919
4920
4921 010011,5.BASE,5.INDEX,5.0,5.FD,000000:COP1X:64,f::LWXC1
4922 "lwxc1 f<FD>, r<INDEX>(r<BASE>)"
4923 *mipsIV:
4924 *mipsV:
4925 *mips32r2:
4926 *mips64:
4927 *mips64r2:
4928 *vr5000:
4929 {
4930   check_fpu (SD_);
4931   check_u64 (SD_, instruction_0);
4932   COP_LW (1, FD, do_load (SD_, AccessLength_WORD, GPR[BASE], GPR[INDEX]));
4933 }
4934
4935
4936
4937 010011,5.FR,5.FT,5.FS,5.FD,100,3.FMT!2!3!4!5!7:COP1X:64,f::MADD.fmt
4938 "madd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
4939 *mipsIV:
4940 *mipsV:
4941 *mips32r2:
4942 *mips64:
4943 *mips64r2:
4944 *vr5000:
4945 {
4946   int fmt = FMT;
4947   check_fpu (SD_);
4948   check_u64 (SD_, instruction_0);
4949   check_fmt_p (SD_, fmt, instruction_0);
4950   StoreFPR (FD, fmt, MultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
4951                                   ValueFPR (FR, fmt), fmt));
4952 }
4953
4954
4955 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1a
4956 "mfc1 r<RT>, f<FS>"
4957 *mipsI:
4958 *mipsII:
4959 *mipsIII:
4960 {
4961   unsigned64 v;
4962   check_fpu (SD_);
4963   v = EXTEND32 (FGR[FS]);
4964   PENDING_FILL (RT, v);
4965   TRACE_ALU_RESULT (v);
4966 }
4967
4968 010001,00000,5.RT,5.FS,00000000000:COP1:32,f::MFC1b
4969 "mfc1 r<RT>, f<FS>"
4970 *mipsIV:
4971 *mipsV:
4972 *mips32:
4973 *mips32r2:
4974 *mips64:
4975 *mips64r2:
4976 *vr4100:
4977 *vr5000:
4978 *r3900:
4979 {
4980   check_fpu (SD_);
4981   GPR[RT] = EXTEND32 (FGR[FS]);
4982   TRACE_ALU_RESULT (GPR[RT]);
4983 }
4984
4985
4986 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000110:COP1:32,f::MOV.fmt
4987 "mov.%s<FMT> f<FD>, f<FS>"
4988 *mipsI:
4989 *mipsII:
4990 *mipsIII:
4991 *mipsIV:
4992 *mipsV:
4993 *mips32:
4994 *mips32r2:
4995 *mips64:
4996 *mips64r2:
4997 *vr4100:
4998 *vr5000:
4999 *r3900:
5000 {
5001   int fmt = FMT;
5002   check_fpu (SD_);
5003   check_fmt_p (SD_, fmt, instruction_0);
5004   StoreFPR (FD, fmt, ValueFPR (FS, fmt));
5005 }
5006
5007
5008 // MOVF
5009 // MOVT
5010 000000,5.RS,3.CC,0,1.TF,5.RD,00000,000001:SPECIAL:32,f::MOVtf
5011 "mov%s<TF> r<RD>, r<RS>, <CC>"
5012 *mipsIV:
5013 *mipsV:
5014 *mips32:
5015 *mips32r2:
5016 *mips64:
5017 *mips64r2:
5018 *vr5000:
5019 {
5020   check_fpu (SD_);
5021   if (GETFCC(CC) == TF)
5022     GPR[RD] = GPR[RS];
5023 }
5024
5025
5026 // MOVF.fmt
5027 // MOVT.fmt
5028 010001,10,3.FMT!2!3!4!5!7,3.CC,0,1.TF,5.FS,5.FD,010001:COP1:32,f::MOVtf.fmt
5029 "mov%s<TF>.%s<FMT> f<FD>, f<FS>, <CC>"
5030 *mipsIV:
5031 *mipsV:
5032 *mips32:
5033 *mips32r2:
5034 *mips64:
5035 *mips64r2:
5036 *vr5000:
5037 {
5038   int fmt = FMT;
5039   check_fpu (SD_);
5040   if (fmt != fmt_ps)
5041     {
5042       if (GETFCC(CC) == TF)
5043         StoreFPR (FD, fmt, ValueFPR (FS, fmt));
5044       else
5045         StoreFPR (FD, fmt, ValueFPR (FD, fmt));   /* set fmt */
5046     }
5047   else
5048     {
5049       unsigned64 fd;
5050       fd = PackPS (PSUpper (ValueFPR ((GETFCC (CC+1) == TF) ? FS : FD,
5051                                       fmt_ps)),
5052                    PSLower (ValueFPR ((GETFCC (CC+0) == TF) ? FS : FD,
5053                                       fmt_ps)));
5054       StoreFPR (FD, fmt_ps, fd);
5055     }
5056 }
5057
5058
5059 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010011:COP1:32,f::MOVN.fmt
5060 "movn.%s<FMT> f<FD>, f<FS>, r<RT>"
5061 *mipsIV:
5062 *mipsV:
5063 *mips32:
5064 *mips32r2:
5065 *mips64:
5066 *mips64r2:
5067 *vr5000:
5068 {
5069   check_fpu (SD_);
5070   if (GPR[RT] != 0)
5071     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
5072   else
5073     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
5074 }
5075
5076
5077 // MOVT see MOVtf
5078
5079
5080 // MOVT.fmt see MOVtf.fmt
5081
5082
5083
5084 010001,10,3.FMT!2!3!4!5!7,5.RT,5.FS,5.FD,010010:COP1:32,f::MOVZ.fmt
5085 "movz.%s<FMT> f<FD>, f<FS>, r<RT>"
5086 *mipsIV:
5087 *mipsV:
5088 *mips32:
5089 *mips32r2:
5090 *mips64:
5091 *mips64r2:
5092 *vr5000:
5093 {
5094   check_fpu (SD_);
5095   if (GPR[RT] == 0)
5096     StoreFPR (FD, FMT, ValueFPR (FS, FMT));
5097   else
5098     StoreFPR (FD, FMT, ValueFPR (FD, FMT));
5099 }
5100
5101
5102 010011,5.FR,5.FT,5.FS,5.FD,101,3.FMT!2!3!4!5!7:COP1X:64,f::MSUB.fmt
5103 "msub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5104 *mipsIV:
5105 *mipsV:
5106 *mips32r2:
5107 *mips64:
5108 *mips64r2:
5109 *vr5000:
5110 {
5111   int fmt = FMT;
5112   check_fpu (SD_);
5113   check_u64 (SD_, instruction_0);
5114   check_fmt_p (SD_, fmt, instruction_0);
5115   StoreFPR (FD, fmt, MultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5116                                   ValueFPR (FR, fmt), fmt));
5117 }
5118
5119
5120 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1a
5121 "mtc1 r<RT>, f<FS>"
5122 *mipsI:
5123 *mipsII:
5124 *mipsIII:
5125 {
5126   check_fpu (SD_);
5127   if (SizeFGR () == 64)
5128     PENDING_FILL ((FS + FGR_BASE), (SET64HI (0xDEADC0DE) | VL4_8 (GPR[RT])));
5129   else
5130     PENDING_FILL ((FS + FGR_BASE), VL4_8 (GPR[RT]));
5131   TRACE_FP_RESULT (GPR[RT]);
5132 }
5133
5134 010001,00100,5.RT,5.FS,00000000000:COP1:32,f::MTC1b
5135 "mtc1 r<RT>, f<FS>"
5136 *mipsIV:
5137 *mipsV:
5138 *mips32:
5139 *mips32r2:
5140 *mips64:
5141 *mips64r2:
5142 *vr4100:
5143 *vr5000:
5144 *r3900:
5145 {
5146   check_fpu (SD_);
5147   StoreFPR (FS, fmt_uninterpreted_32, VL4_8 (GPR[RT]));
5148 }
5149
5150
5151 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000010:COP1:32,f::MUL.fmt
5152 "mul.%s<FMT> f<FD>, f<FS>, f<FT>"
5153 *mipsI:
5154 *mipsII:
5155 *mipsIII:
5156 *mipsIV:
5157 *mipsV:
5158 *mips32:
5159 *mips32r2:
5160 *mips64:
5161 *mips64r2:
5162 *vr4100:
5163 *vr5000:
5164 *r3900:
5165 {
5166   int fmt = FMT;
5167   check_fpu (SD_);
5168   check_fmt_p (SD_, fmt, instruction_0);
5169   StoreFPR (FD, fmt, Multiply (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5170 }
5171
5172
5173 010001,10,3.FMT!2!3!4!5!7,00000,5.FS,5.FD,000111:COP1:32,f::NEG.fmt
5174 "neg.%s<FMT> f<FD>, f<FS>"
5175 *mipsI:
5176 *mipsII:
5177 *mipsIII:
5178 *mipsIV:
5179 *mipsV:
5180 *mips32:
5181 *mips32r2:
5182 *mips64:
5183 *mips64r2:
5184 *vr4100:
5185 *vr5000:
5186 *r3900:
5187 {
5188   int fmt = FMT;
5189   check_fpu (SD_);
5190   check_fmt_p (SD_, fmt, instruction_0);
5191   StoreFPR (FD, fmt, Negate (ValueFPR (FS, fmt), fmt));
5192 }
5193
5194
5195 010011,5.FR,5.FT,5.FS,5.FD,110,3.FMT!2!3!4!5!7:COP1X:64,f::NMADD.fmt
5196 "nmadd.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5197 *mipsIV:
5198 *mipsV:
5199 *mips32r2:
5200 *mips64:
5201 *mips64r2:
5202 *vr5000:
5203 {
5204   int fmt = FMT;
5205   check_fpu (SD_);
5206   check_u64 (SD_, instruction_0);
5207   check_fmt_p (SD_, fmt, instruction_0);
5208   StoreFPR (FD, fmt, NegMultiplyAdd (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5209                                      ValueFPR (FR, fmt), fmt));
5210 }
5211
5212
5213 010011,5.FR,5.FT,5.FS,5.FD,111,3.FMT!2!3!4!5!7:COP1X:64,f::NMSUB.fmt
5214 "nmsub.%s<FMT> f<FD>, f<FR>, f<FS>, f<FT>"
5215 *mipsIV:
5216 *mipsV:
5217 *mips32r2:
5218 *mips64:
5219 *mips64r2:
5220 *vr5000:
5221 {
5222   int fmt = FMT;
5223   check_fpu (SD_);
5224   check_u64 (SD_, instruction_0);
5225   check_fmt_p (SD_, fmt, instruction_0);
5226   StoreFPR (FD, fmt, NegMultiplySub (ValueFPR (FS, fmt), ValueFPR (FT, fmt),
5227                                      ValueFPR (FR, fmt), fmt));
5228 }
5229
5230
5231 010001,10,110,5.FT,5.FS,5.FD,101100:COP1:64,f::PLL.PS
5232 "pll.ps f<FD>, f<FS>, f<FT>"
5233 *mipsV:
5234 *mips32r2:
5235 *mips64:
5236 *mips64r2:
5237 {
5238   check_fpu (SD_);
5239   check_u64 (SD_, instruction_0);
5240   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5241                                 PSLower (ValueFPR (FT, fmt_ps))));
5242 }
5243
5244
5245 010001,10,110,5.FT,5.FS,5.FD,101101:COP1:64,f::PLU.PS
5246 "plu.ps f<FD>, f<FS>, f<FT>"
5247 *mipsV:
5248 *mips32r2:
5249 *mips64:
5250 *mips64r2:
5251 {
5252   check_fpu (SD_);
5253   check_u64 (SD_, instruction_0);
5254   StoreFPR (FD, fmt_ps, PackPS (PSLower (ValueFPR (FS, fmt_ps)),
5255                                 PSUpper (ValueFPR (FT, fmt_ps))));
5256 }
5257
5258
5259 010011,5.BASE,5.INDEX,5.HINT,00000,001111:COP1X:64::PREFX
5260 "prefx <HINT>, r<INDEX>(r<BASE>)"
5261 *mipsIV:
5262 *mipsV:
5263 *mips32r2:
5264 *mips64:
5265 *mips64r2:
5266 *vr5000:
5267 {
5268   address_word base = GPR[BASE];
5269   address_word index = GPR[INDEX];
5270   {
5271     address_word vaddr = loadstore_ea (SD_, base, index);
5272     address_word paddr;
5273     int uncached;
5274     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5275       Prefetch(uncached,paddr,vaddr,isDATA,HINT);
5276   }
5277 }
5278
5279
5280 010001,10,110,5.FT,5.FS,5.FD,101110:COP1:64,f::PUL.PS
5281 "pul.ps f<FD>, f<FS>, f<FT>"
5282 *mipsV:
5283 *mips32r2:
5284 *mips64:
5285 *mips64r2:
5286 {
5287   check_fpu (SD_);
5288   check_u64 (SD_, instruction_0);
5289   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5290                                 PSLower (ValueFPR (FT, fmt_ps))));
5291 }
5292
5293
5294 010001,10,110,5.FT,5.FS,5.FD,101111:COP1:64,f::PUU.PS
5295 "puu.ps f<FD>, f<FS>, f<FT>"
5296 *mipsV:
5297 *mips32r2:
5298 *mips64:
5299 *mips64r2:
5300 {
5301   check_fpu (SD_);
5302   check_u64 (SD_, instruction_0);
5303   StoreFPR (FD, fmt_ps, PackPS (PSUpper (ValueFPR (FS, fmt_ps)),
5304                                 PSUpper (ValueFPR (FT, fmt_ps))));
5305 }
5306
5307
5308 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010101:COP1:32,f::RECIP.fmt
5309 "recip.%s<FMT> f<FD>, f<FS>"
5310 *mipsIV:
5311 *mipsV:
5312 *mips32r2:
5313 *mips64:
5314 *mips64r2:
5315 *vr5000:
5316 {
5317   int fmt = FMT;
5318   check_fpu (SD_);
5319   StoreFPR (FD, fmt, Recip (ValueFPR (FS, fmt), fmt));
5320 }
5321
5322
5323 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001000:COP1:64,f::ROUND.L.fmt
5324 "round.l.%s<FMT> f<FD>, f<FS>"
5325 *mipsIII:
5326 *mipsIV:
5327 *mipsV:
5328 *mips32r2:
5329 *mips64:
5330 *mips64r2:
5331 *vr4100:
5332 *vr5000:
5333 *r3900:
5334 {
5335   int fmt = FMT;
5336   check_fpu (SD_);
5337   StoreFPR (FD, fmt_long, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5338             fmt_long));
5339 }
5340
5341
5342 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001100:COP1:32,f::ROUND.W.fmt
5343 "round.w.%s<FMT> f<FD>, f<FS>"
5344 *mipsII:
5345 *mipsIII:
5346 *mipsIV:
5347 *mipsV:
5348 *mips32:
5349 *mips32r2:
5350 *mips64:
5351 *mips64r2:
5352 *vr4100:
5353 *vr5000:
5354 *r3900:
5355 {
5356   int fmt = FMT;
5357   check_fpu (SD_);
5358   StoreFPR (FD, fmt_word, Convert (FP_RM_NEAREST, ValueFPR (FS, fmt), fmt,
5359             fmt_word));
5360 }
5361
5362
5363 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,010110:COP1:32,f::RSQRT.fmt
5364 "rsqrt.%s<FMT> f<FD>, f<FS>"
5365 *mipsIV:
5366 *mipsV:
5367 *mips32r2:
5368 *mips64:
5369 *mips64r2:
5370 *vr5000:
5371 {
5372   int fmt = FMT;
5373   check_fpu (SD_);
5374   StoreFPR (FD, fmt, RSquareRoot (ValueFPR (FS, fmt), fmt));
5375 }
5376
5377
5378 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1a
5379 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5380 *mipsII:
5381 *mips32:
5382 *mips32r2:
5383 {
5384   check_fpu (SD_);
5385   do_store_double (SD_, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5386 }
5387
5388
5389 111101,5.BASE,5.FT,16.OFFSET:COP1:32,f::SDC1b
5390 "sdc1 f<FT>, <OFFSET>(r<BASE>)"
5391 *mipsIII:
5392 *mipsIV:
5393 *mipsV:
5394 *mips64:
5395 *mips64r2:
5396 *vr4100:
5397 *vr5000:
5398 *r3900:
5399 {
5400   check_fpu (SD_);
5401   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], EXTEND16 (OFFSET), COP_SD (1, FT));
5402 }
5403
5404
5405 010011,5.BASE,5.INDEX,5.FS,00000001001:COP1X:64,f::SDXC1
5406 "sdxc1 f<FS>, r<INDEX>(r<BASE>)"
5407 *mipsIV:
5408 *mipsV:
5409 *mips64:
5410 *mips64r2:
5411 *vr5000:
5412 {
5413   check_fpu (SD_);
5414   check_u64 (SD_, instruction_0);
5415   do_store (SD_, AccessLength_DOUBLEWORD, GPR[BASE], GPR[INDEX], COP_SD (1, FS));
5416 }
5417
5418
5419 010011,5.BASE,5.INDEX,5.FS,00000,001101:COP1X:64,f::SUXC1
5420 "suxc1 f<FS>, r<INDEX>(r<BASE>)"
5421 *mipsV:
5422 *mips64:
5423 *mips64r2:
5424 {
5425   unsigned64 v;
5426   address_word base = GPR[BASE];
5427   address_word index = GPR[INDEX];
5428   address_word vaddr = base + index;
5429   check_fpu (SD_);
5430   check_u64 (SD_, instruction_0);
5431   /* Arrange for the bottom 3 bits of (base + index) to be 0.  */
5432   if ((vaddr & 0x7) != 0)
5433     index -= (vaddr & 0x7);
5434   do_store (SD_, AccessLength_DOUBLEWORD, base, index, COP_SD (1, FS));
5435 }
5436
5437
5438 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,000100:COP1:32,f::SQRT.fmt
5439 "sqrt.%s<FMT> f<FD>, f<FS>"
5440 *mipsII:
5441 *mipsIII:
5442 *mipsIV:
5443 *mipsV:
5444 *mips32:
5445 *mips32r2:
5446 *mips64:
5447 *mips64r2:
5448 *vr4100:
5449 *vr5000:
5450 *r3900:
5451 {
5452   int fmt = FMT;
5453   check_fpu (SD_);
5454   StoreFPR (FD, fmt,  (SquareRoot (ValueFPR (FS, fmt), fmt)));
5455 }
5456
5457
5458 010001,10,3.FMT!2!3!4!5!7,5.FT,5.FS,5.FD,000001:COP1:32,f::SUB.fmt
5459 "sub.%s<FMT> f<FD>, f<FS>, f<FT>"
5460 *mipsI:
5461 *mipsII:
5462 *mipsIII:
5463 *mipsIV:
5464 *mipsV:
5465 *mips32:
5466 *mips32r2:
5467 *mips64:
5468 *mips64r2:
5469 *vr4100:
5470 *vr5000:
5471 *r3900:
5472 {
5473   int fmt = FMT;
5474   check_fpu (SD_);
5475   check_fmt_p (SD_, fmt, instruction_0);
5476   StoreFPR (FD, fmt, Sub (ValueFPR (FS, fmt), ValueFPR (FT, fmt), fmt));
5477 }
5478
5479
5480
5481 111001,5.BASE,5.FT,16.OFFSET:COP1:32,f::SWC1
5482 "swc1 f<FT>, <OFFSET>(r<BASE>)"
5483 *mipsI:
5484 *mipsII:
5485 *mipsIII:
5486 *mipsIV:
5487 *mipsV:
5488 *mips32:
5489 *mips32r2:
5490 *mips64:
5491 *mips64r2:
5492 *vr4100:
5493 *vr5000:
5494 *r3900:
5495 {
5496   address_word base = GPR[BASE];
5497   address_word offset = EXTEND16 (OFFSET);
5498   check_fpu (SD_);
5499   {
5500     address_word vaddr = loadstore_ea (SD_, base, offset);
5501     address_word paddr;
5502     int uncached;
5503     if ((vaddr & 3) != 0)
5504       {
5505         SIM_CORE_SIGNAL (SD, CPU, cia, read_map, AccessLength_WORD+1, vaddr, write_transfer, sim_core_unaligned_signal);
5506       }
5507     else
5508       {
5509         if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5510           {
5511             uword64 memval = 0;
5512             uword64 memval1 = 0;
5513             uword64 mask = (WITH_TARGET_WORD_BITSIZE == 64 ? 0x7 : 0x3);
5514             address_word reverseendian = (ReverseEndian ?(mask ^ AccessLength_WORD): 0);
5515             address_word bigendiancpu = (BigEndianCPU ?(mask ^ AccessLength_WORD): 0);
5516             unsigned int byte;
5517             paddr = ((paddr & ~mask) | ((paddr & mask) ^ reverseendian));
5518             byte = ((vaddr & mask) ^ bigendiancpu);
5519             memval = (((uword64)COP_SW(((instruction_0 >> 26) & 0x3),FT)) << (8 * byte));
5520             StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5521           }
5522       }
5523   }
5524 }
5525
5526
5527 010011,5.BASE,5.INDEX,5.FS,00000,001000:COP1X:32,f::SWXC1
5528 "swxc1 f<FS>, r<INDEX>(r<BASE>)"
5529 *mipsIV:
5530 *mipsV:
5531 *mips32r2:
5532 *mips64:
5533 *mips64r2:
5534 *vr5000:
5535 {
5536
5537   address_word base = GPR[BASE];
5538   address_word index = GPR[INDEX];
5539   check_fpu (SD_);
5540   check_u64 (SD_, instruction_0);
5541   {
5542    address_word vaddr = loadstore_ea (SD_, base, index);
5543    address_word paddr;
5544    int uncached;
5545    if ((vaddr & 3) != 0)
5546      {
5547        SIM_CORE_SIGNAL (SD, CPU, cia, read_map, 4, vaddr, write_transfer, sim_core_unaligned_signal);
5548      }
5549    else
5550    {
5551     if (AddressTranslation(vaddr,isDATA,isSTORE,&paddr,&uncached,isTARGET,isREAL))
5552     {
5553      unsigned64 memval = 0;
5554      unsigned64 memval1 = 0;
5555      unsigned64 mask = 0x7;
5556      unsigned int byte;
5557      paddr = ((paddr & ~mask) | ((paddr & mask) ^ (ReverseEndian << 2)));
5558      byte = ((vaddr & mask) ^ (BigEndianCPU << 2));
5559      memval = (((unsigned64)COP_SW(1,FS)) << (8 * byte));
5560       {
5561        StoreMemory(uncached,AccessLength_WORD,memval,memval1,paddr,vaddr,isREAL);
5562       }
5563     }
5564    }
5565   }
5566 }
5567
5568
5569 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001001:COP1:64,f::TRUNC.L.fmt
5570 "trunc.l.%s<FMT> f<FD>, f<FS>"
5571 *mipsIII:
5572 *mipsIV:
5573 *mipsV:
5574 *mips32r2:
5575 *mips64:
5576 *mips64r2:
5577 *vr4100:
5578 *vr5000:
5579 *r3900:
5580 {
5581   int fmt = FMT;
5582   check_fpu (SD_);
5583   StoreFPR (FD, fmt_long, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5584             fmt_long));
5585 }
5586
5587
5588 010001,10,3.FMT!2!3!4!5!6!7,00000,5.FS,5.FD,001101:COP1:32,f::TRUNC.W
5589 "trunc.w.%s<FMT> f<FD>, f<FS>"
5590 *mipsII:
5591 *mipsIII:
5592 *mipsIV:
5593 *mipsV:
5594 *mips32:
5595 *mips32r2:
5596 *mips64:
5597 *mips64r2:
5598 *vr4100:
5599 *vr5000:
5600 *r3900:
5601 {
5602   int fmt = FMT;
5603   check_fpu (SD_);
5604   StoreFPR (FD, fmt_word, Convert (FP_RM_TOZERO, ValueFPR (FS, fmt), fmt,
5605             fmt_word));
5606 }
5607
5608 \f
5609 //
5610 // MIPS Architecture:
5611 //
5612 //        System Control Instruction Set (COP0)
5613 //
5614
5615
5616 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5617 "bc0f <OFFSET>"
5618 *mipsI:
5619 *mipsII:
5620 *mipsIII:
5621 *mipsIV:
5622 *mipsV:
5623 *mips32:
5624 *mips32r2:
5625 *mips64:
5626 *mips64r2:
5627 *vr4100:
5628 *vr5000:
5629
5630 010000,01000,00000,16.OFFSET:COP0:32::BC0F
5631 "bc0f <OFFSET>"
5632 // stub needed for eCos as tx39 hardware bug workaround
5633 *r3900:
5634 {
5635   /* do nothing */
5636 }
5637
5638
5639 010000,01000,00010,16.OFFSET:COP0:32::BC0FL
5640 "bc0fl <OFFSET>"
5641 *mipsI:
5642 *mipsII:
5643 *mipsIII:
5644 *mipsIV:
5645 *mipsV:
5646 *mips32:
5647 *mips32r2:
5648 *mips64:
5649 *mips64r2:
5650 *vr4100:
5651 *vr5000:
5652
5653
5654 010000,01000,00001,16.OFFSET:COP0:32::BC0T
5655 "bc0t <OFFSET>"
5656 *mipsI:
5657 *mipsII:
5658 *mipsIII:
5659 *mipsIV:
5660 *mipsV:
5661 *mips32:
5662 *mips32r2:
5663 *mips64:
5664 *mips64r2:
5665 *vr4100:
5666
5667
5668 010000,01000,00011,16.OFFSET:COP0:32::BC0TL
5669 "bc0tl <OFFSET>"
5670 *mipsI:
5671 *mipsII:
5672 *mipsIII:
5673 *mipsIV:
5674 *mipsV:
5675 *mips32:
5676 *mips32r2:
5677 *mips64:
5678 *mips64r2:
5679 *vr4100:
5680 *vr5000:
5681
5682
5683 101111,5.BASE,5.OP,16.OFFSET:NORMAL:32::CACHE
5684 "cache <OP>, <OFFSET>(r<BASE>)"
5685 *mipsIII:
5686 *mipsIV:
5687 *mipsV:
5688 *mips32:
5689 *mips32r2:
5690 *mips64:
5691 *mips64r2:
5692 *vr4100:
5693 *vr5000:
5694 *r3900:
5695 {
5696   address_word base = GPR[BASE];
5697   address_word offset = EXTEND16 (OFFSET);
5698   {
5699     address_word vaddr = loadstore_ea (SD_, base, offset);
5700     address_word paddr;
5701     int uncached;
5702     if (AddressTranslation(vaddr,isDATA,isLOAD,&paddr,&uncached,isTARGET,isREAL))
5703       CacheOp(OP,vaddr,paddr,instruction_0);
5704   }
5705 }
5706
5707
5708 010000,00001,5.RT,5.RD,00000000000:COP0:64::DMFC0
5709 "dmfc0 r<RT>, r<RD>"
5710 *mipsIII:
5711 *mipsIV:
5712 *mipsV:
5713 *mips64:
5714 *mips64r2:
5715 {
5716   check_u64 (SD_, instruction_0);
5717   DecodeCoproc (instruction_0);
5718 }
5719
5720
5721 010000,00101,5.RT,5.RD,00000000000:COP0:64::DMTC0
5722 "dmtc0 r<RT>, r<RD>"
5723 *mipsIII:
5724 *mipsIV:
5725 *mipsV:
5726 *mips64:
5727 *mips64r2:
5728 {
5729   check_u64 (SD_, instruction_0);
5730   DecodeCoproc (instruction_0);
5731 }
5732
5733
5734 010000,1,0000000000000000000,011000:COP0:32::ERET
5735 "eret"
5736 *mipsIII:
5737 *mipsIV:
5738 *mipsV:
5739 *mips32:
5740 *mips32r2:
5741 *mips64:
5742 *mips64r2:
5743 *vr4100:
5744 *vr5000:
5745 {
5746   if (SR & status_ERL)
5747     {
5748       /* Oops, not yet available */
5749       sim_io_printf (SD, "Warning: ERET when SR[ERL] set not supported");
5750       NIA = EPC;
5751       SR &= ~status_ERL;
5752     }
5753   else
5754     {
5755       NIA = EPC;
5756       SR &= ~status_EXL;
5757     }
5758 }
5759
5760
5761 010000,00000,5.RT,5.RD,00000,6.REGX:COP0:32::MFC0
5762 "mfc0 r<RT>, r<RD> # <REGX>"
5763 *mipsI:
5764 *mipsII:
5765 *mipsIII:
5766 *mipsIV:
5767 *mipsV:
5768 *mips32:
5769 *mips32r2:
5770 *mips64:
5771 *mips64r2:
5772 *vr4100:
5773 *vr5000:
5774 *r3900:
5775 {
5776   TRACE_ALU_INPUT0 ();
5777   DecodeCoproc (instruction_0);
5778   TRACE_ALU_RESULT (GPR[RT]);
5779 }
5780
5781 010000,00100,5.RT,5.RD,00000,6.REGX:COP0:32::MTC0
5782 "mtc0 r<RT>, r<RD> # <REGX>"
5783 *mipsI:
5784 *mipsII:
5785 *mipsIII:
5786 *mipsIV:
5787 *mipsV:
5788 *mips32:
5789 *mips32r2:
5790 *mips64:
5791 *mips64r2:
5792 *vr4100:
5793 *vr5000:
5794 *r3900:
5795 {
5796   DecodeCoproc (instruction_0);
5797 }
5798
5799
5800 010000,1,0000000000000000000,010000:COP0:32::RFE
5801 "rfe"
5802 *mipsI:
5803 *mipsII:
5804 *mipsIII:
5805 *mipsIV:
5806 *mipsV:
5807 *vr4100:
5808 *vr5000:
5809 *r3900:
5810 {
5811   DecodeCoproc (instruction_0);
5812 }
5813
5814
5815 0100,ZZ!0!1!3,5.COP_FUN0!8,5.COP_FUN1,16.COP_FUN2:NORMAL:32::COPz
5816 "cop<ZZ> <COP_FUN0><COP_FUN1><COP_FUN2>"
5817 *mipsI:
5818 *mipsII:
5819 *mipsIII:
5820 *mipsIV:
5821 *mipsV:
5822 *mips32:
5823 *mips32r2:
5824 *mips64:
5825 *mips64r2:
5826 *vr4100:
5827 *r3900:
5828 {
5829   DecodeCoproc (instruction_0);
5830 }
5831
5832
5833
5834 010000,1,0000000000000000000,001000:COP0:32::TLBP
5835 "tlbp"
5836 *mipsI:
5837 *mipsII:
5838 *mipsIII:
5839 *mipsIV:
5840 *mipsV:
5841 *mips32:
5842 *mips32r2:
5843 *mips64:
5844 *mips64r2:
5845 *vr4100:
5846 *vr5000:
5847
5848
5849 010000,1,0000000000000000000,000001:COP0:32::TLBR
5850 "tlbr"
5851 *mipsI:
5852 *mipsII:
5853 *mipsIII:
5854 *mipsIV:
5855 *mipsV:
5856 *mips32:
5857 *mips32r2:
5858 *mips64:
5859 *mips64r2:
5860 *vr4100:
5861 *vr5000:
5862
5863
5864 010000,1,0000000000000000000,000010:COP0:32::TLBWI
5865 "tlbwi"
5866 *mipsI:
5867 *mipsII:
5868 *mipsIII:
5869 *mipsIV:
5870 *mipsV:
5871 *mips32:
5872 *mips32r2:
5873 *mips64:
5874 *mips64r2:
5875 *vr4100:
5876 *vr5000:
5877
5878
5879 010000,1,0000000000000000000,000110:COP0:32::TLBWR
5880 "tlbwr"
5881 *mipsI:
5882 *mipsII:
5883 *mipsIII:
5884 *mipsIV:
5885 *mipsV:
5886 *mips32:
5887 *mips32r2:
5888 *mips64:
5889 *mips64r2:
5890 *vr4100:
5891 *vr5000:
5892
5893
5894 :include:::mips3264r2.igen
5895 :include:::m16.igen
5896 :include:::m16e.igen
5897 :include:::mdmx.igen
5898 :include:::mips3d.igen
5899 :include:::sb1.igen
5900 :include:::tx.igen
5901 :include:::vr.igen
5902 :include:::dsp.igen
5903 :include:::dsp2.igen
5904 :include:::smartmips.igen
5905