sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35 #include "sim-basics.h"
  36
  37 typedef address_word sim_cia;
  38
  39 #if (WITH_IGEN)
  40 /* Get the number of instructions.  FIXME: must be a more elegant way
  41    of doing this.  */
  42 #include "itable.h"
  43 #define MAX_INSNS (nr_itable_entries)
  44 #define INSN_NAME(i) itable[(i)].name
  45 #endif
  46
  47 #include "sim-base.h"
  48
  49
  50 /* Depreciated macros and types for manipulating 64bit values.  Use
  51    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  52
  53 typedef signed64 word64;
  54 typedef unsigned64 uword64;
  55
  56 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  57 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  58 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  59 #define SET64HI(t)      (((uword64)(t))<<32)
  60 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  61 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  62
  63 /* Sign-extend the given value (e) as a value (b) bits long. We cannot
  64    assume the HI32bits of the operand are zero, so we must perform a
  65    mask to ensure we can use the simple subtraction to sign-extend. */
  66 #define SIGNEXTEND(e,b) \
  67  ((unsigned_word) \
  68   (((e) & ((uword64) 1 << ((b) - 1))) \
  69    ? (((e) & (((uword64) 1 << (b)) - 1)) - ((uword64)1 << (b))) \
  70    : ((e) & (((((uword64) 1 << ((b) - 1)) - 1) << 1) | 1))))
  71
  72 /* Check if a value will fit within a halfword: */
  73 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  74
  75
  76
  77 /* Floating-point operations: */
  78
  79 #include "sim-fpu.h"
  80
  81 /* FPU registers must be one of the following types. All other values
  82    are reserved (and undefined). */
  83 typedef enum {
  84  fmt_single  = 0,
  85  fmt_double  = 1,
  86  fmt_word    = 4,
  87  fmt_long    = 5,
  88  /* The following are well outside the normal acceptable format
  89     range, and are used in the register status vector. */
  90  fmt_unknown       = 0x10000000,
  91  fmt_uninterpreted = 0x20000000,
  92  fmt_uninterpreted_32 = 0x40000000,
  93  fmt_uninterpreted_64 = 0x80000000,
  94 } FP_formats;
  95
  96 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  97 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  98
  99 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
 100 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
 101
 102 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
 103 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
 104 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 105 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 106 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
 107 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
 108 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 109 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 110 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 111 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 112 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 113 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 114 unsigned64 Max PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 115 unsigned64 Min PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
 116 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 117 #define Convert(rm,op,from,to) \
 118 convert (SD, CPU, cia, rm, op, from, to)
 119
 120 /* Macro to update FPSR condition-code field. This is complicated by
 121    the fact that there is a hole in the index range of the bits within
 122    the FCSR register. Also, the number of bits visible depends on the
 123    MIPS ISA version being supported. */
 124
 125 #define SETFCC(cc,v) {\
 126   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 127   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 128 }
 129 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 130
 131 /* This should be the COC1 value at the start of the preceding
 132    instruction: */
 133 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 134
 135 #if 1
 136 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 137 #else
 138 /* They depend on the CPU being simulated */
 139 #define SizeFGR() ((WITH_TARGET_WORD_BITSIZE == 64 && ((SR & status_FR) == 1)) ? 64 : 32)
 140 #endif
 141
 142 /* Standard FCRS bits: */
 143 #define IR (0) /* Inexact Result */
 144 #define UF (1) /* UnderFlow */
 145 #define OF (2) /* OverFlow */
 146 #define DZ (3) /* Division by Zero */
 147 #define IO (4) /* Invalid Operation */
 148 #define UO (5) /* Unimplemented Operation */
 149
 150 /* Get masks for individual flags: */
 151 #if 1 /* SAFE version */
 152 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 153 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 154 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 155 #else
 156 #define FP_FLAGS(b)  (1 << ((b) + 2))
 157 #define FP_ENABLE(b) (1 << ((b) + 7))
 158 #define FP_CAUSE(b)  (1 << ((b) + 12))
 159 #endif
 160
 161 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 162
 163 #define FP_MASK_RM    (0x3)
 164 #define FP_SH_RM      (0)
 165 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 166 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 167 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 168 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 169 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 170
 171 /* start-sanitize-sky */
 172 #ifdef TARGET_SKY
 173 #ifdef SKY_FUNIT
 174 #include "wf.h"
 175 #endif
 176 #endif
 177 /* end-sanitize-sky */
 178
 179
 180
 181
 182
 183 /* HI/LO register accesses */
 184
 185 /* For some MIPS targets, the HI/LO registers have certain timing
 186    restrictions in that, for instance, a read of a HI register must be
 187    separated by at least three instructions from a preceeding read.
 188
 189    The struct below is used to record the last access by each of A MT,
 190    MF or other OP instruction to a HI/LO register.  See mips.igen for
 191    more details. */
 192
 193 typedef struct _hilo_access {
 194   signed64 timestamp;
 195   address_word cia;
 196 } hilo_access;
 197
 198 typedef struct _hilo_history {
 199   hilo_access mt;
 200   hilo_access mf;
 201   hilo_access op;
 202 } hilo_history;
 203
 204
 205
 206
 207 /* Integer ALU operations: */
 208
 209 #include "sim-alu.h"
 210
 211 #define ALU32_END(ANS) \
 212   if (ALU32_HAD_OVERFLOW) \
 213     SignalExceptionIntegerOverflow (); \
 214   (ANS) = ALU32_OVERFLOW_RESULT
 215
 216
 217 #define ALU64_END(ANS) \
 218   if (ALU64_HAD_OVERFLOW) \
 219     SignalExceptionIntegerOverflow (); \
 220   (ANS) = ALU64_OVERFLOW_RESULT;
 221
 222
 223 /* start-sanitize-r5900 */
 224
 225 /* Figure 10-5 FPU Control/Status Register.
 226    Note: some of these bits are different to what is found in a
 227    standard MIPS manual. */
 228 enum {
 229   R5900_FCSR_C = BIT (23), /* OK */
 230   R5900_FCSR_I = BIT (17),
 231   R5900_FCSR_D = BIT (16),
 232   R5900_FCSR_O = BIT (15),
 233   R5900_FCSR_U = BIT (14),
 234   R5900_FCSR_CAUSE = MASK (16,14),
 235   R5900_FCSR_SI = BIT (6),
 236   R5900_FCSR_SD = BIT (5),
 237   R5900_FCSR_SO = BIT (4),
 238   R5900_FCSR_SU = BIT (3),
 239 };
 240
 241 /* Table 10-1 FP format values.
 242    Note: some of these bits are different to what is found in a
 243    standard MIPS manual. */
 244 enum {
 245   R5900_EXPMAX = 128,
 246   R5900_EXPMIN = -127,
 247   R5900_EXPBIAS = 127,
 248 };
 249
 250
 251
 252 typedef struct _sim_r5900_cpu {
 253
 254   /* The R5900 has 32 x 128bit general purpose registers.
 255      Fortunatly, the high 64 bits are only touched by multimedia (MMI)
 256      instructions.  The normal mips instructions just use the lower 64
 257      bits.  To avoid changing the older parts of the simulator to
 258      handle this weirdness, the high 64 bits of each register are kept
 259      in a separate array (registers1).  The high 64 bits of any
 260      register are by convention refered by adding a '1' to the end of
 261      the normal register's name.  So LO still refers to the low 64
 262      bits of the LO register, LO1 refers to the high 64 bits of that
 263      same register.  */
 264   signed_word gpr1[32];
 265 #define GPR1     ((CPU)->r5900.gpr1)
 266   signed_word lo1;
 267   signed_word hi1;
 268 #define LO1      ((CPU)->r5900.lo1)
 269 #define HI1      ((CPU)->r5900.hi1)
 270
 271   /* The R5900 defines a shift amount register, that controls the
 272      amount of certain shift instructions */
 273   unsigned_word sa;        /* the shift amount register */
 274 #define REGISTER_SA     (124) /* GET RID IF THIS! */
 275 #define SA ((CPU)->r5900.sa)
 276
 277   /* The R5900, in addition to the (almost) standard floating point
 278      registers, defines a 32 bit accumulator.  This is used in
 279      multiply/accumulate style instructions */
 280   fp_word acc; /* floating-point accumulator */
 281 #define ACC ((CPU)->r5900.acc)
 282
 283   /* See comments below about needing to count cycles between updating
 284      and setting HI/LO registers */
 285   hilo_history hi1_history;
 286 #define HI1HISTORY (&(CPU)->r5900.hi1_history)
 287   hilo_history lo1_history;
 288 #define LO1HISTORY (&(CPU)->r5900.lo1_history)
 289
 290 } sim_r5900_cpu;
 291
 292 #define BYTES_IN_MMI_REGS       (sizeof(signed_word) + sizeof(signed_word))
 293 #define HALFWORDS_IN_MMI_REGS   (BYTES_IN_MMI_REGS/2)
 294 #define WORDS_IN_MMI_REGS       (BYTES_IN_MMI_REGS/4)
 295 #define DOUBLEWORDS_IN_MMI_REGS (BYTES_IN_MMI_REGS/8)
 296
 297 #define BYTES_IN_MIPS_REGS       (sizeof(signed_word))
 298 #define HALFWORDS_IN_MIPS_REGS   (BYTES_IN_MIPS_REGS/2)
 299 #define WORDS_IN_MIPS_REGS       (BYTES_IN_MIPS_REGS/4)
 300 #define DOUBLEWORDS_IN_MIPS_REGS (BYTES_IN_MIPS_REGS/8)
 301
 302 /* SUB_REG_FETCH - return as lvalue some sub-part of a "register"
 303    T  - type of the sub part
 304    TC - # of T's in the mips part of the "register"
 305    I  - index (from 0) of desired sub part
 306    A  - low part of "register"
 307    A1 - high part of register
 308 */
 309 #define SUB_REG_FETCH(T,TC,A,A1,I) \
 310 (*(((I) < (TC) ? (T*)(A) : (T*)(A1)) \
 311    + (CURRENT_HOST_BYTE_ORDER == BIG_ENDIAN \
 312       ? ((TC) - 1 - (I) % (TC)) \
 313       : ((I) % (TC)) \
 314       ) \
 315    ) \
 316  )
 317
 318 /*
 319 GPR_<type>(R,I) - return, as lvalue, the I'th <type> of general register R
 320             where <type> has two letters:
 321                   1 is S=signed or U=unsigned
 322                   2 is B=byte H=halfword W=word D=doubleword
 323 */
 324
 325 #define SUB_REG_SB(A,A1,I) SUB_REG_FETCH(signed8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 326 #define SUB_REG_SH(A,A1,I) SUB_REG_FETCH(signed16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 327 #define SUB_REG_SW(A,A1,I) SUB_REG_FETCH(signed32, WORDS_IN_MIPS_REGS,       A, A1, I)
 328 #define SUB_REG_SD(A,A1,I) SUB_REG_FETCH(signed64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 329
 330 #define SUB_REG_UB(A,A1,I) SUB_REG_FETCH(unsigned8,  BYTES_IN_MIPS_REGS,       A, A1, I)
 331 #define SUB_REG_UH(A,A1,I) SUB_REG_FETCH(unsigned16, HALFWORDS_IN_MIPS_REGS,   A, A1, I)
 332 #define SUB_REG_UW(A,A1,I) SUB_REG_FETCH(unsigned32, WORDS_IN_MIPS_REGS,       A, A1, I)
 333 #define SUB_REG_UD(A,A1,I) SUB_REG_FETCH(unsigned64, DOUBLEWORDS_IN_MIPS_REGS, A, A1, I)
 334
 335 #define GPR_SB(R,I) SUB_REG_SB(&GPR[R], &GPR1[R], I)
 336 #define GPR_SH(R,I) SUB_REG_SH(&GPR[R], &GPR1[R], I)
 337 #define GPR_SW(R,I) SUB_REG_SW(&GPR[R], &GPR1[R], I)
 338 #define GPR_SD(R,I) SUB_REG_SD(&GPR[R], &GPR1[R], I)
 339
 340 #define GPR_UB(R,I) SUB_REG_UB(&GPR[R], &GPR1[R], I)
 341 #define GPR_UH(R,I) SUB_REG_UH(&GPR[R], &GPR1[R], I)
 342 #define GPR_UW(R,I) SUB_REG_UW(&GPR[R], &GPR1[R], I)
 343 #define GPR_UD(R,I) SUB_REG_UD(&GPR[R], &GPR1[R], I)
 344
 345
 346 #define RS_SB(I) SUB_REG_SB(&rs_reg, &rs_reg1, I)
 347 #define RS_SH(I) SUB_REG_SH(&rs_reg, &rs_reg1, I)
 348 #define RS_SW(I) SUB_REG_SW(&rs_reg, &rs_reg1, I)
 349 #define RS_SD(I) SUB_REG_SD(&rs_reg, &rs_reg1, I)
 350
 351 #define RS_UB(I) SUB_REG_UB(&rs_reg, &rs_reg1, I)
 352 #define RS_UH(I) SUB_REG_UH(&rs_reg, &rs_reg1, I)
 353 #define RS_UW(I) SUB_REG_UW(&rs_reg, &rs_reg1, I)
 354 #define RS_UD(I) SUB_REG_UD(&rs_reg, &rs_reg1, I)
 355
 356 #define RT_SB(I) SUB_REG_SB(&rt_reg, &rt_reg1, I)
 357 #define RT_SH(I) SUB_REG_SH(&rt_reg, &rt_reg1, I)
 358 #define RT_SW(I) SUB_REG_SW(&rt_reg, &rt_reg1, I)
 359 #define RT_SD(I) SUB_REG_SD(&rt_reg, &rt_reg1, I)
 360
 361 #define RT_UB(I) SUB_REG_UB(&rt_reg, &rt_reg1, I)
 362 #define RT_UH(I) SUB_REG_UH(&rt_reg, &rt_reg1, I)
 363 #define RT_UW(I) SUB_REG_UW(&rt_reg, &rt_reg1, I)
 364 #define RT_UD(I) SUB_REG_UD(&rt_reg, &rt_reg1, I)
 365
 366
 367
 368 #define LO_SB(I) SUB_REG_SB(&LO, &LO1, I)
 369 #define LO_SH(I) SUB_REG_SH(&LO, &LO1, I)
 370 #define LO_SW(I) SUB_REG_SW(&LO, &LO1, I)
 371 #define LO_SD(I) SUB_REG_SD(&LO, &LO1, I)
 372
 373 #define LO_UB(I) SUB_REG_UB(&LO, &LO1, I)
 374 #define LO_UH(I) SUB_REG_UH(&LO, &LO1, I)
 375 #define LO_UW(I) SUB_REG_UW(&LO, &LO1, I)
 376 #define LO_UD(I) SUB_REG_UD(&LO, &LO1, I)
 377
 378 #define HI_SB(I) SUB_REG_SB(&HI, &HI1, I)
 379 #define HI_SH(I) SUB_REG_SH(&HI, &HI1, I)
 380 #define HI_SW(I) SUB_REG_SW(&HI, &HI1, I)
 381 #define HI_SD(I) SUB_REG_SD(&HI, &HI1, I)
 382
 383 #define HI_UB(I) SUB_REG_UB(&HI, &HI1, I)
 384 #define HI_UH(I) SUB_REG_UH(&HI, &HI1, I)
 385 #define HI_UW(I) SUB_REG_UW(&HI, &HI1, I)
 386 #define HI_UD(I) SUB_REG_UD(&HI, &HI1, I)
 387
 388 /* end-sanitize-r5900 */
 389
 390
 391
 392 /* The following is probably not used for MIPS IV onwards: */
 393 /* Slots for delayed register updates. For the moment we just have a
 394    fixed number of slots (rather than a more generic, dynamic
 395    system). This keeps the simulator fast. However, we only allow
 396    for the register update to be delayed for a single instruction
 397    cycle. */
 398 #define PSLOTS (8) /* Maximum number of instruction cycles */
 399
 400 typedef struct _pending_write_queue {
 401   int in;
 402   int out;
 403   int total;
 404   int slot_delay[PSLOTS];
 405   int slot_size[PSLOTS];
 406   int slot_bit[PSLOTS];
 407   void *slot_dest[PSLOTS];
 408   unsigned64 slot_value[PSLOTS];
 409 } pending_write_queue;
 410
 411 #ifndef PENDING_TRACE
 412 #define PENDING_TRACE 0
 413 #endif
 414 #define PENDING_IN ((CPU)->pending.in)
 415 #define PENDING_OUT ((CPU)->pending.out)
 416 #define PENDING_TOTAL ((CPU)->pending.total)
 417 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 418 #define PENDING_SLOT_BIT ((CPU)->pending.slot_size)
 419 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 420 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 421 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 422
 423 /* Invalidate the pending write queue, all pending writes are
 424    discarded. */
 425
 426 #define PENDING_INVALIDATE() \
 427 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 428
 429 /* Schedule a write to DEST for N cycles time.  For 64 bit
 430    destinations, schedule two writes.  For floating point registers,
 431    the caller should schedule a write to both the dest register and
 432    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 433    is updated. */
 434
 435 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 436   do {                                                                  \
 437     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 438       sim_engine_abort (SD, CPU, cia,                                   \
 439                         "PENDING_SCHED - buffer overflow\n");           \
 440     if (PENDING_TRACE)                                                  \
 441       sim_io_printf (SD, "PENDING_SCHED - dest 0x%lx, val 0x%lx, pending_in %d, pending_out %d, pending_total %d\n", (unsigned long) (DEST), (unsigned long) (VAL), PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
 442     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 443     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 444     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 445     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 446     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 447   } while (0)
 448
 449 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 450 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 451
 452 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 453
 454 #define PENDING_FLUSH() abort () /* think about this one */
 455 #define PENDING_FP() abort () /* think about this one */
 456
 457 /* For backward compatibility */
 458 #define PENDING_FILL(R,VAL)                                             \
 459 {                                                                       \
 460   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 461     PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 2, -1);                       \
 462   else                                                                  \
 463     PENDING_SCHED(GPR[(R)], VAL, 2, -1);                                \
 464 }
 465
 466
 467
 468 struct _sim_cpu {
 469
 470
 471   /* The following are internal simulator state variables: */
 472 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 473 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 474   address_word dspc;  /* delay-slot PC */
 475 #define DSPC ((CPU)->dspc)
 476
 477 #if !WITH_IGEN
 478   /* Issue a delay slot instruction immediatly by re-calling
 479      idecode_issue */
 480 #define DELAY_SLOT(TARGET) \
 481   do { \
 482     address_word target = (TARGET); \
 483     instruction_word delay_insn; \
 484     sim_events_slip (SD, 1); \
 485     CIA = CIA + 4; /* NOTE not mips16 */ \
 486     STATE |= simDELAYSLOT; \
 487     delay_insn = IMEM32 (CIA); /* NOTE not mips16 */ \
 488     idecode_issue (CPU_, delay_insn, (CIA)); \
 489     STATE &= ~simDELAYSLOT; \
 490     NIA = target; \
 491   } while (0)
 492 #define NULLIFY_NEXT_INSTRUCTION() \
 493   do { \
 494     sim_events_slip (SD, 1); \
 495     dotrace (SD, CPU, tracefh, 2, NIA, 4, "load instruction"); \
 496     NIA = CIA + 8; \
 497   } while (0)
 498 #else
 499 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 500 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 501 #endif
 502
 503
 504   /* State of the simulator */
 505   unsigned int state;
 506   unsigned int dsstate;
 507 #define STATE ((CPU)->state)
 508 #define DSSTATE ((CPU)->dsstate)
 509
 510 /* Flags in the "state" variable: */
 511 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 512 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 513 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 514 #define simPCOC0        (1 << 17) /* COC[1] from current */
 515 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 516 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 517 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 518 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 519 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 520
 521 #define ENGINE_ISSUE_PREFIX_HOOK() \
 522   { \
 523     /* Perform any pending writes */ \
 524     PENDING_TICK(); \
 525     /* Set previous flag, depending on current: */ \
 526     if (STATE & simPCOC0) \
 527      STATE |= simPCOC1; \
 528     else \
 529      STATE &= ~simPCOC1; \
 530     /* and update the current value: */ \
 531     if (GETFCC(0)) \
 532      STATE |= simPCOC0; \
 533     else \
 534      STATE &= ~simPCOC0; \
 535   }
 536
 537
 538 /* This is nasty, since we have to rely on matching the register
 539    numbers used by GDB. Unfortunately, depending on the MIPS target
 540    GDB uses different register numbers. We cannot just include the
 541    relevant "gdb/tm.h" link, since GDB may not be configured before
 542    the sim world, and also the GDB header file requires too much other
 543    state. */
 544
 545 #ifndef TM_MIPS_H
 546 #define LAST_EMBED_REGNUM (89)
 547 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 548 /* start-sanitize-r5900 */
 549 #undef NUM_REGS
 550 #define NUM_REGS (128)
 551 /* end-sanitize-r5900 */
 552 #endif
 553
 554 /* start-sanitize-sky */
 555 #ifdef TARGET_SKY
 556 #ifndef TM_TXVU_H
 557
 558 /* Number of machine registers */
 559 #define NUM_VU_REGS     153
 560 #define NUM_VU_INTEGER_REGS 16
 561
 562 #define NUM_VIF_REGS    25
 563
 564 #define FIRST_VEC_REG   25
 565 #define NUM_R5900_REGS  128
 566
 567 #undef NUM_REGS
 568 #define NUM_REGS (NUM_R5900_REGS + 2*(NUM_VU_REGS) + 2*(NUM_VIF_REGS))
 569 #endif /* no tm-txvu.h */
 570 #endif
 571
 572 enum float_operation
 573 /* start-sanitize-sky */
 574 /* NOTE: THE VALUES of THESE CONSTANTS MUST BE IN SYNC WITH THOSE IN WF.H */
 575 /* end-sanitize-sky */
 576   {
 577     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 578     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 579     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 580   };
 581
 582 /* To keep this default simulator simple, and fast, we use a direct
 583    vector of registers. The internal simulator engine then uses
 584    manifests to access the correct slot. */
 585
 586   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 587   int register_widths[NUM_REGS];
 588 #define REGISTERS       ((CPU)->registers)
 589
 590 #define GPR     (&REGISTERS[0])
 591 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 592
 593   /* While space is allocated for the floating point registers in the
 594      main registers array, they are stored separatly.  This is because
 595      their size may not necessarily match the size of either the
 596      general-purpose or system specific registers */
 597 #define NR_FGR  (32)
 598 #define FGRIDX  (38)
 599   fp_word fgr[NR_FGR];
 600 #define FGR     ((CPU)->fgr)
 601
 602 #define LO      (REGISTERS[33])
 603 #define HI      (REGISTERS[34])
 604 #define PCIDX   37
 605 #define PC      (REGISTERS[PCIDX])
 606 #define CAUSE   (REGISTERS[36])
 607 #define SRIDX   (32)
 608 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 609 #define FCR0IDX  (71)
 610 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 611 #define FCR31IDX (70)
 612 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 613 #define FCSR    (FCR31)
 614 #define Debug   (REGISTERS[86])
 615 #define DEPC    (REGISTERS[87])
 616 #define EPC     (REGISTERS[88])
 617 #define COCIDX  (LAST_EMBED_REGNUM + 2) /* special case : outside the normal range */
 618
 619   unsigned_word c0_config_reg;
 620 #define C0_CONFIG ((CPU)->c0_config_reg)
 621
 622 /* The following are pseudonyms for standard registers */
 623 #define ZERO    (REGISTERS[0])
 624 #define V0      (REGISTERS[2])
 625 #define A0      (REGISTERS[4])
 626 #define A1      (REGISTERS[5])
 627 #define A2      (REGISTERS[6])
 628 #define A3      (REGISTERS[7])
 629 #define T8IDX   24
 630 #define T8      (REGISTERS[T8IDX])
 631 #define SPIDX   29
 632 #define SP      (REGISTERS[SPIDX])
 633 #define RAIDX   31
 634 #define RA      (REGISTERS[RAIDX])
 635
 636   /* Keep the current format state for each register: */
 637   FP_formats fpr_state[32];
 638 #define FPR_STATE ((CPU)->fpr_state)
 639
 640   pending_write_queue pending;
 641
 642   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 643      read-write instructions. It is set when a linked load occurs. It
 644      is tested and cleared by the conditional store. It is cleared
 645      (during other CPU operations) when a store to the location would
 646      no longer be atomic. In particular, it is cleared by exception
 647      return instructions. */
 648   int llbit;
 649 #define LLBIT ((CPU)->llbit)
 650
 651
 652 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 653    corruptions caused by using the HI or LO register too close to a
 654    following operation is spotted. See mips.igen for more details. */
 655
 656   hilo_history hi_history;
 657 #define HIHISTORY (&(CPU)->hi_history)
 658   hilo_history lo_history;
 659 #define LOHISTORY (&(CPU)->lo_history)
 660
 661
 662   /* start-sanitize-r5900 */
 663   sim_r5900_cpu r5900;
 664
 665   /* end-sanitize-r5900 */
 666   /* start-sanitize-vr5400 */
 667
 668   /* The MDMX ISA has a very very large accumulator */
 669   unsigned8 acc[3 * 8];
 670   /* end-sanitize-vr5400 */
 671
 672   sim_cpu_base base;
 673 };
 674
 675
 676 /* MIPS specific simulator watch config */
 677
 678 void watch_options_install PARAMS ((SIM_DESC sd));
 679
 680 struct swatch {
 681   sim_event *pc;
 682   sim_event *clock;
 683   sim_event *cycles;
 684 };
 685
 686
 687 /* FIXME: At present much of the simulator is still static */
 688 struct sim_state {
 689
 690   struct swatch watch;
 691
 692   sim_cpu cpu[MAX_NR_PROCESSORS];
 693 #if (WITH_SMP)
 694 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 695 #else
 696 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 697 #endif
 698
 699   sim_state_base base;
 700 };
 701
 702
 703
 704 /* Status information: */
 705
 706 /* TODO : these should be the bitmasks for these bits within the
 707    status register. At the moment the following are VR4300
 708    bit-positions: */
 709 #define status_KSU_mask  (0x3)          /* mask for KSU bits */
 710 #define status_KSU_shift (3)            /* shift for field */
 711 #define ksu_kernel       (0x0)
 712 #define ksu_supervisor   (0x1)
 713 #define ksu_user         (0x2)
 714 #define ksu_unknown      (0x3)
 715
 716 #define status_IE        (1 <<  0)      /* Interrupt enable */
 717 #define status_EXL       (1 <<  1)      /* Exception level */
 718 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 719 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 720 #define status_SR        (1 << 20)      /* soft reset or NMI */
 721 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 722 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 723 #define status_ERL       (1 <<  2)      /* Error level */
 724 #define status_RP        (1 << 27)      /* Reduced Power mode */
 725 /* start-sanitize-r5900 */
 726 #define status_CU0       (1 << 28)      /* COP0 usable */
 727 #define status_CU1       (1 << 29)      /* COP1 usable */
 728 #define status_CU2       (1 << 30)      /* COP2 usable */
 729 /* end-sanitize-r5900 */
 730
 731 #define cause_BD        ((unsigned)1 << 31)     /* Exception in branch delay slot */
 732
 733 /* NOTE: We keep the following status flags as bit values (1 for true,
 734    0 for false). This allows them to be used in binary boolean
 735    operations without worrying about what exactly the non-zero true
 736    value is. */
 737
 738 /* UserMode */
 739 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 740
 741 /* BigEndianMem */
 742 /* Hardware configuration. Affects endianness of LoadMemory and
 743    StoreMemory and the endianness of Kernel and Supervisor mode
 744    execution. The value is 0 for little-endian; 1 for big-endian. */
 745 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 746 /*(state & simBE) ? 1 : 0)*/
 747
 748 /* ReverseEndian */
 749 /* This mode is selected if in User mode with the RE bit being set in
 750    SR (Status Register). It reverses the endianness of load and store
 751    instructions. */
 752 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 753
 754 /* BigEndianCPU */
 755 /* The endianness for load and store instructions (0=little;1=big). In
 756    User mode this endianness may be switched by setting the state_RE
 757    bit in the SR register. Thus, BigEndianCPU may be computed as
 758    (BigEndianMem EOR ReverseEndian). */
 759 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 760
 761
 762
 763 /* Exceptions: */
 764
 765 /* NOTE: These numbers depend on the processor architecture being
 766    simulated: */
 767 #define Interrupt               (0)
 768 #define TLBModification         (1)
 769 #define TLBLoad                 (2)
 770 #define TLBStore                (3)
 771 #define AddressLoad             (4)
 772 #define AddressStore            (5)
 773 #define InstructionFetch        (6)
 774 #define DataReference           (7)
 775 #define SystemCall              (8)
 776 #define BreakPoint              (9)
 777 #define ReservedInstruction     (10)
 778 #define CoProcessorUnusable     (11)
 779 #define IntegerOverflow         (12)    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 780 #define Trap                    (13)
 781 #define FPE                     (15)
 782 #define DebugBreakPoint         (16)
 783 #define Watch                   (23)
 784
 785 /* The following exception code is actually private to the simulator
 786    world. It is *NOT* a processor feature, and is used to signal
 787    run-time errors in the simulator. */
 788 #define SimulatorFault      (0xFFFFFFFF)
 789
 790 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 791 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 792 #define SignalExceptionInterrupt()           signal_exception (SD, CPU, NULL_CIA, Interrupt)
 793 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 794 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 795 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 796 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 797 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 798 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 799 #define SignalExceptionCoProcessorUnusable() signal_exception (SD, CPU, cia, CoProcessorUnusable)
 800
 801
 802 /* Co-processor accesses */
 803
 804 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 805 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 806 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 807 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 808
 809 #define COP_LW(coproc_num,coproc_reg,memword) \
 810 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 811 #define COP_LD(coproc_num,coproc_reg,memword) \
 812 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 813 #define COP_SW(coproc_num,coproc_reg) \
 814 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 815 #define COP_SD(coproc_num,coproc_reg) \
 816 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 817
 818 /* start-sanitize-sky */
 819 #ifdef TARGET_SKY
 820 void cop_lq  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 821                       int coproc_num, int coproc_reg, unsigned128 memword));
 822 unsigned128 cop_sq PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia,
 823                             int coproc_num, int coproc_reg));
 824 #define COP_LQ(coproc_num,coproc_reg,memword) \
 825 cop_lq (SD, CPU, cia, coproc_num, coproc_reg, memword)
 826 #define COP_SQ(coproc_num,coproc_reg) \
 827 cop_sq (SD, CPU, cia, coproc_num, coproc_reg)
 828 #endif /* TARGET_SKY */
 829 /* end-sanitize-sky */
 830
 831 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 832 #define DecodeCoproc(instruction) \
 833 decode_coproc (SD, CPU, cia, (instruction))
 834
 835
 836
 837 /* Memory accesses */
 838
 839 /* The following are generic to all versions of the MIPS architecture
 840    to date: */
 841
 842 /* Memory Access Types (for CCA): */
 843 #define Uncached                (0)
 844 #define CachedNoncoherent       (1)
 845 #define CachedCoherent          (2)
 846 #define Cached                  (3)
 847
 848 #define isINSTRUCTION   (1 == 0) /* FALSE */
 849 #define isDATA          (1 == 1) /* TRUE */
 850 #define isLOAD          (1 == 0) /* FALSE */
 851 #define isSTORE         (1 == 1) /* TRUE */
 852 #define isREAL          (1 == 0) /* FALSE */
 853 #define isRAW           (1 == 1) /* TRUE */
 854 /* The parameter HOST (isTARGET / isHOST) is ignored */
 855 #define isTARGET        (1 == 0) /* FALSE */
 856 /* #define isHOST          (1 == 1) TRUE */
 857
 858 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 859    is the number of bytes minus 1. */
 860 #define AccessLength_BYTE       (0)
 861 #define AccessLength_HALFWORD   (1)
 862 #define AccessLength_TRIPLEBYTE (2)
 863 #define AccessLength_WORD       (3)
 864 #define AccessLength_QUINTIBYTE (4)
 865 #define AccessLength_SEXTIBYTE  (5)
 866 #define AccessLength_SEPTIBYTE  (6)
 867 #define AccessLength_DOUBLEWORD (7)
 868 #define AccessLength_QUADWORD   (15)
 869
 870 #if (WITH_IGEN)
 871 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 872                     ? AccessLength_DOUBLEWORD /*7*/ \
 873                     : AccessLength_WORD /*3*/)
 874 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 875 #endif
 876
 877
 878 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 879 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 880 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 881
 882 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 883 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 884 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 885
 886 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 887 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 888 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 889
 890 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 891 #define CacheOp(op,pAddr,vAddr,instruction) \
 892 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 893
 894 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 895 #define SyncOperation(stype) \
 896 sync_operation (SD, CPU, cia, (stype))
 897
 898 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 899 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 900 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 901
 902 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 903 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 904 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 905 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 906 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 907
 908 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 909 FILE *tracefh;
 910
 911 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 912
 913 char* pr_addr PARAMS ((SIM_ADDR addr));
 914 char* pr_uword64 PARAMS ((uword64 addr));
 915
 916
 917 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 918 #include "sim-main.c"
 919 #endif
 920
 921 #endif