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[binutils-gdb.git] / sim / mips / sim-main.h
1 /* MIPS Simulator definition.
2 Copyright (C) 1997-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of the MIPS sim.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #ifndef SIM_MAIN_H
21 #define SIM_MAIN_H
22
23 /* hobble some common features for moment */
24 #define WITH_WATCHPOINTS 1
25
26
27 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
28 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
29
30 #include "sim-basics.h"
31 #include "sim-base.h"
32 #include "bfd.h"
33
34 /* Deprecated macros and types for manipulating 64bit values. Use
35 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
36
37 typedef signed64 word64;
38 typedef unsigned64 uword64;
39
40 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
41 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
42 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
43 #define SET64HI(t) (((uword64)(t))<<32)
44 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
45 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
46
47 /* Check if a value will fit within a halfword: */
48 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
49
50
51 typedef enum {
52 cp0_dmfc0,
53 cp0_dmtc0,
54 cp0_mfc0,
55 cp0_mtc0,
56 cp0_tlbr,
57 cp0_tlbwi,
58 cp0_tlbwr,
59 cp0_tlbp,
60 cp0_cache,
61 cp0_eret,
62 cp0_deret,
63 cp0_rfe
64 } CP0_operation;
65
66 /* Floating-point operations: */
67
68 #include "sim-fpu.h"
69 #include "cp1.h"
70
71 /* FPU registers must be one of the following types. All other values
72 are reserved (and undefined). */
73 typedef enum {
74 fmt_single = 0,
75 fmt_double = 1,
76 fmt_word = 4,
77 fmt_long = 5,
78 fmt_ps = 6,
79 /* The following are well outside the normal acceptable format
80 range, and are used in the register status vector. */
81 fmt_unknown = 0x10000000,
82 fmt_uninterpreted = 0x20000000,
83 fmt_uninterpreted_32 = 0x40000000,
84 fmt_uninterpreted_64 = 0x80000000U,
85 } FP_formats;
86
87 /* For paired word (pw) operations, the opcode representation is fmt_word,
88 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
89 #define fmt_pw fmt_long
90
91 /* This should be the COC1 value at the start of the preceding
92 instruction: */
93 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
94
95 #ifdef TARGET_ENABLE_FR
96 /* FIXME: this should be enabled for all targets, but needs testing first. */
97 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
98 ? ((SR & status_FR) ? 64 : 32) \
99 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
100 #else
101 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
102 #endif
103
104
105
106
107
108 /* HI/LO register accesses */
109
110 /* For some MIPS targets, the HI/LO registers have certain timing
111 restrictions in that, for instance, a read of a HI register must be
112 separated by at least three instructions from a preceeding read.
113
114 The struct below is used to record the last access by each of A MT,
115 MF or other OP instruction to a HI/LO register. See mips.igen for
116 more details. */
117
118 typedef struct _hilo_access {
119 signed64 timestamp;
120 address_word cia;
121 } hilo_access;
122
123 typedef struct _hilo_history {
124 hilo_access mt;
125 hilo_access mf;
126 hilo_access op;
127 } hilo_history;
128
129
130
131
132 /* Integer ALU operations: */
133
134 #include "sim-alu.h"
135
136 #define ALU32_END(ANS) \
137 if (ALU32_HAD_OVERFLOW) \
138 SignalExceptionIntegerOverflow (); \
139 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
140
141
142 #define ALU64_END(ANS) \
143 if (ALU64_HAD_OVERFLOW) \
144 SignalExceptionIntegerOverflow (); \
145 (ANS) = ALU64_OVERFLOW_RESULT;
146
147
148
149
150
151 /* The following is probably not used for MIPS IV onwards: */
152 /* Slots for delayed register updates. For the moment we just have a
153 fixed number of slots (rather than a more generic, dynamic
154 system). This keeps the simulator fast. However, we only allow
155 for the register update to be delayed for a single instruction
156 cycle. */
157 #define PSLOTS (8) /* Maximum number of instruction cycles */
158
159 typedef struct _pending_write_queue {
160 int in;
161 int out;
162 int total;
163 int slot_delay[PSLOTS];
164 int slot_size[PSLOTS];
165 int slot_bit[PSLOTS];
166 void *slot_dest[PSLOTS];
167 unsigned64 slot_value[PSLOTS];
168 } pending_write_queue;
169
170 #ifndef PENDING_TRACE
171 #define PENDING_TRACE 0
172 #endif
173 #define PENDING_IN ((CPU)->pending.in)
174 #define PENDING_OUT ((CPU)->pending.out)
175 #define PENDING_TOTAL ((CPU)->pending.total)
176 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
177 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
178 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
179 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
180 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
181
182 /* Invalidate the pending write queue, all pending writes are
183 discarded. */
184
185 #define PENDING_INVALIDATE() \
186 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
187
188 /* Schedule a write to DEST for N cycles time. For 64 bit
189 destinations, schedule two writes. For floating point registers,
190 the caller should schedule a write to both the dest register and
191 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
192 is updated. */
193
194 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
195 do { \
196 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
197 sim_engine_abort (SD, CPU, cia, \
198 "PENDING_SCHED - buffer overflow\n"); \
199 if (PENDING_TRACE) \
200 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
201 (unsigned long) cia, (unsigned long) &(DEST), \
202 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
203 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
204 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
205 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
206 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
207 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
208 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
209 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
210 PENDING_TOTAL += 1; \
211 } while (0)
212
213 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
214 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
215
216 #define PENDING_TICK() pending_tick (SD, CPU, cia)
217
218 #define PENDING_FLUSH() abort () /* think about this one */
219 #define PENDING_FP() abort () /* think about this one */
220
221 /* For backward compatibility */
222 #define PENDING_FILL(R,VAL) \
223 do { \
224 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
225 { \
226 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
227 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
228 } \
229 else \
230 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
231 } while (0)
232
233
234 enum float_operation
235 {
236 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
237 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
238 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
239 };
240
241
242 /* The internal representation of an MDMX accumulator.
243 Note that 24 and 48 bit accumulator elements are represented in
244 32 or 64 bits. Since the accumulators are 2's complement with
245 overflow suppressed, high-order bits can be ignored in most contexts. */
246
247 typedef signed32 signed24;
248 typedef signed64 signed48;
249
250 typedef union {
251 signed24 ob[8];
252 signed48 qh[4];
253 } MDMX_accumulator;
254
255
256 /* Conventional system arguments. */
257 #define SIM_STATE sim_cpu *cpu, address_word cia
258 #define SIM_ARGS CPU, cia
259
260 struct _sim_cpu {
261
262
263 /* The following are internal simulator state variables: */
264 address_word dspc; /* delay-slot PC */
265 #define DSPC ((CPU)->dspc)
266
267 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
268 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
269
270
271 /* State of the simulator */
272 unsigned int state;
273 unsigned int dsstate;
274 #define STATE ((CPU)->state)
275 #define DSSTATE ((CPU)->dsstate)
276
277 /* Flags in the "state" variable: */
278 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
279 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
280 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
281 #define simPCOC0 (1 << 17) /* COC[1] from current */
282 #define simPCOC1 (1 << 18) /* COC[1] from previous */
283 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
284 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
285 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
286 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
287
288 #ifndef ENGINE_ISSUE_PREFIX_HOOK
289 #define ENGINE_ISSUE_PREFIX_HOOK() \
290 { \
291 /* Perform any pending writes */ \
292 PENDING_TICK(); \
293 /* Set previous flag, depending on current: */ \
294 if (STATE & simPCOC0) \
295 STATE |= simPCOC1; \
296 else \
297 STATE &= ~simPCOC1; \
298 /* and update the current value: */ \
299 if (GETFCC(0)) \
300 STATE |= simPCOC0; \
301 else \
302 STATE &= ~simPCOC0; \
303 }
304 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
305
306
307 /* This is nasty, since we have to rely on matching the register
308 numbers used by GDB. Unfortunately, depending on the MIPS target
309 GDB uses different register numbers. We cannot just include the
310 relevant "gdb/tm.h" link, since GDB may not be configured before
311 the sim world, and also the GDB header file requires too much other
312 state. */
313
314 #ifndef TM_MIPS_H
315 #define LAST_EMBED_REGNUM (96)
316 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
317
318 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
319 #define FCRCS_REGNUM 70 /* FP control/status */
320 #define FCRIR_REGNUM 71 /* FP implementation/revision */
321 #endif
322
323
324 /* To keep this default simulator simple, and fast, we use a direct
325 vector of registers. The internal simulator engine then uses
326 manifests to access the correct slot. */
327
328 unsigned_word registers[LAST_EMBED_REGNUM + 1];
329
330 int register_widths[NUM_REGS];
331 #define REGISTERS ((CPU)->registers)
332
333 #define GPR (&REGISTERS[0])
334 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
335
336 #define LO (REGISTERS[33])
337 #define HI (REGISTERS[34])
338 #define PCIDX 37
339 #define PC (REGISTERS[PCIDX])
340 #define CAUSE (REGISTERS[36])
341 #define SRIDX (32)
342 #define SR (REGISTERS[SRIDX]) /* CPU status register */
343 #define FCR0IDX (71)
344 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
345 #define FCR31IDX (70)
346 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
347 #define FCSR (FCR31)
348 #define Debug (REGISTERS[86])
349 #define DEPC (REGISTERS[87])
350 #define EPC (REGISTERS[88])
351 #define ACX (REGISTERS[89])
352
353 #define AC0LOIDX (33) /* Must be the same register as LO */
354 #define AC0HIIDX (34) /* Must be the same register as HI */
355 #define AC1LOIDX (90)
356 #define AC1HIIDX (91)
357 #define AC2LOIDX (92)
358 #define AC2HIIDX (93)
359 #define AC3LOIDX (94)
360 #define AC3HIIDX (95)
361
362 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
363 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
364
365 #define DSPCRIDX (96) /* DSP control register */
366 #define DSPCR (REGISTERS[DSPCRIDX])
367
368 #define DSPCR_POS_SHIFT (0)
369 #define DSPCR_POS_MASK (0x3f)
370 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
371
372 #define DSPCR_SCOUNT_SHIFT (7)
373 #define DSPCR_SCOUNT_MASK (0x3f)
374 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
375
376 #define DSPCR_CARRY_SHIFT (13)
377 #define DSPCR_CARRY_MASK (1)
378 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
379 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
380
381 #define DSPCR_EFI_SHIFT (14)
382 #define DSPCR_EFI_MASK (1)
383 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
384 #define DSPCR_EFI (1 << DSPCR_EFI_MASK)
385
386 #define DSPCR_OUFLAG_SHIFT (16)
387 #define DSPCR_OUFLAG_MASK (0xff)
388 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
389 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
390 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
391 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
392 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
393
394 #define DSPCR_CCOND_SHIFT (24)
395 #define DSPCR_CCOND_MASK (0xf)
396 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
397
398 /* All internal state modified by signal_exception() that may need to be
399 rolled back for passing moment-of-exception image back to gdb. */
400 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
401 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
402 int exc_suspended;
403
404 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
405 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
406 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
407
408 unsigned_word c0_config_reg;
409 #define C0_CONFIG ((CPU)->c0_config_reg)
410
411 /* The following are pseudonyms for standard registers */
412 #define ZERO (REGISTERS[0])
413 #define V0 (REGISTERS[2])
414 #define A0 (REGISTERS[4])
415 #define A1 (REGISTERS[5])
416 #define A2 (REGISTERS[6])
417 #define A3 (REGISTERS[7])
418 #define T8IDX 24
419 #define T8 (REGISTERS[T8IDX])
420 #define SPIDX 29
421 #define SP (REGISTERS[SPIDX])
422 #define RAIDX 31
423 #define RA (REGISTERS[RAIDX])
424
425 /* While space is allocated in the main registers arrray for some of
426 the COP0 registers, that space isn't sufficient. Unknown COP0
427 registers overflow into the array below */
428
429 #define NR_COP0_GPR 32
430 unsigned_word cop0_gpr[NR_COP0_GPR];
431 #define COP0_GPR ((CPU)->cop0_gpr)
432 #define COP0_BADVADDR (COP0_GPR[8])
433
434 /* While space is allocated for the floating point registers in the
435 main registers array, they are stored separatly. This is because
436 their size may not necessarily match the size of either the
437 general-purpose or system specific registers. */
438 #define NR_FGR (32)
439 #define FGR_BASE FP0_REGNUM
440 fp_word fgr[NR_FGR];
441 #define FGR ((CPU)->fgr)
442
443 /* Keep the current format state for each register: */
444 FP_formats fpr_state[32];
445 #define FPR_STATE ((CPU)->fpr_state)
446
447 pending_write_queue pending;
448
449 /* The MDMX accumulator (used only for MDMX ASE). */
450 MDMX_accumulator acc;
451 #define ACC ((CPU)->acc)
452
453 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
454 read-write instructions. It is set when a linked load occurs. It
455 is tested and cleared by the conditional store. It is cleared
456 (during other CPU operations) when a store to the location would
457 no longer be atomic. In particular, it is cleared by exception
458 return instructions. */
459 int llbit;
460 #define LLBIT ((CPU)->llbit)
461
462
463 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
464 corruptions caused by using the HI or LO register too close to a
465 following operation is spotted. See mips.igen for more details. */
466
467 hilo_history hi_history;
468 #define HIHISTORY (&(CPU)->hi_history)
469 hilo_history lo_history;
470 #define LOHISTORY (&(CPU)->lo_history)
471
472
473 sim_cpu_base base;
474 };
475
476 extern void mips_sim_close (SIM_DESC sd, int quitting);
477 #define SIM_CLOSE_HOOK(...) mips_sim_close (__VA_ARGS__)
478
479 /* MIPS specific simulator watch config */
480
481 void watch_options_install (SIM_DESC sd);
482
483 struct swatch {
484 sim_event *pc;
485 sim_event *clock;
486 sim_event *cycles;
487 };
488
489
490 /* FIXME: At present much of the simulator is still static */
491 struct sim_state {
492
493 struct swatch watch;
494
495 sim_cpu *cpu[MAX_NR_PROCESSORS];
496
497 /* microMIPS ISA mode. */
498 int isa_mode;
499
500 sim_state_base base;
501 };
502
503
504
505 /* Status information: */
506
507 /* TODO : these should be the bitmasks for these bits within the
508 status register. At the moment the following are VR4300
509 bit-positions: */
510 #define status_KSU_mask (0x18) /* mask for KSU bits */
511 #define status_KSU_shift (3) /* shift for field */
512 #define ksu_kernel (0x0)
513 #define ksu_supervisor (0x1)
514 #define ksu_user (0x2)
515 #define ksu_unknown (0x3)
516
517 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
518
519 #define status_IE (1 << 0) /* Interrupt enable */
520 #define status_EIE (1 << 16) /* Enable Interrupt Enable */
521 #define status_EXL (1 << 1) /* Exception level */
522 #define status_RE (1 << 25) /* Reverse Endian in user mode */
523 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
524 #define status_SR (1 << 20) /* soft reset or NMI */
525 #define status_BEV (1 << 22) /* Location of general exception vectors */
526 #define status_TS (1 << 21) /* TLB shutdown has occurred */
527 #define status_ERL (1 << 2) /* Error level */
528 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */
529 #define status_RP (1 << 27) /* Reduced Power mode */
530
531 /* Specializations for TX39 family */
532 #define status_IEc (1 << 0) /* Interrupt enable (current) */
533 #define status_KUc (1 << 1) /* Kernel/User mode */
534 #define status_IEp (1 << 2) /* Interrupt enable (previous) */
535 #define status_KUp (1 << 3) /* Kernel/User mode */
536 #define status_IEo (1 << 4) /* Interrupt enable (old) */
537 #define status_KUo (1 << 5) /* Kernel/User mode */
538 #define status_IM_mask (0xff) /* Interrupt mask */
539 #define status_IM_shift (8)
540 #define status_NMI (1 << 20) /* NMI */
541 #define status_NMI (1 << 20) /* NMI */
542
543 /* Status bits used by MIPS32/MIPS64. */
544 #define status_UX (1 << 5) /* 64-bit user addrs */
545 #define status_SX (1 << 6) /* 64-bit supervisor addrs */
546 #define status_KX (1 << 7) /* 64-bit kernel addrs */
547 #define status_TS (1 << 21) /* TLB shutdown has occurred */
548 #define status_PX (1 << 23) /* Enable 64 bit operations */
549 #define status_MX (1 << 24) /* Enable MDMX resources */
550 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */
551 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */
552 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */
553 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */
554 /* Bits reserved for implementations: */
555 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
556
557 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
558 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
559 #define cause_CE_mask 0x30000000 /* Coprocessor exception */
560 #define cause_CE_shift 28
561 #define cause_EXC2_mask 0x00070000
562 #define cause_EXC2_shift 16
563 #define cause_IP7 (1 << 15) /* Interrupt pending */
564 #define cause_SIOP (1 << 12) /* SIO pending */
565 #define cause_IP3 (1 << 11) /* Int 0 pending */
566 #define cause_IP2 (1 << 10) /* Int 1 pending */
567
568 #define cause_EXC_mask (0x1c) /* Exception code */
569 #define cause_EXC_shift (2)
570
571 #define cause_SW0 (1 << 8) /* Software interrupt 0 */
572 #define cause_SW1 (1 << 9) /* Software interrupt 1 */
573 #define cause_IP_mask (0x3f) /* Interrupt pending field */
574 #define cause_IP_shift (10)
575
576 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
577 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
578
579
580 /* NOTE: We keep the following status flags as bit values (1 for true,
581 0 for false). This allows them to be used in binary boolean
582 operations without worrying about what exactly the non-zero true
583 value is. */
584
585 /* UserMode */
586 #ifdef SUBTARGET_R3900
587 #define UserMode ((SR & status_KUc) ? 1 : 0)
588 #else
589 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
590 #endif /* SUBTARGET_R3900 */
591
592 /* BigEndianMem */
593 /* Hardware configuration. Affects endianness of LoadMemory and
594 StoreMemory and the endianness of Kernel and Supervisor mode
595 execution. The value is 0 for little-endian; 1 for big-endian. */
596 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
597 /*(state & simBE) ? 1 : 0)*/
598
599 /* ReverseEndian */
600 /* This mode is selected if in User mode with the RE bit being set in
601 SR (Status Register). It reverses the endianness of load and store
602 instructions. */
603 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
604
605 /* BigEndianCPU */
606 /* The endianness for load and store instructions (0=little;1=big). In
607 User mode this endianness may be switched by setting the state_RE
608 bit in the SR register. Thus, BigEndianCPU may be computed as
609 (BigEndianMem EOR ReverseEndian). */
610 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
611
612
613
614 /* Exceptions: */
615
616 /* NOTE: These numbers depend on the processor architecture being
617 simulated: */
618 enum ExceptionCause {
619 Interrupt = 0,
620 TLBModification = 1,
621 TLBLoad = 2,
622 TLBStore = 3,
623 AddressLoad = 4,
624 AddressStore = 5,
625 InstructionFetch = 6,
626 DataReference = 7,
627 SystemCall = 8,
628 BreakPoint = 9,
629 ReservedInstruction = 10,
630 CoProcessorUnusable = 11,
631 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
632 Trap = 13,
633 FPE = 15,
634 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
635 MDMX = 22,
636 Watch = 23,
637 MCheck = 24,
638 CacheErr = 30,
639 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
640
641
642 /* The following exception code is actually private to the simulator
643 world. It is *NOT* a processor feature, and is used to signal
644 run-time errors in the simulator. */
645 SimulatorFault = 0xFFFFFFFF
646 };
647
648 #define TLB_REFILL (0)
649 #define TLB_INVALID (1)
650
651
652 /* The following break instructions are reserved for use by the
653 simulator. The first is used to halt the simulation. The second
654 is used by gdb for break-points. NOTE: Care must be taken, since
655 this value may be used in later revisions of the MIPS ISA. */
656 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
657
658 #define HALT_INSTRUCTION (0x03ff000d)
659 #define HALT_INSTRUCTION2 (0x0000ffcd)
660
661
662 #define BREAKPOINT_INSTRUCTION (0x0005000d)
663 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
664
665
666
667 void interrupt_event (SIM_DESC sd, void *data);
668
669 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
670 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
671 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
672 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
673 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
674 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
675 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
676 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
677 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
678 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
679 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
680 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
681 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
682 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
683 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
684 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
685 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
686 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
687 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
688 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
689 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
690
691 /* Co-processor accesses */
692
693 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
694 #define COP_Usable(coproc_num) (coproc_num == 1)
695
696 void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
697 void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
698 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
699 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
700
701 #define COP_LW(coproc_num,coproc_reg,memword) \
702 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
703 #define COP_LD(coproc_num,coproc_reg,memword) \
704 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
705 #define COP_SW(coproc_num,coproc_reg) \
706 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
707 #define COP_SD(coproc_num,coproc_reg) \
708 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
709
710
711 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia,
712 unsigned int instruction, int coprocnum, CP0_operation op,
713 int rt, int rd, int sel);
714 #define DecodeCoproc(instruction,coprocnum,op,rt,rd,sel) \
715 decode_coproc (SD, CPU, cia, (instruction), (coprocnum), (op), \
716 (rt), (rd), (sel))
717
718 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
719
720
721 /* FPR access. */
722 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
723 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
724 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
725 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
726 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
727 #define PSLower(op) ps_lower (SIM_ARGS, op)
728 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
729 #define PSUpper(op) ps_upper (SIM_ARGS, op)
730 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
731 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
732
733
734 /* FCR access. */
735 unsigned_word value_fcr (SIM_STATE, int fcr);
736 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
737 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
738 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
739 void test_fcsr (SIM_STATE);
740 #define TestFCSR() test_fcsr (SIM_ARGS)
741
742
743 /* FPU operations. */
744 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
745 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
746 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
747 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
748 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
749 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
750 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
751 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
752 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
753 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
754 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
755 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
756 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
757 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
758 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
759 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
760 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
761 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
762 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
763 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
764 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
765 unsigned64 op3, FP_formats fmt);
766 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
767 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
768 unsigned64 op3, FP_formats fmt);
769 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
770 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
771 unsigned64 op3, FP_formats fmt);
772 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
773 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
774 unsigned64 op3, FP_formats fmt);
775 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
776 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
777 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
778 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
779 FP_formats to);
780 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
781
782
783 /* MIPS-3D ASE operations. */
784 #define CompareAbs(op1,op2,fmt,cond,cc) \
785 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
786 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
787 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
788 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
789 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
790 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
791 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
792 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
793 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
794 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
795 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
796 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
797 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
798
799
800 /* MDMX access. */
801
802 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
803 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
804 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
805
806 #define fmt_mdmx fmt_uninterpreted
807
808 #define MX_VECT_AND (0)
809 #define MX_VECT_NOR (1)
810 #define MX_VECT_OR (2)
811 #define MX_VECT_XOR (3)
812 #define MX_VECT_SLL (4)
813 #define MX_VECT_SRL (5)
814 #define MX_VECT_ADD (6)
815 #define MX_VECT_SUB (7)
816 #define MX_VECT_MIN (8)
817 #define MX_VECT_MAX (9)
818 #define MX_VECT_MUL (10)
819 #define MX_VECT_MSGN (11)
820 #define MX_VECT_SRA (12)
821 #define MX_VECT_ABSD (13) /* SB-1 only. */
822 #define MX_VECT_AVG (14) /* SB-1 only. */
823
824 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
825 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
826 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
827 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
828 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
829 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
830 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
831 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
832 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
833 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
834 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
835 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
836 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
837 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
838 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
839 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
840
841 #define MX_C_EQ 0x1
842 #define MX_C_LT 0x4
843
844 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
845 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
846
847 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
848 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
849
850 #define MX_VECT_ADDA (0)
851 #define MX_VECT_ADDL (1)
852 #define MX_VECT_MULA (2)
853 #define MX_VECT_MULL (3)
854 #define MX_VECT_MULS (4)
855 #define MX_VECT_MULSL (5)
856 #define MX_VECT_SUBA (6)
857 #define MX_VECT_SUBL (7)
858 #define MX_VECT_ABSDA (8) /* SB-1 only. */
859
860 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
861 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
862 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
863 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
864 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
865 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
866 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
867 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
868 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
869 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
870
871 #define MX_FMT_OB (0)
872 #define MX_FMT_QH (1)
873
874 /* The following codes chosen to indicate the units of shift. */
875 #define MX_RAC_L (0)
876 #define MX_RAC_M (1)
877 #define MX_RAC_H (2)
878
879 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
880 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
881
882 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
883 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
884 void mdmx_wach (SIM_STATE, int, unsigned64);
885 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
886
887 #define MX_RND_AS (0)
888 #define MX_RND_AU (1)
889 #define MX_RND_ES (2)
890 #define MX_RND_EU (3)
891 #define MX_RND_ZS (4)
892 #define MX_RND_ZU (5)
893
894 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
895 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
896 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
897 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
898 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
899 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
900 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
901
902 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
903 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
904
905
906
907 /* Memory accesses */
908
909 /* The following are generic to all versions of the MIPS architecture
910 to date: */
911
912 /* Memory Access Types (for CCA): */
913 #define Uncached (0)
914 #define CachedNoncoherent (1)
915 #define CachedCoherent (2)
916 #define Cached (3)
917
918 #define isINSTRUCTION (1 == 0) /* FALSE */
919 #define isDATA (1 == 1) /* TRUE */
920 #define isLOAD (1 == 0) /* FALSE */
921 #define isSTORE (1 == 1) /* TRUE */
922 #define isREAL (1 == 0) /* FALSE */
923 #define isRAW (1 == 1) /* TRUE */
924 /* The parameter HOST (isTARGET / isHOST) is ignored */
925 #define isTARGET (1 == 0) /* FALSE */
926 /* #define isHOST (1 == 1) TRUE */
927
928 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
929 is the number of bytes minus 1. */
930 #define AccessLength_BYTE (0)
931 #define AccessLength_HALFWORD (1)
932 #define AccessLength_TRIPLEBYTE (2)
933 #define AccessLength_WORD (3)
934 #define AccessLength_QUINTIBYTE (4)
935 #define AccessLength_SEXTIBYTE (5)
936 #define AccessLength_SEPTIBYTE (6)
937 #define AccessLength_DOUBLEWORD (7)
938 #define AccessLength_QUADWORD (15)
939
940 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
941 ? AccessLength_DOUBLEWORD /*7*/ \
942 : AccessLength_WORD /*3*/)
943 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
944
945
946 INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
947 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
948 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
949
950 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
951 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
952 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
953
954 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
955 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
956 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
957
958 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
959 #define CacheOp(op,pAddr,vAddr,instruction) \
960 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
961
962 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
963 #define SyncOperation(stype) \
964 sync_operation (SD, CPU, cia, (stype))
965
966 INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
967 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
968 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
969
970 void unpredictable_action (sim_cpu *cpu, address_word cia);
971 #define NotWordValue(val) not_word_value (SD_, (val))
972 #define Unpredictable() unpredictable (SD_)
973 #define UnpredictableResult() /* For now, do nothing. */
974
975 INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
976 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
977 INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
978 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
979 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
980 #define IMEM32_MICROMIPS(CIA) \
981 (ifetch16 (SD, CPU, (CIA), (CIA)) << 16 | ifetch16 (SD, CPU, (CIA + 2), \
982 (CIA + 2)))
983 #define IMEM16_MICROMIPS(CIA) ifetch16 (SD, CPU, (CIA), ((CIA)))
984
985 #define MICROMIPS_MINOR_OPCODE(INSN) ((INSN & 0x1C00) >> 10)
986
987 #define MICROMIPS_DELAYSLOT_SIZE_ANY 0
988 #define MICROMIPS_DELAYSLOT_SIZE_16 2
989 #define MICROMIPS_DELAYSLOT_SIZE_32 4
990
991 extern int isa_mode;
992
993 #define ISA_MODE_MIPS32 0
994 #define ISA_MODE_MICROMIPS 1
995
996 address_word micromips_instruction_decode (SIM_DESC sd, sim_cpu * cpu,
997 address_word cia,
998 int instruction_size);
999
1000 #if WITH_TRACE_ANY_P
1001 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
1002 extern FILE *tracefh;
1003 #else
1004 #define dotrace(sd, cpu, tracefh, type, address, width, comment, ...)
1005 #endif
1006
1007 extern int DSPLO_REGNUM[4];
1008 extern int DSPHI_REGNUM[4];
1009
1010 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
1011 extern SIM_CORE_SIGNAL_FN mips_core_signal;
1012
1013 char* pr_addr (SIM_ADDR addr);
1014 char* pr_uword64 (uword64 addr);
1015
1016
1017 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
1018
1019 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
1020 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
1021 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
1022
1023 #ifdef MIPS_MACH_MULTI
1024 extern int mips_mach_multi(SIM_DESC sd);
1025 #define MIPS_MACH(SD) mips_mach_multi(SD)
1026 #else
1027 #define MIPS_MACH(SD) MIPS_MACH_DEFAULT
1028 #endif
1029
1030 /* Macros for determining whether a MIPS IV or MIPS V part is subject
1031 to the hi/lo restrictions described in mips.igen. */
1032
1033 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
1034 (MIPS_MACH (SD) != bfd_mach_mips5500)
1035
1036 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
1037 (MIPS_MACH (SD) != bfd_mach_mips5500)
1038
1039 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1040 (MIPS_MACH (SD) != bfd_mach_mips5500)
1041
1042 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1043 #include "sim-main.c"
1044 #endif
1045
1046 #endif