sim/mips/sim-main.h

   1 /* MIPS Simulator definition.
   2    Copyright (C) 1997, 1998 Free Software Foundation, Inc.
   3    Contributed by Cygnus Support.
   4
   5 This file is part of GDB, the GNU debugger.
   6
   7 This program is free software; you can redistribute it and/or modify
   8 it under the terms of the GNU General Public License as published by
   9 the Free Software Foundation; either version 2, or (at your option)
  10 any later version.
  11
  12 This program is distributed in the hope that it will be useful,
  13 but WITHOUT ANY WARRANTY; without even the implied warranty of
  14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  15 GNU General Public License for more details.
  16
  17 You should have received a copy of the GNU General Public License along
  18 with this program; if not, write to the Free Software Foundation, Inc.,
  19 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.  */
  20
  21 #ifndef SIM_MAIN_H
  22 #define SIM_MAIN_H
  23
  24 /* This simulator doesn't cache the Current Instruction Address */
  25 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
  26 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
  27
  28 #define SIM_HAVE_BIENDIAN
  29
  30
  31 /* hobble some common features for moment */
  32 #define WITH_WATCHPOINTS 1
  33 #define WITH_MODULO_MEMORY 1
  34
  35
  36 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
  37 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
  38
  39 #include "sim-basics.h"
  40
  41 typedef address_word sim_cia;
  42
  43 #include "sim-base.h"
  44
  45
  46 /* Deprecated macros and types for manipulating 64bit values.  Use
  47    ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
  48
  49 typedef signed64 word64;
  50 typedef unsigned64 uword64;
  51
  52 #define WORD64LO(t)     (unsigned int)((t)&0xFFFFFFFF)
  53 #define WORD64HI(t)     (unsigned int)(((uword64)(t))>>32)
  54 #define SET64LO(t)      (((uword64)(t))&0xFFFFFFFF)
  55 #define SET64HI(t)      (((uword64)(t))<<32)
  56 #define WORD64(h,l)     ((word64)((SET64HI(h)|SET64LO(l))))
  57 #define UWORD64(h,l)     (SET64HI(h)|SET64LO(l))
  58
  59 /* Check if a value will fit within a halfword: */
  60 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
  61
  62
  63
  64 /* Floating-point operations: */
  65
  66 #include "sim-fpu.h"
  67
  68 /* FPU registers must be one of the following types. All other values
  69    are reserved (and undefined). */
  70 typedef enum {
  71  fmt_single  = 0,
  72  fmt_double  = 1,
  73  fmt_word    = 4,
  74  fmt_long    = 5,
  75  /* The following are well outside the normal acceptable format
  76     range, and are used in the register status vector. */
  77  fmt_unknown       = 0x10000000,
  78  fmt_uninterpreted = 0x20000000,
  79  fmt_uninterpreted_32 = 0x40000000,
  80  fmt_uninterpreted_64 = 0x80000000U,
  81 } FP_formats;
  82
  83 unsigned64 value_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats));
  84 #define ValueFPR(FPR,FMT) value_fpr (SD, CPU, cia, (FPR), (FMT))
  85
  86 void store_fpr PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int fpr, FP_formats fmt, unsigned64 value));
  87 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SD, CPU, cia, (FPR), (FMT), (VALUE))
  88
  89 int NaN PARAMS ((unsigned64 op, FP_formats fmt));
  90 int Infinity PARAMS ((unsigned64 op, FP_formats fmt));
  91 int Less PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  92 int Equal PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  93 unsigned64 AbsoluteValue PARAMS ((unsigned64 op, FP_formats fmt));
  94 unsigned64 Negate PARAMS ((unsigned64 op, FP_formats fmt));
  95 unsigned64 Add PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  96 unsigned64 Sub PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  97 unsigned64 Multiply PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  98 unsigned64 Divide PARAMS ((unsigned64 op1, unsigned64 op2, FP_formats fmt));
  99 unsigned64 Recip PARAMS ((unsigned64 op, FP_formats fmt));
 100 unsigned64 SquareRoot PARAMS ((unsigned64 op, FP_formats fmt));
 101 unsigned64 convert PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int rm, unsigned64 op, FP_formats from, FP_formats to));
 102 #define Convert(rm,op,from,to) \
 103 convert (SD, CPU, cia, rm, op, from, to)
 104
 105 /* Macro to update FPSR condition-code field. This is complicated by
 106    the fact that there is a hole in the index range of the bits within
 107    the FCSR register. Also, the number of bits visible depends on the
 108    MIPS ISA version being supported. */
 109
 110 #define SETFCC(cc,v) {\
 111   int bit = ((cc == 0) ? 23 : (24 + (cc)));\
 112   FCSR = ((FCSR & ~(1 << bit)) | ((v) << bit));\
 113 }
 114 #define GETFCC(cc) (((((cc) == 0) ? (FCSR & (1 << 23)) : (FCSR & (1 << (24 + (cc))))) != 0) ? 1U : 0)
 115
 116 /* This should be the COC1 value at the start of the preceding
 117    instruction: */
 118 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
 119
 120 #ifdef TARGET_ENABLE_FR
 121 /* FIXME: this should be enabled for all targets, but needs testing first. */
 122 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
 123    ? ((SR & status_FR) ? 64 : 32) \
 124    : (WITH_TARGET_FLOATING_POINT_BITSIZE))
 125 #else
 126 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
 127 #endif
 128
 129 /* Standard FCRS bits: */
 130 #define IR (0) /* Inexact Result */
 131 #define UF (1) /* UnderFlow */
 132 #define OF (2) /* OverFlow */
 133 #define DZ (3) /* Division by Zero */
 134 #define IO (4) /* Invalid Operation */
 135 #define UO (5) /* Unimplemented Operation */
 136
 137 /* Get masks for individual flags: */
 138 #if 1 /* SAFE version */
 139 #define FP_FLAGS(b)  (((unsigned)(b) < 5) ? (1 << ((b) + 2)) : 0)
 140 #define FP_ENABLE(b) (((unsigned)(b) < 5) ? (1 << ((b) + 7)) : 0)
 141 #define FP_CAUSE(b)  (((unsigned)(b) < 6) ? (1 << ((b) + 12)) : 0)
 142 #else
 143 #define FP_FLAGS(b)  (1 << ((b) + 2))
 144 #define FP_ENABLE(b) (1 << ((b) + 7))
 145 #define FP_CAUSE(b)  (1 << ((b) + 12))
 146 #endif
 147
 148 #define FP_FS         (1 << 24) /* MIPS III onwards : Flush to Zero */
 149
 150 #define FP_MASK_RM    (0x3)
 151 #define FP_SH_RM      (0)
 152 #define FP_RM_NEAREST (0) /* Round to nearest        (Round) */
 153 #define FP_RM_TOZERO  (1) /* Round to zero           (Trunc) */
 154 #define FP_RM_TOPINF  (2) /* Round to Plus infinity  (Ceil) */
 155 #define FP_RM_TOMINF  (3) /* Round to Minus infinity (Floor) */
 156 #define GETRM()       (int)((FCSR >> FP_SH_RM) & FP_MASK_RM)
 157
 158
 159
 160
 161
 162
 163 /* HI/LO register accesses */
 164
 165 /* For some MIPS targets, the HI/LO registers have certain timing
 166    restrictions in that, for instance, a read of a HI register must be
 167    separated by at least three instructions from a preceeding read.
 168
 169    The struct below is used to record the last access by each of A MT,
 170    MF or other OP instruction to a HI/LO register.  See mips.igen for
 171    more details. */
 172
 173 typedef struct _hilo_access {
 174   signed64 timestamp;
 175   address_word cia;
 176 } hilo_access;
 177
 178 typedef struct _hilo_history {
 179   hilo_access mt;
 180   hilo_access mf;
 181   hilo_access op;
 182 } hilo_history;
 183
 184
 185
 186
 187 /* Integer ALU operations: */
 188
 189 #include "sim-alu.h"
 190
 191 #define ALU32_END(ANS) \
 192   if (ALU32_HAD_OVERFLOW) \
 193     SignalExceptionIntegerOverflow (); \
 194   (ANS) = (signed32) ALU32_OVERFLOW_RESULT
 195
 196
 197 #define ALU64_END(ANS) \
 198   if (ALU64_HAD_OVERFLOW) \
 199     SignalExceptionIntegerOverflow (); \
 200   (ANS) = ALU64_OVERFLOW_RESULT;
 201
 202
 203
 204
 205
 206 /* The following is probably not used for MIPS IV onwards: */
 207 /* Slots for delayed register updates. For the moment we just have a
 208    fixed number of slots (rather than a more generic, dynamic
 209    system). This keeps the simulator fast. However, we only allow
 210    for the register update to be delayed for a single instruction
 211    cycle. */
 212 #define PSLOTS (8) /* Maximum number of instruction cycles */
 213
 214 typedef struct _pending_write_queue {
 215   int in;
 216   int out;
 217   int total;
 218   int slot_delay[PSLOTS];
 219   int slot_size[PSLOTS];
 220   int slot_bit[PSLOTS];
 221   void *slot_dest[PSLOTS];
 222   unsigned64 slot_value[PSLOTS];
 223 } pending_write_queue;
 224
 225 #ifndef PENDING_TRACE
 226 #define PENDING_TRACE 0
 227 #endif
 228 #define PENDING_IN ((CPU)->pending.in)
 229 #define PENDING_OUT ((CPU)->pending.out)
 230 #define PENDING_TOTAL ((CPU)->pending.total)
 231 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
 232 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
 233 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
 234 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
 235 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
 236
 237 /* Invalidate the pending write queue, all pending writes are
 238    discarded. */
 239
 240 #define PENDING_INVALIDATE() \
 241 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
 242
 243 /* Schedule a write to DEST for N cycles time.  For 64 bit
 244    destinations, schedule two writes.  For floating point registers,
 245    the caller should schedule a write to both the dest register and
 246    the FPR_STATE register.  When BIT is non-negative, only BIT of DEST
 247    is updated. */
 248
 249 #define PENDING_SCHED(DEST,VAL,DELAY,BIT)                               \
 250   do {                                                                  \
 251     if (PENDING_SLOT_DEST[PENDING_IN] != NULL)                          \
 252       sim_engine_abort (SD, CPU, cia,                                   \
 253                         "PENDING_SCHED - buffer overflow\n");           \
 254     if (PENDING_TRACE)                                                  \
 255       sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n",                  \
 256                       (unsigned long) cia, (unsigned long) &(DEST),     \
 257                       (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
 258                       PENDING_IN, PENDING_OUT, PENDING_TOTAL);          \
 259     PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1;                       \
 260     PENDING_SLOT_DEST[PENDING_IN] = &(DEST);                            \
 261     PENDING_SLOT_VALUE[PENDING_IN] = (VAL);                             \
 262     PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST);                      \
 263     PENDING_SLOT_BIT[PENDING_IN] = (BIT);                               \
 264     PENDING_IN = (PENDING_IN + 1) % PSLOTS;                             \
 265     PENDING_TOTAL += 1;                                                 \
 266   } while (0)
 267
 268 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
 269 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
 270
 271 #define PENDING_TICK() pending_tick (SD, CPU, cia)
 272
 273 #define PENDING_FLUSH() abort () /* think about this one */
 274 #define PENDING_FP() abort () /* think about this one */
 275
 276 /* For backward compatibility */
 277 #define PENDING_FILL(R,VAL)                                             \
 278 do {                                                                    \
 279   if ((R) >= FGRIDX && (R) < FGRIDX + NR_FGR)                           \
 280     {                                                                   \
 281       PENDING_SCHED(FGR[(R) - FGRIDX], VAL, 1, -1);                     \
 282       PENDING_SCHED(FPR_STATE[(R) - FGRIDX], fmt_uninterpreted, 1, -1); \
 283     }                                                                   \
 284   else                                                                  \
 285     PENDING_SCHED(GPR[(R)], VAL, 1, -1);                                \
 286 } while (0)
 287
 288
 289 enum float_operation
 290   {
 291     FLOP_ADD,    FLOP_SUB,    FLOP_MUL,    FLOP_MADD,
 292     FLOP_MSUB,   FLOP_MAX=10, FLOP_MIN,    FLOP_ABS,
 293     FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
 294   };
 295
 296
 297 /* The internal representation of an MDMX accumulator.
 298    Note that 24 and 48 bit accumulator elements are represented in
 299    32 or 64 bits.  Since the accumulators are 2's complement with
 300    overflow suppressed, high-order bits can be ignored in most contexts.  */
 301
 302 typedef signed32 signed24;
 303 typedef signed64 signed48;
 304
 305 typedef union {
 306   signed24  ob[8];
 307   signed48  qh[4];
 308 } MDMX_accumulator;
 309
 310
 311 /* Conventional system arguments.  */
 312 #define SIM_STATE  sim_cpu *cpu, address_word cia
 313 #define SIM_ARGS   CPU, cia
 314
 315 struct _sim_cpu {
 316
 317
 318   /* The following are internal simulator state variables: */
 319 #define CIA_GET(CPU) ((CPU)->registers[PCIDX] + 0)
 320 #define CIA_SET(CPU,CIA) ((CPU)->registers[PCIDX] = (CIA))
 321   address_word dspc;  /* delay-slot PC */
 322 #define DSPC ((CPU)->dspc)
 323
 324 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
 325 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
 326
 327
 328   /* State of the simulator */
 329   unsigned int state;
 330   unsigned int dsstate;
 331 #define STATE ((CPU)->state)
 332 #define DSSTATE ((CPU)->dsstate)
 333
 334 /* Flags in the "state" variable: */
 335 #define simHALTEX       (1 << 2)  /* 0 = run; 1 = halt on exception */
 336 #define simHALTIN       (1 << 3)  /* 0 = run; 1 = halt on interrupt */
 337 #define simTRACE        (1 << 8)  /* 0 = do nothing; 1 = trace address activity */
 338 #define simPCOC0        (1 << 17) /* COC[1] from current */
 339 #define simPCOC1        (1 << 18) /* COC[1] from previous */
 340 #define simDELAYSLOT    (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
 341 #define simSKIPNEXT     (1 << 25) /* 0 = do nothing; 1 = skip instruction */
 342 #define simSIGINT       (1 << 28)  /* 0 = do nothing; 1 = SIGINT has occured */
 343 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
 344
 345 #ifndef ENGINE_ISSUE_PREFIX_HOOK
 346 #define ENGINE_ISSUE_PREFIX_HOOK() \
 347   { \
 348     /* Perform any pending writes */ \
 349     PENDING_TICK(); \
 350     /* Set previous flag, depending on current: */ \
 351     if (STATE & simPCOC0) \
 352      STATE |= simPCOC1; \
 353     else \
 354      STATE &= ~simPCOC1; \
 355     /* and update the current value: */ \
 356     if (GETFCC(0)) \
 357      STATE |= simPCOC0; \
 358     else \
 359      STATE &= ~simPCOC0; \
 360   }
 361 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
 362
 363
 364 /* This is nasty, since we have to rely on matching the register
 365    numbers used by GDB. Unfortunately, depending on the MIPS target
 366    GDB uses different register numbers. We cannot just include the
 367    relevant "gdb/tm.h" link, since GDB may not be configured before
 368    the sim world, and also the GDB header file requires too much other
 369    state. */
 370
 371 #ifndef TM_MIPS_H
 372 #define LAST_EMBED_REGNUM (89)
 373 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
 374
 375
 376 #endif
 377
 378
 379 /* To keep this default simulator simple, and fast, we use a direct
 380    vector of registers. The internal simulator engine then uses
 381    manifests to access the correct slot. */
 382
 383   unsigned_word registers[LAST_EMBED_REGNUM + 1];
 384
 385   int register_widths[NUM_REGS];
 386 #define REGISTERS       ((CPU)->registers)
 387
 388 #define GPR     (&REGISTERS[0])
 389 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
 390
 391   /* While space is allocated for the floating point registers in the
 392      main registers array, they are stored separatly.  This is because
 393      their size may not necessarily match the size of either the
 394      general-purpose or system specific registers */
 395 #define NR_FGR  (32)
 396 #define FGRIDX  (38)
 397   fp_word fgr[NR_FGR];
 398 #define FGR     ((CPU)->fgr)
 399
 400 #define LO      (REGISTERS[33])
 401 #define HI      (REGISTERS[34])
 402 #define PCIDX   37
 403 #define PC      (REGISTERS[PCIDX])
 404 #define CAUSE   (REGISTERS[36])
 405 #define SRIDX   (32)
 406 #define SR      (REGISTERS[SRIDX])      /* CPU status register */
 407 #define FCR0IDX  (71)
 408 #define FCR0    (REGISTERS[FCR0IDX])    /* really a 32bit register */
 409 #define FCR31IDX (70)
 410 #define FCR31   (REGISTERS[FCR31IDX])   /* really a 32bit register */
 411 #define FCSR    (FCR31)
 412 #define Debug   (REGISTERS[86])
 413 #define DEPC    (REGISTERS[87])
 414 #define EPC     (REGISTERS[88])
 415
 416   /* All internal state modified by signal_exception() that may need to be
 417      rolled back for passing moment-of-exception image back to gdb. */
 418   unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
 419   unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
 420   int exc_suspended;
 421
 422 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
 423 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
 424 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
 425
 426   unsigned_word c0_config_reg;
 427 #define C0_CONFIG ((CPU)->c0_config_reg)
 428
 429 /* The following are pseudonyms for standard registers */
 430 #define ZERO    (REGISTERS[0])
 431 #define V0      (REGISTERS[2])
 432 #define A0      (REGISTERS[4])
 433 #define A1      (REGISTERS[5])
 434 #define A2      (REGISTERS[6])
 435 #define A3      (REGISTERS[7])
 436 #define T8IDX   24
 437 #define T8      (REGISTERS[T8IDX])
 438 #define SPIDX   29
 439 #define SP      (REGISTERS[SPIDX])
 440 #define RAIDX   31
 441 #define RA      (REGISTERS[RAIDX])
 442
 443   /* While space is allocated in the main registers arrray for some of
 444      the COP0 registers, that space isn't sufficient.  Unknown COP0
 445      registers overflow into the array below */
 446
 447 #define NR_COP0_GPR     32
 448   unsigned_word cop0_gpr[NR_COP0_GPR];
 449 #define COP0_GPR        ((CPU)->cop0_gpr)
 450 #define COP0_BADVADDR ((unsigned32)(COP0_GPR[8]))
 451
 452   /* Keep the current format state for each register: */
 453   FP_formats fpr_state[32];
 454 #define FPR_STATE ((CPU)->fpr_state)
 455
 456   pending_write_queue pending;
 457
 458   /* The MDMX accumulator (used only for MDMX ASE).  */
 459   MDMX_accumulator acc;
 460 #define ACC             ((CPU)->acc)
 461
 462   /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
 463      read-write instructions. It is set when a linked load occurs. It
 464      is tested and cleared by the conditional store. It is cleared
 465      (during other CPU operations) when a store to the location would
 466      no longer be atomic. In particular, it is cleared by exception
 467      return instructions. */
 468   int llbit;
 469 #define LLBIT ((CPU)->llbit)
 470
 471
 472 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
 473    corruptions caused by using the HI or LO register too close to a
 474    following operation is spotted. See mips.igen for more details. */
 475
 476   hilo_history hi_history;
 477 #define HIHISTORY (&(CPU)->hi_history)
 478   hilo_history lo_history;
 479 #define LOHISTORY (&(CPU)->lo_history)
 480
 481 #define check_branch_bug()
 482 #define mark_branch_bug(TARGET)
 483
 484
 485
 486   sim_cpu_base base;
 487 };
 488
 489
 490 /* MIPS specific simulator watch config */
 491
 492 void watch_options_install PARAMS ((SIM_DESC sd));
 493
 494 struct swatch {
 495   sim_event *pc;
 496   sim_event *clock;
 497   sim_event *cycles;
 498 };
 499
 500
 501 /* FIXME: At present much of the simulator is still static */
 502 struct sim_state {
 503
 504   struct swatch watch;
 505
 506   sim_cpu cpu[MAX_NR_PROCESSORS];
 507 #if (WITH_SMP)
 508 #define STATE_CPU(sd,n) (&(sd)->cpu[n])
 509 #else
 510 #define STATE_CPU(sd,n) (&(sd)->cpu[0])
 511 #endif
 512
 513
 514   sim_state_base base;
 515 };
 516
 517
 518
 519 /* Status information: */
 520
 521 /* TODO : these should be the bitmasks for these bits within the
 522    status register. At the moment the following are VR4300
 523    bit-positions: */
 524 #define status_KSU_mask  (0x18)         /* mask for KSU bits */
 525 #define status_KSU_shift (3)            /* shift for field */
 526 #define ksu_kernel       (0x0)
 527 #define ksu_supervisor   (0x1)
 528 #define ksu_user         (0x2)
 529 #define ksu_unknown      (0x3)
 530
 531 #define SR_KSU           ((SR & status_KSU_mask) >> status_KSU_shift)
 532
 533 #define status_IE        (1 <<  0)      /* Interrupt enable */
 534 #define status_EIE       (1 << 16)      /* Enable Interrupt Enable */
 535 #define status_EXL       (1 <<  1)      /* Exception level */
 536 #define status_RE        (1 << 25)      /* Reverse Endian in user mode */
 537 #define status_FR        (1 << 26)      /* enables MIPS III additional FP registers */
 538 #define status_SR        (1 << 20)      /* soft reset or NMI */
 539 #define status_BEV       (1 << 22)      /* Location of general exception vectors */
 540 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 541 #define status_ERL       (1 <<  2)      /* Error level */
 542 #define status_IM7       (1 << 15)      /* Timer Interrupt Mask */
 543 #define status_RP        (1 << 27)      /* Reduced Power mode */
 544
 545 /* Specializations for TX39 family */
 546 #define status_IEc       (1 << 0)       /* Interrupt enable (current) */
 547 #define status_KUc       (1 << 1)       /* Kernel/User mode */
 548 #define status_IEp       (1 << 2)       /* Interrupt enable (previous) */
 549 #define status_KUp       (1 << 3)       /* Kernel/User mode */
 550 #define status_IEo       (1 << 4)       /* Interrupt enable (old) */
 551 #define status_KUo       (1 << 5)       /* Kernel/User mode */
 552 #define status_IM_mask   (0xff)         /* Interrupt mask */
 553 #define status_IM_shift  (8)
 554 #define status_NMI       (1 << 20)      /* NMI */
 555 #define status_NMI       (1 << 20)      /* NMI */
 556
 557 /* Status bits used by MIPS32/MIPS64.  */
 558 #define status_UX        (1 <<  5)      /* 64-bit user addrs */
 559 #define status_SX        (1 <<  6)      /* 64-bit supervisor addrs */
 560 #define status_KX        (1 <<  7)      /* 64-bit kernel addrs */
 561 #define status_TS        (1 << 21)      /* TLB shutdown has occurred */
 562 #define status_PX        (1 << 23)      /* Enable 64 bit operations */
 563 #define status_MX        (1 << 24)      /* Enable MDMX resources */
 564 #define status_CU0       (1 << 28)      /* Coprocessor 0 usable */
 565 #define status_CU1       (1 << 29)      /* Coprocessor 1 usable */
 566 #define status_CU2       (1 << 30)      /* Coprocessor 2 usable */
 567 #define status_CU3       (1 << 31)      /* Coprocessor 3 usable */
 568 /* Bits reserved for implementations:  */
 569 #define status_SBX       (1 << 16)      /* Enable SiByte SB-1 extensions.  */
 570
 571 #define cause_BD ((unsigned)1 << 31)    /* L1 Exception in branch delay slot */
 572 #define cause_BD2         (1 << 30)     /* L2 Exception in branch delay slot */
 573 #define cause_CE_mask     0x30000000    /* Coprocessor exception */
 574 #define cause_CE_shift    28
 575 #define cause_EXC2_mask   0x00070000
 576 #define cause_EXC2_shift  16
 577 #define cause_IP7         (1 << 15)     /* Interrupt pending */
 578 #define cause_SIOP        (1 << 12)     /* SIO pending */
 579 #define cause_IP3         (1 << 11)     /* Int 0 pending */
 580 #define cause_IP2         (1 << 10)     /* Int 1 pending */
 581
 582 #define cause_EXC_mask  (0x1c)          /* Exception code */
 583 #define cause_EXC_shift (2)
 584
 585 #define cause_SW0       (1 << 8)        /* Software interrupt 0 */
 586 #define cause_SW1       (1 << 9)        /* Software interrupt 1 */
 587 #define cause_IP_mask   (0x3f)          /* Interrupt pending field */
 588 #define cause_IP_shift  (10)
 589
 590 #define cause_set_EXC(x)  CAUSE = (CAUSE & ~cause_EXC_mask)  | ((x << cause_EXC_shift)  & cause_EXC_mask)
 591 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
 592
 593
 594 /* NOTE: We keep the following status flags as bit values (1 for true,
 595    0 for false). This allows them to be used in binary boolean
 596    operations without worrying about what exactly the non-zero true
 597    value is. */
 598
 599 /* UserMode */
 600 #ifdef SUBTARGET_R3900
 601 #define UserMode        ((SR & status_KUc) ? 1 : 0)
 602 #else
 603 #define UserMode        ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
 604 #endif /* SUBTARGET_R3900 */
 605
 606 /* BigEndianMem */
 607 /* Hardware configuration. Affects endianness of LoadMemory and
 608    StoreMemory and the endianness of Kernel and Supervisor mode
 609    execution. The value is 0 for little-endian; 1 for big-endian. */
 610 #define BigEndianMem    (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
 611 /*(state & simBE) ? 1 : 0)*/
 612
 613 /* ReverseEndian */
 614 /* This mode is selected if in User mode with the RE bit being set in
 615    SR (Status Register). It reverses the endianness of load and store
 616    instructions. */
 617 #define ReverseEndian   (((SR & status_RE) && UserMode) ? 1 : 0)
 618
 619 /* BigEndianCPU */
 620 /* The endianness for load and store instructions (0=little;1=big). In
 621    User mode this endianness may be switched by setting the state_RE
 622    bit in the SR register. Thus, BigEndianCPU may be computed as
 623    (BigEndianMem EOR ReverseEndian). */
 624 #define BigEndianCPU    (BigEndianMem ^ ReverseEndian) /* Already bits */
 625
 626
 627
 628 /* Exceptions: */
 629
 630 /* NOTE: These numbers depend on the processor architecture being
 631    simulated: */
 632 enum ExceptionCause {
 633   Interrupt               = 0,
 634   TLBModification         = 1,
 635   TLBLoad                 = 2,
 636   TLBStore                = 3,
 637   AddressLoad             = 4,
 638   AddressStore            = 5,
 639   InstructionFetch        = 6,
 640   DataReference           = 7,
 641   SystemCall              = 8,
 642   BreakPoint              = 9,
 643   ReservedInstruction     = 10,
 644   CoProcessorUnusable     = 11,
 645   IntegerOverflow         = 12,    /* Arithmetic overflow (IDT monitor raises SIGFPE) */
 646   Trap                    = 13,
 647   FPE                     = 15,
 648   DebugBreakPoint         = 16,    /* Impl. dep. in MIPS32/MIPS64.  */
 649   MDMX                    = 22,
 650   Watch                   = 23,
 651   MCheck                  = 24,
 652   CacheErr                = 30,
 653   NMIReset                = 31,    /* Reserved in MIPS32/MIPS64.  */
 654
 655
 656 /* The following exception code is actually private to the simulator
 657    world. It is *NOT* a processor feature, and is used to signal
 658    run-time errors in the simulator. */
 659   SimulatorFault          = 0xFFFFFFFF
 660 };
 661
 662 #define TLB_REFILL  (0)
 663 #define TLB_INVALID (1)
 664
 665
 666 /* The following break instructions are reserved for use by the
 667    simulator.  The first is used to halt the simulation.  The second
 668    is used by gdb for break-points.  NOTE: Care must be taken, since
 669    this value may be used in later revisions of the MIPS ISA. */
 670 #define HALT_INSTRUCTION_MASK   (0x03FFFFC0)
 671
 672 #define HALT_INSTRUCTION        (0x03ff000d)
 673 #define HALT_INSTRUCTION2       (0x0000ffcd)
 674
 675
 676 #define BREAKPOINT_INSTRUCTION  (0x0005000d)
 677 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
 678
 679
 680
 681 void interrupt_event (SIM_DESC sd, void *data);
 682
 683 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
 684 #define SignalException(exc,instruction)     signal_exception (SD, CPU, cia, (exc), (instruction))
 685 #define SignalExceptionInterrupt(level)      signal_exception (SD, CPU, cia, Interrupt, level)
 686 #define SignalExceptionInstructionFetch()    signal_exception (SD, CPU, cia, InstructionFetch)
 687 #define SignalExceptionAddressStore()        signal_exception (SD, CPU, cia, AddressStore)
 688 #define SignalExceptionAddressLoad()         signal_exception (SD, CPU, cia, AddressLoad)
 689 #define SignalExceptionDataReference()       signal_exception (SD, CPU, cia, DataReference)
 690 #define SignalExceptionSimulatorFault(buf)   signal_exception (SD, CPU, cia, SimulatorFault, buf)
 691 #define SignalExceptionFPE()                 signal_exception (SD, CPU, cia, FPE)
 692 #define SignalExceptionIntegerOverflow()     signal_exception (SD, CPU, cia, IntegerOverflow)
 693 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
 694 #define SignalExceptionNMIReset()            signal_exception (SD, CPU, cia, NMIReset)
 695 #define SignalExceptionTLBRefillStore()      signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
 696 #define SignalExceptionTLBRefillLoad()       signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
 697 #define SignalExceptionTLBInvalidStore()     signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
 698 #define SignalExceptionTLBInvalidLoad()      signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
 699 #define SignalExceptionTLBModification()     signal_exception (SD, CPU, cia, TLBModification)
 700 #define SignalExceptionMDMX()                signal_exception (SD, CPU, cia, MDMX)
 701 #define SignalExceptionWatch()               signal_exception (SD, CPU, cia, Watch)
 702 #define SignalExceptionMCheck()              signal_exception (SD, CPU, cia, MCheck)
 703 #define SignalExceptionCacheErr()            signal_exception (SD, CPU, cia, CacheErr)
 704
 705 /* Co-processor accesses */
 706
 707 /* XXX FIXME: For now, assume that FPU (cp1) is always usable.  */
 708 #define COP_Usable(coproc_num)          (coproc_num == 1)
 709
 710 void cop_lw  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword));
 711 void cop_ld  PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword));
 712 unsigned int cop_sw PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 713 uword64 cop_sd PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg));
 714
 715 #define COP_LW(coproc_num,coproc_reg,memword) \
 716 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
 717 #define COP_LD(coproc_num,coproc_reg,memword) \
 718 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
 719 #define COP_SW(coproc_num,coproc_reg) \
 720 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
 721 #define COP_SD(coproc_num,coproc_reg) \
 722 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
 723
 724
 725 void decode_coproc PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction));
 726 #define DecodeCoproc(instruction) \
 727 decode_coproc (SD, CPU, cia, (instruction))
 728
 729 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
 730
 731
 732 /* MDMX access.  */
 733
 734 typedef unsigned int MX_fmtsel;   /* MDMX format select field (5 bits).  */
 735 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
 736 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
 737
 738 #define fmt_mdmx fmt_uninterpreted
 739
 740 #define MX_VECT_AND  (0)
 741 #define MX_VECT_NOR  (1)
 742 #define MX_VECT_OR   (2)
 743 #define MX_VECT_XOR  (3)
 744 #define MX_VECT_SLL  (4)
 745 #define MX_VECT_SRL  (5)
 746 #define MX_VECT_ADD  (6)
 747 #define MX_VECT_SUB  (7)
 748 #define MX_VECT_MIN  (8)
 749 #define MX_VECT_MAX  (9)
 750 #define MX_VECT_MUL  (10)
 751 #define MX_VECT_MSGN (11)
 752 #define MX_VECT_SRA  (12)
 753 #define MX_VECT_ABSD (13)               /* SB-1 only.  */
 754 #define MX_VECT_AVG  (14)               /* SB-1 only.  */
 755
 756 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 757 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
 758 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
 759 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
 760 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
 761 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
 762 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
 763 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
 764 #define MX_Or(op1,vt,fmtsel)  mdmx_cpr_op(SIM_ARGS, MX_VECT_OR,  op1, vt, fmtsel)
 765 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
 766 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
 767 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
 768 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
 769 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
 770 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
 771 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
 772
 773 #define MX_C_EQ  0x1
 774 #define MX_C_LT  0x4
 775
 776 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 777 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
 778
 779 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 780 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
 781
 782 #define MX_VECT_ADDA  (0)
 783 #define MX_VECT_ADDL  (1)
 784 #define MX_VECT_MULA  (2)
 785 #define MX_VECT_MULL  (3)
 786 #define MX_VECT_MULS  (4)
 787 #define MX_VECT_MULSL (5)
 788 #define MX_VECT_SUBA  (6)
 789 #define MX_VECT_SUBL  (7)
 790 #define MX_VECT_ABSDA (8)               /* SB-1 only.  */
 791
 792 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
 793 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
 794 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
 795 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
 796 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
 797 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
 798 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
 799 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
 800 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
 801 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
 802
 803 #define MX_FMT_OB   (0)
 804 #define MX_FMT_QH   (1)
 805
 806 /* The following codes chosen to indicate the units of shift.  */
 807 #define MX_RAC_L    (0)
 808 #define MX_RAC_M    (1)
 809 #define MX_RAC_H    (2)
 810
 811 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
 812 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
 813
 814 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
 815 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
 816 void mdmx_wach (SIM_STATE, int, unsigned64);
 817 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
 818
 819 #define MX_RND_AS   (0)
 820 #define MX_RND_AU   (1)
 821 #define MX_RND_ES   (2)
 822 #define MX_RND_EU   (3)
 823 #define MX_RND_ZS   (4)
 824 #define MX_RND_ZU   (5)
 825
 826 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
 827 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
 828 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
 829 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
 830 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
 831 #define MX_RZS(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
 832 #define MX_RZU(vt,fmt)  mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
 833
 834 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
 835 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
 836
 837
 838
 839 /* Memory accesses */
 840
 841 /* The following are generic to all versions of the MIPS architecture
 842    to date: */
 843
 844 /* Memory Access Types (for CCA): */
 845 #define Uncached                (0)
 846 #define CachedNoncoherent       (1)
 847 #define CachedCoherent          (2)
 848 #define Cached                  (3)
 849
 850 #define isINSTRUCTION   (1 == 0) /* FALSE */
 851 #define isDATA          (1 == 1) /* TRUE */
 852 #define isLOAD          (1 == 0) /* FALSE */
 853 #define isSTORE         (1 == 1) /* TRUE */
 854 #define isREAL          (1 == 0) /* FALSE */
 855 #define isRAW           (1 == 1) /* TRUE */
 856 /* The parameter HOST (isTARGET / isHOST) is ignored */
 857 #define isTARGET        (1 == 0) /* FALSE */
 858 /* #define isHOST          (1 == 1) TRUE */
 859
 860 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
 861    is the number of bytes minus 1. */
 862 #define AccessLength_BYTE       (0)
 863 #define AccessLength_HALFWORD   (1)
 864 #define AccessLength_TRIPLEBYTE (2)
 865 #define AccessLength_WORD       (3)
 866 #define AccessLength_QUINTIBYTE (4)
 867 #define AccessLength_SEXTIBYTE  (5)
 868 #define AccessLength_SEPTIBYTE  (6)
 869 #define AccessLength_DOUBLEWORD (7)
 870 #define AccessLength_QUADWORD   (15)
 871
 872 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
 873                     ? AccessLength_DOUBLEWORD /*7*/ \
 874                     : AccessLength_WORD /*3*/)
 875 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
 876
 877
 878 INLINE_SIM_MAIN (int) address_translation PARAMS ((SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw));
 879 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
 880 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
 881
 882 INLINE_SIM_MAIN (void) load_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD));
 883 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
 884 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
 885
 886 INLINE_SIM_MAIN (void) store_memory PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr));
 887 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
 888 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
 889
 890 INLINE_SIM_MAIN (void) cache_op PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction));
 891 #define CacheOp(op,pAddr,vAddr,instruction) \
 892 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
 893
 894 INLINE_SIM_MAIN (void) sync_operation PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype));
 895 #define SyncOperation(stype) \
 896 sync_operation (SD, CPU, cia, (stype))
 897
 898 INLINE_SIM_MAIN (void) prefetch PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint));
 899 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
 900 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
 901
 902 void unpredictable_action (sim_cpu *cpu, address_word cia);
 903 #define NotWordValue(val)       not_word_value (SD_, (val))
 904 #define Unpredictable()         unpredictable (SD_)
 905 #define UnpredictableResult()   /* For now, do nothing.  */
 906
 907 INLINE_SIM_MAIN (unsigned32) ifetch32 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 908 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
 909 INLINE_SIM_MAIN (unsigned16) ifetch16 PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr));
 910 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
 911 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
 912
 913 void dotrace PARAMS ((SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...));
 914 extern FILE *tracefh;
 915
 916 INLINE_SIM_MAIN (void) pending_tick PARAMS ((SIM_DESC sd, sim_cpu *cpu, address_word cia));
 917 extern SIM_CORE_SIGNAL_FN mips_core_signal;
 918
 919 char* pr_addr PARAMS ((SIM_ADDR addr));
 920 char* pr_uword64 PARAMS ((uword64 addr));
 921
 922
 923 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
 924
 925 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 926 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 927 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 928
 929
 930 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
 931 #include "sim-main.c"
 932 #endif
 933
 934 #endif