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sim: unify SIM_CPU definition
[binutils-gdb.git] / sim / mips / sim-main.h
1 /* MIPS Simulator definition.
2 Copyright (C) 1997-2015 Free Software Foundation, Inc.
3 Contributed by Cygnus Support.
4
5 This file is part of GDB, the GNU debugger.
6
7 This program is free software; you can redistribute it and/or modify
8 it under the terms of the GNU General Public License as published by
9 the Free Software Foundation; either version 3 of the License, or
10 (at your option) any later version.
11
12 This program is distributed in the hope that it will be useful,
13 but WITHOUT ANY WARRANTY; without even the implied warranty of
14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 GNU General Public License for more details.
16
17 You should have received a copy of the GNU General Public License
18 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19
20 #ifndef SIM_MAIN_H
21 #define SIM_MAIN_H
22
23 /* This simulator doesn't cache the Current Instruction Address */
24 /* #define SIM_ENGINE_HALT_HOOK(SD, LAST_CPU, CIA) */
25 /* #define SIM_ENGINE_RESUME_HOOK(SD, LAST_CPU, CIA) */
26
27 /* hobble some common features for moment */
28 #define WITH_WATCHPOINTS 1
29 #define WITH_MODULO_MEMORY 1
30
31
32 #define SIM_CORE_SIGNAL(SD,CPU,CIA,MAP,NR_BYTES,ADDR,TRANSFER,ERROR) \
33 mips_core_signal ((SD), (CPU), (CIA), (MAP), (NR_BYTES), (ADDR), (TRANSFER), (ERROR))
34
35 #include "sim-basics.h"
36 #include "sim-base.h"
37 #include "bfd.h"
38
39 /* Deprecated macros and types for manipulating 64bit values. Use
40 ../common/sim-bits.h and ../common/sim-endian.h macros instead. */
41
42 typedef signed64 word64;
43 typedef unsigned64 uword64;
44
45 #define WORD64LO(t) (unsigned int)((t)&0xFFFFFFFF)
46 #define WORD64HI(t) (unsigned int)(((uword64)(t))>>32)
47 #define SET64LO(t) (((uword64)(t))&0xFFFFFFFF)
48 #define SET64HI(t) (((uword64)(t))<<32)
49 #define WORD64(h,l) ((word64)((SET64HI(h)|SET64LO(l))))
50 #define UWORD64(h,l) (SET64HI(h)|SET64LO(l))
51
52 /* Check if a value will fit within a halfword: */
53 #define NOTHALFWORDVALUE(v) ((((((uword64)(v)>>16) == 0) && !((v) & ((unsigned)1 << 15))) || (((((uword64)(v)>>32) == 0xFFFFFFFF) && ((((uword64)(v)>>16) & 0xFFFF) == 0xFFFF)) && ((v) & ((unsigned)1 << 15)))) ? (1 == 0) : (1 == 1))
54
55
56
57 /* Floating-point operations: */
58
59 #include "sim-fpu.h"
60 #include "cp1.h"
61
62 /* FPU registers must be one of the following types. All other values
63 are reserved (and undefined). */
64 typedef enum {
65 fmt_single = 0,
66 fmt_double = 1,
67 fmt_word = 4,
68 fmt_long = 5,
69 fmt_ps = 6,
70 /* The following are well outside the normal acceptable format
71 range, and are used in the register status vector. */
72 fmt_unknown = 0x10000000,
73 fmt_uninterpreted = 0x20000000,
74 fmt_uninterpreted_32 = 0x40000000,
75 fmt_uninterpreted_64 = 0x80000000U,
76 } FP_formats;
77
78 /* For paired word (pw) operations, the opcode representation is fmt_word,
79 but register transfers (StoreFPR, ValueFPR, etc.) are done as fmt_long. */
80 #define fmt_pw fmt_long
81
82 /* This should be the COC1 value at the start of the preceding
83 instruction: */
84 #define PREVCOC1() ((STATE & simPCOC1) ? 1 : 0)
85
86 #ifdef TARGET_ENABLE_FR
87 /* FIXME: this should be enabled for all targets, but needs testing first. */
88 #define SizeFGR() (((WITH_TARGET_FLOATING_POINT_BITSIZE) == 64) \
89 ? ((SR & status_FR) ? 64 : 32) \
90 : (WITH_TARGET_FLOATING_POINT_BITSIZE))
91 #else
92 #define SizeFGR() (WITH_TARGET_FLOATING_POINT_BITSIZE)
93 #endif
94
95
96
97
98
99 /* HI/LO register accesses */
100
101 /* For some MIPS targets, the HI/LO registers have certain timing
102 restrictions in that, for instance, a read of a HI register must be
103 separated by at least three instructions from a preceeding read.
104
105 The struct below is used to record the last access by each of A MT,
106 MF or other OP instruction to a HI/LO register. See mips.igen for
107 more details. */
108
109 typedef struct _hilo_access {
110 signed64 timestamp;
111 address_word cia;
112 } hilo_access;
113
114 typedef struct _hilo_history {
115 hilo_access mt;
116 hilo_access mf;
117 hilo_access op;
118 } hilo_history;
119
120
121
122
123 /* Integer ALU operations: */
124
125 #include "sim-alu.h"
126
127 #define ALU32_END(ANS) \
128 if (ALU32_HAD_OVERFLOW) \
129 SignalExceptionIntegerOverflow (); \
130 (ANS) = (signed32) ALU32_OVERFLOW_RESULT
131
132
133 #define ALU64_END(ANS) \
134 if (ALU64_HAD_OVERFLOW) \
135 SignalExceptionIntegerOverflow (); \
136 (ANS) = ALU64_OVERFLOW_RESULT;
137
138
139
140
141
142 /* The following is probably not used for MIPS IV onwards: */
143 /* Slots for delayed register updates. For the moment we just have a
144 fixed number of slots (rather than a more generic, dynamic
145 system). This keeps the simulator fast. However, we only allow
146 for the register update to be delayed for a single instruction
147 cycle. */
148 #define PSLOTS (8) /* Maximum number of instruction cycles */
149
150 typedef struct _pending_write_queue {
151 int in;
152 int out;
153 int total;
154 int slot_delay[PSLOTS];
155 int slot_size[PSLOTS];
156 int slot_bit[PSLOTS];
157 void *slot_dest[PSLOTS];
158 unsigned64 slot_value[PSLOTS];
159 } pending_write_queue;
160
161 #ifndef PENDING_TRACE
162 #define PENDING_TRACE 0
163 #endif
164 #define PENDING_IN ((CPU)->pending.in)
165 #define PENDING_OUT ((CPU)->pending.out)
166 #define PENDING_TOTAL ((CPU)->pending.total)
167 #define PENDING_SLOT_SIZE ((CPU)->pending.slot_size)
168 #define PENDING_SLOT_BIT ((CPU)->pending.slot_bit)
169 #define PENDING_SLOT_DELAY ((CPU)->pending.slot_delay)
170 #define PENDING_SLOT_DEST ((CPU)->pending.slot_dest)
171 #define PENDING_SLOT_VALUE ((CPU)->pending.slot_value)
172
173 /* Invalidate the pending write queue, all pending writes are
174 discarded. */
175
176 #define PENDING_INVALIDATE() \
177 memset (&(CPU)->pending, 0, sizeof ((CPU)->pending))
178
179 /* Schedule a write to DEST for N cycles time. For 64 bit
180 destinations, schedule two writes. For floating point registers,
181 the caller should schedule a write to both the dest register and
182 the FPR_STATE register. When BIT is non-negative, only BIT of DEST
183 is updated. */
184
185 #define PENDING_SCHED(DEST,VAL,DELAY,BIT) \
186 do { \
187 if (PENDING_SLOT_DEST[PENDING_IN] != NULL) \
188 sim_engine_abort (SD, CPU, cia, \
189 "PENDING_SCHED - buffer overflow\n"); \
190 if (PENDING_TRACE) \
191 sim_io_eprintf (SD, "PENDING_SCHED - 0x%lx - dest 0x%lx, val 0x%lx, bit %d, size %d, pending_in %d, pending_out %d, pending_total %d\n", \
192 (unsigned long) cia, (unsigned long) &(DEST), \
193 (unsigned long) (VAL), (BIT), (int) sizeof (DEST),\
194 PENDING_IN, PENDING_OUT, PENDING_TOTAL); \
195 PENDING_SLOT_DELAY[PENDING_IN] = (DELAY) + 1; \
196 PENDING_SLOT_DEST[PENDING_IN] = &(DEST); \
197 PENDING_SLOT_VALUE[PENDING_IN] = (VAL); \
198 PENDING_SLOT_SIZE[PENDING_IN] = sizeof (DEST); \
199 PENDING_SLOT_BIT[PENDING_IN] = (BIT); \
200 PENDING_IN = (PENDING_IN + 1) % PSLOTS; \
201 PENDING_TOTAL += 1; \
202 } while (0)
203
204 #define PENDING_WRITE(DEST,VAL,DELAY) PENDING_SCHED(DEST,VAL,DELAY,-1)
205 #define PENDING_BIT(DEST,VAL,DELAY,BIT) PENDING_SCHED(DEST,VAL,DELAY,BIT)
206
207 #define PENDING_TICK() pending_tick (SD, CPU, cia)
208
209 #define PENDING_FLUSH() abort () /* think about this one */
210 #define PENDING_FP() abort () /* think about this one */
211
212 /* For backward compatibility */
213 #define PENDING_FILL(R,VAL) \
214 do { \
215 if ((R) >= FGR_BASE && (R) < FGR_BASE + NR_FGR) \
216 { \
217 PENDING_SCHED(FGR[(R) - FGR_BASE], VAL, 1, -1); \
218 PENDING_SCHED(FPR_STATE[(R) - FGR_BASE], fmt_uninterpreted, 1, -1); \
219 } \
220 else \
221 PENDING_SCHED(GPR[(R)], VAL, 1, -1); \
222 } while (0)
223
224
225 enum float_operation
226 {
227 FLOP_ADD, FLOP_SUB, FLOP_MUL, FLOP_MADD,
228 FLOP_MSUB, FLOP_MAX=10, FLOP_MIN, FLOP_ABS,
229 FLOP_ITOF0=14, FLOP_FTOI0=18, FLOP_NEG=23
230 };
231
232
233 /* The internal representation of an MDMX accumulator.
234 Note that 24 and 48 bit accumulator elements are represented in
235 32 or 64 bits. Since the accumulators are 2's complement with
236 overflow suppressed, high-order bits can be ignored in most contexts. */
237
238 typedef signed32 signed24;
239 typedef signed64 signed48;
240
241 typedef union {
242 signed24 ob[8];
243 signed48 qh[4];
244 } MDMX_accumulator;
245
246
247 /* Conventional system arguments. */
248 #define SIM_STATE sim_cpu *cpu, address_word cia
249 #define SIM_ARGS CPU, cia
250
251 struct _sim_cpu {
252
253
254 /* The following are internal simulator state variables: */
255 address_word dspc; /* delay-slot PC */
256 #define DSPC ((CPU)->dspc)
257
258 #define DELAY_SLOT(TARGET) NIA = delayslot32 (SD_, (TARGET))
259 #define NULLIFY_NEXT_INSTRUCTION() NIA = nullify_next_insn32 (SD_)
260
261
262 /* State of the simulator */
263 unsigned int state;
264 unsigned int dsstate;
265 #define STATE ((CPU)->state)
266 #define DSSTATE ((CPU)->dsstate)
267
268 /* Flags in the "state" variable: */
269 #define simHALTEX (1 << 2) /* 0 = run; 1 = halt on exception */
270 #define simHALTIN (1 << 3) /* 0 = run; 1 = halt on interrupt */
271 #define simTRACE (1 << 8) /* 0 = do nothing; 1 = trace address activity */
272 #define simPCOC0 (1 << 17) /* COC[1] from current */
273 #define simPCOC1 (1 << 18) /* COC[1] from previous */
274 #define simDELAYSLOT (1 << 24) /* 0 = do nothing; 1 = delay slot entry exists */
275 #define simSKIPNEXT (1 << 25) /* 0 = do nothing; 1 = skip instruction */
276 #define simSIGINT (1 << 28) /* 0 = do nothing; 1 = SIGINT has occured */
277 #define simJALDELAYSLOT (1 << 29) /* 1 = in jal delay slot */
278
279 #ifndef ENGINE_ISSUE_PREFIX_HOOK
280 #define ENGINE_ISSUE_PREFIX_HOOK() \
281 { \
282 /* Perform any pending writes */ \
283 PENDING_TICK(); \
284 /* Set previous flag, depending on current: */ \
285 if (STATE & simPCOC0) \
286 STATE |= simPCOC1; \
287 else \
288 STATE &= ~simPCOC1; \
289 /* and update the current value: */ \
290 if (GETFCC(0)) \
291 STATE |= simPCOC0; \
292 else \
293 STATE &= ~simPCOC0; \
294 }
295 #endif /* ENGINE_ISSUE_PREFIX_HOOK */
296
297
298 /* This is nasty, since we have to rely on matching the register
299 numbers used by GDB. Unfortunately, depending on the MIPS target
300 GDB uses different register numbers. We cannot just include the
301 relevant "gdb/tm.h" link, since GDB may not be configured before
302 the sim world, and also the GDB header file requires too much other
303 state. */
304
305 #ifndef TM_MIPS_H
306 #define LAST_EMBED_REGNUM (96)
307 #define NUM_REGS (LAST_EMBED_REGNUM + 1)
308
309 #define FP0_REGNUM 38 /* Floating point register 0 (single float) */
310 #define FCRCS_REGNUM 70 /* FP control/status */
311 #define FCRIR_REGNUM 71 /* FP implementation/revision */
312 #endif
313
314
315 /* To keep this default simulator simple, and fast, we use a direct
316 vector of registers. The internal simulator engine then uses
317 manifests to access the correct slot. */
318
319 unsigned_word registers[LAST_EMBED_REGNUM + 1];
320
321 int register_widths[NUM_REGS];
322 #define REGISTERS ((CPU)->registers)
323
324 #define GPR (&REGISTERS[0])
325 #define GPR_SET(N,VAL) (REGISTERS[(N)] = (VAL))
326
327 #define LO (REGISTERS[33])
328 #define HI (REGISTERS[34])
329 #define PCIDX 37
330 #define PC (REGISTERS[PCIDX])
331 #define CAUSE (REGISTERS[36])
332 #define SRIDX (32)
333 #define SR (REGISTERS[SRIDX]) /* CPU status register */
334 #define FCR0IDX (71)
335 #define FCR0 (REGISTERS[FCR0IDX]) /* really a 32bit register */
336 #define FCR31IDX (70)
337 #define FCR31 (REGISTERS[FCR31IDX]) /* really a 32bit register */
338 #define FCSR (FCR31)
339 #define Debug (REGISTERS[86])
340 #define DEPC (REGISTERS[87])
341 #define EPC (REGISTERS[88])
342 #define ACX (REGISTERS[89])
343
344 #define AC0LOIDX (33) /* Must be the same register as LO */
345 #define AC0HIIDX (34) /* Must be the same register as HI */
346 #define AC1LOIDX (90)
347 #define AC1HIIDX (91)
348 #define AC2LOIDX (92)
349 #define AC2HIIDX (93)
350 #define AC3LOIDX (94)
351 #define AC3HIIDX (95)
352
353 #define DSPLO(N) (REGISTERS[DSPLO_REGNUM[N]])
354 #define DSPHI(N) (REGISTERS[DSPHI_REGNUM[N]])
355
356 #define DSPCRIDX (96) /* DSP control register */
357 #define DSPCR (REGISTERS[DSPCRIDX])
358
359 #define DSPCR_POS_SHIFT (0)
360 #define DSPCR_POS_MASK (0x3f)
361 #define DSPCR_POS_SMASK (DSPCR_POS_MASK << DSPCR_POS_SHIFT)
362
363 #define DSPCR_SCOUNT_SHIFT (7)
364 #define DSPCR_SCOUNT_MASK (0x3f)
365 #define DSPCR_SCOUNT_SMASK (DSPCR_SCOUNT_MASK << DSPCR_SCOUNT_SHIFT)
366
367 #define DSPCR_CARRY_SHIFT (13)
368 #define DSPCR_CARRY_MASK (1)
369 #define DSPCR_CARRY_SMASK (DSPCR_CARRY_MASK << DSPCR_CARRY_SHIFT)
370 #define DSPCR_CARRY (1 << DSPCR_CARRY_SHIFT)
371
372 #define DSPCR_EFI_SHIFT (14)
373 #define DSPCR_EFI_MASK (1)
374 #define DSPCR_EFI_SMASK (DSPCR_EFI_MASK << DSPCR_EFI_SHIFT)
375 #define DSPCR_EFI (1 << DSPCR_EFI_MASK)
376
377 #define DSPCR_OUFLAG_SHIFT (16)
378 #define DSPCR_OUFLAG_MASK (0xff)
379 #define DSPCR_OUFLAG_SMASK (DSPCR_OUFLAG_MASK << DSPCR_OUFLAG_SHIFT)
380 #define DSPCR_OUFLAG4 (1 << (DSPCR_OUFLAG_SHIFT + 4))
381 #define DSPCR_OUFLAG5 (1 << (DSPCR_OUFLAG_SHIFT + 5))
382 #define DSPCR_OUFLAG6 (1 << (DSPCR_OUFLAG_SHIFT + 6))
383 #define DSPCR_OUFLAG7 (1 << (DSPCR_OUFLAG_SHIFT + 7))
384
385 #define DSPCR_CCOND_SHIFT (24)
386 #define DSPCR_CCOND_MASK (0xf)
387 #define DSPCR_CCOND_SMASK (DSPCR_CCOND_MASK << DSPCR_CCOND_SHIFT)
388
389 /* All internal state modified by signal_exception() that may need to be
390 rolled back for passing moment-of-exception image back to gdb. */
391 unsigned_word exc_trigger_registers[LAST_EMBED_REGNUM + 1];
392 unsigned_word exc_suspend_registers[LAST_EMBED_REGNUM + 1];
393 int exc_suspended;
394
395 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mips_cpu_exception_trigger(SD,CPU,CIA)
396 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mips_cpu_exception_suspend(SD,CPU,EXC)
397 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mips_cpu_exception_resume(SD,CPU,EXC)
398
399 unsigned_word c0_config_reg;
400 #define C0_CONFIG ((CPU)->c0_config_reg)
401
402 /* The following are pseudonyms for standard registers */
403 #define ZERO (REGISTERS[0])
404 #define V0 (REGISTERS[2])
405 #define A0 (REGISTERS[4])
406 #define A1 (REGISTERS[5])
407 #define A2 (REGISTERS[6])
408 #define A3 (REGISTERS[7])
409 #define T8IDX 24
410 #define T8 (REGISTERS[T8IDX])
411 #define SPIDX 29
412 #define SP (REGISTERS[SPIDX])
413 #define RAIDX 31
414 #define RA (REGISTERS[RAIDX])
415
416 /* While space is allocated in the main registers arrray for some of
417 the COP0 registers, that space isn't sufficient. Unknown COP0
418 registers overflow into the array below */
419
420 #define NR_COP0_GPR 32
421 unsigned_word cop0_gpr[NR_COP0_GPR];
422 #define COP0_GPR ((CPU)->cop0_gpr)
423 #define COP0_BADVADDR (COP0_GPR[8])
424
425 /* While space is allocated for the floating point registers in the
426 main registers array, they are stored separatly. This is because
427 their size may not necessarily match the size of either the
428 general-purpose or system specific registers. */
429 #define NR_FGR (32)
430 #define FGR_BASE FP0_REGNUM
431 fp_word fgr[NR_FGR];
432 #define FGR ((CPU)->fgr)
433
434 /* Keep the current format state for each register: */
435 FP_formats fpr_state[32];
436 #define FPR_STATE ((CPU)->fpr_state)
437
438 pending_write_queue pending;
439
440 /* The MDMX accumulator (used only for MDMX ASE). */
441 MDMX_accumulator acc;
442 #define ACC ((CPU)->acc)
443
444 /* LLBIT = Load-Linked bit. A bit of "virtual" state used by atomic
445 read-write instructions. It is set when a linked load occurs. It
446 is tested and cleared by the conditional store. It is cleared
447 (during other CPU operations) when a store to the location would
448 no longer be atomic. In particular, it is cleared by exception
449 return instructions. */
450 int llbit;
451 #define LLBIT ((CPU)->llbit)
452
453
454 /* The HIHISTORY and LOHISTORY timestamps are used to ensure that
455 corruptions caused by using the HI or LO register too close to a
456 following operation is spotted. See mips.igen for more details. */
457
458 hilo_history hi_history;
459 #define HIHISTORY (&(CPU)->hi_history)
460 hilo_history lo_history;
461 #define LOHISTORY (&(CPU)->lo_history)
462
463
464 sim_cpu_base base;
465 };
466
467
468 /* MIPS specific simulator watch config */
469
470 void watch_options_install (SIM_DESC sd);
471
472 struct swatch {
473 sim_event *pc;
474 sim_event *clock;
475 sim_event *cycles;
476 };
477
478
479 /* FIXME: At present much of the simulator is still static */
480 struct sim_state {
481
482 struct swatch watch;
483
484 sim_cpu *cpu[MAX_NR_PROCESSORS];
485
486 sim_state_base base;
487 };
488
489
490
491 /* Status information: */
492
493 /* TODO : these should be the bitmasks for these bits within the
494 status register. At the moment the following are VR4300
495 bit-positions: */
496 #define status_KSU_mask (0x18) /* mask for KSU bits */
497 #define status_KSU_shift (3) /* shift for field */
498 #define ksu_kernel (0x0)
499 #define ksu_supervisor (0x1)
500 #define ksu_user (0x2)
501 #define ksu_unknown (0x3)
502
503 #define SR_KSU ((SR & status_KSU_mask) >> status_KSU_shift)
504
505 #define status_IE (1 << 0) /* Interrupt enable */
506 #define status_EIE (1 << 16) /* Enable Interrupt Enable */
507 #define status_EXL (1 << 1) /* Exception level */
508 #define status_RE (1 << 25) /* Reverse Endian in user mode */
509 #define status_FR (1 << 26) /* enables MIPS III additional FP registers */
510 #define status_SR (1 << 20) /* soft reset or NMI */
511 #define status_BEV (1 << 22) /* Location of general exception vectors */
512 #define status_TS (1 << 21) /* TLB shutdown has occurred */
513 #define status_ERL (1 << 2) /* Error level */
514 #define status_IM7 (1 << 15) /* Timer Interrupt Mask */
515 #define status_RP (1 << 27) /* Reduced Power mode */
516
517 /* Specializations for TX39 family */
518 #define status_IEc (1 << 0) /* Interrupt enable (current) */
519 #define status_KUc (1 << 1) /* Kernel/User mode */
520 #define status_IEp (1 << 2) /* Interrupt enable (previous) */
521 #define status_KUp (1 << 3) /* Kernel/User mode */
522 #define status_IEo (1 << 4) /* Interrupt enable (old) */
523 #define status_KUo (1 << 5) /* Kernel/User mode */
524 #define status_IM_mask (0xff) /* Interrupt mask */
525 #define status_IM_shift (8)
526 #define status_NMI (1 << 20) /* NMI */
527 #define status_NMI (1 << 20) /* NMI */
528
529 /* Status bits used by MIPS32/MIPS64. */
530 #define status_UX (1 << 5) /* 64-bit user addrs */
531 #define status_SX (1 << 6) /* 64-bit supervisor addrs */
532 #define status_KX (1 << 7) /* 64-bit kernel addrs */
533 #define status_TS (1 << 21) /* TLB shutdown has occurred */
534 #define status_PX (1 << 23) /* Enable 64 bit operations */
535 #define status_MX (1 << 24) /* Enable MDMX resources */
536 #define status_CU0 (1 << 28) /* Coprocessor 0 usable */
537 #define status_CU1 (1 << 29) /* Coprocessor 1 usable */
538 #define status_CU2 (1 << 30) /* Coprocessor 2 usable */
539 #define status_CU3 (1 << 31) /* Coprocessor 3 usable */
540 /* Bits reserved for implementations: */
541 #define status_SBX (1 << 16) /* Enable SiByte SB-1 extensions. */
542
543 #define cause_BD ((unsigned)1 << 31) /* L1 Exception in branch delay slot */
544 #define cause_BD2 (1 << 30) /* L2 Exception in branch delay slot */
545 #define cause_CE_mask 0x30000000 /* Coprocessor exception */
546 #define cause_CE_shift 28
547 #define cause_EXC2_mask 0x00070000
548 #define cause_EXC2_shift 16
549 #define cause_IP7 (1 << 15) /* Interrupt pending */
550 #define cause_SIOP (1 << 12) /* SIO pending */
551 #define cause_IP3 (1 << 11) /* Int 0 pending */
552 #define cause_IP2 (1 << 10) /* Int 1 pending */
553
554 #define cause_EXC_mask (0x1c) /* Exception code */
555 #define cause_EXC_shift (2)
556
557 #define cause_SW0 (1 << 8) /* Software interrupt 0 */
558 #define cause_SW1 (1 << 9) /* Software interrupt 1 */
559 #define cause_IP_mask (0x3f) /* Interrupt pending field */
560 #define cause_IP_shift (10)
561
562 #define cause_set_EXC(x) CAUSE = (CAUSE & ~cause_EXC_mask) | ((x << cause_EXC_shift) & cause_EXC_mask)
563 #define cause_set_EXC2(x) CAUSE = (CAUSE & ~cause_EXC2_mask) | ((x << cause_EXC2_shift) & cause_EXC2_mask)
564
565
566 /* NOTE: We keep the following status flags as bit values (1 for true,
567 0 for false). This allows them to be used in binary boolean
568 operations without worrying about what exactly the non-zero true
569 value is. */
570
571 /* UserMode */
572 #ifdef SUBTARGET_R3900
573 #define UserMode ((SR & status_KUc) ? 1 : 0)
574 #else
575 #define UserMode ((((SR & status_KSU_mask) >> status_KSU_shift) == ksu_user) ? 1 : 0)
576 #endif /* SUBTARGET_R3900 */
577
578 /* BigEndianMem */
579 /* Hardware configuration. Affects endianness of LoadMemory and
580 StoreMemory and the endianness of Kernel and Supervisor mode
581 execution. The value is 0 for little-endian; 1 for big-endian. */
582 #define BigEndianMem (CURRENT_TARGET_BYTE_ORDER == BIG_ENDIAN)
583 /*(state & simBE) ? 1 : 0)*/
584
585 /* ReverseEndian */
586 /* This mode is selected if in User mode with the RE bit being set in
587 SR (Status Register). It reverses the endianness of load and store
588 instructions. */
589 #define ReverseEndian (((SR & status_RE) && UserMode) ? 1 : 0)
590
591 /* BigEndianCPU */
592 /* The endianness for load and store instructions (0=little;1=big). In
593 User mode this endianness may be switched by setting the state_RE
594 bit in the SR register. Thus, BigEndianCPU may be computed as
595 (BigEndianMem EOR ReverseEndian). */
596 #define BigEndianCPU (BigEndianMem ^ ReverseEndian) /* Already bits */
597
598
599
600 /* Exceptions: */
601
602 /* NOTE: These numbers depend on the processor architecture being
603 simulated: */
604 enum ExceptionCause {
605 Interrupt = 0,
606 TLBModification = 1,
607 TLBLoad = 2,
608 TLBStore = 3,
609 AddressLoad = 4,
610 AddressStore = 5,
611 InstructionFetch = 6,
612 DataReference = 7,
613 SystemCall = 8,
614 BreakPoint = 9,
615 ReservedInstruction = 10,
616 CoProcessorUnusable = 11,
617 IntegerOverflow = 12, /* Arithmetic overflow (IDT monitor raises SIGFPE) */
618 Trap = 13,
619 FPE = 15,
620 DebugBreakPoint = 16, /* Impl. dep. in MIPS32/MIPS64. */
621 MDMX = 22,
622 Watch = 23,
623 MCheck = 24,
624 CacheErr = 30,
625 NMIReset = 31, /* Reserved in MIPS32/MIPS64. */
626
627
628 /* The following exception code is actually private to the simulator
629 world. It is *NOT* a processor feature, and is used to signal
630 run-time errors in the simulator. */
631 SimulatorFault = 0xFFFFFFFF
632 };
633
634 #define TLB_REFILL (0)
635 #define TLB_INVALID (1)
636
637
638 /* The following break instructions are reserved for use by the
639 simulator. The first is used to halt the simulation. The second
640 is used by gdb for break-points. NOTE: Care must be taken, since
641 this value may be used in later revisions of the MIPS ISA. */
642 #define HALT_INSTRUCTION_MASK (0x03FFFFC0)
643
644 #define HALT_INSTRUCTION (0x03ff000d)
645 #define HALT_INSTRUCTION2 (0x0000ffcd)
646
647
648 #define BREAKPOINT_INSTRUCTION (0x0005000d)
649 #define BREAKPOINT_INSTRUCTION2 (0x0000014d)
650
651
652
653 void interrupt_event (SIM_DESC sd, void *data);
654
655 void signal_exception (SIM_DESC sd, sim_cpu *cpu, address_word cia, int exception, ...);
656 #define SignalException(exc,instruction) signal_exception (SD, CPU, cia, (exc), (instruction))
657 #define SignalExceptionInterrupt(level) signal_exception (SD, CPU, cia, Interrupt, level)
658 #define SignalExceptionInstructionFetch() signal_exception (SD, CPU, cia, InstructionFetch)
659 #define SignalExceptionAddressStore() signal_exception (SD, CPU, cia, AddressStore)
660 #define SignalExceptionAddressLoad() signal_exception (SD, CPU, cia, AddressLoad)
661 #define SignalExceptionDataReference() signal_exception (SD, CPU, cia, DataReference)
662 #define SignalExceptionSimulatorFault(buf) signal_exception (SD, CPU, cia, SimulatorFault, buf)
663 #define SignalExceptionFPE() signal_exception (SD, CPU, cia, FPE)
664 #define SignalExceptionIntegerOverflow() signal_exception (SD, CPU, cia, IntegerOverflow)
665 #define SignalExceptionCoProcessorUnusable(cop) signal_exception (SD, CPU, cia, CoProcessorUnusable)
666 #define SignalExceptionNMIReset() signal_exception (SD, CPU, cia, NMIReset)
667 #define SignalExceptionTLBRefillStore() signal_exception (SD, CPU, cia, TLBStore, TLB_REFILL)
668 #define SignalExceptionTLBRefillLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_REFILL)
669 #define SignalExceptionTLBInvalidStore() signal_exception (SD, CPU, cia, TLBStore, TLB_INVALID)
670 #define SignalExceptionTLBInvalidLoad() signal_exception (SD, CPU, cia, TLBLoad, TLB_INVALID)
671 #define SignalExceptionTLBModification() signal_exception (SD, CPU, cia, TLBModification)
672 #define SignalExceptionMDMX() signal_exception (SD, CPU, cia, MDMX)
673 #define SignalExceptionWatch() signal_exception (SD, CPU, cia, Watch)
674 #define SignalExceptionMCheck() signal_exception (SD, CPU, cia, MCheck)
675 #define SignalExceptionCacheErr() signal_exception (SD, CPU, cia, CacheErr)
676
677 /* Co-processor accesses */
678
679 /* XXX FIXME: For now, assume that FPU (cp1) is always usable. */
680 #define COP_Usable(coproc_num) (coproc_num == 1)
681
682 void cop_lw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, unsigned int memword);
683 void cop_ld (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg, uword64 memword);
684 unsigned int cop_sw (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
685 uword64 cop_sd (SIM_DESC sd, sim_cpu *cpu, address_word cia, int coproc_num, int coproc_reg);
686
687 #define COP_LW(coproc_num,coproc_reg,memword) \
688 cop_lw (SD, CPU, cia, coproc_num, coproc_reg, memword)
689 #define COP_LD(coproc_num,coproc_reg,memword) \
690 cop_ld (SD, CPU, cia, coproc_num, coproc_reg, memword)
691 #define COP_SW(coproc_num,coproc_reg) \
692 cop_sw (SD, CPU, cia, coproc_num, coproc_reg)
693 #define COP_SD(coproc_num,coproc_reg) \
694 cop_sd (SD, CPU, cia, coproc_num, coproc_reg)
695
696
697 void decode_coproc (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int instruction);
698 #define DecodeCoproc(instruction) \
699 decode_coproc (SD, CPU, cia, (instruction))
700
701 int sim_monitor (SIM_DESC sd, sim_cpu *cpu, address_word cia, unsigned int arg);
702
703
704 /* FPR access. */
705 unsigned64 value_fpr (SIM_STATE, int fpr, FP_formats);
706 #define ValueFPR(FPR,FMT) value_fpr (SIM_ARGS, (FPR), (FMT))
707 void store_fpr (SIM_STATE, int fpr, FP_formats fmt, unsigned64 value);
708 #define StoreFPR(FPR,FMT,VALUE) store_fpr (SIM_ARGS, (FPR), (FMT), (VALUE))
709 unsigned64 ps_lower (SIM_STATE, unsigned64 op);
710 #define PSLower(op) ps_lower (SIM_ARGS, op)
711 unsigned64 ps_upper (SIM_STATE, unsigned64 op);
712 #define PSUpper(op) ps_upper (SIM_ARGS, op)
713 unsigned64 pack_ps (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats from);
714 #define PackPS(op1,op2) pack_ps (SIM_ARGS, op1, op2, fmt_single)
715
716
717 /* FCR access. */
718 unsigned_word value_fcr (SIM_STATE, int fcr);
719 #define ValueFCR(FCR) value_fcr (SIM_ARGS, (FCR))
720 void store_fcr (SIM_STATE, int fcr, unsigned_word value);
721 #define StoreFCR(FCR,VALUE) store_fcr (SIM_ARGS, (FCR), (VALUE))
722 void test_fcsr (SIM_STATE);
723 #define TestFCSR() test_fcsr (SIM_ARGS)
724
725
726 /* FPU operations. */
727 void fp_cmp (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt, int abs, int cond, int cc);
728 #define Compare(op1,op2,fmt,cond,cc) fp_cmp(SIM_ARGS, op1, op2, fmt, 0, cond, cc)
729 unsigned64 fp_abs (SIM_STATE, unsigned64 op, FP_formats fmt);
730 #define AbsoluteValue(op,fmt) fp_abs(SIM_ARGS, op, fmt)
731 unsigned64 fp_neg (SIM_STATE, unsigned64 op, FP_formats fmt);
732 #define Negate(op,fmt) fp_neg(SIM_ARGS, op, fmt)
733 unsigned64 fp_add (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
734 #define Add(op1,op2,fmt) fp_add(SIM_ARGS, op1, op2, fmt)
735 unsigned64 fp_sub (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
736 #define Sub(op1,op2,fmt) fp_sub(SIM_ARGS, op1, op2, fmt)
737 unsigned64 fp_mul (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
738 #define Multiply(op1,op2,fmt) fp_mul(SIM_ARGS, op1, op2, fmt)
739 unsigned64 fp_div (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
740 #define Divide(op1,op2,fmt) fp_div(SIM_ARGS, op1, op2, fmt)
741 unsigned64 fp_recip (SIM_STATE, unsigned64 op, FP_formats fmt);
742 #define Recip(op,fmt) fp_recip(SIM_ARGS, op, fmt)
743 unsigned64 fp_sqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
744 #define SquareRoot(op,fmt) fp_sqrt(SIM_ARGS, op, fmt)
745 unsigned64 fp_rsqrt (SIM_STATE, unsigned64 op, FP_formats fmt);
746 #define RSquareRoot(op,fmt) fp_rsqrt(SIM_ARGS, op, fmt)
747 unsigned64 fp_madd (SIM_STATE, unsigned64 op1, unsigned64 op2,
748 unsigned64 op3, FP_formats fmt);
749 #define MultiplyAdd(op1,op2,op3,fmt) fp_madd(SIM_ARGS, op1, op2, op3, fmt)
750 unsigned64 fp_msub (SIM_STATE, unsigned64 op1, unsigned64 op2,
751 unsigned64 op3, FP_formats fmt);
752 #define MultiplySub(op1,op2,op3,fmt) fp_msub(SIM_ARGS, op1, op2, op3, fmt)
753 unsigned64 fp_nmadd (SIM_STATE, unsigned64 op1, unsigned64 op2,
754 unsigned64 op3, FP_formats fmt);
755 #define NegMultiplyAdd(op1,op2,op3,fmt) fp_nmadd(SIM_ARGS, op1, op2, op3, fmt)
756 unsigned64 fp_nmsub (SIM_STATE, unsigned64 op1, unsigned64 op2,
757 unsigned64 op3, FP_formats fmt);
758 #define NegMultiplySub(op1,op2,op3,fmt) fp_nmsub(SIM_ARGS, op1, op2, op3, fmt)
759 unsigned64 convert (SIM_STATE, int rm, unsigned64 op, FP_formats from, FP_formats to);
760 #define Convert(rm,op,from,to) convert (SIM_ARGS, rm, op, from, to)
761 unsigned64 convert_ps (SIM_STATE, int rm, unsigned64 op, FP_formats from,
762 FP_formats to);
763 #define ConvertPS(rm,op,from,to) convert_ps (SIM_ARGS, rm, op, from, to)
764
765
766 /* MIPS-3D ASE operations. */
767 #define CompareAbs(op1,op2,fmt,cond,cc) \
768 fp_cmp(SIM_ARGS, op1, op2, fmt, 1, cond, cc)
769 unsigned64 fp_add_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
770 #define AddR(op1,op2,fmt) fp_add_r(SIM_ARGS, op1, op2, fmt)
771 unsigned64 fp_mul_r (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
772 #define MultiplyR(op1,op2,fmt) fp_mul_r(SIM_ARGS, op1, op2, fmt)
773 unsigned64 fp_recip1 (SIM_STATE, unsigned64 op, FP_formats fmt);
774 #define Recip1(op,fmt) fp_recip1(SIM_ARGS, op, fmt)
775 unsigned64 fp_recip2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
776 #define Recip2(op1,op2,fmt) fp_recip2(SIM_ARGS, op1, op2, fmt)
777 unsigned64 fp_rsqrt1 (SIM_STATE, unsigned64 op, FP_formats fmt);
778 #define RSquareRoot1(op,fmt) fp_rsqrt1(SIM_ARGS, op, fmt)
779 unsigned64 fp_rsqrt2 (SIM_STATE, unsigned64 op1, unsigned64 op2, FP_formats fmt);
780 #define RSquareRoot2(op1,op2,fmt) fp_rsqrt2(SIM_ARGS, op1, op2, fmt)
781
782
783 /* MDMX access. */
784
785 typedef unsigned int MX_fmtsel; /* MDMX format select field (5 bits). */
786 #define ob_fmtsel(sel) (((sel)<<1)|0x0)
787 #define qh_fmtsel(sel) (((sel)<<2)|0x1)
788
789 #define fmt_mdmx fmt_uninterpreted
790
791 #define MX_VECT_AND (0)
792 #define MX_VECT_NOR (1)
793 #define MX_VECT_OR (2)
794 #define MX_VECT_XOR (3)
795 #define MX_VECT_SLL (4)
796 #define MX_VECT_SRL (5)
797 #define MX_VECT_ADD (6)
798 #define MX_VECT_SUB (7)
799 #define MX_VECT_MIN (8)
800 #define MX_VECT_MAX (9)
801 #define MX_VECT_MUL (10)
802 #define MX_VECT_MSGN (11)
803 #define MX_VECT_SRA (12)
804 #define MX_VECT_ABSD (13) /* SB-1 only. */
805 #define MX_VECT_AVG (14) /* SB-1 only. */
806
807 unsigned64 mdmx_cpr_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
808 #define MX_Add(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ADD, op1, vt, fmtsel)
809 #define MX_And(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AND, op1, vt, fmtsel)
810 #define MX_Max(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MAX, op1, vt, fmtsel)
811 #define MX_Min(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MIN, op1, vt, fmtsel)
812 #define MX_Msgn(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MSGN, op1, vt, fmtsel)
813 #define MX_Mul(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_MUL, op1, vt, fmtsel)
814 #define MX_Nor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_NOR, op1, vt, fmtsel)
815 #define MX_Or(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_OR, op1, vt, fmtsel)
816 #define MX_ShiftLeftLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SLL, op1, vt, fmtsel)
817 #define MX_ShiftRightArith(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRA, op1, vt, fmtsel)
818 #define MX_ShiftRightLogical(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SRL, op1, vt, fmtsel)
819 #define MX_Sub(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_SUB, op1, vt, fmtsel)
820 #define MX_Xor(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_XOR, op1, vt, fmtsel)
821 #define MX_AbsDiff(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_ABSD, op1, vt, fmtsel)
822 #define MX_Avg(op1,vt,fmtsel) mdmx_cpr_op(SIM_ARGS, MX_VECT_AVG, op1, vt, fmtsel)
823
824 #define MX_C_EQ 0x1
825 #define MX_C_LT 0x4
826
827 void mdmx_cc_op (SIM_STATE, int cond, unsigned64 op1, int vt, MX_fmtsel fmtsel);
828 #define MX_Comp(op1,cond,vt,fmtsel) mdmx_cc_op(SIM_ARGS, cond, op1, vt, fmtsel)
829
830 unsigned64 mdmx_pick_op (SIM_STATE, int tf, unsigned64 op1, int vt, MX_fmtsel fmtsel);
831 #define MX_Pick(tf,op1,vt,fmtsel) mdmx_pick_op(SIM_ARGS, tf, op1, vt, fmtsel)
832
833 #define MX_VECT_ADDA (0)
834 #define MX_VECT_ADDL (1)
835 #define MX_VECT_MULA (2)
836 #define MX_VECT_MULL (3)
837 #define MX_VECT_MULS (4)
838 #define MX_VECT_MULSL (5)
839 #define MX_VECT_SUBA (6)
840 #define MX_VECT_SUBL (7)
841 #define MX_VECT_ABSDA (8) /* SB-1 only. */
842
843 void mdmx_acc_op (SIM_STATE, int op, unsigned64 op1, int vt, MX_fmtsel fmtsel);
844 #define MX_AddA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDA, op1, vt, fmtsel)
845 #define MX_AddL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ADDL, op1, vt, fmtsel)
846 #define MX_MulA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULA, op1, vt, fmtsel)
847 #define MX_MulL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULL, op1, vt, fmtsel)
848 #define MX_MulS(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULS, op1, vt, fmtsel)
849 #define MX_MulSL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_MULSL, op1, vt, fmtsel)
850 #define MX_SubA(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBA, op1, vt, fmtsel)
851 #define MX_SubL(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_SUBL, op1, vt, fmtsel)
852 #define MX_AbsDiffC(op1,vt,fmtsel) mdmx_acc_op(SIM_ARGS, MX_VECT_ABSDA, op1, vt, fmtsel)
853
854 #define MX_FMT_OB (0)
855 #define MX_FMT_QH (1)
856
857 /* The following codes chosen to indicate the units of shift. */
858 #define MX_RAC_L (0)
859 #define MX_RAC_M (1)
860 #define MX_RAC_H (2)
861
862 unsigned64 mdmx_rac_op (SIM_STATE, int, int);
863 #define MX_RAC(op,fmt) mdmx_rac_op(SIM_ARGS, op, fmt)
864
865 void mdmx_wacl (SIM_STATE, int, unsigned64, unsigned64);
866 #define MX_WACL(fmt,vs,vt) mdmx_wacl(SIM_ARGS, fmt, vs, vt)
867 void mdmx_wach (SIM_STATE, int, unsigned64);
868 #define MX_WACH(fmt,vs) mdmx_wach(SIM_ARGS, fmt, vs)
869
870 #define MX_RND_AS (0)
871 #define MX_RND_AU (1)
872 #define MX_RND_ES (2)
873 #define MX_RND_EU (3)
874 #define MX_RND_ZS (4)
875 #define MX_RND_ZU (5)
876
877 unsigned64 mdmx_round_op (SIM_STATE, int, int, MX_fmtsel);
878 #define MX_RNAS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AS, vt, fmt)
879 #define MX_RNAU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_AU, vt, fmt)
880 #define MX_RNES(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ES, vt, fmt)
881 #define MX_RNEU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_EU, vt, fmt)
882 #define MX_RZS(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZS, vt, fmt)
883 #define MX_RZU(vt,fmt) mdmx_round_op(SIM_ARGS, MX_RND_ZU, vt, fmt)
884
885 unsigned64 mdmx_shuffle (SIM_STATE, int, unsigned64, unsigned64);
886 #define MX_SHFL(shop,op1,op2) mdmx_shuffle(SIM_ARGS, shop, op1, op2)
887
888
889
890 /* Memory accesses */
891
892 /* The following are generic to all versions of the MIPS architecture
893 to date: */
894
895 /* Memory Access Types (for CCA): */
896 #define Uncached (0)
897 #define CachedNoncoherent (1)
898 #define CachedCoherent (2)
899 #define Cached (3)
900
901 #define isINSTRUCTION (1 == 0) /* FALSE */
902 #define isDATA (1 == 1) /* TRUE */
903 #define isLOAD (1 == 0) /* FALSE */
904 #define isSTORE (1 == 1) /* TRUE */
905 #define isREAL (1 == 0) /* FALSE */
906 #define isRAW (1 == 1) /* TRUE */
907 /* The parameter HOST (isTARGET / isHOST) is ignored */
908 #define isTARGET (1 == 0) /* FALSE */
909 /* #define isHOST (1 == 1) TRUE */
910
911 /* The "AccessLength" specifications for Loads and Stores. NOTE: This
912 is the number of bytes minus 1. */
913 #define AccessLength_BYTE (0)
914 #define AccessLength_HALFWORD (1)
915 #define AccessLength_TRIPLEBYTE (2)
916 #define AccessLength_WORD (3)
917 #define AccessLength_QUINTIBYTE (4)
918 #define AccessLength_SEXTIBYTE (5)
919 #define AccessLength_SEPTIBYTE (6)
920 #define AccessLength_DOUBLEWORD (7)
921 #define AccessLength_QUADWORD (15)
922
923 #define LOADDRMASK (WITH_TARGET_WORD_BITSIZE == 64 \
924 ? AccessLength_DOUBLEWORD /*7*/ \
925 : AccessLength_WORD /*3*/)
926 #define PSIZE (WITH_TARGET_ADDRESS_BITSIZE)
927
928
929 INLINE_SIM_MAIN (int) address_translation (SIM_DESC sd, sim_cpu *, address_word cia, address_word vAddr, int IorD, int LorS, address_word *pAddr, int *CCA, int raw);
930 #define AddressTranslation(vAddr,IorD,LorS,pAddr,CCA,host,raw) \
931 address_translation (SD, CPU, cia, vAddr, IorD, LorS, pAddr, CCA, raw)
932
933 INLINE_SIM_MAIN (void) load_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, uword64* memvalp, uword64* memval1p, int CCA, unsigned int AccessLength, address_word pAddr, address_word vAddr, int IorD);
934 #define LoadMemory(memvalp,memval1p,CCA,AccessLength,pAddr,vAddr,IorD,raw) \
935 load_memory (SD, CPU, cia, memvalp, memval1p, CCA, AccessLength, pAddr, vAddr, IorD)
936
937 INLINE_SIM_MAIN (void) store_memory (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, unsigned int AccessLength, uword64 MemElem, uword64 MemElem1, address_word pAddr, address_word vAddr);
938 #define StoreMemory(CCA,AccessLength,MemElem,MemElem1,pAddr,vAddr,raw) \
939 store_memory (SD, CPU, cia, CCA, AccessLength, MemElem, MemElem1, pAddr, vAddr)
940
941 INLINE_SIM_MAIN (void) cache_op (SIM_DESC sd, sim_cpu *cpu, address_word cia, int op, address_word pAddr, address_word vAddr, unsigned int instruction);
942 #define CacheOp(op,pAddr,vAddr,instruction) \
943 cache_op (SD, CPU, cia, op, pAddr, vAddr, instruction)
944
945 INLINE_SIM_MAIN (void) sync_operation (SIM_DESC sd, sim_cpu *cpu, address_word cia, int stype);
946 #define SyncOperation(stype) \
947 sync_operation (SD, CPU, cia, (stype))
948
949 INLINE_SIM_MAIN (void) prefetch (SIM_DESC sd, sim_cpu *cpu, address_word cia, int CCA, address_word pAddr, address_word vAddr, int DATA, int hint);
950 #define Prefetch(CCA,pAddr,vAddr,DATA,hint) \
951 prefetch (SD, CPU, cia, CCA, pAddr, vAddr, DATA, hint)
952
953 void unpredictable_action (sim_cpu *cpu, address_word cia);
954 #define NotWordValue(val) not_word_value (SD_, (val))
955 #define Unpredictable() unpredictable (SD_)
956 #define UnpredictableResult() /* For now, do nothing. */
957
958 INLINE_SIM_MAIN (unsigned32) ifetch32 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
959 #define IMEM32(CIA) ifetch32 (SD, CPU, (CIA), (CIA))
960 INLINE_SIM_MAIN (unsigned16) ifetch16 (SIM_DESC sd, sim_cpu *cpu, address_word cia, address_word vaddr);
961 #define IMEM16(CIA) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1))
962 #define IMEM16_IMMED(CIA,NR) ifetch16 (SD, CPU, (CIA), ((CIA) & ~1) + 2 * (NR))
963
964 void dotrace (SIM_DESC sd, sim_cpu *cpu, FILE *tracefh, int type, SIM_ADDR address, int width, char *comment, ...);
965 extern FILE *tracefh;
966
967 extern int DSPLO_REGNUM[4];
968 extern int DSPHI_REGNUM[4];
969
970 INLINE_SIM_MAIN (void) pending_tick (SIM_DESC sd, sim_cpu *cpu, address_word cia);
971 extern SIM_CORE_SIGNAL_FN mips_core_signal;
972
973 char* pr_addr (SIM_ADDR addr);
974 char* pr_uword64 (uword64 addr);
975
976
977 #define GPR_CLEAR(N) do { GPR_SET((N),0); } while (0)
978
979 void mips_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
980 void mips_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
981 void mips_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
982
983 #ifdef MIPS_MACH_MULTI
984 extern int mips_mach_multi(SIM_DESC sd);
985 #define MIPS_MACH(SD) mips_mach_multi(SD)
986 #else
987 #define MIPS_MACH(SD) MIPS_MACH_DEFAULT
988 #endif
989
990 /* Macros for determining whether a MIPS IV or MIPS V part is subject
991 to the hi/lo restrictions described in mips.igen. */
992
993 #define MIPS_MACH_HAS_MT_HILO_HAZARD(SD) \
994 (MIPS_MACH (SD) != bfd_mach_mips5500)
995
996 #define MIPS_MACH_HAS_MULT_HILO_HAZARD(SD) \
997 (MIPS_MACH (SD) != bfd_mach_mips5500)
998
999 #define MIPS_MACH_HAS_DIV_HILO_HAZARD(SD) \
1000 (MIPS_MACH (SD) != bfd_mach_mips5500)
1001
1002 #if H_REVEALS_MODULE_P (SIM_MAIN_INLINE)
1003 #include "sim-main.c"
1004 #endif
1005
1006 #endif