sim/mn10300/ChangeLog

   1 Fri Jan 24 10:47:25 1997  Jeffrey A Law  (law@cygnus.com)
   2
   3         * interp.c (init_system): Allocate 2^19 bytes of space for the
   4         simulator.
   5
   6 Thu Jan 23 11:46:23 1997  Stu Grossman  (grossman@critters.cygnus.com)
   7
   8         * configure configure.in Makefile.in:  Update to new configure
   9         scheme which is more compatible with WinGDB builds.
  10         * configure.in:  Improve comment on how to run autoconf.
  11         * configure:  Re-run autoconf to get new ../common/aclocal.m4.
  12         * Makefile.in:  Use autoconf substitution to install common
  13         makefile fragment.
  14
  15 Tue Jan 21 15:03:04 1997  Jeffrey A Law  (law@cygnus.com)
  16
  17         * simops.c: Undo last change to "rol" and "ror", original code
  18         was correct!
  19
  20 Thu Jan 16 11:28:14 1997  Jeffrey A Law  (law@cygnus.com)
  21
  22         * simops.c: Fix "rol" and "ror".
  23
  24 Wed Jan 15 06:45:58 1997  Jeffrey A Law  (law@cygnus.com)
  25
  26         * simops.c: Fix typo in last change.
  27
  28 Mon Jan 13 13:22:35 1997  Jeffrey A Law  (law@cygnus.com)
  29
  30         * simops.c: Use REG macros in few places not using them yet.
  31
  32 Mon Jan  6 16:21:19 1997  Jeffrey A Law  (law@cygnus.com)
  33
  34         * mn10300_sim.h (struct _state): Fix number of registers!
  35
  36 Tue Dec 31 16:20:41 1996  Jeffrey A Law  (law@cygnus.com)
  37
  38         * mn10300_sim.h (struct _state): Put all registers into a single
  39         array to make gdb implementation easier.
  40         (REG_*): Add definitions for all registers in the state array.
  41         (SEXT32, SEXT40, SEXT44, SEXT60): Remove unused macros.
  42         * simops.c: Related changes.
  43
  44 Wed Dec 18 10:10:45 1996  Jeffrey A Law  (law@cygnus.com)
  45
  46         * interp.c (sim_resume): Handle 0xff as a single byte insn.
  47
  48         * simops.c: Fix overflow computation for "add" and "inc"
  49         instructions.
  50
  51 Mon Dec 16 10:03:52 1996  Jeffrey A Law  (law@cygnus.com)
  52
  53         * simops.c: Handle "break" instruction.
  54
  55         * simops.c: Fix restoring the PC for "ret" and "retf" instructions.
  56
  57 Wed Dec 11 09:53:10 1996  Jeffrey A Law  (law@cygnus.com)
  58
  59         * gencode.c (write_opcodes): Also write out the format of the
  60         opcode.
  61         * mn10300_sim.h (simops): Add "format" field.
  62         * interp.c (sim_resume): Deal with endianness issues here.
  63
  64 Tue Dec 10 15:05:37 1996  Jeffrey A Law  (law@cygnus.com)
  65
  66         * simops.c (REG0_4): Define.
  67         Use REG0_4 for indexed loads/stores.
  68
  69 Sat Dec  7 09:50:28 1996  Jeffrey A Law  (law@cygnus.com)
  70
  71         * simops.c (REG0_16): Fix typo.
  72
  73 Fri Dec  6 14:13:34 1996  Jeffrey A Law  (law@cygnus.com)
  74
  75         * simops.c: Call abort for any instruction that's not currently
  76         simulated.
  77
  78         * simops.c: Define accessor macros to extract register
  79         values from instructions.  Use them consistently.
  80
  81         * interp.c: Delete unused global variable "OP".
  82         (sim_resume): Remove unused variable "opcode".
  83         * simops.c: Fix some uninitialized variable problems, add
  84         parens to fix various -Wall warnings.
  85
  86         * gencode.c (write_header): Add "insn" and "extension" arguments
  87         to the OP_* declarations.
  88         (write_template): Similarly for function templates.
  89         * interp.c (insn, extension): Remove global variables.  Instead
  90         pass them as arguments to the OP_* functions.
  91         * mn10300_sim.h: Remove decls for "insn" and "extension".
  92         * simops.c (OP_*): Accept "insn" and "extension" as arguments
  93         instead of using globals.
  94
  95 Thu Dec  5 22:26:31 1996  Jeffrey A Law  (law@cygnus.com)
  96
  97         * simops.c: Fix typos in "mov am,(d16,an)" and "mov am,(d32,an)"
  98
  99         * simops.c: Fix thinkos in last change to "inc dn".
 100
 101 Wed Dec  4 10:57:53 1996  Jeffrey A Law  (law@cygnus.com)
 102
 103         * simops.c: "add imm,sp" does not effect the condition codes.
 104         "inc dn" does effect the condition codes.
 105
 106 Tue Dec  3 17:37:45 1996  Jeffrey A Law  (law@cygnus.com)
 107
 108         * simops.c: Treat both operands as signed values for
 109         "div" instruction.
 110
 111         * simops.c: Fix simulation of division instructions.
 112         Fix typos/thinkos in several "cmp" and "sub" instructions.
 113
 114 Mon Dec  2 12:31:40 1996  Jeffrey A Law  (law@cygnus.com)
 115
 116         * simops.c: Fix carry bit handling in "sub" and "cmp"
 117         instructions.
 118
 119         * simops.c: Fix "mov imm8,an" and "mov imm16,dn".
 120
 121 Sun Dec  1 16:05:42 1996  Jeffrey A Law  (law@cygnus.com)
 122
 123         * simops.c: Fix overflow computation for many instructions.
 124
 125         * simops.c: Fix "mov dm, an", "movbu dm, (an)", and "movhu dm, (an)".
 126
 127         * simops.c: Fix "mov am, dn".
 128
 129         * simops.c: Fix more bugs in "add imm,an" and
 130         "add imm,dn".
 131
 132 Wed Nov 27 09:20:42 1996  Jeffrey A Law  (law@cygnus.com)
 133
 134         * simops.c: Fix bugs in "movm" and "add imm,an".
 135
 136         * simops.c: Don't lose the upper 24 bits of the return
 137         pointer in "call" and "calls" instructions.  Rough cut
 138         at emulated system calls.
 139
 140         * simops.c: Implement the remaining 5, 6 and 7 byte instructions.
 141
 142         * simops.c: Implement remaining 4 byte instructions.
 143
 144         * simops.c: Implement remaining 3 byte instructions.
 145
 146         * simops.c: Implement remaining 2 byte instructions.  Call
 147         abort for instructions we're not implementing now.
 148
 149 Tue Nov 26 15:43:41 1996  Jeffrey A Law  (law@cygnus.com)
 150
 151         * simops.c: Implement lots of random instructions.
 152
 153         * simops.c: Implement "movm" and "bCC" insns.
 154
 155         * mn10300_sim.h (_state): Add another register (MDR).
 156         (REG_MDR): Define.
 157         * simops.c: Implement "cmp", "calls", "rets", "jmp" and
 158         a few additional random insns.
 159
 160         * mn10300_sim.h (PSW_*): Define for CC status tracking.
 161         (REG_D0, REG_A0, REG_SP): Define.
 162         * simops.c: Implement "add", "addc" and a few other random
 163         instructions.
 164
 165         * gencode.c, interp.c: Snapshot current simulator code.
 166
 167 Mon Nov 25 12:46:38 1996  Jeffrey A Law  (law@cygnus.com)
 168
 169         * Makefile.in, config.in, configure, configure.in: New files.
 170         * gencode.c, interp.c, mn10300_sim.h, simops.c: New files.
 171