1 // 1111 0000 0010 00An; mov USP,An
2 8.0xf0+4.0x2,00,2.AN0:D0m:::mov
7 State.regs[REG_A0 + AN0] = State.regs[REG_USP];
11 // 1111 0000 0010 01An; mov SSP,An
12 8.0xf0+4.0x2,01,2.AN0:D0n:::mov
17 State.regs[REG_A0 + AN0] = State.regs[REG_SSP];
21 // 1111 0000 0010 10An; mov MSP,An
22 8.0xf0+4.0x2,10,2.AN0:D0o:::mov
27 State.regs[REG_A0 + AN0] = State.regs[REG_MSP];
31 // 1111 0000 0010 11An; mov PC,An
32 8.0xf0+4.0x2,11,2.AN0:D0p:::mov
37 State.regs[REG_A0 + AN0] = PC;
41 // 1111 0000 0011 Am00; mov Am,USP
42 8.0xf0+4.0x3,2.AM1,00:D0q:::mov
47 State.regs[REG_USP] = State.regs[REG_A0 + AM1];
50 // 1111 0000 0011 Am01; mov Am,SSP
51 8.0xf0+4.0x3,2.AM1,01:D0r:::mov
56 State.regs[REG_SSP] = State.regs[REG_A0 + AM1];
59 // 1111 0000 0011 Am10; mov Am,MSP
60 8.0xf0+4.0x3,2.AM1,10:D0s:::mov
65 State.regs[REG_MSP] = State.regs[REG_A0 + AM1];
69 // 1111 0000 1110 imm4; syscall
70 8.0xf0+4.0xe,IMM4:D0t:::syscall
74 unsigned int sp, next_pc;
77 sp = State.regs[REG_SP];
78 next_pc = State.regs[REG_PC] + 2;
79 store_word (sp - 4, next_pc);
80 store_word (sp - 8, PSW);
81 State.regs[REG_PC] = 0x40000000 + IMM4 * 8;
86 // 1111 0010 1110 11Dn; mov EPSW,Dn
87 8.0xf2+4.0xe,11,2.DN0:D0u:::mov
92 State.regs[REG_D0 + DN0] = PSW;
96 // 1111 0010 1111 Dm01; mov Dm,EPSW
97 8.0xf2+4.0xf,2.DM1,01:D0v:::mov
102 PSW = State.regs[REG_D0 + DM1];
105 // 1111 0101 00Am Rn; mov Am,Rn
106 8.0xf5+00,2.AM1,4.RN0:D0w:::mov
111 /* The higher register numbers actually correspond to the
112 basic machine's address and data registers. */
113 if (RN0 > 7 && RN0 < 12)
114 State.regs[REG_A0 + RN0 - 8] = State.regs[REG_A0 + AM1];
115 else if (RN0 > 11 && RN0 < 16)
116 State.regs[REG_D0 + RN0 - 12] = State.regs[REG_A0 + AM1];
118 State.regs[REG_E0 + RN0] = State.regs[REG_A0 + AM1] ;
121 // 1111 0101 01Dm Rn; mov Dm,Rn
122 8.0xf5+01,2.DM1,4.RN0:D0x:::mov
127 /* The higher register numbers actually correspond to the
128 basic machine's address and data registers. */
129 if (RN0 > 7 && RN0 < 12)
130 State.regs[REG_A0 + RN0 - 8] = State.regs[REG_D0 + DM1];
131 else if (RN0 > 11 && RN0 < 16)
132 State.regs[REG_D0 + RN0 - 12] = State.regs[REG_D0 + DM1];
134 State.regs[REG_E0 + RN0] = State.regs[REG_D0 + DM1] ;
137 // 1111 0101 10Rm An; mov Rm,An
138 8.0xf5+10,4.RM1,2.AN0:D0y:::mov
143 /* The higher register numbers actually correspond to the
144 basic machine's address and data registers. */
145 if (RM1 > 7 && RM1 < 12)
146 State.regs[REG_A0 + AN0] = State.regs[REG_A0 + RM1 - 8];
147 else if (RM1 > 11 && RM1 < 16)
148 State.regs[REG_A0 + AN0] = State.regs[REG_D0 + RM1 - 12];
150 State.regs[REG_A0 + AN0] = State.regs[REG_E0 + RM1];
153 // 1111 0101 11Rm Dn; mov Rm,Dn
154 8.0xf5+11,4.RM1,2.DN0:D0z:::mov
159 /* The higher register numbers actually correspond to the
160 basic machine's address and data registers. */
161 if (RM1 > 7 && RM1 < 12)
162 State.regs[REG_D0 + DN0] = State.regs[REG_A0 + RM1 - 8];
163 else if (RM1 > 11 && RM1 < 16)
164 State.regs[REG_D0 + DN0] = State.regs[REG_D0 + RM1 - 12];
166 State.regs[REG_D0 + DN0] = State.regs[REG_E0 + RM1];
170 // 1111 1000 1100 1110 regs....; movm (USP),regs
171 8.0xf8+8.0xce+8.REGS:D1a:::movm
175 unsigned long usp = State.regs[REG_USP];
184 State.regs[REG_LAR] = load_word (usp);
186 State.regs[REG_LIR] = load_word (usp);
188 State.regs[REG_MDR] = load_word (usp);
190 State.regs[REG_A0 + 1] = load_word (usp);
192 State.regs[REG_A0] = load_word (usp);
194 State.regs[REG_D0 + 1] = load_word (usp);
196 State.regs[REG_D0] = load_word (usp);
202 State.regs[REG_A0 + 3] = load_word (usp);
208 State.regs[REG_A0 + 2] = load_word (usp);
214 State.regs[REG_D0 + 3] = load_word (usp);
220 State.regs[REG_D0 + 2] = load_word (usp);
224 /* start-sanitize-am33 */
225 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
229 /* Need to restore MDQR, MCRH, MCRL, and MCVF */
231 State.regs[REG_E0 + 1] = load_word (usp);
233 State.regs[REG_E0 + 0] = load_word (usp);
239 State.regs[REG_E0 + 7] = load_word (usp);
241 State.regs[REG_E0 + 6] = load_word (usp);
243 State.regs[REG_E0 + 5] = load_word (usp);
245 State.regs[REG_E0 + 4] = load_word (usp);
251 State.regs[REG_E0 + 3] = load_word (usp);
253 State.regs[REG_E0 + 2] = load_word (usp);
257 /* end-sanitize-am33 */
259 /* And make sure to update the stack pointer. */
260 State.regs[REG_USP] = usp;
263 // 1111 1000 1100 1111 regs....; movm (USP),regs
264 8.0xf8+8.0xcf+8.REGS:D1b:::movm
268 unsigned long usp = State.regs[REG_USP];
271 if (STATE_ARCHITECTURE (sd)->mach == bfd_mach_am33)
276 store_word (usp, State.regs[REG_E0 + 2]);
278 store_word (usp, State.regs[REG_E0 + 3]);
284 store_word (usp, State.regs[REG_E0 + 4]);
286 store_word (usp, State.regs[REG_E0 + 5]);
288 store_word (usp, State.regs[REG_E0 + 6]);
290 store_word (usp, State.regs[REG_E0 + 7]);
296 store_word (usp, State.regs[REG_E0 + 0]);
298 store_word (usp, State.regs[REG_E0 + 1]);
300 /* Need to save MDQR, MCRH, MCRL, and MCVF */
303 /* end-sanitize-am33 */
308 store_word (usp, State.regs[REG_D0 + 2]);
314 store_word (usp, State.regs[REG_D0 + 3]);
320 store_word (usp, State.regs[REG_A0 + 2]);
326 store_word (usp, State.regs[REG_A0 + 3]);
332 store_word (usp, State.regs[REG_D0]);
334 store_word (usp, State.regs[REG_D0 + 1]);
336 store_word (usp, State.regs[REG_A0]);
338 store_word (usp, State.regs[REG_A0 + 1]);
340 store_word (usp, State.regs[REG_MDR]);
342 store_word (usp, State.regs[REG_LIR]);
344 store_word (usp, State.regs[REG_LAR]);
348 /* And make sure to update the stack pointer. */
349 State.regs[REG_USP] = usp;
352 // 1111 1100 1111 1100 imm32...; and imm32,EPSW
353 8.0xfc+8.0xfc+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:4a:::and
358 PSW &= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
361 // 1111 1100 1111 1101 imm32...; or imm32,EPSW
362 8.0xfc+8.0xfd+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D4a:::or
367 PSW |= FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
370 // 1111 1001 0000 1000 Rm Rn; mov Rm,Rn (Rm != Rn)
371 8.0xf9+8.0x08+4.RM2,4.RN0!RM2:D1g:::mov
379 if (RM2 > 7 && RM2 < 12)
380 srcreg = REG_A0 + RM2 - 8;
381 else if (RM2 > 11 && RM2 < 16)
382 srcreg = REG_D0 + RM2 - 12;
384 srcreg = REG_E0 + RM2;
386 if (RN0 > 7 && RN0 < 12)
387 dstreg = REG_A0 + RN0 - 8;
388 else if (RN0 > 11 && RN0 < 16)
389 dstreg = REG_D0 + RN0 - 12;
391 dstreg = REG_E0 + RN0;
393 State.regs[dstreg] = State.regs[srcreg];
396 // 1111 1001 0001 1000 Rn Rn; ext Rn
397 8.0xf9+8.0x18+4.RN0,4.RN2=RN0:D1:::ext
405 if (RN0 > 7 && RN0 < 12)
406 srcreg = REG_A0 + RN0 - 8;
407 else if (RN0 > 11 && RN0 < 16)
408 srcreg = REG_D0 + RN0 - 12;
410 srcreg = REG_E0 + RN0;
412 if (State.regs[srcreg] & 0x80000000)
413 State.regs[REG_MDR] = -1;
415 State.regs[REG_MDR] = 0;
418 // 1111 1001 0010 1000 Rm Rn; extb Rm,Rn
419 8.0xf9+8.0x28+4.RM2,4.RN0!RM2:D1:::extb
427 if (RM2 > 7 && RM2 < 12)
428 srcreg = REG_A0 + RM2 - 8;
429 else if (RM2 > 11 && RM2 < 16)
430 srcreg = REG_D0 + RM2 - 12;
432 srcreg = REG_E0 + RM2;
434 if (RN0 > 7 && RN0 < 12)
435 dstreg = REG_A0 + RN0 - 8;
436 else if (RN0 > 11 && RN0 < 16)
437 dstreg = REG_D0 + RN0 - 12;
439 dstreg = REG_E0 + RN0;
441 State.regs[dstreg] = EXTEND8 (State.regs[srcreg]);
444 // 1111 1001 0011 1000 Rm Rn; extbu Rm,Rn
445 8.0xf9+8.0x38+4.RM2,4.RN0!RM2:D1:::extbu
453 if (RM2 > 7 && RM2 < 12)
454 srcreg = REG_A0 + RM2 - 8;
455 else if (RM2 > 11 && RM2 < 16)
456 srcreg = REG_D0 + RM2 - 12;
458 srcreg = REG_E0 + RM2;
460 if (RN0 > 7 && RN0 < 12)
461 dstreg = REG_A0 + RN0 - 8;
462 else if (RN0 > 11 && RN0 < 16)
463 dstreg = REG_D0 + RN0 - 12;
465 dstreg = REG_E0 + RN0;
467 State.regs[dstreg] = State.regs[srcreg] & 0xff;
470 // 1111 1001 0100 1000 Rm Rn; exth Rm,Rn
471 8.0xf9+8.0x48+4.RM2,4.RN0!RM2:D1:::exth
479 if (RM2 > 7 && RM2 < 12)
480 srcreg = REG_A0 + RM2 - 8;
481 else if (RM2 > 11 && RM2 < 16)
482 srcreg = REG_D0 + RM2 - 12;
484 srcreg = REG_E0 + RM2;
486 if (RN0 > 7 && RN0 < 12)
487 dstreg = REG_A0 + RN0 - 8;
488 else if (RN0 > 11 && RN0 < 16)
489 dstreg = REG_D0 + RN0 - 12;
491 dstreg = REG_E0 + RN0;
493 State.regs[dstreg] = EXTEND16 (State.regs[srcreg]);
496 // 1111 1001 0101 1000 Rm Rn; exthu Rm,Rn
497 8.0xf9+8.0x58+4.RM2,4.RN0!RM2:D1:::exthu
505 if (RM2 > 7 && RM2 < 12)
506 srcreg = REG_A0 + RM2 - 8;
507 else if (RM2 > 11 && RM2 < 16)
508 srcreg = REG_D0 + RM2 - 12;
510 srcreg = REG_E0 + RM2;
512 if (RN0 > 7 && RN0 < 12)
513 dstreg = REG_A0 + RN0 - 8;
514 else if (RN0 > 11 && RN0 < 16)
515 dstreg = REG_D0 + RN0 - 12;
517 dstreg = REG_E0 + RN0;
519 State.regs[dstreg] = State.regs[srcreg] & 0xffff;
522 // 1111 1001 0110 1000 Rn Rn; clr Rn
523 8.0xf9+8.0x68+4.RM2,4.RN0=RM2:D1:::clr
531 if (RN0 > 7 && RN0 < 12)
532 dstreg = REG_A0 + RN0 - 8;
533 else if (RN0 > 11 && RN0 < 16)
534 dstreg = REG_D0 + RN0 - 12;
536 dstreg = REG_E0 + RN0;
538 State.regs[dstreg] = 0;
541 PSW &= ~(PSW_V | PSW_C | PSW_N);
544 // 1111 1001 0111 1000 Rm Rn; add Rm,Rn
545 8.0xf9+8.0x78+4.RM2,4.RN0:D1b:::add
553 if (RM2 > 7 && RM2 < 12)
554 srcreg = REG_A0 + RM2 - 8;
555 else if (RM2 > 11 && RM2 < 16)
556 srcreg = REG_D0 + RM2 - 12;
558 srcreg = REG_E0 + RM2;
560 if (RN0 > 7 && RN0 < 12)
561 dstreg = REG_A0 + RN0 - 8;
562 else if (RN0 > 11 && RN0 < 16)
563 dstreg = REG_D0 + RN0 - 12;
565 dstreg = REG_E0 + RN0;
567 genericAdd (State.regs[srcreg], dstreg);
570 // 1111 1001 1000 1000 Rm Rn; addc Rm,Rn
571 8.0xf9+8.0x88+4.RM2,4.RN0:D1b:::addc
577 unsigned long reg1, reg2, sum;
581 if (RM2 > 7 && RM2 < 12)
582 srcreg = REG_A0 + RM2 - 8;
583 else if (RM2 > 11 && RM2 < 16)
584 srcreg = REG_D0 + RM2 - 12;
586 srcreg = REG_E0 + RM2;
588 if (RN0 > 7 && RN0 < 12)
589 dstreg = REG_A0 + RN0 - 8;
590 else if (RN0 > 11 && RN0 < 16)
591 dstreg = REG_D0 + RN0 - 12;
593 dstreg = REG_E0 + RN0;
595 reg1 = State.regs[srcreg];
596 reg2 = State.regs[dstreg];
597 sum = reg1 + reg2 + ((PSW & PSW_C) != 0);
598 State.regs[dstreg] = sum;
601 n = (sum & 0x80000000);
602 c = (sum < reg1) || (sum < reg2);
603 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
604 && (reg2 & 0x80000000) != (sum & 0x80000000));
606 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
607 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
608 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
611 // 1111 1001 1001 1000 Rm Rn; sub Rm,Rn
612 8.0xf9+8.0x98+4.RM2,4.RN0:D1b:::sub
620 if (RM2 > 7 && RM2 < 12)
621 srcreg = REG_A0 + RM2 - 8;
622 else if (RM2 > 11 && RM2 < 16)
623 srcreg = REG_D0 + RM2 - 12;
625 srcreg = REG_E0 + RM2;
627 if (RN0 > 7 && RN0 < 12)
628 dstreg = REG_A0 + RN0 - 8;
629 else if (RN0 > 11 && RN0 < 16)
630 dstreg = REG_D0 + RN0 - 12;
632 dstreg = REG_E0 + RN0;
634 genericSub (State.regs[srcreg], dstreg);
637 // 1111 1001 1010 1000 Rm Rn; subc Rm,Rn
638 8.0xf9+8.0xa8+4.RM2,4.RN0:D1b:::subc
644 unsigned long reg1, reg2, difference;
648 if (RM2 > 7 && RM2 < 12)
649 srcreg = REG_A0 + RM2 - 8;
650 else if (RM2 > 11 && RM2 < 16)
651 srcreg = REG_D0 + RM2 - 12;
653 srcreg = REG_E0 + RM2;
655 if (RN0 > 7 && RN0 < 12)
656 dstreg = REG_A0 + RN0 - 8;
657 else if (RN0 > 11 && RN0 < 16)
658 dstreg = REG_D0 + RN0 - 12;
660 dstreg = REG_E0 + RN0;
662 reg1 = State.regs[srcreg];
663 reg2 = State.regs[dstreg];
664 difference = reg2 - reg1 - ((PSW & PSW_C) != 0);
665 State.regs[dstreg] = difference;
667 z = (difference == 0);
668 n = (difference & 0x80000000);
670 v = ((reg2 & 0x80000000) == (reg1 & 0x80000000)
671 && (reg2 & 0x80000000) != (difference & 0x80000000));
673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
674 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
675 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
678 // 1111 1001 1011 1000 Rn Rn; inc Rn
679 8.0xf9+8.0xb8+4.RN0,4.RN2=RN0:D1:::inc
687 if (RN0 > 7 && RN0 < 12)
688 dstreg = REG_A0 + RN0 - 8;
689 else if (RN0 > 11 && RN0 < 16)
690 dstreg = REG_D0 + RN0 - 12;
692 dstreg = REG_E0 + RN0;
694 genericAdd (1, dstreg);
697 // 1111 1001 1101 1000 Rn Rn; inc Rn
698 8.0xf9+8.0xc8+4.RN0,4.RN2=RN0:D1:::inc4
706 if (RN0 > 7 && RN0 < 12)
707 dstreg = REG_A0 + RN0 - 8;
708 else if (RN0 > 11 && RN0 < 16)
709 dstreg = REG_D0 + RN0 - 12;
711 dstreg = REG_E0 + RN0;
712 State.regs[dstreg] += 4;
715 // 1111 1001 1101 1000 Rm Rn; cmp Rm,Rn
716 8.0xf9+8.0xd8+4.RM2,4.RN0:D1:::cmp
720 int srcreg1, srcreg2;
724 if (RN0 > 7 && RN0 < 12)
725 srcreg1 = REG_A0 + RN0 - 8;
726 else if (RN0 > 11 && RN0 < 16)
727 srcreg1 = REG_D0 + RN0 - 12;
729 srcreg1 = REG_E0 + RN0;
731 if (RM2 > 7 && RM2 < 12)
732 srcreg2 = REG_A0 + RM2 - 8;
733 else if (RM2 > 11 && RM2 < 16)
734 srcreg2 = REG_D0 + RM2 - 12;
736 srcreg2 = REG_E0 + RM2;
737 genericCmp (State.regs[srcreg2], State.regs[srcreg1]);
740 // 1111 1001 1110 1000 XRm Rn; mov XRm,Rn
741 8.0xf9+8.0xe8+4.XRM2,4.RN0:D1l:::mov
748 if (RN0 > 7 && RN0 < 12)
749 dstreg = REG_A0 + RN0 - 8;
750 else if (RN0 > 11 && RN0 < 16)
751 dstreg = REG_D0 + RN0 - 12;
753 dstreg = REG_E0 + RN0;
757 State.regs[dstreg] = State.regs[REG_SP];
763 // 1111 1001 1111 1000 Rm XRn; mov Rm,XRn
764 8.0xf9+8.0xf8+4.RM2,4.XRN0:D1m:::mov
772 if (RM2 > 7 && RM2 < 12)
773 srcreg = REG_A0 + RM2 - 8;
774 else if (RM2 > 11 && RM2 < 16)
775 srcreg = REG_D0 + RM2 - 12;
777 srcreg = REG_E0 + RM2;
781 State.regs[REG_SP] = State.regs[srcreg];
787 // 1111 1001 0000 1001 Rm Rn; and Rm,Rn
788 8.0xf9+8.0x09+4.RM2,4.RN0:D1a:::and
797 if (RM2 > 7 && RM2 < 12)
798 srcreg = REG_A0 + RM2 - 8;
799 else if (RM2 > 11 && RM2 < 16)
800 srcreg = REG_D0 + RM2 - 12;
802 srcreg = REG_E0 + RM2;
804 if (RN0 > 7 && RN0 < 12)
805 dstreg = REG_A0 + RN0 - 8;
806 else if (RN0 > 11 && RN0 < 16)
807 dstreg = REG_D0 + RN0 - 12;
809 dstreg = REG_E0 + RN0;
811 State.regs[dstreg] &= State.regs[srcreg];
812 z = (State.regs[dstreg] == 0);
813 n = (State.regs[dstreg] & 0x80000000) != 0;
814 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
815 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
818 // 1111 1001 0001 1001 Rm Rn; or Rm,Rn
819 8.0xf9+8.0x19+4.RM2,4.RN0:D1a:::or
828 if (RM2 > 7 && RM2 < 12)
829 srcreg = REG_A0 + RM2 - 8;
830 else if (RM2 > 11 && RM2 < 16)
831 srcreg = REG_D0 + RM2 - 12;
833 srcreg = REG_E0 + RM2;
835 if (RN0 > 7 && RN0 < 12)
836 dstreg = REG_A0 + RN0 - 8;
837 else if (RN0 > 11 && RN0 < 16)
838 dstreg = REG_D0 + RN0 - 12;
840 dstreg = REG_E0 + RN0;
842 State.regs[dstreg] |= State.regs[srcreg];
843 z = (State.regs[dstreg] == 0);
844 n = (State.regs[dstreg] & 0x80000000) != 0;
845 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
846 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
849 // 1111 1001 0010 1001 Rm Rn; xor Rm,Rn
850 8.0xf9+8.0x29+4.RM2,4.RN0:D1a:::xor
859 if (RM2 > 7 && RM2 < 12)
860 srcreg = REG_A0 + RM2 - 8;
861 else if (RM2 > 11 && RM2 < 16)
862 srcreg = REG_D0 + RM2 - 12;
864 srcreg = REG_E0 + RM2;
866 if (RN0 > 7 && RN0 < 12)
867 dstreg = REG_A0 + RN0 - 8;
868 else if (RN0 > 11 && RN0 < 16)
869 dstreg = REG_D0 + RN0 - 12;
871 dstreg = REG_E0 + RN0;
873 State.regs[dstreg] ^= State.regs[srcreg];
874 z = (State.regs[dstreg] == 0);
875 n = (State.regs[dstreg] & 0x80000000) != 0;
876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
877 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
880 // 1111 1001 0011 1001 Rn Rn; not Rn
881 8.0xf9+8.0x39+4.RM2,4.RN0=RM2:D1:::not
890 if (RN0 > 7 && RN0 < 12)
891 dstreg = REG_A0 + RN0 - 8;
892 else if (RN0 > 11 && RN0 < 16)
893 dstreg = REG_D0 + RN0 - 12;
895 dstreg = REG_E0 + RN0;
897 State.regs[dstreg] = ~State.regs[dstreg];
898 z = (State.regs[dstreg] == 0);
899 n = (State.regs[dstreg] & 0x80000000) != 0;
900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
904 // 1111 1001 0100 1001 Rm Rn; asr Rm,Rn
905 8.0xf9+8.0x49+4.RM2,4.RN0:D1a:::asr
915 if (RM2 > 7 && RM2 < 12)
916 srcreg = REG_A0 + RM2 - 8;
917 else if (RM2 > 11 && RM2 < 16)
918 srcreg = REG_D0 + RM2 - 12;
920 srcreg = REG_E0 + RM2;
922 if (RN0 > 7 && RN0 < 12)
923 dstreg = REG_A0 + RN0 - 8;
924 else if (RN0 > 11 && RN0 < 16)
925 dstreg = REG_D0 + RN0 - 12;
927 dstreg = REG_E0 + RN0;
929 temp = State.regs[dstreg];
931 temp >>= State.regs[srcreg];
932 State.regs[dstreg] = temp;
933 z = (State.regs[dstreg] == 0);
934 n = (State.regs[dstreg] & 0x80000000) != 0;
935 PSW &= ~(PSW_Z | PSW_N | PSW_C);
936 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
939 // 1111 1001 0101 1001 Rm Rn; lsr Rm,Rn
940 8.0xf9+8.0x59+4.RM2,4.RN0:D1a:::lsr
949 if (RM2 > 7 && RM2 < 12)
950 srcreg = REG_A0 + RM2 - 8;
951 else if (RM2 > 11 && RM2 < 16)
952 srcreg = REG_D0 + RM2 - 12;
954 srcreg = REG_E0 + RM2;
956 if (RN0 > 7 && RN0 < 12)
957 dstreg = REG_A0 + RN0 - 8;
958 else if (RN0 > 11 && RN0 < 16)
959 dstreg = REG_D0 + RN0 - 12;
961 dstreg = REG_E0 + RN0;
963 c = State.regs[dstreg] & 1;
964 State.regs[dstreg] >>= State.regs[srcreg];
965 z = (State.regs[dstreg] == 0);
966 n = (State.regs[dstreg] & 0x80000000) != 0;
967 PSW &= ~(PSW_Z | PSW_N | PSW_C);
968 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
971 // 1111 1001 0110 1001 Rm Rn; asl Rm,Rn
972 8.0xf9+8.0x69+4.RM2,4.RN0:D1a:::asl
981 if (RM2 > 7 && RM2 < 12)
982 srcreg = REG_A0 + RM2 - 8;
983 else if (RM2 > 11 && RM2 < 16)
984 srcreg = REG_D0 + RM2 - 12;
986 srcreg = REG_E0 + RM2;
988 if (RN0 > 7 && RN0 < 12)
989 dstreg = REG_A0 + RN0 - 8;
990 else if (RN0 > 11 && RN0 < 16)
991 dstreg = REG_D0 + RN0 - 12;
993 dstreg = REG_E0 + RN0;
995 State.regs[dstreg] <<= State.regs[srcreg];
996 z = (State.regs[dstreg] == 0);
997 n = (State.regs[dstreg] & 0x80000000) != 0;
998 PSW &= ~(PSW_Z | PSW_N);
999 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1002 // 1111 1001 0111 1001 Rn Rn; asl2 Rn
1003 8.0xf9+8.0x79+4.RM2,4.RN0=RM2:D1:::asl2
1012 if (RN0 > 7 && RN0 < 12)
1013 dstreg = REG_A0 + RN0 - 8;
1014 else if (RN0 > 11 && RN0 < 16)
1015 dstreg = REG_D0 + RN0 - 12;
1017 dstreg = REG_E0 + RN0;
1019 State.regs[dstreg] <<= 2;
1020 z = (State.regs[dstreg] == 0);
1021 n = (State.regs[dstreg] & 0x80000000) != 0;
1022 PSW &= ~(PSW_Z | PSW_N);
1023 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1026 // 1111 1001 1000 1001 Rn Rn; ror Rn
1027 8.0xf9+8.0x89+4.RM2,4.RN0=RM2:D1:::ror
1033 unsigned long value;
1037 if (RN0 > 7 && RN0 < 12)
1038 dstreg = REG_A0 + RN0 - 8;
1039 else if (RN0 > 11 && RN0 < 16)
1040 dstreg = REG_D0 + RN0 - 12;
1042 dstreg = REG_E0 + RN0;
1044 value = State.regs[dstreg];
1048 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1049 State.regs[dstreg] = value;
1051 n = (value & 0x80000000) != 0;
1052 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1053 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1056 // 1111 1001 1001 1001 Rn Rn; rol Rn
1057 8.0xf9+8.0x99+4.RM2,4.RN0=RM2:D1:::rol
1063 unsigned long value;
1067 if (RN0 > 7 && RN0 < 12)
1068 dstreg = REG_A0 + RN0 - 8;
1069 else if (RN0 > 11 && RN0 < 16)
1070 dstreg = REG_D0 + RN0 - 12;
1072 dstreg = REG_E0 + RN0;
1074 value = State.regs[dstreg];
1075 c = (value & 0x80000000) ? 1 : 0;
1078 value |= ((PSW & PSW_C) != 0);
1079 State.regs[dstreg] = value;
1081 n = (value & 0x80000000) != 0;
1082 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1083 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1086 // 1111 1001 1010 1001 Rm Rn; mul Rm,Rn
1087 8.0xf9+8.0xa9+4.RM2,4.RN0:D1b:::mul
1092 unsigned long long temp;
1097 if (RM2 > 7 && RM2 < 12)
1098 srcreg = REG_A0 + RM2 - 8;
1099 else if (RM2 > 11 && RM2 < 16)
1100 srcreg = REG_D0 + RM2 - 12;
1102 srcreg = REG_E0 + RM2;
1104 if (RN0 > 7 && RN0 < 12)
1105 dstreg = REG_A0 + RN0 - 8;
1106 else if (RN0 > 11 && RN0 < 16)
1107 dstreg = REG_D0 + RN0 - 12;
1109 dstreg = REG_E0 + RN0;
1111 temp = ((signed64)(signed32)State.regs[dstreg]
1112 * (signed64)(signed32)State.regs[srcreg]);
1113 State.regs[dstreg] = temp & 0xffffffff;
1114 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1115 z = (State.regs[dstreg] == 0);
1116 n = (State.regs[dstreg] & 0x80000000) != 0;
1117 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1118 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1121 // 1111 1001 1011 1001 Rm Rn; mulu Rm,Rn
1122 8.0xf9+8.0xb9+4.RM2,4.RN0:D1b:::mulu
1127 unsigned long long temp;
1132 if (RM2 > 7 && RM2 < 12)
1133 srcreg = REG_A0 + RM2 - 8;
1134 else if (RM2 > 11 && RM2 < 16)
1135 srcreg = REG_D0 + RM2 - 12;
1137 srcreg = REG_E0 + RM2;
1139 if (RN0 > 7 && RN0 < 12)
1140 dstreg = REG_A0 + RN0 - 8;
1141 else if (RN0 > 11 && RN0 < 16)
1142 dstreg = REG_D0 + RN0 - 12;
1144 dstreg = REG_E0 + RN0;
1146 temp = ((unsigned64)State.regs[dstreg]
1147 * (unsigned64)State.regs[srcreg]);
1148 State.regs[dstreg] = temp & 0xffffffff;
1149 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1150 z = (State.regs[dstreg] == 0);
1151 n = (State.regs[dstreg] & 0x80000000) != 0;
1152 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1153 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1156 // 1111 1001 1100 1001 Rm Rn; div Rm,Rn
1157 8.0xf9+8.0xc9+4.RM2,4.RN0:D1b:::div
1162 unsigned long long temp;
1167 if (RM2 > 7 && RM2 < 12)
1168 srcreg = REG_A0 + RM2 - 8;
1169 else if (RM2 > 11 && RM2 < 16)
1170 srcreg = REG_D0 + RM2 - 12;
1172 srcreg = REG_E0 + RM2;
1174 if (RN0 > 7 && RN0 < 12)
1175 dstreg = REG_A0 + RN0 - 8;
1176 else if (RN0 > 11 && RN0 < 16)
1177 dstreg = REG_D0 + RN0 - 12;
1179 dstreg = REG_E0 + RN0;
1181 temp = State.regs[REG_MDR];
1183 temp |= State.regs[dstreg];
1184 State.regs[REG_MDR] = temp % (long)State.regs[srcreg];
1185 temp /= (long)State.regs[srcreg];
1186 State.regs[dstreg] = temp & 0xffffffff;
1187 z = (State.regs[dstreg] == 0);
1188 n = (State.regs[dstreg] & 0x80000000) != 0;
1189 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1190 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1193 // 1111 1001 1101 1001 Rm Rn; divu Rm,Rn
1194 8.0xf9+8.0xd9+4.RM2,4.RN0:D1b:::divu
1199 unsigned long long temp;
1204 if (RM2 > 7 && RM2 < 12)
1205 srcreg = REG_A0 + RM2 - 8;
1206 else if (RM2 > 11 && RM2 < 16)
1207 srcreg = REG_D0 + RM2 - 12;
1209 srcreg = REG_E0 + RM2;
1211 if (RN0 > 7 && RN0 < 12)
1212 dstreg = REG_A0 + RN0 - 8;
1213 else if (RN0 > 11 && RN0 < 16)
1214 dstreg = REG_D0 + RN0 - 12;
1216 dstreg = REG_E0 + RN0;
1218 temp = State.regs[REG_MDR];
1220 temp |= State.regs[dstreg];
1221 State.regs[REG_MDR] = temp % State.regs[srcreg];
1222 temp /= State.regs[srcreg];
1223 State.regs[dstreg] = temp & 0xffffffff;
1224 z = (State.regs[dstreg] == 0);
1225 n = (State.regs[dstreg] & 0x80000000) != 0;
1226 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1227 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1231 // 1111 1001 0000 1010 Rm Rn; mov (Rm),Rn
1232 8.0xf9+8.0x0a+4.RN2,4.RM0:D1h:::mov
1240 if (RM0 > 7 && RM0 < 12)
1241 srcreg = REG_A0 + RM0 - 8;
1242 else if (RM0 > 11 && RM0 < 16)
1243 srcreg = REG_D0 + RM0 - 12;
1245 srcreg = REG_E0 + RM0;
1247 if (RN2 > 7 && RN2 < 12)
1248 dstreg = REG_A0 + RN2 - 8;
1249 else if (RN2 > 11 && RN2 < 16)
1250 dstreg = REG_D0 + RN2 - 12;
1252 dstreg = REG_E0 + RN2;
1254 State.regs[dstreg] = load_word (State.regs[srcreg]);
1257 // 1111 1001 0001 1010 Rm Rn; mov Rm,(Rn)
1258 8.0xf9+8.0x1a+4.RM2,4.RN0:D1i:::mov
1266 if (RM2 > 7 && RM2 < 12)
1267 srcreg = REG_A0 + RM2 - 8;
1268 else if (RM2 > 11 && RM2 < 16)
1269 srcreg = REG_D0 + RM2 - 12;
1271 srcreg = REG_E0 + RM2;
1273 if (RN0 > 7 && RN0 < 12)
1274 dstreg = REG_A0 + RN0 - 8;
1275 else if (RN0 > 11 && RN0 < 16)
1276 dstreg = REG_D0 + RN0 - 12;
1278 dstreg = REG_E0 + RN0;
1280 store_word (State.regs[dstreg], State.regs[srcreg]);
1283 // 1111 1001 0010 1010 Rm Rn; movbu (Rm),Rn
1284 8.0xf9+8.0x2a+4.RN2,4.RM0:D1g:::movbu
1292 if (RM0 > 7 && RM0 < 12)
1293 srcreg = REG_A0 + RM0 - 8;
1294 else if (RM0 > 11 && RM0 < 16)
1295 srcreg = REG_D0 + RM0 - 12;
1297 srcreg = REG_E0 + RM0;
1299 if (RN2 > 7 && RN2 < 12)
1300 dstreg = REG_A0 + RN2 - 8;
1301 else if (RN2 > 11 && RN2 < 16)
1302 dstreg = REG_D0 + RN2 - 12;
1304 dstreg = REG_E0 + RN2;
1306 State.regs[dstreg] = load_byte (State.regs[srcreg]);
1309 // 1111 1001 0011 1010 Rm Rn; movbu Rm,(Rn)
1310 8.0xf9+8.0x3a+4.RM2,4.RN0:D1i:::movbu
1318 if (RM2 > 7 && RM2 < 12)
1319 srcreg = REG_A0 + RM2 - 8;
1320 else if (RM2 > 11 && RM2 < 16)
1321 srcreg = REG_D0 + RM2 - 12;
1323 srcreg = REG_E0 + RM2;
1325 if (RN0 > 7 && RN0 < 12)
1326 dstreg = REG_A0 + RN0 - 8;
1327 else if (RN0 > 11 && RN0 < 16)
1328 dstreg = REG_D0 + RN0 - 12;
1330 dstreg = REG_E0 + RN0;
1332 store_byte (State.regs[dstreg], State.regs[srcreg]);
1335 // 1111 1001 0100 1010 Rm Rn; movhu (Rm),Rn
1336 8.0xf9+8.0x4a+4.RN2,4.RM0:D1g:::movhu
1344 if (RM0 > 7 && RM0 < 12)
1345 srcreg = REG_A0 + RM0 - 8;
1346 else if (RM0 > 11 && RM0 < 16)
1347 srcreg = REG_D0 + RM0 - 12;
1349 srcreg = REG_E0 + RM0;
1351 if (RN2 > 7 && RN2 < 12)
1352 dstreg = REG_A0 + RN2 - 8;
1353 else if (RN2 > 11 && RN2 < 16)
1354 dstreg = REG_D0 + RN2 - 12;
1356 dstreg = REG_E0 + RN2;
1358 State.regs[dstreg] = load_half (State.regs[srcreg]);
1361 // 1111 1001 0101 1010 Rm Rn; movhu Rm,(Rn)
1362 8.0xf9+8.0x5a+4.RM2,4.RN0:D1i:::movhu
1370 if (RM2 > 7 && RM2 < 12)
1371 srcreg = REG_A0 + RM2 - 8;
1372 else if (RM2 > 11 && RM2 < 16)
1373 srcreg = REG_D0 + RM2 - 12;
1375 srcreg = REG_E0 + RM2;
1377 if (RN0 > 7 && RN0 < 12)
1378 dstreg = REG_A0 + RN0 - 8;
1379 else if (RN0 > 11 && RN0 < 16)
1380 dstreg = REG_D0 + RN0 - 12;
1382 dstreg = REG_E0 + RN0;
1384 store_half (State.regs[dstreg], State.regs[srcreg]);
1390 // 1111 1001 1000 1010 Rn 0000; mov (sp),Rn
1391 8.0xf9+8.0x8a+4.RN2,4.0000:D1j:::mov
1399 if (RN2 > 7 && RN2 < 12)
1400 dstreg = REG_A0 + RN2 - 8;
1401 else if (RN2 > 11 && RN2 < 16)
1402 dstreg = REG_D0 + RN2 - 12;
1404 dstreg = REG_E0 + RN2;
1406 State.regs[dstreg] = load_word (State.regs[REG_SP]);
1409 // 1111 1001 1001 1010 Rm 0000; mov Rm, (sp)
1410 8.0xf9+8.0x9a+4.RM2,4.0000:D1k:::mov
1418 if (RM2 > 7 && RM2 < 12)
1419 dstreg = REG_A0 + RM2 - 8;
1420 else if (RM2 > 11 && RM2 < 16)
1421 dstreg = REG_D0 + RM2 - 12;
1423 dstreg = REG_E0 + RM2;
1425 store_word (State.regs[REG_SP], State.regs[dstreg]);
1428 // 1111 1001 1010 1010 Rn 0000; mobvu (sp),Rn
1429 8.0xf9+8.0xaa+4.RN2,4.0000:D1j:::movbu
1437 if (RN2 > 7 && RN2 < 12)
1438 dstreg = REG_A0 + RN2 - 8;
1439 else if (RN2 > 11 && RN2 < 16)
1440 dstreg = REG_D0 + RN2 - 12;
1442 dstreg = REG_E0 + RN2;
1444 State.regs[dstreg] = load_byte (State.regs[REG_SP]);
1447 // 1111 1001 1011 1010 Rm 0000; movbu Rm, (sp)
1448 8.0xf9+8.0xba+4.RM2,4.0000:D1k:::movbu
1456 if (RM2 > 7 && RM2 < 12)
1457 dstreg = REG_A0 + RM2 - 8;
1458 else if (RM2 > 11 && RM2 < 16)
1459 dstreg = REG_D0 + RM2 - 12;
1461 dstreg = REG_E0 + RM2;
1463 store_byte (State.regs[REG_SP], State.regs[dstreg]);
1466 // 1111 1001 1000 1100 Rn 0000; movhu (sp),Rn
1467 8.0xf9+8.0xca+4.RN2,4.0000:D1j:::movhu
1475 if (RN2 > 7 && RN2 < 12)
1476 dstreg = REG_A0 + RN2 - 8;
1477 else if (RN2 > 11 && RN2 < 16)
1478 dstreg = REG_D0 + RN2 - 12;
1480 dstreg = REG_E0 + RN2;
1482 State.regs[dstreg] = load_half (State.regs[REG_SP]);
1485 // 1111 1001 1001 1101 Rm 0000; movhu Rm, (sp)
1486 8.0xf9+8.0xda+4.RM2,4.0000:D1k:::movhu
1494 if (RM2 > 7 && RM2 < 12)
1495 dstreg = REG_A0 + RM2 - 8;
1496 else if (RM2 > 11 && RM2 < 16)
1497 dstreg = REG_D0 + RM2 - 12;
1499 dstreg = REG_E0 + RM2;
1501 store_half (State.regs[REG_SP], State.regs[dstreg]);
1521 // 1111 1011 0000 1000 Rn Rn IMM8; mov IMM8,Rn
1522 8.0xfb+8.0x08+4.RM2,4.RN0=RM2+8.IMM8:D2j:::mov
1530 if (RN0 > 7 && RN0 < 12)
1531 dstreg = REG_A0 + RN0 - 8;
1532 else if (RN0 > 11 && RN0 < 16)
1533 dstreg = REG_D0 + RN0 - 12;
1535 dstreg = REG_E0 + RN0;
1537 State.regs[dstreg] = EXTEND8 (IMM8);
1540 // 1111 1011 0001 1000 Rn Rn IMM8; movu IMM8,Rn
1541 8.0xfb+8.0x18+4.RM2,4.RN0=RM2+8.IMM8:D2:::movu
1549 if (RN0 > 7 && RN0 < 12)
1550 dstreg = REG_A0 + RN0 - 8;
1551 else if (RN0 > 11 && RN0 < 16)
1552 dstreg = REG_D0 + RN0 - 12;
1554 dstreg = REG_E0 + RN0;
1556 State.regs[dstreg] = IMM8 & 0xff;
1559 // 1111 1011 0111 1000 Rn Rn IMM8; add IMM8,Rn
1560 8.0xfb+8.0x78+4.RM2,4.RN0=RM2+8.IMM8:D2d:::add
1568 if (RN0 > 7 && RN0 < 12)
1569 dstreg = REG_A0 + RN0 - 8;
1570 else if (RN0 > 11 && RN0 < 16)
1571 dstreg = REG_D0 + RN0 - 12;
1573 dstreg = REG_E0 + RN0;
1575 genericAdd (EXTEND8 (IMM8), dstreg);
1578 // 1111 1011 1000 1000 Rn Rn IMM8; addc IMM8,Rn
1579 8.0xfb+8.0x88+4.RM2,4.RN0=RM2+8.IMM8:D2d:::addc
1585 unsigned long reg1, reg2, sum;
1589 if (RN0 > 7 && RN0 < 12)
1590 dstreg = REG_A0 + RN0 - 8;
1591 else if (RN0 > 11 && RN0 < 16)
1592 dstreg = REG_D0 + RN0 - 12;
1594 dstreg = REG_E0 + RN0;
1596 imm = EXTEND8 (IMM8);
1597 reg2 = State.regs[dstreg];
1598 sum = imm + reg2 + ((PSW & PSW_C) != 0);
1599 State.regs[dstreg] = sum;
1602 n = (sum & 0x80000000);
1603 c = (sum < imm) || (sum < reg2);
1604 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1605 && (reg2 & 0x80000000) != (sum & 0x80000000));
1607 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1608 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1609 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1612 // 1111 1011 1001 1000 Rn Rn IMM8; sub IMM8,Rn
1613 8.0xfb+8.0x98+4.RM2,4.RN0=RM2+8.IMM8:D2d:::sub
1621 if (RN0 > 7 && RN0 < 12)
1622 dstreg = REG_A0 + RN0 - 8;
1623 else if (RN0 > 11 && RN0 < 16)
1624 dstreg = REG_D0 + RN0 - 12;
1626 dstreg = REG_E0 + RN0;
1628 genericSub (EXTEND8 (IMM8), dstreg);
1631 // 1111 1011 1010 1000 Rn Rn IMM8; subc IMM8,Rn
1632 8.0xfb+8.0xa8+4.RM2,4.RN0=RM2+8.IMM8:D2d:::subc
1638 unsigned long reg1, reg2, difference;
1642 if (RN0 > 7 && RN0 < 12)
1643 dstreg = REG_A0 + RN0 - 8;
1644 else if (RN0 > 11 && RN0 < 16)
1645 dstreg = REG_D0 + RN0 - 12;
1647 dstreg = REG_E0 + RN0;
1649 imm = EXTEND8 (IMM8);
1650 reg2 = State.regs[dstreg];
1651 difference = reg2 - imm - ((PSW & PSW_C) != 0);
1652 State.regs[dstreg] = difference;
1654 z = (difference == 0);
1655 n = (difference & 0x80000000);
1657 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
1658 && (reg2 & 0x80000000) != (difference & 0x80000000));
1660 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1661 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1662 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1665 // 1111 1011 1101 1000 Rn Rn IMM8; cmp IMM8,Rn
1666 8.0xfb+8.0xd8+4.RM2,4.RN0=RM2+8.IMM8:D2b:::cmp
1674 if (RN0 > 7 && RN0 < 12)
1675 srcreg = REG_A0 + RN0 - 8;
1676 else if (RN0 > 11 && RN0 < 16)
1677 srcreg = REG_D0 + RN0 - 12;
1679 srcreg = REG_E0 + RN0;
1681 genericCmp (EXTEND8 (IMM8), State.regs[srcreg]);
1684 // 1111 1011 1111 1000 XRn XRn IMM8; mov IMM8,XRn
1685 8.0xfb+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM8:D2k:::mov
1694 State.regs[REG_SP] = EXTEND8 (IMM8);
1699 // 1111 1011 0000 1001 Rn Rn IMM8; and IMM8,Rn
1700 8.0xfb+8.0x09+4.RM2,4.RN0=RM2+8.IMM8:D2d:::and
1709 if (RN0 > 7 && RN0 < 12)
1710 dstreg = REG_A0 + RN0 - 8;
1711 else if (RN0 > 11 && RN0 < 16)
1712 dstreg = REG_D0 + RN0 - 12;
1714 dstreg = REG_E0 + RN0;
1716 State.regs[dstreg] &= (IMM8 & 0xff);
1717 z = (State.regs[dstreg] == 0);
1718 n = (State.regs[dstreg] & 0x80000000) != 0;
1719 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1720 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1723 // 1111 1011 0001 1001 Rn Rn IMM8; or IMM8,Rn
1724 8.0xfb+8.0x19+4.RM2,4.RN0=RM2+8.IMM8:D2d:::or
1733 if (RN0 > 7 && RN0 < 12)
1734 dstreg = REG_A0 + RN0 - 8;
1735 else if (RN0 > 11 && RN0 < 16)
1736 dstreg = REG_D0 + RN0 - 12;
1738 dstreg = REG_E0 + RN0;
1740 State.regs[dstreg] |= (IMM8 & 0xff);
1741 z = (State.regs[dstreg] == 0);
1742 n = (State.regs[dstreg] & 0x80000000) != 0;
1743 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1747 // 1111 1011 0010 1001 Rn Rn IMM8; xor IMM8,Rn
1748 8.0xfb+8.0x29+4.RM2,4.RN0=RM2+8.IMM8:D2d:::xor
1757 if (RN0 > 7 && RN0 < 12)
1758 dstreg = REG_A0 + RN0 - 8;
1759 else if (RN0 > 11 && RN0 < 16)
1760 dstreg = REG_D0 + RN0 - 12;
1762 dstreg = REG_E0 + RN0;
1764 State.regs[dstreg] ^= (IMM8 & 0xff);
1765 z = (State.regs[dstreg] == 0);
1766 n = (State.regs[dstreg] & 0x80000000) != 0;
1767 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1771 // 1111 1011 0100 1001 Rn Rn IMM8; asr IMM8,Rn
1772 8.0xfb+8.0x49+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asr
1782 if (RN0 > 7 && RN0 < 12)
1783 dstreg = REG_A0 + RN0 - 8;
1784 else if (RN0 > 11 && RN0 < 16)
1785 dstreg = REG_D0 + RN0 - 12;
1787 dstreg = REG_E0 + RN0;
1789 temp = State.regs[dstreg];
1791 temp >>= (IMM8 & 0xff);
1792 State.regs[dstreg] = temp;
1793 z = (State.regs[dstreg] == 0);
1794 n = (State.regs[dstreg] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1799 // 1111 1011 0101 1001 Rn Rn IMM8; lsr IMM8,Rn
1800 8.0xfb+8.0x59+4.RM2,4.RN0=RM2+8.IMM8:D2a:::lsr
1809 if (RN0 > 7 && RN0 < 12)
1810 dstreg = REG_A0 + RN0 - 8;
1811 else if (RN0 > 11 && RN0 < 16)
1812 dstreg = REG_D0 + RN0 - 12;
1814 dstreg = REG_E0 + RN0;
1816 c = State.regs[dstreg] & 1;
1817 State.regs[dstreg] >>= (IMM8 & 0xff);
1818 z = (State.regs[dstreg] == 0);
1819 n = (State.regs[dstreg] & 0x80000000) != 0;
1820 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1821 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1824 // 1111 1011 0110 1001 Rn Rn IMM8; asl IMM8,Rn
1825 8.0xfb+8.0x69+4.RM2,4.RN0=RM2+8.IMM8:D2a:::asl
1834 if (RN0 > 7 && RN0 < 12)
1835 dstreg = REG_A0 + RN0 - 8;
1836 else if (RN0 > 11 && RN0 < 16)
1837 dstreg = REG_D0 + RN0 - 12;
1839 dstreg = REG_E0 + RN0;
1841 State.regs[dstreg] <<= (IMM8 & 0xff);
1842 z = (State.regs[dstreg] == 0);
1843 n = (State.regs[dstreg] & 0x80000000) != 0;
1844 PSW &= ~(PSW_Z | PSW_N);
1845 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1848 // 1111 1011 1010 1001 Rn Rn IMM8; mul IMM8,Rn
1849 8.0xfb+8.0xa9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mul
1854 unsigned long long temp;
1859 if (RN0 > 7 && RN0 < 12)
1860 dstreg = REG_A0 + RN0 - 8;
1861 else if (RN0 > 11 && RN0 < 16)
1862 dstreg = REG_D0 + RN0 - 12;
1864 dstreg = REG_E0 + RN0;
1866 temp = ((signed64)(signed32)State.regs[dstreg]
1867 * (signed64)(signed32)EXTEND8 (IMM8));
1868 State.regs[dstreg] = temp & 0xffffffff;
1869 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;;
1870 z = (State.regs[dstreg] == 0);
1871 n = (State.regs[dstreg] & 0x80000000) != 0;
1872 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1873 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1876 // 1111 1011 1011 1001 Rn Rn IMM8; mulu IMM8,Rn
1877 8.0xfb+8.0xb9+4.RM2,4.RN0=RM2+8.IMM8:D2a:::mulu
1882 unsigned long long temp;
1887 if (RN0 > 7 && RN0 < 12)
1888 dstreg = REG_A0 + RN0 - 8;
1889 else if (RN0 > 11 && RN0 < 16)
1890 dstreg = REG_D0 + RN0 - 12;
1892 dstreg = REG_E0 + RN0;
1894 temp = ((unsigned64)State.regs[dstreg]
1895 * (unsigned64)(IMM8 & 0xff));
1896 State.regs[dstreg] = temp & 0xffffffff;
1897 State.regs[REG_MDR] = (temp & 0xffffffff00000000LL) >> 32;
1898 z = (State.regs[dstreg] == 0);
1899 n = (State.regs[dstreg] & 0x80000000) != 0;
1900 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1901 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1904 // 1111 1011 1110 1001 Rn Rn IMM8; btst imm8,Rn
1905 8.0xfb+8.0xe9+4.RN2,4.RM0=RN2+8.IMM8:D2l:::btst
1913 if (RM0 > 7 && RM0 < 12)
1914 srcreg = REG_A0 + RM0 - 8;
1915 else if (RM0 > 11 && RM0 < 16)
1916 srcreg = REG_D0 + RM0 - 12;
1918 srcreg = REG_E0 + RM0;
1920 genericBtst(IMM8, State.regs[srcreg]);
1926 // 1111 1011 0000 1010 Rn Rm IMM8; mov (d8,Rm),Rn
1927 8.0xfb+8.0x0a+4.RN2,4.RM0+8.IMM8:D2l:::mov
1935 if (RM0 > 7 && RM0 < 12)
1936 srcreg = REG_A0 + RM0 - 8;
1937 else if (RM0 > 11 && RM0 < 16)
1938 srcreg = REG_D0 + RM0 - 12;
1940 srcreg = REG_E0 + RM0;
1942 if (RN2 > 7 && RN2 < 12)
1943 dstreg = REG_A0 + RN2 - 8;
1944 else if (RN2 > 11 && RN2 < 16)
1945 dstreg = REG_D0 + RN2 - 12;
1947 dstreg = REG_E0 + RN2;
1949 State.regs[dstreg] = load_word (State.regs[srcreg] + EXTEND8 (IMM8));
1952 // 1111 1011 0001 1010 Rn Rm IMM8; mov Rm,(d8,Rn)
1953 8.0xfb+8.0x1a+4.RM2,4.RN0+8.IMM8:D2m:::mov
1960 if (RM2 > 7 && RM2 < 12)
1961 srcreg = REG_A0 + RM2 - 8;
1962 else if (RM2 > 11 && RM2 < 16)
1963 srcreg = REG_D0 + RM2 - 12;
1965 srcreg = REG_E0 + RM2;
1967 if (RN0 > 7 && RN0 < 12)
1968 dstreg = REG_A0 + RN0 - 8;
1969 else if (RN0 > 11 && RN0 < 16)
1970 dstreg = REG_D0 + RN0 - 12;
1972 dstreg = REG_E0 + RN0;
1974 store_word (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
1977 // 1111 1011 0010 1010 Rn Rm IMM8; movbu (d8,Rm),Rn
1978 8.0xfb+8.0x2a+4.RN2,4.RM0+8.IMM8:D2l:::movbu
1985 if (RM0 > 7 && RM0 < 12)
1986 srcreg = REG_A0 + RM0 - 8;
1987 else if (RM0 > 11 && RM0 < 16)
1988 srcreg = REG_D0 + RM0 - 12;
1990 srcreg = REG_E0 + RM0;
1992 if (RN2 > 7 && RN2 < 12)
1993 dstreg = REG_A0 + RN2 - 8;
1994 else if (RN2 > 11 && RN2 < 16)
1995 dstreg = REG_D0 + RN2 - 12;
1997 dstreg = REG_E0 + RN2;
1999 State.regs[dstreg] = load_byte (State.regs[srcreg] + EXTEND8 (IMM8));
2002 // 1111 1011 0011 1010 Rn Rm IMM8; movbu Rm,(d8,Rn)
2003 8.0xfb+8.0x3a+4.RM2,4.RN0+8.IMM8:D2m:::movbu
2010 if (RM2 > 7 && RM2 < 12)
2011 srcreg = REG_A0 + RM2 - 8;
2012 else if (RM2 > 11 && RM2 < 16)
2013 srcreg = REG_D0 + RM2 - 12;
2015 srcreg = REG_E0 + RM2;
2017 if (RN0 > 7 && RN0 < 12)
2018 dstreg = REG_A0 + RN0 - 8;
2019 else if (RN0 > 11 && RN0 < 16)
2020 dstreg = REG_D0 + RN0 - 12;
2022 dstreg = REG_E0 + RN0;
2024 store_byte (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2027 // 1111 1011 0100 1010 Rn Rm IMM8; movhu (d8,Rm),Rn
2028 8.0xfb+8.0x4a+4.RN2,4.RM0+8.IMM8:D2l:::movhu
2035 if (RM0 > 7 && RM0 < 12)
2036 srcreg = REG_A0 + RM0 - 8;
2037 else if (RM0 > 11 && RM0 < 16)
2038 srcreg = REG_D0 + RM0 - 12;
2040 srcreg = REG_E0 + RM0;
2042 if (RN2 > 7 && RN2 < 12)
2043 dstreg = REG_A0 + RN2 - 8;
2044 else if (RN2 > 11 && RN2 < 16)
2045 dstreg = REG_D0 + RN2 - 12;
2047 dstreg = REG_E0 + RN2;
2049 State.regs[dstreg] = load_half (State.regs[srcreg] + EXTEND8 (IMM8));
2052 // 1111 1011 0101 1010 Rn Rm IMM8; movhu Rm,(d8,Rn)
2053 8.0xfb+8.0x5a+4.RM2,4.RN0+8.IMM8:D2m:::movhu
2060 if (RM2 > 7 && RM2 < 12)
2061 srcreg = REG_A0 + RM2 - 8;
2062 else if (RM2 > 11 && RM2 < 16)
2063 srcreg = REG_D0 + RM2 - 12;
2065 srcreg = REG_E0 + RM2;
2067 if (RN0 > 7 && RN0 < 12)
2068 dstreg = REG_A0 + RN0 - 8;
2069 else if (RN0 > 11 && RN0 < 16)
2070 dstreg = REG_D0 + RN0 - 12;
2072 dstreg = REG_E0 + RN0;
2074 store_half (State.regs[dstreg] + EXTEND8 (IMM8), State.regs[srcreg]);
2080 // 1111 1011 1000 1010 Rn 0000 IMM8; mov (d8,sp),Rn
2081 8.0xfb+8.0x8a+4.RN2,4.0x0+8.IMM8:D2n:::mov
2088 if (RN2 > 7 && RN2 < 12)
2089 dstreg = REG_A0 + RN2 - 8;
2090 else if (RN2 > 11 && RN2 < 16)
2091 dstreg = REG_D0 + RN2 - 12;
2093 dstreg = REG_E0 + RN2;
2095 State.regs[dstreg] = load_word (State.regs[REG_SP] + EXTEND8 (IMM8));
2098 // 1111 1011 1001 1010 Rm 0000 IMM8; mov Rm,(d8,Rn)
2099 8.0xfb+8.0x9a+4.RM2,4.0x0+8.IMM8:D2o:::mov
2106 if (RM2 > 7 && RM2 < 12)
2107 srcreg = REG_A0 + RM2 - 8;
2108 else if (RM2 > 11 && RM2 < 16)
2109 srcreg = REG_D0 + RM2 - 12;
2111 srcreg = REG_E0 + RM2;
2113 store_word (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2116 // 1111 1011 1010 1010 Rn Rm IMM8; movbu (d8,sp),Rn
2117 8.0xfb+8.0xaa+4.RN2,4.0x0+8.IMM8:D2n:::movbu
2124 if (RN2 > 7 && RN2 < 12)
2125 dstreg = REG_A0 + RN2 - 8;
2126 else if (RN2 > 11 && RN2 < 16)
2127 dstreg = REG_D0 + RN2 - 12;
2129 dstreg = REG_E0 + RN2;
2131 State.regs[dstreg] = load_byte (State.regs[REG_SP] + EXTEND8 (IMM8));
2134 // 1111 1011 1011 1010 Rn Rm IMM8; movbu Rm,(sp,Rn)
2135 8.0xfb+8.0xba+4.RM2,4.0x0+8.IMM8:D2o:::movbu
2142 if (RM2 > 7 && RM2 < 12)
2143 srcreg = REG_A0 + RM2 - 8;
2144 else if (RM2 > 11 && RM2 < 16)
2145 srcreg = REG_D0 + RM2 - 12;
2147 srcreg = REG_E0 + RM2;
2149 store_byte (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2152 // 1111 1011 1100 1010 Rn Rm IMM8; movhu (d8,sp),Rn
2153 8.0xfb+8.0xca+4.RN2,4.0x0+8.IMM8:D2n:::movhu
2160 if (RN2 > 7 && RN2 < 12)
2161 dstreg = REG_A0 + RN2 - 8;
2162 else if (RN2 > 11 && RN2 < 16)
2163 dstreg = REG_D0 + RN2 - 12;
2165 dstreg = REG_E0 + RN2;
2167 State.regs[dstreg] = load_half (State.regs[REG_SP] + EXTEND8 (IMM8));
2170 // 1111 1011 1101 1010 Rn Rm IMM8; movhu Rm,(d8,sp)
2171 8.0xfb+8.0xda+4.RM2,4.0x0+8.IMM8:D2o:::movhu
2178 if (RM2 > 7 && RM2 < 12)
2179 srcreg = REG_A0 + RM2 - 8;
2180 else if (RM2 > 11 && RM2 < 16)
2181 srcreg = REG_D0 + RM2 - 12;
2183 srcreg = REG_E0 + RM2;
2185 store_half (State.regs[REG_SP] + EXTEND8 (IMM8), State.regs[srcreg]);
2198 // 1111 1011 0111 1100 Rm Rn Rd; add Rm,Rn,Rd
2199 8.0xfb+8.0x7c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::add
2204 unsigned long sum, source1, source2;
2205 int srcreg1, srcreg2, dstreg;
2209 if (RM2 > 7 && RM2 < 12)
2210 srcreg1 = REG_A0 + RM2 - 8;
2211 else if (RM2 > 11 && RM2 < 16)
2212 srcreg1 = REG_D0 + RM2 - 12;
2214 srcreg1 = REG_E0 + RM2;
2216 if (RN0 > 7 && RN0 < 12)
2217 srcreg2 = REG_A0 + RN0 - 8;
2218 else if (RN0 > 11 && RN0 < 16)
2219 srcreg2 = REG_D0 + RN0 - 12;
2221 srcreg2 = REG_E0 + RN0;
2223 if (RD0 > 7 && RD0 < 12)
2224 dstreg = REG_A0 + RD0 - 8;
2225 else if (RD0 > 11 && RD0 < 16)
2226 dstreg = REG_D0 + RD0 - 12;
2228 dstreg = REG_E0 + RD0;
2230 source1 = State.regs[srcreg1];
2231 source2 = State.regs[srcreg2];
2232 sum = source1 + source2;
2233 State.regs[dstreg] = sum;
2236 n = (sum & 0x80000000);
2237 c = (sum < source1) || (sum < source2);
2238 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2239 && (source1 & 0x80000000) != (sum & 0x80000000));
2241 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2242 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2243 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2246 // 1111 1011 1000 1100 Rm Rn Rd; addc Rm,Rn,Rd
2247 8.0xfb+8.0x8c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::addc
2252 unsigned long sum, source1, source2;
2253 int srcreg1, srcreg2, dstreg;
2257 if (RM2 > 7 && RM2 < 12)
2258 srcreg1 = REG_A0 + RM2 - 8;
2259 else if (RM2 > 11 && RM2 < 16)
2260 srcreg1 = REG_D0 + RM2 - 12;
2262 srcreg1 = REG_E0 + RM2;
2264 if (RN0 > 7 && RN0 < 12)
2265 srcreg2 = REG_A0 + RN0 - 8;
2266 else if (RN0 > 11 && RN0 < 16)
2267 srcreg2 = REG_D0 + RN0 - 12;
2269 srcreg2 = REG_E0 + RN0;
2271 if (RD0 > 7 && RD0 < 12)
2272 dstreg = REG_A0 + RD0 - 8;
2273 else if (RD0 > 11 && RD0 < 16)
2274 dstreg = REG_D0 + RD0 - 12;
2276 dstreg = REG_E0 + RD0;
2278 source1 = State.regs[srcreg1];
2279 source2 = State.regs[srcreg2];
2280 sum = source1 + source2 + ((PSW & PSW_C) != 0);
2281 State.regs[dstreg] = sum;
2284 n = (sum & 0x80000000);
2285 c = (sum < source1) || (sum < source2);
2286 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2287 && (source1 & 0x80000000) != (sum & 0x80000000));
2289 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2290 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2291 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2294 // 1111 1011 1001 1100 Rm Rn Rd; sub Rm,Rn,Rd
2295 8.0xfb+8.0x9c+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::sub
2300 unsigned long difference, source1, source2;
2301 int srcreg1, srcreg2, dstreg;
2305 if (RM2 > 7 && RM2 < 12)
2306 srcreg1 = REG_A0 + RM2 - 8;
2307 else if (RM2 > 11 && RM2 < 16)
2308 srcreg1 = REG_D0 + RM2 - 12;
2310 srcreg1 = REG_E0 + RM2;
2312 if (RN0 > 7 && RN0 < 12)
2313 srcreg2 = REG_A0 + RN0 - 8;
2314 else if (RN0 > 11 && RN0 < 16)
2315 srcreg2 = REG_D0 + RN0 - 12;
2317 srcreg2 = REG_E0 + RN0;
2319 if (RD0 > 7 && RD0 < 12)
2320 dstreg = REG_A0 + RD0 - 8;
2321 else if (RD0 > 11 && RD0 < 16)
2322 dstreg = REG_D0 + RD0 - 12;
2324 dstreg = REG_E0 + RD0;
2326 source1 = State.regs[srcreg1];
2327 source2 = State.regs[srcreg2];
2328 difference = source2 - source1;
2329 State.regs[dstreg] = difference;
2331 z = (difference == 0);
2332 n = (difference & 0x80000000);
2333 c = (source1 > source1);
2334 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2335 && (source1 & 0x80000000) != (difference & 0x80000000));
2337 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2338 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2339 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2342 // 1111 1011 1010 1100 Rm Rn Rd; subc Rm,Rn,Rd
2343 8.0xfb+8.0xac+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::subc
2348 unsigned long difference, source1, source2;
2349 int srcreg1, srcreg2, dstreg;
2353 if (RM2 > 7 && RM2 < 12)
2354 srcreg1 = REG_A0 + RM2 - 8;
2355 else if (RM2 > 11 && RM2 < 16)
2356 srcreg1 = REG_D0 + RM2 - 12;
2358 srcreg1 = REG_E0 + RM2;
2360 if (RN0 > 7 && RN0 < 12)
2361 srcreg2 = REG_A0 + RN0 - 8;
2362 else if (RN0 > 11 && RN0 < 16)
2363 srcreg2 = REG_D0 + RN0 - 12;
2365 srcreg2 = REG_E0 + RN0;
2367 if (RD0 > 7 && RD0 < 12)
2368 dstreg = REG_A0 + RD0 - 8;
2369 else if (RD0 > 11 && RD0 < 16)
2370 dstreg = REG_D0 + RD0 - 12;
2372 dstreg = REG_E0 + RD0;
2374 source1 = State.regs[srcreg1];
2375 source2 = State.regs[srcreg2];
2376 difference = source2 - source1 - ((PSW & PSW_C) != 0);
2377 State.regs[dstreg] = difference;
2379 z = (difference == 0);
2380 n = (difference & 0x80000000);
2381 c = (source1 > source2);
2382 v = ((source1 & 0x80000000) == (source2 & 0x80000000)
2383 && (source1 & 0x80000000) != (difference & 0x80000000));
2385 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2386 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2387 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2390 // 1111 1011 0000 1101 Rm Rn Rd; and Rm,Rn,Rd
2391 8.0xfb+8.0x0d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::and
2396 int srcreg1, srcreg2, dstreg;
2400 if (RM2 > 7 && RM2 < 12)
2401 srcreg1 = REG_A0 + RM2 - 8;
2402 else if (RM2 > 11 && RM2 < 16)
2403 srcreg1 = REG_D0 + RM2 - 12;
2405 srcreg1 = REG_E0 + RM2;
2407 if (RN0 > 7 && RN0 < 12)
2408 srcreg2 = REG_A0 + RN0 - 8;
2409 else if (RN0 > 11 && RN0 < 16)
2410 srcreg2 = REG_D0 + RN0 - 12;
2412 srcreg2 = REG_E0 + RN0;
2414 if (RD0 > 7 && RD0 < 12)
2415 dstreg = REG_A0 + RD0 - 8;
2416 else if (RD0 > 11 && RD0 < 16)
2417 dstreg = REG_D0 + RD0 - 12;
2419 dstreg = REG_E0 + RD0;
2421 State.regs[dstreg] = State.regs[srcreg1] & State.regs[srcreg2];
2423 z = (State.regs[dstreg] == 0);
2424 n = (State.regs[dstreg] & 0x80000000);
2426 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2427 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2430 // 1111 1011 0001 1101 Rm Rn Rd; or Rm,Rn,Rd
2431 8.0xfb+8.0x1d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::or
2436 int srcreg1, srcreg2, dstreg;
2440 if (RM2 > 7 && RM2 < 12)
2441 srcreg1 = REG_A0 + RM2 - 8;
2442 else if (RM2 > 11 && RM2 < 16)
2443 srcreg1 = REG_D0 + RM2 - 12;
2445 srcreg1 = REG_E0 + RM2;
2447 if (RN0 > 7 && RN0 < 12)
2448 srcreg2 = REG_A0 + RN0 - 8;
2449 else if (RN0 > 11 && RN0 < 16)
2450 srcreg2 = REG_D0 + RN0 - 12;
2452 srcreg2 = REG_E0 + RN0;
2454 if (RD0 > 7 && RD0 < 12)
2455 dstreg = REG_A0 + RD0 - 8;
2456 else if (RD0 > 11 && RD0 < 16)
2457 dstreg = REG_D0 + RD0 - 12;
2459 dstreg = REG_E0 + RD0;
2461 State.regs[dstreg] = State.regs[srcreg1] | State.regs[srcreg2];
2463 z = (State.regs[dstreg] == 0);
2464 n = (State.regs[dstreg] & 0x80000000);
2466 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2467 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2470 // 1111 1011 0010 1101 Rm Rn Rd; xor Rm,Rn,Rd
2471 8.0xfb+8.0x2d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::xor
2476 int srcreg1, srcreg2, dstreg;
2480 if (RM2 > 7 && RM2 < 12)
2481 srcreg1 = REG_A0 + RM2 - 8;
2482 else if (RM2 > 11 && RM2 < 16)
2483 srcreg1 = REG_D0 + RM2 - 12;
2485 srcreg1 = REG_E0 + RM2;
2487 if (RN0 > 7 && RN0 < 12)
2488 srcreg2 = REG_A0 + RN0 - 8;
2489 else if (RN0 > 11 && RN0 < 16)
2490 srcreg2 = REG_D0 + RN0 - 12;
2492 srcreg2 = REG_E0 + RN0;
2494 if (RD0 > 7 && RD0 < 12)
2495 dstreg = REG_A0 + RD0 - 8;
2496 else if (RD0 > 11 && RD0 < 16)
2497 dstreg = REG_D0 + RD0 - 12;
2499 dstreg = REG_E0 + RD0;
2501 State.regs[dstreg] = State.regs[srcreg1] ^ State.regs[srcreg2];
2503 z = (State.regs[dstreg] == 0);
2504 n = (State.regs[dstreg] & 0x80000000);
2506 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2507 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2510 // 1111 1011 0100 1101 Rm Rn Rd; asr Rm,Rn,Rd
2511 8.0xfb+8.0x4d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asr
2517 int srcreg1, srcreg2, dstreg;
2521 if (RM2 > 7 && RM2 < 12)
2522 srcreg1 = REG_A0 + RM2 - 8;
2523 else if (RM2 > 11 && RM2 < 16)
2524 srcreg1 = REG_D0 + RM2 - 12;
2526 srcreg1 = REG_E0 + RM2;
2528 if (RN0 > 7 && RN0 < 12)
2529 srcreg2 = REG_A0 + RN0 - 8;
2530 else if (RN0 > 11 && RN0 < 16)
2531 srcreg2 = REG_D0 + RN0 - 12;
2533 srcreg2 = REG_E0 + RN0;
2535 if (RD0 > 7 && RD0 < 12)
2536 dstreg = REG_A0 + RD0 - 8;
2537 else if (RD0 > 11 && RD0 < 16)
2538 dstreg = REG_D0 + RD0 - 12;
2540 dstreg = REG_E0 + RD0;
2542 temp = State.regs[srcreg2];
2544 temp >>= State.regs[srcreg1];
2545 State.regs[dstreg] = temp;
2547 z = (State.regs[dstreg] == 0);
2548 n = (State.regs[dstreg] & 0x80000000);
2550 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2551 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2554 // 1111 1011 0101 1101 Rm Rn Rd; lsr Rm,Rn,Rd
2555 8.0xfb+8.0x5d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::lsr
2560 int srcreg1, srcreg2, dstreg;
2564 if (RM2 > 7 && RM2 < 12)
2565 srcreg1 = REG_A0 + RM2 - 8;
2566 else if (RM2 > 11 && RM2 < 16)
2567 srcreg1 = REG_D0 + RM2 - 12;
2569 srcreg1 = REG_E0 + RM2;
2571 if (RN0 > 7 && RN0 < 12)
2572 srcreg2 = REG_A0 + RN0 - 8;
2573 else if (RN0 > 11 && RN0 < 16)
2574 srcreg2 = REG_D0 + RN0 - 12;
2576 srcreg2 = REG_E0 + RN0;
2578 if (RD0 > 7 && RD0 < 12)
2579 dstreg = REG_A0 + RD0 - 8;
2580 else if (RD0 > 11 && RD0 < 16)
2581 dstreg = REG_D0 + RD0 - 12;
2583 dstreg = REG_E0 + RD0;
2585 c = State.regs[srcreg2] & 1;
2586 State.regs[dstreg] = State.regs[srcreg2] >> State.regs[srcreg1];
2588 z = (State.regs[dstreg] == 0);
2589 n = (State.regs[dstreg] & 0x80000000);
2591 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2592 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2595 // 1111 1011 0110 1101 Rm Rn Rd; asl Rm,Rn,Rd
2596 8.0xfb+8.0x6d+4.RM2,4.RN0+4.RD0,4.0x0:D2c:::asl
2601 int srcreg1, srcreg2, dstreg;
2605 if (RM2 > 7 && RM2 < 12)
2606 srcreg1 = REG_A0 + RM2 - 8;
2607 else if (RM2 > 11 && RM2 < 16)
2608 srcreg1 = REG_D0 + RM2 - 12;
2610 srcreg1 = REG_E0 + RM2;
2612 if (RN0 > 7 && RN0 < 12)
2613 srcreg2 = REG_A0 + RN0 - 8;
2614 else if (RN0 > 11 && RN0 < 16)
2615 srcreg2 = REG_D0 + RN0 - 12;
2617 srcreg2 = REG_E0 + RN0;
2619 if (RD0 > 7 && RD0 < 12)
2620 dstreg = REG_A0 + RD0 - 8;
2621 else if (RD0 > 11 && RD0 < 16)
2622 dstreg = REG_D0 + RD0 - 12;
2624 dstreg = REG_E0 + RD0;
2626 State.regs[dstreg] = State.regs[srcreg2] << State.regs[srcreg1];;
2628 z = (State.regs[dstreg] == 0);
2629 n = (State.regs[dstreg] & 0x80000000);
2631 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2632 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0));
2662 // 1111 1101 0000 1000 Rn Rn IMM32; mov imm24,Rn
2663 8.0xfd+8.0x08+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::mov
2671 if (RN0 > 7 && RN0 < 12)
2672 dstreg = REG_A0 + RN0 - 8;
2673 else if (RN0 > 11 && RN0 < 16)
2674 dstreg = REG_D0 + RN0 - 12;
2676 dstreg = REG_E0 + RN0;
2678 State.regs[dstreg] = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2681 // 1111 1101 0001 1000 Rn Rn IMM32; movu imm24,Rn
2682 8.0xfd+8.0x18+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4k:::movu
2690 if (RN0 > 7 && RN0 < 12)
2691 dstreg = REG_A0 + RN0 - 8;
2692 else if (RN0 > 11 && RN0 < 16)
2693 dstreg = REG_D0 + RN0 - 12;
2695 dstreg = REG_E0 + RN0;
2697 State.regs[dstreg] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
2700 // 1111 1101 0111 1000 Rn Rn IMM32; add imm24,Rn
2701 8.0xfd+8.0x78+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4c:::add
2709 if (RN0 > 7 && RN0 < 12)
2710 dstreg = REG_A0 + RN0 - 8;
2711 else if (RN0 > 11 && RN0 < 16)
2712 dstreg = REG_D0 + RN0 - 12;
2714 dstreg = REG_E0 + RN0;
2716 genericAdd (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
2719 // 1111 1101 1000 1000 Rn Rn IMM32; addc imm24,Rn
2720 8.0xfd+8.0x88+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::addc
2724 int dstreg, z, n, c, v;
2725 unsigned long sum, imm, reg2;
2729 if (RN0 > 7 && RN0 < 12)
2730 dstreg = REG_A0 + RN0 - 8;
2731 else if (RN0 > 11 && RN0 < 16)
2732 dstreg = REG_D0 + RN0 - 12;
2734 dstreg = REG_E0 + RN0;
2736 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2737 reg2 = State.regs[dstreg];
2738 sum = imm + reg2 + ((PSW & PSW_C) != 0);
2739 State.regs[dstreg] = sum;
2742 n = (sum & 0x80000000);
2743 c = (sum < imm) || (sum < reg2);
2744 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2745 && (reg2 & 0x80000000) != (sum & 0x80000000));
2747 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2748 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2749 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2752 // 1111 1101 1001 1000 Rn Rn IMM32; sub imm24,Rn
2753 8.0xfd+8.0x98+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::sub
2761 if (RN0 > 7 && RN0 < 12)
2762 dstreg = REG_A0 + RN0 - 8;
2763 else if (RN0 > 11 && RN0 < 16)
2764 dstreg = REG_D0 + RN0 - 12;
2766 dstreg = REG_E0 + RN0;
2768 genericSub (FETCH24 (IMM24A, IMM24B, IMM24C), dstreg);
2771 // 1111 1101 1010 1000 Rn Rn IMM32; subc imm24,Rn
2772 8.0xfd+8.0xa8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::subc
2776 int dstreg, z, n, c, v;
2777 unsigned long difference, imm, reg2;
2781 if (RN0 > 7 && RN0 < 12)
2782 dstreg = REG_A0 + RN0 - 8;
2783 else if (RN0 > 11 && RN0 < 16)
2784 dstreg = REG_D0 + RN0 - 12;
2786 dstreg = REG_E0 + RN0;
2788 imm = EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C));
2789 reg2 = State.regs[dstreg];
2790 difference = reg2 - imm - ((PSW & PSW_C) != 0);
2791 State.regs[dstreg] = difference;
2793 z = (difference == 0);
2794 n = (difference & 0x80000000);
2796 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
2797 && (reg2 & 0x80000000) != (difference & 0x80000000));
2799 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2800 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
2801 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
2804 // 1111 1101 1101 1000 Rn Rn IMM32; cmp imm24,Rn
2805 8.0xfd+8.0xd8+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::cmp
2813 if (RN0 > 7 && RN0 < 12)
2814 srcreg = REG_A0 + RN0 - 8;
2815 else if (RN0 > 11 && RN0 < 16)
2816 srcreg = REG_D0 + RN0 - 12;
2818 srcreg = REG_E0 + RN0;
2820 genericCmp (EXTEND24 (FETCH24 (IMM24A, IMM24B, IMM24C)), State.regs[srcreg]);
2823 // 1111 1101 1111 1000 XRn XRn IMM32; mov imm24,XRn
2824 8.0xfd+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM24A+8.IMM24B+8.IMM24C:D4o:::mov
2834 State.regs[REG_SP] = FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff;
2840 // 1111 1101 0000 1001 Rn Rn IMM24; and imm24,Rn
2841 8.0xfd+8.0x09+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::and
2850 if (RN0 > 7 && RN0 < 12)
2851 dstreg = REG_A0 + RN0 - 8;
2852 else if (RN0 > 11 && RN0 < 16)
2853 dstreg = REG_D0 + RN0 - 12;
2855 dstreg = REG_E0 + RN0;
2857 State.regs[dstreg] &= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2858 z = (State.regs[dstreg] == 0);
2859 n = (State.regs[dstreg] & 0x80000000) != 0;
2860 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2861 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2864 // 1111 1101 0001 1001 Rn Rn IMM24; or imm24,Rn
2865 8.0xfd+8.0x19+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::or
2874 if (RN0 > 7 && RN0 < 12)
2875 dstreg = REG_A0 + RN0 - 8;
2876 else if (RN0 > 11 && RN0 < 16)
2877 dstreg = REG_D0 + RN0 - 12;
2879 dstreg = REG_E0 + RN0;
2881 State.regs[dstreg] |= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2882 z = (State.regs[dstreg] == 0);
2883 n = (State.regs[dstreg] & 0x80000000) != 0;
2884 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2885 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2888 // 1111 1101 0010 1001 Rn Rn IMM24; xor imm24,Rn
2889 8.0xfd+8.0x29+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::xor
2898 if (RN0 > 7 && RN0 < 12)
2899 dstreg = REG_A0 + RN0 - 8;
2900 else if (RN0 > 11 && RN0 < 16)
2901 dstreg = REG_D0 + RN0 - 12;
2903 dstreg = REG_E0 + RN0;
2905 State.regs[dstreg] ^= (FETCH24 (IMM24A, IMM24B, IMM24C) & 0xffffff);
2906 z = (State.regs[dstreg] == 0);
2907 n = (State.regs[dstreg] & 0x80000000) != 0;
2908 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2909 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2912 // 1111 1101 0100 1001 Rn Rn IMM24; asr imm24,Rn
2913 8.0xfd+8.0x49+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asr
2923 if (RN0 > 7 && RN0 < 12)
2924 dstreg = REG_A0 + RN0 - 8;
2925 else if (RN0 > 11 && RN0 < 16)
2926 dstreg = REG_D0 + RN0 - 12;
2928 dstreg = REG_E0 + RN0;
2930 temp = State.regs[dstreg];
2932 temp >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
2933 State.regs[dstreg] = temp;
2934 z = (State.regs[dstreg] == 0);
2935 n = (State.regs[dstreg] & 0x80000000) != 0;
2936 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2937 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2941 // 1111 1101 0101 1001 Rn Rn IMM24; lsr imm24,Rn
2942 8.0xfd+8.0x59+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::lsr
2951 if (RN0 > 7 && RN0 < 12)
2952 dstreg = REG_A0 + RN0 - 8;
2953 else if (RN0 > 11 && RN0 < 16)
2954 dstreg = REG_D0 + RN0 - 12;
2956 dstreg = REG_E0 + RN0;
2958 c = State.regs[dstreg] & 1;
2959 State.regs[dstreg] >>= (FETCH24 (IMM24A, IMM24B, IMM24C));
2960 z = (State.regs[dstreg] == 0);
2961 n = (State.regs[dstreg] & 0x80000000) != 0;
2962 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2963 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2966 // 1111 1101 0110 1001 Rn Rn IMM24; asl imm24,Rn
2967 8.0xfd+8.0x69+4.RM2,4.RN0=RM2+8.IMM24A+8.IMM24B+8.IMM24C:D4b:::asl
2976 if (RN0 > 7 && RN0 < 12)
2977 dstreg = REG_A0 + RN0 - 8;
2978 else if (RN0 > 11 && RN0 < 16)
2979 dstreg = REG_D0 + RN0 - 12;
2981 dstreg = REG_E0 + RN0;
2983 State.regs[dstreg] <<= (FETCH24 (IMM24A, IMM24B, IMM24C));
2984 z = (State.regs[dstreg] == 0);
2985 n = (State.regs[dstreg] & 0x80000000) != 0;
2986 PSW &= ~(PSW_Z | PSW_N);
2987 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2993 // 1111 1101 1110 1001 Rn Rn IMM24; btst imm24,,Rn
2994 8.0xfd+8.0xe9+4.RN2,4.RN0=RN2+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::btst
3002 if (RN0 > 7 && RN0 < 12)
3003 srcreg = REG_A0 + RN0 - 8;
3004 else if (RN0 > 11 && RN0 < 16)
3005 srcreg = REG_D0 + RN0 - 12;
3007 srcreg = REG_E0 + RN0;
3009 genericBtst (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3012 // 1111 1101 0000 1010 Rn Rm IMM24; mov (d24,Rm),Rn
3013 8.0xfd+8.0x0a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::mov
3021 if (RM0 > 7 && RM0 < 12)
3022 srcreg = REG_A0 + RM0 - 8;
3023 else if (RM0 > 11 && RM0 < 16)
3024 srcreg = REG_D0 + RM0 - 12;
3026 srcreg = REG_E0 + RM0;
3028 if (RN2 > 7 && RN2 < 12)
3029 dstreg = REG_A0 + RN2 - 8;
3030 else if (RN2 > 11 && RN2 < 16)
3031 dstreg = REG_D0 + RN2 - 12;
3033 dstreg = REG_E0 + RN2;
3035 State.regs[dstreg] = load_word (State.regs[srcreg]
3036 + FETCH24 (IMM24A, IMM24B, IMM24C));
3039 // 1111 1101 0001 1010 Rm Rn IMM24; mov Rm,(d24,Rn)
3040 8.0xfd+8.0x1a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::mov
3048 if (RM2 > 7 && RM2 < 12)
3049 srcreg = REG_A0 + RM2 - 8;
3050 else if (RM2 > 11 && RM2 < 16)
3051 srcreg = REG_D0 + RM2 - 12;
3053 srcreg = REG_E0 + RM2;
3055 if (RN0 > 7 && RN0 < 12)
3056 dstreg = REG_A0 + RN0 - 8;
3057 else if (RN0 > 11 && RN0 < 16)
3058 dstreg = REG_D0 + RN0 - 12;
3060 dstreg = REG_E0 + RN0;
3062 store_word (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3063 State.regs[srcreg]);
3066 // 1111 1101 0010 1010 Rn Rm IMM24; movbu (d24,Rm),Rn
3067 8.0xfd+8.0x2a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movbu
3075 if (RM0 > 7 && RM0 < 12)
3076 srcreg = REG_A0 + RM0 - 8;
3077 else if (RM0 > 11 && RM0 < 16)
3078 srcreg = REG_D0 + RM0 - 12;
3080 srcreg = REG_E0 + RM0;
3082 if (RN2 > 7 && RN2 < 12)
3083 dstreg = REG_A0 + RN2 - 8;
3084 else if (RN2 > 11 && RN2 < 16)
3085 dstreg = REG_D0 + RN2 - 12;
3087 dstreg = REG_E0 + RN2;
3089 State.regs[dstreg] = load_byte (State.regs[srcreg]
3090 + FETCH24 (IMM24A, IMM24B, IMM24C));
3093 // 1111 1101 0011 1010 Rm Rn IMM24; movbu Rm,(d24,Rn)
3094 8.0xfd+8.0x3a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movbu
3102 if (RM2 > 7 && RM2 < 12)
3103 srcreg = REG_A0 + RM2 - 8;
3104 else if (RM2 > 11 && RM2 < 16)
3105 srcreg = REG_D0 + RM2 - 12;
3107 srcreg = REG_E0 + RM2;
3109 if (RN0 > 7 && RN0 < 12)
3110 dstreg = REG_A0 + RN0 - 8;
3111 else if (RN0 > 11 && RN0 < 16)
3112 dstreg = REG_D0 + RN0 - 12;
3114 dstreg = REG_E0 + RN0;
3116 store_byte (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3117 State.regs[srcreg]);
3120 // 1111 1101 0100 1010 Rn Rm IMM24; movhu (d24,Rm),Rn
3121 8.0xfd+8.0x4a+4.RN2,4.RM0+8.IMM24A+8.IMM24B+8.IMM24C:D4p:::movhu
3129 if (RM0 > 7 && RM0 < 12)
3130 srcreg = REG_A0 + RM0 - 8;
3131 else if (RM0 > 11 && RM0 < 16)
3132 srcreg = REG_D0 + RM0 - 12;
3134 srcreg = REG_E0 + RM0;
3136 if (RN2 > 7 && RN2 < 12)
3137 dstreg = REG_A0 + RN2 - 8;
3138 else if (RN2 > 11 && RN2 < 16)
3139 dstreg = REG_D0 + RN2 - 12;
3141 dstreg = REG_E0 + RN2;
3143 State.regs[dstreg] = load_half (State.regs[srcreg]
3144 + FETCH24 (IMM24A, IMM24B, IMM24C));
3147 // 1111 1101 0101 1010 Rm Rn IMM24; movhu Rm,(d24,Rn)
3148 8.0xfd+8.0x5a+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4q:::movhu
3156 if (RM2 > 7 && RM2 < 12)
3157 srcreg = REG_A0 + RM2 - 8;
3158 else if (RM2 > 11 && RM2 < 16)
3159 srcreg = REG_D0 + RM2 - 12;
3161 srcreg = REG_E0 + RM2;
3163 if (RN0 > 7 && RN0 < 12)
3164 dstreg = REG_A0 + RN0 - 8;
3165 else if (RN0 > 11 && RN0 < 16)
3166 dstreg = REG_D0 + RN0 - 12;
3168 dstreg = REG_E0 + RN0;
3170 store_half (State.regs[dstreg] + FETCH24 (IMM24A, IMM24B, IMM24C),
3171 State.regs[srcreg]);
3177 // 1111 1101 1000 1010 Rn 0000 IMM24; mov (d24,sp),Rn
3178 8.0xfd+8.0x8a+4.RN2,4.0x0+IMM24A+8.IMM24B+8.IMM24C:D4r:::mov
3186 if (RN2 > 7 && RN2 < 12)
3187 dstreg = REG_A0 + RN2 - 8;
3188 else if (RN2 > 11 && RN2 < 16)
3189 dstreg = REG_D0 + RN2 - 12;
3191 dstreg = REG_E0 + RN2;
3193 State.regs[dstreg] = load_word (State.regs[REG_SP]
3194 + FETCH24 (IMM24A, IMM24B, IMM24C));
3197 // 1111 1101 1001 1010 Rm 0000 IMM24; mov Rm,(d24,sp)
3198 8.0xfd+8.0x9a+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::mov
3206 if (RM2 > 7 && RM2 < 12)
3207 srcreg = REG_A0 + RM2 - 8;
3208 else if (RM2 > 11 && RM2 < 16)
3209 srcreg = REG_D0 + RM2 - 12;
3211 srcreg = REG_E0 + RM2;
3213 store_word (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3214 State.regs[srcreg]);
3217 // 1111 1101 1010 1010 Rn 0000 IMM24; movbu (d24,Rm),Rn
3218 8.0xfd+8.0xaa+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movbu
3226 if (RN2 > 7 && RN2 < 12)
3227 dstreg = REG_A0 + RN2 - 8;
3228 else if (RN2 > 11 && RN2 < 16)
3229 dstreg = REG_D0 + RN2 - 12;
3231 dstreg = REG_E0 + RN2;
3233 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3234 + FETCH24 (IMM24A, IMM24B, IMM24C));
3237 // 1111 1101 1011 1010 Rm 0000 IMM24; movbu Rm,(d24,sp)
3238 8.0xfd+8.0xba+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movbu
3246 if (RM2 > 7 && RM2 < 12)
3247 srcreg = REG_A0 + RM2 - 8;
3248 else if (RM2 > 11 && RM2 < 16)
3249 srcreg = REG_D0 + RM2 - 12;
3251 srcreg = REG_E0 + RM2;
3253 store_byte (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3254 State.regs[srcreg]);
3257 // 1111 1101 1100 1010 Rn 0000 IMM24; movhu (d24,sp),Rn
3258 8.0xfd+8.0xca+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4r:::movhu
3266 if (RN2 > 7 && RN2 < 12)
3267 dstreg = REG_A0 + RN2 - 8;
3268 else if (RN2 > 11 && RN2 < 16)
3269 dstreg = REG_D0 + RN2 - 12;
3271 dstreg = REG_E0 + RN2;
3273 State.regs[dstreg] = load_half (State.regs[REG_SP]
3274 + FETCH24 (IMM24A, IMM24B, IMM24C));
3277 // 1111 1101 1101 1010 Rm Rn IMM24; movhu Rm,(d24,sp)
3278 8.0xfd+8.0xda+4.RM2,4.RN0+8.IMM24A+8.IMM24B+8.IMM24C:D4s:::movhu
3286 if (RM2 > 7 && RM2 < 12)
3287 srcreg = REG_A0 + RM2 - 8;
3288 else if (RM2 > 11 && RM2 < 16)
3289 srcreg = REG_D0 + RM2 - 12;
3291 srcreg = REG_E0 + RM2;
3293 store_half (State.regs[REG_SP] + FETCH24 (IMM24A, IMM24B, IMM24C),
3294 State.regs[srcreg]);
3305 // 1111 1101 0000 1110 Rn 0000 ABS24; mov (abs24),Rn
3306 8.0xfd+8.0x0e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::mov
3314 if (RN2 > 7 && RN2 < 12)
3315 dstreg = REG_A0 + RN2 - 8;
3316 else if (RN2 > 11 && RN2 < 16)
3317 dstreg = REG_D0 + RN2 - 12;
3319 dstreg = REG_E0 + RN2;
3321 State.regs[dstreg] = load_word (FETCH24 (IMM24A, IMM24B, IMM24C));
3324 // 1111 1101 0001 1110 Rm 0000 ABS24; mov Rm,(abs24)
3325 8.0xfd+8.0x1e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4v:::mov
3333 if (RM2 > 7 && RM2 < 12)
3334 srcreg = REG_A0 + RM2 - 8;
3335 else if (RM2 > 11 && RM2 < 16)
3336 srcreg = REG_D0 + RM2 - 12;
3338 srcreg = REG_E0 + RM2;
3340 store_word (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3344 // 1111 1101 0010 1110 Rn 0000 ABS24; movbu (abs24),Rn
3345 8.0xfd+8.0x2e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movbu
3353 if (RN2 > 7 && RN2 < 12)
3354 dstreg = REG_A0 + RN2 - 8;
3355 else if (RN2 > 11 && RN2 < 16)
3356 dstreg = REG_D0 + RN2 - 12;
3358 dstreg = REG_E0 + RN2;
3360 State.regs[dstreg] = load_byte (FETCH24 (IMM24A, IMM24B, IMM24C));
3363 // 1111 1101 0011 1110 Rm 0000 ABS24; movbu Rm,(abs24)
3364 8.0xfd+8.0x3e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movbu
3372 if (RM2 > 7 && RM2 < 12)
3373 srcreg = REG_A0 + RM2 - 8;
3374 else if (RM2 > 11 && RM2 < 16)
3375 srcreg = REG_D0 + RM2 - 12;
3377 srcreg = REG_E0 + RM2;
3379 store_byte (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3383 // 1111 1101 0100 1110 Rn 0000 ABS24; movhu (abs24),Rn
3384 8.0xfd+8.0x4e+4.RN2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4t:::movhu
3392 if (RN2 > 7 && RN2 < 12)
3393 dstreg = REG_A0 + RN2 - 8;
3394 else if (RN2 > 11 && RN2 < 16)
3395 dstreg = REG_D0 + RN2 - 12;
3397 dstreg = REG_E0 + RN2;
3399 State.regs[dstreg] = load_half (FETCH24 (IMM24A, IMM24B, IMM24C));
3402 // 1111 1101 0101 1110 Rm 0000 ABS24; movhu Rm,(abs24)
3403 8.0xfd+8.0x5e+4.RM2,4.0x0+8.IMM24A+8.IMM24B+8.IMM24C:D4u:::movhu
3411 if (RM2 > 7 && RM2 < 12)
3412 srcreg = REG_A0 + RM2 - 8;
3413 else if (RM2 > 11 && RM2 < 16)
3414 srcreg = REG_D0 + RM2 - 12;
3416 srcreg = REG_E0 + RM2;
3418 store_half (FETCH24 (IMM24A, IMM24B, IMM24C), State.regs[srcreg]);
3422 // 1111 1110 0000 1000 Rn Rn IMM32; mov imm32,Rn
3423 8.0xfe+8.0x08+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::mov
3431 if (RN0 > 7 && RN0 < 12)
3432 dstreg = REG_A0 + RN0 - 8;
3433 else if (RN0 > 11 && RN0 < 16)
3434 dstreg = REG_D0 + RN0 - 12;
3436 dstreg = REG_E0 + RN0;
3438 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3441 // 1111 1110 0001 1000 Rn Rn IMM32; movu imm32,Rn
3442 8.0xfe+8.0x18+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movu
3450 if (RN0 > 7 && RN0 < 12)
3451 dstreg = REG_A0 + RN0 - 8;
3452 else if (RN0 > 11 && RN0 < 16)
3453 dstreg = REG_D0 + RN0 - 12;
3455 dstreg = REG_E0 + RN0;
3457 State.regs[dstreg] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3460 // 1111 1110 0111 1000 Rn Rn IMM32; add imm32,Rn
3461 8.0xfe+8.0x78+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::add
3469 if (RN0 > 7 && RN0 < 12)
3470 dstreg = REG_A0 + RN0 - 8;
3471 else if (RN0 > 11 && RN0 < 16)
3472 dstreg = REG_D0 + RN0 - 12;
3474 dstreg = REG_E0 + RN0;
3476 genericAdd (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3479 // 1111 1110 1000 1000 Rn Rn IMM32; addc imm32,Rn
3480 8.0xfe+8.0x88+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::addc
3485 unsigned int imm, reg2, sum;
3490 if (RN0 > 7 && RN0 < 12)
3491 dstreg = REG_A0 + RN0 - 8;
3492 else if (RN0 > 11 && RN0 < 16)
3493 dstreg = REG_D0 + RN0 - 12;
3495 dstreg = REG_E0 + RN0;
3497 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3498 reg2 = State.regs[dstreg];
3499 sum = imm + reg2 + ((PSW & PSW_C) != 0);
3500 State.regs[dstreg] = sum;
3503 n = (sum & 0x80000000);
3504 c = (sum < imm) || (sum < reg2);
3505 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3506 && (reg2 & 0x80000000) != (sum & 0x80000000));
3508 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3509 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3510 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3513 // 1111 1110 1001 1000 Rn Rn IMM32; sub imm32,Rn
3514 8.0xfe+8.0x98+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::sub
3522 if (RN0 > 7 && RN0 < 12)
3523 dstreg = REG_A0 + RN0 - 8;
3524 else if (RN0 > 11 && RN0 < 16)
3525 dstreg = REG_D0 + RN0 - 12;
3527 dstreg = REG_E0 + RN0;
3529 genericSub (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), dstreg);
3532 // 1111 1110 1010 1000 Rn Rn IMM32; subc imm32,Rn
3533 8.0xfe+8.0xa8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::subc
3538 unsigned int imm, reg2, difference;
3543 if (RN0 > 7 && RN0 < 12)
3544 dstreg = REG_A0 + RN0 - 8;
3545 else if (RN0 > 11 && RN0 < 16)
3546 dstreg = REG_D0 + RN0 - 12;
3548 dstreg = REG_E0 + RN0;
3550 imm = FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D);
3551 reg2 = State.regs[dstreg];
3552 difference = reg2 - imm - ((PSW & PSW_C) != 0);
3553 State.regs[dstreg] = difference;
3555 z = (difference == 0);
3556 n = (difference & 0x80000000);
3558 v = ((reg2 & 0x80000000) == (imm & 0x80000000)
3559 && (reg2 & 0x80000000) != (difference & 0x80000000));
3561 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3562 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
3563 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
3566 // 1111 1110 0111 1000 Rn Rn IMM32; cmp imm32,Rn
3567 8.0xfe+8.0xd8+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::cmp
3575 if (RN0 > 7 && RN0 < 12)
3576 srcreg = REG_A0 + RN0 - 8;
3577 else if (RN0 > 11 && RN0 < 16)
3578 srcreg = REG_D0 + RN0 - 12;
3580 srcreg = REG_E0 + RN0;
3582 genericCmp (FETCH32(IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3585 // 1111 1110 1111 1000 XRn XRn IMM32; mov imm32,XRn
3586 8.0xfe+8.0xf8+4.XRM2,4.XRN0=XRM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::mov
3595 State.regs[REG_SP] = FETCH32(IMM32A, IMM32B, IMM32C, IMM32D);
3600 // 1111 1110 0000 1001 Rn Rn IMM32; and imm32,Rn
3601 8.0xfe+8.0x09+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::and
3610 if (RN0 > 7 && RN0 < 12)
3611 dstreg = REG_A0 + RN0 - 8;
3612 else if (RN0 > 11 && RN0 < 16)
3613 dstreg = REG_D0 + RN0 - 12;
3615 dstreg = REG_E0 + RN0;
3617 State.regs[dstreg] &= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3618 z = (State.regs[dstreg] == 0);
3619 n = (State.regs[dstreg] & 0x80000000) != 0;
3620 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3621 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3624 // 1111 1110 0001 1001 Rn Rn IMM32; or imm32,Rn
3625 8.0xfe+8.0x19+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::or
3634 if (RN0 > 7 && RN0 < 12)
3635 dstreg = REG_A0 + RN0 - 8;
3636 else if (RN0 > 11 && RN0 < 16)
3637 dstreg = REG_D0 + RN0 - 12;
3639 dstreg = REG_E0 + RN0;
3641 State.regs[dstreg] |= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3642 z = (State.regs[dstreg] == 0);
3643 n = (State.regs[dstreg] & 0x80000000) != 0;
3644 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3645 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3648 // 1111 1110 0010 1001 Rn Rn IMM32; xor imm32,Rn
3649 8.0xfe+8.0x29+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::xor
3658 if (RN0 > 7 && RN0 < 12)
3659 dstreg = REG_A0 + RN0 - 8;
3660 else if (RN0 > 11 && RN0 < 16)
3661 dstreg = REG_D0 + RN0 - 12;
3663 dstreg = REG_E0 + RN0;
3665 State.regs[dstreg] ^= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3666 z = (State.regs[dstreg] == 0);
3667 n = (State.regs[dstreg] & 0x80000000) != 0;
3668 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
3669 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3672 // 1111 1110 0100 1001 Rn Rn IMM32; asr imm32,Rn
3673 8.0xfe+8.0x49+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asr
3683 if (RN0 > 7 && RN0 < 12)
3684 dstreg = REG_A0 + RN0 - 8;
3685 else if (RN0 > 11 && RN0 < 16)
3686 dstreg = REG_D0 + RN0 - 12;
3688 dstreg = REG_E0 + RN0;
3690 temp = State.regs[dstreg];
3692 temp >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3693 State.regs[dstreg] = temp;
3694 z = (State.regs[dstreg] == 0);
3695 n = (State.regs[dstreg] & 0x80000000) != 0;
3696 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3697 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3700 // 1111 1110 0101 1001 Rn Rn IMM32; lsr imm32,Rn
3701 8.0xfe+8.0x59+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::lsr
3710 if (RN0 > 7 && RN0 < 12)
3711 dstreg = REG_A0 + RN0 - 8;
3712 else if (RN0 > 11 && RN0 < 16)
3713 dstreg = REG_D0 + RN0 - 12;
3715 dstreg = REG_E0 + RN0;
3717 c = State.regs[dstreg] & 1;
3718 State.regs[dstreg] >>= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3719 z = (State.regs[dstreg] == 0);
3720 n = (State.regs[dstreg] & 0x80000000) != 0;
3721 PSW &= ~(PSW_Z | PSW_N | PSW_C);
3722 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
3725 // 1111 1110 0110 1001 Rn Rn IMM32; asl imm32,Rn
3726 8.0xfe+8.0x69+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::asl
3735 if (RN0 > 7 && RN0 < 12)
3736 dstreg = REG_A0 + RN0 - 8;
3737 else if (RN0 > 11 && RN0 < 16)
3738 dstreg = REG_D0 + RN0 - 12;
3740 dstreg = REG_E0 + RN0;
3742 State.regs[dstreg] <<= (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3743 z = (State.regs[dstreg] == 0);
3744 n = (State.regs[dstreg] & 0x80000000) != 0;
3745 PSW &= ~(PSW_Z | PSW_N);
3746 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
3752 // 1111 1110 1110 1001 Rn Rn IMM32; btst imm32,Rn
3753 8.0xfe+8.0xe9+4.RM2,4.RN0=RM2+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5a:::btst
3761 if (RN0 > 7 && RN0 < 12)
3762 srcreg = REG_A0 + RN0 - 8;
3763 else if (RN0 > 11 && RN0 < 16)
3764 srcreg = REG_D0 + RN0 - 12;
3766 srcreg = REG_E0 + RN0;
3768 genericBtst (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
3771 // 1111 1110 0000 1010 Rn Rm IMM32; mov (d32,Rm),Rn
3772 8.0xfe+8.0x0a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5f:::mov
3780 if (RM0 > 7 && RM0 < 12)
3781 srcreg = REG_A0 + RM0 - 8;
3782 else if (RM0 > 11 && RM0 < 16)
3783 srcreg = REG_D0 + RM0 - 12;
3785 srcreg = REG_E0 + RM0;
3787 if (RN2 > 7 && RN2 < 12)
3788 dstreg = REG_A0 + RN2 - 8;
3789 else if (RN2 > 11 && RN2 < 16)
3790 dstreg = REG_D0 + RN2 - 12;
3792 dstreg = REG_E0 + RN2;
3794 State.regs[dstreg] = load_word (State.regs[srcreg]
3795 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3798 // 1111 1110 0001 1010 Rm Rn IMM32; mov Rm,(d32,Rn)
3799 8.0xfe+8.0x1a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5g:::mov
3807 if (RM2 > 7 && RM2 < 12)
3808 srcreg = REG_A0 + RM2 - 8;
3809 else if (RM2 > 11 && RM2 < 16)
3810 srcreg = REG_D0 + RM2 - 12;
3812 srcreg = REG_E0 + RM2;
3814 if (RN0 > 7 && RN0 < 12)
3815 dstreg = REG_A0 + RN0 - 8;
3816 else if (RN0 > 11 && RN0 < 16)
3817 dstreg = REG_D0 + RN0 - 12;
3819 dstreg = REG_E0 + RN0;
3821 store_word (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3822 State.regs[srcreg]);
3825 // 1111 1110 0010 1010 Rn Rm IMM32; movbu (d32,Rm),Rn
3826 8.0xfe+8.0x2a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movbu
3834 if (RM0 > 7 && RM0 < 12)
3835 srcreg = REG_A0 + RM0 - 8;
3836 else if (RM0 > 11 && RM0 < 16)
3837 srcreg = REG_D0 + RM0 - 12;
3839 srcreg = REG_E0 + RM0;
3841 if (RN2 > 7 && RN2 < 12)
3842 dstreg = REG_A0 + RN2 - 8;
3843 else if (RN2 > 11 && RN2 < 16)
3844 dstreg = REG_D0 + RN2 - 12;
3846 dstreg = REG_E0 + RN2;
3848 State.regs[dstreg] = load_byte (State.regs[srcreg]
3849 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3852 // 1111 1110 0011 1010 Rm Rn IMM32; movbu Rm,(d32,Rn)
3853 8.0xfe+8.0x3a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movbu
3861 if (RM2 > 7 && RM2 < 12)
3862 srcreg = REG_A0 + RM2 - 8;
3863 else if (RM2 > 11 && RM2 < 16)
3864 srcreg = REG_D0 + RM2 - 12;
3866 srcreg = REG_E0 + RM2;
3868 if (RN0 > 7 && RN0 < 12)
3869 dstreg = REG_A0 + RN0 - 8;
3870 else if (RN0 > 11 && RN0 < 16)
3871 dstreg = REG_D0 + RN0 - 12;
3873 dstreg = REG_E0 + RN0;
3875 store_byte (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3876 State.regs[srcreg]);
3879 // 1111 1110 0100 1010 Rn Rm IMM32; movhu (d32,Rm),Rn
3880 8.0xfe+8.0x4a+4.RN2,4.RM0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5:::movhu
3888 if (RM0 > 7 && RM0 < 12)
3889 srcreg = REG_A0 + RM0 - 8;
3890 else if (RM0 > 11 && RM0 < 16)
3891 srcreg = REG_D0 + RM0 - 12;
3893 srcreg = REG_E0 + RM0;
3895 if (RN2 > 7 && RN2 < 12)
3896 dstreg = REG_A0 + RN2 - 8;
3897 else if (RN2 > 11 && RN2 < 16)
3898 dstreg = REG_D0 + RN2 - 12;
3900 dstreg = REG_E0 + RN2;
3902 State.regs[dstreg] = load_half (State.regs[srcreg]
3903 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3906 // 1111 1110 0101 1010 Rm Rn IMM32; movhu Rm,(d32,Rn)
3907 8.0xfe+8.0x5a+4.RM2,4.RN0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5b:::movhu
3915 if (RM2 > 7 && RM2 < 12)
3916 srcreg = REG_A0 + RM2 - 8;
3917 else if (RM2 > 11 && RM2 < 16)
3918 srcreg = REG_D0 + RM2 - 12;
3920 srcreg = REG_E0 + RM2;
3922 if (RN0 > 7 && RN0 < 12)
3923 dstreg = REG_A0 + RN0 - 8;
3924 else if (RN0 > 11 && RN0 < 16)
3925 dstreg = REG_D0 + RN0 - 12;
3927 dstreg = REG_E0 + RN0;
3929 store_half (State.regs[dstreg] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3930 State.regs[srcreg]);
3936 // 1111 1110 1000 1010 Rn 0000 IMM32; mov (d32,sp),Rn
3937 8.0xfe+8.0x8a+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::mov
3945 if (RN2 > 7 && RN2 < 12)
3946 dstreg = REG_A0 + RN2 - 8;
3947 else if (RN2 > 11 && RN2 < 16)
3948 dstreg = REG_D0 + RN2 - 12;
3950 dstreg = REG_E0 + RN2;
3952 State.regs[dstreg] = load_word (State.regs[REG_SP]
3953 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3956 // 1111 1110 1001 1010 Rm 0000 IMM32; mov Rm,(d32,sp)
3957 8.0xfe+8.0x9a+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::mov
3965 if (RM2 > 7 && RM2 < 12)
3966 srcreg = REG_A0 + RM2 - 8;
3967 else if (RM2 > 11 && RM2 < 16)
3968 srcreg = REG_D0 + RM2 - 12;
3970 srcreg = REG_E0 + RM2;
3972 store_word (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
3973 State.regs[srcreg]);
3976 // 1111 1110 1010 1010 Rn 0000 IMM32; movbu (d32,sp),Rn
3977 8.0xfe+8.0xaa+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movbu
3985 if (RN2 > 7 && RN2 < 12)
3986 dstreg = REG_A0 + RN2 - 8;
3987 else if (RN2 > 11 && RN2 < 16)
3988 dstreg = REG_D0 + RN2 - 12;
3990 dstreg = REG_E0 + RN2;
3992 State.regs[dstreg] = load_byte (State.regs[REG_SP]
3993 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
3996 // 1111 1110 1011 1010 Rm 0000 IMM32; movbu Rm,(d32,sp)
3997 8.0xfe+8.0xba+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movbu
4005 if (RM2 > 7 && RM2 < 12)
4006 srcreg = REG_A0 + RM2 - 8;
4007 else if (RM2 > 11 && RM2 < 16)
4008 srcreg = REG_D0 + RM2 - 12;
4010 srcreg = REG_E0 + RM2;
4012 store_byte (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4013 State.regs[srcreg]);
4016 // 1111 1110 1100 1010 Rn 0000 IMM32; movhu (d32,sp),Rn
4017 8.0xfe+8.0xca+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5c:::movhu
4025 if (RN2 > 7 && RN2 < 12)
4026 dstreg = REG_A0 + RN2 - 8;
4027 else if (RN2 > 11 && RN2 < 16)
4028 dstreg = REG_D0 + RN2 - 12;
4030 dstreg = REG_E0 + RN2;
4032 State.regs[dstreg] = load_half (State.regs[REG_SP]
4033 + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4036 // 1111 1110 1101 1010 Rm 0000 IMM32; movhu Rm,(d32,sp)
4037 8.0xfe+8.0xda+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5d:::movhu
4045 if (RM2 > 7 && RM2 < 12)
4046 srcreg = REG_A0 + RM2 - 8;
4047 else if (RM2 > 11 && RM2 < 16)
4048 srcreg = REG_D0 + RM2 - 12;
4050 srcreg = REG_E0 + RM2;
4052 store_half (State.regs[REG_SP] + FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D),
4053 State.regs[srcreg]);
4071 // 1111 1110 0000 1110 Rn 0000 IMM32; mov (abs32),Rn
4072 8.0xfe+8.0x0e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5h:::mov
4080 if (RN2 > 7 && RN2 < 12)
4081 dstreg = REG_A0 + RN2 - 8;
4082 else if (RN2 > 11 && RN2 < 16)
4083 dstreg = REG_D0 + RN2 - 12;
4085 dstreg = REG_E0 + RN2;
4087 State.regs[dstreg] = load_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4090 // 1111 1110 0001 1110 Rm 0000 IMM32; mov Rn,(abs32)
4091 8.0xfe+8.0x1e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::mov
4099 if (RM2 > 7 && RM2 < 12)
4100 srcreg = REG_A0 + RM2 - 8;
4101 else if (RM2 > 11 && RM2 < 16)
4102 srcreg = REG_D0 + RM2 - 12;
4104 srcreg = REG_E0 + RM2;
4106 store_word (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4109 // 1111 1110 0020 1110 Rn 0000 IMM32; movbu (abs32),Rn
4110 8.0xfe+8.0x2e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5i:::movbu
4118 if (RN2 > 7 && RN2 < 12)
4119 dstreg = REG_A0 + RN2 - 8;
4120 else if (RN2 > 11 && RN2 < 16)
4121 dstreg = REG_D0 + RN2 - 12;
4123 dstreg = REG_E0 + RN2;
4125 State.regs[dstreg] = load_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4128 // 1111 1110 0011 1110 Rm 0000 IMM32; movbu Rn,(abs32)
4129 8.0xfe+8.0x3e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movbu
4137 if (RM2 > 7 && RM2 < 12)
4138 srcreg = REG_A0 + RM2 - 8;
4139 else if (RM2 > 11 && RM2 < 16)
4140 srcreg = REG_D0 + RM2 - 12;
4142 srcreg = REG_E0 + RM2;
4144 store_byte (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);
4147 // 1111 1110 0100 1110 Rn 0000 IMM32; movhu (abs32),Rn
4148 8.0xfe+8.0x4e+4.RN2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5j:::movhu
4156 if (RN2 > 7 && RN2 < 12)
4157 dstreg = REG_A0 + RN2 - 8;
4158 else if (RN2 > 11 && RN2 < 16)
4159 dstreg = REG_D0 + RN2 - 12;
4161 dstreg = REG_E0 + RN2;
4163 State.regs[dstreg] = load_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D));
4166 // 1111 1110 0101 1110 Rm 0000 IMM32; movhu Rn,(abs32)
4167 8.0xfe+8.0x5e+4.RM2,4.0x0+8.IMM32A+8.IMM32B+8.IMM32C+8.IMM32D:D5e:::movhu
4175 if (RM2 > 7 && RM2 < 12)
4176 srcreg = REG_A0 + RM2 - 8;
4177 else if (RM2 > 11 && RM2 < 16)
4178 srcreg = REG_D0 + RM2 - 12;
4180 srcreg = REG_E0 + RM2;
4182 store_half (FETCH32 (IMM32A, IMM32B, IMM32C, IMM32D), State.regs[srcreg]);