5 #include "sim-options.h"
9 #include "sim-assert.h"
30 /* simulation target board. NULL=default configuration */
31 static char* board
= NULL
;
33 static DECLARE_OPTION_HANDLER (mn10300_option_handler
);
36 OPTION_BOARD
= OPTION_START
,
40 mn10300_option_handler (SIM_DESC sd
,
53 board
= zalloc(strlen(arg
) + 1);
63 static const OPTION mn10300_options
[] =
65 #define BOARD_AM32 "stdeval1"
66 { {"board", required_argument
, NULL
, OPTION_BOARD
},
67 '\0', "none" /* rely on compile-time string concatenation for other options */
69 , "Customize simulation for a particular board.", mn10300_option_handler
},
71 { {NULL
, no_argument
, NULL
, 0}, '\0', NULL
, NULL
, NULL
}
74 /* For compatibility */
78 mn10300_pc_get (sim_cpu
*cpu
)
84 mn10300_pc_set (sim_cpu
*cpu
, sim_cia pc
)
89 static int mn10300_reg_fetch (SIM_CPU
*, int, unsigned char *, int);
90 static int mn10300_reg_store (SIM_CPU
*, int, unsigned char *, int);
92 /* These default values correspond to expected usage for the chip. */
95 sim_open (SIM_OPEN_KIND kind
,
101 SIM_DESC sd
= sim_state_alloc (kind
, cb
);
103 SIM_ASSERT (STATE_MAGIC (sd
) == SIM_MAGIC_NUMBER
);
105 /* The cpu data is kept in a separately allocated chunk of memory. */
106 if (sim_cpu_alloc_all (sd
, 1, /*cgen_cpu_max_extra_bytes ()*/0) != SIM_RC_OK
)
109 /* for compatibility */
112 /* FIXME: should be better way of setting up interrupts. For
113 moment, only support watchpoints causing a breakpoint (gdb
115 STATE_WATCHPOINTS (sd
)->pc
= &(PC
);
116 STATE_WATCHPOINTS (sd
)->sizeof_pc
= sizeof (PC
);
117 STATE_WATCHPOINTS (sd
)->interrupt_handler
= NULL
;
118 STATE_WATCHPOINTS (sd
)->interrupt_names
= NULL
;
120 if (sim_pre_argv_init (sd
, argv
[0]) != SIM_RC_OK
)
122 sim_add_option_table (sd
, NULL
, mn10300_options
);
124 /* Allocate core managed memory */
125 sim_do_command (sd
, "memory region 0,0x100000");
126 sim_do_command (sd
, "memory region 0x40000000,0x200000");
128 /* getopt will print the error message so we just have to exit if this fails.
129 FIXME: Hmmm... in the case of gdb we need getopt to call
131 if (sim_parse_args (sd
, argv
) != SIM_RC_OK
)
133 /* Uninstall the modules to avoid memory leaks,
134 file descriptor leaks, etc. */
135 sim_module_uninstall (sd
);
140 && (strcmp(board
, BOARD_AM32
) == 0 ) )
143 STATE_ENVIRONMENT (sd
) = OPERATING_ENVIRONMENT
;
145 sim_do_command (sd
, "memory region 0x44000000,0x40000");
146 sim_do_command (sd
, "memory region 0x48000000,0x400000");
148 /* device support for mn1030002 */
149 /* interrupt controller */
151 sim_hw_parse (sd
, "/mn103int@0x34000100/reg 0x34000100 0x7C 0x34000200 0x8 0x34000280 0x8");
153 /* DEBUG: NMI input's */
154 sim_hw_parse (sd
, "/glue@0x30000000/reg 0x30000000 12");
155 sim_hw_parse (sd
, "/glue@0x30000000 > int0 nmirq /mn103int");
156 sim_hw_parse (sd
, "/glue@0x30000000 > int1 watchdog /mn103int");
157 sim_hw_parse (sd
, "/glue@0x30000000 > int2 syserr /mn103int");
159 /* DEBUG: ACK input */
160 sim_hw_parse (sd
, "/glue@0x30002000/reg 0x30002000 4");
161 sim_hw_parse (sd
, "/glue@0x30002000 > int ack /mn103int");
163 /* DEBUG: LEVEL output */
164 sim_hw_parse (sd
, "/glue@0x30004000/reg 0x30004000 8");
165 sim_hw_parse (sd
, "/mn103int > nmi int0 /glue@0x30004000");
166 sim_hw_parse (sd
, "/mn103int > level int1 /glue@0x30004000");
168 /* DEBUG: A bunch of interrupt inputs */
169 sim_hw_parse (sd
, "/glue@0x30006000/reg 0x30006000 32");
170 sim_hw_parse (sd
, "/glue@0x30006000 > int0 irq-0 /mn103int");
171 sim_hw_parse (sd
, "/glue@0x30006000 > int1 irq-1 /mn103int");
172 sim_hw_parse (sd
, "/glue@0x30006000 > int2 irq-2 /mn103int");
173 sim_hw_parse (sd
, "/glue@0x30006000 > int3 irq-3 /mn103int");
174 sim_hw_parse (sd
, "/glue@0x30006000 > int4 irq-4 /mn103int");
175 sim_hw_parse (sd
, "/glue@0x30006000 > int5 irq-5 /mn103int");
176 sim_hw_parse (sd
, "/glue@0x30006000 > int6 irq-6 /mn103int");
177 sim_hw_parse (sd
, "/glue@0x30006000 > int7 irq-7 /mn103int");
179 /* processor interrupt device */
182 sim_hw_parse (sd
, "/mn103cpu@0x20000000");
183 sim_hw_parse (sd
, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
185 /* DEBUG: ACK output wired upto a glue device */
186 sim_hw_parse (sd
, "/glue@0x20002000");
187 sim_hw_parse (sd
, "/glue@0x20002000/reg 0x20002000 4");
188 sim_hw_parse (sd
, "/mn103cpu > ack int0 /glue@0x20002000");
190 /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */
191 sim_hw_parse (sd
, "/glue@0x20004000");
192 sim_hw_parse (sd
, "/glue@0x20004000/reg 0x20004000 12");
193 sim_hw_parse (sd
, "/glue@0x20004000 > int0 reset /mn103cpu");
194 sim_hw_parse (sd
, "/glue@0x20004000 > int1 nmi /mn103cpu");
195 sim_hw_parse (sd
, "/glue@0x20004000 > int2 level /mn103cpu");
197 /* REAL: The processor wired up to the real interrupt controller */
198 sim_hw_parse (sd
, "/mn103cpu > ack ack /mn103int");
199 sim_hw_parse (sd
, "/mn103int > level level /mn103cpu");
200 sim_hw_parse (sd
, "/mn103int > nmi nmi /mn103cpu");
206 sim_hw_parse (sd
, "/pal@0x31000000");
207 sim_hw_parse (sd
, "/pal@0x31000000/reg 0x31000000 64");
208 sim_hw_parse (sd
, "/pal@0x31000000/poll? true");
210 /* DEBUG: PAL wired up to a glue device */
211 sim_hw_parse (sd
, "/glue@0x31002000");
212 sim_hw_parse (sd
, "/glue@0x31002000/reg 0x31002000 16");
213 sim_hw_parse (sd
, "/pal@0x31000000 > countdown int0 /glue@0x31002000");
214 sim_hw_parse (sd
, "/pal@0x31000000 > timer int1 /glue@0x31002000");
215 sim_hw_parse (sd
, "/pal@0x31000000 > int int2 /glue@0x31002000");
216 sim_hw_parse (sd
, "/glue@0x31002000 > int0 int3 /glue@0x31002000");
217 sim_hw_parse (sd
, "/glue@0x31002000 > int1 int3 /glue@0x31002000");
218 sim_hw_parse (sd
, "/glue@0x31002000 > int2 int3 /glue@0x31002000");
220 /* REAL: The PAL wired up to the real interrupt controller */
221 sim_hw_parse (sd
, "/pal@0x31000000 > countdown irq-0 /mn103int");
222 sim_hw_parse (sd
, "/pal@0x31000000 > timer irq-1 /mn103int");
223 sim_hw_parse (sd
, "/pal@0x31000000 > int irq-2 /mn103int");
225 /* 8 and 16 bit timers */
226 sim_hw_parse (sd
, "/mn103tim@0x34001000/reg 0x34001000 36 0x34001080 100 0x34004000 16");
228 /* Hook timer interrupts up to interrupt controller */
229 sim_hw_parse (sd
, "/mn103tim > timer-0-underflow timer-0-underflow /mn103int");
230 sim_hw_parse (sd
, "/mn103tim > timer-1-underflow timer-1-underflow /mn103int");
231 sim_hw_parse (sd
, "/mn103tim > timer-2-underflow timer-2-underflow /mn103int");
232 sim_hw_parse (sd
, "/mn103tim > timer-3-underflow timer-3-underflow /mn103int");
233 sim_hw_parse (sd
, "/mn103tim > timer-4-underflow timer-4-underflow /mn103int");
234 sim_hw_parse (sd
, "/mn103tim > timer-5-underflow timer-5-underflow /mn103int");
235 sim_hw_parse (sd
, "/mn103tim > timer-6-underflow timer-6-underflow /mn103int");
236 sim_hw_parse (sd
, "/mn103tim > timer-6-compare-a timer-6-compare-a /mn103int");
237 sim_hw_parse (sd
, "/mn103tim > timer-6-compare-b timer-6-compare-b /mn103int");
240 /* Serial devices 0,1,2 */
241 sim_hw_parse (sd
, "/mn103ser@0x34000800/reg 0x34000800 48");
242 sim_hw_parse (sd
, "/mn103ser@0x34000800/poll? true");
244 /* Hook serial interrupts up to interrupt controller */
245 sim_hw_parse (sd
, "/mn103ser > serial-0-receive serial-0-receive /mn103int");
246 sim_hw_parse (sd
, "/mn103ser > serial-0-transmit serial-0-transmit /mn103int");
247 sim_hw_parse (sd
, "/mn103ser > serial-1-receive serial-1-receive /mn103int");
248 sim_hw_parse (sd
, "/mn103ser > serial-1-transmit serial-1-transmit /mn103int");
249 sim_hw_parse (sd
, "/mn103ser > serial-2-receive serial-2-receive /mn103int");
250 sim_hw_parse (sd
, "/mn103ser > serial-2-transmit serial-2-transmit /mn103int");
252 sim_hw_parse (sd
, "/mn103iop@0x36008000/reg 0x36008000 8 0x36008020 8 0x36008040 0xc 0x36008060 8 0x36008080 8");
254 /* Memory control registers */
255 sim_do_command (sd
, "memory region 0x32000020,0x30");
256 /* Cache control register */
257 sim_do_command (sd
, "memory region 0x20000070,0x4");
258 /* Cache purge regions */
259 sim_do_command (sd
, "memory region 0x28400000,0x800");
260 sim_do_command (sd
, "memory region 0x28401000,0x800");
262 sim_do_command (sd
, "memory region 0x32000100,0xF");
263 sim_do_command (sd
, "memory region 0x32000200,0xF");
264 sim_do_command (sd
, "memory region 0x32000400,0xF");
265 sim_do_command (sd
, "memory region 0x32000800,0xF");
271 sim_io_eprintf (sd
, "Error: Board `%s' unknown.\n", board
);
278 /* check for/establish the a reference program image */
279 if (sim_analyze_program (sd
,
280 (STATE_PROG_ARGV (sd
) != NULL
281 ? *STATE_PROG_ARGV (sd
)
285 sim_module_uninstall (sd
);
289 /* establish any remaining configuration options */
290 if (sim_config (sd
) != SIM_RC_OK
)
292 sim_module_uninstall (sd
);
296 if (sim_post_argv_init (sd
) != SIM_RC_OK
)
298 /* Uninstall the modules to avoid memory leaks,
299 file descriptor leaks, etc. */
300 sim_module_uninstall (sd
);
305 /* set machine specific configuration */
306 /* STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
307 /* | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
309 /* CPU specific initialization. */
310 for (i
= 0; i
< MAX_NR_PROCESSORS
; ++i
)
312 SIM_CPU
*cpu
= STATE_CPU (sd
, i
);
314 CPU_REG_FETCH (cpu
) = mn10300_reg_fetch
;
315 CPU_REG_STORE (cpu
) = mn10300_reg_store
;
316 CPU_PC_FETCH (cpu
) = mn10300_pc_get
;
317 CPU_PC_STORE (cpu
) = mn10300_pc_set
;
324 sim_create_inferior (SIM_DESC sd
,
325 struct bfd
*prog_bfd
,
329 memset (&State
, 0, sizeof (State
));
330 if (prog_bfd
!= NULL
) {
331 PC
= bfd_get_start_address (prog_bfd
);
335 CPU_PC_SET (STATE_CPU (sd
, 0), (unsigned64
) PC
);
337 if (STATE_ARCHITECTURE (sd
)->mach
== bfd_mach_am33_2
)
343 /* FIXME These would more efficient to use than load_mem/store_mem,
344 but need to be changed to use the memory map. */
347 mn10300_reg_fetch (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
349 reg_t reg
= State
.regs
[rn
];
359 mn10300_reg_store (SIM_CPU
*cpu
, int rn
, unsigned char *memory
, int length
)
362 State
.regs
[rn
] = (a
[3] << 24) + (a
[2] << 16) + (a
[1] << 8) + a
[0];
367 mn10300_core_signal (SIM_DESC sd
,
373 transfer_type transfer
,
374 sim_core_signals sig
)
376 const char *copy
= (transfer
== read_transfer
? "read" : "write");
377 address_word ip
= CIA_ADDR (cia
);
381 case sim_core_unmapped_signal
:
382 sim_io_eprintf (sd
, "mn10300-core: %d byte %s to unmapped address 0x%lx at 0x%lx\n",
384 (unsigned long) addr
, (unsigned long) ip
);
385 program_interrupt(sd
, cpu
, cia
, SIM_SIGSEGV
);
388 case sim_core_unaligned_signal
:
389 sim_io_eprintf (sd
, "mn10300-core: %d byte %s to unaligned address 0x%lx at 0x%lx\n",
391 (unsigned long) addr
, (unsigned long) ip
);
392 program_interrupt(sd
, cpu
, cia
, SIM_SIGBUS
);
396 sim_engine_abort (sd
, cpu
, cia
,
397 "mn10300_core_signal - internal error - bad switch");
403 program_interrupt (SIM_DESC sd
,
410 static int in_interrupt
= 0;
412 #ifdef SIM_CPU_EXCEPTION_TRIGGER
413 SIM_CPU_EXCEPTION_TRIGGER(sd
,cpu
,cia
);
416 /* avoid infinite recursion */
418 sim_io_printf (sd
, "ERROR: recursion in program_interrupt during software exception dispatch.");
422 /* copy NMI handler code from dv-mn103cpu.c */
423 store_word (SP
- 4, CPU_PC_GET (cpu
));
424 store_half (SP
- 8, PSW
);
426 /* Set the SYSEF flag in NMICR by backdoor method. See
427 dv-mn103int.c:write_icr(). This is necessary because
428 software exceptions are not modelled by actually talking to
429 the interrupt controller, so it cannot set its own SYSEF
431 if ((NULL
!= board
) && (strcmp(board
, BOARD_AM32
) == 0))
432 store_byte (0x34000103, 0x04);
437 CPU_PC_SET (cpu
, 0x40000008);
440 sim_engine_halt(sd
, cpu
, NULL
, cia
, sim_stopped
, sig
);
445 mn10300_cpu_exception_trigger(SIM_DESC sd
, sim_cpu
* cpu
, address_word cia
)
449 if(State
.exc_suspended
> 0)
450 sim_io_eprintf(sd
, "Warning, nested exception triggered (%d)\n", State
.exc_suspended
);
452 CPU_PC_SET (cpu
, cia
);
453 memcpy(State
.exc_trigger_regs
, State
.regs
, sizeof(State
.exc_trigger_regs
));
454 State
.exc_suspended
= 0;
458 mn10300_cpu_exception_suspend(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
462 if(State
.exc_suspended
> 0)
463 sim_io_eprintf(sd
, "Warning, nested exception signal (%d then %d)\n",
464 State
.exc_suspended
, exception
);
466 memcpy(State
.exc_suspend_regs
, State
.regs
, sizeof(State
.exc_suspend_regs
));
467 memcpy(State
.regs
, State
.exc_trigger_regs
, sizeof(State
.regs
));
468 CPU_PC_SET (cpu
, PC
); /* copy PC back from new State.regs */
469 State
.exc_suspended
= exception
;
473 mn10300_cpu_exception_resume(SIM_DESC sd
, sim_cpu
* cpu
, int exception
)
477 if(exception
== 0 && State
.exc_suspended
> 0)
479 if(State
.exc_suspended
!= SIGTRAP
) /* warn not for breakpoints */
480 sim_io_eprintf(sd
, "Warning, resuming but ignoring pending exception signal (%d)\n",
481 State
.exc_suspended
);
483 else if(exception
!= 0 && State
.exc_suspended
> 0)
485 if(exception
!= State
.exc_suspended
)
486 sim_io_eprintf(sd
, "Warning, resuming with mismatched exception signal (%d vs %d)\n",
487 State
.exc_suspended
, exception
);
489 memcpy(State
.regs
, State
.exc_suspend_regs
, sizeof(State
.regs
));
490 CPU_PC_SET (cpu
, PC
); /* copy PC back from new State.regs */
492 else if(exception
!= 0 && State
.exc_suspended
== 0)
494 sim_io_eprintf(sd
, "Warning, ignoring spontanous exception signal (%d)\n", exception
);
496 State
.exc_suspended
= 0;
499 /* This is called when an FP instruction is issued when the FP unit is
500 disabled, i.e., the FE bit of PSW is zero. It raises interrupt
503 fpu_disabled_exception (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
)
505 sim_io_eprintf(sd
, "FPU disabled exception\n");
506 program_interrupt (sd
, cpu
, cia
, SIM_SIGFPE
);
509 /* This is called when the FP unit is enabled but one of the
510 unimplemented insns is issued. It raises interrupt code 0x1c8. */
512 fpu_unimp_exception (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
)
514 sim_io_eprintf(sd
, "Unimplemented FPU instruction exception\n");
515 program_interrupt (sd
, cpu
, cia
, SIM_SIGFPE
);
518 /* This is called at the end of any FP insns that may have triggered
519 FP exceptions. If no exception is enabled, it returns immediately.
520 Otherwise, it raises an exception code 0x1d0. */
522 fpu_check_signal_exception (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
)
524 if ((FPCR
& EC_MASK
) == 0)
527 sim_io_eprintf(sd
, "FPU %s%s%s%s%s exception\n",
528 (FPCR
& EC_V
) ? "V" : "",
529 (FPCR
& EC_Z
) ? "Z" : "",
530 (FPCR
& EC_O
) ? "O" : "",
531 (FPCR
& EC_U
) ? "U" : "",
532 (FPCR
& EC_I
) ? "I" : "");
533 program_interrupt (sd
, cpu
, cia
, SIM_SIGFPE
);
536 /* Convert a 32-bit single-precision FP value in the target platform
537 format to a sim_fpu value. */
539 reg2val_32 (const void *reg
, sim_fpu
*val
)
541 FS2FPU (*(reg_t
*)reg
, *val
);
544 /* Round the given sim_fpu value to single precision, following the
545 target platform rounding and denormalization conventions. On
546 AM33/2.0, round_near is the only rounding mode. */
548 round_32 (sim_fpu
*val
)
550 return sim_fpu_round_32 (val
, sim_fpu_round_near
, sim_fpu_denorm_zero
);
553 /* Convert a sim_fpu value to the 32-bit single-precision target
556 val2reg_32 (const sim_fpu
*val
, void *reg
)
558 FPU2FS (*val
, *(reg_t
*)reg
);
561 /* Define the 32-bit single-precision conversion and rounding uniform
563 const struct fp_prec_t
565 reg2val_32
, round_32
, val2reg_32
568 /* Convert a 64-bit double-precision FP value in the target platform
569 format to a sim_fpu value. */
571 reg2val_64 (const void *reg
, sim_fpu
*val
)
573 FD2FPU (*(dword
*)reg
, *val
);
576 /* Round the given sim_fpu value to double precision, following the
577 target platform rounding and denormalization conventions. On
578 AM33/2.0, round_near is the only rounding mode. */
580 round_64 (sim_fpu
*val
)
582 return sim_fpu_round_64 (val
, sim_fpu_round_near
, sim_fpu_denorm_zero
);
585 /* Convert a sim_fpu value to the 64-bit double-precision target
588 val2reg_64 (const sim_fpu
*val
, void *reg
)
590 FPU2FD (*val
, *(dword
*)reg
);
593 /* Define the 64-bit single-precision conversion and rounding uniform
595 const struct fp_prec_t
597 reg2val_64
, round_64
, val2reg_64
600 /* Define shortcuts to the uniform interface operations. */
601 #define REG2VAL(reg,val) (*ops->reg2val) (reg,val)
602 #define ROUND(val) (*ops->round) (val)
603 #define VAL2REG(val,reg) (*ops->val2reg) (val,reg)
605 /* Check whether overflow, underflow or inexact exceptions should be
608 fpu_status_ok (sim_fpu_status stat
)
610 if ((stat
& sim_fpu_status_overflow
)
613 else if ((stat
& (sim_fpu_status_underflow
| sim_fpu_status_denorm
))
616 else if ((stat
& (sim_fpu_status_inexact
| sim_fpu_status_rounded
))
619 else if (stat
& ~ (sim_fpu_status_overflow
620 | sim_fpu_status_underflow
621 | sim_fpu_status_denorm
622 | sim_fpu_status_inexact
623 | sim_fpu_status_rounded
))
630 /* Implement a 32/64 bit reciprocal square root, signaling FP
631 exceptions when appropriate. */
633 fpu_rsqrt (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
634 const void *reg_in
, void *reg_out
, const struct fp_prec_t
*ops
)
636 sim_fpu in
, med
, out
;
638 REG2VAL (reg_in
, &in
);
641 switch (sim_fpu_is (&in
))
643 case SIM_FPU_IS_SNAN
:
644 case SIM_FPU_IS_NNUMBER
:
645 case SIM_FPU_IS_NINF
:
649 VAL2REG (&sim_fpu_qnan
, reg_out
);
652 case SIM_FPU_IS_QNAN
:
653 VAL2REG (&sim_fpu_qnan
, reg_out
);
656 case SIM_FPU_IS_PINF
:
657 VAL2REG (&sim_fpu_zero
, reg_out
);
660 case SIM_FPU_IS_PNUMBER
:
662 /* Since we don't have a function to compute rsqrt directly,
664 sim_fpu_status stat
= 0;
665 stat
|= sim_fpu_sqrt (&med
, &in
);
666 stat
|= sim_fpu_inv (&out
, &med
);
667 stat
|= ROUND (&out
);
668 if (fpu_status_ok (stat
))
669 VAL2REG (&out
, reg_out
);
673 case SIM_FPU_IS_NZERO
:
674 case SIM_FPU_IS_PZERO
:
679 /* Generate an INF with the same sign. */
680 sim_fpu_inv (&out
, &in
);
681 VAL2REG (&out
, reg_out
);
689 fpu_check_signal_exception (sd
, cpu
, cia
);
697 case SIM_FPU_IS_SNAN
:
698 case SIM_FPU_IS_QNAN
:
701 case SIM_FPU_IS_NINF
:
702 case SIM_FPU_IS_NNUMBER
:
703 case SIM_FPU_IS_NDENORM
:
706 case SIM_FPU_IS_PINF
:
707 case SIM_FPU_IS_PNUMBER
:
708 case SIM_FPU_IS_PDENORM
:
711 case SIM_FPU_IS_NZERO
:
712 case SIM_FPU_IS_PZERO
:
720 /* Implement a 32/64 bit FP compare, setting the FPCR status and/or
721 exception bits as specified. */
723 fpu_cmp (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
724 const void *reg_in1
, const void *reg_in2
,
725 const struct fp_prec_t
*ops
)
729 REG2VAL (reg_in1
, &m
);
730 REG2VAL (reg_in2
, &n
);
735 if (sim_fpu_is_snan (&m
) || sim_fpu_is_snan (&n
))
743 FPCR
|= cmp2fcc (sim_fpu_cmp (&m
, &n
));
745 fpu_check_signal_exception (sd
, cpu
, cia
);
748 /* Implement a 32/64 bit FP add, setting FP exception bits when
751 fpu_add (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
752 const void *reg_in1
, const void *reg_in2
,
753 void *reg_out
, const struct fp_prec_t
*ops
)
757 REG2VAL (reg_in1
, &m
);
758 REG2VAL (reg_in2
, &n
);
762 if (sim_fpu_is_snan (&m
) || sim_fpu_is_snan (&n
)
763 || (sim_fpu_is (&m
) == SIM_FPU_IS_PINF
764 && sim_fpu_is (&n
) == SIM_FPU_IS_NINF
)
765 || (sim_fpu_is (&m
) == SIM_FPU_IS_NINF
766 && sim_fpu_is (&n
) == SIM_FPU_IS_PINF
))
771 VAL2REG (&sim_fpu_qnan
, reg_out
);
775 sim_fpu_status stat
= sim_fpu_add (&r
, &m
, &n
);
777 if (fpu_status_ok (stat
))
778 VAL2REG (&r
, reg_out
);
781 fpu_check_signal_exception (sd
, cpu
, cia
);
784 /* Implement a 32/64 bit FP sub, setting FP exception bits when
787 fpu_sub (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
788 const void *reg_in1
, const void *reg_in2
,
789 void *reg_out
, const struct fp_prec_t
*ops
)
793 REG2VAL (reg_in1
, &m
);
794 REG2VAL (reg_in2
, &n
);
798 if (sim_fpu_is_snan (&m
) || sim_fpu_is_snan (&n
)
799 || (sim_fpu_is (&m
) == SIM_FPU_IS_PINF
800 && sim_fpu_is (&n
) == SIM_FPU_IS_PINF
)
801 || (sim_fpu_is (&m
) == SIM_FPU_IS_NINF
802 && sim_fpu_is (&n
) == SIM_FPU_IS_NINF
))
807 VAL2REG (&sim_fpu_qnan
, reg_out
);
811 sim_fpu_status stat
= sim_fpu_sub (&r
, &m
, &n
);
813 if (fpu_status_ok (stat
))
814 VAL2REG (&r
, reg_out
);
817 fpu_check_signal_exception (sd
, cpu
, cia
);
820 /* Implement a 32/64 bit FP mul, setting FP exception bits when
823 fpu_mul (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
824 const void *reg_in1
, const void *reg_in2
,
825 void *reg_out
, const struct fp_prec_t
*ops
)
829 REG2VAL (reg_in1
, &m
);
830 REG2VAL (reg_in2
, &n
);
834 if (sim_fpu_is_snan (&m
) || sim_fpu_is_snan (&n
)
835 || (sim_fpu_is_infinity (&m
) && sim_fpu_is_zero (&n
))
836 || (sim_fpu_is_zero (&m
) && sim_fpu_is_infinity (&n
)))
841 VAL2REG (&sim_fpu_qnan
, reg_out
);
845 sim_fpu_status stat
= sim_fpu_mul (&r
, &m
, &n
);
847 if (fpu_status_ok (stat
))
848 VAL2REG (&r
, reg_out
);
851 fpu_check_signal_exception (sd
, cpu
, cia
);
854 /* Implement a 32/64 bit FP div, setting FP exception bits when
857 fpu_div (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
858 const void *reg_in1
, const void *reg_in2
,
859 void *reg_out
, const struct fp_prec_t
*ops
)
863 REG2VAL (reg_in1
, &m
);
864 REG2VAL (reg_in2
, &n
);
868 if (sim_fpu_is_snan (&m
) || sim_fpu_is_snan (&n
)
869 || (sim_fpu_is_infinity (&m
) && sim_fpu_is_infinity (&n
))
870 || (sim_fpu_is_zero (&m
) && sim_fpu_is_zero (&n
)))
875 VAL2REG (&sim_fpu_qnan
, reg_out
);
877 else if (sim_fpu_is_number (&m
) && sim_fpu_is_zero (&n
)
882 sim_fpu_status stat
= sim_fpu_div (&r
, &m
, &n
);
884 if (fpu_status_ok (stat
))
885 VAL2REG (&r
, reg_out
);
888 fpu_check_signal_exception (sd
, cpu
, cia
);
891 /* Implement a 32/64 bit FP madd, setting FP exception bits when
894 fpu_fmadd (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
895 const void *reg_in1
, const void *reg_in2
, const void *reg_in3
,
896 void *reg_out
, const struct fp_prec_t
*ops
)
898 sim_fpu m1
, m2
, m
, n
, r
;
900 REG2VAL (reg_in1
, &m1
);
901 REG2VAL (reg_in2
, &m2
);
902 REG2VAL (reg_in3
, &n
);
907 if (sim_fpu_is_snan (&m1
) || sim_fpu_is_snan (&m2
) || sim_fpu_is_snan (&n
)
908 || (sim_fpu_is_infinity (&m1
) && sim_fpu_is_zero (&m2
))
909 || (sim_fpu_is_zero (&m1
) && sim_fpu_is_infinity (&m2
)))
915 VAL2REG (&sim_fpu_qnan
, reg_out
);
919 sim_fpu_status stat
= sim_fpu_mul (&m
, &m1
, &m2
);
921 if (sim_fpu_is_infinity (&m
) && sim_fpu_is_infinity (&n
)
922 && sim_fpu_sign (&m
) != sim_fpu_sign (&n
))
923 goto invalid_operands
;
925 stat
|= sim_fpu_add (&r
, &m
, &n
);
927 if (fpu_status_ok (stat
))
928 VAL2REG (&r
, reg_out
);
931 fpu_check_signal_exception (sd
, cpu
, cia
);
934 /* Implement a 32/64 bit FP msub, setting FP exception bits when
937 fpu_fmsub (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
938 const void *reg_in1
, const void *reg_in2
, const void *reg_in3
,
939 void *reg_out
, const struct fp_prec_t
*ops
)
941 sim_fpu m1
, m2
, m
, n
, r
;
943 REG2VAL (reg_in1
, &m1
);
944 REG2VAL (reg_in2
, &m2
);
945 REG2VAL (reg_in3
, &n
);
950 if (sim_fpu_is_snan (&m1
) || sim_fpu_is_snan (&m2
) || sim_fpu_is_snan (&n
)
951 || (sim_fpu_is_infinity (&m1
) && sim_fpu_is_zero (&m2
))
952 || (sim_fpu_is_zero (&m1
) && sim_fpu_is_infinity (&m2
)))
958 VAL2REG (&sim_fpu_qnan
, reg_out
);
962 sim_fpu_status stat
= sim_fpu_mul (&m
, &m1
, &m2
);
964 if (sim_fpu_is_infinity (&m
) && sim_fpu_is_infinity (&n
)
965 && sim_fpu_sign (&m
) == sim_fpu_sign (&n
))
966 goto invalid_operands
;
968 stat
|= sim_fpu_sub (&r
, &m
, &n
);
970 if (fpu_status_ok (stat
))
971 VAL2REG (&r
, reg_out
);
974 fpu_check_signal_exception (sd
, cpu
, cia
);
977 /* Implement a 32/64 bit FP nmadd, setting FP exception bits when
980 fpu_fnmadd (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
981 const void *reg_in1
, const void *reg_in2
, const void *reg_in3
,
982 void *reg_out
, const struct fp_prec_t
*ops
)
984 sim_fpu m1
, m2
, m
, mm
, n
, r
;
986 REG2VAL (reg_in1
, &m1
);
987 REG2VAL (reg_in2
, &m2
);
988 REG2VAL (reg_in3
, &n
);
993 if (sim_fpu_is_snan (&m1
) || sim_fpu_is_snan (&m2
) || sim_fpu_is_snan (&n
)
994 || (sim_fpu_is_infinity (&m1
) && sim_fpu_is_zero (&m2
))
995 || (sim_fpu_is_zero (&m1
) && sim_fpu_is_infinity (&m2
)))
1001 VAL2REG (&sim_fpu_qnan
, reg_out
);
1005 sim_fpu_status stat
= sim_fpu_mul (&m
, &m1
, &m2
);
1007 if (sim_fpu_is_infinity (&m
) && sim_fpu_is_infinity (&n
)
1008 && sim_fpu_sign (&m
) == sim_fpu_sign (&n
))
1009 goto invalid_operands
;
1011 stat
|= sim_fpu_neg (&mm
, &m
);
1012 stat
|= sim_fpu_add (&r
, &mm
, &n
);
1014 if (fpu_status_ok (stat
))
1015 VAL2REG (&r
, reg_out
);
1018 fpu_check_signal_exception (sd
, cpu
, cia
);
1021 /* Implement a 32/64 bit FP nmsub, setting FP exception bits when
1024 fpu_fnmsub (SIM_DESC sd
, sim_cpu
*cpu
, sim_cia cia
,
1025 const void *reg_in1
, const void *reg_in2
, const void *reg_in3
,
1026 void *reg_out
, const struct fp_prec_t
*ops
)
1028 sim_fpu m1
, m2
, m
, mm
, n
, r
;
1030 REG2VAL (reg_in1
, &m1
);
1031 REG2VAL (reg_in2
, &m2
);
1032 REG2VAL (reg_in3
, &n
);
1037 if (sim_fpu_is_snan (&m1
) || sim_fpu_is_snan (&m2
) || sim_fpu_is_snan (&n
)
1038 || (sim_fpu_is_infinity (&m1
) && sim_fpu_is_zero (&m2
))
1039 || (sim_fpu_is_zero (&m1
) && sim_fpu_is_infinity (&m2
)))
1045 VAL2REG (&sim_fpu_qnan
, reg_out
);
1049 sim_fpu_status stat
= sim_fpu_mul (&m
, &m1
, &m2
);
1051 if (sim_fpu_is_infinity (&m
) && sim_fpu_is_infinity (&n
)
1052 && sim_fpu_sign (&m
) != sim_fpu_sign (&n
))
1053 goto invalid_operands
;
1055 stat
|= sim_fpu_neg (&mm
, &m
);
1056 stat
|= sim_fpu_sub (&r
, &mm
, &n
);
1058 if (fpu_status_ok (stat
))
1059 VAL2REG (&r
, reg_out
);
1062 fpu_check_signal_exception (sd
, cpu
, cia
);