sim/mn10300/interp.c

   1 #include <signal.h>
   2
   3 #if WITH_COMMON
   4 #include "sim-main.h"
   5 #include "sim-options.h"
   6 /* start-sanitize-am30 */
   7 #include "sim-hw.h"
   8 /* end-sanitize-am30 */
   9 #else
  10 #include "mn10300_sim.h"
  11 #endif
  12
  13 #include "sysdep.h"
  14 #include "bfd.h"
  15 #include "sim-assert.h"
  16
  17
  18 #ifdef HAVE_STDLIB_H
  19 #include <stdlib.h>
  20 #endif
  21
  22 #ifdef HAVE_STRING_H
  23 #include <string.h>
  24 #else
  25 #ifdef HAVE_STRINGS_H
  26 #include <strings.h>
  27 #endif
  28 #endif
  29
  30 #include "bfd.h"
  31
  32 #ifndef INLINE
  33 #ifdef __GNUC__
  34 #define INLINE inline
  35 #else
  36 #define INLINE
  37 #endif
  38 #endif
  39
  40
  41 host_callback *mn10300_callback;
  42 int mn10300_debug;
  43
  44 #if WITH_COMMON
  45 #else
  46 static void dispatch PARAMS ((uint32, uint32, int));
  47 static long hash PARAMS ((long));
  48 static void init_system PARAMS ((void));
  49
  50 static SIM_OPEN_KIND sim_kind;
  51 static char *myname;
  52 #define MAX_HASH  127
  53
  54 struct hash_entry
  55 {
  56   struct hash_entry *next;
  57   long opcode;
  58   long mask;
  59   struct simops *ops;
  60 #ifdef HASH_STAT
  61   unsigned long count;
  62 #endif
  63 };
  64
  65 static int max_mem = 0;
  66 struct hash_entry hash_table[MAX_HASH+1];
  67
  68
  69 /* This probably doesn't do a very good job at bucket filling, but
  70    it's simple... */
  71 static INLINE long
  72 hash(insn)
  73      long insn;
  74 {
  75   /* These are one byte insns, we special case these since, in theory,
  76      they should be the most heavily used.  */
  77   if ((insn & 0xffffff00) == 0)
  78     {
  79       switch (insn & 0xf0)
  80         {
  81           case 0x00:
  82             return 0x70;
  83
  84           case 0x40:
  85             return 0x71;
  86
  87           case 0x10:
  88             return 0x72;
  89
  90           case 0x30:
  91             return 0x73;
  92
  93           case 0x50:
  94             return 0x74;
  95
  96           case 0x60:
  97             return 0x75;
  98
  99           case 0x70:
 100             return 0x76;
 101
 102           case 0x80:
 103             return 0x77;
 104
 105           case 0x90:
 106             return 0x78;
 107
 108           case 0xa0:
 109             return 0x79;
 110
 111           case 0xb0:
 112             return 0x7a;
 113
 114           case 0xe0:
 115             return 0x7b;
 116
 117           default:
 118             return 0x7c;
 119         }
 120     }
 121
 122   /* These are two byte insns */
 123   if ((insn & 0xffff0000) == 0)
 124     {
 125       if ((insn & 0xf000) == 0x2000
 126           || (insn & 0xf000) == 0x5000)
 127         return ((insn & 0xfc00) >> 8) & 0x7f;
 128
 129       if ((insn & 0xf000) == 0x4000)
 130         return ((insn & 0xf300) >> 8) & 0x7f;
 131
 132       if ((insn & 0xf000) == 0x8000
 133           || (insn & 0xf000) == 0x9000
 134           || (insn & 0xf000) == 0xa000
 135           || (insn & 0xf000) == 0xb000)
 136         return ((insn & 0xf000) >> 8) & 0x7f;
 137
 138       if ((insn & 0xff00) == 0xf000
 139           || (insn & 0xff00) == 0xf100
 140           || (insn & 0xff00) == 0xf200
 141           || (insn & 0xff00) == 0xf500
 142           || (insn & 0xff00) == 0xf600)
 143         return ((insn & 0xfff0) >> 4) & 0x7f;
 144
 145       if ((insn & 0xf000) == 0xc000)
 146         return ((insn & 0xff00) >> 8) & 0x7f;
 147
 148       return ((insn & 0xffc0) >> 6) & 0x7f;
 149     }
 150
 151   /* These are three byte insns.  */
 152   if ((insn & 0xff000000) == 0)
 153     {
 154       if ((insn & 0xf00000) == 0x000000)
 155         return ((insn & 0xf30000) >> 16) & 0x7f;
 156
 157       if ((insn & 0xf00000) == 0x200000
 158           || (insn & 0xf00000) == 0x300000)
 159         return ((insn & 0xfc0000) >> 16) & 0x7f;
 160
 161       if ((insn & 0xff0000) == 0xf80000)
 162         return ((insn & 0xfff000) >> 12) & 0x7f;
 163
 164       if ((insn & 0xff0000) == 0xf90000)
 165         return ((insn & 0xfffc00) >> 10) & 0x7f;
 166
 167       return ((insn & 0xff0000) >> 16) & 0x7f;
 168     }
 169
 170   /* These are four byte or larger insns.  */
 171   if ((insn & 0xf0000000) == 0xf0000000)
 172     return ((insn & 0xfff00000) >> 20) & 0x7f;
 173
 174   return ((insn & 0xff000000) >> 24) & 0x7f;
 175 }
 176
 177 static INLINE void
 178 dispatch (insn, extension, length)
 179      uint32 insn;
 180      uint32 extension;
 181      int length;
 182 {
 183   struct hash_entry *h;
 184
 185   h = &hash_table[hash(insn)];
 186
 187   while ((insn & h->mask) != h->opcode
 188           || (length != h->ops->length))
 189     {
 190       if (!h->next)
 191         {
 192           (*mn10300_callback->printf_filtered) (mn10300_callback,
 193             "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC);
 194           exit(1);
 195         }
 196       h = h->next;
 197     }
 198
 199
 200 #ifdef HASH_STAT
 201   h->count++;
 202 #endif
 203
 204   /* Now call the right function.  */
 205   (h->ops->func)(insn, extension);
 206   PC += length;
 207 }
 208
 209 void
 210 sim_size (power)
 211      int power;
 212
 213 {
 214   if (State.mem)
 215     free (State.mem);
 216
 217   max_mem = 1 << power;
 218   State.mem = (uint8 *) calloc (1,  1 << power);
 219   if (!State.mem)
 220     {
 221       (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n");
 222       exit (1);
 223     }
 224 }
 225
 226 static void
 227 init_system ()
 228 {
 229   if (!State.mem)
 230     sim_size(19);
 231 }
 232
 233 int
 234 sim_write (sd, addr, buffer, size)
 235      SIM_DESC sd;
 236      SIM_ADDR addr;
 237      unsigned char *buffer;
 238      int size;
 239 {
 240   int i;
 241
 242   init_system ();
 243
 244   for (i = 0; i < size; i++)
 245     store_byte (addr + i, buffer[i]);
 246
 247   return size;
 248 }
 249
 250 /* Compare two opcode table entries for qsort.  */
 251 static int
 252 compare_simops (arg1, arg2)
 253      const PTR arg1;
 254      const PTR arg2;
 255 {
 256   unsigned long code1 = ((struct simops *)arg1)->opcode;
 257   unsigned long code2 = ((struct simops *)arg2)->opcode;
 258
 259   if (code1 < code2)
 260     return -1;
 261   if (code2 < code1)
 262     return 1;
 263   return 0;
 264 }
 265
 266
 267 SIM_DESC
 268 sim_open (kind, cb, abfd, argv)
 269      SIM_OPEN_KIND kind;
 270      host_callback *cb;
 271      struct _bfd *abfd;
 272      char **argv;
 273 {
 274   struct simops *s;
 275   struct hash_entry *h;
 276   char **p;
 277   int i;
 278
 279   mn10300_callback = cb;
 280
 281   /* Sort the opcode array from smallest opcode to largest.
 282      This will generally improve simulator performance as the smaller
 283      opcodes are generally preferred to the larger opcodes.  */
 284   for (i = 0, s = Simops; s->func; s++, i++)
 285     ;
 286   qsort (Simops, i, sizeof (Simops[0]), compare_simops);
 287
 288   sim_kind = kind;
 289   myname = argv[0];
 290
 291   for (p = argv + 1; *p; ++p)
 292     {
 293       if (strcmp (*p, "-E") == 0)
 294         ++p; /* ignore endian spec */
 295       else
 296 #ifdef DEBUG
 297       if (strcmp (*p, "-t") == 0)
 298         mn10300_debug = DEBUG;
 299       else
 300 #endif
 301         (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p);
 302     }
 303
 304  /* put all the opcodes in the hash table */
 305   for (s = Simops; s->func; s++)
 306     {
 307       h = &hash_table[hash(s->opcode)];
 308
 309       /* go to the last entry in the chain */
 310       while (h->next)
 311         {
 312           /* Don't insert the same opcode more than once.  */
 313           if (h->opcode == s->opcode
 314               && h->mask == s->mask
 315               && h->ops == s)
 316             break;
 317           else
 318             h = h->next;
 319         }
 320
 321       /* Don't insert the same opcode more than once.  */
 322       if (h->opcode == s->opcode
 323           && h->mask == s->mask
 324           && h->ops == s)
 325         continue;
 326
 327       if (h->ops)
 328         {
 329           h->next = calloc(1,sizeof(struct hash_entry));
 330           h = h->next;
 331         }
 332       h->ops = s;
 333       h->mask = s->mask;
 334       h->opcode = s->opcode;
 335 #if HASH_STAT
 336       h->count = 0;
 337 #endif
 338     }
 339
 340
 341   /* fudge our descriptor for now */
 342   return (SIM_DESC) 1;
 343 }
 344
 345
 346 void
 347 sim_close (sd, quitting)
 348      SIM_DESC sd;
 349      int quitting;
 350 {
 351   /* nothing to do */
 352 }
 353
 354 void
 355 sim_set_profile (n)
 356      int n;
 357 {
 358   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n);
 359 }
 360
 361 void
 362 sim_set_profile_size (n)
 363      int n;
 364 {
 365   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n);
 366 }
 367
 368 int
 369 sim_stop (sd)
 370      SIM_DESC sd;
 371 {
 372   return 0;
 373 }
 374
 375 void
 376 sim_resume (sd, step, siggnal)
 377      SIM_DESC sd;
 378      int step, siggnal;
 379 {
 380   uint32 inst;
 381   reg_t oldpc;
 382   struct hash_entry *h;
 383
 384   if (step)
 385     State.exception = SIGTRAP;
 386   else
 387     State.exception = 0;
 388
 389   State.exited = 0;
 390
 391   do
 392     {
 393       unsigned long insn, extension;
 394
 395       /* Fetch the current instruction.  */
 396       inst = load_mem_big (PC, 2);
 397       oldpc = PC;
 398
 399       /* Using a giant case statement may seem like a waste because of the
 400         code/rodata size the table itself will consume.  However, using
 401         a giant case statement speeds up the simulator by 10-15% by avoiding
 402         cascading if/else statements or cascading case statements.  */
 403
 404       switch ((inst >> 8) & 0xff)
 405         {
 406           /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0
 407              which must be handled specially.  */
 408           case 0x00:
 409           case 0x04:
 410           case 0x08:
 411           case 0x0c:
 412           case 0x10:
 413           case 0x11:
 414           case 0x12:
 415           case 0x13:
 416           case 0x14:
 417           case 0x15:
 418           case 0x16:
 419           case 0x17:
 420           case 0x18:
 421           case 0x19:
 422           case 0x1a:
 423           case 0x1b:
 424           case 0x1c:
 425           case 0x1d:
 426           case 0x1e:
 427           case 0x1f:
 428           case 0x3c:
 429           case 0x3d:
 430           case 0x3e:
 431           case 0x3f:
 432           case 0x40:
 433           case 0x41:
 434           case 0x44:
 435           case 0x45:
 436           case 0x48:
 437           case 0x49:
 438           case 0x4c:
 439           case 0x4d:
 440           case 0x50:
 441           case 0x51:
 442           case 0x52:
 443           case 0x53:
 444           case 0x54:
 445           case 0x55:
 446           case 0x56:
 447           case 0x57:
 448           case 0x60:
 449           case 0x61:
 450           case 0x62:
 451           case 0x63:
 452           case 0x64:
 453           case 0x65:
 454           case 0x66:
 455           case 0x67:
 456           case 0x68:
 457           case 0x69:
 458           case 0x6a:
 459           case 0x6b:
 460           case 0x6c:
 461           case 0x6d:
 462           case 0x6e:
 463           case 0x6f:
 464           case 0x70:
 465           case 0x71:
 466           case 0x72:
 467           case 0x73:
 468           case 0x74:
 469           case 0x75:
 470           case 0x76:
 471           case 0x77:
 472           case 0x78:
 473           case 0x79:
 474           case 0x7a:
 475           case 0x7b:
 476           case 0x7c:
 477           case 0x7d:
 478           case 0x7e:
 479           case 0x7f:
 480           case 0xcb:
 481           case 0xd0:
 482           case 0xd1:
 483           case 0xd2:
 484           case 0xd3:
 485           case 0xd4:
 486           case 0xd5:
 487           case 0xd6:
 488           case 0xd7:
 489           case 0xd8:
 490           case 0xd9:
 491           case 0xda:
 492           case 0xdb:
 493           case 0xe0:
 494           case 0xe1:
 495           case 0xe2:
 496           case 0xe3:
 497           case 0xe4:
 498           case 0xe5:
 499           case 0xe6:
 500           case 0xe7:
 501           case 0xe8:
 502           case 0xe9:
 503           case 0xea:
 504           case 0xeb:
 505           case 0xec:
 506           case 0xed:
 507           case 0xee:
 508           case 0xef:
 509           case 0xff:
 510             insn = (inst >> 8) & 0xff;
 511             extension = 0;
 512             dispatch (insn, extension, 1);
 513             break;
 514
 515           /* Special cases where dm == dn is used to encode a different
 516              instruction.  */
 517           case 0x80:
 518           case 0x85:
 519           case 0x8a:
 520           case 0x8f:
 521           case 0x90:
 522           case 0x95:
 523           case 0x9a:
 524           case 0x9f:
 525           case 0xa0:
 526           case 0xa5:
 527           case 0xaa:
 528           case 0xaf:
 529           case 0xb0:
 530           case 0xb5:
 531           case 0xba:
 532           case 0xbf:
 533             insn = inst;
 534             extension = 0;
 535             dispatch (insn, extension, 2);
 536             break;
 537
 538           case 0x81:
 539           case 0x82:
 540           case 0x83:
 541           case 0x84:
 542           case 0x86:
 543           case 0x87:
 544           case 0x88:
 545           case 0x89:
 546           case 0x8b:
 547           case 0x8c:
 548           case 0x8d:
 549           case 0x8e:
 550           case 0x91:
 551           case 0x92:
 552           case 0x93:
 553           case 0x94:
 554           case 0x96:
 555           case 0x97:
 556           case 0x98:
 557           case 0x99:
 558           case 0x9b:
 559           case 0x9c:
 560           case 0x9d:
 561           case 0x9e:
 562           case 0xa1:
 563           case 0xa2:
 564           case 0xa3:
 565           case 0xa4:
 566           case 0xa6:
 567           case 0xa7:
 568           case 0xa8:
 569           case 0xa9:
 570           case 0xab:
 571           case 0xac:
 572           case 0xad:
 573           case 0xae:
 574           case 0xb1:
 575           case 0xb2:
 576           case 0xb3:
 577           case 0xb4:
 578           case 0xb6:
 579           case 0xb7:
 580           case 0xb8:
 581           case 0xb9:
 582           case 0xbb:
 583           case 0xbc:
 584           case 0xbd:
 585           case 0xbe:
 586             insn = (inst >> 8) & 0xff;
 587             extension = 0;
 588           dispatch (insn, extension, 1);
 589           break;
 590
 591           /* The two byte instructions.  */
 592           case 0x20:
 593           case 0x21:
 594           case 0x22:
 595           case 0x23:
 596           case 0x28:
 597           case 0x29:
 598           case 0x2a:
 599           case 0x2b:
 600           case 0x42:
 601           case 0x43:
 602           case 0x46:
 603           case 0x47:
 604           case 0x4a:
 605           case 0x4b:
 606           case 0x4e:
 607           case 0x4f:
 608           case 0x58:
 609           case 0x59:
 610           case 0x5a:
 611           case 0x5b:
 612           case 0x5c:
 613           case 0x5d:
 614           case 0x5e:
 615           case 0x5f:
 616           case 0xc0:
 617           case 0xc1:
 618           case 0xc2:
 619           case 0xc3:
 620           case 0xc4:
 621           case 0xc5:
 622           case 0xc6:
 623           case 0xc7:
 624           case 0xc8:
 625           case 0xc9:
 626           case 0xca:
 627           case 0xce:
 628           case 0xcf:
 629           case 0xf0:
 630           case 0xf1:
 631           case 0xf2:
 632           case 0xf3:
 633           case 0xf4:
 634           case 0xf5:
 635           case 0xf6:
 636             insn = inst;
 637             extension = 0;
 638             dispatch (insn, extension, 2);
 639             break;
 640
 641           /* The three byte insns with a 16bit operand in little endian
 642              format.  */
 643           case 0x01:
 644           case 0x02:
 645           case 0x03:
 646           case 0x05:
 647           case 0x06:
 648           case 0x07:
 649           case 0x09:
 650           case 0x0a:
 651           case 0x0b:
 652           case 0x0d:
 653           case 0x0e:
 654           case 0x0f:
 655           case 0x24:
 656           case 0x25:
 657           case 0x26:
 658           case 0x27:
 659           case 0x2c:
 660           case 0x2d:
 661           case 0x2e:
 662           case 0x2f:
 663           case 0x30:
 664           case 0x31:
 665           case 0x32:
 666           case 0x33:
 667           case 0x34:
 668           case 0x35:
 669           case 0x36:
 670           case 0x37:
 671           case 0x38:
 672           case 0x39:
 673           case 0x3a:
 674           case 0x3b:
 675           case 0xcc:
 676             insn = load_byte (PC);
 677             insn <<= 16;
 678             insn |= load_half (PC + 1);
 679             extension = 0;
 680             dispatch (insn, extension, 3);
 681             break;
 682
 683           /* The three byte insns without 16bit operand.  */
 684           case 0xde:
 685           case 0xdf:
 686           case 0xf8:
 687           case 0xf9:
 688             insn = load_mem_big (PC, 3);
 689             extension = 0;
 690             dispatch (insn, extension, 3);
 691             break;
 692
 693           /* Four byte insns.  */
 694           case 0xfa:
 695           case 0xfb:
 696             if ((inst & 0xfffc) == 0xfaf0
 697                 || (inst & 0xfffc) == 0xfaf4
 698                 || (inst & 0xfffc) == 0xfaf8)
 699               insn = load_mem_big (PC, 4);
 700             else
 701               {
 702                 insn = inst;
 703                 insn <<= 16;
 704                 insn |= load_half (PC + 2);
 705                 extension = 0;
 706               }
 707             dispatch (insn, extension, 4);
 708             break;
 709
 710           /* Five byte insns.  */
 711           case 0xcd:
 712             insn = load_byte (PC);
 713             insn <<= 24;
 714             insn |= (load_half (PC + 1) << 8);
 715             insn |= load_byte (PC + 3);
 716             extension = load_byte (PC + 4);
 717             dispatch (insn, extension, 5);
 718             break;
 719
 720           case 0xdc:
 721             insn = load_byte (PC);
 722             insn <<= 24;
 723             extension = load_word (PC + 1);
 724             insn |= (extension & 0xffffff00) >> 8;
 725             extension &= 0xff;
 726             dispatch (insn, extension, 5);
 727             break;
 728
 729           /* Six byte insns.  */
 730           case 0xfc:
 731           case 0xfd:
 732             insn = (inst << 16);
 733             extension = load_word (PC + 2);
 734             insn |= ((extension & 0xffff0000) >> 16);
 735             extension &= 0xffff;
 736             dispatch (insn, extension, 6);
 737             break;
 738
 739           case 0xdd:
 740             insn = load_byte (PC) << 24;
 741             extension = load_word (PC + 1);
 742             insn |= ((extension >> 8) & 0xffffff);
 743             extension = (extension & 0xff) << 16;
 744             extension |= load_byte (PC + 5) << 8;
 745             extension |= load_byte (PC + 6);
 746             dispatch (insn, extension, 7);
 747             break;
 748
 749           case 0xfe:
 750             insn = inst << 16;
 751             extension = load_word (PC + 2);
 752             insn |= ((extension >> 16) & 0xffff);
 753             extension <<= 8;
 754             extension &= 0xffff00;
 755             extension |= load_byte (PC + 6);
 756             dispatch (insn, extension, 7);
 757             break;
 758
 759           default:
 760             abort ();
 761         }
 762     }
 763   while (!State.exception);
 764
 765 #ifdef HASH_STAT
 766   {
 767     int i;
 768     for (i = 0; i < MAX_HASH; i++)
 769       {
 770          struct hash_entry *h;
 771          h = &hash_table[i];
 772
 773          printf("hash 0x%x:\n", i);
 774
 775          while (h)
 776            {
 777              printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
 778              h = h->next;
 779            }
 780
 781          printf("\n\n");
 782       }
 783     fflush (stdout);
 784   }
 785 #endif
 786
 787 }
 788
 789 int
 790 sim_trace (sd)
 791      SIM_DESC sd;
 792 {
 793 #ifdef DEBUG
 794   mn10300_debug = DEBUG;
 795 #endif
 796   sim_resume (sd, 0, 0);
 797   return 1;
 798 }
 799
 800 void
 801 sim_info (sd, verbose)
 802      SIM_DESC sd;
 803      int verbose;
 804 {
 805   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
 806 }
 807
 808 SIM_RC
 809 sim_create_inferior (sd, abfd, argv, env)
 810      SIM_DESC sd;
 811      struct _bfd *abfd;
 812      char **argv;
 813      char **env;
 814 {
 815   if (abfd != NULL)
 816     PC = bfd_get_start_address (abfd);
 817   else
 818     PC = 0;
 819   return SIM_RC_OK;
 820 }
 821
 822 void
 823 sim_set_callbacks (p)
 824      host_callback *p;
 825 {
 826   mn10300_callback = p;
 827 }
 828
 829 /* All the code for exiting, signals, etc needs to be revamped.
 830
 831    This is enough to get c-torture limping though.  */
 832
 833 void
 834 sim_stop_reason (sd, reason, sigrc)
 835      SIM_DESC sd;
 836      enum sim_stop *reason;
 837      int *sigrc;
 838 {
 839   if (State.exited)
 840     *reason = sim_exited;
 841   else
 842     *reason = sim_stopped;
 843   if (State.exception == SIGQUIT)
 844     *sigrc = 0;
 845   else
 846     *sigrc = State.exception;
 847 }
 848
 849 int
 850 sim_read (sd, addr, buffer, size)
 851      SIM_DESC sd;
 852      SIM_ADDR addr;
 853      unsigned char *buffer;
 854      int size;
 855 {
 856   int i;
 857   for (i = 0; i < size; i++)
 858     buffer[i] = load_byte (addr + i);
 859
 860   return size;
 861 }
 862
 863 void
 864 sim_do_command (sd, cmd)
 865      SIM_DESC sd;
 866      char *cmd;
 867 {
 868   (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
 869 }
 870
 871 SIM_RC
 872 sim_load (sd, prog, abfd, from_tty)
 873      SIM_DESC sd;
 874      char *prog;
 875      bfd *abfd;
 876      int from_tty;
 877 {
 878   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
 879   bfd *prog_bfd;
 880
 881   prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
 882                             sim_kind == SIM_OPEN_DEBUG,
 883                             0, sim_write);
 884   if (prog_bfd == NULL)
 885     return SIM_RC_FAIL;
 886   if (abfd == NULL)
 887     bfd_close (prog_bfd);
 888   return SIM_RC_OK;
 889 }
 890 #endif  /* not WITH_COMMON */
 891
 892
 893 #if WITH_COMMON
 894
 895 /* For compatibility */
 896 SIM_DESC simulator;
 897 /* start-sanitize-am30 */
 898 /* Until the tree root gets moved somewhere else */
 899 struct hw *hw;
 900 /* end-sanitize-am30 */
 901
 902 /* These default values correspond to expected usage for the chip.  */
 903
 904 SIM_DESC
 905 sim_open (kind, cb, abfd, argv)
 906      SIM_OPEN_KIND kind;
 907      host_callback *cb;
 908      struct _bfd *abfd;
 909      char **argv;
 910 {
 911   SIM_DESC sd = sim_state_alloc (kind, cb);
 912   mn10300_callback = cb;
 913
 914   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
 915
 916   /* for compatibility */
 917   simulator = sd;
 918
 919   /* FIXME: should be better way of setting up interrupts.  For
 920      moment, only support watchpoints causing a breakpoint (gdb
 921      halt). */
 922   STATE_WATCHPOINTS (sd)->pc = &(PC);
 923   STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
 924   STATE_WATCHPOINTS (sd)->interrupt_handler = NULL;
 925   STATE_WATCHPOINTS (sd)->interrupt_names = NULL;
 926
 927   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
 928     return 0;
 929
 930   /* Allocate core managed memory */
 931   sim_do_command (sd, "memory region 0,0x100000");
 932   sim_do_command (sd, "memory region 0x40000000,0x100000");
 933
 934   /* getopt will print the error message so we just have to exit if this fails.
 935      FIXME: Hmmm...  in the case of gdb we need getopt to call
 936      print_filtered.  */
 937   if (sim_parse_args (sd, argv) != SIM_RC_OK)
 938     {
 939       /* Uninstall the modules to avoid memory leaks,
 940          file descriptor leaks, etc.  */
 941       sim_module_uninstall (sd);
 942       return 0;
 943     }
 944
 945   /* start-sanitize-am30 */
 946   hw = hw_tree_create (sd, "core");
 947   hw_tree_parse (hw, "/");
 948   if (STATE_VERBOSE_P (sd))
 949     hw_tree_parse (hw, "/trace? true");
 950
 951
 952   /* interrupt controller */
 953
 954   hw_tree_parse (hw, "/mn103int@0x34000100/reg 0x34000100 0x68 0x34000200 0x8 0x3400280 0x8");
 955   if (STATE_VERBOSE_P (sd))
 956     hw_tree_parse (hw, "/mn103int/trace? true");
 957
 958   /* DEBUG: NMI input's */
 959   hw_tree_parse (hw, "/glue@0x30000000/reg 0x30000000 12");
 960   if (STATE_VERBOSE_P (sd))
 961     hw_tree_parse (hw, "/glue@0x30000000/trace? true");
 962   hw_tree_parse (hw, "/glue@0x30000000 > int0 nmirq /mn103int");
 963   hw_tree_parse (hw, "/glue@0x30000000 > int1 watchdog /mn103int");
 964   hw_tree_parse (hw, "/glue@0x30000000 > int2 syserr /mn103int");
 965
 966   /* DEBUG: ACK input */
 967   hw_tree_parse (hw, "/glue@0x30002000/reg 0x30002000 4");
 968   if (STATE_VERBOSE_P (sd))
 969     hw_tree_parse (hw, "/glue@0x30002000/trace? true");
 970   hw_tree_parse (hw, "/glue@0x30002000 > int ack /mn103int");
 971
 972   /* DEBUG: LEVEL output */
 973   hw_tree_parse (hw, "/glue@0x30004000/reg 0x30004000 8");
 974   if (STATE_VERBOSE_P (sd))
 975     hw_tree_parse (hw, "/glue@0x30004000/trace? true");
 976   hw_tree_parse (hw, "/mn103int > nmi int0 /glue@0x30004000");
 977   hw_tree_parse (hw, "/mn103int > level int1 /glue@0x30004000");
 978
 979   /* DEBUG: A bunch of interrupt inputs */
 980   hw_tree_parse (hw, "/glue@0x30006000/reg 0x30006000 32");
 981   if (STATE_VERBOSE_P (sd))
 982     hw_tree_parse (hw, "/glue@0x30006000/trace? true");
 983   hw_tree_parse (hw, "/glue@0x30006000 > int0 irq-0 /mn103int");
 984   hw_tree_parse (hw, "/glue@0x30006000 > int1 irq-1 /mn103int");
 985   hw_tree_parse (hw, "/glue@0x30006000 > int2 irq-2 /mn103int");
 986   hw_tree_parse (hw, "/glue@0x30006000 > int3 irq-3 /mn103int");
 987   hw_tree_parse (hw, "/glue@0x30006000 > int4 irq-4 /mn103int");
 988   hw_tree_parse (hw, "/glue@0x30006000 > int5 irq-5 /mn103int");
 989   hw_tree_parse (hw, "/glue@0x30006000 > int6 irq-6 /mn103int");
 990   hw_tree_parse (hw, "/glue@0x30006000 > int7 irq-7 /mn103int");
 991
 992
 993   /* processor interrupt device */
 994
 995   /* the device */
 996   hw_tree_parse (hw, "/mn103cpu@0x20000000");
 997   if (STATE_VERBOSE_P (sd))
 998     hw_tree_parse (hw, "/mn103cpu@0x20000000/trace? true");
 999   hw_tree_parse (hw, "/mn103cpu@0x20000000/reg 0x20000000 0x42");
1000
1001   /* DEBUG: ACK output wired upto a glue device */
1002   hw_tree_parse (hw, "/glue@0x20002000");
1003   if (STATE_VERBOSE_P (sd))
1004     hw_tree_parse (hw, "/glue@0x20002000/trace? true");
1005   hw_tree_parse (hw, "/glue@0x20002000/reg 0x20002000 4");
1006   hw_tree_parse (hw, "/mn103cpu > ack int0 /glue@0x20002000");
1007
1008   /* DEBUG: RESET/NMI/LEVEL wired up to a glue device */
1009   hw_tree_parse (hw, "/glue@0x20004000");
1010   if (STATE_VERBOSE_P (sd))
1011     hw_tree_parse (hw, "/glue@0x20004000/trace? true");
1012   hw_tree_parse (hw, "/glue@0x20004000/reg 0x20004000 12");
1013   hw_tree_parse (hw, "/glue@0x20004000 > int0 reset /mn103cpu");
1014   hw_tree_parse (hw, "/glue@0x20004000 > int1 nmi /mn103cpu");
1015   hw_tree_parse (hw, "/glue@0x20004000 > int2 level /mn103cpu");
1016
1017   /* REAL: The processor wired up to the real interrupt controller */
1018 #if 1
1019   hw_tree_parse (hw, "/mn103cpu > ack ack /mn103int");
1020   hw_tree_parse (hw, "/mn103int > level level /mn103cpu");
1021   hw_tree_parse (hw, "/mn103int > nmi nmi /mn103cpu");
1022 #endif
1023
1024
1025   /* PAL */
1026
1027   /* the device */
1028   hw_tree_parse (hw, "/pal@0x31000000");
1029   if (STATE_VERBOSE_P (sd))
1030     hw_tree_parse (hw, "/pal@0x31000000/trace? true");
1031   hw_tree_parse (hw, "/pal@0x31000000/reg 0x31000000 64");
1032
1033   /* DEBUG: PAL wired up to a glue device */
1034   hw_tree_parse (hw, "/glue@0x31002000");
1035   if (STATE_VERBOSE_P (sd))
1036     hw_tree_parse (hw, "/glue@0x31002000/trace? true");
1037   hw_tree_parse (hw, "/glue@0x31002000/reg 0x31002000 16");
1038   hw_tree_parse (hw, "/pal@0x31000000 > countdown int0 /glue@0x31002000");
1039   hw_tree_parse (hw, "/pal@0x31000000 > timer int1 /glue@0x31002000");
1040   hw_tree_parse (hw, "/pal@0x31000000 > int int2 /glue@0x31002000");
1041   hw_tree_parse (hw, "/glue@0x31002000 > int0 int3 /glue@0x31002000");
1042   hw_tree_parse (hw, "/glue@0x31002000 > int1 int3 /glue@0x31002000");
1043   hw_tree_parse (hw, "/glue@0x31002000 > int2 int3 /glue@0x31002000");
1044
1045   /* REAL: The PAL wired up to the real interrupt controller */
1046   hw_tree_parse (hw, "/pal@0x31000000 > countdown irq-0 /mn103int");
1047   hw_tree_parse (hw, "/pal@0x31000000 > timer irq-1 /mn103int");
1048   hw_tree_parse (hw, "/pal@0x31000000 > int irq-2 /mn103int");
1049
1050
1051
1052   hw_tree_finish (hw);
1053   if (STATE_VERBOSE_P (sd))
1054     hw_tree_print (hw);
1055   /* end-sanitize-am30 */
1056
1057   /* check for/establish the a reference program image */
1058   if (sim_analyze_program (sd,
1059                            (STATE_PROG_ARGV (sd) != NULL
1060                             ? *STATE_PROG_ARGV (sd)
1061                             : NULL),
1062                            abfd) != SIM_RC_OK)
1063     {
1064       sim_module_uninstall (sd);
1065       return 0;
1066     }
1067
1068   /* establish any remaining configuration options */
1069   if (sim_config (sd) != SIM_RC_OK)
1070     {
1071       sim_module_uninstall (sd);
1072       return 0;
1073     }
1074
1075   if (sim_post_argv_init (sd) != SIM_RC_OK)
1076     {
1077       /* Uninstall the modules to avoid memory leaks,
1078          file descriptor leaks, etc.  */
1079       sim_module_uninstall (sd);
1080       return 0;
1081     }
1082
1083
1084   /* set machine specific configuration */
1085 /*   STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
1086 /*                           | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
1087
1088   return sd;
1089 }
1090
1091
1092 void
1093 sim_close (sd, quitting)
1094      SIM_DESC sd;
1095      int quitting;
1096 {
1097   sim_module_uninstall (sd);
1098 }
1099
1100
1101 SIM_RC
1102 sim_create_inferior (sd, prog_bfd, argv, env)
1103      SIM_DESC sd;
1104      struct _bfd *prog_bfd;
1105      char **argv;
1106      char **env;
1107 {
1108   memset (&State, 0, sizeof (State));
1109   if (prog_bfd != NULL) {
1110     PC = bfd_get_start_address (prog_bfd);
1111   } else {
1112     PC = 0;
1113   }
1114   CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
1115
1116   return SIM_RC_OK;
1117 }
1118
1119 void
1120 sim_do_command (sd, cmd)
1121      SIM_DESC sd;
1122      char *cmd;
1123 {
1124   char *mm_cmd = "memory-map";
1125   char *int_cmd = "interrupt";
1126
1127   if (sim_args_command (sd, cmd) != SIM_RC_OK)
1128     {
1129       if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
1130         sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
1131       else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
1132         sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
1133       else
1134         sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
1135     }
1136 }
1137 #endif  /* WITH_COMMON */
1138
1139 /* FIXME These would more efficient to use than load_mem/store_mem,
1140    but need to be changed to use the memory map.  */
1141
1142 uint8
1143 get_byte (x)
1144      uint8 *x;
1145 {
1146   return *x;
1147 }
1148
1149 uint16
1150 get_half (x)
1151      uint8 *x;
1152 {
1153   uint8 *a = x;
1154   return (a[1] << 8) + (a[0]);
1155 }
1156
1157 uint32
1158 get_word (x)
1159       uint8 *x;
1160 {
1161   uint8 *a = x;
1162   return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
1163 }
1164
1165 void
1166 put_byte (addr, data)
1167      uint8 *addr;
1168      uint8 data;
1169 {
1170   uint8 *a = addr;
1171   a[0] = data;
1172 }
1173
1174 void
1175 put_half (addr, data)
1176      uint8 *addr;
1177      uint16 data;
1178 {
1179   uint8 *a = addr;
1180   a[0] = data & 0xff;
1181   a[1] = (data >> 8) & 0xff;
1182 }
1183
1184 void
1185 put_word (addr, data)
1186      uint8 *addr;
1187      uint32 data;
1188 {
1189   uint8 *a = addr;
1190   a[0] = data & 0xff;
1191   a[1] = (data >> 8) & 0xff;
1192   a[2] = (data >> 16) & 0xff;
1193   a[3] = (data >> 24) & 0xff;
1194 }
1195
1196 int
1197 sim_fetch_register (sd, rn, memory, length)
1198      SIM_DESC sd;
1199      int rn;
1200      unsigned char *memory;
1201      int length;
1202 {
1203   put_word (memory, State.regs[rn]);
1204   return -1;
1205 }
1206
1207 int
1208 sim_store_register (sd, rn, memory, length)
1209      SIM_DESC sd;
1210      int rn;
1211      unsigned char *memory;
1212      int length;
1213 {
1214   State.regs[rn] = get_word (memory);
1215   return -1;
1216 }