sim/mn10300/interp.c

   1 #include <signal.h>
   2 #include "sysdep.h"
   3 #include "bfd.h"
   4
   5 #include "mn10300_sim.h"
   6
   7 #ifndef INLINE
   8 #ifdef __GNUC__
   9 #define INLINE inline
  10 #else
  11 #define INLINE
  12 #endif
  13 #endif
  14
  15 host_callback *mn10300_callback;
  16 int mn10300_debug;
  17 static SIM_OPEN_KIND sim_kind;
  18 static char *myname;
  19
  20 static void dispatch PARAMS ((uint32, uint32, int));
  21 static long hash PARAMS ((long));
  22 static void init_system PARAMS ((void));
  23 #define MAX_HASH  127
  24
  25 struct hash_entry
  26 {
  27   struct hash_entry *next;
  28   long opcode;
  29   long mask;
  30   struct simops *ops;
  31 #ifdef HASH_STAT
  32   unsigned long count;
  33 #endif
  34 };
  35
  36 struct hash_entry hash_table[MAX_HASH+1];
  37
  38
  39 /* This probably doesn't do a very good job at bucket filling, but
  40    it's simple... */
  41 static INLINE long
  42 hash(insn)
  43      long insn;
  44 {
  45   /* These are one byte insns, we special case these since, in theory,
  46      they should be the most heavily used.  */
  47   if ((insn & 0xffffff00) == 0)
  48     {
  49       switch (insn & 0xf0)
  50         {
  51           case 0x00:
  52             return 0x70;
  53
  54           case 0x40:
  55             return 0x71;
  56
  57           case 0x10:
  58             return 0x72;
  59
  60           case 0x30:
  61             return 0x73;
  62
  63           case 0x50:
  64             return 0x74;
  65
  66           case 0x60:
  67             return 0x75;
  68
  69           case 0x70:
  70             return 0x76;
  71
  72           case 0x80:
  73             return 0x77;
  74
  75           case 0x90:
  76             return 0x78;
  77
  78           case 0xa0:
  79             return 0x79;
  80
  81           case 0xb0:
  82             return 0x7a;
  83
  84           case 0xe0:
  85             return 0x7b;
  86
  87           default:
  88             return 0x7c;
  89         }
  90     }
  91
  92   /* These are two byte insns */
  93   if ((insn & 0xffff0000) == 0)
  94     {
  95       if ((insn & 0xf000) == 0x2000
  96           || (insn & 0xf000) == 0x5000)
  97         return ((insn & 0xfc00) >> 8) & 0x7f;
  98
  99       if ((insn & 0xf000) == 0x4000)
 100         return ((insn & 0xf300) >> 8) & 0x7f;
 101
 102       if ((insn & 0xf000) == 0x8000
 103           || (insn & 0xf000) == 0x9000
 104           || (insn & 0xf000) == 0xa000
 105           || (insn & 0xf000) == 0xb000)
 106         return ((insn & 0xf000) >> 8) & 0x7f;
 107
 108       if ((insn & 0xff00) == 0xf000
 109           || (insn & 0xff00) == 0xf100
 110           || (insn & 0xff00) == 0xf200
 111           || (insn & 0xff00) == 0xf500
 112           || (insn & 0xff00) == 0xf600)
 113         return ((insn & 0xfff0) >> 4) & 0x7f;
 114
 115       if ((insn & 0xf000) == 0xc000)
 116         return ((insn & 0xff00) >> 8) & 0x7f;
 117
 118       return ((insn & 0xffc0) >> 6) & 0x7f;
 119     }
 120
 121   /* These are three byte insns.  */
 122   if ((insn & 0xff000000) == 0)
 123     {
 124       if ((insn & 0xf00000) == 0x000000)
 125         return ((insn & 0xf30000) >> 16) & 0x7f;
 126
 127       if ((insn & 0xf00000) == 0x200000
 128           || (insn & 0xf00000) == 0x300000)
 129         return ((insn & 0xfc0000) >> 16) & 0x7f;
 130
 131       if ((insn & 0xff0000) == 0xf80000)
 132         return ((insn & 0xfff000) >> 12) & 0x7f;
 133
 134       if ((insn & 0xff0000) == 0xf90000)
 135         return ((insn & 0xfffc00) >> 10) & 0x7f;
 136
 137       return ((insn & 0xff0000) >> 16) & 0x7f;
 138     }
 139
 140   /* These are four byte or larger insns.  */
 141   if ((insn & 0xf0000000) == 0xf0000000)
 142     return ((insn & 0xfff00000) >> 20) & 0x7f;
 143
 144   return ((insn & 0xff000000) >> 24) & 0x7f;
 145 }
 146
 147 static void
 148 dispatch (insn, extension, length)
 149      uint32 insn;
 150      uint32 extension;
 151      int length;
 152 {
 153   struct hash_entry *h;
 154
 155   h = &hash_table[hash(insn)];
 156
 157   while ((insn & h->mask) != h->opcode
 158           || (length != h->ops->length))
 159     {
 160       if (!h->next)
 161         {
 162           (*mn10300_callback->printf_filtered) (mn10300_callback,
 163             "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC);
 164           exit(1);
 165         }
 166       h = h->next;
 167     }
 168
 169
 170 #ifdef HASH_STAT
 171   h->count++;
 172 #endif
 173
 174   /* Now call the right function.  */
 175   (h->ops->func)(insn, extension);
 176   PC += length;
 177 }
 178
 179 /* FIXME These would more efficient to use than load_mem/store_mem,
 180    but need to be changed to use the memory map.  */
 181
 182 uint8
 183 get_byte (x)
 184      uint8 *x;
 185 {
 186   return *x;
 187 }
 188
 189 uint16
 190 get_half (x)
 191      uint8 *x;
 192 {
 193   uint8 *a = x;
 194   return (a[1] << 8) + (a[0]);
 195 }
 196
 197 uint32
 198 get_word (x)
 199       uint8 *x;
 200 {
 201   uint8 *a = x;
 202   return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
 203 }
 204
 205 void
 206 put_byte (addr, data)
 207      uint8 *addr;
 208      uint8 data;
 209 {
 210   uint8 *a = addr;
 211   a[0] = data;
 212 }
 213
 214 void
 215 put_half (addr, data)
 216      uint8 *addr;
 217      uint16 data;
 218 {
 219   uint8 *a = addr;
 220   a[0] = data & 0xff;
 221   a[1] = (data >> 8) & 0xff;
 222 }
 223
 224 void
 225 put_word (addr, data)
 226      uint8 *addr;
 227      uint32 data;
 228 {
 229   uint8 *a = addr;
 230   a[0] = data & 0xff;
 231   a[1] = (data >> 8) & 0xff;
 232   a[2] = (data >> 16) & 0xff;
 233   a[3] = (data >> 24) & 0xff;
 234 }
 235
 236
 237 uint32
 238 load_mem_big (addr, len)
 239      SIM_ADDR addr;
 240      int len;
 241 {
 242   uint8 *p = addr + State.mem;
 243
 244   switch (len)
 245     {
 246     case 1:
 247       return p[0];
 248     case 2:
 249       return p[0] << 8 | p[1];
 250     case 3:
 251       return p[0] << 16 | p[1] << 8 | p[2];
 252     case 4:
 253       return p[0] << 24 | p[1] << 16 | p[2] << 8 | p[3];
 254     default:
 255       abort ();
 256     }
 257 }
 258
 259 uint32
 260 load_mem (addr, len)
 261      SIM_ADDR addr;
 262      int len;
 263 {
 264   uint8 *p = addr + State.mem;
 265
 266   switch (len)
 267     {
 268     case 1:
 269       return p[0];
 270     case 2:
 271       return p[1] << 8 | p[0];
 272     case 3:
 273       return p[2] << 16 | p[1] << 8 | p[0];
 274     case 4:
 275       return p[3] << 24 | p[2] << 16 | p[1] << 8 | p[0];
 276     default:
 277       abort ();
 278     }
 279 }
 280
 281 void
 282 store_mem (addr, len, data)
 283      SIM_ADDR addr;
 284      int len;
 285      uint32 data;
 286 {
 287   uint8 *p = addr + State.mem;
 288
 289   switch (len)
 290     {
 291     case 1:
 292       p[0] = data;
 293       return;
 294     case 2:
 295       p[0] = data;
 296       p[1] = data >> 8;
 297       return;
 298     case 4:
 299       p[0] = data;
 300       p[1] = data >> 8;
 301       p[2] = data >> 16;
 302       p[3] = data >> 24;
 303       return;
 304     default:
 305       abort ();
 306     }
 307 }
 308
 309 void
 310 sim_size (power)
 311      int power;
 312
 313 {
 314   if (State.mem)
 315     free (State.mem);
 316
 317   State.mem = (uint8 *) calloc (1,  1 << power);
 318   if (!State.mem)
 319     {
 320       (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n");
 321       exit (1);
 322     }
 323 }
 324
 325 static void
 326 init_system ()
 327 {
 328   if (!State.mem)
 329     sim_size(19);
 330 }
 331
 332 int
 333 sim_write (sd, addr, buffer, size)
 334      SIM_DESC sd;
 335      SIM_ADDR addr;
 336      unsigned char *buffer;
 337      int size;
 338 {
 339   int i;
 340
 341   init_system ();
 342
 343   for (i = 0; i < size; i++)
 344     store_mem (addr + i, 1, buffer[i]);
 345
 346   return size;
 347 }
 348
 349 SIM_DESC
 350 sim_open (kind,argv)
 351      SIM_OPEN_KIND kind;
 352      char **argv;
 353 {
 354   struct simops *s;
 355   struct hash_entry *h;
 356   char **p;
 357
 358   sim_kind = kind;
 359   myname = argv[0];
 360
 361   for (p = argv + 1; *p; ++p)
 362     {
 363       if (strcmp (*p, "-E") == 0)
 364         ++p; /* ignore endian spec */
 365       else
 366 #ifdef DEBUG
 367       if (strcmp (*p, "-t") == 0)
 368         mn10300_debug = DEBUG;
 369       else
 370 #endif
 371         (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p);
 372     }
 373
 374  /* put all the opcodes in the hash table */
 375   for (s = Simops; s->func; s++)
 376     {
 377       h = &hash_table[hash(s->opcode)];
 378
 379       /* go to the last entry in the chain */
 380       while (h->next)
 381         {
 382           /* Don't insert the same opcode more than once.  */
 383           if (h->opcode == s->opcode
 384               && h->mask == s->mask
 385               && h->ops == s)
 386             continue;
 387           else
 388             h = h->next;
 389         }
 390
 391       /* Don't insert the same opcode more than once.  */
 392       if (h->opcode == s->opcode
 393           && h->mask == s->mask
 394           && h->ops == s)
 395         continue;
 396
 397       if (h->ops)
 398         {
 399           h->next = calloc(1,sizeof(struct hash_entry));
 400           h = h->next;
 401         }
 402       h->ops = s;
 403       h->mask = s->mask;
 404       h->opcode = s->opcode;
 405 #if HASH_STAT
 406       h->count = 0;
 407 #endif
 408     }
 409
 410
 411   /* fudge our descriptor for now */
 412   return (SIM_DESC) 1;
 413 }
 414
 415
 416 void
 417 sim_close (sd, quitting)
 418      SIM_DESC sd;
 419      int quitting;
 420 {
 421   /* nothing to do */
 422 }
 423
 424 void
 425 sim_set_profile (n)
 426      int n;
 427 {
 428   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n);
 429 }
 430
 431 void
 432 sim_set_profile_size (n)
 433      int n;
 434 {
 435   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n);
 436 }
 437
 438 int
 439 sim_stop (sd)
 440      SIM_DESC sd;
 441 {
 442   return 0;
 443 }
 444
 445 void
 446 sim_resume (sd, step, siggnal)
 447      SIM_DESC sd;
 448      int step, siggnal;
 449 {
 450   uint32 inst;
 451   reg_t oldpc;
 452   struct hash_entry *h;
 453
 454   if (step)
 455     State.exception = SIGTRAP;
 456   else
 457     State.exception = 0;
 458
 459   do
 460     {
 461       unsigned long insn, extension;
 462
 463       /* Fetch the current instruction.  */
 464       inst = load_mem_big (PC, 2);
 465       oldpc = PC;
 466
 467       /* Using a giant case statement may seem like a waste because of the
 468         code/rodata size the table itself will consume.  However, using
 469         a giant case statement speeds up the simulator by 10-15% by avoiding
 470         cascading if/else statements or cascading case statements.  */
 471
 472       switch ((inst >> 8) & 0xff)
 473         {
 474           /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0
 475              which must be handled specially.  */
 476           case 0x00:
 477           case 0x04:
 478           case 0x08:
 479           case 0x0c:
 480           case 0x11:
 481           case 0x12:
 482           case 0x13:
 483           case 0x14:
 484           case 0x15:
 485           case 0x16:
 486           case 0x17:
 487           case 0x18:
 488           case 0x19:
 489           case 0x1a:
 490           case 0x1b:
 491           case 0x1c:
 492           case 0x1d:
 493           case 0x1e:
 494           case 0x1f:
 495           case 0x3c:
 496           case 0x3d:
 497           case 0x3e:
 498           case 0x3f:
 499           case 0x40:
 500           case 0x41:
 501           case 0x44:
 502           case 0x45:
 503           case 0x48:
 504           case 0x49:
 505           case 0x4c:
 506           case 0x4d:
 507           case 0x50:
 508           case 0x51:
 509           case 0x52:
 510           case 0x53:
 511           case 0x54:
 512           case 0x55:
 513           case 0x56:
 514           case 0x57:
 515           case 0x60:
 516           case 0x61:
 517           case 0x62:
 518           case 0x63:
 519           case 0x64:
 520           case 0x65:
 521           case 0x66:
 522           case 0x67:
 523           case 0x68:
 524           case 0x69:
 525           case 0x6a:
 526           case 0x6b:
 527           case 0x6c:
 528           case 0x6d:
 529           case 0x6e:
 530           case 0x6f:
 531           case 0x70:
 532           case 0x71:
 533           case 0x72:
 534           case 0x73:
 535           case 0x74:
 536           case 0x75:
 537           case 0x76:
 538           case 0x77:
 539           case 0x78:
 540           case 0x79:
 541           case 0x7a:
 542           case 0x7b:
 543           case 0x7c:
 544           case 0x7d:
 545           case 0x7e:
 546           case 0x7f:
 547           case 0xcb:
 548           case 0xd0:
 549           case 0xd1:
 550           case 0xd2:
 551           case 0xd3:
 552           case 0xd4:
 553           case 0xd5:
 554           case 0xd6:
 555           case 0xd7:
 556           case 0xd8:
 557           case 0xd9:
 558           case 0xda:
 559           case 0xdb:
 560           case 0xe0:
 561           case 0xe1:
 562           case 0xe2:
 563           case 0xe3:
 564           case 0xe4:
 565           case 0xe5:
 566           case 0xe6:
 567           case 0xe7:
 568           case 0xe8:
 569           case 0xe9:
 570           case 0xea:
 571           case 0xeb:
 572           case 0xec:
 573           case 0xed:
 574           case 0xee:
 575           case 0xef:
 576           case 0xff:
 577             insn = (inst >> 8) & 0xff;
 578             extension = 0;
 579             dispatch (insn, extension, 1);
 580             break;
 581
 582           /* Special cases where dm == dn is used to encode a different
 583              instruction.  */
 584           case 0x80:
 585           case 0x85:
 586           case 0x8a:
 587           case 0x8f:
 588           case 0x90:
 589           case 0x95:
 590           case 0x9a:
 591           case 0x9f:
 592           case 0xa0:
 593           case 0xa5:
 594           case 0xaa:
 595           case 0xaf:
 596           case 0xb0:
 597           case 0xb5:
 598           case 0xba:
 599           case 0xbf:
 600             insn = inst;
 601             extension = 0;
 602             dispatch (insn, extension, 2);
 603             break;
 604
 605           case 0x81:
 606           case 0x82:
 607           case 0x83:
 608           case 0x84:
 609           case 0x86:
 610           case 0x87:
 611           case 0x88:
 612           case 0x89:
 613           case 0x8b:
 614           case 0x8c:
 615           case 0x8d:
 616           case 0x8e:
 617           case 0x91:
 618           case 0x92:
 619           case 0x93:
 620           case 0x94:
 621           case 0x96:
 622           case 0x97:
 623           case 0x98:
 624           case 0x99:
 625           case 0x9b:
 626           case 0x9c:
 627           case 0x9d:
 628           case 0x9e:
 629           case 0xa1:
 630           case 0xa2:
 631           case 0xa3:
 632           case 0xa4:
 633           case 0xa6:
 634           case 0xa7:
 635           case 0xa8:
 636           case 0xa9:
 637           case 0xab:
 638           case 0xac:
 639           case 0xad:
 640           case 0xae:
 641           case 0xb1:
 642           case 0xb2:
 643           case 0xb3:
 644           case 0xb4:
 645           case 0xb6:
 646           case 0xb7:
 647           case 0xb8:
 648           case 0xb9:
 649           case 0xbb:
 650           case 0xbc:
 651           case 0xbd:
 652           case 0xbe:
 653             insn = (inst >> 8) & 0xff;
 654             extension = 0;
 655           dispatch (insn, extension, 1);
 656           break;
 657
 658           /* The two byte instructions.  */
 659           case 0x20:
 660           case 0x21:
 661           case 0x22:
 662           case 0x23:
 663           case 0x28:
 664           case 0x29:
 665           case 0x2a:
 666           case 0x2b:
 667           case 0x42:
 668           case 0x43:
 669           case 0x46:
 670           case 0x47:
 671           case 0x4a:
 672           case 0x4b:
 673           case 0x4e:
 674           case 0x4f:
 675           case 0x58:
 676           case 0x59:
 677           case 0x5a:
 678           case 0x5b:
 679           case 0x5c:
 680           case 0x5d:
 681           case 0x5e:
 682           case 0x5f:
 683           case 0xc0:
 684           case 0xc1:
 685           case 0xc2:
 686           case 0xc3:
 687           case 0xc4:
 688           case 0xc5:
 689           case 0xc6:
 690           case 0xc7:
 691           case 0xc8:
 692           case 0xc9:
 693           case 0xca:
 694           case 0xce:
 695           case 0xcf:
 696           case 0xf0:
 697           case 0xf1:
 698           case 0xf2:
 699           case 0xf3:
 700           case 0xf4:
 701           case 0xf5:
 702           case 0xf6:
 703             insn = inst;
 704             extension = 0;
 705             dispatch (insn, extension, 2);
 706             break;
 707
 708           /* The three byte insns with a 16bit operand in little endian
 709              format.  */
 710           case 0x01:
 711           case 0x02:
 712           case 0x03:
 713           case 0x05:
 714           case 0x06:
 715           case 0x07:
 716           case 0x09:
 717           case 0x0a:
 718           case 0x0b:
 719           case 0x0d:
 720           case 0x0e:
 721           case 0x0f:
 722           case 0x24:
 723           case 0x25:
 724           case 0x26:
 725           case 0x27:
 726           case 0x2c:
 727           case 0x2d:
 728           case 0x2e:
 729           case 0x2f:
 730           case 0x30:
 731           case 0x31:
 732           case 0x32:
 733           case 0x33:
 734           case 0x34:
 735           case 0x35:
 736           case 0x36:
 737           case 0x37:
 738           case 0x38:
 739           case 0x39:
 740           case 0x3a:
 741           case 0x3b:
 742           case 0xcc:
 743             insn = load_mem (PC, 1);
 744             insn <<= 16;
 745             insn |= load_mem (PC + 1, 2);
 746             extension = 0;
 747             dispatch (insn, extension, 3);
 748             break;
 749
 750           /* The three byte insns without 16bit operand.  */
 751           case 0xde:
 752           case 0xdf:
 753           case 0xf8:
 754           case 0xf9:
 755             insn = load_mem_big (PC, 3);
 756             extension = 0;
 757             dispatch (insn, extension, 3);
 758             break;
 759
 760           /* Four byte insns.  */
 761           case 0xfa:
 762           case 0xfb:
 763             if ((inst & 0xfffc) == 0xfaf0
 764                 || (inst & 0xfffc) == 0xfaf4
 765                 || (inst & 0xfffc) == 0xfaf8)
 766               insn = load_mem_big (PC, 4);
 767             else
 768               {
 769                 insn = inst;
 770                 insn <<= 16;
 771                 insn |= load_mem (PC + 2, 2);
 772                 extension = 0;
 773               }
 774             dispatch (insn, extension, 4);
 775             break;
 776
 777           /* Five byte insns.  */
 778           case 0xcd:
 779             insn = load_mem (PC, 1);
 780             insn <<= 24;
 781             insn |= (load_mem (PC + 1, 2) << 8);
 782             insn |= load_mem (PC + 3, 1);
 783             extension = load_mem (PC + 4, 1);
 784             dispatch (insn, extension, 5);
 785             break;
 786
 787           case 0xdc:
 788             insn = load_mem (PC, 1);
 789             insn <<= 24;
 790             extension = load_mem (PC + 1, 4);
 791             insn |= (extension & 0xffffff00) >> 8;
 792             extension &= 0xff;
 793             dispatch (insn, extension, 5);
 794             break;
 795
 796           /* Six byte insns.  */
 797           case 0xfc:
 798           case 0xfd:
 799             insn = (inst << 16);
 800             extension = load_mem (PC + 2, 4);
 801             insn |= ((extension & 0xffff0000) >> 16);
 802             extension &= 0xffff;
 803             dispatch (insn, extension, 6);
 804             break;
 805
 806           case 0xdd:
 807             insn = load_mem (PC, 1) << 24;
 808             extension = load_mem (PC + 1, 4);
 809             insn |= ((extension >> 8) & 0xffffff);
 810             extension = (extension & 0xff) << 16;
 811             extension |= load_mem (PC + 5, 1) << 8;
 812             extension |= load_mem (PC + 6, 1);
 813             dispatch (insn, extension, 7);
 814             break;
 815
 816           case 0xfe:
 817             insn = inst << 16;
 818             extension = load_mem (PC + 2, 4);
 819             insn |= ((extension >> 16) & 0xffff);
 820             extension <<= 8;
 821             extension &= 0xffff00;
 822             extension |= load_mem (PC + 6, 1);
 823             dispatch (insn, extension, 7);
 824             break;
 825
 826           default:
 827             abort ();
 828         }
 829     }
 830   while (!State.exception);
 831
 832 #ifdef HASH_STAT
 833   {
 834     int i;
 835     for (i = 0; i < MAX_HASH; i++)
 836       {
 837          struct hash_entry *h;
 838          h = &hash_table[i];
 839
 840          printf("hash 0x%x:\n", i);
 841
 842          while (h)
 843            {
 844              printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
 845              h = h->next;
 846            }
 847
 848          printf("\n\n");
 849       }
 850     fflush (stdout);
 851   }
 852 #endif
 853
 854 }
 855
 856 int
 857 sim_trace (sd)
 858      SIM_DESC sd;
 859 {
 860 #ifdef DEBUG
 861   mn10300_debug = DEBUG;
 862 #endif
 863   sim_resume (sd, 0, 0);
 864   return 1;
 865 }
 866
 867 void
 868 sim_info (sd, verbose)
 869      SIM_DESC sd;
 870      int verbose;
 871 {
 872   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
 873 }
 874
 875 SIM_RC
 876 sim_create_inferior (sd, argv, env)
 877      SIM_DESC sd;
 878      char **argv;
 879      char **env;
 880 {
 881   return SIM_RC_OK;
 882 }
 883
 884 void
 885 sim_kill (sd)
 886      SIM_DESC sd;
 887 {
 888   /* nothing to do */
 889 }
 890
 891 void
 892 sim_set_callbacks (sd, p)
 893      SIM_DESC sd;
 894      host_callback *p;
 895 {
 896   mn10300_callback = p;
 897 }
 898
 899 /* All the code for exiting, signals, etc needs to be revamped.
 900
 901    This is enough to get c-torture limping though.  */
 902
 903 void
 904 sim_stop_reason (sd, reason, sigrc)
 905      SIM_DESC sd;
 906      enum sim_stop *reason;
 907      int *sigrc;
 908 {
 909   *reason = sim_stopped;
 910   if (State.exception == SIGQUIT)
 911     *sigrc = 0;
 912   else
 913     *sigrc = State.exception;
 914 }
 915
 916 void
 917 sim_fetch_register (sd, rn, memory)
 918      SIM_DESC sd;
 919      int rn;
 920      unsigned char *memory;
 921 {
 922   put_word (memory, State.regs[rn]);
 923 }
 924
 925 void
 926 sim_store_register (sd, rn, memory)
 927      SIM_DESC sd;
 928      int rn;
 929      unsigned char *memory;
 930 {
 931   State.regs[rn] = get_word (memory);
 932 }
 933
 934 int
 935 sim_read (sd, addr, buffer, size)
 936      SIM_DESC sd;
 937      SIM_ADDR addr;
 938      unsigned char *buffer;
 939      int size;
 940 {
 941   int i;
 942   for (i = 0; i < size; i++)
 943     buffer[i] = load_mem (addr + i, 1);
 944
 945   return size;
 946 }
 947
 948 void
 949 sim_do_command (sd, cmd)
 950      SIM_DESC sd;
 951      char *cmd;
 952 {
 953   (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
 954 }
 955
 956 SIM_RC
 957 sim_load (sd, prog, abfd, from_tty)
 958      SIM_DESC sd;
 959      char *prog;
 960      bfd *abfd;
 961      int from_tty;
 962 {
 963   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
 964   bfd *prog_bfd;
 965
 966   prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
 967                             sim_kind == SIM_OPEN_DEBUG);
 968   if (prog_bfd == NULL)
 969     return SIM_RC_FAIL;
 970   PC = bfd_get_start_address (prog_bfd);
 971   if (abfd == NULL)
 972     bfd_close (prog_bfd);
 973   return SIM_RC_OK;
 974 }