sim/mn10300/interp.c

   1 #include <signal.h>
   2
   3 #if WITH_COMMON
   4 #include "sim-main.h"
   5 #include "sim-options.h"
   6 #else
   7 #include "mn10300_sim.h"
   8 #endif
   9
  10 #include "sysdep.h"
  11 #include "bfd.h"
  12 #include "sim-assert.h"
  13
  14
  15 #ifdef HAVE_STDLIB_H
  16 #include <stdlib.h>
  17 #endif
  18
  19 #ifdef HAVE_STRING_H
  20 #include <string.h>
  21 #else
  22 #ifdef HAVE_STRINGS_H
  23 #include <strings.h>
  24 #endif
  25 #endif
  26
  27 #include "bfd.h"
  28
  29 #ifndef INLINE
  30 #ifdef __GNUC__
  31 #define INLINE inline
  32 #else
  33 #define INLINE
  34 #endif
  35 #endif
  36
  37
  38 host_callback *mn10300_callback;
  39 int mn10300_debug;
  40
  41 #if WITH_COMMON
  42 #else
  43 static void dispatch PARAMS ((uint32, uint32, int));
  44 static long hash PARAMS ((long));
  45 static void init_system PARAMS ((void));
  46
  47 static SIM_OPEN_KIND sim_kind;
  48 static char *myname;
  49 #define MAX_HASH  127
  50
  51 struct hash_entry
  52 {
  53   struct hash_entry *next;
  54   long opcode;
  55   long mask;
  56   struct simops *ops;
  57 #ifdef HASH_STAT
  58   unsigned long count;
  59 #endif
  60 };
  61
  62 static int max_mem = 0;
  63 struct hash_entry hash_table[MAX_HASH+1];
  64
  65
  66 /* This probably doesn't do a very good job at bucket filling, but
  67    it's simple... */
  68 static INLINE long
  69 hash(insn)
  70      long insn;
  71 {
  72   /* These are one byte insns, we special case these since, in theory,
  73      they should be the most heavily used.  */
  74   if ((insn & 0xffffff00) == 0)
  75     {
  76       switch (insn & 0xf0)
  77         {
  78           case 0x00:
  79             return 0x70;
  80
  81           case 0x40:
  82             return 0x71;
  83
  84           case 0x10:
  85             return 0x72;
  86
  87           case 0x30:
  88             return 0x73;
  89
  90           case 0x50:
  91             return 0x74;
  92
  93           case 0x60:
  94             return 0x75;
  95
  96           case 0x70:
  97             return 0x76;
  98
  99           case 0x80:
 100             return 0x77;
 101
 102           case 0x90:
 103             return 0x78;
 104
 105           case 0xa0:
 106             return 0x79;
 107
 108           case 0xb0:
 109             return 0x7a;
 110
 111           case 0xe0:
 112             return 0x7b;
 113
 114           default:
 115             return 0x7c;
 116         }
 117     }
 118
 119   /* These are two byte insns */
 120   if ((insn & 0xffff0000) == 0)
 121     {
 122       if ((insn & 0xf000) == 0x2000
 123           || (insn & 0xf000) == 0x5000)
 124         return ((insn & 0xfc00) >> 8) & 0x7f;
 125
 126       if ((insn & 0xf000) == 0x4000)
 127         return ((insn & 0xf300) >> 8) & 0x7f;
 128
 129       if ((insn & 0xf000) == 0x8000
 130           || (insn & 0xf000) == 0x9000
 131           || (insn & 0xf000) == 0xa000
 132           || (insn & 0xf000) == 0xb000)
 133         return ((insn & 0xf000) >> 8) & 0x7f;
 134
 135       if ((insn & 0xff00) == 0xf000
 136           || (insn & 0xff00) == 0xf100
 137           || (insn & 0xff00) == 0xf200
 138           || (insn & 0xff00) == 0xf500
 139           || (insn & 0xff00) == 0xf600)
 140         return ((insn & 0xfff0) >> 4) & 0x7f;
 141
 142       if ((insn & 0xf000) == 0xc000)
 143         return ((insn & 0xff00) >> 8) & 0x7f;
 144
 145       return ((insn & 0xffc0) >> 6) & 0x7f;
 146     }
 147
 148   /* These are three byte insns.  */
 149   if ((insn & 0xff000000) == 0)
 150     {
 151       if ((insn & 0xf00000) == 0x000000)
 152         return ((insn & 0xf30000) >> 16) & 0x7f;
 153
 154       if ((insn & 0xf00000) == 0x200000
 155           || (insn & 0xf00000) == 0x300000)
 156         return ((insn & 0xfc0000) >> 16) & 0x7f;
 157
 158       if ((insn & 0xff0000) == 0xf80000)
 159         return ((insn & 0xfff000) >> 12) & 0x7f;
 160
 161       if ((insn & 0xff0000) == 0xf90000)
 162         return ((insn & 0xfffc00) >> 10) & 0x7f;
 163
 164       return ((insn & 0xff0000) >> 16) & 0x7f;
 165     }
 166
 167   /* These are four byte or larger insns.  */
 168   if ((insn & 0xf0000000) == 0xf0000000)
 169     return ((insn & 0xfff00000) >> 20) & 0x7f;
 170
 171   return ((insn & 0xff000000) >> 24) & 0x7f;
 172 }
 173
 174 static INLINE void
 175 dispatch (insn, extension, length)
 176      uint32 insn;
 177      uint32 extension;
 178      int length;
 179 {
 180   struct hash_entry *h;
 181
 182   h = &hash_table[hash(insn)];
 183
 184   while ((insn & h->mask) != h->opcode
 185           || (length != h->ops->length))
 186     {
 187       if (!h->next)
 188         {
 189           (*mn10300_callback->printf_filtered) (mn10300_callback,
 190             "ERROR looking up hash for 0x%x, PC=0x%x\n", insn, PC);
 191           exit(1);
 192         }
 193       h = h->next;
 194     }
 195
 196
 197 #ifdef HASH_STAT
 198   h->count++;
 199 #endif
 200
 201   /* Now call the right function.  */
 202   (h->ops->func)(insn, extension);
 203   PC += length;
 204 }
 205
 206 void
 207 sim_size (power)
 208      int power;
 209
 210 {
 211   if (State.mem)
 212     free (State.mem);
 213
 214   max_mem = 1 << power;
 215   State.mem = (uint8 *) calloc (1,  1 << power);
 216   if (!State.mem)
 217     {
 218       (*mn10300_callback->printf_filtered) (mn10300_callback, "Allocation of main memory failed.\n");
 219       exit (1);
 220     }
 221 }
 222
 223 static void
 224 init_system ()
 225 {
 226   if (!State.mem)
 227     sim_size(19);
 228 }
 229
 230 int
 231 sim_write (sd, addr, buffer, size)
 232      SIM_DESC sd;
 233      SIM_ADDR addr;
 234      unsigned char *buffer;
 235      int size;
 236 {
 237   int i;
 238
 239   init_system ();
 240
 241   for (i = 0; i < size; i++)
 242     store_byte (addr + i, buffer[i]);
 243
 244   return size;
 245 }
 246
 247 /* Compare two opcode table entries for qsort.  */
 248 static int
 249 compare_simops (arg1, arg2)
 250      const PTR arg1;
 251      const PTR arg2;
 252 {
 253   unsigned long code1 = ((struct simops *)arg1)->opcode;
 254   unsigned long code2 = ((struct simops *)arg2)->opcode;
 255
 256   if (code1 < code2)
 257     return -1;
 258   if (code2 < code1)
 259     return 1;
 260   return 0;
 261 }
 262
 263
 264 SIM_DESC
 265 sim_open (kind, cb, abfd, argv)
 266      SIM_OPEN_KIND kind;
 267      host_callback *cb;
 268      struct _bfd *abfd;
 269      char **argv;
 270 {
 271   struct simops *s;
 272   struct hash_entry *h;
 273   char **p;
 274   int i;
 275
 276   mn10300_callback = cb;
 277
 278   /* Sort the opcode array from smallest opcode to largest.
 279      This will generally improve simulator performance as the smaller
 280      opcodes are generally preferred to the larger opcodes.  */
 281   for (i = 0, s = Simops; s->func; s++, i++)
 282     ;
 283   qsort (Simops, i, sizeof (Simops[0]), compare_simops);
 284
 285   sim_kind = kind;
 286   myname = argv[0];
 287
 288   for (p = argv + 1; *p; ++p)
 289     {
 290       if (strcmp (*p, "-E") == 0)
 291         ++p; /* ignore endian spec */
 292       else
 293 #ifdef DEBUG
 294       if (strcmp (*p, "-t") == 0)
 295         mn10300_debug = DEBUG;
 296       else
 297 #endif
 298         (*mn10300_callback->printf_filtered) (mn10300_callback, "ERROR: unsupported option(s): %s\n",*p);
 299     }
 300
 301  /* put all the opcodes in the hash table */
 302   for (s = Simops; s->func; s++)
 303     {
 304       h = &hash_table[hash(s->opcode)];
 305
 306       /* go to the last entry in the chain */
 307       while (h->next)
 308         {
 309           /* Don't insert the same opcode more than once.  */
 310           if (h->opcode == s->opcode
 311               && h->mask == s->mask
 312               && h->ops == s)
 313             break;
 314           else
 315             h = h->next;
 316         }
 317
 318       /* Don't insert the same opcode more than once.  */
 319       if (h->opcode == s->opcode
 320           && h->mask == s->mask
 321           && h->ops == s)
 322         continue;
 323
 324       if (h->ops)
 325         {
 326           h->next = calloc(1,sizeof(struct hash_entry));
 327           h = h->next;
 328         }
 329       h->ops = s;
 330       h->mask = s->mask;
 331       h->opcode = s->opcode;
 332 #if HASH_STAT
 333       h->count = 0;
 334 #endif
 335     }
 336
 337
 338   /* fudge our descriptor for now */
 339   return (SIM_DESC) 1;
 340 }
 341
 342
 343 void
 344 sim_close (sd, quitting)
 345      SIM_DESC sd;
 346      int quitting;
 347 {
 348   /* nothing to do */
 349 }
 350
 351 void
 352 sim_set_profile (n)
 353      int n;
 354 {
 355   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile %d\n", n);
 356 }
 357
 358 void
 359 sim_set_profile_size (n)
 360      int n;
 361 {
 362   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_set_profile_size %d\n", n);
 363 }
 364
 365 int
 366 sim_stop (sd)
 367      SIM_DESC sd;
 368 {
 369   return 0;
 370 }
 371
 372 void
 373 sim_resume (sd, step, siggnal)
 374      SIM_DESC sd;
 375      int step, siggnal;
 376 {
 377   uint32 inst;
 378   reg_t oldpc;
 379   struct hash_entry *h;
 380
 381   if (step)
 382     State.exception = SIGTRAP;
 383   else
 384     State.exception = 0;
 385
 386   State.exited = 0;
 387
 388   do
 389     {
 390       unsigned long insn, extension;
 391
 392       /* Fetch the current instruction.  */
 393       inst = load_mem_big (PC, 2);
 394       oldpc = PC;
 395
 396       /* Using a giant case statement may seem like a waste because of the
 397         code/rodata size the table itself will consume.  However, using
 398         a giant case statement speeds up the simulator by 10-15% by avoiding
 399         cascading if/else statements or cascading case statements.  */
 400
 401       switch ((inst >> 8) & 0xff)
 402         {
 403           /* All the single byte insns except 0x80, 0x90, 0xa0, 0xb0
 404              which must be handled specially.  */
 405           case 0x00:
 406           case 0x04:
 407           case 0x08:
 408           case 0x0c:
 409           case 0x10:
 410           case 0x11:
 411           case 0x12:
 412           case 0x13:
 413           case 0x14:
 414           case 0x15:
 415           case 0x16:
 416           case 0x17:
 417           case 0x18:
 418           case 0x19:
 419           case 0x1a:
 420           case 0x1b:
 421           case 0x1c:
 422           case 0x1d:
 423           case 0x1e:
 424           case 0x1f:
 425           case 0x3c:
 426           case 0x3d:
 427           case 0x3e:
 428           case 0x3f:
 429           case 0x40:
 430           case 0x41:
 431           case 0x44:
 432           case 0x45:
 433           case 0x48:
 434           case 0x49:
 435           case 0x4c:
 436           case 0x4d:
 437           case 0x50:
 438           case 0x51:
 439           case 0x52:
 440           case 0x53:
 441           case 0x54:
 442           case 0x55:
 443           case 0x56:
 444           case 0x57:
 445           case 0x60:
 446           case 0x61:
 447           case 0x62:
 448           case 0x63:
 449           case 0x64:
 450           case 0x65:
 451           case 0x66:
 452           case 0x67:
 453           case 0x68:
 454           case 0x69:
 455           case 0x6a:
 456           case 0x6b:
 457           case 0x6c:
 458           case 0x6d:
 459           case 0x6e:
 460           case 0x6f:
 461           case 0x70:
 462           case 0x71:
 463           case 0x72:
 464           case 0x73:
 465           case 0x74:
 466           case 0x75:
 467           case 0x76:
 468           case 0x77:
 469           case 0x78:
 470           case 0x79:
 471           case 0x7a:
 472           case 0x7b:
 473           case 0x7c:
 474           case 0x7d:
 475           case 0x7e:
 476           case 0x7f:
 477           case 0xcb:
 478           case 0xd0:
 479           case 0xd1:
 480           case 0xd2:
 481           case 0xd3:
 482           case 0xd4:
 483           case 0xd5:
 484           case 0xd6:
 485           case 0xd7:
 486           case 0xd8:
 487           case 0xd9:
 488           case 0xda:
 489           case 0xdb:
 490           case 0xe0:
 491           case 0xe1:
 492           case 0xe2:
 493           case 0xe3:
 494           case 0xe4:
 495           case 0xe5:
 496           case 0xe6:
 497           case 0xe7:
 498           case 0xe8:
 499           case 0xe9:
 500           case 0xea:
 501           case 0xeb:
 502           case 0xec:
 503           case 0xed:
 504           case 0xee:
 505           case 0xef:
 506           case 0xff:
 507             insn = (inst >> 8) & 0xff;
 508             extension = 0;
 509             dispatch (insn, extension, 1);
 510             break;
 511
 512           /* Special cases where dm == dn is used to encode a different
 513              instruction.  */
 514           case 0x80:
 515           case 0x85:
 516           case 0x8a:
 517           case 0x8f:
 518           case 0x90:
 519           case 0x95:
 520           case 0x9a:
 521           case 0x9f:
 522           case 0xa0:
 523           case 0xa5:
 524           case 0xaa:
 525           case 0xaf:
 526           case 0xb0:
 527           case 0xb5:
 528           case 0xba:
 529           case 0xbf:
 530             insn = inst;
 531             extension = 0;
 532             dispatch (insn, extension, 2);
 533             break;
 534
 535           case 0x81:
 536           case 0x82:
 537           case 0x83:
 538           case 0x84:
 539           case 0x86:
 540           case 0x87:
 541           case 0x88:
 542           case 0x89:
 543           case 0x8b:
 544           case 0x8c:
 545           case 0x8d:
 546           case 0x8e:
 547           case 0x91:
 548           case 0x92:
 549           case 0x93:
 550           case 0x94:
 551           case 0x96:
 552           case 0x97:
 553           case 0x98:
 554           case 0x99:
 555           case 0x9b:
 556           case 0x9c:
 557           case 0x9d:
 558           case 0x9e:
 559           case 0xa1:
 560           case 0xa2:
 561           case 0xa3:
 562           case 0xa4:
 563           case 0xa6:
 564           case 0xa7:
 565           case 0xa8:
 566           case 0xa9:
 567           case 0xab:
 568           case 0xac:
 569           case 0xad:
 570           case 0xae:
 571           case 0xb1:
 572           case 0xb2:
 573           case 0xb3:
 574           case 0xb4:
 575           case 0xb6:
 576           case 0xb7:
 577           case 0xb8:
 578           case 0xb9:
 579           case 0xbb:
 580           case 0xbc:
 581           case 0xbd:
 582           case 0xbe:
 583             insn = (inst >> 8) & 0xff;
 584             extension = 0;
 585           dispatch (insn, extension, 1);
 586           break;
 587
 588           /* The two byte instructions.  */
 589           case 0x20:
 590           case 0x21:
 591           case 0x22:
 592           case 0x23:
 593           case 0x28:
 594           case 0x29:
 595           case 0x2a:
 596           case 0x2b:
 597           case 0x42:
 598           case 0x43:
 599           case 0x46:
 600           case 0x47:
 601           case 0x4a:
 602           case 0x4b:
 603           case 0x4e:
 604           case 0x4f:
 605           case 0x58:
 606           case 0x59:
 607           case 0x5a:
 608           case 0x5b:
 609           case 0x5c:
 610           case 0x5d:
 611           case 0x5e:
 612           case 0x5f:
 613           case 0xc0:
 614           case 0xc1:
 615           case 0xc2:
 616           case 0xc3:
 617           case 0xc4:
 618           case 0xc5:
 619           case 0xc6:
 620           case 0xc7:
 621           case 0xc8:
 622           case 0xc9:
 623           case 0xca:
 624           case 0xce:
 625           case 0xcf:
 626           case 0xf0:
 627           case 0xf1:
 628           case 0xf2:
 629           case 0xf3:
 630           case 0xf4:
 631           case 0xf5:
 632           case 0xf6:
 633             insn = inst;
 634             extension = 0;
 635             dispatch (insn, extension, 2);
 636             break;
 637
 638           /* The three byte insns with a 16bit operand in little endian
 639              format.  */
 640           case 0x01:
 641           case 0x02:
 642           case 0x03:
 643           case 0x05:
 644           case 0x06:
 645           case 0x07:
 646           case 0x09:
 647           case 0x0a:
 648           case 0x0b:
 649           case 0x0d:
 650           case 0x0e:
 651           case 0x0f:
 652           case 0x24:
 653           case 0x25:
 654           case 0x26:
 655           case 0x27:
 656           case 0x2c:
 657           case 0x2d:
 658           case 0x2e:
 659           case 0x2f:
 660           case 0x30:
 661           case 0x31:
 662           case 0x32:
 663           case 0x33:
 664           case 0x34:
 665           case 0x35:
 666           case 0x36:
 667           case 0x37:
 668           case 0x38:
 669           case 0x39:
 670           case 0x3a:
 671           case 0x3b:
 672           case 0xcc:
 673             insn = load_byte (PC);
 674             insn <<= 16;
 675             insn |= load_half (PC + 1);
 676             extension = 0;
 677             dispatch (insn, extension, 3);
 678             break;
 679
 680           /* The three byte insns without 16bit operand.  */
 681           case 0xde:
 682           case 0xdf:
 683           case 0xf8:
 684           case 0xf9:
 685             insn = load_mem_big (PC, 3);
 686             extension = 0;
 687             dispatch (insn, extension, 3);
 688             break;
 689
 690           /* Four byte insns.  */
 691           case 0xfa:
 692           case 0xfb:
 693             if ((inst & 0xfffc) == 0xfaf0
 694                 || (inst & 0xfffc) == 0xfaf4
 695                 || (inst & 0xfffc) == 0xfaf8)
 696               insn = load_mem_big (PC, 4);
 697             else
 698               {
 699                 insn = inst;
 700                 insn <<= 16;
 701                 insn |= load_half (PC + 2);
 702                 extension = 0;
 703               }
 704             dispatch (insn, extension, 4);
 705             break;
 706
 707           /* Five byte insns.  */
 708           case 0xcd:
 709             insn = load_byte (PC);
 710             insn <<= 24;
 711             insn |= (load_half (PC + 1) << 8);
 712             insn |= load_byte (PC + 3);
 713             extension = load_byte (PC + 4);
 714             dispatch (insn, extension, 5);
 715             break;
 716
 717           case 0xdc:
 718             insn = load_byte (PC);
 719             insn <<= 24;
 720             extension = load_word (PC + 1);
 721             insn |= (extension & 0xffffff00) >> 8;
 722             extension &= 0xff;
 723             dispatch (insn, extension, 5);
 724             break;
 725
 726           /* Six byte insns.  */
 727           case 0xfc:
 728           case 0xfd:
 729             insn = (inst << 16);
 730             extension = load_word (PC + 2);
 731             insn |= ((extension & 0xffff0000) >> 16);
 732             extension &= 0xffff;
 733             dispatch (insn, extension, 6);
 734             break;
 735
 736           case 0xdd:
 737             insn = load_byte (PC) << 24;
 738             extension = load_word (PC + 1);
 739             insn |= ((extension >> 8) & 0xffffff);
 740             extension = (extension & 0xff) << 16;
 741             extension |= load_byte (PC + 5) << 8;
 742             extension |= load_byte (PC + 6);
 743             dispatch (insn, extension, 7);
 744             break;
 745
 746           case 0xfe:
 747             insn = inst << 16;
 748             extension = load_word (PC + 2);
 749             insn |= ((extension >> 16) & 0xffff);
 750             extension <<= 8;
 751             extension &= 0xffff00;
 752             extension |= load_byte (PC + 6);
 753             dispatch (insn, extension, 7);
 754             break;
 755
 756           default:
 757             abort ();
 758         }
 759     }
 760   while (!State.exception);
 761
 762 #ifdef HASH_STAT
 763   {
 764     int i;
 765     for (i = 0; i < MAX_HASH; i++)
 766       {
 767          struct hash_entry *h;
 768          h = &hash_table[i];
 769
 770          printf("hash 0x%x:\n", i);
 771
 772          while (h)
 773            {
 774              printf("h->opcode = 0x%x, count = 0x%x\n", h->opcode, h->count);
 775              h = h->next;
 776            }
 777
 778          printf("\n\n");
 779       }
 780     fflush (stdout);
 781   }
 782 #endif
 783
 784 }
 785
 786 int
 787 sim_trace (sd)
 788      SIM_DESC sd;
 789 {
 790 #ifdef DEBUG
 791   mn10300_debug = DEBUG;
 792 #endif
 793   sim_resume (sd, 0, 0);
 794   return 1;
 795 }
 796
 797 void
 798 sim_info (sd, verbose)
 799      SIM_DESC sd;
 800      int verbose;
 801 {
 802   (*mn10300_callback->printf_filtered) (mn10300_callback, "sim_info\n");
 803 }
 804
 805 SIM_RC
 806 sim_create_inferior (sd, abfd, argv, env)
 807      SIM_DESC sd;
 808      struct _bfd *abfd;
 809      char **argv;
 810      char **env;
 811 {
 812   if (abfd != NULL)
 813     PC = bfd_get_start_address (abfd);
 814   else
 815     PC = 0;
 816   return SIM_RC_OK;
 817 }
 818
 819 void
 820 sim_set_callbacks (p)
 821      host_callback *p;
 822 {
 823   mn10300_callback = p;
 824 }
 825
 826 /* All the code for exiting, signals, etc needs to be revamped.
 827
 828    This is enough to get c-torture limping though.  */
 829
 830 void
 831 sim_stop_reason (sd, reason, sigrc)
 832      SIM_DESC sd;
 833      enum sim_stop *reason;
 834      int *sigrc;
 835 {
 836   if (State.exited)
 837     *reason = sim_exited;
 838   else
 839     *reason = sim_stopped;
 840   if (State.exception == SIGQUIT)
 841     *sigrc = 0;
 842   else
 843     *sigrc = State.exception;
 844 }
 845
 846 int
 847 sim_read (sd, addr, buffer, size)
 848      SIM_DESC sd;
 849      SIM_ADDR addr;
 850      unsigned char *buffer;
 851      int size;
 852 {
 853   int i;
 854   for (i = 0; i < size; i++)
 855     buffer[i] = load_byte (addr + i);
 856
 857   return size;
 858 }
 859
 860 void
 861 sim_do_command (sd, cmd)
 862      SIM_DESC sd;
 863      char *cmd;
 864 {
 865   (*mn10300_callback->printf_filtered) (mn10300_callback, "\"%s\" is not a valid mn10300 simulator command.\n", cmd);
 866 }
 867
 868 SIM_RC
 869 sim_load (sd, prog, abfd, from_tty)
 870      SIM_DESC sd;
 871      char *prog;
 872      bfd *abfd;
 873      int from_tty;
 874 {
 875   extern bfd *sim_load_file (); /* ??? Don't know where this should live.  */
 876   bfd *prog_bfd;
 877
 878   prog_bfd = sim_load_file (sd, myname, mn10300_callback, prog, abfd,
 879                             sim_kind == SIM_OPEN_DEBUG,
 880                             0, sim_write);
 881   if (prog_bfd == NULL)
 882     return SIM_RC_FAIL;
 883   if (abfd == NULL)
 884     bfd_close (prog_bfd);
 885   return SIM_RC_OK;
 886 }
 887 #endif  /* not WITH_COMMON */
 888
 889
 890 #if WITH_COMMON
 891
 892 /* For compatibility */
 893 SIM_DESC simulator;
 894
 895 /* mn10300 interrupt model */
 896
 897 enum interrupt_type
 898 {
 899   int_reset,
 900   int_nmi,
 901   int_intov1,
 902   int_intp10,
 903   int_intp11,
 904   int_intp12,
 905   int_intp13,
 906   int_intcm4,
 907   num_int_types
 908 };
 909
 910 char *interrupt_names[] = {
 911   "reset",
 912   "nmi",
 913   "intov1",
 914   "intp10",
 915   "intp11",
 916   "intp12",
 917   "intp13",
 918   "intcm4",
 919   NULL
 920 };
 921
 922
 923 static void
 924 do_interrupt (sd, data)
 925      SIM_DESC sd;
 926      void *data;
 927 {
 928 #if 0
 929   char **interrupt_name = (char**)data;
 930   enum interrupt_type inttype;
 931   inttype = (interrupt_name - STATE_WATCHPOINTS (sd)->interrupt_names);
 932
 933   /* For a hardware reset, drop everything and jump to the start
 934      address */
 935   if (inttype == int_reset)
 936     {
 937       PC = 0;
 938       PSW = 0x20;
 939       ECR = 0;
 940       sim_engine_restart (sd, NULL, NULL, NULL_CIA);
 941     }
 942
 943   /* Deliver an NMI when allowed */
 944   if (inttype == int_nmi)
 945     {
 946       if (PSW & PSW_NP)
 947         {
 948           /* We're already working on an NMI, so this one must wait
 949              around until the previous one is done.  The processor
 950              ignores subsequent NMIs, so we don't need to count them.
 951              Just keep re-scheduling a single NMI until it manages to
 952              be delivered */
 953           if (STATE_CPU (sd, 0)->pending_nmi != NULL)
 954             sim_events_deschedule (sd, STATE_CPU (sd, 0)->pending_nmi);
 955           STATE_CPU (sd, 0)->pending_nmi =
 956             sim_events_schedule (sd, 1, do_interrupt, data);
 957           return;
 958         }
 959       else
 960         {
 961           /* NMI can be delivered.  Do not deschedule pending_nmi as
 962              that, if still in the event queue, is a second NMI that
 963              needs to be delivered later. */
 964           FEPC = PC;
 965           FEPSW = PSW;
 966           /* Set the FECC part of the ECR. */
 967           ECR &= 0x0000ffff;
 968           ECR |= 0x10;
 969           PSW |= PSW_NP;
 970           PSW &= ~PSW_EP;
 971           PSW |= PSW_ID;
 972           PC = 0x10;
 973           sim_engine_restart (sd, NULL, NULL, NULL_CIA);
 974         }
 975     }
 976
 977   /* deliver maskable interrupt when allowed */
 978   if (inttype > int_nmi && inttype < num_int_types)
 979     {
 980       if ((PSW & PSW_NP) || (PSW & PSW_ID))
 981         {
 982           /* Can't deliver this interrupt, reschedule it for later */
 983           sim_events_schedule (sd, 1, do_interrupt, data);
 984           return;
 985         }
 986       else
 987         {
 988           /* save context */
 989           EIPC = PC;
 990           EIPSW = PSW;
 991           /* Disable further interrupts.  */
 992           PSW |= PSW_ID;
 993           /* Indicate that we're doing interrupt not exception processing.  */
 994           PSW &= ~PSW_EP;
 995           /* Clear the EICC part of the ECR, will set below. */
 996           ECR &= 0xffff0000;
 997           switch (inttype)
 998             {
 999             case int_intov1:
1000               PC = 0x80;
1001               ECR |= 0x80;
1002               break;
1003             case int_intp10:
1004               PC = 0x90;
1005               ECR |= 0x90;
1006               break;
1007             case int_intp11:
1008               PC = 0xa0;
1009               ECR |= 0xa0;
1010               break;
1011             case int_intp12:
1012               PC = 0xb0;
1013               ECR |= 0xb0;
1014               break;
1015             case int_intp13:
1016               PC = 0xc0;
1017               ECR |= 0xc0;
1018               break;
1019             case int_intcm4:
1020               PC = 0xd0;
1021               ECR |= 0xd0;
1022               break;
1023             default:
1024               /* Should never be possible.  */
1025               sim_engine_abort (sd, NULL, NULL_CIA,
1026                                 "do_interrupt - internal error - bad switch");
1027               break;
1028             }
1029         }
1030       sim_engine_restart (sd, NULL, NULL, NULL_CIA);
1031     }
1032
1033   /* some other interrupt? */
1034   sim_engine_abort (sd, NULL, NULL_CIA,
1035                     "do_interrupt - internal error - interrupt %d unknown",
1036                     inttype);
1037 #endif  /* 0 */
1038 }
1039
1040 /* These default values correspond to expected usage for the chip.  */
1041
1042 SIM_DESC
1043 sim_open (kind, cb, abfd, argv)
1044      SIM_OPEN_KIND kind;
1045      host_callback *cb;
1046      struct _bfd *abfd;
1047      char **argv;
1048 {
1049   SIM_DESC sd = sim_state_alloc (kind, cb);
1050   mn10300_callback = cb;
1051
1052   SIM_ASSERT (STATE_MAGIC (sd) == SIM_MAGIC_NUMBER);
1053
1054   /* for compatibility */
1055   simulator = sd;
1056
1057   /* FIXME: should be better way of setting up interrupts */
1058   STATE_WATCHPOINTS (sd)->pc = &(PC);
1059   STATE_WATCHPOINTS (sd)->sizeof_pc = sizeof (PC);
1060   STATE_WATCHPOINTS (sd)->interrupt_handler = do_interrupt;
1061   STATE_WATCHPOINTS (sd)->interrupt_names = interrupt_names;
1062
1063   if (sim_pre_argv_init (sd, argv[0]) != SIM_RC_OK)
1064     return 0;
1065
1066   /* Allocate core managed memory */
1067
1068   /* "Mirror" the ROM addresses below 1MB. */
1069   sim_do_command (sd, "memory region 0,0x100000");
1070
1071   /* getopt will print the error message so we just have to exit if this fails.
1072      FIXME: Hmmm...  in the case of gdb we need getopt to call
1073      print_filtered.  */
1074   if (sim_parse_args (sd, argv) != SIM_RC_OK)
1075     {
1076       /* Uninstall the modules to avoid memory leaks,
1077          file descriptor leaks, etc.  */
1078       sim_module_uninstall (sd);
1079       return 0;
1080     }
1081
1082   /* check for/establish the a reference program image */
1083   if (sim_analyze_program (sd,
1084                            (STATE_PROG_ARGV (sd) != NULL
1085                             ? *STATE_PROG_ARGV (sd)
1086                             : NULL),
1087                            abfd) != SIM_RC_OK)
1088     {
1089       sim_module_uninstall (sd);
1090       return 0;
1091     }
1092
1093   /* establish any remaining configuration options */
1094   if (sim_config (sd) != SIM_RC_OK)
1095     {
1096       sim_module_uninstall (sd);
1097       return 0;
1098     }
1099
1100   if (sim_post_argv_init (sd) != SIM_RC_OK)
1101     {
1102       /* Uninstall the modules to avoid memory leaks,
1103          file descriptor leaks, etc.  */
1104       sim_module_uninstall (sd);
1105       return 0;
1106     }
1107
1108
1109   /* set machine specific configuration */
1110 /*   STATE_CPU (sd, 0)->psw_mask = (PSW_NP | PSW_EP | PSW_ID | PSW_SAT */
1111 /*                           | PSW_CY | PSW_OV | PSW_S | PSW_Z); */
1112
1113   return sd;
1114 }
1115
1116
1117 void
1118 sim_close (sd, quitting)
1119      SIM_DESC sd;
1120      int quitting;
1121 {
1122   sim_module_uninstall (sd);
1123 }
1124
1125
1126 SIM_RC
1127 sim_create_inferior (sd, prog_bfd, argv, env)
1128      SIM_DESC sd;
1129      struct _bfd *prog_bfd;
1130      char **argv;
1131      char **env;
1132 {
1133   memset (&State, 0, sizeof (State));
1134   if (prog_bfd != NULL) {
1135     PC = bfd_get_start_address (prog_bfd);
1136   } else {
1137     PC = 0;
1138   }
1139   CIA_SET (STATE_CPU (sd, 0), (unsigned64) PC);
1140
1141   return SIM_RC_OK;
1142 }
1143
1144 void
1145 sim_do_command (sd, cmd)
1146      SIM_DESC sd;
1147      char *cmd;
1148 {
1149   char *mm_cmd = "memory-map";
1150   char *int_cmd = "interrupt";
1151
1152   if (sim_args_command (sd, cmd) != SIM_RC_OK)
1153     {
1154       if (strncmp (cmd, mm_cmd, strlen (mm_cmd) == 0))
1155         sim_io_eprintf (sd, "`memory-map' command replaced by `sim memory'\n");
1156       else if (strncmp (cmd, int_cmd, strlen (int_cmd)) == 0)
1157         sim_io_eprintf (sd, "`interrupt' command replaced by `sim watch'\n");
1158       else
1159         sim_io_eprintf (sd, "Unknown command `%s'\n", cmd);
1160     }
1161 }
1162 #endif  /* WITH_COMMON */
1163
1164 /* FIXME These would more efficient to use than load_mem/store_mem,
1165    but need to be changed to use the memory map.  */
1166
1167 uint8
1168 get_byte (x)
1169      uint8 *x;
1170 {
1171   return *x;
1172 }
1173
1174 uint16
1175 get_half (x)
1176      uint8 *x;
1177 {
1178   uint8 *a = x;
1179   return (a[1] << 8) + (a[0]);
1180 }
1181
1182 uint32
1183 get_word (x)
1184       uint8 *x;
1185 {
1186   uint8 *a = x;
1187   return (a[3]<<24) + (a[2]<<16) + (a[1]<<8) + (a[0]);
1188 }
1189
1190 void
1191 put_byte (addr, data)
1192      uint8 *addr;
1193      uint8 data;
1194 {
1195   uint8 *a = addr;
1196   a[0] = data;
1197 }
1198
1199 void
1200 put_half (addr, data)
1201      uint8 *addr;
1202      uint16 data;
1203 {
1204   uint8 *a = addr;
1205   a[0] = data & 0xff;
1206   a[1] = (data >> 8) & 0xff;
1207 }
1208
1209 void
1210 put_word (addr, data)
1211      uint8 *addr;
1212      uint32 data;
1213 {
1214   uint8 *a = addr;
1215   a[0] = data & 0xff;
1216   a[1] = (data >> 8) & 0xff;
1217   a[2] = (data >> 16) & 0xff;
1218   a[3] = (data >> 24) & 0xff;
1219 }
1220
1221 int
1222 sim_fetch_register (sd, rn, memory, length)
1223      SIM_DESC sd;
1224      int rn;
1225      unsigned char *memory;
1226      int length;
1227 {
1228   put_word (memory, State.regs[rn]);
1229   return -1;
1230 }
1231
1232 int
1233 sim_store_register (sd, rn, memory, length)
1234      SIM_DESC sd;
1235      int rn;
1236      unsigned char *memory;
1237      int length;
1238 {
1239   State.regs[rn] = get_word (memory);
1240   return -1;
1241 }