sim/mn10300/mn10300_sim.h

   1 #include <stdio.h>
   2 #include <ctype.h>
   3 #include "ansidecl.h"
   4 #include "sim/callback.h"
   5 #include "opcode/mn10300.h"
   6 #include <limits.h>
   7 #include "sim/sim.h"
   8 #include "bfd.h"
   9 #include "sim-fpu.h"
  10 #include "sim-signal.h"
  11
  12 extern SIM_DESC simulator;
  13
  14 typedef struct
  15 {
  16   uint32_t low, high;
  17 } dword;
  18 typedef uint32_t reg_t;
  19
  20 struct simops
  21 {
  22   long opcode;
  23   long mask;
  24   void (*func)();
  25   int length;
  26   int format;
  27   int numops;
  28   int operands[16];
  29 };
  30
  31 /* The current state of the processor; registers, memory, etc.  */
  32
  33 struct _state
  34 {
  35   reg_t regs[32];               /* registers, d0-d3, a0-a3, sp, pc, mdr, psw,
  36                                    lir, lar, mdrq, plus some room for processor
  37                                    specific regs.  */
  38   union
  39   {
  40     reg_t fs[32]; /* FS0-31 */
  41     dword fd[16]; /* FD0,2,...,30 */
  42   } fpregs;
  43
  44   /* All internal state modified by signal_exception() that may need to be
  45      rolled back for passing moment-of-exception image back to gdb. */
  46   reg_t exc_trigger_regs[32];
  47   reg_t exc_suspend_regs[32];
  48   int exc_suspended;
  49
  50 #define SIM_CPU_EXCEPTION_TRIGGER(SD,CPU,CIA) mn10300_cpu_exception_trigger(SD,CPU,CIA)
  51 #define SIM_CPU_EXCEPTION_SUSPEND(SD,CPU,EXC) mn10300_cpu_exception_suspend(SD,CPU,EXC)
  52 #define SIM_CPU_EXCEPTION_RESUME(SD,CPU,EXC) mn10300_cpu_exception_resume(SD,CPU,EXC)
  53 };
  54
  55 extern struct _state State;
  56
  57 #define PC      (State.regs[REG_PC])
  58 #define SP      (State.regs[REG_SP])
  59
  60 #define PSW (State.regs[11])
  61 #define PSW_Z 0x1
  62 #define PSW_N 0x2
  63 #define PSW_C 0x4
  64 #define PSW_V 0x8
  65 #define PSW_IE LSBIT (11)
  66 #define PSW_LM LSMASK (10, 8)
  67
  68 #define EXTRACT_PSW_LM LSEXTRACTED16 (PSW, 10, 8)
  69 #define INSERT_PSW_LM(l) LSINSERTED16 ((l), 10, 8)
  70
  71 #define REG_D0 0
  72 #define REG_A0 4
  73 #define REG_SP 8
  74 #define REG_PC 9
  75 #define REG_MDR 10
  76 #define REG_PSW 11
  77 #define REG_LIR 12
  78 #define REG_LAR 13
  79 #define REG_MDRQ 14
  80 #define REG_E0 15
  81 #define REG_SSP 23
  82 #define REG_MSP 24
  83 #define REG_USP 25
  84 #define REG_MCRH 26
  85 #define REG_MCRL 27
  86 #define REG_MCVF 28
  87
  88 #define REG_FPCR 29
  89
  90 #define FPCR (State.regs[REG_FPCR])
  91
  92 #define FCC_MASK LSMASK (21, 18)
  93 #define RM_MASK  LSMASK (17, 16) /* Must always be zero.  */
  94 #define EC_MASK  LSMASK (14, 10)
  95 #define EE_MASK  LSMASK ( 9,  5)
  96 #define EF_MASK  LSMASK ( 4,  0)
  97 #define FPCR_MASK (FCC_MASK | EC_MASK | EE_MASK | EF_MASK)
  98
  99 #define FCC_L LSBIT (21)
 100 #define FCC_G LSBIT (20)
 101 #define FCC_E LSBIT (19)
 102 #define FCC_U LSBIT (18)
 103
 104 #define EC_V LSBIT (14)
 105 #define EC_Z LSBIT (13)
 106 #define EC_O LSBIT (12)
 107 #define EC_U LSBIT (11)
 108 #define EC_I LSBIT (10)
 109
 110 #define EE_V LSBIT (9)
 111 #define EE_Z LSBIT (8)
 112 #define EE_O LSBIT (7)
 113 #define EE_U LSBIT (6)
 114 #define EE_I LSBIT (5)
 115
 116 #define EF_V LSBIT (4)
 117 #define EF_Z LSBIT (3)
 118 #define EF_O LSBIT (2)
 119 #define EF_U LSBIT (1)
 120 #define EF_I LSBIT (0)
 121
 122 #define PSW_FE LSBIT(20)
 123 #define FPU_DISABLED !(PSW & PSW_FE)
 124
 125 #define XS2FS(X,S) State.fpregs.fs[((X<<4)|(S))]
 126 #define AS2FS(A,S) State.fpregs.fs[((A<<2)|(S))]
 127 #define Xf2FD(X,f) State.fpregs.fd[((X<<3)|(f))]
 128
 129 #define FS2FPU(FS,F) sim_fpu_32to (&(F), (FS))
 130 #define FD2FPU(FD,F) sim_fpu_232to (&(F), ((FD).high), ((FD).low))
 131 #define FPU2FS(F,FS) sim_fpu_to32 (&(FS), &(F))
 132 #define FPU2FD(F,FD) sim_fpu_to232 (&((FD).high), &((FD).low), &(F))
 133
 134 #define FETCH32(a,b,c,d) \
 135  ((a)+((b)<<8)+((c)<<16)+((d)<<24))
 136
 137 #define FETCH24(a,b,c) \
 138  ((a)+((b)<<8)+((c)<<16))
 139
 140 #define FETCH16(a,b) ((a)+((b)<<8))
 141
 142 #define load_byte(ADDR) \
 143 sim_core_read_unaligned_1 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 144
 145 #define load_half(ADDR) \
 146 sim_core_read_unaligned_2 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 147
 148 #define load_word(ADDR) \
 149 sim_core_read_unaligned_4 (STATE_CPU (simulator, 0), PC, read_map, (ADDR))
 150
 151 #define load_dword(ADDR) \
 152 u642dw (sim_core_read_unaligned_8 (STATE_CPU (simulator, 0), \
 153                                    PC, read_map, (ADDR)))
 154
 155 static INLINE2 dword
 156 u642dw (uint64_t dw)
 157 {
 158   dword r;
 159
 160   r.low = (uint32_t)dw;
 161   r.high = (uint32_t)(dw >> 32);
 162   return r;
 163 }
 164
 165 #define store_byte(ADDR, DATA) \
 166 sim_core_write_unaligned_1 (STATE_CPU (simulator, 0), \
 167                             PC, write_map, (ADDR), (DATA))
 168
 169
 170 #define store_half(ADDR, DATA) \
 171 sim_core_write_unaligned_2 (STATE_CPU (simulator, 0), \
 172                             PC, write_map, (ADDR), (DATA))
 173
 174
 175 #define store_word(ADDR, DATA) \
 176 sim_core_write_unaligned_4 (STATE_CPU (simulator, 0), \
 177                             PC, write_map, (ADDR), (DATA))
 178 #define store_dword(ADDR, DATA) \
 179 sim_core_write_unaligned_8 (STATE_CPU (simulator, 0), \
 180                             PC, write_map, (ADDR), dw2u64 (DATA))
 181
 182 static INLINE2 uint64_t
 183 dw2u64 (dword data)
 184 {
 185   return data.low | (((uint64_t)data.high) << 32);
 186 }
 187
 188 /* Function declarations.  */
 189
 190 INLINE_SIM_MAIN (void) genericAdd (uint32_t source, uint32_t destReg);
 191 INLINE_SIM_MAIN (void) genericSub (uint32_t source, uint32_t destReg);
 192 INLINE_SIM_MAIN (void) genericCmp (uint32_t leftOpnd, uint32_t rightOpnd);
 193 INLINE_SIM_MAIN (void) genericOr (uint32_t source, uint32_t destReg);
 194 INLINE_SIM_MAIN (void) genericXor (uint32_t source, uint32_t destReg);
 195 INLINE_SIM_MAIN (void) genericBtst (uint32_t leftOpnd, uint32_t rightOpnd);
 196 INLINE_SIM_MAIN (void) do_syscall (SIM_DESC sd);
 197 void program_interrupt (SIM_DESC sd, sim_cpu *cpu, sim_cia cia, SIM_SIGNAL sig);
 198
 199 void mn10300_cpu_exception_trigger(SIM_DESC sd, sim_cpu* cpu, address_word pc);
 200 void mn10300_cpu_exception_suspend(SIM_DESC sd, sim_cpu* cpu, int exception);
 201 void mn10300_cpu_exception_resume(SIM_DESC sd, sim_cpu* cpu, int exception);
 202
 203 void fpu_disabled_exception     (SIM_DESC, sim_cpu *, address_word);
 204 void fpu_unimp_exception        (SIM_DESC, sim_cpu *, address_word);
 205 void fpu_check_signal_exception (SIM_DESC, sim_cpu *, address_word);
 206
 207 extern const struct fp_prec_t
 208 {
 209   void (* reg2val) (const void *, sim_fpu *);
 210   int (*  round)   (sim_fpu *);
 211   void (* val2reg) (const sim_fpu *, void *);
 212 } fp_single_prec, fp_double_prec;
 213
 214 #define FP_SINGLE (&fp_single_prec)
 215 #define FP_DOUBLE (&fp_double_prec)
 216
 217 void fpu_rsqrt  (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
 218 void fpu_sqrt   (SIM_DESC, sim_cpu *, address_word, const void *, void *, const struct fp_prec_t *);
 219 void fpu_cmp    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const struct fp_prec_t *);
 220 void fpu_add    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 221 void fpu_sub    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 222 void fpu_mul    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 223 void fpu_div    (SIM_DESC, sim_cpu *, address_word, const void *, const void *, void *, const struct fp_prec_t *);
 224 void fpu_fmadd  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 225 void fpu_fmsub  (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 226 void fpu_fnmadd (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);
 227 void fpu_fnmsub (SIM_DESC, sim_cpu *, address_word, const void *, const void *, const void *, void *, const struct fp_prec_t *);