sim/mn10300/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #ifdef HAVE_UNISTD_H
   5 #include <unistd.h>
   6 #endif
   7 #include "mn10300_sim.h"
   8 #include "simops.h"
   9 #include "sys/syscall.h"
  10 #include "bfd.h"
  11 #include <errno.h>
  12 #include <sys/stat.h>
  13 #include <sys/times.h>
  14 #include <sys/time.h>
  15
  16 enum op_types {
  17   OP_UNKNOWN,
  18 };
  19
  20 #ifdef DEBUG
  21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
  22 static void trace_output PARAMS ((enum op_types result));
  23 static int init_text_p = 0;
  24 static asection *text;
  25 static bfd_vma text_start;
  26 static bfd_vma text_end;
  27 extern bfd *exec_bfd;
  28
  29 #ifndef SIZE_INSTRUCTION
  30 #define SIZE_INSTRUCTION 6
  31 #endif
  32
  33 #ifndef SIZE_OPERANDS
  34 #define SIZE_OPERANDS 16
  35 #endif
  36
  37 #ifndef SIZE_VALUES
  38 #define SIZE_VALUES 11
  39 #endif
  40
  41 #ifndef SIZE_LOCATION
  42 #define SIZE_LOCATION 40
  43 #endif
  44
  45 static void
  46 trace_input (name, type, size)
  47      char *name;
  48      enum op_types type;
  49      int size;
  50 {
  51 }
  52
  53 static void
  54 trace_output (result)
  55      enum op_types result;
  56 {
  57 }
  58
  59 #else
  60 #define trace_input(NAME, IN1, IN2)
  61 #define trace_output(RESULT)
  62 #endif
  63
  64 \f
  65 /* mov imm8, dn */
  66 void OP_8000 ()
  67 {
  68   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
  69 }
  70
  71 /* mov dm, dn */
  72 void OP_80 ()
  73 {
  74   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
  75 }
  76
  77 /* mov dm, an */
  78 void OP_F1E0 ()
  79 {
  80   State.regs[REG_A0 + ((insn & 0xc) >> 2)] = State.regs[REG_D0 + (insn & 0x3)];
  81 }
  82
  83 /* mov am, dn */
  84 void OP_F1D0 ()
  85 {
  86   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  87 }
  88
  89 /* mov imm8, an */
  90 void OP_9000 ()
  91 {
  92   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = insn & 0xff;
  93 }
  94
  95 /* mov am, an */
  96 void OP_90 ()
  97 {
  98   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  99 }
 100
 101 /* mov sp, an */
 102 void OP_3C ()
 103 {
 104   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
 105 }
 106
 107 /* mov am, sp */
 108 void OP_F2F0 ()
 109 {
 110   State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 111 }
 112
 113 /* mov psw, dn */
 114 void OP_F2E4 ()
 115 {
 116   State.regs[REG_D0 + (insn & 0x3)] = PSW;
 117 }
 118
 119 /* mov dm, psw */
 120 void OP_F2F3 ()
 121 {
 122   PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 123 }
 124
 125 /* mov mdr, dn */
 126 void OP_F2E0 ()
 127 {
 128   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
 129 }
 130
 131 /* mov dm, mdr */
 132 void OP_F2F2 ()
 133 {
 134   State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 135 }
 136
 137 /* mov (am), dn */
 138 void OP_70 ()
 139 {
 140   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 141     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 142 }
 143
 144 /* mov (d8,am), dn */
 145 void OP_F80000 ()
 146 {
 147   State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
 148     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 149                  + SEXT8 (insn & 0xff)), 4);
 150 }
 151
 152 /* mov */
 153 void OP_FA000000 ()
 154 {
 155 }
 156
 157 /* mov */
 158 void OP_FC000000 ()
 159 {
 160 }
 161
 162 /* mov (d8,sp), dn */
 163 void OP_5800 ()
 164 {
 165   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 166     = load_mem (State.regs[REG_SP] + insn & 0xff, 4);
 167 }
 168
 169 /* mov */
 170 void OP_FAB40000 ()
 171 {
 172 }
 173
 174 /* mov */
 175 void OP_FCB40000 ()
 176 {
 177 }
 178
 179 /* mov (di,am), dn */
 180 void OP_F300 ()
 181 {
 182   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 183     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 184                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
 185 }
 186
 187 /* mov (abs16), dn */
 188 void OP_300000 ()
 189 {
 190   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 4);
 191 }
 192
 193 /* mov */
 194 void OP_FCA40000 ()
 195 {
 196 }
 197
 198 /* mov (am), an */
 199 void OP_F000 ()
 200 {
 201   State.regs[REG_A0 + ((insn & 0xc) >> 2)]
 202     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 203 }
 204
 205 /* mov (d8,am), an */
 206 void OP_F82000 ()
 207 {
 208   State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
 209     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 210                  + SEXT8 (insn & 0xff)), 4);
 211 }
 212
 213 /* mov */
 214 void OP_FA200000 ()
 215 {
 216 }
 217
 218 /* mov */
 219 void OP_FC200000 ()
 220 {
 221 }
 222
 223 /* mov (d8,sp), an */
 224 void OP_5C00 ()
 225 {
 226   State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 227     = load_mem (State.regs[REG_SP] + insn & 0xff, 4);
 228 }
 229
 230 /* mov */
 231 void OP_FAB00000 ()
 232 {
 233 }
 234
 235 /* mov */
 236 void OP_FCB00000 ()
 237 {
 238 }
 239
 240 /* mov (di,am), an*/
 241 void OP_F380 ()
 242 {
 243   State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 244     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 245                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
 246 }
 247
 248 /* mov */
 249 void OP_FAA00000 ()
 250 {
 251 }
 252
 253 /* mov */
 254 void OP_FCA00000 ()
 255 {
 256 }
 257
 258 /* mov (d8,am), sp */
 259 void OP_F8F000 ()
 260 {
 261   State.regs[REG_SP]
 262     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 263                  + SEXT8 (insn & 0xff)), 4);
 264 }
 265
 266 /* mov dm, (an) */
 267 void OP_60 ()
 268 {
 269   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 270              State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
 271 }
 272
 273 /* mov dm, (d8,an) */
 274 void OP_F81000 ()
 275 {
 276   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 277               + SEXT8 (insn & 0xff)), 4,
 278              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 279 }
 280
 281 /* mov */
 282 void OP_FA100000 ()
 283 {
 284 }
 285
 286 /* mov */
 287 void OP_FC100000 ()
 288 {
 289 }
 290
 291 /* mov dm, (d8,sp) */
 292 void OP_4200 ()
 293 {
 294   store_mem (State.regs[REG_SP] + insn & 0xff, 4,
 295              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 296 }
 297
 298 /* mov */
 299 void OP_FA910000 ()
 300 {
 301 }
 302
 303 /* mov */
 304 void OP_FC910000 ()
 305 {
 306 }
 307
 308 /* mov dm, (di,an) */
 309 void OP_F340 ()
 310 {
 311   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 312               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
 313              State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
 314 }
 315
 316 /* mov dm, (abs16) */
 317 void OP_10000 ()
 318 {
 319   store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 320 }
 321
 322 /* mov */
 323 void OP_FC810000 ()
 324 {
 325 }
 326
 327 /* mov am, (an) */
 328 void OP_F010 ()
 329 {
 330   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 331              State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
 332 }
 333
 334 /* mov am, (d8,an) */
 335 void OP_F83000 ()
 336 {
 337   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 338               + SEXT8 (insn & 0xff)), 4,
 339              State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
 340 }
 341
 342 /* mov */
 343 void OP_FA300000 ()
 344 {
 345 }
 346
 347 /* mov */
 348 void OP_FC300000 ()
 349 {
 350 }
 351
 352 /* mov am, (d8,sp) */
 353 void OP_4300 ()
 354 {
 355   store_mem (State.regs[REG_SP] + insn & 0xff, 4,
 356              State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
 357 }
 358
 359 /* mov */
 360 void OP_FA900000 ()
 361 {
 362 }
 363
 364 /* mov */
 365 void OP_FC900000 ()
 366 {
 367 }
 368
 369 /* mov am, (di,an) */
 370 void OP_F3C0 ()
 371 {
 372   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 373               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
 374              State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
 375 }
 376
 377 /* mov */
 378 void OP_FA800000 ()
 379 {
 380 }
 381
 382 /* mov */
 383 void OP_FC800000 ()
 384 {
 385 }
 386
 387 /* mov sp, (d8,an) */
 388 void OP_F8F400 ()
 389 {
 390   store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
 391              4, State.regs[REG_SP]);
 392 }
 393
 394 /* mov imm16, dn */
 395 void OP_2C0000 ()
 396 {
 397   unsigned long value;
 398
 399   value = SEXT16 (insn & 0xffff);
 400   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 401 }
 402
 403 /* mov */
 404 void OP_FCCC0000 ()
 405 {
 406 }
 407
 408 /* mov imm16, an */
 409 void OP_240000 ()
 410 {
 411   unsigned long value;
 412
 413   value = insn & 0xffff;
 414   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 415 }
 416
 417 /* mov imm32, an*/
 418 void OP_FCDC0000 ()
 419 {
 420   unsigned long value;
 421
 422   value = (insn & 0xffff) << 16 | extension;
 423   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 424 }
 425
 426 /* movbu (am), dn */
 427 void OP_F040 ()
 428 {
 429   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 430     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
 431 }
 432
 433 /* movbu (d8,am), dn */
 434 void OP_F84000 ()
 435 {
 436   State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
 437     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 438                  + SEXT8 (insn & 0xff)), 1);
 439 }
 440
 441 /* movbu */
 442 void OP_FA400000 ()
 443 {
 444 }
 445
 446 /* movbu */
 447 void OP_FC400000 ()
 448 {
 449 }
 450
 451 /* movbu (d8,sp), dn */
 452 void OP_F8B800 ()
 453 {
 454   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 455     = load_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 1);
 456 }
 457
 458 /* movbu */
 459 void OP_FAB80000 ()
 460 {
 461 }
 462
 463 /* movbu */
 464 void OP_FCB80000 ()
 465 {
 466 }
 467
 468 /* movbu (di,am), dn */
 469 void OP_F400 ()
 470 {
 471   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 472     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 473                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
 474 }
 475
 476 /* movbu (abs16), dn */
 477 void OP_340000 ()
 478 {
 479   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 1);
 480 }
 481
 482 /* movbu */
 483 void OP_FCA80000 ()
 484 {
 485 }
 486
 487 /* movbu dm, (an) */
 488 void OP_F050 ()
 489 {
 490   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
 491              State.regs[REG_D0 + (insn & 0x3)]);
 492 }
 493
 494 /* movbu dm, (d8,an) */
 495 void OP_F85000 ()
 496 {
 497   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 498               + SEXT8 (insn & 0xff)), 1,
 499              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 500 }
 501
 502 /* movbu */
 503 void OP_FA500000 ()
 504 {
 505 }
 506
 507 /* movbu */
 508 void OP_FC500000 ()
 509 {
 510 }
 511
 512 /* movbu dm, (d8,sp) */
 513 void OP_F89200 ()
 514 {
 515   store_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 1,
 516              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 517 }
 518
 519 /* movbu */
 520 void OP_FA920000 ()
 521 {
 522 }
 523
 524 /* movbu */
 525 void OP_FC920000 ()
 526 {
 527 }
 528
 529 /* movbu dm, (di,an) */
 530 void OP_F440 ()
 531 {
 532   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 533               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
 534              State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
 535 }
 536
 537 /* movbu dm, (abs16) */
 538 void OP_20000 ()
 539 {
 540   store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 541 }
 542
 543 /* movbu */
 544 void OP_FC820000 ()
 545 {
 546 }
 547
 548 /* movhu (am), dn */
 549 void OP_F060 ()
 550 {
 551   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 552     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
 553 }
 554
 555 /* movhu (d8,am), dn */
 556 void OP_F86000 ()
 557 {
 558   State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
 559     = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 560                  + SEXT8 (insn & 0xff)), 2);
 561 }
 562
 563 /* movhu */
 564 void OP_FA600000 ()
 565 {
 566 }
 567
 568 /* movhu */
 569 void OP_FC600000 ()
 570 {
 571 }
 572
 573 /* movhu (d8,sp) dn */
 574 void OP_F8BC00 ()
 575 {
 576   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 577     = load_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 2);
 578 }
 579
 580 /* movhu */
 581 void OP_FABC0000 ()
 582 {
 583 }
 584
 585 /* movhu */
 586 void OP_FCBC0000 ()
 587 {
 588 }
 589
 590 /* movhu (di,am), dn */
 591 void OP_F480 ()
 592 {
 593   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 594     = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
 595                  + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
 596 }
 597
 598 /* movhu (abs16), dn */
 599 void OP_380000 ()
 600 {
 601   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 2);
 602 }
 603
 604 /* movhu */
 605 void OP_FCAC0000 ()
 606 {
 607 }
 608
 609 /* movhu dm, (an) */
 610 void OP_F070 ()
 611 {
 612   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 2,
 613              State.regs[REG_D0 + (insn & 0x3)]);
 614 }
 615
 616 /* movhu dm, (d8,an) */
 617 void OP_F87000 ()
 618 {
 619   store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 620               + SEXT8 (insn & 0xff)), 2,
 621              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 622 }
 623
 624 /* movhu */
 625 void OP_FA700000 ()
 626 {
 627 }
 628
 629 /* movhu */
 630 void OP_FC700000 ()
 631 {
 632 }
 633
 634 /* movhu dm,(d8,sp) */
 635 void OP_F89300 ()
 636 {
 637   store_mem ((State.regs[REG_SP] + SEXT8 (insn & 0xff)), 2,
 638              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 639 }
 640
 641 /* movhu */
 642 void OP_FA930000 ()
 643 {
 644 }
 645
 646 /* movhu */
 647 void OP_FC930000 ()
 648 {
 649 }
 650
 651 /* movhu dm, (di,an) */
 652 void OP_F4C0 ()
 653 {
 654   store_mem ((State.regs[REG_A0 + (insn & 0x3)]
 655               + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
 656              State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
 657 }
 658
 659 /* movhu dm, (abs16) */
 660 void OP_30000 ()
 661 {
 662   store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 663 }
 664
 665 /* movhu */
 666 void OP_FC830000 ()
 667 {
 668 }
 669
 670 /* ext dn */
 671 void OP_F2D0 ()
 672 {
 673   if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
 674     State.regs[REG_MDR] = -1;
 675   else
 676     State.regs[REG_MDR] = 0;
 677 }
 678
 679 /* extb dn */
 680 void OP_10 ()
 681 {
 682   State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
 683 }
 684
 685 /* extbu dn */
 686 void OP_14 ()
 687 {
 688   State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
 689 }
 690
 691 /* exth dn */
 692 void OP_18 ()
 693 {
 694   State.regs[REG_D0 + (insn & 0x3)]
 695     = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
 696 }
 697
 698 /* exthu dn */
 699 void OP_1C ()
 700 {
 701   State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
 702 }
 703
 704 /* movm (sp), reg_list */
 705 void OP_CE00 ()
 706 {
 707   unsigned long sp = State.regs[REG_SP];
 708   unsigned long mask;
 709
 710   mask = insn & 0xff;
 711
 712   if (mask & 0x8)
 713     {
 714       sp += 4;
 715       State.regs[REG_LAR] = load_mem (sp, 4);
 716       sp += 4;
 717       State.regs[REG_LIR] = load_mem (sp, 4);
 718       sp += 4;
 719       State.regs[REG_MDR] = load_mem (sp, 4);
 720       sp += 4;
 721       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 722       sp += 4;
 723       State.regs[REG_A0] = load_mem (sp, 4);
 724       sp += 4;
 725       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 726       sp += 4;
 727       State.regs[REG_D0] = load_mem (sp, 4);
 728       sp += 4;
 729     }
 730
 731   if (mask & 0x10)
 732     {
 733       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 734       sp += 4;
 735     }
 736
 737   if (mask & 0x20)
 738     {
 739       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 740       sp += 4;
 741     }
 742
 743   if (mask & 0x40)
 744     {
 745       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 746       sp += 4;
 747     }
 748
 749   if (mask & 0x80)
 750     {
 751       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 752       sp += 4;
 753     }
 754
 755   /* And make sure to update the stack pointer.  */
 756   State.regs[REG_SP] = sp;
 757 }
 758
 759 /* movm reg_list, (sp) */
 760 void OP_CF00 ()
 761 {
 762   unsigned long sp = State.regs[REG_SP];
 763   unsigned long mask;
 764
 765   mask = insn & 0xff;
 766
 767   if (mask & 0x80)
 768     {
 769       sp -= 4;
 770       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 771     }
 772
 773   if (mask & 0x40)
 774     {
 775       sp -= 4;
 776       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 777     }
 778
 779   if (mask & 0x20)
 780     {
 781       sp -= 4;
 782       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 783     }
 784
 785   if (mask & 0x10)
 786     {
 787       sp -= 4;
 788       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 789     }
 790
 791   if (mask & 0x8)
 792     {
 793       sp -= 4;
 794       State.regs[REG_D0] = load_mem (sp, 4);
 795       sp -= 4;
 796       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 797       sp -= 4;
 798       State.regs[REG_A0] = load_mem (sp, 4);
 799       sp -= 4;
 800       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 801       sp -= 4;
 802       State.regs[REG_MDR] = load_mem (sp, 4);
 803       sp -= 4;
 804       State.regs[REG_LIR] = load_mem (sp, 4);
 805       sp -= 4;
 806       State.regs[REG_LAR] = load_mem (sp, 4);
 807       sp -= 4;
 808     }
 809
 810   /* And make sure to update the stack pointer.  */
 811   State.regs[REG_SP] = sp;
 812 }
 813
 814 /* clr dn */
 815 void OP_0 ()
 816 {
 817   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
 818
 819   PSW |= PSW_Z;
 820   PSW &= ~(PSW_V | PSW_C | PSW_N);
 821 }
 822
 823 /* add dm,dn*/
 824 void OP_E0 ()
 825 {
 826   int z, c, n, v;
 827   unsigned long reg1, reg2, value;
 828
 829   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 830   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 831   value = reg1 + reg2;
 832   State.regs[REG_D0 + (insn & 0x3)] = value;
 833
 834   z = (value == 0);
 835   n = (value & 0x80000000);
 836   c = (reg1 < reg2);
 837   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 838        && (reg2 & 0x8000000) != (value & 0x80000000));
 839
 840   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 841   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 842           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 843 }
 844
 845 /* add dm, an */
 846 void OP_F160 ()
 847 {
 848   int z, c, n, v;
 849   unsigned long reg1, reg2, value;
 850
 851   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 852   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 853   value = reg1 + reg2;
 854   State.regs[REG_A0 + (insn & 0x3)] = value;
 855
 856   z = (value == 0);
 857   n = (value & 0x80000000);
 858   c = (reg1 < reg2);
 859   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 860        && (reg2 & 0x8000000) != (value & 0x80000000));
 861
 862   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 863   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 864           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 865 }
 866
 867 /* add am, dn*/
 868 void OP_F150 ()
 869 {
 870   int z, c, n, v;
 871   unsigned long reg1, reg2, value;
 872
 873   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 874   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 875   value = reg1 + reg2;
 876   State.regs[REG_D0 + (insn & 0x3)] = value;
 877
 878   z = (value == 0);
 879   n = (value & 0x80000000);
 880   c = (reg1 < reg2);
 881   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 882        && (reg2 & 0x8000000) != (value & 0x80000000));
 883
 884   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 885   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 886           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 887 }
 888
 889 /* add am,an */
 890 void OP_F170 ()
 891 {
 892   int z, c, n, v;
 893   unsigned long reg1, reg2, value;
 894
 895   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 896   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 897   value = reg1 + reg2;
 898   State.regs[REG_A0 + (insn & 0x3)] = value;
 899
 900   z = (value == 0);
 901   n = (value & 0x80000000);
 902   c = (reg1 < reg2);
 903   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 904        && (reg2 & 0x8000000) != (value & 0x80000000));
 905
 906   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 907   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 908           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 909 }
 910
 911 /* add imm8, dn */
 912 void OP_2800 ()
 913 {
 914   int z, c, n, v;
 915   unsigned long reg1, imm, value;
 916
 917   reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
 918   imm = SEXT8 (insn & 0xff);
 919   value = reg1 + imm;
 920   State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
 921
 922   z = (value == 0);
 923   n = (value & 0x80000000);
 924   c = (reg1 < imm);
 925   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 926        && (imm & 0x8000000) != (value & 0x80000000));
 927
 928   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 929   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 930           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 931 }
 932
 933 /* add imm16, dn */
 934 void OP_FAC00000 ()
 935 {
 936   int z, c, n, v;
 937   unsigned long reg1, imm, value;
 938
 939   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 940   imm = SEXT16 (insn & 0xffff);
 941   value = reg1 + imm;
 942   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 943
 944   z = (value == 0);
 945   n = (value & 0x80000000);
 946   c = (reg1 < imm);
 947   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 948        && (imm & 0x8000000) != (value & 0x80000000));
 949
 950   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 951   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 952           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 953 }
 954
 955 /* add imm32,dn */
 956 void OP_FCC00000 ()
 957 {
 958   int z, c, n, v;
 959   unsigned long reg1, imm, value;
 960
 961   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 962   imm = ((insn & 0xffff) << 16) | extension;
 963   value = reg1 + imm;
 964   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 965
 966   z = (value == 0);
 967   n = (value & 0x80000000);
 968   c = (reg1 < imm);
 969   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 970        && (imm & 0x8000000) != (value & 0x80000000));
 971
 972   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 973   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 974           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 975 }
 976
 977 /* add imm8, an */
 978 void OP_2000 ()
 979 {
 980   int z, c, n, v;
 981   unsigned long reg1, imm, value;
 982
 983   reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
 984   imm = insn & 0xff;
 985   value = reg1 + imm;
 986   State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
 987
 988   z = (value == 0);
 989   n = (value & 0x80000000);
 990   c = (reg1 < imm);
 991   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 992        && (imm & 0x8000000) != (value & 0x80000000));
 993
 994   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 995   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 996           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 997 }
 998
 999 /* add imm16, an */
1000 void OP_FAD00000 ()
1001 {
1002   int z, c, n, v;
1003   unsigned long reg1, imm, value;
1004
1005   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
1006   imm = 0xffff;
1007   value = reg1 + imm;
1008   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
1009
1010   z = (value == 0);
1011   n = (value & 0x80000000);
1012   c = (reg1 < imm);
1013   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1014        && (imm & 0x8000000) != (value & 0x80000000));
1015
1016   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1017   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1018           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1019 }
1020
1021 /* add imm32, an */
1022 void OP_FCD00000 ()
1023 {
1024   int z, c, n, v;
1025   unsigned long reg1, imm, value;
1026
1027   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
1028   imm = ((insn & 0xffff) << 16) | extension;
1029   value = reg1 + imm;
1030   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
1031
1032   z = (value == 0);
1033   n = (value & 0x80000000);
1034   c = (reg1 < imm);
1035   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1036        && (imm & 0x8000000) != (value & 0x80000000));
1037
1038   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1039   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1040           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1041 }
1042
1043 /* add imm8, sp*/
1044 void OP_F8FE00 ()
1045 {
1046   int z, c, n, v;
1047   unsigned long reg1, imm, value;
1048
1049   reg1 = State.regs[REG_SP];
1050   imm = SEXT8 (insn & 0xff);
1051   value = reg1 + imm;
1052   State.regs[REG_SP] = value;
1053
1054   z = (value == 0);
1055   n = (value & 0x80000000);
1056   c = (reg1 < imm);
1057   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1058        && (imm & 0x8000000) != (value & 0x80000000));
1059
1060   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1061   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1062           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1063 }
1064
1065 /* add imm16,sp */
1066 void OP_FAFE0000 ()
1067 {
1068   int z, c, n, v;
1069   unsigned long reg1, imm, value;
1070
1071   reg1 = State.regs[REG_SP];
1072   imm = SEXT16 (insn & 0xffff);
1073   value = reg1 + imm;
1074   State.regs[REG_SP] = value;
1075
1076   z = (value == 0);
1077   n = (value & 0x80000000);
1078   c = (reg1 < imm);
1079   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1080        && (imm & 0x8000000) != (value & 0x80000000));
1081
1082   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1083   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1084           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1085 }
1086
1087 /* add */
1088 void OP_FCFE0000 ()
1089 {
1090   int z, c, n, v;
1091   unsigned long reg1, imm, value;
1092
1093   reg1 = State.regs[REG_SP];
1094   imm = ((insn & 0xffff) << 16) | extension;
1095   value = reg1 + imm;
1096   State.regs[REG_SP] = value;
1097
1098   z = (value == 0);
1099   n = (value & 0x80000000);
1100   c = (reg1 < imm);
1101   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1102        && (imm & 0x8000000) != (value & 0x80000000));
1103
1104   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1105   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1106           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1107 }
1108
1109 /* addc */
1110 void OP_F140 ()
1111 {
1112   int z, c, n, v;
1113   unsigned long reg1, reg2, value;
1114
1115   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1116   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1117   value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1118   State.regs[REG_D0 + (insn & 0x3)] = value;
1119
1120   z = (value == 0);
1121   n = (value & 0x80000000);
1122   c = (reg1 < reg2);
1123   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1124        && (reg2 & 0x8000000) != (value & 0x80000000));
1125
1126   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1127   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1128           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1129 }
1130
1131 /* sub dm, dn */
1132 void OP_F100 ()
1133 {
1134   int z, c, n, v;
1135   unsigned long reg1, reg2, value;
1136
1137   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1138   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1139   value = reg2 - reg1;
1140
1141   z = (value == 0);
1142   n = (value & 0x80000000);
1143   c = (reg1 < reg2);
1144   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1145        && (reg2 & 0x8000000) != (value & 0x80000000));
1146
1147   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1148   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1149           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1150   State.regs[REG_D0 + (insn & 0x3)] = value;
1151 }
1152
1153 /* sub dm, an */
1154 void OP_F120 ()
1155 {
1156   int z, c, n, v;
1157   unsigned long reg1, reg2, value;
1158
1159   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1160   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1161   value = reg2 - reg1;
1162
1163   z = (value == 0);
1164   n = (value & 0x80000000);
1165   c = (reg1 < reg2);
1166   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1167        && (reg2 & 0x8000000) != (value & 0x80000000));
1168
1169   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1170   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1171           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1172   State.regs[REG_A0 + (insn & 0x3)] = value;
1173 }
1174
1175 /* sub am, dn */
1176 void OP_F110 ()
1177 {
1178   int z, c, n, v;
1179   unsigned long reg1, reg2, value;
1180
1181   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1182   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1183   value = reg2 - reg1;
1184
1185   z = (value == 0);
1186   n = (value & 0x80000000);
1187   c = (reg1 < reg2);
1188   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1189        && (reg2 & 0x8000000) != (value & 0x80000000));
1190
1191   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1192   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1193           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1194   State.regs[REG_D0 + (insn & 0x3)] = value;
1195 }
1196
1197 /* sub am, an */
1198 void OP_F130 ()
1199 {
1200   int z, c, n, v;
1201   unsigned long reg1, reg2, value;
1202
1203   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1204   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1205   value = reg2 - reg1;
1206
1207   z = (value == 0);
1208   n = (value & 0x80000000);
1209   c = (reg1 < reg2);
1210   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1211        && (reg2 & 0x8000000) != (value & 0x80000000));
1212
1213   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1214   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1215           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1216   State.regs[REG_A0 + (insn & 0x3)] = value;
1217 }
1218
1219 /* sub */
1220 void OP_FCC40000 ()
1221 {
1222   int z, c, n, v;
1223   unsigned long reg1, imm, value;
1224
1225   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1226   imm = ((insn & 0xffff) << 16) | extension;
1227   value = reg1 - imm;
1228
1229   z = (value == 0);
1230   n = (value & 0x80000000);
1231   c = (reg1 < imm);
1232   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1233        && (imm & 0x8000000) != (value & 0x80000000));
1234
1235   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1236   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1237           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1238   State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
1239 }
1240
1241 /* sub */
1242 void OP_FCD40000 ()
1243 {
1244   int z, c, n, v;
1245   unsigned long reg1, imm, value;
1246
1247   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1248   imm = ((insn & 0xffff) << 16) | extension;
1249   value = reg1 - imm;
1250
1251   z = (value == 0);
1252   n = (value & 0x80000000);
1253   c = (reg1 < imm);
1254   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1255        && (imm & 0x8000000) != (value & 0x80000000));
1256
1257   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1258   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1259           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1260   State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
1261 }
1262
1263 /* subc */
1264 void OP_F180 ()
1265 {
1266   int z, c, n, v;
1267   unsigned long reg1, reg2, value;
1268
1269   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1270   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1271   value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1272
1273   z = (value == 0);
1274   n = (value & 0x80000000);
1275   c = (reg1 < reg2);
1276   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1277        && (reg2 & 0x8000000) != (value & 0x80000000));
1278
1279   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1280   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1281           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1282   State.regs[REG_D0 + (insn & 0x3)] = value;
1283 }
1284
1285 /* mul */
1286 void OP_F240 ()
1287 {
1288   unsigned long long temp;
1289   int n, z;
1290
1291   temp = (State.regs[REG_D0 + (insn & 0x3)]
1292           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1293   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1294   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1295   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1296   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1297   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1298   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1299 }
1300
1301 /* mulu */
1302 void OP_F250 ()
1303 {
1304   unsigned long long temp;
1305   int n, z;
1306
1307   temp = (State.regs[REG_D0 + (insn & 0x3)]
1308           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1309   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1310   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1311   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1312   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1313   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1314   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1315 }
1316
1317 /* div */
1318 void OP_F260 ()
1319 {
1320   long long temp;
1321   int n, z;
1322
1323   temp = State.regs[REG_MDR];
1324   temp <<= 32;
1325   temp |= State.regs[REG_D0 + (insn & 0x3)];
1326   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1327   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1328   temp = (State.regs[REG_D0 + (insn & 0x3)]
1329           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1330   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1331   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1332   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1333   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1334   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1335   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1336 }
1337
1338 /* divu */
1339 void OP_F270 ()
1340 {
1341   unsigned long long temp;
1342   int n, z;
1343
1344   temp = State.regs[REG_MDR];
1345   temp <<= 32;
1346   temp |= State.regs[REG_D0 + (insn & 0x3)];
1347   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1348   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1349   temp = (State.regs[REG_D0 + (insn & 0x3)]
1350           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1351   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1352   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1353   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1354   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1355   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1356   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1357 }
1358
1359 /* inc dn */
1360 void OP_40 ()
1361 {
1362   State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
1363 }
1364
1365 /* inc an */
1366 void OP_41 ()
1367 {
1368   State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1369 }
1370
1371 /* inc4 an */
1372 void OP_50 ()
1373 {
1374   State.regs[REG_A0 + (insn & 0x3)] += 4;
1375 }
1376
1377 /* cmp imm8, dn */
1378 void OP_A000 ()
1379 {
1380   int z, c, n, v;
1381   unsigned long reg1, imm, value;
1382
1383   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1384   imm = SEXT8 (insn & 0xff);
1385   value = reg1 - imm;
1386
1387   z = (value == 0);
1388   n = (value & 0x80000000);
1389   c = (reg1 < imm);
1390   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1391        && (imm & 0x8000000) != (value & 0x80000000));
1392
1393   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1394   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1395           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1396 }
1397
1398 /* cmp dm, dn */
1399 void OP_A0 ()
1400 {
1401   int z, c, n, v;
1402   unsigned long reg1, reg2, value;
1403
1404   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1405   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1406   value = reg2 - reg1;
1407
1408   z = (value == 0);
1409   n = (value & 0x80000000);
1410   c = (reg1 < reg2);
1411   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1412        && (reg2 & 0x8000000) != (value & 0x80000000));
1413
1414   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1415   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1416           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1417 }
1418
1419 /* cmp dm, an */
1420 void OP_F1A0 ()
1421 {
1422   int z, c, n, v;
1423   unsigned long reg1, reg2, value;
1424
1425   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1426   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1427   value = reg2 - reg1;
1428
1429   z = (value == 0);
1430   n = (value & 0x80000000);
1431   c = (reg1 < reg2);
1432   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1433        && (reg2 & 0x8000000) != (value & 0x80000000));
1434
1435   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1436   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1437           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1438 }
1439
1440 /* cmp am, dn */
1441 void OP_F190 ()
1442 {
1443   int z, c, n, v;
1444   unsigned long reg1, reg2, value;
1445
1446   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1447   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1448   value = reg2 - reg1;
1449
1450   z = (value == 0);
1451   n = (value & 0x80000000);
1452   c = (reg1 < reg2);
1453   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1454        && (reg2 & 0x8000000) != (value & 0x80000000));
1455
1456   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1457   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1458           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1459 }
1460
1461 /* cmp imm8, an */
1462 void OP_B000 ()
1463 {
1464   int z, c, n, v;
1465   unsigned long reg1, imm, value;
1466
1467   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1468   imm = insn & 0xff;
1469   value = reg1 - imm;
1470
1471   z = (value == 0);
1472   n = (value & 0x80000000);
1473   c = (reg1 < imm);
1474   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1475        && (imm & 0x8000000) != (value & 0x80000000));
1476
1477   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1478   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1479           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1480 }
1481
1482 /* cmp am, an */
1483 void OP_B0 ()
1484 {
1485   int z, c, n, v;
1486   unsigned long reg1, reg2, value;
1487
1488   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1489   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1490   value = reg2 - reg1;
1491
1492   z = (value == 0);
1493   n = (value & 0x80000000);
1494   c = (reg1 < reg2);
1495   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1496        && (reg2 & 0x8000000) != (value & 0x80000000));
1497
1498   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1499   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1500           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1501 }
1502
1503 /* cmp imm16, dn */
1504 void OP_FAC80000 ()
1505 {
1506   int z, c, n, v;
1507   unsigned long reg1, imm, value;
1508
1509   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1510   imm = SEXT16 (insn & 0xffff);
1511   value = reg1 - imm;
1512
1513   z = (value == 0);
1514   n = (value & 0x80000000);
1515   c = (reg1 < imm);
1516   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1517        && (imm & 0x8000000) != (value & 0x80000000));
1518
1519   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1520   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1521           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1522 }
1523
1524 /* cmp imm32, dn */
1525 void OP_FCC80000 ()
1526 {
1527   int z, c, n, v;
1528   unsigned long reg1, imm, value;
1529
1530   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1531   imm = ((insn & 0xffff) << 16) | extension;
1532   value = reg1 - imm;
1533
1534   z = (value == 0);
1535   n = (value & 0x80000000);
1536   c = (reg1 < imm);
1537   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1538        && (imm & 0x8000000) != (value & 0x80000000));
1539
1540   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1541   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1542           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1543 }
1544
1545 /* cmp imm16, an */
1546 void OP_FAD80000 ()
1547 {
1548   int z, c, n, v;
1549   unsigned long reg1, imm, value;
1550
1551   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1552   imm = insn & 0xffff;
1553   value = reg1 - imm;
1554
1555   z = (value == 0);
1556   n = (value & 0x80000000);
1557   c = (reg1 < imm);
1558   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1559        && (imm & 0x8000000) != (value & 0x80000000));
1560
1561   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1562   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1563           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1564 }
1565
1566 /* cmp imm32, an */
1567 void OP_FCD80000 ()
1568 {
1569   int z, c, n, v;
1570   unsigned long reg1, imm, value;
1571
1572   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1573   imm = ((insn & 0xffff) << 16) | extension;
1574   value = reg1 - imm;
1575
1576   z = (value == 0);
1577   n = (value & 0x80000000);
1578   c = (reg1 < imm);
1579   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1580        && (imm & 0x8000000) != (value & 0x80000000));
1581
1582   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1583   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1584           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1585 }
1586
1587 /* and dm, dn */
1588 void OP_F200 ()
1589 {
1590   int n, z;
1591
1592   State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1593   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1594   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1595   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1596   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1597 }
1598
1599 /* and imm8, dn */
1600 void OP_F8E000 ()
1601 {
1602   int n, z;
1603
1604   State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1605   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1606   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1607   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1608   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1609 }
1610
1611 /* and */
1612 void OP_FAE00000 ()
1613 {
1614 }
1615
1616 /* and */
1617 void OP_FCE00000 ()
1618 {
1619 }
1620
1621 /* and */
1622 void OP_FAFC0000 ()
1623 {
1624 }
1625
1626 /* or dm, dn*/
1627 void OP_F210 ()
1628 {
1629   int n, z;
1630
1631   State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1632   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1633   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1634   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1635   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1636 }
1637
1638 /* or imm8, dn */
1639 void OP_F8E400 ()
1640 {
1641   int n, z;
1642
1643   State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1644   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1645   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1646   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1647   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1648 }
1649
1650 /* or */
1651 void OP_FAE40000 ()
1652 {
1653 }
1654
1655 /* or */
1656 void OP_FCE40000 ()
1657 {
1658 }
1659
1660 /* or */
1661 void OP_FAFD0000 ()
1662 {
1663 }
1664
1665 /* xor dm, dn*/
1666 void OP_F220 ()
1667 {
1668   int n, z;
1669
1670   State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1671   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1672   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1673   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1674   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1675 }
1676
1677 /* xor */
1678 void OP_FAE80000 ()
1679 {
1680 }
1681
1682 /* xor */
1683 void OP_FCE80000 ()
1684 {
1685 }
1686
1687 /* not */
1688 void OP_F230 ()
1689 {
1690   int n, z;
1691
1692   State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1693   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1694   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1695   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1696   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1697 }
1698
1699 /* btst imm8, dn */
1700 void OP_F8EC00 ()
1701 {
1702   unsigned long temp;
1703   int z, n;
1704
1705   temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1706   temp &= (insn & 0xff);
1707   n = (temp & 0x80000000) != 0;
1708   z = (temp == 0);
1709   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1710   PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1711 }
1712
1713 /* btst */
1714 void OP_FAEC0000 ()
1715 {
1716 }
1717
1718 /* btst */
1719 void OP_FCEC0000 ()
1720 {
1721 }
1722
1723 /* btst */
1724 void OP_FE020000 ()
1725 {
1726 }
1727
1728 /* btst */
1729 void OP_FAF80000 ()
1730 {
1731 }
1732
1733 /* bset dm, (an) */
1734 void OP_F080 ()
1735 {
1736   unsigned long temp;
1737   int z;
1738
1739   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1740   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1741   temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1742   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1743   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1744   PSW |= (z ? PSW_Z : 0);
1745 }
1746
1747 /* bset */
1748 void OP_FE000000 ()
1749 {
1750 }
1751
1752 /* bset */
1753 void OP_FAF00000 ()
1754 {
1755 }
1756
1757 /* bclr dm, (an) */
1758 void OP_F090 ()
1759 {
1760   unsigned long temp;
1761   int z;
1762
1763   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1764   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1765   temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1766   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1767   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1768   PSW |= (z ? PSW_Z : 0);
1769 }
1770
1771 /* bclr */
1772 void OP_FE010000 ()
1773 {
1774 }
1775
1776 /* bclr */
1777 void OP_FAF40000 ()
1778 {
1779 }
1780
1781 /* asr dm, dn */
1782 void OP_F2B0 ()
1783 {
1784   long temp;
1785   int z, n, c;
1786
1787   temp = State.regs[REG_D0 + (insn & 0x3)];
1788   c = temp & 1;
1789   temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1790   State.regs[REG_D0 + (insn & 0x3)] = temp;
1791   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1792   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1793   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1794   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1795 }
1796
1797 /* asr imm8, dn */
1798 void OP_F8C800 ()
1799 {
1800   long temp;
1801   int z, n, c;
1802
1803   temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1804   c = temp & 1;
1805   temp >>= (insn & 0xff);
1806   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
1807   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1808   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1809   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1810   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1811 }
1812
1813 /* lsr dm, dn */
1814 void OP_F2A0 ()
1815 {
1816   int z, n, c;
1817
1818   c = State.regs[REG_D0 + (insn & 0x3)] & 1;
1819   State.regs[REG_D0 + (insn & 0x3)]
1820     >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1821   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1822   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1823   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1824   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1825 }
1826
1827 /* lsr dm, dn */
1828 void OP_F8C400 ()
1829 {
1830   int z, n, c;
1831
1832   c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
1833   State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>=  (insn & 0xff);
1834   z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
1835   n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x8000000) != 0;
1836   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1837   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1838 }
1839
1840 /* asl dm, dn */
1841 void OP_F290 ()
1842 {
1843   int n, z;
1844
1845   State.regs[REG_D0 + (insn & 0x3)]
1846     <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1847   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1848   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1849   PSW &= ~(PSW_Z | PSW_N);
1850   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1851 }
1852
1853 /* asl imm8, dn */
1854 void OP_F8C000 ()
1855 {
1856   int n, z;
1857
1858   State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
1859   z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1860   n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x8000000) != 0;
1861   PSW &= ~(PSW_Z | PSW_N);
1862   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1863 }
1864
1865 /* asl2 dn */
1866 void OP_54 ()
1867 {
1868   int n, z;
1869
1870   State.regs[REG_D0 + (insn & 0x3)] <<= 2;
1871   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1872   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1873   PSW &= ~(PSW_Z | PSW_N);
1874   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1875 }
1876
1877 /* ror dn */
1878 void OP_F284 ()
1879 {
1880   unsigned long value;
1881   int c,n,z;
1882
1883   value = State.regs[REG_D0 + (insn & 0x3)];
1884   if (value & 0x1)
1885     c = 1;
1886
1887   value >>= 1;
1888   value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1889   State.regs[REG_D0 + (insn & 0x3)] = value;
1890   z = (value == 0);
1891   n = (value & 0x8000000) != 0;
1892   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1893   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1894 }
1895
1896 /* rol dn */
1897 void OP_F280 ()
1898 {
1899   unsigned long value;
1900   int c,n,z;
1901
1902   value = State.regs[REG_D0 + (insn & 0x3)];
1903   if (value & 0x80000000)
1904     c = 1;
1905
1906   value <<= 1;
1907   value |= ((PSW & PSW_C) != 0);
1908   State.regs[REG_D0 + (insn & 0x3)] = value;
1909   z = (value == 0);
1910   n = (value & 0x8000000) != 0;
1911   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1912   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1913 }
1914
1915 /* beq label:8 */
1916 void OP_C800 ()
1917 {
1918   /* The dispatching code will add 2 after we return, so
1919      we subtract two here to make things right.  */
1920   if (PSW & PSW_Z)
1921     State.pc += SEXT8 (insn & 0xff) - 2;
1922 }
1923
1924 /* bne label:8 */
1925 void OP_C900 ()
1926 {
1927   /* The dispatching code will add 2 after we return, so
1928      we subtract two here to make things right.  */
1929   if (!(PSW & PSW_Z))
1930     State.pc += SEXT8 (insn & 0xff) - 2;
1931 }
1932
1933 /* bgt label:8 */
1934 void OP_C100 ()
1935 {
1936   /* The dispatching code will add 2 after we return, so
1937      we subtract two here to make things right.  */
1938   if (!((PSW & PSW_Z)
1939         || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
1940     State.pc += SEXT8 (insn & 0xff) - 2;
1941 }
1942
1943 /* bge label:8 */
1944 void OP_C200 ()
1945 {
1946   /* The dispatching code will add 2 after we return, so
1947      we subtract two here to make things right.  */
1948   if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
1949     State.pc += SEXT8 (insn & 0xff) - 2;
1950 }
1951
1952 /* ble label:8 */
1953 void OP_C300 ()
1954 {
1955   /* The dispatching code will add 2 after we return, so
1956      we subtract two here to make things right.  */
1957   if ((PSW & PSW_Z)
1958        || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
1959     State.pc += SEXT8 (insn & 0xff) - 2;
1960 }
1961
1962 /* blt label:8 */
1963 void OP_C000 ()
1964 {
1965   /* The dispatching code will add 2 after we return, so
1966      we subtract two here to make things right.  */
1967   if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
1968     State.pc += SEXT8 (insn & 0xff) - 2;
1969 }
1970
1971 /* bhi label:8 */
1972 void OP_C500 ()
1973 {
1974   /* The dispatching code will add 2 after we return, so
1975      we subtract two here to make things right.  */
1976   if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
1977     State.pc += SEXT8 (insn & 0xff) - 2;
1978 }
1979
1980 /* bcc label:8 */
1981 void OP_C600 ()
1982 {
1983   /* The dispatching code will add 2 after we return, so
1984      we subtract two here to make things right.  */
1985   if (!(PSW & PSW_C))
1986     State.pc += SEXT8 (insn & 0xff) - 2;
1987 }
1988
1989 /* bls label:8 */
1990 void OP_C700 ()
1991 {
1992   /* The dispatching code will add 2 after we return, so
1993      we subtract two here to make things right.  */
1994   if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
1995     State.pc += SEXT8 (insn & 0xff) - 2;
1996 }
1997
1998 /* bcs label:8 */
1999 void OP_C400 ()
2000 {
2001   /* The dispatching code will add 2 after we return, so
2002      we subtract two here to make things right.  */
2003   if (PSW & PSW_C)
2004     State.pc += SEXT8 (insn & 0xff) - 2;
2005 }
2006
2007 /* bvc label:8 */
2008 void OP_F8E800 ()
2009 {
2010   /* The dispatching code will add 3 after we return, so
2011      we subtract two here to make things right.  */
2012   if (!(PSW & PSW_V))
2013     State.pc += SEXT8 (insn & 0xff) - 3;
2014 }
2015
2016 /* bvs label:8 */
2017 void OP_F8E900 ()
2018 {
2019   /* The dispatching code will add 3 after we return, so
2020      we subtract two here to make things right.  */
2021   if (PSW & PSW_V)
2022     State.pc += SEXT8 (insn & 0xff) - 3;
2023 }
2024
2025 /* bnc label:8 */
2026 void OP_F8EA00 ()
2027 {
2028   /* The dispatching code will add 3 after we return, so
2029      we subtract two here to make things right.  */
2030   if (!(PSW & PSW_N))
2031     State.pc += SEXT8 (insn & 0xff) - 3;
2032 }
2033
2034 /* bns label:8 */
2035 void OP_F8EB00 ()
2036 {
2037   /* The dispatching code will add 3 after we return, so
2038      we subtract two here to make things right.  */
2039   if (PSW & PSW_N)
2040     State.pc += SEXT8 (insn & 0xff) - 3;
2041 }
2042
2043 /* bra label:8 */
2044 void OP_CA00 ()
2045 {
2046   /* The dispatching code will add 2 after we return, so
2047      we subtract two here to make things right.  */
2048   State.pc += SEXT8 (insn & 0xff) - 2;
2049 }
2050
2051 /* leq */
2052 void OP_D8 ()
2053 {
2054  abort ();
2055 }
2056
2057 /* lne */
2058 void OP_D9 ()
2059 {
2060  abort ();
2061 }
2062
2063 /* lgt */
2064 void OP_D1 ()
2065 {
2066  abort ();
2067 }
2068
2069 /* lge */
2070 void OP_D2 ()
2071 {
2072  abort ();
2073 }
2074
2075 /* lle */
2076 void OP_D3 ()
2077 {
2078  abort ();
2079 }
2080
2081 /* llt */
2082 void OP_D0 ()
2083 {
2084  abort ();
2085 }
2086
2087 /* lhi */
2088 void OP_D5 ()
2089 {
2090  abort ();
2091 }
2092
2093 /* lcc */
2094 void OP_D6 ()
2095 {
2096  abort ();
2097 }
2098
2099 /* lls */
2100 void OP_D7 ()
2101 {
2102  abort ();
2103 }
2104
2105 /* lcs */
2106 void OP_D4 ()
2107 {
2108  abort ();
2109 }
2110
2111 /* lra */
2112 void OP_DA ()
2113 {
2114  abort ();
2115 }
2116
2117 /* setlb */
2118 void OP_DB ()
2119 {
2120  abort ();
2121 }
2122
2123 /* jmp (an) */
2124 void OP_F0F4 ()
2125 {
2126   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2127 }
2128
2129 /* jmp label:16 */
2130 void OP_CC0000 ()
2131 {
2132   State.pc += SEXT16 (insn & 0xffff) - 3;
2133 }
2134
2135 /* jmp label:32 */
2136 void OP_DC000000 ()
2137 {
2138   State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2139 }
2140
2141 /* call label:16,reg_list,imm8 */
2142 void OP_CD000000 ()
2143 {
2144   unsigned int next_pc, sp, adjust;
2145   unsigned long mask;
2146
2147   sp = State.regs[REG_SP];
2148   next_pc = State.pc + 2;
2149   State.mem[sp] = next_pc & 0xff;
2150   State.mem[sp+1] = next_pc & 0xff00;
2151   State.mem[sp+2] = next_pc & 0xff0000;
2152   State.mem[sp+3] = next_pc & 0xff000000;
2153
2154   mask = insn & 0xff;
2155
2156   adjust = 0;
2157   if (mask & 0x80)
2158     {
2159       adjust -= 4;
2160       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2161     }
2162
2163   if (mask & 0x40)
2164     {
2165       adjust -= 4;
2166       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2167     }
2168
2169   if (mask & 0x20)
2170     {
2171       adjust -= 4;
2172       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2173     }
2174
2175   if (mask & 0x10)
2176     {
2177       adjust -= 4;
2178       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2179     }
2180
2181   if (mask & 0x8)
2182     {
2183       adjust -= 4;
2184       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2185       adjust -= 4;
2186       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2187       adjust -= 4;
2188       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2189       adjust -= 4;
2190       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2191       adjust -= 4;
2192       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2193       adjust -= 4;
2194       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2195       adjust -= 4;
2196       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2197       adjust -= 4;
2198     }
2199
2200   /* And make sure to update the stack pointer.  */
2201   State.regs[REG_SP] -= extension;
2202   State.regs[REG_MDR] = next_pc;
2203   State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2204 }
2205
2206 /* call label:32,reg_list,imm8*/
2207 void OP_DD000000 ()
2208 {
2209   unsigned int next_pc, sp, adjust;
2210   unsigned long mask;
2211
2212   sp = State.regs[REG_SP];
2213   next_pc = State.pc + 2;
2214   State.mem[sp] = next_pc & 0xff;
2215   State.mem[sp+1] = next_pc & 0xff00;
2216   State.mem[sp+2] = next_pc & 0xff0000;
2217   State.mem[sp+3] = next_pc & 0xff000000;
2218
2219   mask = (extension & 0xff00) >> 8;
2220
2221   adjust = 0;
2222   if (mask & 0x80)
2223     {
2224       adjust -= 4;
2225       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2226     }
2227
2228   if (mask & 0x40)
2229     {
2230       adjust -= 4;
2231       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2232     }
2233
2234   if (mask & 0x20)
2235     {
2236       adjust -= 4;
2237       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2238     }
2239
2240   if (mask & 0x10)
2241     {
2242       adjust -= 4;
2243       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2244     }
2245
2246   if (mask & 0x8)
2247     {
2248       adjust -= 4;
2249       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2250       adjust -= 4;
2251       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2252       adjust -= 4;
2253       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2254       adjust -= 4;
2255       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2256       adjust -= 4;
2257       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2258       adjust -= 4;
2259       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2260       adjust -= 4;
2261       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2262       adjust -= 4;
2263     }
2264
2265   /* And make sure to update the stack pointer.  */
2266   State.regs[REG_SP] -= (extension & 0xff);
2267   State.regs[REG_MDR] = next_pc;
2268   State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2269 }
2270
2271 /* calls (an) */
2272 void OP_F0F0 ()
2273 {
2274   unsigned int next_pc, sp;
2275
2276   sp = State.regs[REG_SP];
2277   next_pc = State.pc + 2;
2278   State.mem[sp] = next_pc & 0xff;
2279   State.mem[sp+1] = next_pc & 0xff00;
2280   State.mem[sp+2] = next_pc & 0xff0000;
2281   State.mem[sp+3] = next_pc & 0xff000000;
2282   State.regs[REG_MDR] = next_pc;
2283   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2284 }
2285
2286 /* calls label:16 */
2287 void OP_FAFF0000 ()
2288 {
2289   unsigned int next_pc, sp;
2290
2291   sp = State.regs[REG_SP];
2292   next_pc = State.pc + 4;
2293   State.mem[sp] = next_pc & 0xff;
2294   State.mem[sp+1] = next_pc & 0xff00;
2295   State.mem[sp+2] = next_pc & 0xff0000;
2296   State.mem[sp+3] = next_pc & 0xff000000;
2297   State.regs[REG_MDR] = next_pc;
2298   State.pc += SEXT16 (insn & 0xffff) - 4;
2299 }
2300
2301 /* calls label:32 */
2302 void OP_FCFF0000 ()
2303 {
2304   unsigned int next_pc, sp;
2305
2306   sp = State.regs[REG_SP];
2307   next_pc = State.pc + 6;
2308   State.mem[sp] = next_pc & 0xff;
2309   State.mem[sp+1] = next_pc & 0xff00;
2310   State.mem[sp+2] = next_pc & 0xff0000;
2311   State.mem[sp+3] = next_pc & 0xff000000;
2312   State.regs[REG_MDR] = next_pc;
2313   State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2314 }
2315
2316 /* ret */
2317 void OP_DF0000 ()
2318 {
2319   unsigned int sp;
2320   unsigned long mask;
2321
2322   State.regs[REG_SP] += insn & 0xff;
2323   State.pc = State.regs[REG_MDR] - 3;
2324   sp = State.regs[REG_SP];
2325
2326   mask = (insn & 0xff00) >> 8;
2327
2328   if (mask & 0x8)
2329     {
2330       sp += 4;
2331       State.regs[REG_LAR] = load_mem (sp, 4);
2332       sp += 4;
2333       State.regs[REG_LIR] = load_mem (sp, 4);
2334       sp += 4;
2335       State.regs[REG_MDR] = load_mem (sp, 4);
2336       sp += 4;
2337       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2338       sp += 4;
2339       State.regs[REG_A0] = load_mem (sp, 4);
2340       sp += 4;
2341       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2342       sp += 4;
2343       State.regs[REG_D0] = load_mem (sp, 4);
2344       sp += 4;
2345     }
2346
2347   if (mask & 0x10)
2348     {
2349       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2350       sp += 4;
2351     }
2352
2353   if (mask & 0x20)
2354     {
2355       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2356       sp += 4;
2357     }
2358
2359   if (mask & 0x40)
2360     {
2361       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2362       sp += 4;
2363     }
2364
2365   if (mask & 0x80)
2366     {
2367       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2368       sp += 4;
2369     }
2370 }
2371
2372 /* retf reg_list,imm8 */
2373 void OP_DE0000 ()
2374 {
2375   unsigned int sp;
2376   unsigned long mask;
2377
2378   State.regs[REG_SP] += insn & 0xff;
2379   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2380               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2381   State.pc -= 3;
2382
2383   sp = State.regs[REG_SP];
2384
2385   mask = (insn & 0xff00) >> 8;
2386
2387   if (mask & 0x8)
2388     {
2389       sp += 4;
2390       State.regs[REG_LAR] = load_mem (sp, 4);
2391       sp += 4;
2392       State.regs[REG_LIR] = load_mem (sp, 4);
2393       sp += 4;
2394       State.regs[REG_MDR] = load_mem (sp, 4);
2395       sp += 4;
2396       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2397       sp += 4;
2398       State.regs[REG_A0] = load_mem (sp, 4);
2399       sp += 4;
2400       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2401       sp += 4;
2402       State.regs[REG_D0] = load_mem (sp, 4);
2403       sp += 4;
2404     }
2405
2406   if (mask & 0x10)
2407     {
2408       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2409       sp += 4;
2410     }
2411
2412   if (mask & 0x20)
2413     {
2414       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2415       sp += 4;
2416     }
2417
2418   if (mask & 0x40)
2419     {
2420       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2421       sp += 4;
2422     }
2423
2424   if (mask & 0x80)
2425     {
2426       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2427       sp += 4;
2428     }
2429 }
2430
2431 /* rets */
2432 void OP_F0FC ()
2433 {
2434   unsigned int sp;
2435
2436   sp = State.regs[REG_SP];
2437   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2438               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2439   State.pc -= 2;
2440 }
2441
2442 /* rti */
2443 void OP_F0FD ()
2444 {
2445   abort ();
2446 }
2447
2448 /* trap */
2449 void OP_F0FE ()
2450 {
2451  abort ();
2452 }
2453
2454 /* rtm */
2455 void OP_F0FF ()
2456 {
2457  abort ();
2458 }
2459
2460 /* nop */
2461 void OP_CB ()
2462 {
2463 }
2464
2465 /* putx */
2466 void OP_F500 ()
2467 {
2468 }
2469
2470 /* getx */
2471 void OP_F6F0 ()
2472 {
2473 }
2474
2475 /* mulq */
2476 void OP_F600 ()
2477 {
2478 }
2479
2480 /* mulq */
2481 void OP_F90000 ()
2482 {
2483 }
2484
2485 /* mulq */
2486 void OP_FB000000 ()
2487 {
2488 }
2489
2490 /* mulq */
2491 void OP_FD000000 ()
2492 {
2493 }
2494
2495 /* mulqu */
2496 void OP_F610 ()
2497 {
2498 }
2499
2500 /* mulqu */
2501 void OP_F91400 ()
2502 {
2503 }
2504
2505 /* mulqu */
2506 void OP_FB140000 ()
2507 {
2508 }
2509
2510 /* mulqu */
2511 void OP_FD140000 ()
2512 {
2513 }
2514
2515 /* sat16 */
2516 void OP_F640 ()
2517 {
2518 }
2519
2520 /* sat24 */
2521 void OP_F650 ()
2522 {
2523 }
2524
2525 /* bsch */
2526 void OP_F670 ()
2527 {
2528 }