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* simops.c: "add imm,sp" does not effect the condition codes.
[binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 enum op_types {
17 OP_UNKNOWN,
18 };
19
20 #ifdef DEBUG
21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
22 static void trace_output PARAMS ((enum op_types result));
23 static int init_text_p = 0;
24 static asection *text;
25 static bfd_vma text_start;
26 static bfd_vma text_end;
27 extern bfd *exec_bfd;
28
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
31 #endif
32
33 #ifndef SIZE_OPERANDS
34 #define SIZE_OPERANDS 16
35 #endif
36
37 #ifndef SIZE_VALUES
38 #define SIZE_VALUES 11
39 #endif
40
41 #ifndef SIZE_LOCATION
42 #define SIZE_LOCATION 40
43 #endif
44
45 static void
46 trace_input (name, type, size)
47 char *name;
48 enum op_types type;
49 int size;
50 {
51 }
52
53 static void
54 trace_output (result)
55 enum op_types result;
56 {
57 }
58
59 #else
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
62 #endif
63
64 \f
65 /* mov imm8, dn */
66 void OP_8000 ()
67 {
68 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
69 }
70
71 /* mov dm, dn */
72 void OP_80 ()
73 {
74 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
75 }
76
77 /* mov dm, an */
78 void OP_F1E0 ()
79 {
80 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
81 }
82
83 /* mov am, dn */
84 void OP_F1D0 ()
85 {
86 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
87 }
88
89 /* mov imm8, an */
90 void OP_9000 ()
91 {
92 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
93 }
94
95 /* mov am, an */
96 void OP_90 ()
97 {
98 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
99 }
100
101 /* mov sp, an */
102 void OP_3C ()
103 {
104 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
105 }
106
107 /* mov am, sp */
108 void OP_F2F0 ()
109 {
110 State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
111 }
112
113 /* mov psw, dn */
114 void OP_F2E4 ()
115 {
116 State.regs[REG_D0 + (insn & 0x3)] = PSW;
117 }
118
119 /* mov dm, psw */
120 void OP_F2F3 ()
121 {
122 PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
123 }
124
125 /* mov mdr, dn */
126 void OP_F2E0 ()
127 {
128 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
129 }
130
131 /* mov dm, mdr */
132 void OP_F2F2 ()
133 {
134 State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
135 }
136
137 /* mov (am), dn */
138 void OP_70 ()
139 {
140 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
141 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
142 }
143
144 /* mov (d8,am), dn */
145 void OP_F80000 ()
146 {
147 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
148 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
149 + SEXT8 (insn & 0xff)), 4);
150 }
151
152 /* mov (d16,am), dn */
153 void OP_FA000000 ()
154 {
155 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
156 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
157 + SEXT16 (insn & 0xffff)), 4);
158 }
159
160 /* mov (d32,am), dn */
161 void OP_FC000000 ()
162 {
163 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
164 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
165 + ((insn & 0xffff) << 16) | extension), 4);
166 }
167
168 /* mov (d8,sp), dn */
169 void OP_5800 ()
170 {
171 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
172 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
173 }
174
175 /* mov (d16,sp), dn */
176 void OP_FAB40000 ()
177 {
178 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
179 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
180 }
181
182 /* mov (d32,sp), dn */
183 void OP_FCB40000 ()
184 {
185 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
186 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
187 }
188
189 /* mov (di,am), dn */
190 void OP_F300 ()
191 {
192 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
193 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
194 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
195 }
196
197 /* mov (abs16), dn */
198 void OP_300000 ()
199 {
200 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
201 }
202
203 /* mov (abs32), dn */
204 void OP_FCA40000 ()
205 {
206 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
207 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
208 }
209
210 /* mov (am), an */
211 void OP_F000 ()
212 {
213 State.regs[REG_A0 + ((insn & 0xc) >> 2)]
214 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
215 }
216
217 /* mov (d8,am), an */
218 void OP_F82000 ()
219 {
220 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
221 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
222 + SEXT8 (insn & 0xff)), 4);
223 }
224
225 /* mov (d16,am), an */
226 void OP_FA200000 ()
227 {
228 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
229 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
230 + SEXT16 (insn & 0xffff)), 4);
231 }
232
233 /* mov (d32,am), an */
234 void OP_FC200000 ()
235 {
236 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
237 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
238 + ((insn & 0xffff) << 16) + extension), 4);
239 }
240
241 /* mov (d8,sp), an */
242 void OP_5C00 ()
243 {
244 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
245 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
246 }
247
248 /* mov (d16,sp), an */
249 void OP_FAB00000 ()
250 {
251 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
252 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
253 }
254
255 /* mov (d32,sp), an */
256 void OP_FCB00000 ()
257 {
258 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
259 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
260 }
261
262 /* mov (di,am), an */
263 void OP_F380 ()
264 {
265 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
266 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
267 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
268 }
269
270 /* mov (abs16), an */
271 void OP_FAA00000 ()
272 {
273 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
274 }
275
276 /* mov (abs32), an */
277 void OP_FCA00000 ()
278 {
279 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
280 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
281 }
282
283 /* mov (d8,am), sp */
284 void OP_F8F000 ()
285 {
286 State.regs[REG_SP]
287 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
288 + SEXT8 (insn & 0xff)), 4);
289 }
290
291 /* mov dm, (an) */
292 void OP_60 ()
293 {
294 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
295 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
296 }
297
298 /* mov dm, (d8,an) */
299 void OP_F81000 ()
300 {
301 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
302 + SEXT8 (insn & 0xff)), 4,
303 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
304 }
305
306 /* mov dm (d16,an) */
307 void OP_FA100000 ()
308 {
309 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
310 + SEXT16 (insn & 0xffff)), 4,
311 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
312 }
313
314 /* mov dm (d32,an) */
315 void OP_FC100000 ()
316 {
317 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
318 + ((insn & 0xffff) << 16) + extension), 4,
319 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
320 }
321
322 /* mov dm, (d8,sp) */
323 void OP_4200 ()
324 {
325 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
326 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
327 }
328
329 /* mov dm, (d16,sp) */
330 void OP_FA910000 ()
331 {
332 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
333 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
334 }
335
336 /* mov dm, (d32,sp) */
337 void OP_FC910000 ()
338 {
339 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
340 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
341 }
342
343 /* mov dm, (di,an) */
344 void OP_F340 ()
345 {
346 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
347 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
348 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
349 }
350
351 /* mov dm, (abs16) */
352 void OP_10000 ()
353 {
354 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
355 }
356
357 /* mov dm, (abs32) */
358 void OP_FC810000 ()
359 {
360 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
361 }
362
363 /* mov am, (an) */
364 void OP_F010 ()
365 {
366 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
367 State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
368 }
369
370 /* mov am, (d8,an) */
371 void OP_F83000 ()
372 {
373 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
374 + SEXT8 (insn & 0xff)), 4,
375 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
376 }
377
378 /* mov am, (d16,an) */
379 void OP_FA300000 ()
380 {
381 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
382 + SEXT16 (insn & 0xffff)), 4,
383 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
384 }
385
386 /* mov am, (d32,an) */
387 void OP_FC300000 ()
388 {
389 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 17)]
390 + ((insn & 0xffff) << 16) + extension), 4,
391 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
392 }
393
394 /* mov am, (d8,sp) */
395 void OP_4300 ()
396 {
397 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
398 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
399 }
400
401 /* mov am, (d16,sp) */
402 void OP_FA900000 ()
403 {
404 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
405 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
406 }
407
408 /* mov am, (d32,sp) */
409 void OP_FC900000 ()
410 {
411 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
412 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
413 }
414
415 /* mov am, (di,an) */
416 void OP_F3C0 ()
417 {
418 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
419 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
420 State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
421 }
422
423 /* mov am, (abs16) */
424 void OP_FA800000 ()
425 {
426 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
427 }
428
429 /* mov am, (abs32) */
430 void OP_FC800000 ()
431 {
432 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
433 }
434
435 /* mov sp, (d8,an) */
436 void OP_F8F400 ()
437 {
438 store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
439 4, State.regs[REG_SP]);
440 }
441
442 /* mov imm16, dn */
443 void OP_2C0000 ()
444 {
445 unsigned long value;
446
447 value = SEXT16 (insn & 0xffff);
448 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
449 }
450
451 /* mov imm32,dn */
452 void OP_FCCC0000 ()
453 {
454 unsigned long value;
455
456 value = (insn & 0xffff) << 16 | extension;
457 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
458 }
459
460 /* mov imm16, an */
461 void OP_240000 ()
462 {
463 unsigned long value;
464
465 value = insn & 0xffff;
466 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
467 }
468
469 /* mov imm32, an */
470 void OP_FCDC0000 ()
471 {
472 unsigned long value;
473
474 value = (insn & 0xffff) << 16 | extension;
475 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
476 }
477
478 /* movbu (am), dn */
479 void OP_F040 ()
480 {
481 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
482 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
483 }
484
485 /* movbu (d8,am), dn */
486 void OP_F84000 ()
487 {
488 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
489 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
490 + SEXT8 (insn & 0xff)), 1);
491 }
492
493 /* movbu (d16,am), dn */
494 void OP_FA400000 ()
495 {
496 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
497 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
498 + SEXT16 (insn & 0xffff)), 1);
499 }
500
501 /* movbu (d32,am), dn */
502 void OP_FC400000 ()
503 {
504 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
505 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
506 + ((insn & 0xffff) << 16) + extension), 1);
507 }
508
509 /* movbu (d8,sp), dn */
510 void OP_F8B800 ()
511 {
512 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
513 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
514 }
515
516 /* movbu (d16,sp), dn */
517 void OP_FAB80000 ()
518 {
519 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
520 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
521 }
522
523 /* movbu (d32,sp), dn */
524 void OP_FCB80000 ()
525 {
526 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
527 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
528 }
529
530 /* movbu (di,am), dn */
531 void OP_F400 ()
532 {
533 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
534 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
535 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
536 }
537
538 /* movbu (abs16), dn */
539 void OP_340000 ()
540 {
541 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
542 }
543
544 /* movbu (abs32), dn */
545 void OP_FCA80000 ()
546 {
547 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
548 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
549 }
550
551 /* movbu dm, (an) */
552 void OP_F050 ()
553 {
554 store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
555 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
556 }
557
558 /* movbu dm, (d8,an) */
559 void OP_F85000 ()
560 {
561 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
562 + SEXT8 (insn & 0xff)), 1,
563 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
564 }
565
566 /* movbu dm, (d16,an) */
567 void OP_FA500000 ()
568 {
569 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
570 + SEXT16 (insn & 0xffff)), 1,
571 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
572 }
573
574 /* movbu dm, (d32,an) */
575 void OP_FC500000 ()
576 {
577 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
578 + ((insn & 0xffff) << 16) + extension), 1,
579 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
580 }
581
582 /* movbu dm, (d8,sp) */
583 void OP_F89200 ()
584 {
585 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
586 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
587 }
588
589 /* movbu dm, (d16,sp) */
590 void OP_FA920000 ()
591 {
592 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
593 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
594 }
595
596 /* movbu dm (d32,sp) */
597 void OP_FC920000 ()
598 {
599 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
600 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
601 }
602
603 /* movbu dm, (di,an) */
604 void OP_F440 ()
605 {
606 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
607 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
608 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
609 }
610
611 /* movbu dm, (abs16) */
612 void OP_20000 ()
613 {
614 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
615 }
616
617 /* movbu dm, (abs32) */
618 void OP_FC820000 ()
619 {
620 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
621 }
622
623 /* movhu (am), dn */
624 void OP_F060 ()
625 {
626 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
627 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
628 }
629
630 /* movhu (d8,am), dn */
631 void OP_F86000 ()
632 {
633 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
634 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
635 + SEXT8 (insn & 0xff)), 2);
636 }
637
638 /* movhu (d16,am), dn */
639 void OP_FA600000 ()
640 {
641 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
642 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
643 + SEXT16 (insn & 0xffff)), 2);
644 }
645
646 /* movhu (d32,am), dn */
647 void OP_FC600000 ()
648 {
649 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
650 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
651 + ((insn & 0xffff) << 16) + extension), 2);
652 }
653
654 /* movhu (d8,sp) dn */
655 void OP_F8BC00 ()
656 {
657 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
658 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
659 }
660
661 /* movhu (d16,sp), dn */
662 void OP_FABC0000 ()
663 {
664 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
665 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
666 }
667
668 /* movhu (d32,sp), dn */
669 void OP_FCBC0000 ()
670 {
671 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
672 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
673 }
674
675 /* movhu (di,am), dn */
676 void OP_F480 ()
677 {
678 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
679 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
680 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
681 }
682
683 /* movhu (abs16), dn */
684 void OP_380000 ()
685 {
686 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
687 }
688
689 /* movhu (abs32), dn */
690 void OP_FCAC0000 ()
691 {
692 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
693 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
694 }
695
696 /* movhu dm, (an) */
697 void OP_F070 ()
698 {
699 store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
700 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
701 }
702
703 /* movhu dm, (d8,an) */
704 void OP_F87000 ()
705 {
706 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
707 + SEXT8 (insn & 0xff)), 2,
708 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
709 }
710
711 /* movhu dm, (d16,an) */
712 void OP_FA700000 ()
713 {
714 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
715 + SEXT16 (insn & 0xffff)), 2,
716 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
717 }
718
719 /* movhu dm, (d32,an) */
720 void OP_FC700000 ()
721 {
722 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
723 + ((insn & 0xffff) << 16) + extension), 2,
724 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
725 }
726
727 /* movhu dm,(d8,sp) */
728 void OP_F89300 ()
729 {
730 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
731 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
732 }
733
734 /* movhu dm,(d16,sp) */
735 void OP_FA930000 ()
736 {
737 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
738 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
739 }
740
741 /* movhu dm,(d32,sp) */
742 void OP_FC930000 ()
743 {
744 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
745 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
746 }
747
748 /* movhu dm, (di,an) */
749 void OP_F4C0 ()
750 {
751 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
752 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
753 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
754 }
755
756 /* movhu dm, (abs16) */
757 void OP_30000 ()
758 {
759 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
760 }
761
762 /* movhu dm, (abs32) */
763 void OP_FC830000 ()
764 {
765 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
766 }
767
768 /* ext dn */
769 void OP_F2D0 ()
770 {
771 if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
772 State.regs[REG_MDR] = -1;
773 else
774 State.regs[REG_MDR] = 0;
775 }
776
777 /* extb dn */
778 void OP_10 ()
779 {
780 State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
781 }
782
783 /* extbu dn */
784 void OP_14 ()
785 {
786 State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
787 }
788
789 /* exth dn */
790 void OP_18 ()
791 {
792 State.regs[REG_D0 + (insn & 0x3)]
793 = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
794 }
795
796 /* exthu dn */
797 void OP_1C ()
798 {
799 State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
800 }
801
802 /* movm (sp), reg_list */
803 void OP_CE00 ()
804 {
805 unsigned long sp = State.regs[REG_SP];
806 unsigned long mask;
807
808 mask = insn & 0xff;
809
810 if (mask & 0x8)
811 {
812 sp += 4;
813 State.regs[REG_LAR] = load_mem (sp, 4);
814 sp += 4;
815 State.regs[REG_LIR] = load_mem (sp, 4);
816 sp += 4;
817 State.regs[REG_MDR] = load_mem (sp, 4);
818 sp += 4;
819 State.regs[REG_A0 + 1] = load_mem (sp, 4);
820 sp += 4;
821 State.regs[REG_A0] = load_mem (sp, 4);
822 sp += 4;
823 State.regs[REG_D0 + 1] = load_mem (sp, 4);
824 sp += 4;
825 State.regs[REG_D0] = load_mem (sp, 4);
826 sp += 4;
827 }
828
829 if (mask & 0x10)
830 {
831 State.regs[REG_A0 + 3] = load_mem (sp, 4);
832 sp += 4;
833 }
834
835 if (mask & 0x20)
836 {
837 State.regs[REG_A0 + 2] = load_mem (sp, 4);
838 sp += 4;
839 }
840
841 if (mask & 0x40)
842 {
843 State.regs[REG_D0 + 3] = load_mem (sp, 4);
844 sp += 4;
845 }
846
847 if (mask & 0x80)
848 {
849 State.regs[REG_D0 + 2] = load_mem (sp, 4);
850 sp += 4;
851 }
852
853 /* And make sure to update the stack pointer. */
854 State.regs[REG_SP] = sp;
855 }
856
857 /* movm reg_list, (sp) */
858 void OP_CF00 ()
859 {
860 unsigned long sp = State.regs[REG_SP];
861 unsigned long mask;
862
863 mask = insn & 0xff;
864
865 if (mask & 0x80)
866 {
867 sp -= 4;
868 store_mem (sp, 4, State.regs[REG_D0 + 2]);
869 }
870
871 if (mask & 0x40)
872 {
873 sp -= 4;
874 store_mem (sp, 4, State.regs[REG_D0 + 3]);
875 }
876
877 if (mask & 0x20)
878 {
879 sp -= 4;
880 store_mem (sp, 4, State.regs[REG_A0 + 2]);
881 }
882
883 if (mask & 0x10)
884 {
885 sp -= 4;
886 store_mem (sp, 4, State.regs[REG_A0 + 3]);
887 }
888
889 if (mask & 0x8)
890 {
891 sp -= 4;
892 store_mem (sp, 4, State.regs[REG_D0]);
893 sp -= 4;
894 store_mem (sp, 4, State.regs[REG_D0 + 1]);
895 sp -= 4;
896 store_mem (sp, 4, State.regs[REG_A0]);
897 sp -= 4;
898 store_mem (sp, 4, State.regs[REG_A0 + 1]);
899 sp -= 4;
900 store_mem (sp, 4, State.regs[REG_MDR]);
901 sp -= 4;
902 store_mem (sp, 4, State.regs[REG_LIR]);
903 sp -= 4;
904 store_mem (sp, 4, State.regs[REG_LAR]);
905 sp -= 4;
906 }
907
908 /* And make sure to update the stack pointer. */
909 State.regs[REG_SP] = sp;
910 }
911
912 /* clr dn */
913 void OP_0 ()
914 {
915 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
916
917 PSW |= PSW_Z;
918 PSW &= ~(PSW_V | PSW_C | PSW_N);
919 }
920
921 /* add dm,dn */
922 void OP_E0 ()
923 {
924 int z, c, n, v;
925 unsigned long reg1, reg2, value;
926
927 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
928 reg2 = State.regs[REG_D0 + (insn & 0x3)];
929 value = reg1 + reg2;
930 State.regs[REG_D0 + (insn & 0x3)] = value;
931
932 z = (value == 0);
933 n = (value & 0x80000000);
934 c = (reg1 < reg2);
935 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
936 && (reg2 & 0x80000000) != (value & 0x80000000));
937
938 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
939 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
940 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
941 }
942
943 /* add dm, an */
944 void OP_F160 ()
945 {
946 int z, c, n, v;
947 unsigned long reg1, reg2, value;
948
949 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
950 reg2 = State.regs[REG_A0 + (insn & 0x3)];
951 value = reg1 + reg2;
952 State.regs[REG_A0 + (insn & 0x3)] = value;
953
954 z = (value == 0);
955 n = (value & 0x80000000);
956 c = (reg1 < reg2);
957 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
958 && (reg2 & 0x80000000) != (value & 0x80000000));
959
960 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
961 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
962 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
963 }
964
965 /* add am, dn */
966 void OP_F150 ()
967 {
968 int z, c, n, v;
969 unsigned long reg1, reg2, value;
970
971 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
972 reg2 = State.regs[REG_D0 + (insn & 0x3)];
973 value = reg1 + reg2;
974 State.regs[REG_D0 + (insn & 0x3)] = value;
975
976 z = (value == 0);
977 n = (value & 0x80000000);
978 c = (reg1 < reg2);
979 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
980 && (reg2 & 0x80000000) != (value & 0x80000000));
981
982 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
983 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
984 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
985 }
986
987 /* add am,an */
988 void OP_F170 ()
989 {
990 int z, c, n, v;
991 unsigned long reg1, reg2, value;
992
993 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
994 reg2 = State.regs[REG_A0 + (insn & 0x3)];
995 value = reg1 + reg2;
996 State.regs[REG_A0 + (insn & 0x3)] = value;
997
998 z = (value == 0);
999 n = (value & 0x80000000);
1000 c = (reg1 < reg2);
1001 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1002 && (reg2 & 0x80000000) != (value & 0x80000000));
1003
1004 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1007 }
1008
1009 /* add imm8, dn */
1010 void OP_2800 ()
1011 {
1012 int z, c, n, v;
1013 unsigned long reg1, imm, value;
1014
1015 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1016 imm = SEXT8 (insn & 0xff);
1017 value = reg1 + imm;
1018 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
1019
1020 z = (value == 0);
1021 n = (value & 0x80000000);
1022 c = (reg1 < imm);
1023 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1024 && (reg1 & 0x80000000) != (value & 0x80000000));
1025
1026 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1027 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1028 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1029 }
1030
1031 /* add imm16, dn */
1032 void OP_FAC00000 ()
1033 {
1034 int z, c, n, v;
1035 unsigned long reg1, imm, value;
1036
1037 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1038 imm = SEXT16 (insn & 0xffff);
1039 value = reg1 + imm;
1040 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1041
1042 z = (value == 0);
1043 n = (value & 0x80000000);
1044 c = (reg1 < imm);
1045 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1046 && (reg1 & 0x80000000) != (value & 0x80000000));
1047
1048 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1049 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1050 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1051 }
1052
1053 /* add imm32,dn */
1054 void OP_FCC00000 ()
1055 {
1056 int z, c, n, v;
1057 unsigned long reg1, imm, value;
1058
1059 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1060 imm = ((insn & 0xffff) << 16) | extension;
1061 value = reg1 + imm;
1062 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1063
1064 z = (value == 0);
1065 n = (value & 0x80000000);
1066 c = (reg1 < imm);
1067 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1068 && (reg1 & 0x80000000) != (value & 0x80000000));
1069
1070 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1071 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1072 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1073 }
1074
1075 /* add imm8, an */
1076 void OP_2000 ()
1077 {
1078 int z, c, n, v;
1079 unsigned long reg1, imm, value;
1080
1081 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1082 imm = SEXT8 (insn & 0xff);
1083 value = reg1 + imm;
1084 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
1085
1086 z = (value == 0);
1087 n = (value & 0x80000000);
1088 c = (reg1 < imm);
1089 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1090 && (reg1 & 0x80000000) != (value & 0x80000000));
1091
1092 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1093 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1094 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1095 }
1096
1097 /* add imm16, an */
1098 void OP_FAD00000 ()
1099 {
1100 int z, c, n, v;
1101 unsigned long reg1, imm, value;
1102
1103 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1104 imm = SEXT16 (insn & 0xffff);
1105 value = reg1 + imm;
1106 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1107
1108 z = (value == 0);
1109 n = (value & 0x80000000);
1110 c = (reg1 < imm);
1111 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1112 && (reg1 & 0x80000000) != (value & 0x80000000));
1113
1114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1115 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1116 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1117 }
1118
1119 /* add imm32, an */
1120 void OP_FCD00000 ()
1121 {
1122 int z, c, n, v;
1123 unsigned long reg1, imm, value;
1124
1125 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1126 imm = ((insn & 0xffff) << 16) | extension;
1127 value = reg1 + imm;
1128 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1129
1130 z = (value == 0);
1131 n = (value & 0x80000000);
1132 c = (reg1 < imm);
1133 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1134 && (reg1 & 0x80000000) != (value & 0x80000000));
1135
1136 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1137 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1138 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1139 }
1140
1141 /* add imm8, sp */
1142 void OP_F8FE00 ()
1143 {
1144 int z, c, n, v;
1145 unsigned long reg1, imm, value;
1146
1147 reg1 = State.regs[REG_SP];
1148 imm = SEXT8 (insn & 0xff);
1149 value = reg1 + imm;
1150 State.regs[REG_SP] = value;
1151 }
1152
1153 /* add imm16,sp */
1154 void OP_FAFE0000 ()
1155 {
1156 int z, c, n, v;
1157 unsigned long reg1, imm, value;
1158
1159 reg1 = State.regs[REG_SP];
1160 imm = SEXT16 (insn & 0xffff);
1161 value = reg1 + imm;
1162 State.regs[REG_SP] = value;
1163 }
1164
1165 /* add imm32, sp */
1166 void OP_FCFE0000 ()
1167 {
1168 int z, c, n, v;
1169 unsigned long reg1, imm, value;
1170
1171 reg1 = State.regs[REG_SP];
1172 imm = ((insn & 0xffff) << 16) | extension;
1173 value = reg1 + imm;
1174 State.regs[REG_SP] = value;
1175 }
1176
1177 /* addc dm,dn */
1178 void OP_F140 ()
1179 {
1180 int z, c, n, v;
1181 unsigned long reg1, reg2, value;
1182
1183 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1184 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1185 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1186 State.regs[REG_D0 + (insn & 0x3)] = value;
1187
1188 z = (value == 0);
1189 n = (value & 0x80000000);
1190 c = (reg1 < reg2);
1191 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1192 && (reg2 & 0x80000000) != (value & 0x80000000));
1193
1194 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1195 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1196 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1197 }
1198
1199 /* sub dm, dn */
1200 void OP_F100 ()
1201 {
1202 int z, c, n, v;
1203 unsigned long reg1, reg2, value;
1204
1205 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1206 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1207 value = reg2 - reg1;
1208
1209 z = (value == 0);
1210 n = (value & 0x80000000);
1211 c = (reg1 > reg2);
1212 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1213 && (reg2 & 0x80000000) != (value & 0x80000000));
1214
1215 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1216 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1217 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1218 State.regs[REG_D0 + (insn & 0x3)] = value;
1219 }
1220
1221 /* sub dm, an */
1222 void OP_F120 ()
1223 {
1224 int z, c, n, v;
1225 unsigned long reg1, reg2, value;
1226
1227 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1228 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1229 value = reg2 - reg1;
1230
1231 z = (value == 0);
1232 n = (value & 0x80000000);
1233 c = (reg1 > reg2);
1234 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1235 && (reg2 & 0x80000000) != (value & 0x80000000));
1236
1237 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1238 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1239 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1240 State.regs[REG_A0 + (insn & 0x3)] = value;
1241 }
1242
1243 /* sub am, dn */
1244 void OP_F110 ()
1245 {
1246 int z, c, n, v;
1247 unsigned long reg1, reg2, value;
1248
1249 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1250 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1251 value = reg2 - reg1;
1252
1253 z = (value == 0);
1254 n = (value & 0x80000000);
1255 c = (reg1 > reg2);
1256 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1257 && (reg2 & 0x80000000) != (value & 0x80000000));
1258
1259 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1260 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1261 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1262 State.regs[REG_D0 + (insn & 0x3)] = value;
1263 }
1264
1265 /* sub am, an */
1266 void OP_F130 ()
1267 {
1268 int z, c, n, v;
1269 unsigned long reg1, reg2, value;
1270
1271 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1272 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1273 value = reg2 - reg1;
1274
1275 z = (value == 0);
1276 n = (value & 0x80000000);
1277 c = (reg1 > reg2);
1278 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1279 && (reg2 & 0x80000000) != (value & 0x80000000));
1280
1281 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1282 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1283 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1284 State.regs[REG_A0 + (insn & 0x3)] = value;
1285 }
1286
1287 /* sub imm32, dn */
1288 void OP_FCC40000 ()
1289 {
1290 int z, c, n, v;
1291 unsigned long reg1, imm, value;
1292
1293 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1294 imm = ((insn & 0xffff) << 16) | extension;
1295 value = reg1 - imm;
1296
1297 z = (value == 0);
1298 n = (value & 0x80000000);
1299 c = (reg1 < imm);
1300 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1301 && (reg1 & 0x80000000) != (value & 0x80000000));
1302
1303 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1304 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1305 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1306 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1307 }
1308
1309 /* sub imm32, an */
1310 void OP_FCD40000 ()
1311 {
1312 int z, c, n, v;
1313 unsigned long reg1, imm, value;
1314
1315 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1316 imm = ((insn & 0xffff) << 16) | extension;
1317 value = reg1 - imm;
1318
1319 z = (value == 0);
1320 n = (value & 0x80000000);
1321 c = (reg1 < imm);
1322 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1323 && (reg1 & 0x80000000) != (value & 0x80000000));
1324
1325 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1326 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1327 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1328 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1329 }
1330
1331 /* subc dm, dn */
1332 void OP_F180 ()
1333 {
1334 int z, c, n, v;
1335 unsigned long reg1, reg2, value;
1336
1337 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1338 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1339 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1340
1341 z = (value == 0);
1342 n = (value & 0x80000000);
1343 c = (reg1 > reg2);
1344 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1345 && (reg2 & 0x80000000) != (value & 0x80000000));
1346
1347 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1348 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1349 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1350 State.regs[REG_D0 + (insn & 0x3)] = value;
1351 }
1352
1353 /* mul dm, dn */
1354 void OP_F240 ()
1355 {
1356 unsigned long long temp;
1357 int n, z;
1358
1359 temp = (State.regs[REG_D0 + (insn & 0x3)]
1360 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1361 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1362 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1363 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1364 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1365 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1366 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1367 }
1368
1369 /* mulu dm, dn */
1370 void OP_F250 ()
1371 {
1372 unsigned long long temp;
1373 int n, z;
1374
1375 temp = (State.regs[REG_D0 + (insn & 0x3)]
1376 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1377 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1378 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1379 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1380 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1381 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1382 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1383 }
1384
1385 /* div dm, dn */
1386 void OP_F260 ()
1387 {
1388 long long temp;
1389 int n, z;
1390
1391 temp = State.regs[REG_MDR];
1392 temp <<= 32;
1393 temp |= State.regs[REG_D0 + (insn & 0x3)];
1394 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1395 temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1396 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1397 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1398 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1399 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1400 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1401 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1402 }
1403
1404 /* divu dm, dn */
1405 void OP_F270 ()
1406 {
1407 unsigned long long temp;
1408 int n, z;
1409
1410 temp = State.regs[REG_MDR];
1411 temp <<= 32;
1412 temp |= State.regs[REG_D0 + (insn & 0x3)];
1413 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1414 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1415 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1416 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1417 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1418 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1419 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1420 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1421 }
1422
1423 /* inc dn */
1424 void OP_40 ()
1425 {
1426 int z,n,c,v;
1427 unsigned int value;
1428
1429 value = State.regs[REG_D0 + ((insn & 0xc) >> 2)] + 1;
1430 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
1431
1432 z = (value == 0);
1433 n = (value & 0x80000000);
1434 c = (reg1 < reg2);
1435 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1436 && (reg2 & 0x80000000) != (value & 0x80000000));
1437
1438 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1439 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1440 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1441 }
1442
1443 /* inc an */
1444 void OP_41 ()
1445 {
1446 State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1447 }
1448
1449 /* inc4 an */
1450 void OP_50 ()
1451 {
1452 State.regs[REG_A0 + (insn & 0x3)] += 4;
1453 }
1454
1455 /* cmp imm8, dn */
1456 void OP_A000 ()
1457 {
1458 int z, c, n, v;
1459 unsigned long reg1, imm, value;
1460
1461 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1462 imm = SEXT8 (insn & 0xff);
1463 value = reg1 - imm;
1464
1465 z = (value == 0);
1466 n = (value & 0x80000000);
1467 c = (reg1 < imm);
1468 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1469 && (reg1 & 0x80000000) != (value & 0x80000000));
1470
1471 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1472 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1473 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1474 }
1475
1476 /* cmp dm, dn */
1477 void OP_A0 ()
1478 {
1479 int z, c, n, v;
1480 unsigned long reg1, reg2, value;
1481
1482 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1483 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1484 value = reg2 - reg1;
1485
1486 z = (value == 0);
1487 n = (value & 0x80000000);
1488 c = (reg1 > reg2);
1489 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1490 && (reg2 & 0x80000000) != (value & 0x80000000));
1491
1492 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1493 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1494 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1495 }
1496
1497 /* cmp dm, an */
1498 void OP_F1A0 ()
1499 {
1500 int z, c, n, v;
1501 unsigned long reg1, reg2, value;
1502
1503 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1504 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1505 value = reg2 - reg1;
1506
1507 z = (value == 0);
1508 n = (value & 0x80000000);
1509 c = (reg1 > reg2);
1510 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1511 && (reg2 & 0x80000000) != (value & 0x80000000));
1512
1513 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1514 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1515 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1516 }
1517
1518 /* cmp am, dn */
1519 void OP_F190 ()
1520 {
1521 int z, c, n, v;
1522 unsigned long reg1, reg2, value;
1523
1524 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1525 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1526 value = reg2 - reg1;
1527
1528 z = (value == 0);
1529 n = (value & 0x80000000);
1530 c = (reg1 > reg2);
1531 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1532 && (reg2 & 0x80000000) != (value & 0x80000000));
1533
1534 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1535 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1536 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1537 }
1538
1539 /* cmp imm8, an */
1540 void OP_B000 ()
1541 {
1542 int z, c, n, v;
1543 unsigned long reg1, imm, value;
1544
1545 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1546 imm = insn & 0xff;
1547 value = reg1 - imm;
1548
1549 z = (value == 0);
1550 n = (value & 0x80000000);
1551 c = (reg1 < imm);
1552 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1553 && (reg1 & 0x80000000) != (value & 0x80000000));
1554
1555 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1556 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1557 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1558 }
1559
1560 /* cmp am, an */
1561 void OP_B0 ()
1562 {
1563 int z, c, n, v;
1564 unsigned long reg1, reg2, value;
1565
1566 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1567 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1568 value = reg2 - reg1;
1569
1570 z = (value == 0);
1571 n = (value & 0x80000000);
1572 c = (reg1 > reg2);
1573 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1574 && (reg2 & 0x80000000) != (value & 0x80000000));
1575
1576 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1577 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1578 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1579 }
1580
1581 /* cmp imm16, dn */
1582 void OP_FAC80000 ()
1583 {
1584 int z, c, n, v;
1585 unsigned long reg1, imm, value;
1586
1587 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1588 imm = SEXT16 (insn & 0xffff);
1589 value = reg1 - imm;
1590
1591 z = (value == 0);
1592 n = (value & 0x80000000);
1593 c = (reg1 < imm);
1594 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1595 && (reg1 & 0x80000000) != (value & 0x80000000));
1596
1597 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1598 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1599 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1600 }
1601
1602 /* cmp imm32, dn */
1603 void OP_FCC80000 ()
1604 {
1605 int z, c, n, v;
1606 unsigned long reg1, imm, value;
1607
1608 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1609 imm = ((insn & 0xffff) << 16) | extension;
1610 value = reg1 - imm;
1611
1612 z = (value == 0);
1613 n = (value & 0x80000000);
1614 c = (reg1 < imm);
1615 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1616 && (reg1 & 0x80000000) != (value & 0x80000000));
1617
1618 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1619 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1620 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1621 }
1622
1623 /* cmp imm16, an */
1624 void OP_FAD80000 ()
1625 {
1626 int z, c, n, v;
1627 unsigned long reg1, imm, value;
1628
1629 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1630 imm = insn & 0xffff;
1631 value = reg1 - imm;
1632
1633 z = (value == 0);
1634 n = (value & 0x80000000);
1635 c = (reg1 < imm);
1636 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1637 && (reg1 & 0x80000000) != (value & 0x80000000));
1638
1639 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1640 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1641 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1642 }
1643
1644 /* cmp imm32, an */
1645 void OP_FCD80000 ()
1646 {
1647 int z, c, n, v;
1648 unsigned long reg1, imm, value;
1649
1650 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1651 imm = ((insn & 0xffff) << 16) | extension;
1652 value = reg1 - imm;
1653
1654 z = (value == 0);
1655 n = (value & 0x80000000);
1656 c = (reg1 < imm);
1657 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1658 && (reg1 & 0x80000000) != (value & 0x80000000));
1659
1660 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1661 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1662 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1663 }
1664
1665 /* and dm, dn */
1666 void OP_F200 ()
1667 {
1668 int n, z;
1669
1670 State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1671 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1672 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1673 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1674 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1675 }
1676
1677 /* and imm8, dn */
1678 void OP_F8E000 ()
1679 {
1680 int n, z;
1681
1682 State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1683 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1684 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1685 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1686 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1687 }
1688
1689 /* and imm16, dn */
1690 void OP_FAE00000 ()
1691 {
1692 int n, z;
1693
1694 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1695 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1696 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1697 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1698 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1699 }
1700
1701 /* and imm32, dn */
1702 void OP_FCE00000 ()
1703 {
1704 int n, z;
1705
1706 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1707 &= ((insn & 0xffff) << 16 | extension);
1708 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1709 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1710 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1711 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1712 }
1713
1714 /* and imm16, psw */
1715 void OP_FAFC0000 ()
1716 {
1717 PSW &= (insn & 0xffff);
1718 }
1719
1720 /* or dm, dn*/
1721 void OP_F210 ()
1722 {
1723 int n, z;
1724
1725 State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1726 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1727 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1728 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1729 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1730 }
1731
1732 /* or imm8, dn */
1733 void OP_F8E400 ()
1734 {
1735 int n, z;
1736
1737 State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1738 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1739 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1740 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1741 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1742 }
1743
1744 /* or imm16, dn*/
1745 void OP_FAE40000 ()
1746 {
1747 int n, z;
1748
1749 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1750 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1751 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1752 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1753 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1754 }
1755
1756 /* or imm32, dn */
1757 void OP_FCE40000 ()
1758 {
1759 int n, z;
1760
1761 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1762 |= ((insn & 0xffff) << 16 | extension);
1763 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1764 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1765 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1766 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1767 }
1768
1769 /* or imm16,psw */
1770 void OP_FAFD0000 ()
1771 {
1772 PSW |= (insn & 0xffff);
1773 }
1774
1775 /* xor dm, dn*/
1776 void OP_F220 ()
1777 {
1778 int n, z;
1779
1780 State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1781 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1782 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1783 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1784 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1785 }
1786
1787 /* xor imm16, dn */
1788 void OP_FAE80000 ()
1789 {
1790 int n, z;
1791
1792 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1793 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1794 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1795 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1796 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1797 }
1798
1799 /* xor imm32, dn */
1800 void OP_FCE80000 ()
1801 {
1802 int n, z;
1803
1804 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1805 ^= ((insn & 0xffff) << 16 | extension);
1806 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1807 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1808 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1809 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1810 }
1811
1812 /* not dn */
1813 void OP_F230 ()
1814 {
1815 int n, z;
1816
1817 State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1818 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1819 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1820 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1821 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1822 }
1823
1824 /* btst imm8, dn */
1825 void OP_F8EC00 ()
1826 {
1827 unsigned long temp;
1828 int z, n;
1829
1830 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1831 temp &= (insn & 0xff);
1832 n = (temp & 0x80000000) != 0;
1833 z = (temp == 0);
1834 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1835 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1836 }
1837
1838 /* btst imm16, dn */
1839 void OP_FAEC0000 ()
1840 {
1841 unsigned long temp;
1842 int z, n;
1843
1844 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1845 temp &= (insn & 0xffff);
1846 n = (temp & 0x80000000) != 0;
1847 z = (temp == 0);
1848 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1849 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1850 }
1851
1852 /* btst imm32, dn */
1853 void OP_FCEC0000 ()
1854 {
1855 unsigned long temp;
1856 int z, n;
1857
1858 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1859 temp &= ((insn & 0xffff) << 16 | extension);
1860 n = (temp & 0x80000000) != 0;
1861 z = (temp == 0);
1862 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1863 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1864 }
1865
1866 /* btst imm8,(abs32) */
1867 void OP_FE020000 ()
1868 {
1869 unsigned long temp;
1870 int n, z;
1871
1872 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1873 temp &= (extension & 0xff);
1874 n = (temp & 0x80000000) != 0;
1875 z = (temp == 0);
1876 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1877 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1878 }
1879
1880 /* btst imm8,(d8,an) */
1881 void OP_FAF80000 ()
1882 {
1883 unsigned long temp;
1884 int n, z;
1885
1886 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1887 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1888 temp &= (insn & 0xff);
1889 n = (temp & 0x80000000) != 0;
1890 z = (temp == 0);
1891 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1892 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1893 }
1894
1895 /* bset dm, (an) */
1896 void OP_F080 ()
1897 {
1898 unsigned long temp;
1899 int z;
1900
1901 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1902 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1903 temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1904 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1905 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1906 PSW |= (z ? PSW_Z : 0);
1907 }
1908
1909 /* bset imm8, (abs32) */
1910 void OP_FE000000 ()
1911 {
1912 unsigned long temp;
1913 int z;
1914
1915 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
1916 z = (temp & (extension & 0xff)) == 0;
1917 temp |= (extension & 0xff);
1918 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
1919 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1920 PSW |= (z ? PSW_Z : 0);
1921 }
1922
1923 /* bset imm8,(d8,an) */
1924 void OP_FAF00000 ()
1925 {
1926 unsigned long temp;
1927 int z;
1928
1929 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1930 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1931 z = (temp & (insn & 0xff)) == 0;
1932 temp |= (insn & 0xff);
1933 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1934 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1935 PSW |= (z ? PSW_Z : 0);
1936 }
1937
1938 /* bclr dm, (an) */
1939 void OP_F090 ()
1940 {
1941 unsigned long temp;
1942 int z;
1943
1944 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1945 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1946 temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1947 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1948 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1949 PSW |= (z ? PSW_Z : 0);
1950 }
1951
1952 /* bclr imm8, (abs32) */
1953 void OP_FE010000 ()
1954 {
1955 unsigned long temp;
1956 int z;
1957
1958 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
1959 z = (temp & (extension & 0xff)) == 0;
1960 temp = ~temp & (extension & 0xff);
1961 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
1962 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1963 PSW |= (z ? PSW_Z : 0);
1964 }
1965
1966 /* bclr imm8,(d8,an) */
1967 void OP_FAF40000 ()
1968 {
1969 unsigned long temp;
1970 int z;
1971
1972 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
1973 + SEXT8 ((insn & 0xff00) >> 8)), 1);
1974 z = (temp & (insn & 0xff)) == 0;
1975 temp = ~temp & (insn & 0xff);
1976 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
1977 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1978 PSW |= (z ? PSW_Z : 0);
1979 }
1980
1981 /* asr dm, dn */
1982 void OP_F2B0 ()
1983 {
1984 long temp;
1985 int z, n, c;
1986
1987 temp = State.regs[REG_D0 + (insn & 0x3)];
1988 c = temp & 1;
1989 temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1990 State.regs[REG_D0 + (insn & 0x3)] = temp;
1991 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1992 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1993 PSW &= ~(PSW_Z | PSW_N | PSW_C);
1994 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1995 }
1996
1997 /* asr imm8, dn */
1998 void OP_F8C800 ()
1999 {
2000 long temp;
2001 int z, n, c;
2002
2003 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
2004 c = temp & 1;
2005 temp >>= (insn & 0xff);
2006 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
2007 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2008 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2009 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2010 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2011 }
2012
2013 /* lsr dm, dn */
2014 void OP_F2A0 ()
2015 {
2016 int z, n, c;
2017
2018 c = State.regs[REG_D0 + (insn & 0x3)] & 1;
2019 State.regs[REG_D0 + (insn & 0x3)]
2020 >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2021 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2022 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2023 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2024 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2025 }
2026
2027 /* lsr dm, dn */
2028 void OP_F8C400 ()
2029 {
2030 int z, n, c;
2031
2032 c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
2033 State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
2034 z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
2035 n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x80000000) != 0;
2036 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2037 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2038 }
2039
2040 /* asl dm, dn */
2041 void OP_F290 ()
2042 {
2043 int n, z;
2044
2045 State.regs[REG_D0 + (insn & 0x3)]
2046 <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2047 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2048 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2049 PSW &= ~(PSW_Z | PSW_N);
2050 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2051 }
2052
2053 /* asl imm8, dn */
2054 void OP_F8C000 ()
2055 {
2056 int n, z;
2057
2058 State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
2059 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2060 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2061 PSW &= ~(PSW_Z | PSW_N);
2062 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2063 }
2064
2065 /* asl2 dn */
2066 void OP_54 ()
2067 {
2068 int n, z;
2069
2070 State.regs[REG_D0 + (insn & 0x3)] <<= 2;
2071 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2072 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2073 PSW &= ~(PSW_Z | PSW_N);
2074 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2075 }
2076
2077 /* ror dn */
2078 void OP_F284 ()
2079 {
2080 unsigned long value;
2081 int c,n,z;
2082
2083 value = State.regs[REG_D0 + (insn & 0x3)];
2084 if (value & 0x1)
2085 c = 1;
2086
2087 value >>= 1;
2088 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2089 State.regs[REG_D0 + (insn & 0x3)] = value;
2090 z = (value == 0);
2091 n = (value & 0x80000000) != 0;
2092 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2093 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2094 }
2095
2096 /* rol dn */
2097 void OP_F280 ()
2098 {
2099 unsigned long value;
2100 int c,n,z;
2101
2102 value = State.regs[REG_D0 + (insn & 0x3)];
2103 if (value & 0x80000000)
2104 c = 1;
2105
2106 value <<= 1;
2107 value |= ((PSW & PSW_C) != 0);
2108 State.regs[REG_D0 + (insn & 0x3)] = value;
2109 z = (value == 0);
2110 n = (value & 0x80000000) != 0;
2111 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2112 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2113 }
2114
2115 /* beq label:8 */
2116 void OP_C800 ()
2117 {
2118 /* The dispatching code will add 2 after we return, so
2119 we subtract two here to make things right. */
2120 if (PSW & PSW_Z)
2121 State.pc += SEXT8 (insn & 0xff) - 2;
2122 }
2123
2124 /* bne label:8 */
2125 void OP_C900 ()
2126 {
2127 /* The dispatching code will add 2 after we return, so
2128 we subtract two here to make things right. */
2129 if (!(PSW & PSW_Z))
2130 State.pc += SEXT8 (insn & 0xff) - 2;
2131 }
2132
2133 /* bgt label:8 */
2134 void OP_C100 ()
2135 {
2136 /* The dispatching code will add 2 after we return, so
2137 we subtract two here to make things right. */
2138 if (!((PSW & PSW_Z)
2139 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)))
2140 State.pc += SEXT8 (insn & 0xff) - 2;
2141 }
2142
2143 /* bge label:8 */
2144 void OP_C200 ()
2145 {
2146 /* The dispatching code will add 2 after we return, so
2147 we subtract two here to make things right. */
2148 if (!(((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2149 State.pc += SEXT8 (insn & 0xff) - 2;
2150 }
2151
2152 /* ble label:8 */
2153 void OP_C300 ()
2154 {
2155 /* The dispatching code will add 2 after we return, so
2156 we subtract two here to make things right. */
2157 if ((PSW & PSW_Z)
2158 || (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0))
2159 State.pc += SEXT8 (insn & 0xff) - 2;
2160 }
2161
2162 /* blt label:8 */
2163 void OP_C000 ()
2164 {
2165 /* The dispatching code will add 2 after we return, so
2166 we subtract two here to make things right. */
2167 if (((PSW & PSW_N) != 0) ^ (PSW & PSW_V) != 0)
2168 State.pc += SEXT8 (insn & 0xff) - 2;
2169 }
2170
2171 /* bhi label:8 */
2172 void OP_C500 ()
2173 {
2174 /* The dispatching code will add 2 after we return, so
2175 we subtract two here to make things right. */
2176 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2177 State.pc += SEXT8 (insn & 0xff) - 2;
2178 }
2179
2180 /* bcc label:8 */
2181 void OP_C600 ()
2182 {
2183 /* The dispatching code will add 2 after we return, so
2184 we subtract two here to make things right. */
2185 if (!(PSW & PSW_C))
2186 State.pc += SEXT8 (insn & 0xff) - 2;
2187 }
2188
2189 /* bls label:8 */
2190 void OP_C700 ()
2191 {
2192 /* The dispatching code will add 2 after we return, so
2193 we subtract two here to make things right. */
2194 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2195 State.pc += SEXT8 (insn & 0xff) - 2;
2196 }
2197
2198 /* bcs label:8 */
2199 void OP_C400 ()
2200 {
2201 /* The dispatching code will add 2 after we return, so
2202 we subtract two here to make things right. */
2203 if (PSW & PSW_C)
2204 State.pc += SEXT8 (insn & 0xff) - 2;
2205 }
2206
2207 /* bvc label:8 */
2208 void OP_F8E800 ()
2209 {
2210 /* The dispatching code will add 3 after we return, so
2211 we subtract two here to make things right. */
2212 if (!(PSW & PSW_V))
2213 State.pc += SEXT8 (insn & 0xff) - 3;
2214 }
2215
2216 /* bvs label:8 */
2217 void OP_F8E900 ()
2218 {
2219 /* The dispatching code will add 3 after we return, so
2220 we subtract two here to make things right. */
2221 if (PSW & PSW_V)
2222 State.pc += SEXT8 (insn & 0xff) - 3;
2223 }
2224
2225 /* bnc label:8 */
2226 void OP_F8EA00 ()
2227 {
2228 /* The dispatching code will add 3 after we return, so
2229 we subtract two here to make things right. */
2230 if (!(PSW & PSW_N))
2231 State.pc += SEXT8 (insn & 0xff) - 3;
2232 }
2233
2234 /* bns label:8 */
2235 void OP_F8EB00 ()
2236 {
2237 /* The dispatching code will add 3 after we return, so
2238 we subtract two here to make things right. */
2239 if (PSW & PSW_N)
2240 State.pc += SEXT8 (insn & 0xff) - 3;
2241 }
2242
2243 /* bra label:8 */
2244 void OP_CA00 ()
2245 {
2246 /* The dispatching code will add 2 after we return, so
2247 we subtract two here to make things right. */
2248 State.pc += SEXT8 (insn & 0xff) - 2;
2249 }
2250
2251 /* leq */
2252 void OP_D8 ()
2253 {
2254 abort ();
2255 }
2256
2257 /* lne */
2258 void OP_D9 ()
2259 {
2260 abort ();
2261 }
2262
2263 /* lgt */
2264 void OP_D1 ()
2265 {
2266 abort ();
2267 }
2268
2269 /* lge */
2270 void OP_D2 ()
2271 {
2272 abort ();
2273 }
2274
2275 /* lle */
2276 void OP_D3 ()
2277 {
2278 abort ();
2279 }
2280
2281 /* llt */
2282 void OP_D0 ()
2283 {
2284 abort ();
2285 }
2286
2287 /* lhi */
2288 void OP_D5 ()
2289 {
2290 abort ();
2291 }
2292
2293 /* lcc */
2294 void OP_D6 ()
2295 {
2296 abort ();
2297 }
2298
2299 /* lls */
2300 void OP_D7 ()
2301 {
2302 abort ();
2303 }
2304
2305 /* lcs */
2306 void OP_D4 ()
2307 {
2308 abort ();
2309 }
2310
2311 /* lra */
2312 void OP_DA ()
2313 {
2314 abort ();
2315 }
2316
2317 /* setlb */
2318 void OP_DB ()
2319 {
2320 abort ();
2321 }
2322
2323 /* jmp (an) */
2324 void OP_F0F4 ()
2325 {
2326 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2327 }
2328
2329 /* jmp label:16 */
2330 void OP_CC0000 ()
2331 {
2332 State.pc += SEXT16 (insn & 0xffff) - 3;
2333 }
2334
2335 /* jmp label:32 */
2336 void OP_DC000000 ()
2337 {
2338 State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
2339 }
2340
2341 /* call label:16,reg_list,imm8 */
2342 void OP_CD000000 ()
2343 {
2344 unsigned int next_pc, sp, adjust;
2345 unsigned long mask;
2346
2347 sp = State.regs[REG_SP];
2348 next_pc = State.pc + 2;
2349 State.mem[sp] = next_pc & 0xff;
2350 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2351 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2352 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2353
2354 mask = insn & 0xff;
2355
2356 adjust = 0;
2357 if (mask & 0x80)
2358 {
2359 adjust -= 4;
2360 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2361 }
2362
2363 if (mask & 0x40)
2364 {
2365 adjust -= 4;
2366 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2367 }
2368
2369 if (mask & 0x20)
2370 {
2371 adjust -= 4;
2372 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2373 }
2374
2375 if (mask & 0x10)
2376 {
2377 adjust -= 4;
2378 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2379 }
2380
2381 if (mask & 0x8)
2382 {
2383 adjust -= 4;
2384 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2385 adjust -= 4;
2386 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2387 adjust -= 4;
2388 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2389 adjust -= 4;
2390 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2391 adjust -= 4;
2392 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2393 adjust -= 4;
2394 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2395 adjust -= 4;
2396 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2397 adjust -= 4;
2398 }
2399
2400 /* And make sure to update the stack pointer. */
2401 State.regs[REG_SP] -= extension;
2402 State.regs[REG_MDR] = next_pc;
2403 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2404 }
2405
2406 /* call label:32,reg_list,imm8*/
2407 void OP_DD000000 ()
2408 {
2409 unsigned int next_pc, sp, adjust;
2410 unsigned long mask;
2411
2412 sp = State.regs[REG_SP];
2413 next_pc = State.pc + 2;
2414 State.mem[sp] = next_pc & 0xff;
2415 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2416 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2417 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2418
2419 mask = (extension & 0xff00) >> 8;
2420
2421 adjust = 0;
2422 if (mask & 0x80)
2423 {
2424 adjust -= 4;
2425 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2426 }
2427
2428 if (mask & 0x40)
2429 {
2430 adjust -= 4;
2431 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2432 }
2433
2434 if (mask & 0x20)
2435 {
2436 adjust -= 4;
2437 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2438 }
2439
2440 if (mask & 0x10)
2441 {
2442 adjust -= 4;
2443 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2444 }
2445
2446 if (mask & 0x8)
2447 {
2448 adjust -= 4;
2449 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2450 adjust -= 4;
2451 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2452 adjust -= 4;
2453 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2454 adjust -= 4;
2455 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2456 adjust -= 4;
2457 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2458 adjust -= 4;
2459 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2460 adjust -= 4;
2461 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2462 adjust -= 4;
2463 }
2464
2465 /* And make sure to update the stack pointer. */
2466 State.regs[REG_SP] -= (extension & 0xff);
2467 State.regs[REG_MDR] = next_pc;
2468 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2469 }
2470
2471 /* calls (an) */
2472 void OP_F0F0 ()
2473 {
2474 unsigned int next_pc, sp;
2475
2476 sp = State.regs[REG_SP];
2477 next_pc = State.pc + 2;
2478 State.mem[sp] = next_pc & 0xff;
2479 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2480 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2481 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2482 State.regs[REG_MDR] = next_pc;
2483 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2484 }
2485
2486 /* calls label:16 */
2487 void OP_FAFF0000 ()
2488 {
2489 unsigned int next_pc, sp;
2490
2491 sp = State.regs[REG_SP];
2492 next_pc = State.pc + 4;
2493 State.mem[sp] = next_pc & 0xff;
2494 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2495 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2496 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2497 State.regs[REG_MDR] = next_pc;
2498 State.pc += SEXT16 (insn & 0xffff) - 4;
2499 }
2500
2501 /* calls label:32 */
2502 void OP_FCFF0000 ()
2503 {
2504 unsigned int next_pc, sp;
2505
2506 sp = State.regs[REG_SP];
2507 next_pc = State.pc + 6;
2508 State.mem[sp] = next_pc & 0xff;
2509 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2510 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2511 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2512 State.regs[REG_MDR] = next_pc;
2513 State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2514 }
2515
2516 /* ret reg_list, imm8 */
2517 void OP_DF0000 ()
2518 {
2519 unsigned int sp;
2520 unsigned long mask;
2521
2522 State.regs[REG_SP] += insn & 0xff;
2523 State.pc = State.regs[REG_MDR] - 3;
2524 sp = State.regs[REG_SP];
2525
2526 mask = (insn & 0xff00) >> 8;
2527
2528 if (mask & 0x8)
2529 {
2530 sp += 4;
2531 State.regs[REG_LAR] = load_mem (sp, 4);
2532 sp += 4;
2533 State.regs[REG_LIR] = load_mem (sp, 4);
2534 sp += 4;
2535 State.regs[REG_MDR] = load_mem (sp, 4);
2536 sp += 4;
2537 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2538 sp += 4;
2539 State.regs[REG_A0] = load_mem (sp, 4);
2540 sp += 4;
2541 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2542 sp += 4;
2543 State.regs[REG_D0] = load_mem (sp, 4);
2544 sp += 4;
2545 }
2546
2547 if (mask & 0x10)
2548 {
2549 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2550 sp += 4;
2551 }
2552
2553 if (mask & 0x20)
2554 {
2555 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2556 sp += 4;
2557 }
2558
2559 if (mask & 0x40)
2560 {
2561 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2562 sp += 4;
2563 }
2564
2565 if (mask & 0x80)
2566 {
2567 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2568 sp += 4;
2569 }
2570 }
2571
2572 /* retf reg_list,imm8 */
2573 void OP_DE0000 ()
2574 {
2575 unsigned int sp;
2576 unsigned long mask;
2577
2578 State.regs[REG_SP] += insn & 0xff;
2579 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2580 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2581 State.pc -= 3;
2582
2583 sp = State.regs[REG_SP];
2584
2585 mask = (insn & 0xff00) >> 8;
2586
2587 if (mask & 0x8)
2588 {
2589 sp += 4;
2590 State.regs[REG_LAR] = load_mem (sp, 4);
2591 sp += 4;
2592 State.regs[REG_LIR] = load_mem (sp, 4);
2593 sp += 4;
2594 State.regs[REG_MDR] = load_mem (sp, 4);
2595 sp += 4;
2596 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2597 sp += 4;
2598 State.regs[REG_A0] = load_mem (sp, 4);
2599 sp += 4;
2600 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2601 sp += 4;
2602 State.regs[REG_D0] = load_mem (sp, 4);
2603 sp += 4;
2604 }
2605
2606 if (mask & 0x10)
2607 {
2608 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2609 sp += 4;
2610 }
2611
2612 if (mask & 0x20)
2613 {
2614 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2615 sp += 4;
2616 }
2617
2618 if (mask & 0x40)
2619 {
2620 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2621 sp += 4;
2622 }
2623
2624 if (mask & 0x80)
2625 {
2626 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2627 sp += 4;
2628 }
2629 }
2630
2631 /* rets */
2632 void OP_F0FC ()
2633 {
2634 unsigned int sp;
2635
2636 sp = State.regs[REG_SP];
2637 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2638 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2639 State.pc -= 2;
2640 }
2641
2642 /* rti */
2643 void OP_F0FD ()
2644 {
2645 abort ();
2646 }
2647
2648 /* trap */
2649 void OP_F0FE ()
2650 {
2651 /* We use this for simulated system calls; we may need to change
2652 it to a reserved instruction if we conflict with uses at
2653 Matsushita. */
2654 int save_errno = errno;
2655 errno = 0;
2656
2657 /* Registers passed to trap 0 */
2658
2659 /* Function number. */
2660 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2661
2662 /* Parameters. */
2663 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2664 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2665 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2666
2667 /* Registers set by trap 0 */
2668
2669 #define RETVAL State.regs[0] /* return value */
2670 #define RETERR State.regs[1] /* return error code */
2671
2672 /* Turn a pointer in a register into a pointer into real memory. */
2673
2674 #define MEMPTR(x) (State.mem + x)
2675
2676 switch (FUNC)
2677 {
2678 #if !defined(__GO32__) && !defined(_WIN32)
2679 case SYS_fork:
2680 RETVAL = fork ();
2681 break;
2682 case SYS_execve:
2683 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2684 (char **)MEMPTR (PARM3));
2685 break;
2686 case SYS_execv:
2687 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2688 break;
2689 #endif
2690
2691 case SYS_read:
2692 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2693 MEMPTR (PARM2), PARM3);
2694 break;
2695 case SYS_write:
2696 if (PARM1 == 1)
2697 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2698 MEMPTR (PARM2), PARM3);
2699 else
2700 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2701 MEMPTR (PARM2), PARM3);
2702 break;
2703 case SYS_lseek:
2704 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2705 break;
2706 case SYS_close:
2707 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2708 break;
2709 case SYS_open:
2710 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2711 break;
2712 case SYS_exit:
2713 /* EXIT - caller can look in PARM1 to work out the
2714 reason */
2715 if (PARM1 == 0xdead || PARM1 == 0x1)
2716 State.exception = SIGABRT;
2717 else
2718 State.exception = SIGQUIT;
2719 break;
2720
2721 case SYS_stat: /* added at hmsi */
2722 /* stat system call */
2723 {
2724 struct stat host_stat;
2725 reg_t buf;
2726
2727 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2728
2729 buf = PARM2;
2730
2731 /* Just wild-assed guesses. */
2732 store_mem (buf, 2, host_stat.st_dev);
2733 store_mem (buf + 2, 2, host_stat.st_ino);
2734 store_mem (buf + 4, 4, host_stat.st_mode);
2735 store_mem (buf + 8, 2, host_stat.st_nlink);
2736 store_mem (buf + 10, 2, host_stat.st_uid);
2737 store_mem (buf + 12, 2, host_stat.st_gid);
2738 store_mem (buf + 14, 2, host_stat.st_rdev);
2739 store_mem (buf + 16, 4, host_stat.st_size);
2740 store_mem (buf + 20, 4, host_stat.st_atime);
2741 store_mem (buf + 28, 4, host_stat.st_mtime);
2742 store_mem (buf + 36, 4, host_stat.st_ctime);
2743 }
2744 break;
2745
2746 case SYS_chown:
2747 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2748 break;
2749 case SYS_chmod:
2750 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2751 break;
2752 case SYS_time:
2753 RETVAL = time (MEMPTR (PARM1));
2754 break;
2755 case SYS_times:
2756 {
2757 struct tms tms;
2758 RETVAL = times (&tms);
2759 store_mem (PARM1, 4, tms.tms_utime);
2760 store_mem (PARM1 + 4, 4, tms.tms_stime);
2761 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2762 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2763 break;
2764 }
2765 case SYS_gettimeofday:
2766 {
2767 struct timeval t;
2768 struct timezone tz;
2769 RETVAL = gettimeofday (&t, &tz);
2770 store_mem (PARM1, 4, t.tv_sec);
2771 store_mem (PARM1 + 4, 4, t.tv_usec);
2772 store_mem (PARM2, 4, tz.tz_minuteswest);
2773 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2774 break;
2775 }
2776 case SYS_utime:
2777 /* Cast the second argument to void *, to avoid type mismatch
2778 if a prototype is present. */
2779 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2780 break;
2781 default:
2782 abort ();
2783 }
2784 RETERR = errno;
2785 errno = save_errno;
2786 }
2787
2788 /* rtm */
2789 void OP_F0FF ()
2790 {
2791 abort ();
2792 }
2793
2794 /* nop */
2795 void OP_CB ()
2796 {
2797 }
2798
2799 /* putx */
2800 void OP_F500 ()
2801 {
2802 }
2803
2804 /* getx */
2805 void OP_F6F0 ()
2806 {
2807 }
2808
2809 /* mulq */
2810 void OP_F600 ()
2811 {
2812 }
2813
2814 /* mulq */
2815 void OP_F90000 ()
2816 {
2817 }
2818
2819 /* mulq */
2820 void OP_FB000000 ()
2821 {
2822 }
2823
2824 /* mulq */
2825 void OP_FD000000 ()
2826 {
2827 }
2828
2829 /* mulqu */
2830 void OP_F610 ()
2831 {
2832 }
2833
2834 /* mulqu */
2835 void OP_F91400 ()
2836 {
2837 }
2838
2839 /* mulqu */
2840 void OP_FB140000 ()
2841 {
2842 }
2843
2844 /* mulqu */
2845 void OP_FD140000 ()
2846 {
2847 }
2848
2849 /* sat16 */
2850 void OP_F640 ()
2851 {
2852 }
2853
2854 /* sat24 */
2855 void OP_F650 ()
2856 {
2857 }
2858
2859 /* bsch */
2860 void OP_F670 ()
2861 {
2862 }