7 #include "mn10300_sim.h"
9 #include "sys/syscall.h"
13 #include <sys/times.h>
16 #define REG0(X) ((X) & 0x3)
17 #define REG1(X) (((X) & 0xc) >> 2)
18 #define REG0_4(X) (((X) & 0x30) >> 4)
19 #define REG0_8(X) (((X) & 0x300) >> 8)
20 #define REG1_8(X) (((X) & 0xc00) >> 10)
21 #define REG0_16(X) (((X) & 0x30000) >> 16)
22 #define REG1_16(X) (((X) & 0xc0000) >> 18)
25 void OP_8000 (insn
, extension
)
26 unsigned long insn
, extension
;
28 State
.regs
[REG_D0
+ REG0_8 (insn
)] = SEXT8 (insn
& 0xff);
32 void OP_80 (insn
, extension
)
33 unsigned long insn
, extension
;
35 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG1 (insn
)];
39 void OP_F1E0 (insn
, extension
)
40 unsigned long insn
, extension
;
42 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_D0
+ REG1 (insn
)];
46 void OP_F1D0 (insn
, extension
)
47 unsigned long insn
, extension
;
49 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_A0
+ REG1 (insn
)];
53 void OP_9000 (insn
, extension
)
54 unsigned long insn
, extension
;
56 State
.regs
[REG_A0
+ REG0_8 (insn
)] = insn
& 0xff;
60 void OP_90 (insn
, extension
)
61 unsigned long insn
, extension
;
63 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_A0
+ REG1 (insn
)];
67 void OP_3C (insn
, extension
)
68 unsigned long insn
, extension
;
70 State
.regs
[REG_A0
+ REG0 (insn
)] = State
.regs
[REG_SP
];
74 void OP_F2F0 (insn
, extension
)
75 unsigned long insn
, extension
;
77 State
.regs
[REG_SP
] = State
.regs
[REG_A0
+ REG1 (insn
)];
81 void OP_F2E4 (insn
, extension
)
82 unsigned long insn
, extension
;
84 State
.regs
[REG_D0
+ REG0 (insn
)] = PSW
;
88 void OP_F2F3 (insn
, extension
)
89 unsigned long insn
, extension
;
91 PSW
= State
.regs
[REG_D0
+ REG1 (insn
)];
95 void OP_F2E0 (insn
, extension
)
96 unsigned long insn
, extension
;
98 State
.regs
[REG_D0
+ REG0 (insn
)] = State
.regs
[REG_MDR
];
102 void OP_F2F2 (insn
, extension
)
103 unsigned long insn
, extension
;
105 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ REG1 (insn
)];
109 void OP_70 (insn
, extension
)
110 unsigned long insn
, extension
;
112 State
.regs
[REG_D0
+ REG1 (insn
)]
113 = load_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 4);
116 /* mov (d8,am), dn */
117 void OP_F80000 (insn
, extension
)
118 unsigned long insn
, extension
;
120 State
.regs
[REG_D0
+ REG1_8 (insn
)]
121 = load_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
122 + SEXT8 (insn
& 0xff)), 4);
125 /* mov (d16,am), dn */
126 void OP_FA000000 (insn
, extension
)
127 unsigned long insn
, extension
;
129 State
.regs
[REG_D0
+ REG1_16 (insn
)]
130 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
131 + SEXT16 (insn
& 0xffff)), 4);
134 /* mov (d32,am), dn */
135 void OP_FC000000 (insn
, extension
)
136 unsigned long insn
, extension
;
138 State
.regs
[REG_D0
+ REG1_16 (insn
)]
139 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
140 + ((insn
& 0xffff) << 16) + extension
), 4);
143 /* mov (d8,sp), dn */
144 void OP_5800 (insn
, extension
)
145 unsigned long insn
, extension
;
147 State
.regs
[REG_D0
+ REG0_8 (insn
)]
148 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
151 /* mov (d16,sp), dn */
152 void OP_FAB40000 (insn
, extension
)
153 unsigned long insn
, extension
;
155 State
.regs
[REG_D0
+ REG0_16 (insn
)]
156 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
159 /* mov (d32,sp), dn */
160 void OP_FCB40000 (insn
, extension
)
161 unsigned long insn
, extension
;
163 State
.regs
[REG_D0
+ REG0_16 (insn
)]
164 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
167 /* mov (di,am), dn */
168 void OP_F300 (insn
, extension
)
169 unsigned long insn
, extension
;
171 State
.regs
[REG_D0
+ REG0_4 (insn
)]
172 = load_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
173 + State
.regs
[REG_D0
+ REG1 (insn
)]), 4);
176 /* mov (abs16), dn */
177 void OP_300000 (insn
, extension
)
178 unsigned long insn
, extension
;
180 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_mem ((insn
& 0xffff), 4);
183 /* mov (abs32), dn */
184 void OP_FCA40000 (insn
, extension
)
185 unsigned long insn
, extension
;
187 State
.regs
[REG_D0
+ REG0_16 (insn
)]
188 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
192 void OP_F000 (insn
, extension
)
193 unsigned long insn
, extension
;
195 State
.regs
[REG_A0
+ REG1 (insn
)]
196 = load_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 4);
199 /* mov (d8,am), an */
200 void OP_F82000 (insn
, extension
)
201 unsigned long insn
, extension
;
203 State
.regs
[REG_A0
+ REG1_8 (insn
)]
204 = load_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
205 + SEXT8 (insn
& 0xff)), 4);
208 /* mov (d16,am), an */
209 void OP_FA200000 (insn
, extension
)
210 unsigned long insn
, extension
;
212 State
.regs
[REG_A0
+ REG1_16 (insn
)]
213 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
214 + SEXT16 (insn
& 0xffff)), 4);
217 /* mov (d32,am), an */
218 void OP_FC200000 (insn
, extension
)
219 unsigned long insn
, extension
;
221 State
.regs
[REG_A0
+ REG1_16 (insn
)]
222 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
223 + ((insn
& 0xffff) << 16) + extension
), 4);
226 /* mov (d8,sp), an */
227 void OP_5C00 (insn
, extension
)
228 unsigned long insn
, extension
;
230 State
.regs
[REG_A0
+ REG0_8 (insn
)]
231 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
234 /* mov (d16,sp), an */
235 void OP_FAB00000 (insn
, extension
)
236 unsigned long insn
, extension
;
238 State
.regs
[REG_A0
+ REG0_16 (insn
)]
239 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
242 /* mov (d32,sp), an */
243 void OP_FCB00000 (insn
, extension
)
244 unsigned long insn
, extension
;
246 State
.regs
[REG_A0
+ REG0_16 (insn
)]
247 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
250 /* mov (di,am), an */
251 void OP_F380 (insn
, extension
)
252 unsigned long insn
, extension
;
254 State
.regs
[REG_A0
+ REG0_4 (insn
)]
255 = load_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
256 + State
.regs
[REG_D0
+ REG1 (insn
)]), 4);
259 /* mov (abs16), an */
260 void OP_FAA00000 (insn
, extension
)
261 unsigned long insn
, extension
;
263 State
.regs
[REG_A0
+ REG0_16 (insn
)] = load_mem ((insn
& 0xffff), 4);
266 /* mov (abs32), an */
267 void OP_FCA00000 (insn
, extension
)
268 unsigned long insn
, extension
;
270 State
.regs
[REG_A0
+ REG0_16 (insn
)]
271 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
274 /* mov (d8,am), sp */
275 void OP_F8F000 (insn
, extension
)
276 unsigned long insn
, extension
;
279 = load_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
280 + SEXT8 (insn
& 0xff)), 4);
284 void OP_60 (insn
, extension
)
285 unsigned long insn
, extension
;
287 store_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 4,
288 State
.regs
[REG_D0
+ REG1 (insn
)]);
291 /* mov dm, (d8,an) */
292 void OP_F81000 (insn
, extension
)
293 unsigned long insn
, extension
;
295 store_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
296 + SEXT8 (insn
& 0xff)), 4,
297 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
300 /* mov dm (d16,an) */
301 void OP_FA100000 (insn
, extension
)
302 unsigned long insn
, extension
;
304 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
305 + SEXT16 (insn
& 0xffff)), 4,
306 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
309 /* mov dm (d32,an) */
310 void OP_FC100000 (insn
, extension
)
311 unsigned long insn
, extension
;
313 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
314 + ((insn
& 0xffff) << 16) + extension
), 4,
315 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
318 /* mov dm, (d8,sp) */
319 void OP_4200 (insn
, extension
)
320 unsigned long insn
, extension
;
322 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
323 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
326 /* mov dm, (d16,sp) */
327 void OP_FA910000 (insn
, extension
)
328 unsigned long insn
, extension
;
330 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
331 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
334 /* mov dm, (d32,sp) */
335 void OP_FC910000 (insn
, extension
)
336 unsigned long insn
, extension
;
338 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
339 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
342 /* mov dm, (di,an) */
343 void OP_F340 (insn
, extension
)
344 unsigned long insn
, extension
;
346 store_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
347 + State
.regs
[REG_D0
+ REG1 (insn
)]), 4,
348 State
.regs
[REG_D0
+ REG0_4 (insn
)]);
351 /* mov dm, (abs16) */
352 void OP_10000 (insn
, extension
)
353 unsigned long insn
, extension
;
355 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_D0
+ REG1_16 (insn
)]);
358 /* mov dm, (abs32) */
359 void OP_FC810000 (insn
, extension
)
360 unsigned long insn
, extension
;
362 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_D0
+ REG1_16 (insn
)]);
366 void OP_F010 (insn
, extension
)
367 unsigned long insn
, extension
;
369 store_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 4,
370 State
.regs
[REG_A0
+ REG1 (insn
)]);
373 /* mov am, (d8,an) */
374 void OP_F83000 (insn
, extension
)
375 unsigned long insn
, extension
;
377 store_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
378 + SEXT8 (insn
& 0xff)), 4,
379 State
.regs
[REG_A0
+ REG1_8 (insn
)]);
382 /* mov am, (d16,an) */
383 void OP_FA300000 (insn
, extension
)
384 unsigned long insn
, extension
;
386 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
387 + SEXT16 (insn
& 0xffff)), 4,
388 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
391 /* mov am, (d32,an) */
392 void OP_FC300000 (insn
, extension
)
393 unsigned long insn
, extension
;
395 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
396 + ((insn
& 0xffff) << 16) + extension
), 4,
397 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
400 /* mov am, (d8,sp) */
401 void OP_4300 (insn
, extension
)
402 unsigned long insn
, extension
;
404 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
405 State
.regs
[REG_A0
+ REG1_8 (insn
)]);
408 /* mov am, (d16,sp) */
409 void OP_FA900000 (insn
, extension
)
410 unsigned long insn
, extension
;
412 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
413 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
416 /* mov am, (d32,sp) */
417 void OP_FC900000 (insn
, extension
)
418 unsigned long insn
, extension
;
420 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
421 State
.regs
[REG_A0
+ REG1_16 (insn
)]);
424 /* mov am, (di,an) */
425 void OP_F3C0 (insn
, extension
)
426 unsigned long insn
, extension
;
428 store_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
429 + State
.regs
[REG_D0
+ REG1 (insn
)]), 4,
430 State
.regs
[REG_A0
+ REG0_4 (insn
)]);
433 /* mov am, (abs16) */
434 void OP_FA800000 (insn
, extension
)
435 unsigned long insn
, extension
;
437 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_A0
+ REG1_16 (insn
)]);
440 /* mov am, (abs32) */
441 void OP_FC800000 (insn
, extension
)
442 unsigned long insn
, extension
;
444 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_A0
+ REG1_16 (insn
)]);
447 /* mov sp, (d8,an) */
448 void OP_F8F400 (insn
, extension
)
449 unsigned long insn
, extension
;
451 store_mem (State
.regs
[REG_A0
+ REG0_8 (insn
)] + SEXT8 (insn
& 0xff),
452 4, State
.regs
[REG_SP
]);
456 void OP_2C0000 (insn
, extension
)
457 unsigned long insn
, extension
;
461 value
= SEXT16 (insn
& 0xffff);
462 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
466 void OP_FCCC0000 (insn
, extension
)
467 unsigned long insn
, extension
;
471 value
= ((insn
& 0xffff) << 16) + extension
;
472 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
476 void OP_240000 (insn
, extension
)
477 unsigned long insn
, extension
;
481 value
= insn
& 0xffff;
482 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
486 void OP_FCDC0000 (insn
, extension
)
487 unsigned long insn
, extension
;
491 value
= ((insn
& 0xffff) << 16) + extension
;
492 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
496 void OP_F040 (insn
, extension
)
497 unsigned long insn
, extension
;
499 State
.regs
[REG_D0
+ REG1 (insn
)]
500 = load_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 1);
503 /* movbu (d8,am), dn */
504 void OP_F84000 (insn
, extension
)
505 unsigned long insn
, extension
;
507 State
.regs
[REG_D0
+ REG1_8 (insn
)]
508 = load_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
509 + SEXT8 (insn
& 0xff)), 1);
512 /* movbu (d16,am), dn */
513 void OP_FA400000 (insn
, extension
)
514 unsigned long insn
, extension
;
516 State
.regs
[REG_D0
+ REG1_16 (insn
)]
517 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
518 + SEXT16 (insn
& 0xffff)), 1);
521 /* movbu (d32,am), dn */
522 void OP_FC400000 (insn
, extension
)
523 unsigned long insn
, extension
;
525 State
.regs
[REG_D0
+ REG1_16 (insn
)]
526 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
527 + ((insn
& 0xffff) << 16) + extension
), 1);
530 /* movbu (d8,sp), dn */
531 void OP_F8B800 (insn
, extension
)
532 unsigned long insn
, extension
;
534 State
.regs
[REG_D0
+ REG0_8 (insn
)]
535 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 1);
538 /* movbu (d16,sp), dn */
539 void OP_FAB80000 (insn
, extension
)
540 unsigned long insn
, extension
;
542 State
.regs
[REG_D0
+ REG0_16 (insn
)]
543 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 1);
546 /* movbu (d32,sp), dn */
547 void OP_FCB80000 (insn
, extension
)
548 unsigned long insn
, extension
;
550 State
.regs
[REG_D0
+ REG0_16 (insn
)]
551 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 1);
554 /* movbu (di,am), dn */
555 void OP_F400 (insn
, extension
)
556 unsigned long insn
, extension
;
558 State
.regs
[REG_D0
+ REG0_4 (insn
)]
559 = load_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
560 + State
.regs
[REG_D0
+ REG1 (insn
)]), 1);
563 /* movbu (abs16), dn */
564 void OP_340000 (insn
, extension
)
565 unsigned long insn
, extension
;
567 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_mem ((insn
& 0xffff), 1);
570 /* movbu (abs32), dn */
571 void OP_FCA80000 (insn
, extension
)
572 unsigned long insn
, extension
;
574 State
.regs
[REG_D0
+ REG0_16 (insn
)]
575 = load_mem ((((insn
& 0xffff) << 16) + extension
), 1);
579 void OP_F050 (insn
, extension
)
580 unsigned long insn
, extension
;
582 store_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 1,
583 State
.regs
[REG_D0
+ REG1 (insn
)]);
586 /* movbu dm, (d8,an) */
587 void OP_F85000 (insn
, extension
)
588 unsigned long insn
, extension
;
590 store_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
591 + SEXT8 (insn
& 0xff)), 1,
592 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
595 /* movbu dm, (d16,an) */
596 void OP_FA500000 (insn
, extension
)
597 unsigned long insn
, extension
;
599 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
600 + SEXT16 (insn
& 0xffff)), 1,
601 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
604 /* movbu dm, (d32,an) */
605 void OP_FC500000 (insn
, extension
)
606 unsigned long insn
, extension
;
608 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
609 + ((insn
& 0xffff) << 16) + extension
), 1,
610 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
613 /* movbu dm, (d8,sp) */
614 void OP_F89200 (insn
, extension
)
615 unsigned long insn
, extension
;
617 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 1,
618 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
621 /* movbu dm, (d16,sp) */
622 void OP_FA920000 (insn
, extension
)
623 unsigned long insn
, extension
;
625 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
626 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
629 /* movbu dm (d32,sp) */
630 void OP_FC920000 (insn
, extension
)
631 unsigned long insn
, extension
;
633 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
634 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
637 /* movbu dm, (di,an) */
638 void OP_F440 (insn
, extension
)
639 unsigned long insn
, extension
;
641 store_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
642 + State
.regs
[REG_D0
+ REG1 (insn
)]), 1,
643 State
.regs
[REG_D0
+ REG0_4 (insn
)]);
646 /* movbu dm, (abs16) */
647 void OP_20000 (insn
, extension
)
648 unsigned long insn
, extension
;
650 store_mem ((insn
& 0xffff), 1, State
.regs
[REG_D0
+ REG1_16 (insn
)]);
653 /* movbu dm, (abs32) */
654 void OP_FC820000 (insn
, extension
)
655 unsigned long insn
, extension
;
657 store_mem ((((insn
& 0xffff) << 16) + extension
), 1, State
.regs
[REG_D0
+ REG1_16 (insn
)]);
661 void OP_F060 (insn
, extension
)
662 unsigned long insn
, extension
;
664 State
.regs
[REG_D0
+ REG1 (insn
)]
665 = load_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 2);
668 /* movhu (d8,am), dn */
669 void OP_F86000 (insn
, extension
)
670 unsigned long insn
, extension
;
672 State
.regs
[REG_D0
+ REG1_8 (insn
)]
673 = load_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
674 + SEXT8 (insn
& 0xff)), 2);
677 /* movhu (d16,am), dn */
678 void OP_FA600000 (insn
, extension
)
679 unsigned long insn
, extension
;
681 State
.regs
[REG_D0
+ REG1_16 (insn
)]
682 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
683 + SEXT16 (insn
& 0xffff)), 2);
686 /* movhu (d32,am), dn */
687 void OP_FC600000 (insn
, extension
)
688 unsigned long insn
, extension
;
690 State
.regs
[REG_D0
+ REG1_16 (insn
)]
691 = load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
692 + ((insn
& 0xffff) << 16) + extension
), 2);
695 /* movhu (d8,sp) dn */
696 void OP_F8BC00 (insn
, extension
)
697 unsigned long insn
, extension
;
699 State
.regs
[REG_D0
+ REG0_8 (insn
)]
700 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 2);
703 /* movhu (d16,sp), dn */
704 void OP_FABC0000 (insn
, extension
)
705 unsigned long insn
, extension
;
707 State
.regs
[REG_D0
+ REG0_16 (insn
)]
708 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 2);
711 /* movhu (d32,sp), dn */
712 void OP_FCBC0000 (insn
, extension
)
713 unsigned long insn
, extension
;
715 State
.regs
[REG_D0
+ REG0_16 (insn
)]
716 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2);
719 /* movhu (di,am), dn */
720 void OP_F480 (insn
, extension
)
721 unsigned long insn
, extension
;
723 State
.regs
[REG_D0
+ REG0_4 (insn
)]
724 = load_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
725 + State
.regs
[REG_D0
+ REG1 (insn
)]), 2);
728 /* movhu (abs16), dn */
729 void OP_380000 (insn
, extension
)
730 unsigned long insn
, extension
;
732 State
.regs
[REG_D0
+ REG0_16 (insn
)] = load_mem ((insn
& 0xffff), 2);
735 /* movhu (abs32), dn */
736 void OP_FCAC0000 (insn
, extension
)
737 unsigned long insn
, extension
;
739 State
.regs
[REG_D0
+ REG0_16 (insn
)]
740 = load_mem ((((insn
& 0xffff) << 16) + extension
), 2);
744 void OP_F070 (insn
, extension
)
745 unsigned long insn
, extension
;
747 store_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 2,
748 State
.regs
[REG_D0
+ REG1 (insn
)]);
751 /* movhu dm, (d8,an) */
752 void OP_F87000 (insn
, extension
)
753 unsigned long insn
, extension
;
755 store_mem ((State
.regs
[REG_A0
+ REG0_8 (insn
)]
756 + SEXT8 (insn
& 0xff)), 2,
757 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
760 /* movhu dm, (d16,an) */
761 void OP_FA700000 (insn
, extension
)
762 unsigned long insn
, extension
;
764 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
765 + SEXT16 (insn
& 0xffff)), 2,
766 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
769 /* movhu dm, (d32,an) */
770 void OP_FC700000 (insn
, extension
)
771 unsigned long insn
, extension
;
773 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
774 + ((insn
& 0xffff) << 16) + extension
), 2,
775 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
778 /* movhu dm,(d8,sp) */
779 void OP_F89300 (insn
, extension
)
780 unsigned long insn
, extension
;
782 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 2,
783 State
.regs
[REG_D0
+ REG1_8 (insn
)]);
786 /* movhu dm,(d16,sp) */
787 void OP_FA930000 (insn
, extension
)
788 unsigned long insn
, extension
;
790 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
791 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
794 /* movhu dm,(d32,sp) */
795 void OP_FC930000 (insn
, extension
)
796 unsigned long insn
, extension
;
798 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
799 State
.regs
[REG_D0
+ REG1_16 (insn
)]);
802 /* movhu dm, (di,an) */
803 void OP_F4C0 (insn
, extension
)
804 unsigned long insn
, extension
;
806 store_mem ((State
.regs
[REG_A0
+ REG0 (insn
)]
807 + State
.regs
[REG_D0
+ REG1 (insn
)]), 2,
808 State
.regs
[REG_D0
+ REG0_4 (insn
)]);
811 /* movhu dm, (abs16) */
812 void OP_30000 (insn
, extension
)
813 unsigned long insn
, extension
;
815 store_mem ((insn
& 0xffff), 2, State
.regs
[REG_D0
+ REG1_16 (insn
)]);
818 /* movhu dm, (abs32) */
819 void OP_FC830000 (insn
, extension
)
820 unsigned long insn
, extension
;
822 store_mem ((((insn
& 0xffff) << 16) + extension
), 2, State
.regs
[REG_D0
+ REG1_16 (insn
)]);
826 void OP_F2D0 (insn
, extension
)
827 unsigned long insn
, extension
;
829 if (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000)
830 State
.regs
[REG_MDR
] = -1;
832 State
.regs
[REG_MDR
] = 0;
836 void OP_10 (insn
, extension
)
837 unsigned long insn
, extension
;
839 State
.regs
[REG_D0
+ REG0 (insn
)] = SEXT8 (State
.regs
[REG_D0
+ REG0 (insn
)]);
843 void OP_14 (insn
, extension
)
844 unsigned long insn
, extension
;
846 State
.regs
[REG_D0
+ REG0 (insn
)] &= 0xff;
850 void OP_18 (insn
, extension
)
851 unsigned long insn
, extension
;
853 State
.regs
[REG_D0
+ REG0 (insn
)]
854 = SEXT16 (State
.regs
[REG_D0
+ REG0 (insn
)]);
858 void OP_1C (insn
, extension
)
859 unsigned long insn
, extension
;
861 State
.regs
[REG_D0
+ REG0 (insn
)] &= 0xffff;
864 /* movm (sp), reg_list */
865 void OP_CE00 (insn
, extension
)
866 unsigned long insn
, extension
;
868 unsigned long sp
= State
.regs
[REG_SP
];
876 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
878 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
880 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
882 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
884 State
.regs
[REG_A0
] = load_mem (sp
, 4);
886 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
888 State
.regs
[REG_D0
] = load_mem (sp
, 4);
894 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
900 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
906 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
912 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
916 /* And make sure to update the stack pointer. */
917 State
.regs
[REG_SP
] = sp
;
920 /* movm reg_list, (sp) */
921 void OP_CF00 (insn
, extension
)
922 unsigned long insn
, extension
;
924 unsigned long sp
= State
.regs
[REG_SP
];
932 store_mem (sp
, 4, State
.regs
[REG_D0
+ 2]);
938 store_mem (sp
, 4, State
.regs
[REG_D0
+ 3]);
944 store_mem (sp
, 4, State
.regs
[REG_A0
+ 2]);
950 store_mem (sp
, 4, State
.regs
[REG_A0
+ 3]);
956 store_mem (sp
, 4, State
.regs
[REG_D0
]);
958 store_mem (sp
, 4, State
.regs
[REG_D0
+ 1]);
960 store_mem (sp
, 4, State
.regs
[REG_A0
]);
962 store_mem (sp
, 4, State
.regs
[REG_A0
+ 1]);
964 store_mem (sp
, 4, State
.regs
[REG_MDR
]);
966 store_mem (sp
, 4, State
.regs
[REG_LIR
]);
968 store_mem (sp
, 4, State
.regs
[REG_LAR
]);
972 /* And make sure to update the stack pointer. */
973 State
.regs
[REG_SP
] = sp
;
977 void OP_0 (insn
, extension
)
978 unsigned long insn
, extension
;
980 State
.regs
[REG_D0
+ REG1 (insn
)] = 0;
983 PSW
&= ~(PSW_V
| PSW_C
| PSW_N
);
987 void OP_E0 (insn
, extension
)
988 unsigned long insn
, extension
;
991 unsigned long reg1
, reg2
, value
;
993 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
994 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
996 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
999 n
= (value
& 0x80000000);
1000 c
= (value
< reg1
) || (value
< reg2
);
1001 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1002 && (reg2
& 0x80000000) != (value
& 0x80000000));
1004 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1005 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1006 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1010 void OP_F160 (insn
, extension
)
1011 unsigned long insn
, extension
;
1014 unsigned long reg1
, reg2
, value
;
1016 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1017 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1018 value
= reg1
+ reg2
;
1019 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1022 n
= (value
& 0x80000000);
1023 c
= (value
< reg1
) || (value
< reg2
);
1024 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1025 && (reg2
& 0x80000000) != (value
& 0x80000000));
1027 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1028 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1029 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1033 void OP_F150 (insn
, extension
)
1034 unsigned long insn
, extension
;
1037 unsigned long reg1
, reg2
, value
;
1039 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1040 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1041 value
= reg1
+ reg2
;
1042 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1045 n
= (value
& 0x80000000);
1046 c
= (value
< reg1
) || (value
< reg2
);
1047 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1048 && (reg2
& 0x80000000) != (value
& 0x80000000));
1050 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1051 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1052 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1056 void OP_F170 (insn
, extension
)
1057 unsigned long insn
, extension
;
1060 unsigned long reg1
, reg2
, value
;
1062 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1063 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1064 value
= reg1
+ reg2
;
1065 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1068 n
= (value
& 0x80000000);
1069 c
= (value
< reg1
) || (value
< reg2
);
1070 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1071 && (reg2
& 0x80000000) != (value
& 0x80000000));
1073 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1074 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1075 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1079 void OP_2800 (insn
, extension
)
1080 unsigned long insn
, extension
;
1083 unsigned long reg1
, imm
, value
;
1085 reg1
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1086 imm
= SEXT8 (insn
& 0xff);
1088 State
.regs
[REG_D0
+ REG0_8 (insn
)] = value
;
1091 n
= (value
& 0x80000000);
1092 c
= (value
< reg1
) || (value
< imm
);
1093 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1094 && (reg1
& 0x80000000) != (value
& 0x80000000));
1096 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1097 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1098 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1102 void OP_FAC00000 (insn
, extension
)
1103 unsigned long insn
, extension
;
1106 unsigned long reg1
, imm
, value
;
1108 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1109 imm
= SEXT16 (insn
& 0xffff);
1111 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1114 n
= (value
& 0x80000000);
1115 c
= (value
< reg1
) || (value
< imm
);
1116 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1117 && (reg1
& 0x80000000) != (value
& 0x80000000));
1119 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1120 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1121 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1125 void OP_FCC00000 (insn
, extension
)
1126 unsigned long insn
, extension
;
1129 unsigned long reg1
, imm
, value
;
1131 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1132 imm
= ((insn
& 0xffff) << 16) + extension
;
1134 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1137 n
= (value
& 0x80000000);
1138 c
= (value
< reg1
) || (value
< imm
);
1139 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1140 && (reg1
& 0x80000000) != (value
& 0x80000000));
1142 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1143 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1144 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1148 void OP_2000 (insn
, extension
)
1149 unsigned long insn
, extension
;
1152 unsigned long reg1
, imm
, value
;
1154 reg1
= State
.regs
[REG_A0
+ REG0_8 (insn
)];
1155 imm
= SEXT8 (insn
& 0xff);
1157 State
.regs
[REG_A0
+ REG0_8 (insn
)] = value
;
1160 n
= (value
& 0x80000000);
1161 c
= (value
< reg1
) || (value
< imm
);
1162 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1163 && (reg1
& 0x80000000) != (value
& 0x80000000));
1165 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1166 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1167 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1171 void OP_FAD00000 (insn
, extension
)
1172 unsigned long insn
, extension
;
1175 unsigned long reg1
, imm
, value
;
1177 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1178 imm
= SEXT16 (insn
& 0xffff);
1180 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1183 n
= (value
& 0x80000000);
1184 c
= (value
< reg1
) || (value
< imm
);
1185 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1186 && (reg1
& 0x80000000) != (value
& 0x80000000));
1188 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1189 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1190 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1194 void OP_FCD00000 (insn
, extension
)
1195 unsigned long insn
, extension
;
1198 unsigned long reg1
, imm
, value
;
1200 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1201 imm
= ((insn
& 0xffff) << 16) + extension
;
1203 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1206 n
= (value
& 0x80000000);
1207 c
= (value
< reg1
) || (value
< imm
);
1208 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1209 && (reg1
& 0x80000000) != (value
& 0x80000000));
1211 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1212 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1213 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1217 void OP_F8FE00 (insn
, extension
)
1218 unsigned long insn
, extension
;
1220 unsigned long reg1
, imm
, value
;
1222 reg1
= State
.regs
[REG_SP
];
1223 imm
= SEXT8 (insn
& 0xff);
1225 State
.regs
[REG_SP
] = value
;
1229 void OP_FAFE0000 (insn
, extension
)
1230 unsigned long insn
, extension
;
1232 unsigned long reg1
, imm
, value
;
1234 reg1
= State
.regs
[REG_SP
];
1235 imm
= SEXT16 (insn
& 0xffff);
1237 State
.regs
[REG_SP
] = value
;
1241 void OP_FCFE0000 (insn
, extension
)
1242 unsigned long insn
, extension
;
1244 unsigned long reg1
, imm
, value
;
1246 reg1
= State
.regs
[REG_SP
];
1247 imm
= ((insn
& 0xffff) << 16) + extension
;
1249 State
.regs
[REG_SP
] = value
;
1253 void OP_F140 (insn
, extension
)
1254 unsigned long insn
, extension
;
1257 unsigned long reg1
, reg2
, value
;
1259 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1260 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1261 value
= reg1
+ reg2
+ ((PSW
& PSW_C
) != 0);
1262 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1265 n
= (value
& 0x80000000);
1266 c
= (value
< reg1
) || (value
< reg2
);
1267 v
= ((reg2
& 0x80000000) == (reg1
& 0x80000000)
1268 && (reg2
& 0x80000000) != (value
& 0x80000000));
1270 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1271 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1272 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1276 void OP_F100 (insn
, extension
)
1277 unsigned long insn
, extension
;
1280 unsigned long reg1
, reg2
, value
;
1282 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1283 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1284 value
= reg2
- reg1
;
1285 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1288 n
= (value
& 0x80000000);
1290 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1291 && (reg2
& 0x80000000) != (value
& 0x80000000));
1293 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1294 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1295 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1299 void OP_F120 (insn
, extension
)
1300 unsigned long insn
, extension
;
1303 unsigned long reg1
, reg2
, value
;
1305 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1306 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1307 value
= reg2
- reg1
;
1308 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1311 n
= (value
& 0x80000000);
1313 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1314 && (reg2
& 0x80000000) != (value
& 0x80000000));
1316 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1317 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1318 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1322 void OP_F110 (insn
, extension
)
1323 unsigned long insn
, extension
;
1326 unsigned long reg1
, reg2
, value
;
1328 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1329 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1330 value
= reg2
- reg1
;
1331 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1334 n
= (value
& 0x80000000);
1336 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1337 && (reg2
& 0x80000000) != (value
& 0x80000000));
1339 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1340 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1341 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1345 void OP_F130 (insn
, extension
)
1346 unsigned long insn
, extension
;
1349 unsigned long reg1
, reg2
, value
;
1351 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1352 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1353 value
= reg2
- reg1
;
1354 State
.regs
[REG_A0
+ REG0 (insn
)] = value
;
1357 n
= (value
& 0x80000000);
1359 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1360 && (reg2
& 0x80000000) != (value
& 0x80000000));
1362 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1363 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1364 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1368 void OP_FCC40000 (insn
, extension
)
1369 unsigned long insn
, extension
;
1372 unsigned long reg1
, imm
, value
;
1374 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1375 imm
= ((insn
& 0xffff) << 16) + extension
;
1377 State
.regs
[REG_D0
+ REG0_16 (insn
)] = value
;
1380 n
= (value
& 0x80000000);
1382 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1383 && (reg1
& 0x80000000) != (value
& 0x80000000));
1385 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1386 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1387 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1391 void OP_FCD40000 (insn
, extension
)
1392 unsigned long insn
, extension
;
1395 unsigned long reg1
, imm
, value
;
1397 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1398 imm
= ((insn
& 0xffff) << 16) + extension
;
1400 State
.regs
[REG_A0
+ REG0_16 (insn
)] = value
;
1403 n
= (value
& 0x80000000);
1405 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1406 && (reg1
& 0x80000000) != (value
& 0x80000000));
1408 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1409 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1410 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1414 void OP_F180 (insn
, extension
)
1415 unsigned long insn
, extension
;
1418 unsigned long reg1
, reg2
, value
;
1420 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1421 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1422 value
= reg2
- reg1
- ((PSW
& PSW_C
) != 0);
1423 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
1426 n
= (value
& 0x80000000);
1428 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1429 && (reg2
& 0x80000000) != (value
& 0x80000000));
1431 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1432 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1433 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1437 void OP_F240 (insn
, extension
)
1438 unsigned long insn
, extension
;
1440 unsigned long long temp
;
1443 temp
= ((signed long)State
.regs
[REG_D0
+ REG0 (insn
)]
1444 * (signed long)State
.regs
[REG_D0
+ REG1 (insn
)]);
1445 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1446 State
.regs
[REG_MDR
] = (temp
& 0xffffffff00000000LL
) >> 32;;
1447 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1448 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1449 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1450 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1454 void OP_F250 (insn
, extension
)
1455 unsigned long insn
, extension
;
1457 unsigned long long temp
;
1460 temp
= (State
.regs
[REG_D0
+ REG0 (insn
)]
1461 * State
.regs
[REG_D0
+ REG1 (insn
)]);
1462 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1463 State
.regs
[REG_MDR
] = (temp
& 0xffffffff00000000LL
) >> 32;
1464 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1465 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1466 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1467 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1471 void OP_F260 (insn
, extension
)
1472 unsigned long insn
, extension
;
1477 temp
= State
.regs
[REG_MDR
];
1479 temp
|= State
.regs
[REG_D0
+ REG0 (insn
)];
1480 State
.regs
[REG_MDR
] = temp
% (long)State
.regs
[REG_D0
+ REG1 (insn
)];
1481 temp
/= (long)State
.regs
[REG_D0
+ REG1 (insn
)];
1482 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1483 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1484 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1485 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1486 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1490 void OP_F270 (insn
, extension
)
1491 unsigned long insn
, extension
;
1493 unsigned long long temp
;
1496 temp
= State
.regs
[REG_MDR
];
1498 temp
|= State
.regs
[REG_D0
+ REG0 (insn
)];
1499 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ REG1 (insn
)];
1500 temp
/= State
.regs
[REG_D0
+ REG1 (insn
)];
1501 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
& 0xffffffff;
1502 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1503 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1504 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1505 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1509 void OP_40 (insn
, extension
)
1510 unsigned long insn
, extension
;
1513 unsigned int value
, imm
, reg1
;
1515 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1518 State
.regs
[REG_D0
+ REG1 (insn
)] = value
;
1521 n
= (value
& 0x80000000);
1523 v
= ((reg1
& 0x80000000) == (imm
& 0x80000000)
1524 && (reg1
& 0x80000000) != (value
& 0x80000000));
1526 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1527 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1528 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1532 void OP_41 (insn
, extension
)
1533 unsigned long insn
, extension
;
1535 State
.regs
[REG_A0
+ REG1 (insn
)] += 1;
1539 void OP_50 (insn
, extension
)
1540 unsigned long insn
, extension
;
1542 State
.regs
[REG_A0
+ REG0 (insn
)] += 4;
1546 void OP_A000 (insn
, extension
)
1547 unsigned long insn
, extension
;
1550 unsigned long reg1
, imm
, value
;
1552 reg1
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1553 imm
= SEXT8 (insn
& 0xff);
1557 n
= (value
& 0x80000000);
1559 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1560 && (reg1
& 0x80000000) != (value
& 0x80000000));
1562 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1563 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1564 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1568 void OP_A0 (insn
, extension
)
1569 unsigned long insn
, extension
;
1572 unsigned long reg1
, reg2
, value
;
1574 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1575 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1576 value
= reg2
- reg1
;
1579 n
= (value
& 0x80000000);
1581 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1582 && (reg2
& 0x80000000) != (value
& 0x80000000));
1584 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1585 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1586 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1590 void OP_F1A0 (insn
, extension
)
1591 unsigned long insn
, extension
;
1594 unsigned long reg1
, reg2
, value
;
1596 reg1
= State
.regs
[REG_D0
+ REG1 (insn
)];
1597 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1598 value
= reg2
- reg1
;
1601 n
= (value
& 0x80000000);
1603 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1604 && (reg2
& 0x80000000) != (value
& 0x80000000));
1606 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1607 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1608 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1612 void OP_F190 (insn
, extension
)
1613 unsigned long insn
, extension
;
1616 unsigned long reg1
, reg2
, value
;
1618 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1619 reg2
= State
.regs
[REG_D0
+ REG0 (insn
)];
1620 value
= reg2
- reg1
;
1623 n
= (value
& 0x80000000);
1625 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1626 && (reg2
& 0x80000000) != (value
& 0x80000000));
1628 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1629 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1630 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1634 void OP_B000 (insn
, extension
)
1635 unsigned long insn
, extension
;
1638 unsigned long reg1
, imm
, value
;
1640 reg1
= State
.regs
[REG_A0
+ REG0_8 (insn
)];
1645 n
= (value
& 0x80000000);
1647 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1648 && (reg1
& 0x80000000) != (value
& 0x80000000));
1650 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1651 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1652 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1656 void OP_B0 (insn
, extension
)
1657 unsigned long insn
, extension
;
1660 unsigned long reg1
, reg2
, value
;
1662 reg1
= State
.regs
[REG_A0
+ REG1 (insn
)];
1663 reg2
= State
.regs
[REG_A0
+ REG0 (insn
)];
1664 value
= reg2
- reg1
;
1667 n
= (value
& 0x80000000);
1669 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1670 && (reg2
& 0x80000000) != (value
& 0x80000000));
1672 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1673 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1674 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1678 void OP_FAC80000 (insn
, extension
)
1679 unsigned long insn
, extension
;
1682 unsigned long reg1
, imm
, value
;
1684 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1685 imm
= SEXT16 (insn
& 0xffff);
1689 n
= (value
& 0x80000000);
1691 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1692 && (reg1
& 0x80000000) != (value
& 0x80000000));
1694 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1695 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1696 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1700 void OP_FCC80000 (insn
, extension
)
1701 unsigned long insn
, extension
;
1704 unsigned long reg1
, imm
, value
;
1706 reg1
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1707 imm
= ((insn
& 0xffff) << 16) + extension
;
1711 n
= (value
& 0x80000000);
1713 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1714 && (reg1
& 0x80000000) != (value
& 0x80000000));
1716 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1717 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1718 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1722 void OP_FAD80000 (insn
, extension
)
1723 unsigned long insn
, extension
;
1726 unsigned long reg1
, imm
, value
;
1728 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1729 imm
= insn
& 0xffff;
1733 n
= (value
& 0x80000000);
1735 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1736 && (reg1
& 0x80000000) != (value
& 0x80000000));
1738 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1739 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1740 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1744 void OP_FCD80000 (insn
, extension
)
1745 unsigned long insn
, extension
;
1748 unsigned long reg1
, imm
, value
;
1750 reg1
= State
.regs
[REG_A0
+ REG0_16 (insn
)];
1751 imm
= ((insn
& 0xffff) << 16) + extension
;
1755 n
= (value
& 0x80000000);
1757 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1758 && (reg1
& 0x80000000) != (value
& 0x80000000));
1760 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1761 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1762 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1766 void OP_F200 (insn
, extension
)
1767 unsigned long insn
, extension
;
1771 State
.regs
[REG_D0
+ REG0 (insn
)] &= State
.regs
[REG_D0
+ REG1 (insn
)];
1772 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1773 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1774 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1775 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1779 void OP_F8E000 (insn
, extension
)
1780 unsigned long insn
, extension
;
1784 State
.regs
[REG_D0
+ REG0_8 (insn
)] &= (insn
& 0xff);
1785 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
1786 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
1787 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1788 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1792 void OP_FAE00000 (insn
, extension
)
1793 unsigned long insn
, extension
;
1797 State
.regs
[REG_D0
+ REG0_16 (insn
)] &= (insn
& 0xffff);
1798 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1799 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1800 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1801 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1805 void OP_FCE00000 (insn
, extension
)
1806 unsigned long insn
, extension
;
1810 State
.regs
[REG_D0
+ REG0_16 (insn
)]
1811 &= ((insn
& 0xffff) << 16) + extension
;
1812 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1813 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1814 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1815 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1818 /* and imm16, psw */
1819 void OP_FAFC0000 (insn
, extension
)
1820 unsigned long insn
, extension
;
1822 PSW
&= (insn
& 0xffff);
1826 void OP_F210 (insn
, extension
)
1827 unsigned long insn
, extension
;
1831 State
.regs
[REG_D0
+ REG0 (insn
)] |= State
.regs
[REG_D0
+ REG1 (insn
)];
1832 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1833 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1834 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1835 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1839 void OP_F8E400 (insn
, extension
)
1840 unsigned long insn
, extension
;
1844 State
.regs
[REG_D0
+ REG0_8 (insn
)] |= insn
& 0xff;
1845 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
1846 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
1847 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1848 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1852 void OP_FAE40000 (insn
, extension
)
1853 unsigned long insn
, extension
;
1857 State
.regs
[REG_D0
+ REG0_16 (insn
)] |= insn
& 0xffff;
1858 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1859 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1860 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1861 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1865 void OP_FCE40000 (insn
, extension
)
1866 unsigned long insn
, extension
;
1870 State
.regs
[REG_D0
+ REG0_16 (insn
)]
1871 |= ((insn
& 0xffff) << 16) + extension
;
1872 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1873 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1874 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1875 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1879 void OP_FAFD0000 (insn
, extension
)
1880 unsigned long insn
, extension
;
1882 PSW
|= (insn
& 0xffff);
1886 void OP_F220 (insn
, extension
)
1887 unsigned long insn
, extension
;
1891 State
.regs
[REG_D0
+ REG0 (insn
)] ^= State
.regs
[REG_D0
+ REG1 (insn
)];
1892 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1893 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1894 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1895 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1899 void OP_FAE80000 (insn
, extension
)
1900 unsigned long insn
, extension
;
1904 State
.regs
[REG_D0
+ REG0_16 (insn
)] ^= insn
& 0xffff;
1905 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1906 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1907 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1908 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1912 void OP_FCE80000 (insn
, extension
)
1913 unsigned long insn
, extension
;
1917 State
.regs
[REG_D0
+ REG0_16 (insn
)]
1918 ^= ((insn
& 0xffff) << 16) + extension
;
1919 z
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] == 0);
1920 n
= (State
.regs
[REG_D0
+ REG0_16 (insn
)] & 0x80000000) != 0;
1921 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1922 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1926 void OP_F230 (insn
, extension
)
1927 unsigned long insn
, extension
;
1931 State
.regs
[REG_D0
+ REG0 (insn
)] = ~State
.regs
[REG_D0
+ REG0 (insn
)];
1932 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
1933 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
1934 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1935 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1939 void OP_F8EC00 (insn
, extension
)
1940 unsigned long insn
, extension
;
1945 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
1946 temp
&= (insn
& 0xff);
1947 n
= (temp
& 0x80000000) != 0;
1949 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1950 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1953 /* btst imm16, dn */
1954 void OP_FAEC0000 (insn
, extension
)
1955 unsigned long insn
, extension
;
1960 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1961 temp
&= (insn
& 0xffff);
1962 n
= (temp
& 0x80000000) != 0;
1964 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1965 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1968 /* btst imm32, dn */
1969 void OP_FCEC0000 (insn
, extension
)
1970 unsigned long insn
, extension
;
1975 temp
= State
.regs
[REG_D0
+ REG0_16 (insn
)];
1976 temp
&= ((insn
& 0xffff) << 16) + extension
;
1977 n
= (temp
& 0x80000000) != 0;
1979 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1980 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1983 /* btst imm8,(abs32) */
1984 void OP_FE020000 (insn
, extension
)
1985 unsigned long insn
, extension
;
1990 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
1991 temp
&= (extension
& 0xff);
1992 n
= (temp
& 0x80000000) != 0;
1994 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1995 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1998 /* btst imm8,(d8,an) */
1999 void OP_FAF80000 (insn
, extension
)
2000 unsigned long insn
, extension
;
2005 temp
= load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2006 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
2007 temp
&= (insn
& 0xff);
2008 n
= (temp
& 0x80000000) != 0;
2010 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2011 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
2015 void OP_F080 (insn
, extension
)
2016 unsigned long insn
, extension
;
2021 temp
= load_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 1);
2022 z
= (temp
& State
.regs
[REG_D0
+ REG1 (insn
)]) == 0;
2023 temp
|= State
.regs
[REG_D0
+ REG1 (insn
)];
2024 store_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 1, temp
);
2025 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2026 PSW
|= (z
? PSW_Z
: 0);
2029 /* bset imm8, (abs32) */
2030 void OP_FE000000 (insn
, extension
)
2031 unsigned long insn
, extension
;
2036 temp
= load_mem (((insn
& 0xffff) << 16 | (extension
>> 8)), 1);
2037 z
= (temp
& (extension
& 0xff)) == 0;
2038 temp
|= (extension
& 0xff);
2039 store_mem ((((insn
& 0xffff) << 16) | (extension
>> 8)), 1, temp
);
2040 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2041 PSW
|= (z
? PSW_Z
: 0);
2044 /* bset imm8,(d8,an) */
2045 void OP_FAF00000 (insn
, extension
)
2046 unsigned long insn
, extension
;
2051 temp
= load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2052 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
2053 z
= (temp
& (insn
& 0xff)) == 0;
2054 temp
|= (insn
& 0xff);
2055 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2056 + SEXT8 ((insn
& 0xff00) >> 8)), 1, temp
);
2057 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2058 PSW
|= (z
? PSW_Z
: 0);
2062 void OP_F090 (insn
, extension
)
2063 unsigned long insn
, extension
;
2068 temp
= load_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 1);
2069 z
= (temp
& State
.regs
[REG_D0
+ REG1 (insn
)]) == 0;
2070 temp
= temp
& ~State
.regs
[REG_D0
+ REG1 (insn
)];
2071 store_mem (State
.regs
[REG_A0
+ REG0 (insn
)], 1, temp
);
2072 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2073 PSW
|= (z
? PSW_Z
: 0);
2076 /* bclr imm8, (abs32) */
2077 void OP_FE010000 (insn
, extension
)
2078 unsigned long insn
, extension
;
2083 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
2084 z
= (temp
& (extension
& 0xff)) == 0;
2085 temp
= temp
& ~(extension
& 0xff);
2086 store_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1, temp
);
2087 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2088 PSW
|= (z
? PSW_Z
: 0);
2091 /* bclr imm8,(d8,an) */
2092 void OP_FAF40000 (insn
, extension
)
2093 unsigned long insn
, extension
;
2098 temp
= load_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2099 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
2100 z
= (temp
& (insn
& 0xff)) == 0;
2101 temp
= temp
& ~(insn
& 0xff);
2102 store_mem ((State
.regs
[REG_A0
+ REG0_16 (insn
)]
2103 + SEXT8 ((insn
& 0xff00) >> 8)), 1, temp
);
2104 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2105 PSW
|= (z
? PSW_Z
: 0);
2109 void OP_F2B0 (insn
, extension
)
2110 unsigned long insn
, extension
;
2115 temp
= State
.regs
[REG_D0
+ REG0 (insn
)];
2117 temp
>>= State
.regs
[REG_D0
+ REG1 (insn
)];
2118 State
.regs
[REG_D0
+ REG0 (insn
)] = temp
;
2119 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2120 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2121 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2122 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2126 void OP_F8C800 (insn
, extension
)
2127 unsigned long insn
, extension
;
2132 temp
= State
.regs
[REG_D0
+ REG0_8 (insn
)];
2134 temp
>>= (insn
& 0xff);
2135 State
.regs
[REG_D0
+ REG0_8 (insn
)] = temp
;
2136 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
2137 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
2138 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2139 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2143 void OP_F2A0 (insn
, extension
)
2144 unsigned long insn
, extension
;
2148 c
= State
.regs
[REG_D0
+ REG0 (insn
)] & 1;
2149 State
.regs
[REG_D0
+ REG0 (insn
)]
2150 >>= State
.regs
[REG_D0
+ REG1 (insn
)];
2151 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2152 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2153 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2154 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2158 void OP_F8C400 (insn
, extension
)
2159 unsigned long insn
, extension
;
2163 c
= State
.regs
[REG_D0
+ REG0_8 (insn
)] & 1;
2164 State
.regs
[REG_D0
+ REG0_8 (insn
)] >>= (insn
& 0xff);
2165 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
2166 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
2167 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2168 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2172 void OP_F290 (insn
, extension
)
2173 unsigned long insn
, extension
;
2177 State
.regs
[REG_D0
+ REG0 (insn
)]
2178 <<= State
.regs
[REG_D0
+ REG1 (insn
)];
2179 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2180 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2181 PSW
&= ~(PSW_Z
| PSW_N
);
2182 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2186 void OP_F8C000 (insn
, extension
)
2187 unsigned long insn
, extension
;
2191 State
.regs
[REG_D0
+ REG0_8 (insn
)] <<= (insn
& 0xff);
2192 z
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] == 0);
2193 n
= (State
.regs
[REG_D0
+ REG0_8 (insn
)] & 0x80000000) != 0;
2194 PSW
&= ~(PSW_Z
| PSW_N
);
2195 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2199 void OP_54 (insn
, extension
)
2200 unsigned long insn
, extension
;
2204 State
.regs
[REG_D0
+ REG0 (insn
)] <<= 2;
2205 z
= (State
.regs
[REG_D0
+ REG0 (insn
)] == 0);
2206 n
= (State
.regs
[REG_D0
+ REG0 (insn
)] & 0x80000000) != 0;
2207 PSW
&= ~(PSW_Z
| PSW_N
);
2208 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2212 void OP_F284 (insn
, extension
)
2213 unsigned long insn
, extension
;
2215 unsigned long value
;
2218 value
= State
.regs
[REG_D0
+ REG0 (insn
)];
2222 value
|= ((PSW
& PSW_C
) != 0) ? 0x80000000 : 0;
2223 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
2225 n
= (value
& 0x80000000) != 0;
2226 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2227 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2231 void OP_F280 (insn
, extension
)
2232 unsigned long insn
, extension
;
2234 unsigned long value
;
2237 value
= State
.regs
[REG_D0
+ REG0 (insn
)];
2238 c
= (value
& 0x80000000) ? 1 : 0;
2241 value
|= ((PSW
& PSW_C
) != 0);
2242 State
.regs
[REG_D0
+ REG0 (insn
)] = value
;
2244 n
= (value
& 0x80000000) != 0;
2245 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2246 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2250 void OP_C800 (insn
, extension
)
2251 unsigned long insn
, extension
;
2253 /* The dispatching code will add 2 after we return, so
2254 we subtract two here to make things right. */
2256 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2260 void OP_C900 (insn
, extension
)
2261 unsigned long insn
, extension
;
2263 /* The dispatching code will add 2 after we return, so
2264 we subtract two here to make things right. */
2266 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2270 void OP_C100 (insn
, extension
)
2271 unsigned long insn
, extension
;
2273 /* The dispatching code will add 2 after we return, so
2274 we subtract two here to make things right. */
2276 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))))
2277 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2281 void OP_C200 (insn
, extension
)
2282 unsigned long insn
, extension
;
2284 /* The dispatching code will add 2 after we return, so
2285 we subtract two here to make things right. */
2286 if (!(((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2287 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2291 void OP_C300 (insn
, extension
)
2292 unsigned long insn
, extension
;
2294 /* The dispatching code will add 2 after we return, so
2295 we subtract two here to make things right. */
2297 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2298 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2302 void OP_C000 (insn
, extension
)
2303 unsigned long insn
, extension
;
2305 /* The dispatching code will add 2 after we return, so
2306 we subtract two here to make things right. */
2307 if (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))
2308 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2312 void OP_C500 (insn
, extension
)
2313 unsigned long insn
, extension
;
2315 /* The dispatching code will add 2 after we return, so
2316 we subtract two here to make things right. */
2317 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2318 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2322 void OP_C600 (insn
, extension
)
2323 unsigned long insn
, extension
;
2325 /* The dispatching code will add 2 after we return, so
2326 we subtract two here to make things right. */
2328 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2332 void OP_C700 (insn
, extension
)
2333 unsigned long insn
, extension
;
2335 /* The dispatching code will add 2 after we return, so
2336 we subtract two here to make things right. */
2337 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2338 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2342 void OP_C400 (insn
, extension
)
2343 unsigned long insn
, extension
;
2345 /* The dispatching code will add 2 after we return, so
2346 we subtract two here to make things right. */
2348 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2352 void OP_F8E800 (insn
, extension
)
2353 unsigned long insn
, extension
;
2355 /* The dispatching code will add 3 after we return, so
2356 we subtract two here to make things right. */
2358 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2362 void OP_F8E900 (insn
, extension
)
2363 unsigned long insn
, extension
;
2365 /* The dispatching code will add 3 after we return, so
2366 we subtract two here to make things right. */
2368 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2372 void OP_F8EA00 (insn
, extension
)
2373 unsigned long insn
, extension
;
2375 /* The dispatching code will add 3 after we return, so
2376 we subtract two here to make things right. */
2378 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2382 void OP_F8EB00 (insn
, extension
)
2383 unsigned long insn
, extension
;
2385 /* The dispatching code will add 3 after we return, so
2386 we subtract two here to make things right. */
2388 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 3;
2392 void OP_CA00 (insn
, extension
)
2393 unsigned long insn
, extension
;
2395 /* The dispatching code will add 2 after we return, so
2396 we subtract two here to make things right. */
2397 State
.regs
[REG_PC
] += SEXT8 (insn
& 0xff) - 2;
2401 void OP_D8 (insn
, extension
)
2402 unsigned long insn
, extension
;
2404 /* The dispatching code will add 1 after we return, so
2405 we subtract one here to make things right. */
2407 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2411 void OP_D9 (insn
, extension
)
2412 unsigned long insn
, extension
;
2414 /* The dispatching code will add 1 after we return, so
2415 we subtract one here to make things right. */
2417 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2421 void OP_D1 (insn
, extension
)
2422 unsigned long insn
, extension
;
2424 /* The dispatching code will add 1 after we return, so
2425 we subtract one here to make things right. */
2427 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))))
2428 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2432 void OP_D2 (insn
, extension
)
2433 unsigned long insn
, extension
;
2435 /* The dispatching code will add 1 after we return, so
2436 we subtract one here to make things right. */
2437 if (!(((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2438 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2442 void OP_D3 (insn
, extension
)
2443 unsigned long insn
, extension
;
2445 /* The dispatching code will add 1 after we return, so
2446 we subtract one here to make things right. */
2448 || (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0)))
2449 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2453 void OP_D0 (insn
, extension
)
2454 unsigned long insn
, extension
;
2456 /* The dispatching code will add 1 after we return, so
2457 we subtract one here to make things right. */
2458 if (((PSW
& PSW_N
) != 0) ^ ((PSW
& PSW_V
) != 0))
2459 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2463 void OP_D5 (insn
, extension
)
2464 unsigned long insn
, extension
;
2466 /* The dispatching code will add 1 after we return, so
2467 we subtract one here to make things right. */
2468 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2469 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2473 void OP_D6 (insn
, extension
)
2474 unsigned long insn
, extension
;
2476 /* The dispatching code will add 1 after we return, so
2477 we subtract one here to make things right. */
2479 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2483 void OP_D7 (insn
, extension
)
2484 unsigned long insn
, extension
;
2486 /* The dispatching code will add 1 after we return, so
2487 we subtract one here to make things right. */
2488 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2489 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2493 void OP_D4 (insn
, extension
)
2494 unsigned long insn
, extension
;
2496 /* The dispatching code will add 1 after we return, so
2497 we subtract one here to make things right. */
2499 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2503 void OP_DA (insn
, extension
)
2504 unsigned long insn
, extension
;
2506 State
.regs
[REG_PC
] = State
.regs
[REG_LAR
] - 4 - 1;
2510 void OP_DB (insn
, extension
)
2511 unsigned long insn
, extension
;
2513 State
.regs
[REG_LIR
] = load_mem_big (State
.regs
[REG_PC
] + 1, 4);
2514 State
.regs
[REG_LAR
] = State
.regs
[REG_PC
] + 5;
2518 void OP_F0F4 (insn
, extension
)
2519 unsigned long insn
, extension
;
2521 State
.regs
[REG_PC
] = State
.regs
[REG_A0
+ REG0 (insn
)] - 2;
2525 void OP_CC0000 (insn
, extension
)
2526 unsigned long insn
, extension
;
2528 State
.regs
[REG_PC
] += SEXT16 (insn
& 0xffff) - 3;
2532 void OP_DC000000 (insn
, extension
)
2533 unsigned long insn
, extension
;
2535 State
.regs
[REG_PC
] += (((insn
& 0xffffff) << 8) + extension
) - 5;
2538 /* call label:16,reg_list,imm8 */
2539 void OP_CD000000 (insn
, extension
)
2540 unsigned long insn
, extension
;
2542 unsigned int next_pc
, sp
, adjust
;
2545 sp
= State
.regs
[REG_SP
];
2546 next_pc
= State
.regs
[REG_PC
] + 2;
2547 State
.mem
[sp
] = next_pc
& 0xff;
2548 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2549 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2550 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2558 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2564 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2570 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2576 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2582 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2584 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2586 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2588 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2590 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2592 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2594 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2598 /* And make sure to update the stack pointer. */
2599 State
.regs
[REG_SP
] -= extension
;
2600 State
.regs
[REG_MDR
] = next_pc
;
2601 State
.regs
[REG_PC
] += SEXT16 ((insn
& 0xffff00) >> 8) - 5;
2604 /* call label:32,reg_list,imm8*/
2605 void OP_DD000000 (insn
, extension
)
2606 unsigned long insn
, extension
;
2608 unsigned int next_pc
, sp
, adjust
;
2611 sp
= State
.regs
[REG_SP
];
2612 next_pc
= State
.regs
[REG_PC
] + 2;
2613 State
.mem
[sp
] = next_pc
& 0xff;
2614 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2615 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2616 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2618 mask
= (extension
& 0xff00) >> 8;
2624 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2630 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2636 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2642 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2648 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2650 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2652 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2654 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2656 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2658 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2660 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2664 /* And make sure to update the stack pointer. */
2665 State
.regs
[REG_SP
] -= (extension
& 0xff);
2666 State
.regs
[REG_MDR
] = next_pc
;
2667 State
.regs
[REG_PC
] += (((insn
& 0xffffff) << 8) | ((extension
& 0xff0000) >> 16)) - 7;
2671 void OP_F0F0 (insn
, extension
)
2672 unsigned long insn
, extension
;
2674 unsigned int next_pc
, sp
;
2676 sp
= State
.regs
[REG_SP
];
2677 next_pc
= State
.regs
[REG_PC
] + 2;
2678 State
.mem
[sp
] = next_pc
& 0xff;
2679 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2680 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2681 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2682 State
.regs
[REG_MDR
] = next_pc
;
2683 State
.regs
[REG_PC
] = State
.regs
[REG_A0
+ REG0 (insn
)] - 2;
2686 /* calls label:16 */
2687 void OP_FAFF0000 (insn
, extension
)
2688 unsigned long insn
, extension
;
2690 unsigned int next_pc
, sp
;
2692 sp
= State
.regs
[REG_SP
];
2693 next_pc
= State
.regs
[REG_PC
] + 4;
2694 State
.mem
[sp
] = next_pc
& 0xff;
2695 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2696 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2697 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2698 State
.regs
[REG_MDR
] = next_pc
;
2699 State
.regs
[REG_PC
] += SEXT16 (insn
& 0xffff) - 4;
2702 /* calls label:32 */
2703 void OP_FCFF0000 (insn
, extension
)
2704 unsigned long insn
, extension
;
2706 unsigned int next_pc
, sp
;
2708 sp
= State
.regs
[REG_SP
];
2709 next_pc
= State
.regs
[REG_PC
] + 6;
2710 State
.mem
[sp
] = next_pc
& 0xff;
2711 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2712 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2713 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2714 State
.regs
[REG_MDR
] = next_pc
;
2715 State
.regs
[REG_PC
] += (((insn
& 0xffff) << 16) + extension
) - 6;
2718 /* ret reg_list, imm8 */
2719 void OP_DF0000 (insn
, extension
)
2720 unsigned long insn
, extension
;
2725 State
.regs
[REG_SP
] += insn
& 0xff;
2726 sp
= State
.regs
[REG_SP
];
2728 mask
= (insn
& 0xff00) >> 8;
2733 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2735 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2737 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2739 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2741 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2743 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2745 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2751 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2757 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2763 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2769 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2773 /* And make sure to update the stack pointer. */
2774 State
.regs
[REG_SP
] = sp
;
2776 /* Restore the PC value. */
2777 State
.regs
[REG_PC
] = (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2778 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2779 State
.regs
[REG_PC
] -= 3;
2782 /* retf reg_list,imm8 */
2783 void OP_DE0000 (insn
, extension
)
2784 unsigned long insn
, extension
;
2789 sp
= State
.regs
[REG_SP
] + (insn
& 0xff);
2790 State
.regs
[REG_SP
] = sp
;
2791 State
.regs
[REG_PC
] = State
.regs
[REG_MDR
] - 3;
2793 sp
= State
.regs
[REG_SP
];
2795 mask
= (insn
& 0xff00) >> 8;
2800 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2802 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2804 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2806 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2808 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2810 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2812 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2818 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2824 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2830 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2836 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2840 /* And make sure to update the stack pointer. */
2841 State
.regs
[REG_SP
] = sp
;
2845 void OP_F0FC (insn
, extension
)
2846 unsigned long insn
, extension
;
2850 sp
= State
.regs
[REG_SP
];
2851 State
.regs
[REG_PC
] = (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2852 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2853 State
.regs
[REG_PC
] -= 2;
2857 void OP_F0FD (insn
, extension
)
2858 unsigned long insn
, extension
;
2860 unsigned int sp
, next_pc
;
2862 PSW
= State
.mem
[sp
] | (State
.mem
[sp
+ 1] << 8);
2863 State
.regs
[REG_PC
] = (State
.mem
[sp
+4] | (State
.mem
[sp
+5] << 8)
2864 | (State
.mem
[sp
+6] << 16) | (State
.mem
[sp
+7] << 24));
2865 State
.regs
[REG_SP
] += 8;
2869 void OP_F0FE (insn
, extension
)
2870 unsigned long insn
, extension
;
2872 unsigned int sp
, next_pc
;
2874 sp
= State
.regs
[REG_SP
];
2875 next_pc
= State
.regs
[REG_PC
] + 2;
2876 State
.mem
[sp
] = next_pc
& 0xff;
2877 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2878 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2879 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2880 State
.regs
[REG_PC
] = 0x40000010 - 2;
2885 void OP_F020 (insn
, extension
)
2886 unsigned long insn
, extension
;
2888 /* We use this for simulated system calls; we may need to change
2889 it to a reserved instruction if we conflict with uses at
2891 int save_errno
= errno
;
2894 /* Registers passed to trap 0 */
2896 /* Function number. */
2897 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2900 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2901 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2902 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2904 /* Registers set by trap 0 */
2906 #define RETVAL State.regs[0] /* return value */
2907 #define RETERR State.regs[1] /* return error code */
2909 /* Turn a pointer in a register into a pointer into real memory. */
2911 #define MEMPTR(x) (State.mem + x)
2915 #if !defined(__GO32__) && !defined(_WIN32)
2920 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2921 (char **)MEMPTR (PARM3
));
2924 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2929 RETVAL
= mn10300_callback
->read (mn10300_callback
, PARM1
,
2930 MEMPTR (PARM2
), PARM3
);
2934 RETVAL
= (int)mn10300_callback
->write_stdout (mn10300_callback
,
2935 MEMPTR (PARM2
), PARM3
);
2937 RETVAL
= (int)mn10300_callback
->write (mn10300_callback
, PARM1
,
2938 MEMPTR (PARM2
), PARM3
);
2941 RETVAL
= mn10300_callback
->lseek (mn10300_callback
, PARM1
, PARM2
, PARM3
);
2944 RETVAL
= mn10300_callback
->close (mn10300_callback
, PARM1
);
2947 RETVAL
= mn10300_callback
->open (mn10300_callback
, MEMPTR (PARM1
), PARM2
);
2950 /* EXIT - caller can look in PARM1 to work out the
2952 if (PARM1
== 0xdead || PARM1
== 0x1)
2953 State
.exception
= SIGABRT
;
2955 State
.exception
= SIGQUIT
;
2958 case SYS_stat
: /* added at hmsi */
2959 /* stat system call */
2961 struct stat host_stat
;
2964 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2968 /* Just wild-assed guesses. */
2969 store_mem (buf
, 2, host_stat
.st_dev
);
2970 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2971 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2972 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2973 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2974 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2975 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2976 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2977 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2978 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2979 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2984 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2987 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2990 RETVAL
= time (MEMPTR (PARM1
));
2995 RETVAL
= times (&tms
);
2996 store_mem (PARM1
, 4, tms
.tms_utime
);
2997 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2998 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2999 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
3002 case SYS_gettimeofday
:
3006 RETVAL
= gettimeofday (&t
, &tz
);
3007 store_mem (PARM1
, 4, t
.tv_sec
);
3008 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
3009 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
3010 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
3014 /* Cast the second argument to void *, to avoid type mismatch
3015 if a prototype is present. */
3016 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
3026 void OP_F0FF (insn
, extension
)
3027 unsigned long insn
, extension
;
3033 void OP_CB (insn
, extension
)
3034 unsigned long insn
, extension
;
3039 void OP_F500 (insn
, extension
)
3040 unsigned long insn
, extension
;
3046 void OP_F6F0 (insn
, extension
)
3047 unsigned long insn
, extension
;
3053 void OP_F600 (insn
, extension
)
3054 unsigned long insn
, extension
;
3060 void OP_F90000 (insn
, extension
)
3061 unsigned long insn
, extension
;
3067 void OP_FB000000 (insn
, extension
)
3068 unsigned long insn
, extension
;
3074 void OP_FD000000 (insn
, extension
)
3075 unsigned long insn
, extension
;
3081 void OP_F610 (insn
, extension
)
3082 unsigned long insn
, extension
;
3088 void OP_F91400 (insn
, extension
)
3089 unsigned long insn
, extension
;
3095 void OP_FB140000 (insn
, extension
)
3096 unsigned long insn
, extension
;
3102 void OP_FD140000 (insn
, extension
)
3103 unsigned long insn
, extension
;
3109 void OP_F640 (insn
, extension
)
3110 unsigned long insn
, extension
;
3116 void OP_F650 (insn
, extension
)
3117 unsigned long insn
, extension
;
3123 void OP_F670 (insn
, extension
)
3124 unsigned long insn
, extension
;
3131 OP_FF (insn
, extension
)
3132 unsigned long insn
, extension
;
3134 State
.exception
= SIGTRAP
;