7 #include "mn10300_sim.h"
9 #include "sys/syscall.h"
13 #include <sys/times.h>
21 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
22 static void trace_output
PARAMS ((enum op_types result
));
23 static int init_text_p
= 0;
24 static asection
*text
;
25 static bfd_vma text_start
;
26 static bfd_vma text_end
;
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
34 #define SIZE_OPERANDS 16
38 #define SIZE_VALUES 11
42 #define SIZE_LOCATION 40
46 trace_input (name
, type
, size
)
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
68 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = SEXT8 (insn
& 0xff);
74 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
80 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)] = State
.regs
[REG_D0
+ (insn
& 0x3)];
86 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
92 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = insn
& 0xff;
98 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
104 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_SP
];
110 State
.regs
[REG_SP
] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
116 State
.regs
[REG_D0
+ (insn
& 0x3)] = PSW
;
122 PSW
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
128 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_MDR
];
134 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
140 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
141 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
144 /* mov (d8,am), dn */
147 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
148 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
149 + SEXT8 (insn
& 0xff)), 4);
152 /* mov (d16,am), dn */
155 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
156 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
157 + SEXT16 (insn
& 0xffff)), 4);
160 /* mov (d32,am), dn */
163 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
164 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
165 + ((insn
& 0xffff) << 16) | extension
), 4);
168 /* mov (d8,sp), dn */
171 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
172 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
175 /* mov (d16,sp), dn */
178 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
179 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
182 /* mov (d32,sp), dn */
185 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
186 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
189 /* mov (di,am), dn */
192 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
193 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
194 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
197 /* mov (abs16), dn */
200 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 4);
203 /* mov (abs32), dn */
206 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
207 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
213 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]
214 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
217 /* mov (d8,am), an */
220 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]
221 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
222 + SEXT8 (insn
& 0xff)), 4);
225 /* mov (d16,am), an */
228 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]
229 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
230 + SEXT16 (insn
& 0xffff)), 4);
233 /* mov (d32,am), an */
236 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]
237 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
238 + ((insn
& 0xffff) << 16) + extension
), 4);
241 /* mov (d8,sp), an */
244 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
245 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
248 /* mov (d16,sp), an */
251 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
252 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
255 /* mov (d32,sp), an */
258 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
259 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
262 /* mov (di,am), an */
265 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
266 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
267 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
270 /* mov (abs16), an */
273 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 4);
276 /* mov (abs32), an */
279 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
280 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
283 /* mov (d8,am), sp */
287 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
288 + SEXT8 (insn
& 0xff)), 4);
294 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
295 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
298 /* mov dm, (d8,an) */
301 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
302 + SEXT8 (insn
& 0xff)), 4,
303 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
306 /* mov dm (d16,an) */
309 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
310 + SEXT16 (insn
& 0xffff)), 4,
311 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
314 /* mov dm (d32,an) */
317 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
318 + ((insn
& 0xffff) << 16) + extension
), 4,
319 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
322 /* mov dm, (d8,sp) */
325 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
326 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
329 /* mov dm, (d16,sp) */
332 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
333 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
336 /* mov dm, (d32,sp) */
339 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
340 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
343 /* mov dm, (di,an) */
346 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
347 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
348 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
351 /* mov dm, (abs16) */
354 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
357 /* mov dm, (abs32) */
360 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
366 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
367 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]);
370 /* mov am, (d8,an) */
373 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
374 + SEXT8 (insn
& 0xff)), 4,
375 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
378 /* mov am, (d16,an) */
381 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 17)]
382 + SEXT16 (insn
& 0xffff)), 4,
383 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
386 /* mov am, (d32,an) */
389 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 17)]
390 + ((insn
& 0xffff) << 16) + extension
), 4,
391 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
394 /* mov am, (d8,sp) */
397 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
398 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
401 /* mov am, (d16,sp) */
404 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
405 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
408 /* mov am, (d32,sp) */
411 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
412 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
415 /* mov am, (di,an) */
418 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
419 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
420 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]);
423 /* mov am, (abs16) */
426 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
429 /* mov am, (abs32) */
432 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
435 /* mov sp, (d8,an) */
438 store_mem (State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] + SEXT8 (insn
& 0xff),
439 4, State
.regs
[REG_SP
]);
447 value
= SEXT16 (insn
& 0xffff);
448 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
456 value
= (insn
& 0xffff) << 16 | extension
;
457 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
465 value
= insn
& 0xffff;
466 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
474 value
= (insn
& 0xffff) << 16 | extension
;
475 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
481 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
482 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 1);
485 /* movbu (d8,am), dn */
488 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
489 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
490 + SEXT8 (insn
& 0xff)), 1);
493 /* movbu (d16,am), dn */
496 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
497 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
498 + SEXT16 (insn
& 0xffff)), 1);
501 /* movbu (d32,am), dn */
504 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
505 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
506 + ((insn
& 0xffff) << 16) + extension
), 1);
509 /* movbu (d8,sp), dn */
512 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
513 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 1);
516 /* movbu (d16,sp), dn */
519 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
520 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 1);
523 /* movbu (d32,sp), dn */
526 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
527 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 1);
530 /* movbu (di,am), dn */
533 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
534 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
535 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1);
538 /* movbu (abs16), dn */
541 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 1);
544 /* movbu (abs32), dn */
547 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
548 = load_mem ((((insn
& 0xffff) << 16) + extension
), 1);
554 store_mem (State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)], 1,
555 State
.regs
[REG_D0
+ (insn
& 0x3)]);
558 /* movbu dm, (d8,an) */
561 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
562 + SEXT8 (insn
& 0xff)), 1,
563 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
566 /* movbu dm, (d16,an) */
569 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
570 + SEXT16 (insn
& 0xffff)), 1,
571 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
574 /* movbu dm, (d32,an) */
577 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
578 + ((insn
& 0xffff) << 16) + extension
), 1,
579 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
582 /* movbu dm, (d8,sp) */
585 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 1,
586 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
589 /* movbu dm, (d16,sp) */
592 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
593 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
596 /* movbu dm (d32,sp) */
599 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
600 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
603 /* movbu dm, (di,an) */
606 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
607 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1,
608 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
611 /* movbu dm, (abs16) */
614 store_mem ((insn
& 0xffff), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
617 /* movbu dm, (abs32) */
620 store_mem ((((insn
& 0xffff) << 16) + extension
), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
626 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
627 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 2);
630 /* movhu (d8,am), dn */
633 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
634 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
635 + SEXT8 (insn
& 0xff)), 2);
638 /* movhu (d16,am), dn */
641 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
642 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
643 + SEXT16 (insn
& 0xffff)), 2);
646 /* movhu (d32,am), dn */
649 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
650 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
651 + ((insn
& 0xffff) << 16) + extension
), 2);
654 /* movhu (d8,sp) dn */
657 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
658 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 2);
661 /* movhu (d16,sp), dn */
664 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
665 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 2);
668 /* movhu (d32,sp), dn */
671 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
672 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2);
675 /* movhu (di,am), dn */
678 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
679 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
680 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2);
683 /* movhu (abs16), dn */
686 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 2);
689 /* movhu (abs32), dn */
692 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
693 = load_mem ((((insn
& 0xffff) << 16) + extension
), 2);
699 store_mem (State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)], 2,
700 State
.regs
[REG_D0
+ (insn
& 0x3)]);
703 /* movhu dm, (d8,an) */
706 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
707 + SEXT8 (insn
& 0xff)), 2,
708 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
711 /* movhu dm, (d16,an) */
714 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
715 + SEXT16 (insn
& 0xffff)), 2,
716 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
719 /* movhu dm, (d32,an) */
722 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
723 + ((insn
& 0xffff) << 16) + extension
), 2,
724 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
727 /* movhu dm,(d8,sp) */
730 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 2,
731 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
734 /* movhu dm,(d16,sp) */
737 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
738 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
741 /* movhu dm,(d32,sp) */
744 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
745 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
748 /* movhu dm, (di,an) */
751 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
752 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2,
753 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
756 /* movhu dm, (abs16) */
759 store_mem ((insn
& 0xffff), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
762 /* movhu dm, (abs32) */
765 store_mem ((((insn
& 0xffff) << 16) + extension
), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
771 if (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000)
772 State
.regs
[REG_MDR
] = -1;
774 State
.regs
[REG_MDR
] = 0;
780 State
.regs
[REG_D0
+ (insn
& 0x3)] = SEXT8 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
786 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xff;
792 State
.regs
[REG_D0
+ (insn
& 0x3)]
793 = SEXT16 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
799 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xffff;
802 /* movm (sp), reg_list */
805 unsigned long sp
= State
.regs
[REG_SP
];
813 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
815 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
817 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
819 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
821 State
.regs
[REG_A0
] = load_mem (sp
, 4);
823 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
825 State
.regs
[REG_D0
] = load_mem (sp
, 4);
831 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
837 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
843 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
849 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
853 /* And make sure to update the stack pointer. */
854 State
.regs
[REG_SP
] = sp
;
857 /* movm reg_list, (sp) */
860 unsigned long sp
= State
.regs
[REG_SP
];
868 store_mem (sp
, 4, State
.regs
[REG_D0
+ 2]);
874 store_mem (sp
, 4, State
.regs
[REG_D0
+ 3]);
880 store_mem (sp
, 4, State
.regs
[REG_A0
+ 2]);
886 store_mem (sp
, 4, State
.regs
[REG_A0
+ 3]);
892 store_mem (sp
, 4, State
.regs
[REG_D0
]);
894 store_mem (sp
, 4, State
.regs
[REG_D0
+ 1]);
896 store_mem (sp
, 4, State
.regs
[REG_A0
]);
898 store_mem (sp
, 4, State
.regs
[REG_A0
+ 1]);
900 store_mem (sp
, 4, State
.regs
[REG_MDR
]);
902 store_mem (sp
, 4, State
.regs
[REG_LIR
]);
904 store_mem (sp
, 4, State
.regs
[REG_LAR
]);
908 /* And make sure to update the stack pointer. */
909 State
.regs
[REG_SP
] = sp
;
915 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] = 0;
918 PSW
&= ~(PSW_V
| PSW_C
| PSW_N
);
925 unsigned long reg1
, reg2
, value
;
927 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
928 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
930 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
933 n
= (value
& 0x80000000);
935 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
936 && (reg2
& 0x8000000) != (value
& 0x80000000));
938 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
939 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
940 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
947 unsigned long reg1
, reg2
, value
;
949 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
950 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
952 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
955 n
= (value
& 0x80000000);
957 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
958 && (reg2
& 0x8000000) != (value
& 0x80000000));
960 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
961 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
962 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
969 unsigned long reg1
, reg2
, value
;
971 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
972 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
974 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
977 n
= (value
& 0x80000000);
979 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
980 && (reg2
& 0x8000000) != (value
& 0x80000000));
982 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
983 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
984 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
991 unsigned long reg1
, reg2
, value
;
993 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
994 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
996 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
999 n
= (value
& 0x80000000);
1001 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1002 && (reg2
& 0x8000000) != (value
& 0x80000000));
1004 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1005 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1006 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1013 unsigned long reg1
, imm
, value
;
1015 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1016 imm
= SEXT8 (insn
& 0xff);
1018 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = value
;
1021 n
= (value
& 0x80000000);
1023 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1024 && (imm
& 0x8000000) != (value
& 0x80000000));
1026 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1027 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1028 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1035 unsigned long reg1
, imm
, value
;
1037 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)];
1038 imm
= SEXT16 (insn
& 0xffff);
1040 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)] = value
;
1043 n
= (value
& 0x80000000);
1045 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1046 && (imm
& 0x8000000) != (value
& 0x80000000));
1048 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1049 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1050 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1057 unsigned long reg1
, imm
, value
;
1059 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)];
1060 imm
= ((insn
& 0xffff) << 16) | extension
;
1062 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)] = value
;
1065 n
= (value
& 0x80000000);
1067 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1068 && (imm
& 0x8000000) != (value
& 0x80000000));
1070 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1071 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1072 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1079 unsigned long reg1
, imm
, value
;
1081 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1082 imm
= SEXT8 (insn
& 0xff);
1084 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] = value
;
1087 n
= (value
& 0x80000000);
1089 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1090 && (imm
& 0x8000000) != (value
& 0x80000000));
1092 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1093 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1094 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1101 unsigned long reg1
, imm
, value
;
1103 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)];
1104 imm
= SEXT16 (insn
& 0xffff);
1106 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)] = value
;
1109 n
= (value
& 0x80000000);
1111 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1112 && (imm
& 0x8000000) != (value
& 0x80000000));
1114 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1115 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1116 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1123 unsigned long reg1
, imm
, value
;
1125 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)];
1126 imm
= ((insn
& 0xffff) << 16) | extension
;
1128 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)] = value
;
1131 n
= (value
& 0x80000000);
1133 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1134 && (imm
& 0x8000000) != (value
& 0x80000000));
1136 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1137 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1138 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1145 unsigned long reg1
, imm
, value
;
1147 reg1
= State
.regs
[REG_SP
];
1148 imm
= SEXT8 (insn
& 0xff);
1150 State
.regs
[REG_SP
] = value
;
1153 n
= (value
& 0x80000000);
1155 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1156 && (imm
& 0x8000000) != (value
& 0x80000000));
1158 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1159 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1160 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1167 unsigned long reg1
, imm
, value
;
1169 reg1
= State
.regs
[REG_SP
];
1170 imm
= SEXT16 (insn
& 0xffff);
1172 State
.regs
[REG_SP
] = value
;
1175 n
= (value
& 0x80000000);
1177 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1178 && (imm
& 0x8000000) != (value
& 0x80000000));
1180 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1181 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1182 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1189 unsigned long reg1
, imm
, value
;
1191 reg1
= State
.regs
[REG_SP
];
1192 imm
= ((insn
& 0xffff) << 16) | extension
;
1194 State
.regs
[REG_SP
] = value
;
1197 n
= (value
& 0x80000000);
1199 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1200 && (imm
& 0x8000000) != (value
& 0x80000000));
1202 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1203 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1204 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1211 unsigned long reg1
, reg2
, value
;
1213 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1214 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1215 value
= reg1
+ reg2
+ ((PSW
& PSW_C
) != 0);
1216 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1219 n
= (value
& 0x80000000);
1221 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1222 && (reg2
& 0x8000000) != (value
& 0x80000000));
1224 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1225 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1226 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1233 unsigned long reg1
, reg2
, value
;
1235 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1236 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1237 value
= reg2
- reg1
;
1240 n
= (value
& 0x80000000);
1242 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1243 && (reg2
& 0x8000000) != (value
& 0x80000000));
1245 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1246 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1247 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1248 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1255 unsigned long reg1
, reg2
, value
;
1257 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1258 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1259 value
= reg2
- reg1
;
1262 n
= (value
& 0x80000000);
1264 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1265 && (reg2
& 0x8000000) != (value
& 0x80000000));
1267 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1268 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1269 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1270 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1277 unsigned long reg1
, reg2
, value
;
1279 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1280 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1281 value
= reg2
- reg1
;
1284 n
= (value
& 0x80000000);
1286 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1287 && (reg2
& 0x8000000) != (value
& 0x80000000));
1289 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1290 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1291 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1292 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1299 unsigned long reg1
, reg2
, value
;
1301 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1302 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1303 value
= reg2
- reg1
;
1306 n
= (value
& 0x80000000);
1308 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1309 && (reg2
& 0x8000000) != (value
& 0x80000000));
1311 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1312 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1313 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1314 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1321 unsigned long reg1
, imm
, value
;
1323 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)];
1324 imm
= ((insn
& 0xffff) << 16) | extension
;
1328 n
= (value
& 0x80000000);
1330 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1331 && (imm
& 0x8000000) != (value
& 0x80000000));
1333 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1334 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1335 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1336 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)] = value
;
1343 unsigned long reg1
, imm
, value
;
1345 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)];
1346 imm
= ((insn
& 0xffff) << 16) | extension
;
1350 n
= (value
& 0x80000000);
1352 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1353 && (imm
& 0x8000000) != (value
& 0x80000000));
1355 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1356 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1357 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1358 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)] = value
;
1365 unsigned long reg1
, reg2
, value
;
1367 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1368 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1369 value
= reg2
- reg1
- ((PSW
& PSW_C
) != 0);
1372 n
= (value
& 0x80000000);
1374 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1375 && (reg2
& 0x8000000) != (value
& 0x80000000));
1377 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1378 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1379 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1380 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1386 unsigned long long temp
;
1389 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1390 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1391 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1392 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1393 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1394 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1395 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1396 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1402 unsigned long long temp
;
1405 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1406 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1407 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1408 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1409 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1410 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1411 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1412 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1421 temp
= State
.regs
[REG_MDR
];
1423 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1424 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1425 temp
/= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1426 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1427 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1428 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1429 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1430 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1431 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1432 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1433 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1439 unsigned long long temp
;
1442 temp
= State
.regs
[REG_MDR
];
1444 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1445 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1446 temp
/= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1447 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1448 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1449 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1450 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1451 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1452 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1453 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1454 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1460 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] += 1;
1466 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)] += 1;
1472 State
.regs
[REG_A0
+ (insn
& 0x3)] += 4;
1479 unsigned long reg1
, imm
, value
;
1481 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1482 imm
= SEXT8 (insn
& 0xff);
1486 n
= (value
& 0x80000000);
1488 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1489 && (imm
& 0x8000000) != (value
& 0x80000000));
1491 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1492 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1493 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1500 unsigned long reg1
, reg2
, value
;
1502 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1503 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1504 value
= reg2
- reg1
;
1507 n
= (value
& 0x80000000);
1509 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1510 && (reg2
& 0x8000000) != (value
& 0x80000000));
1512 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1513 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1514 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1521 unsigned long reg1
, reg2
, value
;
1523 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1524 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1525 value
= reg2
- reg1
;
1528 n
= (value
& 0x80000000);
1530 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1531 && (reg2
& 0x8000000) != (value
& 0x80000000));
1533 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1534 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1535 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1542 unsigned long reg1
, reg2
, value
;
1544 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1545 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1546 value
= reg2
- reg1
;
1549 n
= (value
& 0x80000000);
1551 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1552 && (reg2
& 0x8000000) != (value
& 0x80000000));
1554 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1555 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1556 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1563 unsigned long reg1
, imm
, value
;
1565 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1570 n
= (value
& 0x80000000);
1572 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1573 && (imm
& 0x8000000) != (value
& 0x80000000));
1575 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1576 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1577 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1584 unsigned long reg1
, reg2
, value
;
1586 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1587 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1588 value
= reg2
- reg1
;
1591 n
= (value
& 0x80000000);
1593 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1594 && (reg2
& 0x8000000) != (value
& 0x80000000));
1596 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1597 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1598 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1605 unsigned long reg1
, imm
, value
;
1607 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)];
1608 imm
= SEXT16 (insn
& 0xffff);
1612 n
= (value
& 0x80000000);
1614 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1615 && (imm
& 0x8000000) != (value
& 0x80000000));
1617 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1618 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1619 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1626 unsigned long reg1
, imm
, value
;
1628 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)];
1629 imm
= ((insn
& 0xffff) << 16) | extension
;
1633 n
= (value
& 0x80000000);
1635 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1636 && (imm
& 0x8000000) != (value
& 0x80000000));
1638 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1639 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1640 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1647 unsigned long reg1
, imm
, value
;
1649 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)];
1650 imm
= insn
& 0xffff;
1654 n
= (value
& 0x80000000);
1656 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1657 && (imm
& 0x8000000) != (value
& 0x80000000));
1659 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1660 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1661 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1668 unsigned long reg1
, imm
, value
;
1670 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)];
1671 imm
= ((insn
& 0xffff) << 16) | extension
;
1675 n
= (value
& 0x80000000);
1677 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1678 && (imm
& 0x8000000) != (value
& 0x80000000));
1680 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1681 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1682 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1690 State
.regs
[REG_D0
+ (insn
& 0x3)] &= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1691 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1692 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1693 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1694 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1702 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] &= (insn
& 0xff);
1703 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
1704 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x8000000) != 0;
1705 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1706 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1714 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] &= (insn
& 0xffff);
1715 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1716 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x8000000) != 0;
1717 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1718 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1726 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1727 &= ((insn
& 0xffff) << 16 | extension
);
1728 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1729 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x8000000) != 0;
1730 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1731 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1734 /* and imm16, psw */
1737 PSW
&= (insn
& 0xffff);
1745 State
.regs
[REG_D0
+ (insn
& 0x3)] |= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1746 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1747 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1748 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1749 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1757 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] |= insn
& 0xff;
1758 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
1759 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x8000000) != 0;
1760 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1761 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1769 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] |= insn
& 0xffff;
1770 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1771 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x8000000) != 0;
1772 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1773 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1781 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1782 |= ((insn
& 0xffff) << 16 | extension
);
1783 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1784 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x8000000) != 0;
1785 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1786 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1792 PSW
|= (insn
& 0xffff);
1800 State
.regs
[REG_D0
+ (insn
& 0x3)] ^= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1801 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1802 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1803 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1804 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1812 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] ^= insn
& 0xffff;
1813 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1814 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x8000000) != 0;
1815 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1816 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1824 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1825 ^= ((insn
& 0xffff) << 16 | extension
);
1826 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1827 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x8000000) != 0;
1828 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1829 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1837 State
.regs
[REG_D0
+ (insn
& 0x3)] = ~State
.regs
[REG_D0
+ (insn
& 0x3)];
1838 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1839 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1840 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1841 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1850 temp
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1851 temp
&= (insn
& 0xff);
1852 n
= (temp
& 0x80000000) != 0;
1854 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1855 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1858 /* btst imm16, dn */
1864 temp
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1865 temp
&= (insn
& 0xffff);
1866 n
= (temp
& 0x80000000) != 0;
1868 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1869 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1872 /* btst imm32, dn */
1878 temp
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1879 temp
&= ((insn
& 0xffff) << 16 | extension
);
1880 n
= (temp
& 0x80000000) != 0;
1882 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1883 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1886 /* btst imm8,(abs32) */
1892 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
1893 temp
&= (extension
& 0xff);
1894 n
= (temp
& 0x80000000) != 0;
1896 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1897 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1900 /* btst imm8,(d8,an) */
1906 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
1907 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
1908 temp
&= (insn
& 0xff);
1909 n
= (temp
& 0x80000000) != 0;
1911 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1912 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1921 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
1922 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
1923 temp
|= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1924 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
1925 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1926 PSW
|= (z
? PSW_Z
: 0);
1929 /* bset imm8, (abs32) */
1935 temp
= load_mem (((insn
& 0xffff) << 16 | (extension
>> 8)), 1);
1936 z
= (temp
& (extension
& 0xff)) == 0;
1937 temp
|= (extension
& 0xff);
1938 store_mem ((((insn
& 0xffff) << 16) | (extension
>> 8)), 1, temp
);
1939 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1940 PSW
|= (z
? PSW_Z
: 0);
1943 /* bset imm8,(d8,an) */
1949 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
1950 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
1951 z
= (temp
& (insn
& 0xff)) == 0;
1952 temp
|= (insn
& 0xff);
1953 store_mem (State
.regs
[REG_A0
+ ((insn
& 30000)>> 16)], 1, temp
);
1954 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1955 PSW
|= (z
? PSW_Z
: 0);
1964 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
1965 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
1966 temp
= ~temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1967 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
1968 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1969 PSW
|= (z
? PSW_Z
: 0);
1972 /* bclr imm8, (abs32) */
1978 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
1979 z
= (temp
& (extension
& 0xff)) == 0;
1980 temp
= ~temp
& (extension
& 0xff);
1981 store_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1, temp
);
1982 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1983 PSW
|= (z
? PSW_Z
: 0);
1986 /* bclr imm8,(d8,an) */
1992 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
1993 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
1994 z
= (temp
& (insn
& 0xff)) == 0;
1995 temp
= ~temp
& (insn
& 0xff);
1996 store_mem (State
.regs
[REG_A0
+ ((insn
& 30000)>> 16)], 1, temp
);
1997 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1998 PSW
|= (z
? PSW_Z
: 0);
2007 temp
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2009 temp
>>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2010 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
;
2011 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2012 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
2013 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2014 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2023 temp
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
2025 temp
>>= (insn
& 0xff);
2026 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = temp
;
2027 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
2028 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x8000000) != 0;
2029 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2030 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2038 c
= State
.regs
[REG_D0
+ (insn
& 0x3)] & 1;
2039 State
.regs
[REG_D0
+ (insn
& 0x3)]
2040 >>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2041 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2042 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
2043 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2044 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2052 c
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 1;
2053 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] >>= (insn
& 0xff);
2054 z
= (State
.regs
[REG_D0
+ ((insn
& 0x3) >> 8)] == 0);
2055 n
= (State
.regs
[REG_D0
+ ((insn
& 0x3) >> 8)] & 0x8000000) != 0;
2056 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2057 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2065 State
.regs
[REG_D0
+ (insn
& 0x3)]
2066 <<= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2067 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2068 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
2069 PSW
&= ~(PSW_Z
| PSW_N
);
2070 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2078 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] <<= (insn
& 0xff);
2079 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
2080 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x8000000) != 0;
2081 PSW
&= ~(PSW_Z
| PSW_N
);
2082 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2090 State
.regs
[REG_D0
+ (insn
& 0x3)] <<= 2;
2091 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2092 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
2093 PSW
&= ~(PSW_Z
| PSW_N
);
2094 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2100 unsigned long value
;
2103 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2108 value
|= ((PSW
& PSW_C
) != 0) ? 0x80000000 : 0;
2109 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
2111 n
= (value
& 0x8000000) != 0;
2112 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2113 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2119 unsigned long value
;
2122 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2123 if (value
& 0x80000000)
2127 value
|= ((PSW
& PSW_C
) != 0);
2128 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
2130 n
= (value
& 0x8000000) != 0;
2131 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2132 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2138 /* The dispatching code will add 2 after we return, so
2139 we subtract two here to make things right. */
2141 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2147 /* The dispatching code will add 2 after we return, so
2148 we subtract two here to make things right. */
2150 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2156 /* The dispatching code will add 2 after we return, so
2157 we subtract two here to make things right. */
2159 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)))
2160 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2166 /* The dispatching code will add 2 after we return, so
2167 we subtract two here to make things right. */
2168 if (!(((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
2169 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2175 /* The dispatching code will add 2 after we return, so
2176 we subtract two here to make things right. */
2178 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
2179 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2185 /* The dispatching code will add 2 after we return, so
2186 we subtract two here to make things right. */
2187 if (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)
2188 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2194 /* The dispatching code will add 2 after we return, so
2195 we subtract two here to make things right. */
2196 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2197 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2203 /* The dispatching code will add 2 after we return, so
2204 we subtract two here to make things right. */
2206 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2212 /* The dispatching code will add 2 after we return, so
2213 we subtract two here to make things right. */
2214 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2215 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2221 /* The dispatching code will add 2 after we return, so
2222 we subtract two here to make things right. */
2224 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2230 /* The dispatching code will add 3 after we return, so
2231 we subtract two here to make things right. */
2233 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2239 /* The dispatching code will add 3 after we return, so
2240 we subtract two here to make things right. */
2242 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2248 /* The dispatching code will add 3 after we return, so
2249 we subtract two here to make things right. */
2251 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2257 /* The dispatching code will add 3 after we return, so
2258 we subtract two here to make things right. */
2260 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2266 /* The dispatching code will add 2 after we return, so
2267 we subtract two here to make things right. */
2268 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2346 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2352 State
.pc
+= SEXT16 (insn
& 0xffff) - 3;
2358 State
.pc
+= (((insn
& 0xffffff) << 8) | extension
) - 5;
2361 /* call label:16,reg_list,imm8 */
2364 unsigned int next_pc
, sp
, adjust
;
2367 sp
= State
.regs
[REG_SP
];
2368 next_pc
= State
.pc
+ 2;
2369 State
.mem
[sp
] = next_pc
& 0xff;
2370 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2371 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2372 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2380 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2386 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2392 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2398 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2404 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2406 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2408 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2410 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2412 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2414 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2416 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2420 /* And make sure to update the stack pointer. */
2421 State
.regs
[REG_SP
] -= extension
;
2422 State
.regs
[REG_MDR
] = next_pc
;
2423 State
.pc
+= SEXT16 ((insn
& 0xffff00) >> 8) - 5;
2426 /* call label:32,reg_list,imm8*/
2429 unsigned int next_pc
, sp
, adjust
;
2432 sp
= State
.regs
[REG_SP
];
2433 next_pc
= State
.pc
+ 2;
2434 State
.mem
[sp
] = next_pc
& 0xff;
2435 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2436 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2437 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2439 mask
= (extension
& 0xff00) >> 8;
2445 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2451 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2457 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2463 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2469 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2471 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2473 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2475 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2477 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2479 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2481 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2485 /* And make sure to update the stack pointer. */
2486 State
.regs
[REG_SP
] -= (extension
& 0xff);
2487 State
.regs
[REG_MDR
] = next_pc
;
2488 State
.pc
+= (((insn
& 0xffffff) << 8) | ((extension
& 0xff0000) >> 16)) - 7;
2494 unsigned int next_pc
, sp
;
2496 sp
= State
.regs
[REG_SP
];
2497 next_pc
= State
.pc
+ 2;
2498 State
.mem
[sp
] = next_pc
& 0xff;
2499 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2500 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2501 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2502 State
.regs
[REG_MDR
] = next_pc
;
2503 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2506 /* calls label:16 */
2509 unsigned int next_pc
, sp
;
2511 sp
= State
.regs
[REG_SP
];
2512 next_pc
= State
.pc
+ 4;
2513 State
.mem
[sp
] = next_pc
& 0xff;
2514 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2515 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2516 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2517 State
.regs
[REG_MDR
] = next_pc
;
2518 State
.pc
+= SEXT16 (insn
& 0xffff) - 4;
2521 /* calls label:32 */
2524 unsigned int next_pc
, sp
;
2526 sp
= State
.regs
[REG_SP
];
2527 next_pc
= State
.pc
+ 6;
2528 State
.mem
[sp
] = next_pc
& 0xff;
2529 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2530 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2531 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2532 State
.regs
[REG_MDR
] = next_pc
;
2533 State
.pc
+= (((insn
& 0xffff) << 16) | extension
) - 6;
2536 /* ret reg_list, imm8 */
2542 State
.regs
[REG_SP
] += insn
& 0xff;
2543 State
.pc
= State
.regs
[REG_MDR
] - 3;
2544 sp
= State
.regs
[REG_SP
];
2546 mask
= (insn
& 0xff00) >> 8;
2551 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2553 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2555 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2557 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2559 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2561 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2563 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2569 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2575 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2581 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2587 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2592 /* retf reg_list,imm8 */
2598 State
.regs
[REG_SP
] += insn
& 0xff;
2599 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2600 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2603 sp
= State
.regs
[REG_SP
];
2605 mask
= (insn
& 0xff00) >> 8;
2610 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2612 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2614 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2616 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2618 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2620 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2622 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2628 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2634 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2640 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2646 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2656 sp
= State
.regs
[REG_SP
];
2657 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2658 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2671 /* We use this for simulated system calls; we may need to change
2672 it to a reserved instruction if we conflict with uses at
2674 int save_errno
= errno
;
2677 /* Registers passed to trap 0 */
2679 /* Function number. */
2680 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2683 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2684 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2685 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2687 /* Registers set by trap 0 */
2689 #define RETVAL State.regs[0] /* return value */
2690 #define RETERR State.regs[1] /* return error code */
2692 /* Turn a pointer in a register into a pointer into real memory. */
2694 #define MEMPTR(x) (State.mem + x)
2698 #if !defined(__GO32__) && !defined(_WIN32)
2703 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2704 (char **)MEMPTR (PARM3
));
2707 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2712 RETVAL
= mn10300_callback
->read (mn10300_callback
, PARM1
,
2713 MEMPTR (PARM2
), PARM3
);
2717 RETVAL
= (int)mn10300_callback
->write_stdout (mn10300_callback
,
2718 MEMPTR (PARM2
), PARM3
);
2720 RETVAL
= (int)mn10300_callback
->write (mn10300_callback
, PARM1
,
2721 MEMPTR (PARM2
), PARM3
);
2724 RETVAL
= mn10300_callback
->lseek (mn10300_callback
, PARM1
, PARM2
, PARM3
);
2727 RETVAL
= mn10300_callback
->close (mn10300_callback
, PARM1
);
2730 RETVAL
= mn10300_callback
->open (mn10300_callback
, MEMPTR (PARM1
), PARM2
);
2733 /* EXIT - caller can look in PARM1 to work out the
2735 if (PARM1
== 0xdead || PARM1
== 0x1)
2736 State
.exception
= SIGABRT
;
2738 State
.exception
= SIGQUIT
;
2741 case SYS_stat
: /* added at hmsi */
2742 /* stat system call */
2744 struct stat host_stat
;
2747 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2751 /* Just wild-assed guesses. */
2752 store_mem (buf
, 2, host_stat
.st_dev
);
2753 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2754 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2755 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2756 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2757 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2758 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2759 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2760 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2761 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2762 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2767 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2770 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2773 RETVAL
= time (MEMPTR (PARM1
));
2778 RETVAL
= times (&tms
);
2779 store_mem (PARM1
, 4, tms
.tms_utime
);
2780 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2781 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2782 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2785 case SYS_gettimeofday
:
2789 RETVAL
= gettimeofday (&t
, &tz
);
2790 store_mem (PARM1
, 4, t
.tv_sec
);
2791 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2792 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2793 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2797 /* Cast the second argument to void *, to avoid type mismatch
2798 if a prototype is present. */
2799 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));