sim/mn10300/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #ifdef HAVE_UNISTD_H
   5 #include <unistd.h>
   6 #endif
   7 #include "mn10300_sim.h"
   8 #include "simops.h"
   9 #include "sys/syscall.h"
  10 #include "bfd.h"
  11 #include <errno.h>
  12 #include <sys/stat.h>
  13 #include <sys/times.h>
  14 #include <sys/time.h>
  15
  16 enum op_types {
  17   OP_UNKNOWN,
  18 };
  19
  20 #ifdef DEBUG
  21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
  22 static void trace_output PARAMS ((enum op_types result));
  23 static int init_text_p = 0;
  24 static asection *text;
  25 static bfd_vma text_start;
  26 static bfd_vma text_end;
  27 extern bfd *exec_bfd;
  28
  29 #ifndef SIZE_INSTRUCTION
  30 #define SIZE_INSTRUCTION 6
  31 #endif
  32
  33 #ifndef SIZE_OPERANDS
  34 #define SIZE_OPERANDS 16
  35 #endif
  36
  37 #ifndef SIZE_VALUES
  38 #define SIZE_VALUES 11
  39 #endif
  40
  41 #ifndef SIZE_LOCATION
  42 #define SIZE_LOCATION 40
  43 #endif
  44
  45 static void
  46 trace_input (name, type, size)
  47      char *name;
  48      enum op_types type;
  49      int size;
  50 {
  51 }
  52
  53 static void
  54 trace_output (result)
  55      enum op_types result;
  56 {
  57 }
  58
  59 #else
  60 #define trace_input(NAME, IN1, IN2)
  61 #define trace_output(RESULT)
  62 #endif
  63
  64 \f
  65 /* mov imm8, dn */
  66 void OP_8000 ()
  67 {
  68   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
  69 }
  70
  71 /* mov dm, dn */
  72 void OP_80 ()
  73 {
  74   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
  75 }
  76
  77 /* mov dm, an */
  78 void OP_F1E0 ()
  79 {
  80   State.regs[REG_A0 + ((insn & 0xc) >> 2)] = State.regs[REG_D0 + (insn & 0x3)];
  81 }
  82
  83 /* mov am, dn */
  84 void OP_F1D0 ()
  85 {
  86   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  87 }
  88
  89 /* mov imm8, an */
  90 void OP_9000 ()
  91 {
  92   State.regs[REG_D0 + ((insn & 0x300) >> 8)] = insn & 0xff;
  93 }
  94
  95 /* mov am, an */
  96 void OP_90 ()
  97 {
  98   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
  99 }
 100
 101 /* mov sp, an */
 102 void OP_3C ()
 103 {
 104   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
 105 }
 106
 107 /* mov am, sp */
 108 void OP_F2F0 ()
 109 {
 110   State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 111 }
 112
 113 /* mov psw, dn */
 114 void OP_F2E4 ()
 115 {
 116   State.regs[REG_D0 + (insn & 0x3)] = PSW;
 117 }
 118
 119 /* mov dm, psw */
 120 void OP_F2F3 ()
 121 {
 122   PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 123 }
 124
 125 /* mov mdr, dn */
 126 void OP_F2E0 ()
 127 {
 128   State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
 129 }
 130
 131 /* mov dm, mdr */
 132 void OP_F2F2 ()
 133 {
 134   State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 135 }
 136
 137 /* mov */
 138 void OP_70 ()
 139 {
 140   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 141     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 142 }
 143
 144 /* mov */
 145 void OP_F80000 ()
 146 {
 147 }
 148
 149 /* mov */
 150 void OP_FA000000 ()
 151 {
 152 }
 153
 154 /* mov */
 155 void OP_FC000000 ()
 156 {
 157 }
 158
 159 /* mov (d8,sp), dn */
 160 void OP_5800 ()
 161 {
 162   State.regs[REG_D0 + ((insn & 0x300) >> 8)]
 163     = load_mem (State.regs[REG_SP] + insn & 0xff, 4);
 164 }
 165
 166 /* mov */
 167 void OP_FAB40000 ()
 168 {
 169 }
 170
 171 /* mov */
 172 void OP_FCB40000 ()
 173 {
 174 }
 175
 176 /* mov */
 177 void OP_F300 ()
 178 {
 179 }
 180
 181 /* mov (abs16), dn */
 182 void OP_300000 ()
 183 {
 184   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 4);
 185 }
 186
 187 /* mov */
 188 void OP_FCA40000 ()
 189 {
 190 }
 191
 192 /* mov (am), an */
 193 void OP_F000 ()
 194 {
 195   State.regs[REG_A0 + ((insn & 0xc) >> 2)]
 196     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
 197 }
 198
 199 /* mov */
 200 void OP_F82000 ()
 201 {
 202 }
 203
 204 /* mov */
 205 void OP_FA200000 ()
 206 {
 207 }
 208
 209 /* mov */
 210 void OP_FC200000 ()
 211 {
 212 }
 213
 214 /* mov (d8,sp), an */
 215 void OP_5C00 ()
 216 {
 217   State.regs[REG_A0 + ((insn & 0x300) >> 8)]
 218     = load_mem (State.regs[REG_SP] + insn & 0xff, 4);
 219 }
 220
 221 /* mov */
 222 void OP_FAB00000 ()
 223 {
 224 }
 225
 226 /* mov */
 227 void OP_FCB00000 ()
 228 {
 229 }
 230
 231 /* mov */
 232 void OP_F380 ()
 233 {
 234 }
 235
 236 /* mov */
 237 void OP_FAA00000 ()
 238 {
 239 }
 240
 241 /* mov */
 242 void OP_FCA00000 ()
 243 {
 244 }
 245
 246 /* mov */
 247 void OP_F8F000 ()
 248 {
 249 }
 250
 251 /* mov dm, (an) */
 252 void OP_60 ()
 253 {
 254   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 255              State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
 256 }
 257
 258 /* mov */
 259 void OP_F81000 ()
 260 {
 261 }
 262
 263 /* mov */
 264 void OP_FA100000 ()
 265 {
 266 }
 267
 268 /* mov */
 269 void OP_FC100000 ()
 270 {
 271 }
 272
 273 /* mov dm, (d8,sp) */
 274 void OP_4200 ()
 275 {
 276   store_mem (State.regs[REG_SP] + insn & 0xff, 4,
 277              State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
 278 }
 279
 280 /* mov */
 281 void OP_FA910000 ()
 282 {
 283 }
 284
 285 /* mov */
 286 void OP_FC910000 ()
 287 {
 288 }
 289
 290 /* mov */
 291 void OP_F340 ()
 292 {
 293 }
 294
 295 /* mov dm, (abs16) */
 296 void OP_10000 ()
 297 {
 298   store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 299 }
 300
 301 /* mov */
 302 void OP_FC810000 ()
 303 {
 304 }
 305
 306 /* mov am, (an) */
 307 void OP_F010 ()
 308 {
 309   store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
 310              State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
 311 }
 312
 313 /* mov */
 314 void OP_F83000 ()
 315 {
 316 }
 317
 318 /* mov */
 319 void OP_FA300000 ()
 320 {
 321 }
 322
 323 /* mov */
 324 void OP_FC300000 ()
 325 {
 326 }
 327
 328 /* mov am, (d8,sp) */
 329 void OP_4300 ()
 330 {
 331   store_mem (State.regs[REG_SP] + insn & 0xff, 4,
 332              State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
 333 }
 334
 335 /* mov */
 336 void OP_FA900000 ()
 337 {
 338 }
 339
 340 /* mov */
 341 void OP_FC900000 ()
 342 {
 343 }
 344
 345 /* mov */
 346 void OP_F3C0 ()
 347 {
 348 }
 349
 350 /* mov */
 351 void OP_FA800000 ()
 352 {
 353 }
 354
 355 /* mov */
 356 void OP_FC800000 ()
 357 {
 358 }
 359
 360 /* mov */
 361 void OP_F8F400 ()
 362 {
 363 }
 364
 365 /* mov imm16, dn */
 366 void OP_2C0000 ()
 367 {
 368   unsigned long value;
 369
 370   value = SEXT16 (insn & 0xffff);
 371   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 372 }
 373
 374 /* mov */
 375 void OP_FCCC0000 ()
 376 {
 377 }
 378
 379 /* mov imm16, an */
 380 void OP_240000 ()
 381 {
 382   unsigned long value;
 383
 384   value = insn & 0xffff;
 385   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 386 }
 387
 388 /* mov imm32, an*/
 389 void OP_FCDC0000 ()
 390 {
 391   unsigned long value;
 392
 393   value = (insn & 0xffff) << 16 | extension;
 394   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 395 }
 396
 397 /* movbu (am), dn */
 398 void OP_F040 ()
 399 {
 400   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 401     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
 402 }
 403
 404 /* movbu */
 405 void OP_F84000 ()
 406 {
 407 }
 408
 409 /* movbu */
 410 void OP_FA400000 ()
 411 {
 412 }
 413
 414 /* movbu */
 415 void OP_FC400000 ()
 416 {
 417 }
 418
 419 /* movbu */
 420 void OP_F8B800 ()
 421 {
 422 }
 423
 424 /* movbu */
 425 void OP_FAB80000 ()
 426 {
 427 }
 428
 429 /* movbu */
 430 void OP_FCB80000 ()
 431 {
 432 }
 433
 434 /* movbu */
 435 void OP_F400 ()
 436 {
 437 }
 438
 439 /* movbu (abs16), dn */
 440 void OP_340000 ()
 441 {
 442   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 1);
 443 }
 444
 445 /* movbu */
 446 void OP_FCA80000 ()
 447 {
 448 }
 449
 450 /* movbu dm, (an) */
 451 void OP_F050 ()
 452 {
 453   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
 454              State.regs[REG_D0 + (insn & 0x3)]);
 455 }
 456
 457 /* movbu */
 458 void OP_F85000 ()
 459 {
 460 }
 461
 462 /* movbu */
 463 void OP_FA500000 ()
 464 {
 465 }
 466
 467 /* movbu */
 468 void OP_FC500000 ()
 469 {
 470 }
 471
 472 /* movbu */
 473 void OP_F89200 ()
 474 {
 475 }
 476
 477 /* movbu */
 478 void OP_FA920000 ()
 479 {
 480 }
 481
 482 /* movbu */
 483 void OP_FC920000 ()
 484 {
 485 }
 486
 487 /* movbu */
 488 void OP_F440 ()
 489 {
 490 }
 491
 492 /* movbu dm, (abs16) */
 493 void OP_20000 ()
 494 {
 495   store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 496 }
 497
 498 /* movbu */
 499 void OP_FC820000 ()
 500 {
 501 }
 502
 503 /* movhu (am), dn */
 504 void OP_F060 ()
 505 {
 506   State.regs[REG_D0 + ((insn & 0xc) >> 2)]
 507     = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
 508 }
 509
 510 /* movhu */
 511 void OP_F86000 ()
 512 {
 513 }
 514
 515 /* movhu */
 516 void OP_FA600000 ()
 517 {
 518 }
 519
 520 /* movhu */
 521 void OP_FC600000 ()
 522 {
 523 }
 524
 525 /* movhu */
 526 void OP_F8BC00 ()
 527 {
 528 }
 529
 530 /* movhu */
 531 void OP_FABC0000 ()
 532 {
 533 }
 534
 535 /* movhu */
 536 void OP_FCBC0000 ()
 537 {
 538 }
 539
 540 /* movhu */
 541 void OP_F480 ()
 542 {
 543 }
 544
 545 /* movhu (abs16), dn */
 546 void OP_380000 ()
 547 {
 548   State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem (insn & 0xffff, 2);
 549 }
 550
 551 /* movhu */
 552 void OP_FCAC0000 ()
 553 {
 554 }
 555
 556 /* movhu dm, (an) */
 557 void OP_F070 ()
 558 {
 559   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 2,
 560              State.regs[REG_D0 + (insn & 0x3)]);
 561 }
 562
 563 /* movhu */
 564 void OP_F87000 ()
 565 {
 566 }
 567
 568 /* movhu */
 569 void OP_FA700000 ()
 570 {
 571 }
 572
 573 /* movhu */
 574 void OP_FC700000 ()
 575 {
 576 }
 577
 578 /* movhu */
 579 void OP_F89300 ()
 580 {
 581 }
 582
 583 /* movhu */
 584 void OP_FA930000 ()
 585 {
 586 }
 587
 588 /* movhu */
 589 void OP_FC930000 ()
 590 {
 591 }
 592
 593 /* movhu */
 594 void OP_F4C0 ()
 595 {
 596 }
 597
 598 /* movhu dm, (abs16) */
 599 void OP_30000 ()
 600 {
 601   store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
 602 }
 603
 604 /* movhu */
 605 void OP_FC830000 ()
 606 {
 607 }
 608
 609 /* ext dn */
 610 void OP_F2D0 ()
 611 {
 612   if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
 613     State.regs[REG_MDR] = -1;
 614   else
 615     State.regs[REG_MDR] = 0;
 616 }
 617
 618 /* extb dn */
 619 void OP_10 ()
 620 {
 621   State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
 622 }
 623
 624 /* extbu dn */
 625 void OP_14 ()
 626 {
 627   State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
 628 }
 629
 630 /* exth dn */
 631 void OP_18 ()
 632 {
 633   State.regs[REG_D0 + (insn & 0x3)]
 634     = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
 635 }
 636
 637 /* exthu dn */
 638 void OP_1C ()
 639 {
 640   State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
 641 }
 642
 643 /* movm (sp), reg_list */
 644 void OP_CE00 ()
 645 {
 646   unsigned long sp = State.regs[REG_SP];
 647   unsigned long mask;
 648
 649   mask = insn & 0xff;
 650
 651   if (mask & 0x8)
 652     {
 653       sp += 4;
 654       State.regs[REG_LAR] = load_mem (sp, 4);
 655       sp += 4;
 656       State.regs[REG_LIR] = load_mem (sp, 4);
 657       sp += 4;
 658       State.regs[REG_MDR] = load_mem (sp, 4);
 659       sp += 4;
 660       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 661       sp += 4;
 662       State.regs[REG_A0] = load_mem (sp, 4);
 663       sp += 4;
 664       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 665       sp += 4;
 666       State.regs[REG_D0] = load_mem (sp, 4);
 667       sp += 4;
 668     }
 669
 670   if (mask & 0x10)
 671     {
 672       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 673       sp += 4;
 674     }
 675
 676   if (mask & 0x20)
 677     {
 678       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 679       sp += 4;
 680     }
 681
 682   if (mask & 0x40)
 683     {
 684       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 685       sp += 4;
 686     }
 687
 688   if (mask & 0x80)
 689     {
 690       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 691       sp += 4;
 692     }
 693
 694   /* And make sure to update the stack pointer.  */
 695   State.regs[REG_SP] = sp;
 696 }
 697
 698 /* movm reg_list, (sp) */
 699 void OP_CF00 ()
 700 {
 701   unsigned long sp = State.regs[REG_SP];
 702   unsigned long mask;
 703
 704   mask = insn & 0xff;
 705
 706   if (mask & 0x80)
 707     {
 708       sp -= 4;
 709       State.regs[REG_D0 + 2] = load_mem (sp, 4);
 710     }
 711
 712   if (mask & 0x40)
 713     {
 714       sp -= 4;
 715       State.regs[REG_D0 + 3] = load_mem (sp, 4);
 716     }
 717
 718   if (mask & 0x20)
 719     {
 720       sp -= 4;
 721       State.regs[REG_A0 + 2] = load_mem (sp, 4);
 722     }
 723
 724   if (mask & 0x10)
 725     {
 726       sp -= 4;
 727       State.regs[REG_A0 + 3] = load_mem (sp, 4);
 728     }
 729
 730   if (mask & 0x8)
 731     {
 732       sp -= 4;
 733       State.regs[REG_D0] = load_mem (sp, 4);
 734       sp -= 4;
 735       State.regs[REG_D0 + 1] = load_mem (sp, 4);
 736       sp -= 4;
 737       State.regs[REG_A0] = load_mem (sp, 4);
 738       sp -= 4;
 739       State.regs[REG_A0 + 1] = load_mem (sp, 4);
 740       sp -= 4;
 741       State.regs[REG_MDR] = load_mem (sp, 4);
 742       sp -= 4;
 743       State.regs[REG_LIR] = load_mem (sp, 4);
 744       sp -= 4;
 745       State.regs[REG_LAR] = load_mem (sp, 4);
 746       sp -= 4;
 747     }
 748
 749   /* And make sure to update the stack pointer.  */
 750   State.regs[REG_SP] = sp;
 751 }
 752
 753 /* clr dn */
 754 void OP_0 ()
 755 {
 756   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
 757
 758   PSW |= PSW_Z;
 759   PSW &= ~(PSW_V | PSW_C | PSW_N);
 760 }
 761
 762 /* add dm,dn*/
 763 void OP_E0 ()
 764 {
 765   int z, c, n, v;
 766   unsigned long reg1, reg2, value;
 767
 768   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 769   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 770   value = reg1 + reg2;
 771   State.regs[REG_D0 + (insn & 0x3)] = value;
 772
 773   z = (value == 0);
 774   n = (value & 0x80000000);
 775   c = (reg1 < reg2);
 776   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 777        && (reg2 & 0x8000000) != (value & 0x80000000));
 778
 779   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 780   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 781           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 782 }
 783
 784 /* add dm, an */
 785 void OP_F160 ()
 786 {
 787   int z, c, n, v;
 788   unsigned long reg1, reg2, value;
 789
 790   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 791   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 792   value = reg1 + reg2;
 793   State.regs[REG_A0 + (insn & 0x3)] = value;
 794
 795   z = (value == 0);
 796   n = (value & 0x80000000);
 797   c = (reg1 < reg2);
 798   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 799        && (reg2 & 0x8000000) != (value & 0x80000000));
 800
 801   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 802   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 803           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 804 }
 805
 806 /* add am, dn*/
 807 void OP_F150 ()
 808 {
 809   int z, c, n, v;
 810   unsigned long reg1, reg2, value;
 811
 812   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 813   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 814   value = reg1 + reg2;
 815   State.regs[REG_D0 + (insn & 0x3)] = value;
 816
 817   z = (value == 0);
 818   n = (value & 0x80000000);
 819   c = (reg1 < reg2);
 820   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 821        && (reg2 & 0x8000000) != (value & 0x80000000));
 822
 823   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 824   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 825           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 826 }
 827
 828 /* add am,an */
 829 void OP_F170 ()
 830 {
 831   int z, c, n, v;
 832   unsigned long reg1, reg2, value;
 833
 834   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 835   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 836   value = reg1 + reg2;
 837   State.regs[REG_A0 + (insn & 0x3)] = value;
 838
 839   z = (value == 0);
 840   n = (value & 0x80000000);
 841   c = (reg1 < reg2);
 842   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 843        && (reg2 & 0x8000000) != (value & 0x80000000));
 844
 845   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 846   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 847           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 848 }
 849
 850 /* add imm8, dn */
 851 void OP_2800 ()
 852 {
 853   int z, c, n, v;
 854   unsigned long reg1, imm, value;
 855
 856   reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
 857   imm = SEXT8 (insn & 0xff);
 858   value = reg1 + imm;
 859   State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
 860
 861   z = (value == 0);
 862   n = (value & 0x80000000);
 863   c = (reg1 < imm);
 864   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 865        && (imm & 0x8000000) != (value & 0x80000000));
 866
 867   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 868   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 869           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 870 }
 871
 872 /* add imm16, dn */
 873 void OP_FAC00000 ()
 874 {
 875   int z, c, n, v;
 876   unsigned long reg1, imm, value;
 877
 878   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 879   imm = SEXT16 (insn & 0xffff);
 880   value = reg1 + imm;
 881   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 882
 883   z = (value == 0);
 884   n = (value & 0x80000000);
 885   c = (reg1 < imm);
 886   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 887        && (imm & 0x8000000) != (value & 0x80000000));
 888
 889   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 890   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 891           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 892 }
 893
 894 /* add imm32,dn */
 895 void OP_FCC00000 ()
 896 {
 897   int z, c, n, v;
 898   unsigned long reg1, imm, value;
 899
 900   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 901   imm = ((insn & 0xffff) << 16) | extension;
 902   value = reg1 + imm;
 903   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 904
 905   z = (value == 0);
 906   n = (value & 0x80000000);
 907   c = (reg1 < imm);
 908   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 909        && (imm & 0x8000000) != (value & 0x80000000));
 910
 911   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 912   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 913           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 914 }
 915
 916 /* add imm8, an */
 917 void OP_2000 ()
 918 {
 919   int z, c, n, v;
 920   unsigned long reg1, imm, value;
 921
 922   reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
 923   imm = insn & 0xff;
 924   value = reg1 + imm;
 925   State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
 926
 927   z = (value == 0);
 928   n = (value & 0x80000000);
 929   c = (reg1 < imm);
 930   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 931        && (imm & 0x8000000) != (value & 0x80000000));
 932
 933   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 934   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 935           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 936 }
 937
 938 /* add imm16, an */
 939 void OP_FAD00000 ()
 940 {
 941   int z, c, n, v;
 942   unsigned long reg1, imm, value;
 943
 944   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 945   imm = 0xffff;
 946   value = reg1 + imm;
 947   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 948
 949   z = (value == 0);
 950   n = (value & 0x80000000);
 951   c = (reg1 < imm);
 952   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 953        && (imm & 0x8000000) != (value & 0x80000000));
 954
 955   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 956   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 957           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 958 }
 959
 960 /* add imm32, an */
 961 void OP_FCD00000 ()
 962 {
 963   int z, c, n, v;
 964   unsigned long reg1, imm, value;
 965
 966   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 967   imm = ((insn & 0xffff) << 16) | extension;
 968   value = reg1 + imm;
 969   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 970
 971   z = (value == 0);
 972   n = (value & 0x80000000);
 973   c = (reg1 < imm);
 974   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 975        && (imm & 0x8000000) != (value & 0x80000000));
 976
 977   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 978   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 979           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 980 }
 981
 982 /* add imm8, sp*/
 983 void OP_F8FE00 ()
 984 {
 985   int z, c, n, v;
 986   unsigned long reg1, imm, value;
 987
 988   reg1 = State.regs[REG_SP];
 989   imm = SEXT8 (insn & 0xff);
 990   value = reg1 + imm;
 991   State.regs[REG_SP] = value;
 992
 993   z = (value == 0);
 994   n = (value & 0x80000000);
 995   c = (reg1 < imm);
 996   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 997        && (imm & 0x8000000) != (value & 0x80000000));
 998
 999   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1000   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1001           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1002 }
1003
1004 /* add imm16,sp */
1005 void OP_FAFE0000 ()
1006 {
1007   int z, c, n, v;
1008   unsigned long reg1, imm, value;
1009
1010   reg1 = State.regs[REG_SP];
1011   imm = SEXT16 (insn & 0xffff);
1012   value = reg1 + imm;
1013   State.regs[REG_SP] = value;
1014
1015   z = (value == 0);
1016   n = (value & 0x80000000);
1017   c = (reg1 < imm);
1018   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1019        && (imm & 0x8000000) != (value & 0x80000000));
1020
1021   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1022   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1023           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1024 }
1025
1026 /* add */
1027 void OP_FCFE0000 ()
1028 {
1029   int z, c, n, v;
1030   unsigned long reg1, imm, value;
1031
1032   reg1 = State.regs[REG_SP];
1033   imm = ((insn & 0xffff) << 16) | extension;
1034   value = reg1 + imm;
1035   State.regs[REG_SP] = value;
1036
1037   z = (value == 0);
1038   n = (value & 0x80000000);
1039   c = (reg1 < imm);
1040   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1041        && (imm & 0x8000000) != (value & 0x80000000));
1042
1043   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1044   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1045           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1046 }
1047
1048 /* addc */
1049 void OP_F140 ()
1050 {
1051   int z, c, n, v;
1052   unsigned long reg1, reg2, value;
1053
1054   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1055   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1056   value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1057   State.regs[REG_D0 + (insn & 0x3)] = value;
1058
1059   z = (value == 0);
1060   n = (value & 0x80000000);
1061   c = (reg1 < reg2);
1062   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1063        && (reg2 & 0x8000000) != (value & 0x80000000));
1064
1065   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1066   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1067           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1068 }
1069
1070 /* sub dm, dn */
1071 void OP_F100 ()
1072 {
1073   int z, c, n, v;
1074   unsigned long reg1, reg2, value;
1075
1076   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1077   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1078   value = reg2 - reg1;
1079
1080   z = (value == 0);
1081   n = (value & 0x80000000);
1082   c = (reg1 < reg2);
1083   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1084        && (reg2 & 0x8000000) != (value & 0x80000000));
1085
1086   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1087   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1088           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1089   State.regs[REG_D0 + (insn & 0x3)] = value;
1090 }
1091
1092 /* sub dm, an */
1093 void OP_F120 ()
1094 {
1095   int z, c, n, v;
1096   unsigned long reg1, reg2, value;
1097
1098   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1099   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1100   value = reg2 - reg1;
1101
1102   z = (value == 0);
1103   n = (value & 0x80000000);
1104   c = (reg1 < reg2);
1105   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1106        && (reg2 & 0x8000000) != (value & 0x80000000));
1107
1108   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1109   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1110           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1111   State.regs[REG_A0 + (insn & 0x3)] = value;
1112 }
1113
1114 /* sub am, dn */
1115 void OP_F110 ()
1116 {
1117   int z, c, n, v;
1118   unsigned long reg1, reg2, value;
1119
1120   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1121   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1122   value = reg2 - reg1;
1123
1124   z = (value == 0);
1125   n = (value & 0x80000000);
1126   c = (reg1 < reg2);
1127   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1128        && (reg2 & 0x8000000) != (value & 0x80000000));
1129
1130   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1131   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1132           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1133   State.regs[REG_D0 + (insn & 0x3)] = value;
1134 }
1135
1136 /* sub am, an */
1137 void OP_F130 ()
1138 {
1139   int z, c, n, v;
1140   unsigned long reg1, reg2, value;
1141
1142   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1143   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1144   value = reg2 - reg1;
1145
1146   z = (value == 0);
1147   n = (value & 0x80000000);
1148   c = (reg1 < reg2);
1149   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1150        && (reg2 & 0x8000000) != (value & 0x80000000));
1151
1152   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1153   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1154           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1155   State.regs[REG_A0 + (insn & 0x3)] = value;
1156 }
1157
1158 /* sub */
1159 void OP_FCC40000 ()
1160 {
1161   int z, c, n, v;
1162   unsigned long reg1, imm, value;
1163
1164   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1165   imm = ((insn & 0xffff) << 16) | extension;
1166   value = reg1 - imm;
1167
1168   z = (value == 0);
1169   n = (value & 0x80000000);
1170   c = (reg1 < imm);
1171   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1172        && (imm & 0x8000000) != (value & 0x80000000));
1173
1174   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1175   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1176           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1177   State.regs[REG_D0 + ((insn & 0x300) >> 16)] = value;
1178 }
1179
1180 /* sub */
1181 void OP_FCD40000 ()
1182 {
1183   int z, c, n, v;
1184   unsigned long reg1, imm, value;
1185
1186   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1187   imm = ((insn & 0xffff) << 16) | extension;
1188   value = reg1 - imm;
1189
1190   z = (value == 0);
1191   n = (value & 0x80000000);
1192   c = (reg1 < imm);
1193   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1194        && (imm & 0x8000000) != (value & 0x80000000));
1195
1196   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1197   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1198           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1199   State.regs[REG_A0 + ((insn & 0x300) >> 16)] = value;
1200 }
1201
1202 /* subc */
1203 void OP_F180 ()
1204 {
1205   int z, c, n, v;
1206   unsigned long reg1, reg2, value;
1207
1208   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1209   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1210   value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1211
1212   z = (value == 0);
1213   n = (value & 0x80000000);
1214   c = (reg1 < reg2);
1215   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1216        && (reg2 & 0x8000000) != (value & 0x80000000));
1217
1218   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1219   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1220           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1221   State.regs[REG_D0 + (insn & 0x3)] = value;
1222 }
1223
1224 /* mul */
1225 void OP_F240 ()
1226 {
1227   unsigned long long temp;
1228   int n, z;
1229
1230   temp = (State.regs[REG_D0 + (insn & 0x3)]
1231           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1232   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1233   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1234   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1235   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1236   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1237   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1238 }
1239
1240 /* mulu */
1241 void OP_F250 ()
1242 {
1243   unsigned long long temp;
1244   int n, z;
1245
1246   temp = (State.regs[REG_D0 + (insn & 0x3)]
1247           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1248   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1249   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1250   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1251   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1252   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1253   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1254 }
1255
1256 /* div */
1257 void OP_F260 ()
1258 {
1259   long long temp;
1260   int n, z;
1261
1262   temp = State.regs[REG_MDR];
1263   temp <<= 32;
1264   temp |= State.regs[REG_D0 + (insn & 0x3)];
1265   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1266   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1267   temp = (State.regs[REG_D0 + (insn & 0x3)]
1268           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1269   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1270   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1271   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1272   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1273   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1274   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1275 }
1276
1277 /* divu */
1278 void OP_F270 ()
1279 {
1280   unsigned long long temp;
1281   int n, z;
1282
1283   temp = State.regs[REG_MDR];
1284   temp <<= 32;
1285   temp |= State.regs[REG_D0 + (insn & 0x3)];
1286   State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1287   temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1288   temp = (State.regs[REG_D0 + (insn & 0x3)]
1289           *  State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1290   State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1291   State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1292   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1293   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1294   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1295   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1296 }
1297
1298 /* inc dn */
1299 void OP_40 ()
1300 {
1301   State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
1302 }
1303
1304 /* inc an */
1305 void OP_41 ()
1306 {
1307   State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1308 }
1309
1310 /* inc4 an */
1311 void OP_50 ()
1312 {
1313   State.regs[REG_A0 + (insn & 0x3)] += 4;
1314 }
1315
1316 /* cmp imm8, dn */
1317 void OP_A000 ()
1318 {
1319   int z, c, n, v;
1320   unsigned long reg1, imm, value;
1321
1322   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1323   imm = SEXT8 (insn & 0xff);
1324   value = reg1 - imm;
1325
1326   z = (value == 0);
1327   n = (value & 0x80000000);
1328   c = (reg1 < imm);
1329   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1330        && (imm & 0x8000000) != (value & 0x80000000));
1331
1332   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1333   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1334           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1335 }
1336
1337 /* cmp dm, dn */
1338 void OP_A0 ()
1339 {
1340   int z, c, n, v;
1341   unsigned long reg1, reg2, value;
1342
1343   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1344   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1345   value = reg2 - reg1;
1346
1347   z = (value == 0);
1348   n = (value & 0x80000000);
1349   c = (reg1 < reg2);
1350   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1351        && (reg2 & 0x8000000) != (value & 0x80000000));
1352
1353   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1354   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1355           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1356 }
1357
1358 /* cmp dm, an */
1359 void OP_F1A0 ()
1360 {
1361   int z, c, n, v;
1362   unsigned long reg1, reg2, value;
1363
1364   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1365   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1366   value = reg2 - reg1;
1367
1368   z = (value == 0);
1369   n = (value & 0x80000000);
1370   c = (reg1 < reg2);
1371   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1372        && (reg2 & 0x8000000) != (value & 0x80000000));
1373
1374   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1375   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1376           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1377 }
1378
1379 /* cmp am, dn */
1380 void OP_F190 ()
1381 {
1382   int z, c, n, v;
1383   unsigned long reg1, reg2, value;
1384
1385   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1386   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1387   value = reg2 - reg1;
1388
1389   z = (value == 0);
1390   n = (value & 0x80000000);
1391   c = (reg1 < reg2);
1392   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1393        && (reg2 & 0x8000000) != (value & 0x80000000));
1394
1395   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1396   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1397           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1398 }
1399
1400 /* cmp imm8, an */
1401 void OP_B000 ()
1402 {
1403   int z, c, n, v;
1404   unsigned long reg1, imm, value;
1405
1406   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1407   imm = insn & 0xff;
1408   value = reg1 - imm;
1409
1410   z = (value == 0);
1411   n = (value & 0x80000000);
1412   c = (reg1 < imm);
1413   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1414        && (imm & 0x8000000) != (value & 0x80000000));
1415
1416   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1417   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1418           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1419 }
1420
1421 /* cmp am, an */
1422 void OP_B0 ()
1423 {
1424   int z, c, n, v;
1425   unsigned long reg1, reg2, value;
1426
1427   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1428   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1429   value = reg2 - reg1;
1430
1431   z = (value == 0);
1432   n = (value & 0x80000000);
1433   c = (reg1 < reg2);
1434   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1435        && (reg2 & 0x8000000) != (value & 0x80000000));
1436
1437   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1438   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1439           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1440 }
1441
1442 /* cmp imm16, dn */
1443 void OP_FAC80000 ()
1444 {
1445   int z, c, n, v;
1446   unsigned long reg1, imm, value;
1447
1448   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1449   imm = SEXT16 (insn & 0xffff);
1450   value = reg1 - imm;
1451
1452   z = (value == 0);
1453   n = (value & 0x80000000);
1454   c = (reg1 < imm);
1455   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1456        && (imm & 0x8000000) != (value & 0x80000000));
1457
1458   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1459   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1460           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1461 }
1462
1463 /* cmp imm32, dn */
1464 void OP_FCC80000 ()
1465 {
1466   int z, c, n, v;
1467   unsigned long reg1, imm, value;
1468
1469   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1470   imm = ((insn & 0xffff) << 16) | extension;
1471   value = reg1 - imm;
1472
1473   z = (value == 0);
1474   n = (value & 0x80000000);
1475   c = (reg1 < imm);
1476   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1477        && (imm & 0x8000000) != (value & 0x80000000));
1478
1479   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1480   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1481           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1482 }
1483
1484 /* cmp imm16, an */
1485 void OP_FAD80000 ()
1486 {
1487   int z, c, n, v;
1488   unsigned long reg1, imm, value;
1489
1490   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1491   imm = insn & 0xffff;
1492   value = reg1 - imm;
1493
1494   z = (value == 0);
1495   n = (value & 0x80000000);
1496   c = (reg1 < imm);
1497   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1498        && (imm & 0x8000000) != (value & 0x80000000));
1499
1500   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1501   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1502           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1503 }
1504
1505 /* cmp imm32, an */
1506 void OP_FCD80000 ()
1507 {
1508   int z, c, n, v;
1509   unsigned long reg1, imm, value;
1510
1511   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1512   imm = ((insn & 0xffff) << 16) | extension;
1513   value = reg1 - imm;
1514
1515   z = (value == 0);
1516   n = (value & 0x80000000);
1517   c = (reg1 < imm);
1518   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1519        && (imm & 0x8000000) != (value & 0x80000000));
1520
1521   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1522   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1523           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1524 }
1525
1526 /* and dm, dn */
1527 void OP_F200 ()
1528 {
1529   int n, z;
1530
1531   State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1532   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1533   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1534   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1535   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1536 }
1537
1538 /* and */
1539 void OP_F8E000 ()
1540 {
1541 }
1542
1543 /* and */
1544 void OP_FAE00000 ()
1545 {
1546 }
1547
1548 /* and */
1549 void OP_FCE00000 ()
1550 {
1551 }
1552
1553 /* and */
1554 void OP_FAFC0000 ()
1555 {
1556 }
1557
1558 /* or dm, dn*/
1559 void OP_F210 ()
1560 {
1561   int n, z;
1562
1563   State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1564   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1565   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1566   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1567   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1568 }
1569
1570 /* or */
1571 void OP_F8E400 ()
1572 {
1573 }
1574
1575 /* or */
1576 void OP_FAE40000 ()
1577 {
1578 }
1579
1580 /* or */
1581 void OP_FCE40000 ()
1582 {
1583 }
1584
1585 /* or */
1586 void OP_FAFD0000 ()
1587 {
1588 }
1589
1590 /* xor dm, dn*/
1591 void OP_F220 ()
1592 {
1593   int n, z;
1594
1595   State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1596   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1597   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1598   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1599   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1600 }
1601
1602 /* xor */
1603 void OP_FAE80000 ()
1604 {
1605 }
1606
1607 /* xor */
1608 void OP_FCE80000 ()
1609 {
1610 }
1611
1612 /* not */
1613 void OP_F230 ()
1614 {
1615   int n, z;
1616
1617   State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1618   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1619   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1620   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1621   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1622 }
1623
1624 /* btst */
1625 void OP_F8EC00 ()
1626 {
1627 }
1628
1629 /* btst */
1630 void OP_FAEC0000 ()
1631 {
1632 }
1633
1634 /* btst */
1635 void OP_FCEC0000 ()
1636 {
1637 }
1638
1639 /* btst */
1640 void OP_FE020000 ()
1641 {
1642 }
1643
1644 /* btst */
1645 void OP_FAF80000 ()
1646 {
1647 }
1648
1649 /* bset dm, (an) */
1650 void OP_F080 ()
1651 {
1652   unsigned long temp;
1653   int z;
1654
1655   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1656   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1657   temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1658   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1659   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1660   PSW |= (z ? PSW_Z : 0);
1661 }
1662
1663 /* bset */
1664 void OP_FE000000 ()
1665 {
1666 }
1667
1668 /* bset */
1669 void OP_FAF00000 ()
1670 {
1671 }
1672
1673 /* bclr dm, (an) */
1674 void OP_F090 ()
1675 {
1676   unsigned long temp;
1677   int z;
1678
1679   temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
1680   z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
1681   temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1682   store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
1683   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1684   PSW |= (z ? PSW_Z : 0);
1685 }
1686
1687 /* bclr */
1688 void OP_FE010000 ()
1689 {
1690 }
1691
1692 /* bclr */
1693 void OP_FAF40000 ()
1694 {
1695 }
1696
1697 /* asr */
1698 void OP_F2B0 ()
1699 {
1700   long temp;
1701   int z, n, c;
1702
1703   temp = State.regs[REG_D0 + (insn & 0x3)];
1704   c = temp & 1;
1705   temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1706   State.regs[REG_D0 + (insn & 0x3)] = temp;
1707   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1708   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1709   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1710   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1711 }
1712
1713 /* asr */
1714 void OP_F8C800 ()
1715 {
1716 }
1717
1718 /* lsr */
1719 void OP_F2A0 ()
1720 {
1721   int z, n, c;
1722
1723   c = State.regs[REG_D0 + (insn & 0x3)] & 1;
1724   State.regs[REG_D0 + (insn & 0x3)]
1725     >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1726   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1727   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1728   PSW &= ~(PSW_Z | PSW_N | PSW_C);
1729   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1730 }
1731
1732 /* lsr */
1733 void OP_F8C400 ()
1734 {
1735 }
1736
1737 /* asl */
1738 void OP_F290 ()
1739 {
1740   int n, z;
1741
1742   State.regs[REG_D0 + (insn & 0x3)]
1743     <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1744   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1745   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1746   PSW &= ~(PSW_Z | PSW_N);
1747   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1748 }
1749
1750 /* asl */
1751 void OP_F8C000 ()
1752 {
1753 }
1754
1755 /* asl2 dn */
1756 void OP_54 ()
1757 {
1758   int n, z;
1759
1760   State.regs[REG_D0 + (insn & 0x3)] <<= 2;
1761   z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1762   n = (State.regs[REG_D0 + (insn & 0x3)] & 0x8000000) != 0;
1763   PSW &= ~(PSW_Z | PSW_N);
1764   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1765 }
1766
1767 /* ror dn */
1768 void OP_F284 ()
1769 {
1770   unsigned long value;
1771   int c,n,z;
1772
1773   value = State.regs[REG_D0 + (insn & 0x3)];
1774   if (value & 0x1)
1775     c = 1;
1776
1777   value >>= 1;
1778   value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
1779   State.regs[REG_D0 + (insn & 0x3)] = value;
1780   z = (value == 0);
1781   n = (value & 0x8000000) != 0;
1782   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1783   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1784 }
1785
1786 /* rol dn */
1787 void OP_F280 ()
1788 {
1789   unsigned long value;
1790   int c,n,z;
1791
1792   value = State.regs[REG_D0 + (insn & 0x3)];
1793   if (value & 0x80000000)
1794     c = 1;
1795
1796   value <<= 1;
1797   value |= ((PSW & PSW_C) != 0);
1798   State.regs[REG_D0 + (insn & 0x3)] = value;
1799   z = (value == 0);
1800   n = (value & 0x8000000) != 0;
1801   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1802   PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
1803 }
1804
1805 /* beq */
1806 void OP_C800 ()
1807 {
1808   /* The dispatching code will add 2 after we return, so
1809      we subtract two here to make things right.  */
1810   if (PSW & PSW_Z)
1811     State.pc += SEXT8 (insn & 0xff) - 2;
1812 }
1813
1814 /* bne */
1815 void OP_C900 ()
1816 {
1817   /* The dispatching code will add 2 after we return, so
1818      we subtract two here to make things right.  */
1819   if (!(PSW & PSW_Z))
1820     State.pc += SEXT8 (insn & 0xff) - 2;
1821 }
1822
1823 /* bgt */
1824 void OP_C100 ()
1825 {
1826 }
1827
1828 /* bge */
1829 void OP_C200 ()
1830 {
1831 }
1832
1833 /* ble */
1834 void OP_C300 ()
1835 {
1836 }
1837
1838 /* blt */
1839 void OP_C000 ()
1840 {
1841 }
1842
1843 /* bhi */
1844 void OP_C500 ()
1845 {
1846 }
1847
1848 /* bcc */
1849 void OP_C600 ()
1850 {
1851 }
1852
1853 /* bls */
1854 void OP_C700 ()
1855 {
1856 }
1857
1858 /* bcs */
1859 void OP_C400 ()
1860 {
1861 }
1862
1863 /* bvc */
1864 void OP_F8E800 ()
1865 {
1866 }
1867
1868 /* bvs */
1869 void OP_F8E900 ()
1870 {
1871 }
1872
1873 /* bnc */
1874 void OP_F8EA00 ()
1875 {
1876 }
1877
1878 /* bns */
1879 void OP_F8EB00 ()
1880 {
1881 }
1882
1883 /* bra */
1884 void OP_CA00 ()
1885 {
1886 }
1887
1888 /* leq */
1889 void OP_D8 ()
1890 {
1891 }
1892
1893 /* lne */
1894 void OP_D9 ()
1895 {
1896 }
1897
1898 /* lgt */
1899 void OP_D1 ()
1900 {
1901 }
1902
1903 /* lge */
1904 void OP_D2 ()
1905 {
1906 }
1907
1908 /* lle */
1909 void OP_D3 ()
1910 {
1911 }
1912
1913 /* llt */
1914 void OP_D0 ()
1915 {
1916 }
1917
1918 /* lhi */
1919 void OP_D5 ()
1920 {
1921 }
1922
1923 /* lcc */
1924 void OP_D6 ()
1925 {
1926 }
1927
1928 /* lls */
1929 void OP_D7 ()
1930 {
1931 }
1932
1933 /* lcs */
1934 void OP_D4 ()
1935 {
1936 }
1937
1938 /* lra */
1939 void OP_DA ()
1940 {
1941 }
1942
1943 /* setlb */
1944 void OP_DB ()
1945 {
1946 }
1947
1948 /* jmp (an) */
1949 void OP_F0F4 ()
1950 {
1951   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
1952 }
1953
1954 /* jmp label:16 */
1955 void OP_CC0000 ()
1956 {
1957   State.pc += SEXT16 (insn & 0xffff) - 3;
1958 }
1959
1960 /* jmp label:32 */
1961 void OP_DC000000 ()
1962 {
1963   State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
1964 }
1965
1966 /* call label:16,reg_list,imm8 */
1967 void OP_CD000000 ()
1968 {
1969   unsigned int next_pc, sp, adjust;
1970   unsigned long mask;
1971
1972   sp = State.regs[REG_SP];
1973   next_pc = State.pc + 2;
1974   State.mem[sp] = next_pc & 0xff;
1975   State.mem[sp+1] = next_pc & 0xff00;
1976   State.mem[sp+2] = next_pc & 0xff0000;
1977   State.mem[sp+3] = next_pc & 0xff000000;
1978
1979   mask = insn & 0xff;
1980
1981   adjust = 0;
1982   if (mask & 0x80)
1983     {
1984       adjust -= 4;
1985       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
1986     }
1987
1988   if (mask & 0x40)
1989     {
1990       adjust -= 4;
1991       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
1992     }
1993
1994   if (mask & 0x20)
1995     {
1996       adjust -= 4;
1997       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
1998     }
1999
2000   if (mask & 0x10)
2001     {
2002       adjust -= 4;
2003       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2004     }
2005
2006   if (mask & 0x8)
2007     {
2008       adjust -= 4;
2009       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2010       adjust -= 4;
2011       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2012       adjust -= 4;
2013       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2014       adjust -= 4;
2015       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2016       adjust -= 4;
2017       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2018       adjust -= 4;
2019       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2020       adjust -= 4;
2021       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2022       adjust -= 4;
2023     }
2024
2025   /* And make sure to update the stack pointer.  */
2026   State.regs[REG_SP] -= extension;
2027   State.regs[REG_MDR] = next_pc;
2028   State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2029 }
2030
2031 /* call label:32,reg_list,imm8*/
2032 void OP_DD000000 ()
2033 {
2034   unsigned int next_pc, sp, adjust;
2035   unsigned long mask;
2036
2037   sp = State.regs[REG_SP];
2038   next_pc = State.pc + 2;
2039   State.mem[sp] = next_pc & 0xff;
2040   State.mem[sp+1] = next_pc & 0xff00;
2041   State.mem[sp+2] = next_pc & 0xff0000;
2042   State.mem[sp+3] = next_pc & 0xff000000;
2043
2044   mask = (extension & 0xff00) >> 8;
2045
2046   adjust = 0;
2047   if (mask & 0x80)
2048     {
2049       adjust -= 4;
2050       State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2051     }
2052
2053   if (mask & 0x40)
2054     {
2055       adjust -= 4;
2056       State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2057     }
2058
2059   if (mask & 0x20)
2060     {
2061       adjust -= 4;
2062       State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2063     }
2064
2065   if (mask & 0x10)
2066     {
2067       adjust -= 4;
2068       State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2069     }
2070
2071   if (mask & 0x8)
2072     {
2073       adjust -= 4;
2074       State.regs[REG_D0] = load_mem (sp + adjust, 4);
2075       adjust -= 4;
2076       State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2077       adjust -= 4;
2078       State.regs[REG_A0] = load_mem (sp + adjust, 4);
2079       adjust -= 4;
2080       State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2081       adjust -= 4;
2082       State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2083       adjust -= 4;
2084       State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2085       adjust -= 4;
2086       State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2087       adjust -= 4;
2088     }
2089
2090   /* And make sure to update the stack pointer.  */
2091   State.regs[REG_SP] -= (extension & 0xff);
2092   State.regs[REG_MDR] = next_pc;
2093   State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2094 }
2095
2096 /* calls (an) */
2097 void OP_F0F0 ()
2098 {
2099   unsigned int next_pc, sp;
2100
2101   sp = State.regs[REG_SP];
2102   next_pc = State.pc + 2;
2103   State.mem[sp] = next_pc & 0xff;
2104   State.mem[sp+1] = next_pc & 0xff00;
2105   State.mem[sp+2] = next_pc & 0xff0000;
2106   State.mem[sp+3] = next_pc & 0xff000000;
2107   State.regs[REG_MDR] = next_pc;
2108   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2109 }
2110
2111 /* calls label:16 */
2112 void OP_FAFF0000 ()
2113 {
2114   unsigned int next_pc, sp;
2115
2116   sp = State.regs[REG_SP];
2117   next_pc = State.pc + 4;
2118   State.mem[sp] = next_pc & 0xff;
2119   State.mem[sp+1] = next_pc & 0xff00;
2120   State.mem[sp+2] = next_pc & 0xff0000;
2121   State.mem[sp+3] = next_pc & 0xff000000;
2122   State.regs[REG_MDR] = next_pc;
2123   State.pc += SEXT16 (insn & 0xffff) - 4;
2124 }
2125
2126 /* calls label:32 */
2127 void OP_FCFF0000 ()
2128 {
2129   unsigned int next_pc, sp;
2130
2131   sp = State.regs[REG_SP];
2132   next_pc = State.pc + 6;
2133   State.mem[sp] = next_pc & 0xff;
2134   State.mem[sp+1] = next_pc & 0xff00;
2135   State.mem[sp+2] = next_pc & 0xff0000;
2136   State.mem[sp+3] = next_pc & 0xff000000;
2137   State.regs[REG_MDR] = next_pc;
2138   State.pc += (((insn & 0xffff) << 16) | extension) - 6;
2139 }
2140
2141 /* ret */
2142 void OP_DF0000 ()
2143 {
2144   unsigned int sp;
2145   unsigned long mask;
2146
2147   State.regs[REG_SP] += insn & 0xff;
2148   State.pc = State.regs[REG_MDR] - 3;
2149   sp = State.regs[REG_SP];
2150
2151   mask = (insn & 0xff00) >> 8;
2152
2153   if (mask & 0x8)
2154     {
2155       sp += 4;
2156       State.regs[REG_LAR] = load_mem (sp, 4);
2157       sp += 4;
2158       State.regs[REG_LIR] = load_mem (sp, 4);
2159       sp += 4;
2160       State.regs[REG_MDR] = load_mem (sp, 4);
2161       sp += 4;
2162       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2163       sp += 4;
2164       State.regs[REG_A0] = load_mem (sp, 4);
2165       sp += 4;
2166       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2167       sp += 4;
2168       State.regs[REG_D0] = load_mem (sp, 4);
2169       sp += 4;
2170     }
2171
2172   if (mask & 0x10)
2173     {
2174       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2175       sp += 4;
2176     }
2177
2178   if (mask & 0x20)
2179     {
2180       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2181       sp += 4;
2182     }
2183
2184   if (mask & 0x40)
2185     {
2186       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2187       sp += 4;
2188     }
2189
2190   if (mask & 0x80)
2191     {
2192       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2193       sp += 4;
2194     }
2195 }
2196
2197 /* retf reg_list,imm8 */
2198 void OP_DE0000 ()
2199 {
2200   unsigned int sp;
2201   unsigned long mask;
2202
2203   State.regs[REG_SP] += insn & 0xff;
2204   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2205               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2206   State.pc -= 3;
2207
2208   sp = State.regs[REG_SP];
2209
2210   mask = (insn & 0xff00) >> 8;
2211
2212   if (mask & 0x8)
2213     {
2214       sp += 4;
2215       State.regs[REG_LAR] = load_mem (sp, 4);
2216       sp += 4;
2217       State.regs[REG_LIR] = load_mem (sp, 4);
2218       sp += 4;
2219       State.regs[REG_MDR] = load_mem (sp, 4);
2220       sp += 4;
2221       State.regs[REG_A0 + 1] = load_mem (sp, 4);
2222       sp += 4;
2223       State.regs[REG_A0] = load_mem (sp, 4);
2224       sp += 4;
2225       State.regs[REG_D0 + 1] = load_mem (sp, 4);
2226       sp += 4;
2227       State.regs[REG_D0] = load_mem (sp, 4);
2228       sp += 4;
2229     }
2230
2231   if (mask & 0x10)
2232     {
2233       State.regs[REG_A0 + 3] = load_mem (sp, 4);
2234       sp += 4;
2235     }
2236
2237   if (mask & 0x20)
2238     {
2239       State.regs[REG_A0 + 2] = load_mem (sp, 4);
2240       sp += 4;
2241     }
2242
2243   if (mask & 0x40)
2244     {
2245       State.regs[REG_D0 + 3] = load_mem (sp, 4);
2246       sp += 4;
2247     }
2248
2249   if (mask & 0x80)
2250     {
2251       State.regs[REG_D0 + 2] = load_mem (sp, 4);
2252       sp += 4;
2253     }
2254 }
2255
2256 /* rets */
2257 void OP_F0FC ()
2258 {
2259   unsigned int sp;
2260
2261   sp = State.regs[REG_SP];
2262   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2263               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2264   State.pc -= 2;
2265 }
2266
2267 /* rti */
2268 void OP_F0FD ()
2269 {
2270 }
2271
2272 /* trap */
2273 void OP_F0FE ()
2274 {
2275 }
2276
2277 /* rtm */
2278 void OP_F0FF ()
2279 {
2280 }
2281
2282 /* nop */
2283 void OP_CB ()
2284 {
2285 }
2286
2287 /* putx */
2288 void OP_F500 ()
2289 {
2290 }
2291
2292 /* getx */
2293 void OP_F6F0 ()
2294 {
2295 }
2296
2297 /* mulq */
2298 void OP_F600 ()
2299 {
2300 }
2301
2302 /* mulq */
2303 void OP_F90000 ()
2304 {
2305 }
2306
2307 /* mulq */
2308 void OP_FB000000 ()
2309 {
2310 }
2311
2312 /* mulq */
2313 void OP_FD000000 ()
2314 {
2315 }
2316
2317 /* mulqu */
2318 void OP_F610 ()
2319 {
2320 }
2321
2322 /* mulqu */
2323 void OP_F91400 ()
2324 {
2325 }
2326
2327 /* mulqu */
2328 void OP_FB140000 ()
2329 {
2330 }
2331
2332 /* mulqu */
2333 void OP_FD140000 ()
2334 {
2335 }
2336
2337 /* sat16 */
2338 void OP_F640 ()
2339 {
2340 }
2341
2342 /* sat24 */
2343 void OP_F650 ()
2344 {
2345 }
2346
2347 /* bsch */
2348 void OP_F670 ()
2349 {
2350 }