sim/mn10300/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #ifdef HAVE_UNISTD_H
   5 #include <unistd.h>
   6 #endif
   7 #include "mn10300_sim.h"
   8 #include "simops.h"
   9 #include "sys/syscall.h"
  10 #include "bfd.h"
  11 #include <errno.h>
  12 #include <sys/stat.h>
  13 #include <sys/times.h>
  14 #include <sys/time.h>
  15
  16 enum op_types {
  17   OP_UNKNOWN,
  18 };
  19
  20 #ifdef DEBUG
  21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
  22 static void trace_output PARAMS ((enum op_types result));
  23 static int init_text_p = 0;
  24 static asection *text;
  25 static bfd_vma text_start;
  26 static bfd_vma text_end;
  27 extern bfd *exec_bfd;
  28
  29 #ifndef SIZE_INSTRUCTION
  30 #define SIZE_INSTRUCTION 6
  31 #endif
  32
  33 #ifndef SIZE_OPERANDS
  34 #define SIZE_OPERANDS 16
  35 #endif
  36
  37 #ifndef SIZE_VALUES
  38 #define SIZE_VALUES 11
  39 #endif
  40
  41 #ifndef SIZE_LOCATION
  42 #define SIZE_LOCATION 40
  43 #endif
  44
  45 static void
  46 trace_input (name, type, size)
  47      char *name;
  48      enum op_types type;
  49      int size;
  50 {
  51 }
  52
  53 static void
  54 trace_output (result)
  55      enum op_types result;
  56 {
  57 }
  58
  59 #else
  60 #define trace_input(NAME, IN1, IN2)
  61 #define trace_output(RESULT)
  62 #endif
  63
  64 \f
  65 /* mov */
  66 void OP_8000 ()
  67 {
  68 }
  69
  70 /* mov */
  71 void OP_80 ()
  72 {
  73 }
  74
  75 /* mov */
  76 void OP_F1E0 ()
  77 {
  78 }
  79
  80 /* mov */
  81 void OP_F1D0 ()
  82 {
  83 }
  84
  85 /* mov */
  86 void OP_9000 ()
  87 {
  88 }
  89
  90 /* mov */
  91 void OP_90 ()
  92 {
  93 }
  94
  95 /* mov */
  96 void OP_3C ()
  97 {
  98 }
  99
 100 /* mov am, sp*/
 101 void OP_F2F0 ()
 102 {
 103   State.regs[REG_SP] = State.regs[REG_A0 + (insn & 0x3)];
 104 }
 105
 106 /* mov */
 107 void OP_F2E4 ()
 108 {
 109 }
 110
 111 /* mov */
 112 void OP_F2F3 ()
 113 {
 114 }
 115
 116 /* mov */
 117 void OP_F2E0 ()
 118 {
 119 }
 120
 121 /* mov */
 122 void OP_F2F2 ()
 123 {
 124 }
 125
 126 /* mov */
 127 void OP_70 ()
 128 {
 129 }
 130
 131 /* mov */
 132 void OP_F80000 ()
 133 {
 134 }
 135
 136 /* mov */
 137 void OP_FA000000 ()
 138 {
 139 }
 140
 141 /* mov */
 142 void OP_FC000000 ()
 143 {
 144 }
 145
 146 /* mov */
 147 void OP_5800 ()
 148 {
 149 }
 150
 151 /* mov */
 152 void OP_FAB40000 ()
 153 {
 154 }
 155
 156 /* mov */
 157 void OP_FCB40000 ()
 158 {
 159 }
 160
 161 /* mov */
 162 void OP_F300 ()
 163 {
 164 }
 165
 166 /* mov */
 167 void OP_300000 ()
 168 {
 169 }
 170
 171 /* mov */
 172 void OP_FCA40000 ()
 173 {
 174 }
 175
 176 /* mov */
 177 void OP_F000 ()
 178 {
 179 }
 180
 181 /* mov */
 182 void OP_F82000 ()
 183 {
 184 }
 185
 186 /* mov */
 187 void OP_FA200000 ()
 188 {
 189 }
 190
 191 /* mov */
 192 void OP_FC200000 ()
 193 {
 194 }
 195
 196 /* mov */
 197 void OP_5C00 ()
 198 {
 199 }
 200
 201 /* mov */
 202 void OP_FAB00000 ()
 203 {
 204 }
 205
 206 /* mov */
 207 void OP_FCB00000 ()
 208 {
 209 }
 210
 211 /* mov */
 212 void OP_F380 ()
 213 {
 214 }
 215
 216 /* mov */
 217 void OP_FAA00000 ()
 218 {
 219 }
 220
 221 /* mov */
 222 void OP_FCA00000 ()
 223 {
 224 }
 225
 226 /* mov */
 227 void OP_F8F000 ()
 228 {
 229 }
 230
 231 /* mov */
 232 void OP_60 ()
 233 {
 234 }
 235
 236 /* mov */
 237 void OP_F81000 ()
 238 {
 239 }
 240
 241 /* mov */
 242 void OP_FA100000 ()
 243 {
 244 }
 245
 246 /* mov */
 247 void OP_FC100000 ()
 248 {
 249 }
 250
 251 /* mov */
 252 void OP_4200 ()
 253 {
 254 }
 255
 256 /* mov */
 257 void OP_FA910000 ()
 258 {
 259 }
 260
 261 /* mov */
 262 void OP_FC910000 ()
 263 {
 264 }
 265
 266 /* mov */
 267 void OP_F340 ()
 268 {
 269 }
 270
 271 /* mov */
 272 void OP_10000 ()
 273 {
 274 }
 275
 276 /* mov */
 277 void OP_FC810000 ()
 278 {
 279 }
 280
 281 /* mov */
 282 void OP_F010 ()
 283 {
 284 }
 285
 286 /* mov */
 287 void OP_F83000 ()
 288 {
 289 }
 290
 291 /* mov */
 292 void OP_FA300000 ()
 293 {
 294 }
 295
 296 /* mov */
 297 void OP_FC300000 ()
 298 {
 299 }
 300
 301 /* mov */
 302 void OP_4300 ()
 303 {
 304 }
 305
 306 /* mov */
 307 void OP_FA900000 ()
 308 {
 309 }
 310
 311 /* mov */
 312 void OP_FC900000 ()
 313 {
 314 }
 315
 316 /* mov */
 317 void OP_F3C0 ()
 318 {
 319 }
 320
 321 /* mov */
 322 void OP_FA800000 ()
 323 {
 324 }
 325
 326 /* mov */
 327 void OP_FC800000 ()
 328 {
 329 }
 330
 331 /* mov */
 332 void OP_F8F400 ()
 333 {
 334 }
 335
 336 /* mov */
 337 void OP_2C0000 ()
 338 {
 339 }
 340
 341 /* mov */
 342 void OP_FCCC0000 ()
 343 {
 344 }
 345
 346 /* mov */
 347 void OP_240000 ()
 348 {
 349 }
 350
 351 /* mov imm32, an*/
 352 void OP_FCDC0000 ()
 353 {
 354   unsigned long value;
 355
 356   value = (insn & 0xffff) << 16 | extension;
 357   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 358 }
 359
 360 /* movbu */
 361 void OP_F040 ()
 362 {
 363 }
 364
 365 /* movbu */
 366 void OP_F84000 ()
 367 {
 368 }
 369
 370 /* movbu */
 371 void OP_FA400000 ()
 372 {
 373 }
 374
 375 /* movbu */
 376 void OP_FC400000 ()
 377 {
 378 }
 379
 380 /* movbu */
 381 void OP_F8B800 ()
 382 {
 383 }
 384
 385 /* movbu */
 386 void OP_FAB80000 ()
 387 {
 388 }
 389
 390 /* movbu */
 391 void OP_FCB80000 ()
 392 {
 393 }
 394
 395 /* movbu */
 396 void OP_F400 ()
 397 {
 398 }
 399
 400 /* movbu */
 401 void OP_340000 ()
 402 {
 403 }
 404
 405 /* movbu */
 406 void OP_FCA80000 ()
 407 {
 408 }
 409
 410 /* movbu dm,(an) */
 411 void OP_F050 ()
 412 {
 413   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
 414              State.regs[REG_D0 + (insn & 0x3)]);
 415 }
 416
 417 /* movbu */
 418 void OP_F85000 ()
 419 {
 420 }
 421
 422 /* movbu */
 423 void OP_FA500000 ()
 424 {
 425 }
 426
 427 /* movbu */
 428 void OP_FC500000 ()
 429 {
 430 }
 431
 432 /* movbu */
 433 void OP_F89200 ()
 434 {
 435 }
 436
 437 /* movbu */
 438 void OP_FA920000 ()
 439 {
 440 }
 441
 442 /* movbu */
 443 void OP_FC920000 ()
 444 {
 445 }
 446
 447 /* movbu */
 448 void OP_F440 ()
 449 {
 450 }
 451
 452 /* movbu */
 453 void OP_20000 ()
 454 {
 455 }
 456
 457 /* movbu */
 458 void OP_FC820000 ()
 459 {
 460 }
 461
 462 /* movhu */
 463 void OP_F060 ()
 464 {
 465 }
 466
 467 /* movhu */
 468 void OP_F86000 ()
 469 {
 470 }
 471
 472 /* movhu */
 473 void OP_FA600000 ()
 474 {
 475 }
 476
 477 /* movhu */
 478 void OP_FC600000 ()
 479 {
 480 }
 481
 482 /* movhu */
 483 void OP_F8BC00 ()
 484 {
 485 }
 486
 487 /* movhu */
 488 void OP_FABC0000 ()
 489 {
 490 }
 491
 492 /* movhu */
 493 void OP_FCBC0000 ()
 494 {
 495 }
 496
 497 /* movhu */
 498 void OP_F480 ()
 499 {
 500 }
 501
 502 /* movhu */
 503 void OP_380000 ()
 504 {
 505 }
 506
 507 /* movhu */
 508 void OP_FCAC0000 ()
 509 {
 510 }
 511
 512 /* movhu */
 513 void OP_F070 ()
 514 {
 515 }
 516
 517 /* movhu */
 518 void OP_F87000 ()
 519 {
 520 }
 521
 522 /* movhu */
 523 void OP_FA700000 ()
 524 {
 525 }
 526
 527 /* movhu */
 528 void OP_FC700000 ()
 529 {
 530 }
 531
 532 /* movhu */
 533 void OP_F89300 ()
 534 {
 535 }
 536
 537 /* movhu */
 538 void OP_FA930000 ()
 539 {
 540 }
 541
 542 /* movhu */
 543 void OP_FC930000 ()
 544 {
 545 }
 546
 547 /* movhu */
 548 void OP_F4C0 ()
 549 {
 550 }
 551
 552 /* movhu */
 553 void OP_30000 ()
 554 {
 555 }
 556
 557 /* movhu */
 558 void OP_FC830000 ()
 559 {
 560 }
 561
 562 /* ext */
 563 void OP_F2D0 ()
 564 {
 565 }
 566
 567 /* extb */
 568 void OP_10 ()
 569 {
 570 }
 571
 572 /* extbu */
 573 void OP_14 ()
 574 {
 575 }
 576
 577 /* exth */
 578 void OP_18 ()
 579 {
 580 }
 581
 582 /* exthu */
 583 void OP_1C ()
 584 {
 585 }
 586
 587 /* movm */
 588 void OP_CE00 ()
 589 {
 590 }
 591
 592 /* movm */
 593 void OP_CF00 ()
 594 {
 595 }
 596
 597 /* clr dn */
 598 void OP_0 ()
 599 {
 600   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
 601
 602   PSW |= PSW_Z;
 603   PSW &= ~(PSW_V | PSW_C | PSW_N);
 604 }
 605
 606 /* add dm,dn*/
 607 void OP_E0 ()
 608 {
 609   int z, c, n, v;
 610   unsigned long reg1, reg2, value;
 611
 612   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 613   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 614   value = reg1 + reg2;
 615   State.regs[REG_D0 + (insn & 0x3)] = value;
 616
 617   z = (value == 0);
 618   n = (value & 0x80000000);
 619   c = (reg1 < reg2);
 620   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 621        && (reg2 & 0x8000000) != (value & 0x80000000));
 622
 623   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 624   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 625           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 626 }
 627
 628 /* add dm, an */
 629 void OP_F160 ()
 630 {
 631   int z, c, n, v;
 632   unsigned long reg1, reg2, value;
 633
 634   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 635   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 636   value = reg1 + reg2;
 637   State.regs[REG_A0 + (insn & 0x3)] = value;
 638
 639   z = (value == 0);
 640   n = (value & 0x80000000);
 641   c = (reg1 < reg2);
 642   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 643        && (reg2 & 0x8000000) != (value & 0x80000000));
 644
 645   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 646   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 647           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 648 }
 649
 650 /* add am, dn*/
 651 void OP_F150 ()
 652 {
 653   int z, c, n, v;
 654   unsigned long reg1, reg2, value;
 655
 656   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 657   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 658   value = reg1 + reg2;
 659   State.regs[REG_D0 + (insn & 0x3)] = value;
 660
 661   z = (value == 0);
 662   n = (value & 0x80000000);
 663   c = (reg1 < reg2);
 664   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 665        && (reg2 & 0x8000000) != (value & 0x80000000));
 666
 667   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 668   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 669           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 670 }
 671
 672 /* add am,an */
 673 void OP_F170 ()
 674 {
 675   int z, c, n, v;
 676   unsigned long reg1, reg2, value;
 677
 678   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 679   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 680   value = reg1 + reg2;
 681   State.regs[REG_A0 + (insn & 0x3)] = value;
 682
 683   z = (value == 0);
 684   n = (value & 0x80000000);
 685   c = (reg1 < reg2);
 686   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 687        && (reg2 & 0x8000000) != (value & 0x80000000));
 688
 689   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 690   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 691           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 692 }
 693
 694 /* add imm8, dn */
 695 void OP_2800 ()
 696 {
 697   int z, c, n, v;
 698   unsigned long reg1, imm, value;
 699
 700   reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
 701   imm = SEXT8 (insn & 0xff);
 702   value = reg1 + imm;
 703   State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
 704
 705   z = (value == 0);
 706   n = (value & 0x80000000);
 707   c = (reg1 < imm);
 708   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 709        && (imm & 0x8000000) != (value & 0x80000000));
 710
 711   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 712   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 713           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 714 }
 715
 716 /* add imm16, dn */
 717 void OP_FAC00000 ()
 718 {
 719   int z, c, n, v;
 720   unsigned long reg1, imm, value;
 721
 722   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 723   imm = SEXT16 (insn & 0xffff);
 724   value = reg1 + imm;
 725   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 726
 727   z = (value == 0);
 728   n = (value & 0x80000000);
 729   c = (reg1 < imm);
 730   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 731        && (imm & 0x8000000) != (value & 0x80000000));
 732
 733   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 734   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 735           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 736 }
 737
 738 /* add imm32,dn */
 739 void OP_FCC00000 ()
 740 {
 741   int z, c, n, v;
 742   unsigned long reg1, imm, value;
 743
 744   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 745   imm = ((insn & 0xffff) << 16) | extension;
 746   value = reg1 + imm;
 747   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 748
 749   z = (value == 0);
 750   n = (value & 0x80000000);
 751   c = (reg1 < imm);
 752   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 753        && (imm & 0x8000000) != (value & 0x80000000));
 754
 755   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 756   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 757           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 758 }
 759
 760 /* add imm8, an */
 761 void OP_2000 ()
 762 {
 763   int z, c, n, v;
 764   unsigned long reg1, imm, value;
 765
 766   reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
 767   imm = insn & 0xff;
 768   value = reg1 + imm;
 769   State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
 770
 771   z = (value == 0);
 772   n = (value & 0x80000000);
 773   c = (reg1 < imm);
 774   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 775        && (imm & 0x8000000) != (value & 0x80000000));
 776
 777   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 778   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 779           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 780 }
 781
 782 /* add imm16, an */
 783 void OP_FAD00000 ()
 784 {
 785   int z, c, n, v;
 786   unsigned long reg1, imm, value;
 787
 788   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 789   imm = 0xffff;
 790   value = reg1 + imm;
 791   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 792
 793   z = (value == 0);
 794   n = (value & 0x80000000);
 795   c = (reg1 < imm);
 796   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 797        && (imm & 0x8000000) != (value & 0x80000000));
 798
 799   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 800   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 801           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 802 }
 803
 804 /* add imm32, an */
 805 void OP_FCD00000 ()
 806 {
 807   int z, c, n, v;
 808   unsigned long reg1, imm, value;
 809
 810   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 811   imm = ((insn & 0xffff) << 16) | extension;
 812   value = reg1 + imm;
 813   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 814
 815   z = (value == 0);
 816   n = (value & 0x80000000);
 817   c = (reg1 < imm);
 818   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 819        && (imm & 0x8000000) != (value & 0x80000000));
 820
 821   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 822   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 823           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 824 }
 825
 826 /* add imm8, sp*/
 827 void OP_F8FE00 ()
 828 {
 829   int z, c, n, v;
 830   unsigned long reg1, imm, value;
 831
 832   reg1 = State.regs[REG_SP];
 833   imm = SEXT8 (insn & 0xff);
 834   value = reg1 + imm;
 835   State.regs[REG_SP] = value;
 836
 837   z = (value == 0);
 838   n = (value & 0x80000000);
 839   c = (reg1 < imm);
 840   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 841        && (imm & 0x8000000) != (value & 0x80000000));
 842
 843   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 844   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 845           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 846 }
 847
 848 /* add imm16,sp */
 849 void OP_FAFE0000 ()
 850 {
 851   int z, c, n, v;
 852   unsigned long reg1, imm, value;
 853
 854   reg1 = State.regs[REG_SP];
 855   imm = SEXT16 (insn & 0xffff);
 856   value = reg1 + imm;
 857   State.regs[REG_SP] = value;
 858
 859   z = (value == 0);
 860   n = (value & 0x80000000);
 861   c = (reg1 < imm);
 862   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 863        && (imm & 0x8000000) != (value & 0x80000000));
 864
 865   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 866   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 867           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 868 }
 869
 870 /* add */
 871 void OP_FCFE0000 ()
 872 {
 873   int z, c, n, v;
 874   unsigned long reg1, imm, value;
 875
 876   reg1 = State.regs[REG_SP];
 877   imm = ((insn & 0xffff) << 16) | extension;
 878   value = reg1 + imm;
 879   State.regs[REG_SP] = value;
 880
 881   z = (value == 0);
 882   n = (value & 0x80000000);
 883   c = (reg1 < imm);
 884   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 885        && (imm & 0x8000000) != (value & 0x80000000));
 886
 887   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 888   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 889           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 890 }
 891
 892 /* addc */
 893 void OP_F140 ()
 894 {
 895   int z, c, n, v;
 896   unsigned long reg1, reg2, value;
 897
 898   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 899   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 900   value = reg1 + reg2 + ((PSW & PSW_C) != 0);
 901   State.regs[REG_D0 + (insn & 0x3)] = value;
 902
 903   z = (value == 0);
 904   n = (value & 0x80000000);
 905   c = (reg1 < reg2);
 906   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 907        && (reg2 & 0x8000000) != (value & 0x80000000));
 908
 909   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 910   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 911           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 912 }
 913
 914 /* sub */
 915 void OP_F100 ()
 916 {
 917 }
 918
 919 /* sub */
 920 void OP_F120 ()
 921 {
 922 }
 923
 924 /* sub */
 925 void OP_F110 ()
 926 {
 927 }
 928
 929 /* sub */
 930 void OP_F130 ()
 931 {
 932 }
 933
 934 /* sub */
 935 void OP_FCC40000 ()
 936 {
 937 }
 938
 939 /* sub */
 940 void OP_FCD40000 ()
 941 {
 942 }
 943
 944 /* subc */
 945 void OP_F180 ()
 946 {
 947 }
 948
 949 /* mul */
 950 void OP_F240 ()
 951 {
 952 }
 953
 954 /* mulu */
 955 void OP_F250 ()
 956 {
 957 }
 958
 959 /* div */
 960 void OP_F260 ()
 961 {
 962 }
 963
 964 /* divu */
 965 void OP_F270 ()
 966 {
 967 }
 968
 969 /* inc dn */
 970 void OP_40 ()
 971 {
 972   State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
 973 }
 974
 975 /* inc an */
 976 void OP_41 ()
 977 {
 978   State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
 979 }
 980
 981 /* inc4 */
 982 void OP_50 ()
 983 {
 984   State.regs[REG_A0 + (insn & 0x3)] += 4;
 985 }
 986
 987 /* cmp */
 988 void OP_A000 ()
 989 {
 990 }
 991
 992 /* cmp */
 993 void OP_A0 ()
 994 {
 995 }
 996
 997 /* cmp */
 998 void OP_F1A0 ()
 999 {
1000 }
1001
1002 /* cmp */
1003 void OP_F190 ()
1004 {
1005 }
1006
1007 /* cmp */
1008 void OP_B000 ()
1009 {
1010 }
1011
1012 /* cmp am,an */
1013 void OP_B0 ()
1014 {
1015   int z, c, n, v;
1016   unsigned long reg1, reg2, value;
1017
1018   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1019   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1020   value = reg1 - reg2;
1021
1022   z = (value == 0);
1023   n = (value & 0x80000000);
1024   c = (reg1 < reg2);
1025   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1026        && (reg2 & 0x8000000) != (value & 0x80000000));
1027
1028   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1029   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1030           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1031 }
1032
1033 /* cmp */
1034 void OP_FAC80000 ()
1035 {
1036 }
1037
1038 /* cmp */
1039 void OP_FCC80000 ()
1040 {
1041 }
1042
1043 /* cmp */
1044 void OP_FAD80000 ()
1045 {
1046 }
1047
1048 /* cmp */
1049 void OP_FCD80000 ()
1050 {
1051 }
1052
1053 /* and */
1054 void OP_F200 ()
1055 {
1056 }
1057
1058 /* and */
1059 void OP_F8E000 ()
1060 {
1061 }
1062
1063 /* and */
1064 void OP_FAE00000 ()
1065 {
1066 }
1067
1068 /* and */
1069 void OP_FCE00000 ()
1070 {
1071 }
1072
1073 /* and */
1074 void OP_FAFC0000 ()
1075 {
1076 }
1077
1078 /* or */
1079 void OP_F210 ()
1080 {
1081 }
1082
1083 /* or */
1084 void OP_F8E400 ()
1085 {
1086 }
1087
1088 /* or */
1089 void OP_FAE40000 ()
1090 {
1091 }
1092
1093 /* or */
1094 void OP_FCE40000 ()
1095 {
1096 }
1097
1098 /* or */
1099 void OP_FAFD0000 ()
1100 {
1101 }
1102
1103 /* xor */
1104 void OP_F220 ()
1105 {
1106 }
1107
1108 /* xor */
1109 void OP_FAE80000 ()
1110 {
1111 }
1112
1113 /* xor */
1114 void OP_FCE80000 ()
1115 {
1116 }
1117
1118 /* not */
1119 void OP_F230 ()
1120 {
1121 }
1122
1123 /* btst */
1124 void OP_F8EC00 ()
1125 {
1126 }
1127
1128 /* btst */
1129 void OP_FAEC0000 ()
1130 {
1131 }
1132
1133 /* btst */
1134 void OP_FCEC0000 ()
1135 {
1136 }
1137
1138 /* btst */
1139 void OP_FE020000 ()
1140 {
1141 }
1142
1143 /* btst */
1144 void OP_FAF80000 ()
1145 {
1146 }
1147
1148 /* btst */
1149 void OP_F080 ()
1150 {
1151 }
1152
1153 /* btst */
1154 void OP_FE000000 ()
1155 {
1156 }
1157
1158 /* btst */
1159 void OP_FAF00000 ()
1160 {
1161 }
1162
1163 /* bclr */
1164 void OP_F090 ()
1165 {
1166 }
1167
1168 /* bclr */
1169 void OP_FE010000 ()
1170 {
1171 }
1172
1173 /* bclr */
1174 void OP_FAF40000 ()
1175 {
1176 }
1177
1178 /* asr */
1179 void OP_F2B0 ()
1180 {
1181 }
1182
1183 /* asr */
1184 void OP_F8C800 ()
1185 {
1186 }
1187
1188 /* lsr */
1189 void OP_F2A0 ()
1190 {
1191 }
1192
1193 /* lsr */
1194 void OP_F8C400 ()
1195 {
1196 }
1197
1198 /* asl */
1199 void OP_F290 ()
1200 {
1201 }
1202
1203 /* asl */
1204 void OP_F8C000 ()
1205 {
1206 }
1207
1208 /* asl2 */
1209 void OP_54 ()
1210 {
1211 }
1212
1213 /* ror */
1214 void OP_F284 ()
1215 {
1216 }
1217
1218 /* rol */
1219 void OP_F280 ()
1220 {
1221 }
1222
1223 /* beq */
1224 void OP_C800 ()
1225 {
1226   /* The dispatching code will add 2 after we return, so
1227      we subtract two here to make things right.  */
1228   if (PSW & PSW_Z)
1229     State.pc += SEXT8 (insn & 0xff) - 2;
1230 }
1231
1232 /* bne */
1233 void OP_C900 ()
1234 {
1235   /* The dispatching code will add 2 after we return, so
1236      we subtract two here to make things right.  */
1237   if (!(PSW & PSW_Z))
1238     State.pc += SEXT8 (insn & 0xff) - 2;
1239 }
1240
1241 /* bgt */
1242 void OP_C100 ()
1243 {
1244 }
1245
1246 /* bge */
1247 void OP_C200 ()
1248 {
1249 }
1250
1251 /* ble */
1252 void OP_C300 ()
1253 {
1254 }
1255
1256 /* blt */
1257 void OP_C000 ()
1258 {
1259 }
1260
1261 /* bhi */
1262 void OP_C500 ()
1263 {
1264 }
1265
1266 /* bcc */
1267 void OP_C600 ()
1268 {
1269 }
1270
1271 /* bls */
1272 void OP_C700 ()
1273 {
1274 }
1275
1276 /* bcs */
1277 void OP_C400 ()
1278 {
1279 }
1280
1281 /* bvc */
1282 void OP_F8E800 ()
1283 {
1284 }
1285
1286 /* bvs */
1287 void OP_F8E900 ()
1288 {
1289 }
1290
1291 /* bnc */
1292 void OP_F8EA00 ()
1293 {
1294 }
1295
1296 /* bns */
1297 void OP_F8EB00 ()
1298 {
1299 }
1300
1301 /* bra */
1302 void OP_CA00 ()
1303 {
1304 }
1305
1306 /* leq */
1307 void OP_D8 ()
1308 {
1309 }
1310
1311 /* lne */
1312 void OP_D9 ()
1313 {
1314 }
1315
1316 /* lgt */
1317 void OP_D1 ()
1318 {
1319 }
1320
1321 /* lge */
1322 void OP_D2 ()
1323 {
1324 }
1325
1326 /* lle */
1327 void OP_D3 ()
1328 {
1329 }
1330
1331 /* llt */
1332 void OP_D0 ()
1333 {
1334 }
1335
1336 /* lhi */
1337 void OP_D5 ()
1338 {
1339 }
1340
1341 /* lcc */
1342 void OP_D6 ()
1343 {
1344 }
1345
1346 /* lls */
1347 void OP_D7 ()
1348 {
1349 }
1350
1351 /* lcs */
1352 void OP_D4 ()
1353 {
1354 }
1355
1356 /* lra */
1357 void OP_DA ()
1358 {
1359 }
1360
1361 /* setlb */
1362 void OP_DB ()
1363 {
1364 }
1365
1366 /* jmp */
1367 void OP_F0F4 ()
1368 {
1369 }
1370
1371 /* jmp */
1372 void OP_CC0000 ()
1373 {
1374 }
1375
1376 /* jmp */
1377 void OP_DC000000 ()
1378 {
1379 }
1380
1381 /* call */
1382 void OP_CD000000 ()
1383 {
1384 }
1385
1386 /* call */
1387 void OP_DD000000 ()
1388 {
1389 }
1390
1391 /* calls */
1392 void OP_F0F0 ()
1393 {
1394 }
1395
1396 /* calls */
1397 void OP_FAFF0000 ()
1398 {
1399 }
1400
1401 /* calls */
1402 void OP_FCFF0000 ()
1403 {
1404 }
1405
1406 /* ret */
1407 void OP_DF0000 ()
1408 {
1409 }
1410
1411 /* retf */
1412 void OP_DE0000 ()
1413 {
1414 }
1415
1416 /* rets */
1417 void OP_F0FC ()
1418 {
1419 }
1420
1421 /* rti */
1422 void OP_F0FD ()
1423 {
1424 }
1425
1426 /* trap */
1427 void OP_F0FE ()
1428 {
1429 }
1430
1431 /* rtm */
1432 void OP_F0FF ()
1433 {
1434 }
1435
1436 /* nop */
1437 void OP_CB ()
1438 {
1439 }
1440
1441 /* putx */
1442 void OP_F500 ()
1443 {
1444 }
1445
1446 /* getx */
1447 void OP_F6F0 ()
1448 {
1449 }
1450
1451 /* mulq */
1452 void OP_F600 ()
1453 {
1454 }
1455
1456 /* mulq */
1457 void OP_F90000 ()
1458 {
1459 }
1460
1461 /* mulq */
1462 void OP_FB000000 ()
1463 {
1464 }
1465
1466 /* mulq */
1467 void OP_FD000000 ()
1468 {
1469 }
1470
1471 /* mulqu */
1472 void OP_F610 ()
1473 {
1474 }
1475
1476 /* mulqu */
1477 void OP_F91400 ()
1478 {
1479 }
1480
1481 /* mulqu */
1482 void OP_FB140000 ()
1483 {
1484 }
1485
1486 /* mulqu */
1487 void OP_FD140000 ()
1488 {
1489 }
1490
1491 /* sat16 */
1492 void OP_F640 ()
1493 {
1494 }
1495
1496 /* sat24 */
1497 void OP_F650 ()
1498 {
1499 }
1500
1501 /* bsch */
1502 void OP_F670 ()
1503 {
1504 }