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* interp.c: Delete unused global variable "OP".
[binutils-gdb.git] / sim / mn10300 / simops.c
1 #include "config.h"
2
3 #include <signal.h>
4 #ifdef HAVE_UNISTD_H
5 #include <unistd.h>
6 #endif
7 #include "mn10300_sim.h"
8 #include "simops.h"
9 #include "sys/syscall.h"
10 #include "bfd.h"
11 #include <errno.h>
12 #include <sys/stat.h>
13 #include <sys/times.h>
14 #include <sys/time.h>
15
16 enum op_types {
17 OP_UNKNOWN,
18 };
19
20 #ifdef DEBUG
21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
22 static void trace_output PARAMS ((enum op_types result));
23 static int init_text_p = 0;
24 static asection *text;
25 static bfd_vma text_start;
26 static bfd_vma text_end;
27 extern bfd *exec_bfd;
28
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
31 #endif
32
33 #ifndef SIZE_OPERANDS
34 #define SIZE_OPERANDS 16
35 #endif
36
37 #ifndef SIZE_VALUES
38 #define SIZE_VALUES 11
39 #endif
40
41 #ifndef SIZE_LOCATION
42 #define SIZE_LOCATION 40
43 #endif
44
45 static void
46 trace_input (name, type, size)
47 char *name;
48 enum op_types type;
49 int size;
50 {
51 }
52
53 static void
54 trace_output (result)
55 enum op_types result;
56 {
57 }
58
59 #else
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
62 #endif
63
64 \f
65 /* mov imm8, dn */
66 void OP_8000 (insn, extension)
67 unsigned long insn, extension;
68 {
69 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = SEXT8 (insn & 0xff);
70 }
71
72 /* mov dm, dn */
73 void OP_80 (insn, extension)
74 unsigned long insn, extension;
75 {
76 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
77 }
78
79 /* mov dm, an */
80 void OP_F1E0 (insn, extension)
81 unsigned long insn, extension;
82 {
83 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
84 }
85
86 /* mov am, dn */
87 void OP_F1D0 (insn, extension)
88 unsigned long insn, extension;
89 {
90 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
91 }
92
93 /* mov imm8, an */
94 void OP_9000 (insn, extension)
95 unsigned long insn, extension;
96 {
97 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = insn & 0xff;
98 }
99
100 /* mov am, an */
101 void OP_90 (insn, extension)
102 unsigned long insn, extension;
103 {
104 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
105 }
106
107 /* mov sp, an */
108 void OP_3C (insn, extension)
109 unsigned long insn, extension;
110 {
111 State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
112 }
113
114 /* mov am, sp */
115 void OP_F2F0 (insn, extension)
116 unsigned long insn, extension;
117 {
118 State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
119 }
120
121 /* mov psw, dn */
122 void OP_F2E4 (insn, extension)
123 unsigned long insn, extension;
124 {
125 State.regs[REG_D0 + (insn & 0x3)] = PSW;
126 }
127
128 /* mov dm, psw */
129 void OP_F2F3 (insn, extension)
130 unsigned long insn, extension;
131 {
132 PSW = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
133 }
134
135 /* mov mdr, dn */
136 void OP_F2E0 (insn, extension)
137 unsigned long insn, extension;
138 {
139 State.regs[REG_D0 + (insn & 0x3)] = State.regs[REG_MDR];
140 }
141
142 /* mov dm, mdr */
143 void OP_F2F2 (insn, extension)
144 unsigned long insn, extension;
145 {
146 State.regs[REG_MDR] = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
147 }
148
149 /* mov (am), dn */
150 void OP_70 (insn, extension)
151 unsigned long insn, extension;
152 {
153 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
154 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
155 }
156
157 /* mov (d8,am), dn */
158 void OP_F80000 (insn, extension)
159 unsigned long insn, extension;
160 {
161 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
162 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
163 + SEXT8 (insn & 0xff)), 4);
164 }
165
166 /* mov (d16,am), dn */
167 void OP_FA000000 (insn, extension)
168 unsigned long insn, extension;
169 {
170 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
171 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
172 + SEXT16 (insn & 0xffff)), 4);
173 }
174
175 /* mov (d32,am), dn */
176 void OP_FC000000 (insn, extension)
177 unsigned long insn, extension;
178 {
179 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
180 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
181 + ((insn & 0xffff) << 16) + extension), 4);
182 }
183
184 /* mov (d8,sp), dn */
185 void OP_5800 (insn, extension)
186 unsigned long insn, extension;
187 {
188 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
189 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
190 }
191
192 /* mov (d16,sp), dn */
193 void OP_FAB40000 (insn, extension)
194 unsigned long insn, extension;
195 {
196 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
197 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
198 }
199
200 /* mov (d32,sp), dn */
201 void OP_FCB40000 (insn, extension)
202 unsigned long insn, extension;
203 {
204 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
205 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
206 }
207
208 /* mov (di,am), dn */
209 void OP_F300 (insn, extension)
210 unsigned long insn, extension;
211 {
212 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
213 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
214 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
215 }
216
217 /* mov (abs16), dn */
218 void OP_300000 (insn, extension)
219 unsigned long insn, extension;
220 {
221 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
222 }
223
224 /* mov (abs32), dn */
225 void OP_FCA40000 (insn, extension)
226 unsigned long insn, extension;
227 {
228 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
229 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
230 }
231
232 /* mov (am), an */
233 void OP_F000 (insn, extension)
234 unsigned long insn, extension;
235 {
236 State.regs[REG_A0 + ((insn & 0xc) >> 2)]
237 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 4);
238 }
239
240 /* mov (d8,am), an */
241 void OP_F82000 (insn, extension)
242 unsigned long insn, extension;
243 {
244 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]
245 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
246 + SEXT8 (insn & 0xff)), 4);
247 }
248
249 /* mov (d16,am), an */
250 void OP_FA200000 (insn, extension)
251 unsigned long insn, extension;
252 {
253 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
254 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
255 + SEXT16 (insn & 0xffff)), 4);
256 }
257
258 /* mov (d32,am), an */
259 void OP_FC200000 (insn, extension)
260 unsigned long insn, extension;
261 {
262 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]
263 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
264 + ((insn & 0xffff) << 16) + extension), 4);
265 }
266
267 /* mov (d8,sp), an */
268 void OP_5C00 (insn, extension)
269 unsigned long insn, extension;
270 {
271 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
272 = load_mem (State.regs[REG_SP] + (insn & 0xff), 4);
273 }
274
275 /* mov (d16,sp), an */
276 void OP_FAB00000 (insn, extension)
277 unsigned long insn, extension;
278 {
279 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
280 = load_mem (State.regs[REG_SP] + (insn & 0xffff), 4);
281 }
282
283 /* mov (d32,sp), an */
284 void OP_FCB00000 (insn, extension)
285 unsigned long insn, extension;
286 {
287 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
288 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4);
289 }
290
291 /* mov (di,am), an */
292 void OP_F380 (insn, extension)
293 unsigned long insn, extension;
294 {
295 State.regs[REG_A0 + ((insn & 0x300) >> 8)]
296 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
297 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4);
298 }
299
300 /* mov (abs16), an */
301 void OP_FAA00000 (insn, extension)
302 unsigned long insn, extension;
303 {
304 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 4);
305 }
306
307 /* mov (abs32), an */
308 void OP_FCA00000 (insn, extension)
309 unsigned long insn, extension;
310 {
311 State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
312 = load_mem ((((insn & 0xffff) << 16) + extension), 4);
313 }
314
315 /* mov (d8,am), sp */
316 void OP_F8F000 (insn, extension)
317 unsigned long insn, extension;
318 {
319 State.regs[REG_SP]
320 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
321 + SEXT8 (insn & 0xff)), 4);
322 }
323
324 /* mov dm, (an) */
325 void OP_60 (insn, extension)
326 unsigned long insn, extension;
327 {
328 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
329 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
330 }
331
332 /* mov dm, (d8,an) */
333 void OP_F81000 (insn, extension)
334 unsigned long insn, extension;
335 {
336 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
337 + SEXT8 (insn & 0xff)), 4,
338 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
339 }
340
341 /* mov dm (d16,an) */
342 void OP_FA100000 (insn, extension)
343 unsigned long insn, extension;
344 {
345 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
346 + SEXT16 (insn & 0xffff)), 4,
347 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
348 }
349
350 /* mov dm (d32,an) */
351 void OP_FC100000 (insn, extension)
352 unsigned long insn, extension;
353 {
354 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
355 + ((insn & 0xffff) << 16) + extension), 4,
356 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
357 }
358
359 /* mov dm, (d8,sp) */
360 void OP_4200 (insn, extension)
361 unsigned long insn, extension;
362 {
363 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
364 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
365 }
366
367 /* mov dm, (d16,sp) */
368 void OP_FA910000 (insn, extension)
369 unsigned long insn, extension;
370 {
371 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
372 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
373 }
374
375 /* mov dm, (d32,sp) */
376 void OP_FC910000 (insn, extension)
377 unsigned long insn, extension;
378 {
379 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
380 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
381 }
382
383 /* mov dm, (di,an) */
384 void OP_F340 (insn, extension)
385 unsigned long insn, extension;
386 {
387 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
388 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
389 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
390 }
391
392 /* mov dm, (abs16) */
393 void OP_10000 (insn, extension)
394 unsigned long insn, extension;
395 {
396 store_mem ((insn & 0xffff), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
397 }
398
399 /* mov dm, (abs32) */
400 void OP_FC810000 (insn, extension)
401 unsigned long insn, extension;
402 {
403 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
404 }
405
406 /* mov am, (an) */
407 void OP_F010 (insn, extension)
408 unsigned long insn, extension;
409 {
410 store_mem (State.regs[REG_A0 + (insn & 0x3)], 4,
411 State.regs[REG_A0 + ((insn & 0xc) >> 2)]);
412 }
413
414 /* mov am, (d8,an) */
415 void OP_F83000 (insn, extension)
416 unsigned long insn, extension;
417 {
418 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
419 + SEXT8 (insn & 0xff)), 4,
420 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
421 }
422
423 /* mov am, (d16,an) */
424 void OP_FA300000 (insn, extension)
425 unsigned long insn, extension;
426 {
427 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
428 + SEXT16 (insn & 0xffff)), 4,
429 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
430 }
431
432 /* mov am, (d32,an) */
433 void OP_FC300000 (insn, extension)
434 unsigned long insn, extension;
435 {
436 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
437 + ((insn & 0xffff) << 16) + extension), 4,
438 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
439 }
440
441 /* mov am, (d8,sp) */
442 void OP_4300 (insn, extension)
443 unsigned long insn, extension;
444 {
445 store_mem (State.regs[REG_SP] + (insn & 0xff), 4,
446 State.regs[REG_A0 + ((insn & 0xc00) >> 10)]);
447 }
448
449 /* mov am, (d16,sp) */
450 void OP_FA900000 (insn, extension)
451 unsigned long insn, extension;
452 {
453 store_mem (State.regs[REG_SP] + (insn & 0xffff), 4,
454 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
455 }
456
457 /* mov am, (d32,sp) */
458 void OP_FC900000 (insn, extension)
459 unsigned long insn, extension;
460 {
461 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 4,
462 State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
463 }
464
465 /* mov am, (di,an) */
466 void OP_F3C0 (insn, extension)
467 unsigned long insn, extension;
468 {
469 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
470 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 4,
471 State.regs[REG_A0 + ((insn & 0x300) >> 8)]);
472 }
473
474 /* mov am, (abs16) */
475 void OP_FA800000 (insn, extension)
476 unsigned long insn, extension;
477 {
478 store_mem ((insn & 0xffff), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
479 }
480
481 /* mov am, (abs32) */
482 void OP_FC800000 (insn, extension)
483 unsigned long insn, extension;
484 {
485 store_mem ((((insn & 0xffff) << 16) + extension), 4, State.regs[REG_A0 + ((insn & 0xc0000) >> 18)]);
486 }
487
488 /* mov sp, (d8,an) */
489 void OP_F8F400 (insn, extension)
490 unsigned long insn, extension;
491 {
492 store_mem (State.regs[REG_A0 + ((insn & 0x300) >> 8)] + SEXT8 (insn & 0xff),
493 4, State.regs[REG_SP]);
494 }
495
496 /* mov imm16, dn */
497 void OP_2C0000 (insn, extension)
498 unsigned long insn, extension;
499 {
500 unsigned long value;
501
502 value = SEXT16 (insn & 0xffff);
503 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
504 }
505
506 /* mov imm32,dn */
507 void OP_FCCC0000 (insn, extension)
508 unsigned long insn, extension;
509 {
510 unsigned long value;
511
512 value = ((insn & 0xffff) << 16) + extension;
513 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
514 }
515
516 /* mov imm16, an */
517 void OP_240000 (insn, extension)
518 unsigned long insn, extension;
519 {
520 unsigned long value;
521
522 value = insn & 0xffff;
523 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
524 }
525
526 /* mov imm32, an */
527 void OP_FCDC0000 (insn, extension)
528 unsigned long insn, extension;
529 {
530 unsigned long value;
531
532 value = ((insn & 0xffff) << 16) + extension;
533 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
534 }
535
536 /* movbu (am), dn */
537 void OP_F040 (insn, extension)
538 unsigned long insn, extension;
539 {
540 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
541 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 1);
542 }
543
544 /* movbu (d8,am), dn */
545 void OP_F84000 (insn, extension)
546 unsigned long insn, extension;
547 {
548 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
549 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
550 + SEXT8 (insn & 0xff)), 1);
551 }
552
553 /* movbu (d16,am), dn */
554 void OP_FA400000 (insn, extension)
555 unsigned long insn, extension;
556 {
557 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
558 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
559 + SEXT16 (insn & 0xffff)), 1);
560 }
561
562 /* movbu (d32,am), dn */
563 void OP_FC400000 (insn, extension)
564 unsigned long insn, extension;
565 {
566 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
567 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
568 + ((insn & 0xffff) << 16) + extension), 1);
569 }
570
571 /* movbu (d8,sp), dn */
572 void OP_F8B800 (insn, extension)
573 unsigned long insn, extension;
574 {
575 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
576 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 1);
577 }
578
579 /* movbu (d16,sp), dn */
580 void OP_FAB80000 (insn, extension)
581 unsigned long insn, extension;
582 {
583 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
584 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 1);
585 }
586
587 /* movbu (d32,sp), dn */
588 void OP_FCB80000 (insn, extension)
589 unsigned long insn, extension;
590 {
591 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
592 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 1);
593 }
594
595 /* movbu (di,am), dn */
596 void OP_F400 (insn, extension)
597 unsigned long insn, extension;
598 {
599 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
600 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
601 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1);
602 }
603
604 /* movbu (abs16), dn */
605 void OP_340000 (insn, extension)
606 unsigned long insn, extension;
607 {
608 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 1);
609 }
610
611 /* movbu (abs32), dn */
612 void OP_FCA80000 (insn, extension)
613 unsigned long insn, extension;
614 {
615 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
616 = load_mem ((((insn & 0xffff) << 16) + extension), 1);
617 }
618
619 /* movbu dm, (an) */
620 void OP_F050 (insn, extension)
621 unsigned long insn, extension;
622 {
623 store_mem (State.regs[REG_A0 + (insn & 0x3)], 1,
624 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
625 }
626
627 /* movbu dm, (d8,an) */
628 void OP_F85000 (insn, extension)
629 unsigned long insn, extension;
630 {
631 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
632 + SEXT8 (insn & 0xff)), 1,
633 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
634 }
635
636 /* movbu dm, (d16,an) */
637 void OP_FA500000 (insn, extension)
638 unsigned long insn, extension;
639 {
640 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
641 + SEXT16 (insn & 0xffff)), 1,
642 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
643 }
644
645 /* movbu dm, (d32,an) */
646 void OP_FC500000 (insn, extension)
647 unsigned long insn, extension;
648 {
649 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
650 + ((insn & 0xffff) << 16) + extension), 1,
651 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
652 }
653
654 /* movbu dm, (d8,sp) */
655 void OP_F89200 (insn, extension)
656 unsigned long insn, extension;
657 {
658 store_mem (State.regs[REG_SP] + (insn & 0xff), 1,
659 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
660 }
661
662 /* movbu dm, (d16,sp) */
663 void OP_FA920000 (insn, extension)
664 unsigned long insn, extension;
665 {
666 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
667 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
668 }
669
670 /* movbu dm (d32,sp) */
671 void OP_FC920000 (insn, extension)
672 unsigned long insn, extension;
673 {
674 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
675 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
676 }
677
678 /* movbu dm, (di,an) */
679 void OP_F440 (insn, extension)
680 unsigned long insn, extension;
681 {
682 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
683 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 1,
684 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
685 }
686
687 /* movbu dm, (abs16) */
688 void OP_20000 (insn, extension)
689 unsigned long insn, extension;
690 {
691 store_mem ((insn & 0xffff), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
692 }
693
694 /* movbu dm, (abs32) */
695 void OP_FC820000 (insn, extension)
696 unsigned long insn, extension;
697 {
698 store_mem ((((insn & 0xffff) << 16) + extension), 1, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
699 }
700
701 /* movhu (am), dn */
702 void OP_F060 (insn, extension)
703 unsigned long insn, extension;
704 {
705 State.regs[REG_D0 + ((insn & 0xc) >> 2)]
706 = load_mem (State.regs[REG_A0 + (insn & 0x3)], 2);
707 }
708
709 /* movhu (d8,am), dn */
710 void OP_F86000 (insn, extension)
711 unsigned long insn, extension;
712 {
713 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]
714 = load_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
715 + SEXT8 (insn & 0xff)), 2);
716 }
717
718 /* movhu (d16,am), dn */
719 void OP_FA600000 (insn, extension)
720 unsigned long insn, extension;
721 {
722 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
723 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
724 + SEXT16 (insn & 0xffff)), 2);
725 }
726
727 /* movhu (d32,am), dn */
728 void OP_FC600000 (insn, extension)
729 unsigned long insn, extension;
730 {
731 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]
732 = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
733 + ((insn & 0xffff) << 16) + extension), 2);
734 }
735
736 /* movhu (d8,sp) dn */
737 void OP_F8BC00 (insn, extension)
738 unsigned long insn, extension;
739 {
740 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
741 = load_mem ((State.regs[REG_SP] + (insn & 0xff)), 2);
742 }
743
744 /* movhu (d16,sp), dn */
745 void OP_FABC0000 (insn, extension)
746 unsigned long insn, extension;
747 {
748 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
749 = load_mem ((State.regs[REG_SP] + (insn & 0xffff)), 2);
750 }
751
752 /* movhu (d32,sp), dn */
753 void OP_FCBC0000 (insn, extension)
754 unsigned long insn, extension;
755 {
756 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
757 = load_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2);
758 }
759
760 /* movhu (di,am), dn */
761 void OP_F480 (insn, extension)
762 unsigned long insn, extension;
763 {
764 State.regs[REG_D0 + ((insn & 0x300) >> 8)]
765 = load_mem ((State.regs[REG_A0 + (insn & 0x3)]
766 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2);
767 }
768
769 /* movhu (abs16), dn */
770 void OP_380000 (insn, extension)
771 unsigned long insn, extension;
772 {
773 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = load_mem ((insn & 0xffff), 2);
774 }
775
776 /* movhu (abs32), dn */
777 void OP_FCAC0000 (insn, extension)
778 unsigned long insn, extension;
779 {
780 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
781 = load_mem ((((insn & 0xffff) << 16) + extension), 2);
782 }
783
784 /* movhu dm, (an) */
785 void OP_F070 (insn, extension)
786 unsigned long insn, extension;
787 {
788 store_mem (State.regs[REG_A0 + (insn & 0x3)], 2,
789 State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
790 }
791
792 /* movhu dm, (d8,an) */
793 void OP_F87000 (insn, extension)
794 unsigned long insn, extension;
795 {
796 store_mem ((State.regs[REG_A0 + ((insn & 0x300) >> 8)]
797 + SEXT8 (insn & 0xff)), 2,
798 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
799 }
800
801 /* movhu dm, (d16,an) */
802 void OP_FA700000 (insn, extension)
803 unsigned long insn, extension;
804 {
805 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
806 + SEXT16 (insn & 0xffff)), 2,
807 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
808 }
809
810 /* movhu dm, (d32,an) */
811 void OP_FC700000 (insn, extension)
812 unsigned long insn, extension;
813 {
814 store_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
815 + ((insn & 0xffff) << 16) + extension), 2,
816 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
817 }
818
819 /* movhu dm,(d8,sp) */
820 void OP_F89300 (insn, extension)
821 unsigned long insn, extension;
822 {
823 store_mem (State.regs[REG_SP] + (insn & 0xff), 2,
824 State.regs[REG_D0 + ((insn & 0xc00) >> 10)]);
825 }
826
827 /* movhu dm,(d16,sp) */
828 void OP_FA930000 (insn, extension)
829 unsigned long insn, extension;
830 {
831 store_mem (State.regs[REG_SP] + (insn & 0xffff), 2,
832 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
833 }
834
835 /* movhu dm,(d32,sp) */
836 void OP_FC930000 (insn, extension)
837 unsigned long insn, extension;
838 {
839 store_mem (State.regs[REG_SP] + (((insn & 0xffff) << 16) + extension), 2,
840 State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
841 }
842
843 /* movhu dm, (di,an) */
844 void OP_F4C0 (insn, extension)
845 unsigned long insn, extension;
846 {
847 store_mem ((State.regs[REG_A0 + (insn & 0x3)]
848 + State.regs[REG_D0 + ((insn & 0xc) >> 2)]), 2,
849 State.regs[REG_D0 + ((insn & 0x300) >> 8)]);
850 }
851
852 /* movhu dm, (abs16) */
853 void OP_30000 (insn, extension)
854 unsigned long insn, extension;
855 {
856 store_mem ((insn & 0xffff), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
857 }
858
859 /* movhu dm, (abs32) */
860 void OP_FC830000 (insn, extension)
861 unsigned long insn, extension;
862 {
863 store_mem ((((insn & 0xffff) << 16) + extension), 2, State.regs[REG_D0 + ((insn & 0xc0000) >> 18)]);
864 }
865
866 /* ext dn */
867 void OP_F2D0 (insn, extension)
868 unsigned long insn, extension;
869 {
870 if (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000)
871 State.regs[REG_MDR] = -1;
872 else
873 State.regs[REG_MDR] = 0;
874 }
875
876 /* extb dn */
877 void OP_10 (insn, extension)
878 unsigned long insn, extension;
879 {
880 State.regs[REG_D0 + (insn & 0x3)] = SEXT8 (State.regs[REG_D0 + (insn & 0x3)]);
881 }
882
883 /* extbu dn */
884 void OP_14 (insn, extension)
885 unsigned long insn, extension;
886 {
887 State.regs[REG_D0 + (insn & 0x3)] &= 0xff;
888 }
889
890 /* exth dn */
891 void OP_18 (insn, extension)
892 unsigned long insn, extension;
893 {
894 State.regs[REG_D0 + (insn & 0x3)]
895 = SEXT16 (State.regs[REG_D0 + (insn & 0x3)]);
896 }
897
898 /* exthu dn */
899 void OP_1C (insn, extension)
900 unsigned long insn, extension;
901 {
902 State.regs[REG_D0 + (insn & 0x3)] &= 0xffff;
903 }
904
905 /* movm (sp), reg_list */
906 void OP_CE00 (insn, extension)
907 unsigned long insn, extension;
908 {
909 unsigned long sp = State.regs[REG_SP];
910 unsigned long mask;
911
912 mask = insn & 0xff;
913
914 if (mask & 0x8)
915 {
916 sp += 4;
917 State.regs[REG_LAR] = load_mem (sp, 4);
918 sp += 4;
919 State.regs[REG_LIR] = load_mem (sp, 4);
920 sp += 4;
921 State.regs[REG_MDR] = load_mem (sp, 4);
922 sp += 4;
923 State.regs[REG_A0 + 1] = load_mem (sp, 4);
924 sp += 4;
925 State.regs[REG_A0] = load_mem (sp, 4);
926 sp += 4;
927 State.regs[REG_D0 + 1] = load_mem (sp, 4);
928 sp += 4;
929 State.regs[REG_D0] = load_mem (sp, 4);
930 sp += 4;
931 }
932
933 if (mask & 0x10)
934 {
935 State.regs[REG_A0 + 3] = load_mem (sp, 4);
936 sp += 4;
937 }
938
939 if (mask & 0x20)
940 {
941 State.regs[REG_A0 + 2] = load_mem (sp, 4);
942 sp += 4;
943 }
944
945 if (mask & 0x40)
946 {
947 State.regs[REG_D0 + 3] = load_mem (sp, 4);
948 sp += 4;
949 }
950
951 if (mask & 0x80)
952 {
953 State.regs[REG_D0 + 2] = load_mem (sp, 4);
954 sp += 4;
955 }
956
957 /* And make sure to update the stack pointer. */
958 State.regs[REG_SP] = sp;
959 }
960
961 /* movm reg_list, (sp) */
962 void OP_CF00 (insn, extension)
963 unsigned long insn, extension;
964 {
965 unsigned long sp = State.regs[REG_SP];
966 unsigned long mask;
967
968 mask = insn & 0xff;
969
970 if (mask & 0x80)
971 {
972 sp -= 4;
973 store_mem (sp, 4, State.regs[REG_D0 + 2]);
974 }
975
976 if (mask & 0x40)
977 {
978 sp -= 4;
979 store_mem (sp, 4, State.regs[REG_D0 + 3]);
980 }
981
982 if (mask & 0x20)
983 {
984 sp -= 4;
985 store_mem (sp, 4, State.regs[REG_A0 + 2]);
986 }
987
988 if (mask & 0x10)
989 {
990 sp -= 4;
991 store_mem (sp, 4, State.regs[REG_A0 + 3]);
992 }
993
994 if (mask & 0x8)
995 {
996 sp -= 4;
997 store_mem (sp, 4, State.regs[REG_D0]);
998 sp -= 4;
999 store_mem (sp, 4, State.regs[REG_D0 + 1]);
1000 sp -= 4;
1001 store_mem (sp, 4, State.regs[REG_A0]);
1002 sp -= 4;
1003 store_mem (sp, 4, State.regs[REG_A0 + 1]);
1004 sp -= 4;
1005 store_mem (sp, 4, State.regs[REG_MDR]);
1006 sp -= 4;
1007 store_mem (sp, 4, State.regs[REG_LIR]);
1008 sp -= 4;
1009 store_mem (sp, 4, State.regs[REG_LAR]);
1010 sp -= 4;
1011 }
1012
1013 /* And make sure to update the stack pointer. */
1014 State.regs[REG_SP] = sp;
1015 }
1016
1017 /* clr dn */
1018 void OP_0 (insn, extension)
1019 unsigned long insn, extension;
1020 {
1021 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
1022
1023 PSW |= PSW_Z;
1024 PSW &= ~(PSW_V | PSW_C | PSW_N);
1025 }
1026
1027 /* add dm,dn */
1028 void OP_E0 (insn, extension)
1029 unsigned long insn, extension;
1030 {
1031 int z, c, n, v;
1032 unsigned long reg1, reg2, value;
1033
1034 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1035 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1036 value = reg1 + reg2;
1037 State.regs[REG_D0 + (insn & 0x3)] = value;
1038
1039 z = (value == 0);
1040 n = (value & 0x80000000);
1041 c = (reg1 < reg2);
1042 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1043 && (reg2 & 0x80000000) != (value & 0x80000000));
1044
1045 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1046 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1047 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1048 }
1049
1050 /* add dm, an */
1051 void OP_F160 (insn, extension)
1052 unsigned long insn, extension;
1053 {
1054 int z, c, n, v;
1055 unsigned long reg1, reg2, value;
1056
1057 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1058 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1059 value = reg1 + reg2;
1060 State.regs[REG_A0 + (insn & 0x3)] = value;
1061
1062 z = (value == 0);
1063 n = (value & 0x80000000);
1064 c = (reg1 < reg2);
1065 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1066 && (reg2 & 0x80000000) != (value & 0x80000000));
1067
1068 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1069 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1070 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1071 }
1072
1073 /* add am, dn */
1074 void OP_F150 (insn, extension)
1075 unsigned long insn, extension;
1076 {
1077 int z, c, n, v;
1078 unsigned long reg1, reg2, value;
1079
1080 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1081 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1082 value = reg1 + reg2;
1083 State.regs[REG_D0 + (insn & 0x3)] = value;
1084
1085 z = (value == 0);
1086 n = (value & 0x80000000);
1087 c = (reg1 < reg2);
1088 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1089 && (reg2 & 0x80000000) != (value & 0x80000000));
1090
1091 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1092 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1093 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1094 }
1095
1096 /* add am,an */
1097 void OP_F170 (insn, extension)
1098 unsigned long insn, extension;
1099 {
1100 int z, c, n, v;
1101 unsigned long reg1, reg2, value;
1102
1103 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1104 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1105 value = reg1 + reg2;
1106 State.regs[REG_A0 + (insn & 0x3)] = value;
1107
1108 z = (value == 0);
1109 n = (value & 0x80000000);
1110 c = (reg1 < reg2);
1111 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1112 && (reg2 & 0x80000000) != (value & 0x80000000));
1113
1114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1115 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1116 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1117 }
1118
1119 /* add imm8, dn */
1120 void OP_2800 (insn, extension)
1121 unsigned long insn, extension;
1122 {
1123 int z, c, n, v;
1124 unsigned long reg1, imm, value;
1125
1126 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1127 imm = SEXT8 (insn & 0xff);
1128 value = reg1 + imm;
1129 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = value;
1130
1131 z = (value == 0);
1132 n = (value & 0x80000000);
1133 c = (reg1 < imm);
1134 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1135 && (reg1 & 0x80000000) != (value & 0x80000000));
1136
1137 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1138 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1139 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1140 }
1141
1142 /* add imm16, dn */
1143 void OP_FAC00000 (insn, extension)
1144 unsigned long insn, extension;
1145 {
1146 int z, c, n, v;
1147 unsigned long reg1, imm, value;
1148
1149 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1150 imm = SEXT16 (insn & 0xffff);
1151 value = reg1 + imm;
1152 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1153
1154 z = (value == 0);
1155 n = (value & 0x80000000);
1156 c = (reg1 < imm);
1157 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1158 && (reg1 & 0x80000000) != (value & 0x80000000));
1159
1160 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1161 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1162 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1163 }
1164
1165 /* add imm32,dn */
1166 void OP_FCC00000 (insn, extension)
1167 unsigned long insn, extension;
1168 {
1169 int z, c, n, v;
1170 unsigned long reg1, imm, value;
1171
1172 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1173 imm = ((insn & 0xffff) << 16) + extension;
1174 value = reg1 + imm;
1175 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1176
1177 z = (value == 0);
1178 n = (value & 0x80000000);
1179 c = (reg1 < imm);
1180 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1181 && (reg1 & 0x80000000) != (value & 0x80000000));
1182
1183 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1184 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1185 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1186 }
1187
1188 /* add imm8, an */
1189 void OP_2000 (insn, extension)
1190 unsigned long insn, extension;
1191 {
1192 int z, c, n, v;
1193 unsigned long reg1, imm, value;
1194
1195 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1196 imm = SEXT8 (insn & 0xff);
1197 value = reg1 + imm;
1198 State.regs[REG_A0 + ((insn & 0x300) >> 8)] = value;
1199
1200 z = (value == 0);
1201 n = (value & 0x80000000);
1202 c = (reg1 < imm);
1203 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1204 && (reg1 & 0x80000000) != (value & 0x80000000));
1205
1206 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1207 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1208 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1209 }
1210
1211 /* add imm16, an */
1212 void OP_FAD00000 (insn, extension)
1213 unsigned long insn, extension;
1214 {
1215 int z, c, n, v;
1216 unsigned long reg1, imm, value;
1217
1218 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1219 imm = SEXT16 (insn & 0xffff);
1220 value = reg1 + imm;
1221 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1222
1223 z = (value == 0);
1224 n = (value & 0x80000000);
1225 c = (reg1 < imm);
1226 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1227 && (reg1 & 0x80000000) != (value & 0x80000000));
1228
1229 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1230 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1231 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1232 }
1233
1234 /* add imm32, an */
1235 void OP_FCD00000 (insn, extension)
1236 unsigned long insn, extension;
1237 {
1238 int z, c, n, v;
1239 unsigned long reg1, imm, value;
1240
1241 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1242 imm = ((insn & 0xffff) << 16) + extension;
1243 value = reg1 + imm;
1244 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1245
1246 z = (value == 0);
1247 n = (value & 0x80000000);
1248 c = (reg1 < imm);
1249 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1250 && (reg1 & 0x80000000) != (value & 0x80000000));
1251
1252 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1253 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1254 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1255 }
1256
1257 /* add imm8, sp */
1258 void OP_F8FE00 (insn, extension)
1259 unsigned long insn, extension;
1260 {
1261 unsigned long reg1, imm, value;
1262
1263 reg1 = State.regs[REG_SP];
1264 imm = SEXT8 (insn & 0xff);
1265 value = reg1 + imm;
1266 State.regs[REG_SP] = value;
1267 }
1268
1269 /* add imm16,sp */
1270 void OP_FAFE0000 (insn, extension)
1271 unsigned long insn, extension;
1272 {
1273 unsigned long reg1, imm, value;
1274
1275 reg1 = State.regs[REG_SP];
1276 imm = SEXT16 (insn & 0xffff);
1277 value = reg1 + imm;
1278 State.regs[REG_SP] = value;
1279 }
1280
1281 /* add imm32, sp */
1282 void OP_FCFE0000 (insn, extension)
1283 unsigned long insn, extension;
1284 {
1285 unsigned long reg1, imm, value;
1286
1287 reg1 = State.regs[REG_SP];
1288 imm = ((insn & 0xffff) << 16) + extension;
1289 value = reg1 + imm;
1290 State.regs[REG_SP] = value;
1291 }
1292
1293 /* addc dm,dn */
1294 void OP_F140 (insn, extension)
1295 unsigned long insn, extension;
1296 {
1297 int z, c, n, v;
1298 unsigned long reg1, reg2, value;
1299
1300 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1301 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1302 value = reg1 + reg2 + ((PSW & PSW_C) != 0);
1303 State.regs[REG_D0 + (insn & 0x3)] = value;
1304
1305 z = (value == 0);
1306 n = (value & 0x80000000);
1307 c = (reg1 < reg2);
1308 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1309 && (reg2 & 0x80000000) != (value & 0x80000000));
1310
1311 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1312 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1313 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1314 }
1315
1316 /* sub dm, dn */
1317 void OP_F100 (insn, extension)
1318 unsigned long insn, extension;
1319 {
1320 int z, c, n, v;
1321 unsigned long reg1, reg2, value;
1322
1323 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1324 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1325 value = reg2 - reg1;
1326
1327 z = (value == 0);
1328 n = (value & 0x80000000);
1329 c = (reg1 > reg2);
1330 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1331 && (reg2 & 0x80000000) != (value & 0x80000000));
1332
1333 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1334 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1335 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1336 State.regs[REG_D0 + (insn & 0x3)] = value;
1337 }
1338
1339 /* sub dm, an */
1340 void OP_F120 (insn, extension)
1341 unsigned long insn, extension;
1342 {
1343 int z, c, n, v;
1344 unsigned long reg1, reg2, value;
1345
1346 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1347 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1348 value = reg2 - reg1;
1349
1350 z = (value == 0);
1351 n = (value & 0x80000000);
1352 c = (reg1 > reg2);
1353 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1354 && (reg2 & 0x80000000) != (value & 0x80000000));
1355
1356 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1357 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1358 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1359 State.regs[REG_A0 + (insn & 0x3)] = value;
1360 }
1361
1362 /* sub am, dn */
1363 void OP_F110 (insn, extension)
1364 unsigned long insn, extension;
1365 {
1366 int z, c, n, v;
1367 unsigned long reg1, reg2, value;
1368
1369 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1370 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1371 value = reg2 - reg1;
1372
1373 z = (value == 0);
1374 n = (value & 0x80000000);
1375 c = (reg1 > reg2);
1376 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1377 && (reg2 & 0x80000000) != (value & 0x80000000));
1378
1379 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1380 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1381 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1382 State.regs[REG_D0 + (insn & 0x3)] = value;
1383 }
1384
1385 /* sub am, an */
1386 void OP_F130 (insn, extension)
1387 unsigned long insn, extension;
1388 {
1389 int z, c, n, v;
1390 unsigned long reg1, reg2, value;
1391
1392 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1393 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1394 value = reg2 - reg1;
1395
1396 z = (value == 0);
1397 n = (value & 0x80000000);
1398 c = (reg1 > reg2);
1399 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1400 && (reg2 & 0x80000000) != (value & 0x80000000));
1401
1402 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1403 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1404 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1405 State.regs[REG_A0 + (insn & 0x3)] = value;
1406 }
1407
1408 /* sub imm32, dn */
1409 void OP_FCC40000 (insn, extension)
1410 unsigned long insn, extension;
1411 {
1412 int z, c, n, v;
1413 unsigned long reg1, imm, value;
1414
1415 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1416 imm = ((insn & 0xffff) << 16) + extension;
1417 value = reg1 - imm;
1418
1419 z = (value == 0);
1420 n = (value & 0x80000000);
1421 c = (reg1 < imm);
1422 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1423 && (reg1 & 0x80000000) != (value & 0x80000000));
1424
1425 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1426 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1427 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1428 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] = value;
1429 }
1430
1431 /* sub imm32, an */
1432 void OP_FCD40000 (insn, extension)
1433 unsigned long insn, extension;
1434 {
1435 int z, c, n, v;
1436 unsigned long reg1, imm, value;
1437
1438 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1439 imm = ((insn & 0xffff) << 16) + extension;
1440 value = reg1 - imm;
1441
1442 z = (value == 0);
1443 n = (value & 0x80000000);
1444 c = (reg1 < imm);
1445 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1446 && (reg1 & 0x80000000) != (value & 0x80000000));
1447
1448 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1449 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1450 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1451 State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
1452 }
1453
1454 /* subc dm, dn */
1455 void OP_F180 (insn, extension)
1456 unsigned long insn, extension;
1457 {
1458 int z, c, n, v;
1459 unsigned long reg1, reg2, value;
1460
1461 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1462 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1463 value = reg2 - reg1 - ((PSW & PSW_C) != 0);
1464
1465 z = (value == 0);
1466 n = (value & 0x80000000);
1467 c = (reg1 > reg2);
1468 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1469 && (reg2 & 0x80000000) != (value & 0x80000000));
1470
1471 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1472 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1473 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1474 State.regs[REG_D0 + (insn & 0x3)] = value;
1475 }
1476
1477 /* mul dm, dn */
1478 void OP_F240 (insn, extension)
1479 unsigned long insn, extension;
1480 {
1481 unsigned long long temp;
1482 int n, z;
1483
1484 temp = (State.regs[REG_D0 + (insn & 0x3)]
1485 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1486 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1487 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1488 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1489 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1490 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1491 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1492 }
1493
1494 /* mulu dm, dn */
1495 void OP_F250 (insn, extension)
1496 unsigned long insn, extension;
1497 {
1498 unsigned long long temp;
1499 int n, z;
1500
1501 temp = (State.regs[REG_D0 + (insn & 0x3)]
1502 * State.regs[REG_D0 + ((insn & 0xc) >> 2)]);
1503 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1504 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1505 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1506 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1507 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1508 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1509 }
1510
1511 /* div dm, dn */
1512 void OP_F260 (insn, extension)
1513 unsigned long insn, extension;
1514 {
1515 long long temp;
1516 int n, z;
1517
1518 temp = State.regs[REG_MDR];
1519 temp <<= 32;
1520 temp |= State.regs[REG_D0 + (insn & 0x3)];
1521 State.regs[REG_MDR] = temp % (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1522 temp /= (long)State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1523 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1524 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1525 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1526 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1527 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1528 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1529 }
1530
1531 /* divu dm, dn */
1532 void OP_F270 (insn, extension)
1533 unsigned long insn, extension;
1534 {
1535 unsigned long long temp;
1536 int n, z;
1537
1538 temp = State.regs[REG_MDR];
1539 temp <<= 32;
1540 temp |= State.regs[REG_D0 + (insn & 0x3)];
1541 State.regs[REG_MDR] = temp % State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1542 temp /= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1543 State.regs[REG_D0 + (insn & 0x3)] = temp & 0xffffffff;
1544 State.regs[REG_MDR] = temp & 0xffffffff00000000LL;
1545 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1546 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1547 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1548 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1549 }
1550
1551 /* inc dn */
1552 void OP_40 (insn, extension)
1553 unsigned long insn, extension;
1554 {
1555 int z,n,c,v;
1556 unsigned int value, imm, reg1;
1557
1558 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1559 imm = 1;
1560 value = reg1 + imm;
1561 State.regs[REG_D0 + ((insn & 0xc) >> 2)] = value;
1562
1563 z = (value == 0);
1564 n = (value & 0x80000000);
1565 c = (reg1 < imm);
1566 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1567 && (reg1 & 0x80000000) != (value & 0x80000000));
1568
1569 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1570 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1571 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1572 }
1573
1574 /* inc an */
1575 void OP_41 (insn, extension)
1576 unsigned long insn, extension;
1577 {
1578 State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
1579 }
1580
1581 /* inc4 an */
1582 void OP_50 (insn, extension)
1583 unsigned long insn, extension;
1584 {
1585 State.regs[REG_A0 + (insn & 0x3)] += 4;
1586 }
1587
1588 /* cmp imm8, dn */
1589 void OP_A000 (insn, extension)
1590 unsigned long insn, extension;
1591 {
1592 int z, c, n, v;
1593 unsigned long reg1, imm, value;
1594
1595 reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1596 imm = SEXT8 (insn & 0xff);
1597 value = reg1 - imm;
1598
1599 z = (value == 0);
1600 n = (value & 0x80000000);
1601 c = (reg1 < imm);
1602 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1603 && (reg1 & 0x80000000) != (value & 0x80000000));
1604
1605 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1606 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1607 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1608 }
1609
1610 /* cmp dm, dn */
1611 void OP_A0 (insn, extension)
1612 unsigned long insn, extension;
1613 {
1614 int z, c, n, v;
1615 unsigned long reg1, reg2, value;
1616
1617 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1618 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1619 value = reg2 - reg1;
1620
1621 z = (value == 0);
1622 n = (value & 0x80000000);
1623 c = (reg1 > reg2);
1624 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1625 && (reg2 & 0x80000000) != (value & 0x80000000));
1626
1627 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1628 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1629 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1630 }
1631
1632 /* cmp dm, an */
1633 void OP_F1A0 (insn, extension)
1634 unsigned long insn, extension;
1635 {
1636 int z, c, n, v;
1637 unsigned long reg1, reg2, value;
1638
1639 reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1640 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1641 value = reg2 - reg1;
1642
1643 z = (value == 0);
1644 n = (value & 0x80000000);
1645 c = (reg1 > reg2);
1646 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1647 && (reg2 & 0x80000000) != (value & 0x80000000));
1648
1649 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1650 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1651 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1652 }
1653
1654 /* cmp am, dn */
1655 void OP_F190 (insn, extension)
1656 unsigned long insn, extension;
1657 {
1658 int z, c, n, v;
1659 unsigned long reg1, reg2, value;
1660
1661 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1662 reg2 = State.regs[REG_D0 + (insn & 0x3)];
1663 value = reg2 - reg1;
1664
1665 z = (value == 0);
1666 n = (value & 0x80000000);
1667 c = (reg1 > reg2);
1668 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1669 && (reg2 & 0x80000000) != (value & 0x80000000));
1670
1671 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1672 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1673 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1674 }
1675
1676 /* cmp imm8, an */
1677 void OP_B000 (insn, extension)
1678 unsigned long insn, extension;
1679 {
1680 int z, c, n, v;
1681 unsigned long reg1, imm, value;
1682
1683 reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1684 imm = insn & 0xff;
1685 value = reg1 - imm;
1686
1687 z = (value == 0);
1688 n = (value & 0x80000000);
1689 c = (reg1 < imm);
1690 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1691 && (reg1 & 0x80000000) != (value & 0x80000000));
1692
1693 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1694 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1695 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1696 }
1697
1698 /* cmp am, an */
1699 void OP_B0 (insn, extension)
1700 unsigned long insn, extension;
1701 {
1702 int z, c, n, v;
1703 unsigned long reg1, reg2, value;
1704
1705 reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1706 reg2 = State.regs[REG_A0 + (insn & 0x3)];
1707 value = reg2 - reg1;
1708
1709 z = (value == 0);
1710 n = (value & 0x80000000);
1711 c = (reg1 > reg2);
1712 v = ((reg2 & 0x80000000) != (reg1 & 0x80000000)
1713 && (reg2 & 0x80000000) != (value & 0x80000000));
1714
1715 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1716 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1717 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1718 }
1719
1720 /* cmp imm16, dn */
1721 void OP_FAC80000 (insn, extension)
1722 unsigned long insn, extension;
1723 {
1724 int z, c, n, v;
1725 unsigned long reg1, imm, value;
1726
1727 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1728 imm = SEXT16 (insn & 0xffff);
1729 value = reg1 - imm;
1730
1731 z = (value == 0);
1732 n = (value & 0x80000000);
1733 c = (reg1 < imm);
1734 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1735 && (reg1 & 0x80000000) != (value & 0x80000000));
1736
1737 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1738 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1739 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1740 }
1741
1742 /* cmp imm32, dn */
1743 void OP_FCC80000 (insn, extension)
1744 unsigned long insn, extension;
1745 {
1746 int z, c, n, v;
1747 unsigned long reg1, imm, value;
1748
1749 reg1 = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
1750 imm = ((insn & 0xffff) << 16) + extension;
1751 value = reg1 - imm;
1752
1753 z = (value == 0);
1754 n = (value & 0x80000000);
1755 c = (reg1 < imm);
1756 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1757 && (reg1 & 0x80000000) != (value & 0x80000000));
1758
1759 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1760 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1761 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1762 }
1763
1764 /* cmp imm16, an */
1765 void OP_FAD80000 (insn, extension)
1766 unsigned long insn, extension;
1767 {
1768 int z, c, n, v;
1769 unsigned long reg1, imm, value;
1770
1771 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1772 imm = insn & 0xffff;
1773 value = reg1 - imm;
1774
1775 z = (value == 0);
1776 n = (value & 0x80000000);
1777 c = (reg1 < imm);
1778 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1779 && (reg1 & 0x80000000) != (value & 0x80000000));
1780
1781 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1782 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1783 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1784 }
1785
1786 /* cmp imm32, an */
1787 void OP_FCD80000 (insn, extension)
1788 unsigned long insn, extension;
1789 {
1790 int z, c, n, v;
1791 unsigned long reg1, imm, value;
1792
1793 reg1 = State.regs[REG_A0 + ((insn & 0x30000) >> 16)];
1794 imm = ((insn & 0xffff) << 16) + extension;
1795 value = reg1 - imm;
1796
1797 z = (value == 0);
1798 n = (value & 0x80000000);
1799 c = (reg1 < imm);
1800 v = ((reg1 & 0x80000000) != (imm & 0x80000000)
1801 && (reg1 & 0x80000000) != (value & 0x80000000));
1802
1803 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1804 PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1805 | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1806 }
1807
1808 /* and dm, dn */
1809 void OP_F200 (insn, extension)
1810 unsigned long insn, extension;
1811 {
1812 int n, z;
1813
1814 State.regs[REG_D0 + (insn & 0x3)] &= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1815 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1816 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1817 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1818 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1819 }
1820
1821 /* and imm8, dn */
1822 void OP_F8E000 (insn, extension)
1823 unsigned long insn, extension;
1824 {
1825 int n, z;
1826
1827 State.regs[REG_D0 + ((insn & 0x300) >> 8)] &= (insn & 0xff);
1828 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1829 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1830 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1831 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1832 }
1833
1834 /* and imm16, dn */
1835 void OP_FAE00000 (insn, extension)
1836 unsigned long insn, extension;
1837 {
1838 int n, z;
1839
1840 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] &= (insn & 0xffff);
1841 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1842 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1843 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1844 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1845 }
1846
1847 /* and imm32, dn */
1848 void OP_FCE00000 (insn, extension)
1849 unsigned long insn, extension;
1850 {
1851 int n, z;
1852
1853 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1854 &= ((insn & 0xffff) << 16) + extension;
1855 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1856 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1857 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1858 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1859 }
1860
1861 /* and imm16, psw */
1862 void OP_FAFC0000 (insn, extension)
1863 unsigned long insn, extension;
1864 {
1865 PSW &= (insn & 0xffff);
1866 }
1867
1868 /* or dm, dn*/
1869 void OP_F210 (insn, extension)
1870 unsigned long insn, extension;
1871 {
1872 int n, z;
1873
1874 State.regs[REG_D0 + (insn & 0x3)] |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1875 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1876 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1877 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1878 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1879 }
1880
1881 /* or imm8, dn */
1882 void OP_F8E400 (insn, extension)
1883 unsigned long insn, extension;
1884 {
1885 int n, z;
1886
1887 State.regs[REG_D0 + ((insn & 0x300) >> 8)] |= insn & 0xff;
1888 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
1889 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
1890 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1891 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1892 }
1893
1894 /* or imm16, dn*/
1895 void OP_FAE40000 (insn, extension)
1896 unsigned long insn, extension;
1897 {
1898 int n, z;
1899
1900 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] |= insn & 0xffff;
1901 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1902 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1903 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1904 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1905 }
1906
1907 /* or imm32, dn */
1908 void OP_FCE40000 (insn, extension)
1909 unsigned long insn, extension;
1910 {
1911 int n, z;
1912
1913 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1914 |= ((insn & 0xffff) << 16) + extension;
1915 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1916 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1917 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1918 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1919 }
1920
1921 /* or imm16,psw */
1922 void OP_FAFD0000 (insn, extension)
1923 unsigned long insn, extension;
1924 {
1925 PSW |= (insn & 0xffff);
1926 }
1927
1928 /* xor dm, dn*/
1929 void OP_F220 (insn, extension)
1930 unsigned long insn, extension;
1931 {
1932 int n, z;
1933
1934 State.regs[REG_D0 + (insn & 0x3)] ^= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1935 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1936 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1937 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1938 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1939 }
1940
1941 /* xor imm16, dn */
1942 void OP_FAE80000 (insn, extension)
1943 unsigned long insn, extension;
1944 {
1945 int n, z;
1946
1947 State.regs[REG_D0 + ((insn & 0x30000) >> 16)] ^= insn & 0xffff;
1948 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1949 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1950 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1951 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1952 }
1953
1954 /* xor imm32, dn */
1955 void OP_FCE80000 (insn, extension)
1956 unsigned long insn, extension;
1957 {
1958 int n, z;
1959
1960 State.regs[REG_D0 + ((insn & 0x30000) >> 16)]
1961 ^= ((insn & 0xffff) << 16) + extension;
1962 z = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] == 0);
1963 n = (State.regs[REG_D0 + ((insn & 0x30000) >> 16)] & 0x80000000) != 0;
1964 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1965 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1966 }
1967
1968 /* not dn */
1969 void OP_F230 (insn, extension)
1970 unsigned long insn, extension;
1971 {
1972 int n, z;
1973
1974 State.regs[REG_D0 + (insn & 0x3)] = ~State.regs[REG_D0 + (insn & 0x3)];
1975 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
1976 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
1977 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1978 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
1979 }
1980
1981 /* btst imm8, dn */
1982 void OP_F8EC00 (insn, extension)
1983 unsigned long insn, extension;
1984 {
1985 unsigned long temp;
1986 int z, n;
1987
1988 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
1989 temp &= (insn & 0xff);
1990 n = (temp & 0x80000000) != 0;
1991 z = (temp == 0);
1992 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1993 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
1994 }
1995
1996 /* btst imm16, dn */
1997 void OP_FAEC0000 (insn, extension)
1998 unsigned long insn, extension;
1999 {
2000 unsigned long temp;
2001 int z, n;
2002
2003 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
2004 temp &= (insn & 0xffff);
2005 n = (temp & 0x80000000) != 0;
2006 z = (temp == 0);
2007 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2008 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2009 }
2010
2011 /* btst imm32, dn */
2012 void OP_FCEC0000 (insn, extension)
2013 unsigned long insn, extension;
2014 {
2015 unsigned long temp;
2016 int z, n;
2017
2018 temp = State.regs[REG_D0 + ((insn & 0x30000) >> 16)];
2019 temp &= ((insn & 0xffff) << 16) + extension;
2020 n = (temp & 0x80000000) != 0;
2021 z = (temp == 0);
2022 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2023 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2024 }
2025
2026 /* btst imm8,(abs32) */
2027 void OP_FE020000 (insn, extension)
2028 unsigned long insn, extension;
2029 {
2030 unsigned long temp;
2031 int n, z;
2032
2033 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2034 temp &= (extension & 0xff);
2035 n = (temp & 0x80000000) != 0;
2036 z = (temp == 0);
2037 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2038 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2039 }
2040
2041 /* btst imm8,(d8,an) */
2042 void OP_FAF80000 (insn, extension)
2043 unsigned long insn, extension;
2044 {
2045 unsigned long temp;
2046 int n, z;
2047
2048 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
2049 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2050 temp &= (insn & 0xff);
2051 n = (temp & 0x80000000) != 0;
2052 z = (temp == 0);
2053 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2054 PSW |= (z ? PSW_Z : 0) | (n ? PSW_N : 0);
2055 }
2056
2057 /* bset dm, (an) */
2058 void OP_F080 (insn, extension)
2059 unsigned long insn, extension;
2060 {
2061 unsigned long temp;
2062 int z;
2063
2064 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
2065 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
2066 temp |= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2067 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2068 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2069 PSW |= (z ? PSW_Z : 0);
2070 }
2071
2072 /* bset imm8, (abs32) */
2073 void OP_FE000000 (insn, extension)
2074 unsigned long insn, extension;
2075 {
2076 unsigned long temp;
2077 int z;
2078
2079 temp = load_mem (((insn & 0xffff) << 16 | (extension >> 8)), 1);
2080 z = (temp & (extension & 0xff)) == 0;
2081 temp |= (extension & 0xff);
2082 store_mem ((((insn & 0xffff) << 16) | (extension >> 8)), 1, temp);
2083 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2084 PSW |= (z ? PSW_Z : 0);
2085 }
2086
2087 /* bset imm8,(d8,an) */
2088 void OP_FAF00000 (insn, extension)
2089 unsigned long insn, extension;
2090 {
2091 unsigned long temp;
2092 int z;
2093
2094 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
2095 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2096 z = (temp & (insn & 0xff)) == 0;
2097 temp |= (insn & 0xff);
2098 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
2099 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2100 PSW |= (z ? PSW_Z : 0);
2101 }
2102
2103 /* bclr dm, (an) */
2104 void OP_F090 (insn, extension)
2105 unsigned long insn, extension;
2106 {
2107 unsigned long temp;
2108 int z;
2109
2110 temp = load_mem (State.regs[REG_A0 + (insn & 3)], 1);
2111 z = (temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)]) == 0;
2112 temp = ~temp & State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2113 store_mem (State.regs[REG_A0 + (insn & 3)], 1, temp);
2114 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2115 PSW |= (z ? PSW_Z : 0);
2116 }
2117
2118 /* bclr imm8, (abs32) */
2119 void OP_FE010000 (insn, extension)
2120 unsigned long insn, extension;
2121 {
2122 unsigned long temp;
2123 int z;
2124
2125 temp = load_mem (((insn & 0xffff) << 16) | (extension >> 8), 1);
2126 z = (temp & (extension & 0xff)) == 0;
2127 temp = ~temp & (extension & 0xff);
2128 store_mem (((insn & 0xffff) << 16) | (extension >> 8), 1, temp);
2129 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2130 PSW |= (z ? PSW_Z : 0);
2131 }
2132
2133 /* bclr imm8,(d8,an) */
2134 void OP_FAF40000 (insn, extension)
2135 unsigned long insn, extension;
2136 {
2137 unsigned long temp;
2138 int z;
2139
2140 temp = load_mem ((State.regs[REG_A0 + ((insn & 0x30000) >> 16)]
2141 + SEXT8 ((insn & 0xff00) >> 8)), 1);
2142 z = (temp & (insn & 0xff)) == 0;
2143 temp = ~temp & (insn & 0xff);
2144 store_mem (State.regs[REG_A0 + ((insn & 30000)>> 16)], 1, temp);
2145 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2146 PSW |= (z ? PSW_Z : 0);
2147 }
2148
2149 /* asr dm, dn */
2150 void OP_F2B0 (insn, extension)
2151 unsigned long insn, extension;
2152 {
2153 long temp;
2154 int z, n, c;
2155
2156 temp = State.regs[REG_D0 + (insn & 0x3)];
2157 c = temp & 1;
2158 temp >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2159 State.regs[REG_D0 + (insn & 0x3)] = temp;
2160 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2161 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2162 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2163 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2164 }
2165
2166 /* asr imm8, dn */
2167 void OP_F8C800 (insn, extension)
2168 unsigned long insn, extension;
2169 {
2170 long temp;
2171 int z, n, c;
2172
2173 temp = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
2174 c = temp & 1;
2175 temp >>= (insn & 0xff);
2176 State.regs[REG_D0 + ((insn & 0x300) >> 8)] = temp;
2177 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2178 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2179 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2180 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2181 }
2182
2183 /* lsr dm, dn */
2184 void OP_F2A0 (insn, extension)
2185 unsigned long insn, extension;
2186 {
2187 int z, n, c;
2188
2189 c = State.regs[REG_D0 + (insn & 0x3)] & 1;
2190 State.regs[REG_D0 + (insn & 0x3)]
2191 >>= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2192 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2193 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2194 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2195 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2196 }
2197
2198 /* lsr dm, dn */
2199 void OP_F8C400 (insn, extension)
2200 unsigned long insn, extension;
2201 {
2202 int z, n, c;
2203
2204 c = State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 1;
2205 State.regs[REG_D0 + ((insn & 0x300) >> 8)] >>= (insn & 0xff);
2206 z = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] == 0);
2207 n = (State.regs[REG_D0 + ((insn & 0x3) >> 8)] & 0x80000000) != 0;
2208 PSW &= ~(PSW_Z | PSW_N | PSW_C);
2209 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2210 }
2211
2212 /* asl dm, dn */
2213 void OP_F290 (insn, extension)
2214 unsigned long insn, extension;
2215 {
2216 int n, z;
2217
2218 State.regs[REG_D0 + (insn & 0x3)]
2219 <<= State.regs[REG_D0 + ((insn & 0xc) >> 2)];
2220 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2221 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2222 PSW &= ~(PSW_Z | PSW_N);
2223 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2224 }
2225
2226 /* asl imm8, dn */
2227 void OP_F8C000 (insn, extension)
2228 unsigned long insn, extension;
2229 {
2230 int n, z;
2231
2232 State.regs[REG_D0 + ((insn & 0x300) >> 8)] <<= (insn & 0xff);
2233 z = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] == 0);
2234 n = (State.regs[REG_D0 + ((insn & 0x300) >> 8)] & 0x80000000) != 0;
2235 PSW &= ~(PSW_Z | PSW_N);
2236 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2237 }
2238
2239 /* asl2 dn */
2240 void OP_54 (insn, extension)
2241 unsigned long insn, extension;
2242 {
2243 int n, z;
2244
2245 State.regs[REG_D0 + (insn & 0x3)] <<= 2;
2246 z = (State.regs[REG_D0 + (insn & 0x3)] == 0);
2247 n = (State.regs[REG_D0 + (insn & 0x3)] & 0x80000000) != 0;
2248 PSW &= ~(PSW_Z | PSW_N);
2249 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0));
2250 }
2251
2252 /* ror dn */
2253 void OP_F284 (insn, extension)
2254 unsigned long insn, extension;
2255 {
2256 unsigned long value;
2257 int c,n,z;
2258
2259 value = State.regs[REG_D0 + (insn & 0x3)];
2260 c = (value & 0x1);
2261
2262 value >>= 1;
2263 value |= ((PSW & PSW_C) != 0) ? 0x80000000 : 0;
2264 State.regs[REG_D0 + (insn & 0x3)] = value;
2265 z = (value == 0);
2266 n = (value & 0x80000000) != 0;
2267 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2268 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2269 }
2270
2271 /* rol dn */
2272 void OP_F280 (insn, extension)
2273 unsigned long insn, extension;
2274 {
2275 unsigned long value;
2276 int c,n,z;
2277
2278 value = State.regs[REG_D0 + (insn & 0x3)];
2279 c = (value & 0x80000000) ? 1 : 0;
2280
2281 value <<= 1;
2282 value |= ((PSW & PSW_C) != 0);
2283 State.regs[REG_D0 + (insn & 0x3)] = value;
2284 z = (value == 0);
2285 n = (value & 0x80000000) != 0;
2286 PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
2287 PSW |= ((z ? PSW_Z : 0) | (n ? PSW_N : 0) | (c ? PSW_C : 0));
2288 }
2289
2290 /* beq label:8 */
2291 void OP_C800 (insn, extension)
2292 unsigned long insn, extension;
2293 {
2294 /* The dispatching code will add 2 after we return, so
2295 we subtract two here to make things right. */
2296 if (PSW & PSW_Z)
2297 State.pc += SEXT8 (insn & 0xff) - 2;
2298 }
2299
2300 /* bne label:8 */
2301 void OP_C900 (insn, extension)
2302 unsigned long insn, extension;
2303 {
2304 /* The dispatching code will add 2 after we return, so
2305 we subtract two here to make things right. */
2306 if (!(PSW & PSW_Z))
2307 State.pc += SEXT8 (insn & 0xff) - 2;
2308 }
2309
2310 /* bgt label:8 */
2311 void OP_C100 (insn, extension)
2312 unsigned long insn, extension;
2313 {
2314 /* The dispatching code will add 2 after we return, so
2315 we subtract two here to make things right. */
2316 if (!((PSW & PSW_Z)
2317 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))))
2318 State.pc += SEXT8 (insn & 0xff) - 2;
2319 }
2320
2321 /* bge label:8 */
2322 void OP_C200 (insn, extension)
2323 unsigned long insn, extension;
2324 {
2325 /* The dispatching code will add 2 after we return, so
2326 we subtract two here to make things right. */
2327 if (!(((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2328 State.pc += SEXT8 (insn & 0xff) - 2;
2329 }
2330
2331 /* ble label:8 */
2332 void OP_C300 (insn, extension)
2333 unsigned long insn, extension;
2334 {
2335 /* The dispatching code will add 2 after we return, so
2336 we subtract two here to make things right. */
2337 if ((PSW & PSW_Z)
2338 || (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0)))
2339 State.pc += SEXT8 (insn & 0xff) - 2;
2340 }
2341
2342 /* blt label:8 */
2343 void OP_C000 (insn, extension)
2344 unsigned long insn, extension;
2345 {
2346 /* The dispatching code will add 2 after we return, so
2347 we subtract two here to make things right. */
2348 if (((PSW & PSW_N) != 0) ^ ((PSW & PSW_V) != 0))
2349 State.pc += SEXT8 (insn & 0xff) - 2;
2350 }
2351
2352 /* bhi label:8 */
2353 void OP_C500 (insn, extension)
2354 unsigned long insn, extension;
2355 {
2356 /* The dispatching code will add 2 after we return, so
2357 we subtract two here to make things right. */
2358 if (!(((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0))
2359 State.pc += SEXT8 (insn & 0xff) - 2;
2360 }
2361
2362 /* bcc label:8 */
2363 void OP_C600 (insn, extension)
2364 unsigned long insn, extension;
2365 {
2366 /* The dispatching code will add 2 after we return, so
2367 we subtract two here to make things right. */
2368 if (!(PSW & PSW_C))
2369 State.pc += SEXT8 (insn & 0xff) - 2;
2370 }
2371
2372 /* bls label:8 */
2373 void OP_C700 (insn, extension)
2374 unsigned long insn, extension;
2375 {
2376 /* The dispatching code will add 2 after we return, so
2377 we subtract two here to make things right. */
2378 if (((PSW & PSW_C) != 0) || (PSW & PSW_Z) != 0)
2379 State.pc += SEXT8 (insn & 0xff) - 2;
2380 }
2381
2382 /* bcs label:8 */
2383 void OP_C400 (insn, extension)
2384 unsigned long insn, extension;
2385 {
2386 /* The dispatching code will add 2 after we return, so
2387 we subtract two here to make things right. */
2388 if (PSW & PSW_C)
2389 State.pc += SEXT8 (insn & 0xff) - 2;
2390 }
2391
2392 /* bvc label:8 */
2393 void OP_F8E800 (insn, extension)
2394 unsigned long insn, extension;
2395 {
2396 /* The dispatching code will add 3 after we return, so
2397 we subtract two here to make things right. */
2398 if (!(PSW & PSW_V))
2399 State.pc += SEXT8 (insn & 0xff) - 3;
2400 }
2401
2402 /* bvs label:8 */
2403 void OP_F8E900 (insn, extension)
2404 unsigned long insn, extension;
2405 {
2406 /* The dispatching code will add 3 after we return, so
2407 we subtract two here to make things right. */
2408 if (PSW & PSW_V)
2409 State.pc += SEXT8 (insn & 0xff) - 3;
2410 }
2411
2412 /* bnc label:8 */
2413 void OP_F8EA00 (insn, extension)
2414 unsigned long insn, extension;
2415 {
2416 /* The dispatching code will add 3 after we return, so
2417 we subtract two here to make things right. */
2418 if (!(PSW & PSW_N))
2419 State.pc += SEXT8 (insn & 0xff) - 3;
2420 }
2421
2422 /* bns label:8 */
2423 void OP_F8EB00 (insn, extension)
2424 unsigned long insn, extension;
2425 {
2426 /* The dispatching code will add 3 after we return, so
2427 we subtract two here to make things right. */
2428 if (PSW & PSW_N)
2429 State.pc += SEXT8 (insn & 0xff) - 3;
2430 }
2431
2432 /* bra label:8 */
2433 void OP_CA00 (insn, extension)
2434 unsigned long insn, extension;
2435 {
2436 /* The dispatching code will add 2 after we return, so
2437 we subtract two here to make things right. */
2438 State.pc += SEXT8 (insn & 0xff) - 2;
2439 }
2440
2441 /* leq */
2442 void OP_D8 (insn, extension)
2443 unsigned long insn, extension;
2444 {
2445 abort ();
2446 }
2447
2448 /* lne */
2449 void OP_D9 (insn, extension)
2450 unsigned long insn, extension;
2451 {
2452 abort ();
2453 }
2454
2455 /* lgt */
2456 void OP_D1 (insn, extension)
2457 unsigned long insn, extension;
2458 {
2459 abort ();
2460 }
2461
2462 /* lge */
2463 void OP_D2 (insn, extension)
2464 unsigned long insn, extension;
2465 {
2466 abort ();
2467 }
2468
2469 /* lle */
2470 void OP_D3 (insn, extension)
2471 unsigned long insn, extension;
2472 {
2473 abort ();
2474 }
2475
2476 /* llt */
2477 void OP_D0 (insn, extension)
2478 unsigned long insn, extension;
2479 {
2480 abort ();
2481 }
2482
2483 /* lhi */
2484 void OP_D5 (insn, extension)
2485 unsigned long insn, extension;
2486 {
2487 abort ();
2488 }
2489
2490 /* lcc */
2491 void OP_D6 (insn, extension)
2492 unsigned long insn, extension;
2493 {
2494 abort ();
2495 }
2496
2497 /* lls */
2498 void OP_D7 (insn, extension)
2499 unsigned long insn, extension;
2500 {
2501 abort ();
2502 }
2503
2504 /* lcs */
2505 void OP_D4 (insn, extension)
2506 unsigned long insn, extension;
2507 {
2508 abort ();
2509 }
2510
2511 /* lra */
2512 void OP_DA (insn, extension)
2513 unsigned long insn, extension;
2514 {
2515 abort ();
2516 }
2517
2518 /* setlb */
2519 void OP_DB (insn, extension)
2520 unsigned long insn, extension;
2521 {
2522 abort ();
2523 }
2524
2525 /* jmp (an) */
2526 void OP_F0F4 (insn, extension)
2527 unsigned long insn, extension;
2528 {
2529 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2530 }
2531
2532 /* jmp label:16 */
2533 void OP_CC0000 (insn, extension)
2534 unsigned long insn, extension;
2535 {
2536 State.pc += SEXT16 (insn & 0xffff) - 3;
2537 }
2538
2539 /* jmp label:32 */
2540 void OP_DC000000 (insn, extension)
2541 unsigned long insn, extension;
2542 {
2543 State.pc += (((insn & 0xffffff) << 8) + extension) - 5;
2544 }
2545
2546 /* call label:16,reg_list,imm8 */
2547 void OP_CD000000 (insn, extension)
2548 unsigned long insn, extension;
2549 {
2550 unsigned int next_pc, sp, adjust;
2551 unsigned long mask;
2552
2553 sp = State.regs[REG_SP];
2554 next_pc = State.pc + 2;
2555 State.mem[sp] = next_pc & 0xff;
2556 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2557 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2558 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2559
2560 mask = insn & 0xff;
2561
2562 adjust = 0;
2563 if (mask & 0x80)
2564 {
2565 adjust -= 4;
2566 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2567 }
2568
2569 if (mask & 0x40)
2570 {
2571 adjust -= 4;
2572 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2573 }
2574
2575 if (mask & 0x20)
2576 {
2577 adjust -= 4;
2578 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2579 }
2580
2581 if (mask & 0x10)
2582 {
2583 adjust -= 4;
2584 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2585 }
2586
2587 if (mask & 0x8)
2588 {
2589 adjust -= 4;
2590 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2591 adjust -= 4;
2592 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2593 adjust -= 4;
2594 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2595 adjust -= 4;
2596 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2597 adjust -= 4;
2598 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2599 adjust -= 4;
2600 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2601 adjust -= 4;
2602 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2603 adjust -= 4;
2604 }
2605
2606 /* And make sure to update the stack pointer. */
2607 State.regs[REG_SP] -= extension;
2608 State.regs[REG_MDR] = next_pc;
2609 State.pc += SEXT16 ((insn & 0xffff00) >> 8) - 5;
2610 }
2611
2612 /* call label:32,reg_list,imm8*/
2613 void OP_DD000000 (insn, extension)
2614 unsigned long insn, extension;
2615 {
2616 unsigned int next_pc, sp, adjust;
2617 unsigned long mask;
2618
2619 sp = State.regs[REG_SP];
2620 next_pc = State.pc + 2;
2621 State.mem[sp] = next_pc & 0xff;
2622 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2623 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2624 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2625
2626 mask = (extension & 0xff00) >> 8;
2627
2628 adjust = 0;
2629 if (mask & 0x80)
2630 {
2631 adjust -= 4;
2632 State.regs[REG_D0 + 2] = load_mem (sp + adjust, 4);
2633 }
2634
2635 if (mask & 0x40)
2636 {
2637 adjust -= 4;
2638 State.regs[REG_D0 + 3] = load_mem (sp + adjust, 4);
2639 }
2640
2641 if (mask & 0x20)
2642 {
2643 adjust -= 4;
2644 State.regs[REG_A0 + 2] = load_mem (sp + adjust, 4);
2645 }
2646
2647 if (mask & 0x10)
2648 {
2649 adjust -= 4;
2650 State.regs[REG_A0 + 3] = load_mem (sp + adjust, 4);
2651 }
2652
2653 if (mask & 0x8)
2654 {
2655 adjust -= 4;
2656 State.regs[REG_D0] = load_mem (sp + adjust, 4);
2657 adjust -= 4;
2658 State.regs[REG_D0 + 1] = load_mem (sp + adjust, 4);
2659 adjust -= 4;
2660 State.regs[REG_A0] = load_mem (sp + adjust, 4);
2661 adjust -= 4;
2662 State.regs[REG_A0 + 1] = load_mem (sp + adjust, 4);
2663 adjust -= 4;
2664 State.regs[REG_MDR] = load_mem (sp + adjust, 4);
2665 adjust -= 4;
2666 State.regs[REG_LIR] = load_mem (sp + adjust, 4);
2667 adjust -= 4;
2668 State.regs[REG_LAR] = load_mem (sp + adjust, 4);
2669 adjust -= 4;
2670 }
2671
2672 /* And make sure to update the stack pointer. */
2673 State.regs[REG_SP] -= (extension & 0xff);
2674 State.regs[REG_MDR] = next_pc;
2675 State.pc += (((insn & 0xffffff) << 8) | ((extension & 0xff0000) >> 16)) - 7;
2676 }
2677
2678 /* calls (an) */
2679 void OP_F0F0 (insn, extension)
2680 unsigned long insn, extension;
2681 {
2682 unsigned int next_pc, sp;
2683
2684 sp = State.regs[REG_SP];
2685 next_pc = State.pc + 2;
2686 State.mem[sp] = next_pc & 0xff;
2687 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2688 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2689 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2690 State.regs[REG_MDR] = next_pc;
2691 State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
2692 }
2693
2694 /* calls label:16 */
2695 void OP_FAFF0000 (insn, extension)
2696 unsigned long insn, extension;
2697 {
2698 unsigned int next_pc, sp;
2699
2700 sp = State.regs[REG_SP];
2701 next_pc = State.pc + 4;
2702 State.mem[sp] = next_pc & 0xff;
2703 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2704 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2705 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2706 State.regs[REG_MDR] = next_pc;
2707 State.pc += SEXT16 (insn & 0xffff) - 4;
2708 }
2709
2710 /* calls label:32 */
2711 void OP_FCFF0000 (insn, extension)
2712 unsigned long insn, extension;
2713 {
2714 unsigned int next_pc, sp;
2715
2716 sp = State.regs[REG_SP];
2717 next_pc = State.pc + 6;
2718 State.mem[sp] = next_pc & 0xff;
2719 State.mem[sp+1] = (next_pc & 0xff00) >> 8;
2720 State.mem[sp+2] = (next_pc & 0xff0000) >> 16;
2721 State.mem[sp+3] = (next_pc & 0xff000000) >> 24;
2722 State.regs[REG_MDR] = next_pc;
2723 State.pc += (((insn & 0xffff) << 16) + extension) - 6;
2724 }
2725
2726 /* ret reg_list, imm8 */
2727 void OP_DF0000 (insn, extension)
2728 unsigned long insn, extension;
2729 {
2730 unsigned int sp;
2731 unsigned long mask;
2732
2733 State.regs[REG_SP] += insn & 0xff;
2734 State.pc = State.regs[REG_MDR] - 3;
2735 sp = State.regs[REG_SP];
2736
2737 mask = (insn & 0xff00) >> 8;
2738
2739 if (mask & 0x8)
2740 {
2741 sp += 4;
2742 State.regs[REG_LAR] = load_mem (sp, 4);
2743 sp += 4;
2744 State.regs[REG_LIR] = load_mem (sp, 4);
2745 sp += 4;
2746 State.regs[REG_MDR] = load_mem (sp, 4);
2747 sp += 4;
2748 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2749 sp += 4;
2750 State.regs[REG_A0] = load_mem (sp, 4);
2751 sp += 4;
2752 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2753 sp += 4;
2754 State.regs[REG_D0] = load_mem (sp, 4);
2755 sp += 4;
2756 }
2757
2758 if (mask & 0x10)
2759 {
2760 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2761 sp += 4;
2762 }
2763
2764 if (mask & 0x20)
2765 {
2766 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2767 sp += 4;
2768 }
2769
2770 if (mask & 0x40)
2771 {
2772 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2773 sp += 4;
2774 }
2775
2776 if (mask & 0x80)
2777 {
2778 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2779 sp += 4;
2780 }
2781 }
2782
2783 /* retf reg_list,imm8 */
2784 void OP_DE0000 (insn, extension)
2785 unsigned long insn, extension;
2786 {
2787 unsigned int sp;
2788 unsigned long mask;
2789
2790 sp = State.regs[REG_SP] + (insn & 0xff);
2791 State.regs[REG_SP] = sp;
2792 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2793 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2794 State.pc -= 3;
2795
2796 sp = State.regs[REG_SP];
2797
2798 mask = (insn & 0xff00) >> 8;
2799
2800 if (mask & 0x8)
2801 {
2802 sp += 4;
2803 State.regs[REG_LAR] = load_mem (sp, 4);
2804 sp += 4;
2805 State.regs[REG_LIR] = load_mem (sp, 4);
2806 sp += 4;
2807 State.regs[REG_MDR] = load_mem (sp, 4);
2808 sp += 4;
2809 State.regs[REG_A0 + 1] = load_mem (sp, 4);
2810 sp += 4;
2811 State.regs[REG_A0] = load_mem (sp, 4);
2812 sp += 4;
2813 State.regs[REG_D0 + 1] = load_mem (sp, 4);
2814 sp += 4;
2815 State.regs[REG_D0] = load_mem (sp, 4);
2816 sp += 4;
2817 }
2818
2819 if (mask & 0x10)
2820 {
2821 State.regs[REG_A0 + 3] = load_mem (sp, 4);
2822 sp += 4;
2823 }
2824
2825 if (mask & 0x20)
2826 {
2827 State.regs[REG_A0 + 2] = load_mem (sp, 4);
2828 sp += 4;
2829 }
2830
2831 if (mask & 0x40)
2832 {
2833 State.regs[REG_D0 + 3] = load_mem (sp, 4);
2834 sp += 4;
2835 }
2836
2837 if (mask & 0x80)
2838 {
2839 State.regs[REG_D0 + 2] = load_mem (sp, 4);
2840 sp += 4;
2841 }
2842 }
2843
2844 /* rets */
2845 void OP_F0FC (insn, extension)
2846 unsigned long insn, extension;
2847 {
2848 unsigned int sp;
2849
2850 sp = State.regs[REG_SP];
2851 State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
2852 | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
2853 State.pc -= 2;
2854 }
2855
2856 /* rti */
2857 void OP_F0FD (insn, extension)
2858 unsigned long insn, extension;
2859 {
2860 abort ();
2861 }
2862
2863 /* trap */
2864 void OP_F0FE (insn, extension)
2865 unsigned long insn, extension;
2866 {
2867 /* We use this for simulated system calls; we may need to change
2868 it to a reserved instruction if we conflict with uses at
2869 Matsushita. */
2870 int save_errno = errno;
2871 errno = 0;
2872
2873 /* Registers passed to trap 0 */
2874
2875 /* Function number. */
2876 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2877
2878 /* Parameters. */
2879 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2880 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2881 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2882
2883 /* Registers set by trap 0 */
2884
2885 #define RETVAL State.regs[0] /* return value */
2886 #define RETERR State.regs[1] /* return error code */
2887
2888 /* Turn a pointer in a register into a pointer into real memory. */
2889
2890 #define MEMPTR(x) (State.mem + x)
2891
2892 switch (FUNC)
2893 {
2894 #if !defined(__GO32__) && !defined(_WIN32)
2895 case SYS_fork:
2896 RETVAL = fork ();
2897 break;
2898 case SYS_execve:
2899 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2),
2900 (char **)MEMPTR (PARM3));
2901 break;
2902 case SYS_execv:
2903 RETVAL = execve (MEMPTR (PARM1), (char **) MEMPTR (PARM2), NULL);
2904 break;
2905 #endif
2906
2907 case SYS_read:
2908 RETVAL = mn10300_callback->read (mn10300_callback, PARM1,
2909 MEMPTR (PARM2), PARM3);
2910 break;
2911 case SYS_write:
2912 if (PARM1 == 1)
2913 RETVAL = (int)mn10300_callback->write_stdout (mn10300_callback,
2914 MEMPTR (PARM2), PARM3);
2915 else
2916 RETVAL = (int)mn10300_callback->write (mn10300_callback, PARM1,
2917 MEMPTR (PARM2), PARM3);
2918 break;
2919 case SYS_lseek:
2920 RETVAL = mn10300_callback->lseek (mn10300_callback, PARM1, PARM2, PARM3);
2921 break;
2922 case SYS_close:
2923 RETVAL = mn10300_callback->close (mn10300_callback, PARM1);
2924 break;
2925 case SYS_open:
2926 RETVAL = mn10300_callback->open (mn10300_callback, MEMPTR (PARM1), PARM2);
2927 break;
2928 case SYS_exit:
2929 /* EXIT - caller can look in PARM1 to work out the
2930 reason */
2931 if (PARM1 == 0xdead || PARM1 == 0x1)
2932 State.exception = SIGABRT;
2933 else
2934 State.exception = SIGQUIT;
2935 break;
2936
2937 case SYS_stat: /* added at hmsi */
2938 /* stat system call */
2939 {
2940 struct stat host_stat;
2941 reg_t buf;
2942
2943 RETVAL = stat (MEMPTR (PARM1), &host_stat);
2944
2945 buf = PARM2;
2946
2947 /* Just wild-assed guesses. */
2948 store_mem (buf, 2, host_stat.st_dev);
2949 store_mem (buf + 2, 2, host_stat.st_ino);
2950 store_mem (buf + 4, 4, host_stat.st_mode);
2951 store_mem (buf + 8, 2, host_stat.st_nlink);
2952 store_mem (buf + 10, 2, host_stat.st_uid);
2953 store_mem (buf + 12, 2, host_stat.st_gid);
2954 store_mem (buf + 14, 2, host_stat.st_rdev);
2955 store_mem (buf + 16, 4, host_stat.st_size);
2956 store_mem (buf + 20, 4, host_stat.st_atime);
2957 store_mem (buf + 28, 4, host_stat.st_mtime);
2958 store_mem (buf + 36, 4, host_stat.st_ctime);
2959 }
2960 break;
2961
2962 case SYS_chown:
2963 RETVAL = chown (MEMPTR (PARM1), PARM2, PARM3);
2964 break;
2965 case SYS_chmod:
2966 RETVAL = chmod (MEMPTR (PARM1), PARM2);
2967 break;
2968 case SYS_time:
2969 RETVAL = time (MEMPTR (PARM1));
2970 break;
2971 case SYS_times:
2972 {
2973 struct tms tms;
2974 RETVAL = times (&tms);
2975 store_mem (PARM1, 4, tms.tms_utime);
2976 store_mem (PARM1 + 4, 4, tms.tms_stime);
2977 store_mem (PARM1 + 8, 4, tms.tms_cutime);
2978 store_mem (PARM1 + 12, 4, tms.tms_cstime);
2979 break;
2980 }
2981 case SYS_gettimeofday:
2982 {
2983 struct timeval t;
2984 struct timezone tz;
2985 RETVAL = gettimeofday (&t, &tz);
2986 store_mem (PARM1, 4, t.tv_sec);
2987 store_mem (PARM1 + 4, 4, t.tv_usec);
2988 store_mem (PARM2, 4, tz.tz_minuteswest);
2989 store_mem (PARM2 + 4, 4, tz.tz_dsttime);
2990 break;
2991 }
2992 case SYS_utime:
2993 /* Cast the second argument to void *, to avoid type mismatch
2994 if a prototype is present. */
2995 RETVAL = utime (MEMPTR (PARM1), (void *) MEMPTR (PARM2));
2996 break;
2997 default:
2998 abort ();
2999 }
3000 RETERR = errno;
3001 errno = save_errno;
3002 }
3003
3004 /* rtm */
3005 void OP_F0FF (insn, extension)
3006 unsigned long insn, extension;
3007 {
3008 abort ();
3009 }
3010
3011 /* nop */
3012 void OP_CB (insn, extension)
3013 unsigned long insn, extension;
3014 {
3015 }
3016
3017 /* putx */
3018 void OP_F500 (insn, extension)
3019 unsigned long insn, extension;
3020 {
3021 }
3022
3023 /* getx */
3024 void OP_F6F0 (insn, extension)
3025 unsigned long insn, extension;
3026 {
3027 }
3028
3029 /* mulq */
3030 void OP_F600 (insn, extension)
3031 unsigned long insn, extension;
3032 {
3033 }
3034
3035 /* mulq */
3036 void OP_F90000 (insn, extension)
3037 unsigned long insn, extension;
3038 {
3039 }
3040
3041 /* mulq */
3042 void OP_FB000000 (insn, extension)
3043 unsigned long insn, extension;
3044 {
3045 }
3046
3047 /* mulq */
3048 void OP_FD000000 (insn, extension)
3049 unsigned long insn, extension;
3050 {
3051 }
3052
3053 /* mulqu */
3054 void OP_F610 (insn, extension)
3055 unsigned long insn, extension;
3056 {
3057 }
3058
3059 /* mulqu */
3060 void OP_F91400 (insn, extension)
3061 unsigned long insn, extension;
3062 {
3063 }
3064
3065 /* mulqu */
3066 void OP_FB140000 (insn, extension)
3067 unsigned long insn, extension;
3068 {
3069 }
3070
3071 /* mulqu */
3072 void OP_FD140000 (insn, extension)
3073 unsigned long insn, extension;
3074 {
3075 }
3076
3077 /* sat16 */
3078 void OP_F640 (insn, extension)
3079 unsigned long insn, extension;
3080 {
3081 }
3082
3083 /* sat24 */
3084 void OP_F650 (insn, extension)
3085 unsigned long insn, extension;
3086 {
3087 }
3088
3089 /* bsch */
3090 void OP_F670 (insn, extension)
3091 unsigned long insn, extension;
3092 {
3093 }