sim/mn10300/simops.c

   1 #include "config.h"
   2
   3 #include <signal.h>
   4 #ifdef HAVE_UNISTD_H
   5 #include <unistd.h>
   6 #endif
   7 #include "mn10300_sim.h"
   8 #include "simops.h"
   9 #include "sys/syscall.h"
  10 #include "bfd.h"
  11 #include <errno.h>
  12 #include <sys/stat.h>
  13 #include <sys/times.h>
  14 #include <sys/time.h>
  15
  16 enum op_types {
  17   OP_UNKNOWN,
  18 };
  19
  20 #ifdef DEBUG
  21 static void trace_input PARAMS ((char *name, enum op_types type, int size));
  22 static void trace_output PARAMS ((enum op_types result));
  23 static int init_text_p = 0;
  24 static asection *text;
  25 static bfd_vma text_start;
  26 static bfd_vma text_end;
  27 extern bfd *exec_bfd;
  28
  29 #ifndef SIZE_INSTRUCTION
  30 #define SIZE_INSTRUCTION 6
  31 #endif
  32
  33 #ifndef SIZE_OPERANDS
  34 #define SIZE_OPERANDS 16
  35 #endif
  36
  37 #ifndef SIZE_VALUES
  38 #define SIZE_VALUES 11
  39 #endif
  40
  41 #ifndef SIZE_LOCATION
  42 #define SIZE_LOCATION 40
  43 #endif
  44
  45 static void
  46 trace_input (name, type, size)
  47      char *name;
  48      enum op_types type;
  49      int size;
  50 {
  51 }
  52
  53 static void
  54 trace_output (result)
  55      enum op_types result;
  56 {
  57 }
  58
  59 #else
  60 #define trace_input(NAME, IN1, IN2)
  61 #define trace_output(RESULT)
  62 #endif
  63
  64 \f
  65 /* mov */
  66 void OP_8000 ()
  67 {
  68 }
  69
  70 /* mov */
  71 void OP_80 ()
  72 {
  73 }
  74
  75 /* mov */
  76 void OP_F1E0 ()
  77 {
  78 }
  79
  80 /* mov */
  81 void OP_F1D0 ()
  82 {
  83 }
  84
  85 /* mov */
  86 void OP_9000 ()
  87 {
  88 }
  89
  90 /* mov */
  91 void OP_90 ()
  92 {
  93 }
  94
  95 /* mov sp, an*/
  96 void OP_3C ()
  97 {
  98   State.regs[REG_A0 + (insn & 0x3)] = State.regs[REG_SP];
  99 }
 100
 101 /* mov am, sp*/
 102 void OP_F2F0 ()
 103 {
 104   State.regs[REG_SP] = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 105 }
 106
 107 /* mov */
 108 void OP_F2E4 ()
 109 {
 110 }
 111
 112 /* mov */
 113 void OP_F2F3 ()
 114 {
 115 }
 116
 117 /* mov */
 118 void OP_F2E0 ()
 119 {
 120 }
 121
 122 /* mov */
 123 void OP_F2F2 ()
 124 {
 125 }
 126
 127 /* mov */
 128 void OP_70 ()
 129 {
 130 }
 131
 132 /* mov */
 133 void OP_F80000 ()
 134 {
 135 }
 136
 137 /* mov */
 138 void OP_FA000000 ()
 139 {
 140 }
 141
 142 /* mov */
 143 void OP_FC000000 ()
 144 {
 145 }
 146
 147 /* mov */
 148 void OP_5800 ()
 149 {
 150 }
 151
 152 /* mov */
 153 void OP_FAB40000 ()
 154 {
 155 }
 156
 157 /* mov */
 158 void OP_FCB40000 ()
 159 {
 160 }
 161
 162 /* mov */
 163 void OP_F300 ()
 164 {
 165 }
 166
 167 /* mov */
 168 void OP_300000 ()
 169 {
 170 }
 171
 172 /* mov */
 173 void OP_FCA40000 ()
 174 {
 175 }
 176
 177 /* mov */
 178 void OP_F000 ()
 179 {
 180 }
 181
 182 /* mov */
 183 void OP_F82000 ()
 184 {
 185 }
 186
 187 /* mov */
 188 void OP_FA200000 ()
 189 {
 190 }
 191
 192 /* mov */
 193 void OP_FC200000 ()
 194 {
 195 }
 196
 197 /* mov */
 198 void OP_5C00 ()
 199 {
 200 }
 201
 202 /* mov */
 203 void OP_FAB00000 ()
 204 {
 205 }
 206
 207 /* mov */
 208 void OP_FCB00000 ()
 209 {
 210 }
 211
 212 /* mov */
 213 void OP_F380 ()
 214 {
 215 }
 216
 217 /* mov */
 218 void OP_FAA00000 ()
 219 {
 220 }
 221
 222 /* mov */
 223 void OP_FCA00000 ()
 224 {
 225 }
 226
 227 /* mov */
 228 void OP_F8F000 ()
 229 {
 230 }
 231
 232 /* mov */
 233 void OP_60 ()
 234 {
 235 }
 236
 237 /* mov */
 238 void OP_F81000 ()
 239 {
 240 }
 241
 242 /* mov */
 243 void OP_FA100000 ()
 244 {
 245 }
 246
 247 /* mov */
 248 void OP_FC100000 ()
 249 {
 250 }
 251
 252 /* mov */
 253 void OP_4200 ()
 254 {
 255 }
 256
 257 /* mov */
 258 void OP_FA910000 ()
 259 {
 260 }
 261
 262 /* mov */
 263 void OP_FC910000 ()
 264 {
 265 }
 266
 267 /* mov */
 268 void OP_F340 ()
 269 {
 270 }
 271
 272 /* mov */
 273 void OP_10000 ()
 274 {
 275 }
 276
 277 /* mov */
 278 void OP_FC810000 ()
 279 {
 280 }
 281
 282 /* mov */
 283 void OP_F010 ()
 284 {
 285 }
 286
 287 /* mov */
 288 void OP_F83000 ()
 289 {
 290 }
 291
 292 /* mov */
 293 void OP_FA300000 ()
 294 {
 295 }
 296
 297 /* mov */
 298 void OP_FC300000 ()
 299 {
 300 }
 301
 302 /* mov */
 303 void OP_4300 ()
 304 {
 305 }
 306
 307 /* mov */
 308 void OP_FA900000 ()
 309 {
 310 }
 311
 312 /* mov */
 313 void OP_FC900000 ()
 314 {
 315 }
 316
 317 /* mov */
 318 void OP_F3C0 ()
 319 {
 320 }
 321
 322 /* mov */
 323 void OP_FA800000 ()
 324 {
 325 }
 326
 327 /* mov */
 328 void OP_FC800000 ()
 329 {
 330 }
 331
 332 /* mov */
 333 void OP_F8F400 ()
 334 {
 335 }
 336
 337 /* mov */
 338 void OP_2C0000 ()
 339 {
 340 }
 341
 342 /* mov */
 343 void OP_FCCC0000 ()
 344 {
 345 }
 346
 347 /* mov */
 348 void OP_240000 ()
 349 {
 350 }
 351
 352 /* mov imm32, an*/
 353 void OP_FCDC0000 ()
 354 {
 355   unsigned long value;
 356
 357   value = (insn & 0xffff) << 16 | extension;
 358   State.regs[REG_A0 + ((insn & 0x30000) >> 16)] = value;
 359 }
 360
 361 /* movbu */
 362 void OP_F040 ()
 363 {
 364 }
 365
 366 /* movbu */
 367 void OP_F84000 ()
 368 {
 369 }
 370
 371 /* movbu */
 372 void OP_FA400000 ()
 373 {
 374 }
 375
 376 /* movbu */
 377 void OP_FC400000 ()
 378 {
 379 }
 380
 381 /* movbu */
 382 void OP_F8B800 ()
 383 {
 384 }
 385
 386 /* movbu */
 387 void OP_FAB80000 ()
 388 {
 389 }
 390
 391 /* movbu */
 392 void OP_FCB80000 ()
 393 {
 394 }
 395
 396 /* movbu */
 397 void OP_F400 ()
 398 {
 399 }
 400
 401 /* movbu */
 402 void OP_340000 ()
 403 {
 404 }
 405
 406 /* movbu */
 407 void OP_FCA80000 ()
 408 {
 409 }
 410
 411 /* movbu dm,(an) */
 412 void OP_F050 ()
 413 {
 414   store_mem (State.regs[REG_A0 + ((insn & 0xc) >> 2)], 1,
 415              State.regs[REG_D0 + (insn & 0x3)]);
 416 }
 417
 418 /* movbu */
 419 void OP_F85000 ()
 420 {
 421 }
 422
 423 /* movbu */
 424 void OP_FA500000 ()
 425 {
 426 }
 427
 428 /* movbu */
 429 void OP_FC500000 ()
 430 {
 431 }
 432
 433 /* movbu */
 434 void OP_F89200 ()
 435 {
 436 }
 437
 438 /* movbu */
 439 void OP_FA920000 ()
 440 {
 441 }
 442
 443 /* movbu */
 444 void OP_FC920000 ()
 445 {
 446 }
 447
 448 /* movbu */
 449 void OP_F440 ()
 450 {
 451 }
 452
 453 /* movbu */
 454 void OP_20000 ()
 455 {
 456 }
 457
 458 /* movbu */
 459 void OP_FC820000 ()
 460 {
 461 }
 462
 463 /* movhu */
 464 void OP_F060 ()
 465 {
 466 }
 467
 468 /* movhu */
 469 void OP_F86000 ()
 470 {
 471 }
 472
 473 /* movhu */
 474 void OP_FA600000 ()
 475 {
 476 }
 477
 478 /* movhu */
 479 void OP_FC600000 ()
 480 {
 481 }
 482
 483 /* movhu */
 484 void OP_F8BC00 ()
 485 {
 486 }
 487
 488 /* movhu */
 489 void OP_FABC0000 ()
 490 {
 491 }
 492
 493 /* movhu */
 494 void OP_FCBC0000 ()
 495 {
 496 }
 497
 498 /* movhu */
 499 void OP_F480 ()
 500 {
 501 }
 502
 503 /* movhu */
 504 void OP_380000 ()
 505 {
 506 }
 507
 508 /* movhu */
 509 void OP_FCAC0000 ()
 510 {
 511 }
 512
 513 /* movhu */
 514 void OP_F070 ()
 515 {
 516 }
 517
 518 /* movhu */
 519 void OP_F87000 ()
 520 {
 521 }
 522
 523 /* movhu */
 524 void OP_FA700000 ()
 525 {
 526 }
 527
 528 /* movhu */
 529 void OP_FC700000 ()
 530 {
 531 }
 532
 533 /* movhu */
 534 void OP_F89300 ()
 535 {
 536 }
 537
 538 /* movhu */
 539 void OP_FA930000 ()
 540 {
 541 }
 542
 543 /* movhu */
 544 void OP_FC930000 ()
 545 {
 546 }
 547
 548 /* movhu */
 549 void OP_F4C0 ()
 550 {
 551 }
 552
 553 /* movhu */
 554 void OP_30000 ()
 555 {
 556 }
 557
 558 /* movhu */
 559 void OP_FC830000 ()
 560 {
 561 }
 562
 563 /* ext */
 564 void OP_F2D0 ()
 565 {
 566 }
 567
 568 /* extb */
 569 void OP_10 ()
 570 {
 571 }
 572
 573 /* extbu */
 574 void OP_14 ()
 575 {
 576 }
 577
 578 /* exth */
 579 void OP_18 ()
 580 {
 581 }
 582
 583 /* exthu */
 584 void OP_1C ()
 585 {
 586 }
 587
 588 /* movm */
 589 void OP_CE00 ()
 590 {
 591 }
 592
 593 /* movm */
 594 void OP_CF00 ()
 595 {
 596 }
 597
 598 /* clr dn */
 599 void OP_0 ()
 600 {
 601   State.regs[REG_D0 + ((insn & 0xc) >> 2)] = 0;
 602
 603   PSW |= PSW_Z;
 604   PSW &= ~(PSW_V | PSW_C | PSW_N);
 605 }
 606
 607 /* add dm,dn*/
 608 void OP_E0 ()
 609 {
 610   int z, c, n, v;
 611   unsigned long reg1, reg2, value;
 612
 613   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 614   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 615   value = reg1 + reg2;
 616   State.regs[REG_D0 + (insn & 0x3)] = value;
 617
 618   z = (value == 0);
 619   n = (value & 0x80000000);
 620   c = (reg1 < reg2);
 621   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 622        && (reg2 & 0x8000000) != (value & 0x80000000));
 623
 624   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 625   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 626           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 627 }
 628
 629 /* add dm, an */
 630 void OP_F160 ()
 631 {
 632   int z, c, n, v;
 633   unsigned long reg1, reg2, value;
 634
 635   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 636   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 637   value = reg1 + reg2;
 638   State.regs[REG_A0 + (insn & 0x3)] = value;
 639
 640   z = (value == 0);
 641   n = (value & 0x80000000);
 642   c = (reg1 < reg2);
 643   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 644        && (reg2 & 0x8000000) != (value & 0x80000000));
 645
 646   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 647   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 648           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 649 }
 650
 651 /* add am, dn*/
 652 void OP_F150 ()
 653 {
 654   int z, c, n, v;
 655   unsigned long reg1, reg2, value;
 656
 657   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 658   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 659   value = reg1 + reg2;
 660   State.regs[REG_D0 + (insn & 0x3)] = value;
 661
 662   z = (value == 0);
 663   n = (value & 0x80000000);
 664   c = (reg1 < reg2);
 665   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 666        && (reg2 & 0x8000000) != (value & 0x80000000));
 667
 668   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 669   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 670           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 671 }
 672
 673 /* add am,an */
 674 void OP_F170 ()
 675 {
 676   int z, c, n, v;
 677   unsigned long reg1, reg2, value;
 678
 679   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
 680   reg2 = State.regs[REG_A0 + (insn & 0x3)];
 681   value = reg1 + reg2;
 682   State.regs[REG_A0 + (insn & 0x3)] = value;
 683
 684   z = (value == 0);
 685   n = (value & 0x80000000);
 686   c = (reg1 < reg2);
 687   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 688        && (reg2 & 0x8000000) != (value & 0x80000000));
 689
 690   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 691   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 692           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 693 }
 694
 695 /* add imm8, dn */
 696 void OP_2800 ()
 697 {
 698   int z, c, n, v;
 699   unsigned long reg1, imm, value;
 700
 701   reg1 = State.regs[REG_D0 + ((insn & 0xc00) >> 8)];
 702   imm = SEXT8 (insn & 0xff);
 703   value = reg1 + imm;
 704   State.regs[REG_D0 + ((insn & 0xc00) >> 8)] = value;
 705
 706   z = (value == 0);
 707   n = (value & 0x80000000);
 708   c = (reg1 < imm);
 709   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 710        && (imm & 0x8000000) != (value & 0x80000000));
 711
 712   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 713   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 714           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 715 }
 716
 717 /* add imm16, dn */
 718 void OP_FAC00000 ()
 719 {
 720   int z, c, n, v;
 721   unsigned long reg1, imm, value;
 722
 723   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 724   imm = SEXT16 (insn & 0xffff);
 725   value = reg1 + imm;
 726   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 727
 728   z = (value == 0);
 729   n = (value & 0x80000000);
 730   c = (reg1 < imm);
 731   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 732        && (imm & 0x8000000) != (value & 0x80000000));
 733
 734   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 735   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 736           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 737 }
 738
 739 /* add imm32,dn */
 740 void OP_FCC00000 ()
 741 {
 742   int z, c, n, v;
 743   unsigned long reg1, imm, value;
 744
 745   reg1 = State.regs[REG_D0 + ((insn & 0xc0000) >> 16)];
 746   imm = ((insn & 0xffff) << 16) | extension;
 747   value = reg1 + imm;
 748   State.regs[REG_D0 + ((insn & 0xc0000) >> 16)] = value;
 749
 750   z = (value == 0);
 751   n = (value & 0x80000000);
 752   c = (reg1 < imm);
 753   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 754        && (imm & 0x8000000) != (value & 0x80000000));
 755
 756   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 757   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 758           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 759 }
 760
 761 /* add imm8, an */
 762 void OP_2000 ()
 763 {
 764   int z, c, n, v;
 765   unsigned long reg1, imm, value;
 766
 767   reg1 = State.regs[REG_A0 + ((insn & 0xc00) >> 8)];
 768   imm = insn & 0xff;
 769   value = reg1 + imm;
 770   State.regs[REG_A0 + ((insn & 0xc00) >> 8)] = value;
 771
 772   z = (value == 0);
 773   n = (value & 0x80000000);
 774   c = (reg1 < imm);
 775   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 776        && (imm & 0x8000000) != (value & 0x80000000));
 777
 778   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 779   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 780           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 781 }
 782
 783 /* add imm16, an */
 784 void OP_FAD00000 ()
 785 {
 786   int z, c, n, v;
 787   unsigned long reg1, imm, value;
 788
 789   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 790   imm = 0xffff;
 791   value = reg1 + imm;
 792   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 793
 794   z = (value == 0);
 795   n = (value & 0x80000000);
 796   c = (reg1 < imm);
 797   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 798        && (imm & 0x8000000) != (value & 0x80000000));
 799
 800   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 801   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 802           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 803 }
 804
 805 /* add imm32, an */
 806 void OP_FCD00000 ()
 807 {
 808   int z, c, n, v;
 809   unsigned long reg1, imm, value;
 810
 811   reg1 = State.regs[REG_A0 + ((insn & 0xc0000) >> 16)];
 812   imm = ((insn & 0xffff) << 16) | extension;
 813   value = reg1 + imm;
 814   State.regs[REG_A0 + ((insn & 0xc0000) >> 16)] = value;
 815
 816   z = (value == 0);
 817   n = (value & 0x80000000);
 818   c = (reg1 < imm);
 819   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 820        && (imm & 0x8000000) != (value & 0x80000000));
 821
 822   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 823   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 824           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 825 }
 826
 827 /* add imm8, sp*/
 828 void OP_F8FE00 ()
 829 {
 830   int z, c, n, v;
 831   unsigned long reg1, imm, value;
 832
 833   reg1 = State.regs[REG_SP];
 834   imm = SEXT8 (insn & 0xff);
 835   value = reg1 + imm;
 836   State.regs[REG_SP] = value;
 837
 838   z = (value == 0);
 839   n = (value & 0x80000000);
 840   c = (reg1 < imm);
 841   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 842        && (imm & 0x8000000) != (value & 0x80000000));
 843
 844   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 845   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 846           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 847 }
 848
 849 /* add imm16,sp */
 850 void OP_FAFE0000 ()
 851 {
 852   int z, c, n, v;
 853   unsigned long reg1, imm, value;
 854
 855   reg1 = State.regs[REG_SP];
 856   imm = SEXT16 (insn & 0xffff);
 857   value = reg1 + imm;
 858   State.regs[REG_SP] = value;
 859
 860   z = (value == 0);
 861   n = (value & 0x80000000);
 862   c = (reg1 < imm);
 863   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 864        && (imm & 0x8000000) != (value & 0x80000000));
 865
 866   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 867   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 868           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 869 }
 870
 871 /* add */
 872 void OP_FCFE0000 ()
 873 {
 874   int z, c, n, v;
 875   unsigned long reg1, imm, value;
 876
 877   reg1 = State.regs[REG_SP];
 878   imm = ((insn & 0xffff) << 16) | extension;
 879   value = reg1 + imm;
 880   State.regs[REG_SP] = value;
 881
 882   z = (value == 0);
 883   n = (value & 0x80000000);
 884   c = (reg1 < imm);
 885   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
 886        && (imm & 0x8000000) != (value & 0x80000000));
 887
 888   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 889   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 890           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 891 }
 892
 893 /* addc */
 894 void OP_F140 ()
 895 {
 896   int z, c, n, v;
 897   unsigned long reg1, reg2, value;
 898
 899   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
 900   reg2 = State.regs[REG_D0 + (insn & 0x3)];
 901   value = reg1 + reg2 + ((PSW & PSW_C) != 0);
 902   State.regs[REG_D0 + (insn & 0x3)] = value;
 903
 904   z = (value == 0);
 905   n = (value & 0x80000000);
 906   c = (reg1 < reg2);
 907   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
 908        && (reg2 & 0x8000000) != (value & 0x80000000));
 909
 910   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
 911   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
 912           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
 913 }
 914
 915 /* sub */
 916 void OP_F100 ()
 917 {
 918 }
 919
 920 /* sub */
 921 void OP_F120 ()
 922 {
 923 }
 924
 925 /* sub */
 926 void OP_F110 ()
 927 {
 928 }
 929
 930 /* sub */
 931 void OP_F130 ()
 932 {
 933 }
 934
 935 /* sub */
 936 void OP_FCC40000 ()
 937 {
 938 }
 939
 940 /* sub */
 941 void OP_FCD40000 ()
 942 {
 943 }
 944
 945 /* subc */
 946 void OP_F180 ()
 947 {
 948 }
 949
 950 /* mul */
 951 void OP_F240 ()
 952 {
 953 }
 954
 955 /* mulu */
 956 void OP_F250 ()
 957 {
 958 }
 959
 960 /* div */
 961 void OP_F260 ()
 962 {
 963 }
 964
 965 /* divu */
 966 void OP_F270 ()
 967 {
 968 }
 969
 970 /* inc dn */
 971 void OP_40 ()
 972 {
 973   State.regs[REG_D0 + ((insn & 0xc) >> 2)] += 1;
 974 }
 975
 976 /* inc an */
 977 void OP_41 ()
 978 {
 979   State.regs[REG_A0 + ((insn & 0xc) >> 2)] += 1;
 980 }
 981
 982 /* inc4 an */
 983 void OP_50 ()
 984 {
 985   State.regs[REG_A0 + (insn & 0x3)] += 4;
 986 }
 987
 988 /* cmp imm8, dn */
 989 void OP_A000 ()
 990 {
 991   int z, c, n, v;
 992   unsigned long reg1, imm, value;
 993
 994   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 8)];
 995   imm = SEXT8 (insn & 0xff);
 996   value = reg1 - imm;
 997
 998   z = (value == 0);
 999   n = (value & 0x80000000);
1000   c = (reg1 < imm);
1001   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1002        && (imm & 0x8000000) != (value & 0x80000000));
1003
1004   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1005   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1006           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1007 }
1008
1009 /* cmp dm, dn */
1010 void OP_A0 ()
1011 {
1012   int z, c, n, v;
1013   unsigned long reg1, reg2, value;
1014
1015   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1016   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1017   value = reg1 - reg2;
1018
1019   z = (value == 0);
1020   n = (value & 0x80000000);
1021   c = (reg1 < reg2);
1022   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1023        && (reg2 & 0x8000000) != (value & 0x80000000));
1024
1025   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1026   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1027           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1028 }
1029
1030 /* cmp dm, an */
1031 void OP_F1A0 ()
1032 {
1033   int z, c, n, v;
1034   unsigned long reg1, reg2, value;
1035
1036   reg1 = State.regs[REG_D0 + ((insn & 0xc) >> 2)];
1037   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1038   value = reg1 - reg2;
1039
1040   z = (value == 0);
1041   n = (value & 0x80000000);
1042   c = (reg1 < reg2);
1043   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1044        && (reg2 & 0x8000000) != (value & 0x80000000));
1045
1046   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1047   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1048           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1049 }
1050
1051 /* cmp am, dn */
1052 void OP_F190 ()
1053 {
1054   int z, c, n, v;
1055   unsigned long reg1, reg2, value;
1056
1057   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1058   reg2 = State.regs[REG_D0 + (insn & 0x3)];
1059   value = reg1 - reg2;
1060
1061   z = (value == 0);
1062   n = (value & 0x80000000);
1063   c = (reg1 < reg2);
1064   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1065        && (reg2 & 0x8000000) != (value & 0x80000000));
1066
1067   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1068   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1069           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1070 }
1071
1072 /* cmp imm8, an */
1073 void OP_B000 ()
1074 {
1075   int z, c, n, v;
1076   unsigned long reg1, imm, value;
1077
1078   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 8)];
1079   imm = insn & 0xff;
1080   value = reg1 - imm;
1081
1082   z = (value == 0);
1083   n = (value & 0x80000000);
1084   c = (reg1 < imm);
1085   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1086        && (imm & 0x8000000) != (value & 0x80000000));
1087
1088   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1089   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1090           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1091 }
1092
1093 /* cmp am,an */
1094 void OP_B0 ()
1095 {
1096   int z, c, n, v;
1097   unsigned long reg1, reg2, value;
1098
1099   reg1 = State.regs[REG_A0 + ((insn & 0xc) >> 2)];
1100   reg2 = State.regs[REG_A0 + (insn & 0x3)];
1101   value = reg1 - reg2;
1102
1103   z = (value == 0);
1104   n = (value & 0x80000000);
1105   c = (reg1 < reg2);
1106   v = ((reg2 & 0x8000000) != (reg1 & 0x80000000)
1107        && (reg2 & 0x8000000) != (value & 0x80000000));
1108
1109   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1110   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1111           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1112 }
1113
1114 /* cmp */
1115 void OP_FAC80000 ()
1116 {
1117   int z, c, n, v;
1118   unsigned long reg1, imm, value;
1119
1120   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1121   imm = SEXT16 (insn & 0xffff);
1122   value = reg1 - imm;
1123
1124   z = (value == 0);
1125   n = (value & 0x80000000);
1126   c = (reg1 < imm);
1127   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1128        && (imm & 0x8000000) != (value & 0x80000000));
1129
1130   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1131   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1132           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1133 }
1134
1135 /* cmp */
1136 void OP_FCC80000 ()
1137 {
1138   int z, c, n, v;
1139   unsigned long reg1, imm, value;
1140
1141   reg1 = State.regs[REG_D0 + ((insn & 0x300) >> 16)];
1142   imm = ((insn & 0xffff) << 16) | extension;
1143   value = reg1 - imm;
1144
1145   z = (value == 0);
1146   n = (value & 0x80000000);
1147   c = (reg1 < imm);
1148   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1149        && (imm & 0x8000000) != (value & 0x80000000));
1150
1151   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1152   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1153           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1154 }
1155
1156 /* cmp */
1157 void OP_FAD80000 ()
1158 {
1159   int z, c, n, v;
1160   unsigned long reg1, imm, value;
1161
1162   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1163   imm = insn & 0xffff;
1164   value = reg1 - imm;
1165
1166   z = (value == 0);
1167   n = (value & 0x80000000);
1168   c = (reg1 < imm);
1169   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1170        && (imm & 0x8000000) != (value & 0x80000000));
1171
1172   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1173   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1174           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1175 }
1176
1177 /* cmp */
1178 void OP_FCD80000 ()
1179 {
1180   int z, c, n, v;
1181   unsigned long reg1, imm, value;
1182
1183   reg1 = State.regs[REG_A0 + ((insn & 0x300) >> 16)];
1184   imm = ((insn & 0xffff) << 16) | extension;
1185   value = reg1 - imm;
1186
1187   z = (value == 0);
1188   n = (value & 0x80000000);
1189   c = (reg1 < imm);
1190   v = ((imm & 0x8000000) != (reg1 & 0x80000000)
1191        && (imm & 0x8000000) != (value & 0x80000000));
1192
1193   PSW &= ~(PSW_Z | PSW_N | PSW_C | PSW_V);
1194   PSW |= ((z ? PSW_Z : 0) | ( n ? PSW_N : 0)
1195           | (c ? PSW_C : 0) | (v ? PSW_V : 0));
1196 }
1197
1198 /* and */
1199 void OP_F200 ()
1200 {
1201 }
1202
1203 /* and */
1204 void OP_F8E000 ()
1205 {
1206 }
1207
1208 /* and */
1209 void OP_FAE00000 ()
1210 {
1211 }
1212
1213 /* and */
1214 void OP_FCE00000 ()
1215 {
1216 }
1217
1218 /* and */
1219 void OP_FAFC0000 ()
1220 {
1221 }
1222
1223 /* or */
1224 void OP_F210 ()
1225 {
1226 }
1227
1228 /* or */
1229 void OP_F8E400 ()
1230 {
1231 }
1232
1233 /* or */
1234 void OP_FAE40000 ()
1235 {
1236 }
1237
1238 /* or */
1239 void OP_FCE40000 ()
1240 {
1241 }
1242
1243 /* or */
1244 void OP_FAFD0000 ()
1245 {
1246 }
1247
1248 /* xor */
1249 void OP_F220 ()
1250 {
1251 }
1252
1253 /* xor */
1254 void OP_FAE80000 ()
1255 {
1256 }
1257
1258 /* xor */
1259 void OP_FCE80000 ()
1260 {
1261 }
1262
1263 /* not */
1264 void OP_F230 ()
1265 {
1266 }
1267
1268 /* btst */
1269 void OP_F8EC00 ()
1270 {
1271 }
1272
1273 /* btst */
1274 void OP_FAEC0000 ()
1275 {
1276 }
1277
1278 /* btst */
1279 void OP_FCEC0000 ()
1280 {
1281 }
1282
1283 /* btst */
1284 void OP_FE020000 ()
1285 {
1286 }
1287
1288 /* btst */
1289 void OP_FAF80000 ()
1290 {
1291 }
1292
1293 /* btst */
1294 void OP_F080 ()
1295 {
1296 }
1297
1298 /* btst */
1299 void OP_FE000000 ()
1300 {
1301 }
1302
1303 /* btst */
1304 void OP_FAF00000 ()
1305 {
1306 }
1307
1308 /* bclr */
1309 void OP_F090 ()
1310 {
1311 }
1312
1313 /* bclr */
1314 void OP_FE010000 ()
1315 {
1316 }
1317
1318 /* bclr */
1319 void OP_FAF40000 ()
1320 {
1321 }
1322
1323 /* asr */
1324 void OP_F2B0 ()
1325 {
1326 }
1327
1328 /* asr */
1329 void OP_F8C800 ()
1330 {
1331 }
1332
1333 /* lsr */
1334 void OP_F2A0 ()
1335 {
1336 }
1337
1338 /* lsr */
1339 void OP_F8C400 ()
1340 {
1341 }
1342
1343 /* asl */
1344 void OP_F290 ()
1345 {
1346 }
1347
1348 /* asl */
1349 void OP_F8C000 ()
1350 {
1351 }
1352
1353 /* asl2 */
1354 void OP_54 ()
1355 {
1356 }
1357
1358 /* ror */
1359 void OP_F284 ()
1360 {
1361 }
1362
1363 /* rol */
1364 void OP_F280 ()
1365 {
1366 }
1367
1368 /* beq */
1369 void OP_C800 ()
1370 {
1371   /* The dispatching code will add 2 after we return, so
1372      we subtract two here to make things right.  */
1373   if (PSW & PSW_Z)
1374     State.pc += SEXT8 (insn & 0xff) - 2;
1375 }
1376
1377 /* bne */
1378 void OP_C900 ()
1379 {
1380   /* The dispatching code will add 2 after we return, so
1381      we subtract two here to make things right.  */
1382   if (!(PSW & PSW_Z))
1383     State.pc += SEXT8 (insn & 0xff) - 2;
1384 }
1385
1386 /* bgt */
1387 void OP_C100 ()
1388 {
1389 }
1390
1391 /* bge */
1392 void OP_C200 ()
1393 {
1394 }
1395
1396 /* ble */
1397 void OP_C300 ()
1398 {
1399 }
1400
1401 /* blt */
1402 void OP_C000 ()
1403 {
1404 }
1405
1406 /* bhi */
1407 void OP_C500 ()
1408 {
1409 }
1410
1411 /* bcc */
1412 void OP_C600 ()
1413 {
1414 }
1415
1416 /* bls */
1417 void OP_C700 ()
1418 {
1419 }
1420
1421 /* bcs */
1422 void OP_C400 ()
1423 {
1424 }
1425
1426 /* bvc */
1427 void OP_F8E800 ()
1428 {
1429 }
1430
1431 /* bvs */
1432 void OP_F8E900 ()
1433 {
1434 }
1435
1436 /* bnc */
1437 void OP_F8EA00 ()
1438 {
1439 }
1440
1441 /* bns */
1442 void OP_F8EB00 ()
1443 {
1444 }
1445
1446 /* bra */
1447 void OP_CA00 ()
1448 {
1449 }
1450
1451 /* leq */
1452 void OP_D8 ()
1453 {
1454 }
1455
1456 /* lne */
1457 void OP_D9 ()
1458 {
1459 }
1460
1461 /* lgt */
1462 void OP_D1 ()
1463 {
1464 }
1465
1466 /* lge */
1467 void OP_D2 ()
1468 {
1469 }
1470
1471 /* lle */
1472 void OP_D3 ()
1473 {
1474 }
1475
1476 /* llt */
1477 void OP_D0 ()
1478 {
1479 }
1480
1481 /* lhi */
1482 void OP_D5 ()
1483 {
1484 }
1485
1486 /* lcc */
1487 void OP_D6 ()
1488 {
1489 }
1490
1491 /* lls */
1492 void OP_D7 ()
1493 {
1494 }
1495
1496 /* lcs */
1497 void OP_D4 ()
1498 {
1499 }
1500
1501 /* lra */
1502 void OP_DA ()
1503 {
1504 }
1505
1506 /* setlb */
1507 void OP_DB ()
1508 {
1509 }
1510
1511 /* jmp */
1512 void OP_F0F4 ()
1513 {
1514   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
1515 }
1516
1517 /* jmp */
1518 void OP_CC0000 ()
1519 {
1520   State.pc += SEXT16 (insn & 0xffff) - 3;
1521 }
1522
1523 /* jmp */
1524 void OP_DC000000 ()
1525 {
1526   State.pc += (((insn & 0xffffff) << 8) | extension) - 5;
1527 }
1528
1529 /* call */
1530 void OP_CD000000 ()
1531 {
1532 }
1533
1534 /* call */
1535 void OP_DD000000 ()
1536 {
1537 }
1538
1539 /* calls */
1540 void OP_F0F0 ()
1541 {
1542   unsigned int next_pc, sp;
1543
1544   sp = State.regs[REG_SP];
1545   next_pc = State.pc + 2;
1546   State.mem[sp] = next_pc & 0xff;
1547   State.mem[sp+1] = next_pc & 0xff00;
1548   State.mem[sp+2] = next_pc & 0xff0000;
1549   State.mem[sp+3] = next_pc & 0xff000000;
1550   State.regs[REG_MDR] = next_pc;
1551   State.pc = State.regs[REG_A0 + (insn & 0x3)] - 2;
1552 }
1553
1554 /* calls */
1555 void OP_FAFF0000 ()
1556 {
1557   unsigned int next_pc, sp;
1558
1559   sp = State.regs[REG_SP];
1560   next_pc = State.pc + 4;
1561   State.mem[sp] = next_pc & 0xff;
1562   State.mem[sp+1] = next_pc & 0xff00;
1563   State.mem[sp+2] = next_pc & 0xff0000;
1564   State.mem[sp+3] = next_pc & 0xff000000;
1565   State.regs[REG_MDR] = next_pc;
1566   State.pc += SEXT16 (insn & 0xffff) - 4;
1567 }
1568
1569 /* calls */
1570 void OP_FCFF0000 ()
1571 {
1572   unsigned int next_pc, sp;
1573
1574   sp = State.regs[REG_SP];
1575   next_pc = State.pc + 6;
1576   State.mem[sp] = next_pc & 0xff;
1577   State.mem[sp+1] = next_pc & 0xff00;
1578   State.mem[sp+2] = next_pc & 0xff0000;
1579   State.mem[sp+3] = next_pc & 0xff000000;
1580   State.regs[REG_MDR] = next_pc;
1581   State.pc += (((insn & 0xffff) << 16) | extension) - 6;
1582 }
1583
1584 /* ret */
1585 void OP_DF0000 ()
1586 {
1587 }
1588
1589 /* retf */
1590 void OP_DE0000 ()
1591 {
1592 }
1593
1594 /* rets */
1595 void OP_F0FC ()
1596 {
1597   unsigned int sp;
1598
1599   sp = State.regs[REG_SP];
1600   State.pc = (State.mem[sp] | (State.mem[sp+1] << 8)
1601               | (State.mem[sp+2] << 16) | (State.mem[sp+3] << 24));
1602   State.pc -= 2;
1603 }
1604
1605 /* rti */
1606 void OP_F0FD ()
1607 {
1608 }
1609
1610 /* trap */
1611 void OP_F0FE ()
1612 {
1613 }
1614
1615 /* rtm */
1616 void OP_F0FF ()
1617 {
1618 }
1619
1620 /* nop */
1621 void OP_CB ()
1622 {
1623 }
1624
1625 /* putx */
1626 void OP_F500 ()
1627 {
1628 }
1629
1630 /* getx */
1631 void OP_F6F0 ()
1632 {
1633 }
1634
1635 /* mulq */
1636 void OP_F600 ()
1637 {
1638 }
1639
1640 /* mulq */
1641 void OP_F90000 ()
1642 {
1643 }
1644
1645 /* mulq */
1646 void OP_FB000000 ()
1647 {
1648 }
1649
1650 /* mulq */
1651 void OP_FD000000 ()
1652 {
1653 }
1654
1655 /* mulqu */
1656 void OP_F610 ()
1657 {
1658 }
1659
1660 /* mulqu */
1661 void OP_F91400 ()
1662 {
1663 }
1664
1665 /* mulqu */
1666 void OP_FB140000 ()
1667 {
1668 }
1669
1670 /* mulqu */
1671 void OP_FD140000 ()
1672 {
1673 }
1674
1675 /* sat16 */
1676 void OP_F640 ()
1677 {
1678 }
1679
1680 /* sat24 */
1681 void OP_F650 ()
1682 {
1683 }
1684
1685 /* bsch */
1686 void OP_F670 ()
1687 {
1688 }