7 #include "mn10300_sim.h"
9 #include "sys/syscall.h"
13 #include <sys/times.h>
21 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
22 static void trace_output
PARAMS ((enum op_types result
));
23 static int init_text_p
= 0;
24 static asection
*text
;
25 static bfd_vma text_start
;
26 static bfd_vma text_end
;
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
34 #define SIZE_OPERANDS 16
38 #define SIZE_VALUES 11
42 #define SIZE_LOCATION 40
46 trace_input (name
, type
, size
)
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
66 void OP_8000 (insn
, extension
)
67 unsigned long insn
, extension
;
69 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = SEXT8 (insn
& 0xff);
73 void OP_80 (insn
, extension
)
74 unsigned long insn
, extension
;
76 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
80 void OP_F1E0 (insn
, extension
)
81 unsigned long insn
, extension
;
83 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
87 void OP_F1D0 (insn
, extension
)
88 unsigned long insn
, extension
;
90 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
94 void OP_9000 (insn
, extension
)
95 unsigned long insn
, extension
;
97 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] = insn
& 0xff;
101 void OP_90 (insn
, extension
)
102 unsigned long insn
, extension
;
104 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
108 void OP_3C (insn
, extension
)
109 unsigned long insn
, extension
;
111 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_SP
];
115 void OP_F2F0 (insn
, extension
)
116 unsigned long insn
, extension
;
118 State
.regs
[REG_SP
] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
122 void OP_F2E4 (insn
, extension
)
123 unsigned long insn
, extension
;
125 State
.regs
[REG_D0
+ (insn
& 0x3)] = PSW
;
129 void OP_F2F3 (insn
, extension
)
130 unsigned long insn
, extension
;
132 PSW
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
136 void OP_F2E0 (insn
, extension
)
137 unsigned long insn
, extension
;
139 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_MDR
];
143 void OP_F2F2 (insn
, extension
)
144 unsigned long insn
, extension
;
146 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
150 void OP_70 (insn
, extension
)
151 unsigned long insn
, extension
;
153 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
154 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
157 /* mov (d8,am), dn */
158 void OP_F80000 (insn
, extension
)
159 unsigned long insn
, extension
;
161 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
162 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
163 + SEXT8 (insn
& 0xff)), 4);
166 /* mov (d16,am), dn */
167 void OP_FA000000 (insn
, extension
)
168 unsigned long insn
, extension
;
170 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
171 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
172 + SEXT16 (insn
& 0xffff)), 4);
175 /* mov (d32,am), dn */
176 void OP_FC000000 (insn
, extension
)
177 unsigned long insn
, extension
;
179 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
180 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
181 + ((insn
& 0xffff) << 16) | extension
), 4);
184 /* mov (d8,sp), dn */
185 void OP_5800 (insn
, extension
)
186 unsigned long insn
, extension
;
188 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
189 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
192 /* mov (d16,sp), dn */
193 void OP_FAB40000 (insn
, extension
)
194 unsigned long insn
, extension
;
196 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
197 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
200 /* mov (d32,sp), dn */
201 void OP_FCB40000 (insn
, extension
)
202 unsigned long insn
, extension
;
204 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
205 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
208 /* mov (di,am), dn */
209 void OP_F300 (insn
, extension
)
210 unsigned long insn
, extension
;
212 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
213 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
214 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
217 /* mov (abs16), dn */
218 void OP_300000 (insn
, extension
)
219 unsigned long insn
, extension
;
221 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 4);
224 /* mov (abs32), dn */
225 void OP_FCA40000 (insn
, extension
)
226 unsigned long insn
, extension
;
228 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
229 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
233 void OP_F000 (insn
, extension
)
234 unsigned long insn
, extension
;
236 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]
237 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
240 /* mov (d8,am), an */
241 void OP_F82000 (insn
, extension
)
242 unsigned long insn
, extension
;
244 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]
245 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
246 + SEXT8 (insn
& 0xff)), 4);
249 /* mov (d16,am), an */
250 void OP_FA200000 (insn
, extension
)
251 unsigned long insn
, extension
;
253 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]
254 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
255 + SEXT16 (insn
& 0xffff)), 4);
258 /* mov (d32,am), an */
259 void OP_FC200000 (insn
, extension
)
260 unsigned long insn
, extension
;
262 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]
263 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
264 + ((insn
& 0xffff) << 16) + extension
), 4);
267 /* mov (d8,sp), an */
268 void OP_5C00 (insn
, extension
)
269 unsigned long insn
, extension
;
271 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
272 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
275 /* mov (d16,sp), an */
276 void OP_FAB00000 (insn
, extension
)
277 unsigned long insn
, extension
;
279 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
280 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
283 /* mov (d32,sp), an */
284 void OP_FCB00000 (insn
, extension
)
285 unsigned long insn
, extension
;
287 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
288 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
291 /* mov (di,am), an */
292 void OP_F380 (insn
, extension
)
293 unsigned long insn
, extension
;
295 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
296 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
297 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
300 /* mov (abs16), an */
301 void OP_FAA00000 (insn
, extension
)
302 unsigned long insn
, extension
;
304 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 4);
307 /* mov (abs32), an */
308 void OP_FCA00000 (insn
, extension
)
309 unsigned long insn
, extension
;
311 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
312 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
315 /* mov (d8,am), sp */
316 void OP_F8F000 (insn
, extension
)
317 unsigned long insn
, extension
;
320 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
321 + SEXT8 (insn
& 0xff)), 4);
325 void OP_60 (insn
, extension
)
326 unsigned long insn
, extension
;
328 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
329 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
332 /* mov dm, (d8,an) */
333 void OP_F81000 (insn
, extension
)
334 unsigned long insn
, extension
;
336 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
337 + SEXT8 (insn
& 0xff)), 4,
338 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
341 /* mov dm (d16,an) */
342 void OP_FA100000 (insn
, extension
)
343 unsigned long insn
, extension
;
345 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
346 + SEXT16 (insn
& 0xffff)), 4,
347 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
350 /* mov dm (d32,an) */
351 void OP_FC100000 (insn
, extension
)
352 unsigned long insn
, extension
;
354 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
355 + ((insn
& 0xffff) << 16) + extension
), 4,
356 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
359 /* mov dm, (d8,sp) */
360 void OP_4200 (insn
, extension
)
361 unsigned long insn
, extension
;
363 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
364 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
367 /* mov dm, (d16,sp) */
368 void OP_FA910000 (insn
, extension
)
369 unsigned long insn
, extension
;
371 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
372 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
375 /* mov dm, (d32,sp) */
376 void OP_FC910000 (insn
, extension
)
377 unsigned long insn
, extension
;
379 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
380 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
383 /* mov dm, (di,an) */
384 void OP_F340 (insn
, extension
)
385 unsigned long insn
, extension
;
387 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
388 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
389 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
392 /* mov dm, (abs16) */
393 void OP_10000 (insn
, extension
)
394 unsigned long insn
, extension
;
396 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
399 /* mov dm, (abs32) */
400 void OP_FC810000 (insn
, extension
)
401 unsigned long insn
, extension
;
403 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
407 void OP_F010 (insn
, extension
)
408 unsigned long insn
, extension
;
410 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
411 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]);
414 /* mov am, (d8,an) */
415 void OP_F83000 (insn
, extension
)
416 unsigned long insn
, extension
;
418 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
419 + SEXT8 (insn
& 0xff)), 4,
420 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
423 /* mov am, (d16,an) */
424 void OP_FA300000 (insn
, extension
)
425 unsigned long insn
, extension
;
427 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
428 + SEXT16 (insn
& 0xffff)), 4,
429 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
432 /* mov am, (d32,an) */
433 void OP_FC300000 (insn
, extension
)
434 unsigned long insn
, extension
;
436 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
437 + ((insn
& 0xffff) << 16) + extension
), 4,
438 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
441 /* mov am, (d8,sp) */
442 void OP_4300 (insn
, extension
)
443 unsigned long insn
, extension
;
445 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
446 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
449 /* mov am, (d16,sp) */
450 void OP_FA900000 (insn
, extension
)
451 unsigned long insn
, extension
;
453 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
454 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
457 /* mov am, (d32,sp) */
458 void OP_FC900000 (insn
, extension
)
459 unsigned long insn
, extension
;
461 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
462 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
465 /* mov am, (di,an) */
466 void OP_F3C0 (insn
, extension
)
467 unsigned long insn
, extension
;
469 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
470 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
471 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]);
474 /* mov am, (abs16) */
475 void OP_FA800000 (insn
, extension
)
476 unsigned long insn
, extension
;
478 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
481 /* mov am, (abs32) */
482 void OP_FC800000 (insn
, extension
)
483 unsigned long insn
, extension
;
485 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
488 /* mov sp, (d8,an) */
489 void OP_F8F400 (insn
, extension
)
490 unsigned long insn
, extension
;
492 store_mem (State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] + SEXT8 (insn
& 0xff),
493 4, State
.regs
[REG_SP
]);
497 void OP_2C0000 (insn
, extension
)
498 unsigned long insn
, extension
;
502 value
= SEXT16 (insn
& 0xffff);
503 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
507 void OP_FCCC0000 (insn
, extension
)
508 unsigned long insn
, extension
;
512 value
= (insn
& 0xffff) << 16 | extension
;
513 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
517 void OP_240000 (insn
, extension
)
518 unsigned long insn
, extension
;
522 value
= insn
& 0xffff;
523 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
527 void OP_FCDC0000 (insn
, extension
)
528 unsigned long insn
, extension
;
532 value
= (insn
& 0xffff) << 16 | extension
;
533 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
537 void OP_F040 (insn
, extension
)
538 unsigned long insn
, extension
;
540 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
541 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 1);
544 /* movbu (d8,am), dn */
545 void OP_F84000 (insn
, extension
)
546 unsigned long insn
, extension
;
548 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
549 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
550 + SEXT8 (insn
& 0xff)), 1);
553 /* movbu (d16,am), dn */
554 void OP_FA400000 (insn
, extension
)
555 unsigned long insn
, extension
;
557 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
558 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
559 + SEXT16 (insn
& 0xffff)), 1);
562 /* movbu (d32,am), dn */
563 void OP_FC400000 (insn
, extension
)
564 unsigned long insn
, extension
;
566 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
567 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
568 + ((insn
& 0xffff) << 16) + extension
), 1);
571 /* movbu (d8,sp), dn */
572 void OP_F8B800 (insn
, extension
)
573 unsigned long insn
, extension
;
575 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
576 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 1);
579 /* movbu (d16,sp), dn */
580 void OP_FAB80000 (insn
, extension
)
581 unsigned long insn
, extension
;
583 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
584 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 1);
587 /* movbu (d32,sp), dn */
588 void OP_FCB80000 (insn
, extension
)
589 unsigned long insn
, extension
;
591 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
592 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 1);
595 /* movbu (di,am), dn */
596 void OP_F400 (insn
, extension
)
597 unsigned long insn
, extension
;
599 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
600 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
601 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1);
604 /* movbu (abs16), dn */
605 void OP_340000 (insn
, extension
)
606 unsigned long insn
, extension
;
608 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 1);
611 /* movbu (abs32), dn */
612 void OP_FCA80000 (insn
, extension
)
613 unsigned long insn
, extension
;
615 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
616 = load_mem ((((insn
& 0xffff) << 16) + extension
), 1);
620 void OP_F050 (insn
, extension
)
621 unsigned long insn
, extension
;
623 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 1,
624 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
627 /* movbu dm, (d8,an) */
628 void OP_F85000 (insn
, extension
)
629 unsigned long insn
, extension
;
631 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
632 + SEXT8 (insn
& 0xff)), 1,
633 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
636 /* movbu dm, (d16,an) */
637 void OP_FA500000 (insn
, extension
)
638 unsigned long insn
, extension
;
640 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
641 + SEXT16 (insn
& 0xffff)), 1,
642 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
645 /* movbu dm, (d32,an) */
646 void OP_FC500000 (insn
, extension
)
647 unsigned long insn
, extension
;
649 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
650 + ((insn
& 0xffff) << 16) + extension
), 1,
651 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
654 /* movbu dm, (d8,sp) */
655 void OP_F89200 (insn
, extension
)
656 unsigned long insn
, extension
;
658 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 1,
659 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
662 /* movbu dm, (d16,sp) */
663 void OP_FA920000 (insn
, extension
)
664 unsigned long insn
, extension
;
666 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
667 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
670 /* movbu dm (d32,sp) */
671 void OP_FC920000 (insn
, extension
)
672 unsigned long insn
, extension
;
674 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
675 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
678 /* movbu dm, (di,an) */
679 void OP_F440 (insn
, extension
)
680 unsigned long insn
, extension
;
682 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
683 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1,
684 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
687 /* movbu dm, (abs16) */
688 void OP_20000 (insn
, extension
)
689 unsigned long insn
, extension
;
691 store_mem ((insn
& 0xffff), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
694 /* movbu dm, (abs32) */
695 void OP_FC820000 (insn
, extension
)
696 unsigned long insn
, extension
;
698 store_mem ((((insn
& 0xffff) << 16) + extension
), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
702 void OP_F060 (insn
, extension
)
703 unsigned long insn
, extension
;
705 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
706 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 2);
709 /* movhu (d8,am), dn */
710 void OP_F86000 (insn
, extension
)
711 unsigned long insn
, extension
;
713 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
714 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
715 + SEXT8 (insn
& 0xff)), 2);
718 /* movhu (d16,am), dn */
719 void OP_FA600000 (insn
, extension
)
720 unsigned long insn
, extension
;
722 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
723 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
724 + SEXT16 (insn
& 0xffff)), 2);
727 /* movhu (d32,am), dn */
728 void OP_FC600000 (insn
, extension
)
729 unsigned long insn
, extension
;
731 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
732 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
733 + ((insn
& 0xffff) << 16) + extension
), 2);
736 /* movhu (d8,sp) dn */
737 void OP_F8BC00 (insn
, extension
)
738 unsigned long insn
, extension
;
740 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
741 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 2);
744 /* movhu (d16,sp), dn */
745 void OP_FABC0000 (insn
, extension
)
746 unsigned long insn
, extension
;
748 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
749 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 2);
752 /* movhu (d32,sp), dn */
753 void OP_FCBC0000 (insn
, extension
)
754 unsigned long insn
, extension
;
756 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
757 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2);
760 /* movhu (di,am), dn */
761 void OP_F480 (insn
, extension
)
762 unsigned long insn
, extension
;
764 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
765 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
766 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2);
769 /* movhu (abs16), dn */
770 void OP_380000 (insn
, extension
)
771 unsigned long insn
, extension
;
773 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 2);
776 /* movhu (abs32), dn */
777 void OP_FCAC0000 (insn
, extension
)
778 unsigned long insn
, extension
;
780 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
781 = load_mem ((((insn
& 0xffff) << 16) + extension
), 2);
785 void OP_F070 (insn
, extension
)
786 unsigned long insn
, extension
;
788 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 2,
789 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
792 /* movhu dm, (d8,an) */
793 void OP_F87000 (insn
, extension
)
794 unsigned long insn
, extension
;
796 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
797 + SEXT8 (insn
& 0xff)), 2,
798 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
801 /* movhu dm, (d16,an) */
802 void OP_FA700000 (insn
, extension
)
803 unsigned long insn
, extension
;
805 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
806 + SEXT16 (insn
& 0xffff)), 2,
807 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
810 /* movhu dm, (d32,an) */
811 void OP_FC700000 (insn
, extension
)
812 unsigned long insn
, extension
;
814 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
815 + ((insn
& 0xffff) << 16) + extension
), 2,
816 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
819 /* movhu dm,(d8,sp) */
820 void OP_F89300 (insn
, extension
)
821 unsigned long insn
, extension
;
823 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 2,
824 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
827 /* movhu dm,(d16,sp) */
828 void OP_FA930000 (insn
, extension
)
829 unsigned long insn
, extension
;
831 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
832 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
835 /* movhu dm,(d32,sp) */
836 void OP_FC930000 (insn
, extension
)
837 unsigned long insn
, extension
;
839 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
840 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
843 /* movhu dm, (di,an) */
844 void OP_F4C0 (insn
, extension
)
845 unsigned long insn
, extension
;
847 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
848 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2,
849 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
852 /* movhu dm, (abs16) */
853 void OP_30000 (insn
, extension
)
854 unsigned long insn
, extension
;
856 store_mem ((insn
& 0xffff), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
859 /* movhu dm, (abs32) */
860 void OP_FC830000 (insn
, extension
)
861 unsigned long insn
, extension
;
863 store_mem ((((insn
& 0xffff) << 16) + extension
), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
867 void OP_F2D0 (insn
, extension
)
868 unsigned long insn
, extension
;
870 if (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000)
871 State
.regs
[REG_MDR
] = -1;
873 State
.regs
[REG_MDR
] = 0;
877 void OP_10 (insn
, extension
)
878 unsigned long insn
, extension
;
880 State
.regs
[REG_D0
+ (insn
& 0x3)] = SEXT8 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
884 void OP_14 (insn
, extension
)
885 unsigned long insn
, extension
;
887 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xff;
891 void OP_18 (insn
, extension
)
892 unsigned long insn
, extension
;
894 State
.regs
[REG_D0
+ (insn
& 0x3)]
895 = SEXT16 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
899 void OP_1C (insn
, extension
)
900 unsigned long insn
, extension
;
902 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xffff;
905 /* movm (sp), reg_list */
906 void OP_CE00 (insn
, extension
)
907 unsigned long insn
, extension
;
909 unsigned long sp
= State
.regs
[REG_SP
];
917 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
919 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
921 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
923 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
925 State
.regs
[REG_A0
] = load_mem (sp
, 4);
927 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
929 State
.regs
[REG_D0
] = load_mem (sp
, 4);
935 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
941 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
947 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
953 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
957 /* And make sure to update the stack pointer. */
958 State
.regs
[REG_SP
] = sp
;
961 /* movm reg_list, (sp) */
962 void OP_CF00 (insn
, extension
)
963 unsigned long insn
, extension
;
965 unsigned long sp
= State
.regs
[REG_SP
];
973 store_mem (sp
, 4, State
.regs
[REG_D0
+ 2]);
979 store_mem (sp
, 4, State
.regs
[REG_D0
+ 3]);
985 store_mem (sp
, 4, State
.regs
[REG_A0
+ 2]);
991 store_mem (sp
, 4, State
.regs
[REG_A0
+ 3]);
997 store_mem (sp
, 4, State
.regs
[REG_D0
]);
999 store_mem (sp
, 4, State
.regs
[REG_D0
+ 1]);
1001 store_mem (sp
, 4, State
.regs
[REG_A0
]);
1003 store_mem (sp
, 4, State
.regs
[REG_A0
+ 1]);
1005 store_mem (sp
, 4, State
.regs
[REG_MDR
]);
1007 store_mem (sp
, 4, State
.regs
[REG_LIR
]);
1009 store_mem (sp
, 4, State
.regs
[REG_LAR
]);
1013 /* And make sure to update the stack pointer. */
1014 State
.regs
[REG_SP
] = sp
;
1018 void OP_0 (insn
, extension
)
1019 unsigned long insn
, extension
;
1021 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] = 0;
1024 PSW
&= ~(PSW_V
| PSW_C
| PSW_N
);
1028 void OP_E0 (insn
, extension
)
1029 unsigned long insn
, extension
;
1032 unsigned long reg1
, reg2
, value
;
1034 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1035 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1036 value
= reg1
+ reg2
;
1037 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1040 n
= (value
& 0x80000000);
1042 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1043 && (reg2
& 0x80000000) != (value
& 0x80000000));
1045 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1046 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1047 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1051 void OP_F160 (insn
, extension
)
1052 unsigned long insn
, extension
;
1055 unsigned long reg1
, reg2
, value
;
1057 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1058 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1059 value
= reg1
+ reg2
;
1060 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1063 n
= (value
& 0x80000000);
1065 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1066 && (reg2
& 0x80000000) != (value
& 0x80000000));
1068 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1069 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1070 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1074 void OP_F150 (insn
, extension
)
1075 unsigned long insn
, extension
;
1078 unsigned long reg1
, reg2
, value
;
1080 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1081 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1082 value
= reg1
+ reg2
;
1083 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1086 n
= (value
& 0x80000000);
1088 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1089 && (reg2
& 0x80000000) != (value
& 0x80000000));
1091 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1092 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1093 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1097 void OP_F170 (insn
, extension
)
1098 unsigned long insn
, extension
;
1101 unsigned long reg1
, reg2
, value
;
1103 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1104 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1105 value
= reg1
+ reg2
;
1106 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1109 n
= (value
& 0x80000000);
1111 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1112 && (reg2
& 0x80000000) != (value
& 0x80000000));
1114 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1115 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1116 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1120 void OP_2800 (insn
, extension
)
1121 unsigned long insn
, extension
;
1124 unsigned long reg1
, imm
, value
;
1126 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1127 imm
= SEXT8 (insn
& 0xff);
1129 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = value
;
1132 n
= (value
& 0x80000000);
1134 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1135 && (reg1
& 0x80000000) != (value
& 0x80000000));
1137 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1138 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1139 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1143 void OP_FAC00000 (insn
, extension
)
1144 unsigned long insn
, extension
;
1147 unsigned long reg1
, imm
, value
;
1149 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1150 imm
= SEXT16 (insn
& 0xffff);
1152 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
1155 n
= (value
& 0x80000000);
1157 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1158 && (reg1
& 0x80000000) != (value
& 0x80000000));
1160 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1161 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1162 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1166 void OP_FCC00000 (insn
, extension
)
1167 unsigned long insn
, extension
;
1170 unsigned long reg1
, imm
, value
;
1172 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1173 imm
= ((insn
& 0xffff) << 16) | extension
;
1175 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
1178 n
= (value
& 0x80000000);
1180 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1181 && (reg1
& 0x80000000) != (value
& 0x80000000));
1183 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1184 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1185 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1189 void OP_2000 (insn
, extension
)
1190 unsigned long insn
, extension
;
1193 unsigned long reg1
, imm
, value
;
1195 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1196 imm
= SEXT8 (insn
& 0xff);
1198 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] = value
;
1201 n
= (value
& 0x80000000);
1203 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1204 && (reg1
& 0x80000000) != (value
& 0x80000000));
1206 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1207 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1208 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1212 void OP_FAD00000 (insn
, extension
)
1213 unsigned long insn
, extension
;
1216 unsigned long reg1
, imm
, value
;
1218 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1219 imm
= SEXT16 (insn
& 0xffff);
1221 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
1224 n
= (value
& 0x80000000);
1226 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1227 && (reg1
& 0x80000000) != (value
& 0x80000000));
1229 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1230 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1231 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1235 void OP_FCD00000 (insn
, extension
)
1236 unsigned long insn
, extension
;
1239 unsigned long reg1
, imm
, value
;
1241 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1242 imm
= ((insn
& 0xffff) << 16) | extension
;
1244 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
1247 n
= (value
& 0x80000000);
1249 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1250 && (reg1
& 0x80000000) != (value
& 0x80000000));
1252 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1253 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1254 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1258 void OP_F8FE00 (insn
, extension
)
1259 unsigned long insn
, extension
;
1262 unsigned long reg1
, imm
, value
;
1264 reg1
= State
.regs
[REG_SP
];
1265 imm
= SEXT8 (insn
& 0xff);
1267 State
.regs
[REG_SP
] = value
;
1271 void OP_FAFE0000 (insn
, extension
)
1272 unsigned long insn
, extension
;
1275 unsigned long reg1
, imm
, value
;
1277 reg1
= State
.regs
[REG_SP
];
1278 imm
= SEXT16 (insn
& 0xffff);
1280 State
.regs
[REG_SP
] = value
;
1284 void OP_FCFE0000 (insn
, extension
)
1285 unsigned long insn
, extension
;
1288 unsigned long reg1
, imm
, value
;
1290 reg1
= State
.regs
[REG_SP
];
1291 imm
= ((insn
& 0xffff) << 16) | extension
;
1293 State
.regs
[REG_SP
] = value
;
1297 void OP_F140 (insn
, extension
)
1298 unsigned long insn
, extension
;
1301 unsigned long reg1
, reg2
, value
;
1303 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1304 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1305 value
= reg1
+ reg2
+ ((PSW
& PSW_C
) != 0);
1306 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1309 n
= (value
& 0x80000000);
1311 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1312 && (reg2
& 0x80000000) != (value
& 0x80000000));
1314 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1315 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1316 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1320 void OP_F100 (insn
, extension
)
1321 unsigned long insn
, extension
;
1324 unsigned long reg1
, reg2
, value
;
1326 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1327 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1328 value
= reg2
- reg1
;
1331 n
= (value
& 0x80000000);
1333 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1334 && (reg2
& 0x80000000) != (value
& 0x80000000));
1336 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1337 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1338 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1339 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1343 void OP_F120 (insn
, extension
)
1344 unsigned long insn
, extension
;
1347 unsigned long reg1
, reg2
, value
;
1349 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1350 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1351 value
= reg2
- reg1
;
1354 n
= (value
& 0x80000000);
1356 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1357 && (reg2
& 0x80000000) != (value
& 0x80000000));
1359 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1360 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1361 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1362 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1366 void OP_F110 (insn
, extension
)
1367 unsigned long insn
, extension
;
1370 unsigned long reg1
, reg2
, value
;
1372 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1373 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1374 value
= reg2
- reg1
;
1377 n
= (value
& 0x80000000);
1379 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1380 && (reg2
& 0x80000000) != (value
& 0x80000000));
1382 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1383 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1384 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1385 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1389 void OP_F130 (insn
, extension
)
1390 unsigned long insn
, extension
;
1393 unsigned long reg1
, reg2
, value
;
1395 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1396 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1397 value
= reg2
- reg1
;
1400 n
= (value
& 0x80000000);
1402 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1403 && (reg2
& 0x80000000) != (value
& 0x80000000));
1405 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1406 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1407 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1408 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1412 void OP_FCC40000 (insn
, extension
)
1413 unsigned long insn
, extension
;
1416 unsigned long reg1
, imm
, value
;
1418 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1419 imm
= ((insn
& 0xffff) << 16) | extension
;
1423 n
= (value
& 0x80000000);
1425 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1426 && (reg1
& 0x80000000) != (value
& 0x80000000));
1428 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1429 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1430 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1431 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
1435 void OP_FCD40000 (insn
, extension
)
1436 unsigned long insn
, extension
;
1439 unsigned long reg1
, imm
, value
;
1441 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1442 imm
= ((insn
& 0xffff) << 16) | extension
;
1446 n
= (value
& 0x80000000);
1448 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1449 && (reg1
& 0x80000000) != (value
& 0x80000000));
1451 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1452 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1453 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1454 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
1458 void OP_F180 (insn
, extension
)
1459 unsigned long insn
, extension
;
1462 unsigned long reg1
, reg2
, value
;
1464 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1465 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1466 value
= reg2
- reg1
- ((PSW
& PSW_C
) != 0);
1469 n
= (value
& 0x80000000);
1471 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1472 && (reg2
& 0x80000000) != (value
& 0x80000000));
1474 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1475 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1476 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1477 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1481 void OP_F240 (insn
, extension
)
1482 unsigned long insn
, extension
;
1484 unsigned long long temp
;
1487 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1488 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1489 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1490 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1491 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1492 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1493 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1494 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1498 void OP_F250 (insn
, extension
)
1499 unsigned long insn
, extension
;
1501 unsigned long long temp
;
1504 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1505 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1506 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1507 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1508 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1509 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1510 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1511 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1515 void OP_F260 (insn
, extension
)
1516 unsigned long insn
, extension
;
1521 temp
= State
.regs
[REG_MDR
];
1523 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1524 State
.regs
[REG_MDR
] = temp
% (long)State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1525 temp
/= (long)State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1526 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1527 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1528 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1529 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1530 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1531 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1535 void OP_F270 (insn
, extension
)
1536 unsigned long insn
, extension
;
1538 unsigned long long temp
;
1541 temp
= State
.regs
[REG_MDR
];
1543 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1544 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1545 temp
/= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1546 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1547 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1548 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1549 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1550 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1551 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1555 void OP_40 (insn
, extension
)
1556 unsigned long insn
, extension
;
1559 unsigned int value
, imm
, reg1
;
1561 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1564 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] = value
;
1567 n
= (value
& 0x80000000);
1569 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1570 && (reg1
& 0x80000000) != (value
& 0x80000000));
1572 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1573 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1574 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1578 void OP_41 (insn
, extension
)
1579 unsigned long insn
, extension
;
1581 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)] += 1;
1585 void OP_50 (insn
, extension
)
1586 unsigned long insn
, extension
;
1588 State
.regs
[REG_A0
+ (insn
& 0x3)] += 4;
1592 void OP_A000 (insn
, extension
)
1593 unsigned long insn
, extension
;
1596 unsigned long reg1
, imm
, value
;
1598 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1599 imm
= SEXT8 (insn
& 0xff);
1603 n
= (value
& 0x80000000);
1605 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1606 && (reg1
& 0x80000000) != (value
& 0x80000000));
1608 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1609 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1610 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1614 void OP_A0 (insn
, extension
)
1615 unsigned long insn
, extension
;
1618 unsigned long reg1
, reg2
, value
;
1620 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1621 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1622 value
= reg2
- reg1
;
1625 n
= (value
& 0x80000000);
1627 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1628 && (reg2
& 0x80000000) != (value
& 0x80000000));
1630 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1631 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1632 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1636 void OP_F1A0 (insn
, extension
)
1637 unsigned long insn
, extension
;
1640 unsigned long reg1
, reg2
, value
;
1642 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1643 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1644 value
= reg2
- reg1
;
1647 n
= (value
& 0x80000000);
1649 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1650 && (reg2
& 0x80000000) != (value
& 0x80000000));
1652 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1653 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1654 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1658 void OP_F190 (insn
, extension
)
1659 unsigned long insn
, extension
;
1662 unsigned long reg1
, reg2
, value
;
1664 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1665 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1666 value
= reg2
- reg1
;
1669 n
= (value
& 0x80000000);
1671 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1672 && (reg2
& 0x80000000) != (value
& 0x80000000));
1674 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1675 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1676 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1680 void OP_B000 (insn
, extension
)
1681 unsigned long insn
, extension
;
1684 unsigned long reg1
, imm
, value
;
1686 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1691 n
= (value
& 0x80000000);
1693 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1694 && (reg1
& 0x80000000) != (value
& 0x80000000));
1696 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1697 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1698 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1702 void OP_B0 (insn
, extension
)
1703 unsigned long insn
, extension
;
1706 unsigned long reg1
, reg2
, value
;
1708 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1709 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1710 value
= reg2
- reg1
;
1713 n
= (value
& 0x80000000);
1715 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1716 && (reg2
& 0x80000000) != (value
& 0x80000000));
1718 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1719 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1720 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1724 void OP_FAC80000 (insn
, extension
)
1725 unsigned long insn
, extension
;
1728 unsigned long reg1
, imm
, value
;
1730 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1731 imm
= SEXT16 (insn
& 0xffff);
1735 n
= (value
& 0x80000000);
1737 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1738 && (reg1
& 0x80000000) != (value
& 0x80000000));
1740 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1741 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1742 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1746 void OP_FCC80000 (insn
, extension
)
1747 unsigned long insn
, extension
;
1750 unsigned long reg1
, imm
, value
;
1752 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1753 imm
= ((insn
& 0xffff) << 16) | extension
;
1757 n
= (value
& 0x80000000);
1759 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1760 && (reg1
& 0x80000000) != (value
& 0x80000000));
1762 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1763 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1764 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1768 void OP_FAD80000 (insn
, extension
)
1769 unsigned long insn
, extension
;
1772 unsigned long reg1
, imm
, value
;
1774 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1775 imm
= insn
& 0xffff;
1779 n
= (value
& 0x80000000);
1781 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1782 && (reg1
& 0x80000000) != (value
& 0x80000000));
1784 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1785 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1786 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1790 void OP_FCD80000 (insn
, extension
)
1791 unsigned long insn
, extension
;
1794 unsigned long reg1
, imm
, value
;
1796 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1797 imm
= ((insn
& 0xffff) << 16) | extension
;
1801 n
= (value
& 0x80000000);
1803 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1804 && (reg1
& 0x80000000) != (value
& 0x80000000));
1806 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1807 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1808 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1812 void OP_F200 (insn
, extension
)
1813 unsigned long insn
, extension
;
1817 State
.regs
[REG_D0
+ (insn
& 0x3)] &= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1818 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1819 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1820 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1821 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1825 void OP_F8E000 (insn
, extension
)
1826 unsigned long insn
, extension
;
1830 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] &= (insn
& 0xff);
1831 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
1832 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
1833 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1834 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1838 void OP_FAE00000 (insn
, extension
)
1839 unsigned long insn
, extension
;
1843 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] &= (insn
& 0xffff);
1844 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1845 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1846 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1847 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1851 void OP_FCE00000 (insn
, extension
)
1852 unsigned long insn
, extension
;
1856 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1857 &= ((insn
& 0xffff) << 16 | extension
);
1858 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1859 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1860 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1861 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1864 /* and imm16, psw */
1865 void OP_FAFC0000 (insn
, extension
)
1866 unsigned long insn
, extension
;
1868 PSW
&= (insn
& 0xffff);
1872 void OP_F210 (insn
, extension
)
1873 unsigned long insn
, extension
;
1877 State
.regs
[REG_D0
+ (insn
& 0x3)] |= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1878 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1879 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1880 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1881 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1885 void OP_F8E400 (insn
, extension
)
1886 unsigned long insn
, extension
;
1890 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] |= insn
& 0xff;
1891 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
1892 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
1893 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1894 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1898 void OP_FAE40000 (insn
, extension
)
1899 unsigned long insn
, extension
;
1903 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] |= insn
& 0xffff;
1904 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1905 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1906 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1907 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1911 void OP_FCE40000 (insn
, extension
)
1912 unsigned long insn
, extension
;
1916 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1917 |= ((insn
& 0xffff) << 16 | extension
);
1918 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1919 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1920 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1921 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1925 void OP_FAFD0000 (insn
, extension
)
1926 unsigned long insn
, extension
;
1928 PSW
|= (insn
& 0xffff);
1932 void OP_F220 (insn
, extension
)
1933 unsigned long insn
, extension
;
1937 State
.regs
[REG_D0
+ (insn
& 0x3)] ^= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1938 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1939 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1940 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1941 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1945 void OP_FAE80000 (insn
, extension
)
1946 unsigned long insn
, extension
;
1950 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] ^= insn
& 0xffff;
1951 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1952 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1953 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1954 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1958 void OP_FCE80000 (insn
, extension
)
1959 unsigned long insn
, extension
;
1963 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1964 ^= ((insn
& 0xffff) << 16 | extension
);
1965 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1966 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1967 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1968 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1972 void OP_F230 (insn
, extension
)
1973 unsigned long insn
, extension
;
1977 State
.regs
[REG_D0
+ (insn
& 0x3)] = ~State
.regs
[REG_D0
+ (insn
& 0x3)];
1978 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1979 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1980 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1981 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1985 void OP_F8EC00 (insn
, extension
)
1986 unsigned long insn
, extension
;
1991 temp
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1992 temp
&= (insn
& 0xff);
1993 n
= (temp
& 0x80000000) != 0;
1995 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1996 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1999 /* btst imm16, dn */
2000 void OP_FAEC0000 (insn
, extension
)
2001 unsigned long insn
, extension
;
2006 temp
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
2007 temp
&= (insn
& 0xffff);
2008 n
= (temp
& 0x80000000) != 0;
2010 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2011 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
2014 /* btst imm32, dn */
2015 void OP_FCEC0000 (insn
, extension
)
2016 unsigned long insn
, extension
;
2021 temp
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
2022 temp
&= ((insn
& 0xffff) << 16 | extension
);
2023 n
= (temp
& 0x80000000) != 0;
2025 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2026 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
2029 /* btst imm8,(abs32) */
2030 void OP_FE020000 (insn
, extension
)
2031 unsigned long insn
, extension
;
2036 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
2037 temp
&= (extension
& 0xff);
2038 n
= (temp
& 0x80000000) != 0;
2040 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2041 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
2044 /* btst imm8,(d8,an) */
2045 void OP_FAF80000 (insn
, extension
)
2046 unsigned long insn
, extension
;
2051 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
2052 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
2053 temp
&= (insn
& 0xff);
2054 n
= (temp
& 0x80000000) != 0;
2056 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2057 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
2061 void OP_F080 (insn
, extension
)
2062 unsigned long insn
, extension
;
2067 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
2068 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
2069 temp
|= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2070 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
2071 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2072 PSW
|= (z
? PSW_Z
: 0);
2075 /* bset imm8, (abs32) */
2076 void OP_FE000000 (insn
, extension
)
2077 unsigned long insn
, extension
;
2082 temp
= load_mem (((insn
& 0xffff) << 16 | (extension
>> 8)), 1);
2083 z
= (temp
& (extension
& 0xff)) == 0;
2084 temp
|= (extension
& 0xff);
2085 store_mem ((((insn
& 0xffff) << 16) | (extension
>> 8)), 1, temp
);
2086 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2087 PSW
|= (z
? PSW_Z
: 0);
2090 /* bset imm8,(d8,an) */
2091 void OP_FAF00000 (insn
, extension
)
2092 unsigned long insn
, extension
;
2097 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
2098 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
2099 z
= (temp
& (insn
& 0xff)) == 0;
2100 temp
|= (insn
& 0xff);
2101 store_mem (State
.regs
[REG_A0
+ ((insn
& 30000)>> 16)], 1, temp
);
2102 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2103 PSW
|= (z
? PSW_Z
: 0);
2107 void OP_F090 (insn
, extension
)
2108 unsigned long insn
, extension
;
2113 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
2114 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
2115 temp
= ~temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2116 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
2117 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2118 PSW
|= (z
? PSW_Z
: 0);
2121 /* bclr imm8, (abs32) */
2122 void OP_FE010000 (insn
, extension
)
2123 unsigned long insn
, extension
;
2128 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
2129 z
= (temp
& (extension
& 0xff)) == 0;
2130 temp
= ~temp
& (extension
& 0xff);
2131 store_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1, temp
);
2132 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2133 PSW
|= (z
? PSW_Z
: 0);
2136 /* bclr imm8,(d8,an) */
2137 void OP_FAF40000 (insn
, extension
)
2138 unsigned long insn
, extension
;
2143 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
2144 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
2145 z
= (temp
& (insn
& 0xff)) == 0;
2146 temp
= ~temp
& (insn
& 0xff);
2147 store_mem (State
.regs
[REG_A0
+ ((insn
& 30000)>> 16)], 1, temp
);
2148 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2149 PSW
|= (z
? PSW_Z
: 0);
2153 void OP_F2B0 (insn
, extension
)
2154 unsigned long insn
, extension
;
2159 temp
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2161 temp
>>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2162 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
;
2163 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2164 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2165 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2166 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2170 void OP_F8C800 (insn
, extension
)
2171 unsigned long insn
, extension
;
2176 temp
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
2178 temp
>>= (insn
& 0xff);
2179 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = temp
;
2180 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
2181 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
2182 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2183 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2187 void OP_F2A0 (insn
, extension
)
2188 unsigned long insn
, extension
;
2192 c
= State
.regs
[REG_D0
+ (insn
& 0x3)] & 1;
2193 State
.regs
[REG_D0
+ (insn
& 0x3)]
2194 >>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2195 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2196 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2197 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2198 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2202 void OP_F8C400 (insn
, extension
)
2203 unsigned long insn
, extension
;
2207 c
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 1;
2208 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] >>= (insn
& 0xff);
2209 z
= (State
.regs
[REG_D0
+ ((insn
& 0x3) >> 8)] == 0);
2210 n
= (State
.regs
[REG_D0
+ ((insn
& 0x3) >> 8)] & 0x80000000) != 0;
2211 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2212 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2216 void OP_F290 (insn
, extension
)
2217 unsigned long insn
, extension
;
2221 State
.regs
[REG_D0
+ (insn
& 0x3)]
2222 <<= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2223 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2224 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2225 PSW
&= ~(PSW_Z
| PSW_N
);
2226 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2230 void OP_F8C000 (insn
, extension
)
2231 unsigned long insn
, extension
;
2235 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] <<= (insn
& 0xff);
2236 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
2237 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
2238 PSW
&= ~(PSW_Z
| PSW_N
);
2239 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2243 void OP_54 (insn
, extension
)
2244 unsigned long insn
, extension
;
2248 State
.regs
[REG_D0
+ (insn
& 0x3)] <<= 2;
2249 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2250 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2251 PSW
&= ~(PSW_Z
| PSW_N
);
2252 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2256 void OP_F284 (insn
, extension
)
2257 unsigned long insn
, extension
;
2259 unsigned long value
;
2262 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2267 value
|= ((PSW
& PSW_C
) != 0) ? 0x80000000 : 0;
2268 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
2270 n
= (value
& 0x80000000) != 0;
2271 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2272 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2276 void OP_F280 (insn
, extension
)
2277 unsigned long insn
, extension
;
2279 unsigned long value
;
2282 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2283 if (value
& 0x80000000)
2287 value
|= ((PSW
& PSW_C
) != 0);
2288 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
2290 n
= (value
& 0x80000000) != 0;
2291 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2292 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2296 void OP_C800 (insn
, extension
)
2297 unsigned long insn
, extension
;
2299 /* The dispatching code will add 2 after we return, so
2300 we subtract two here to make things right. */
2302 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2306 void OP_C900 (insn
, extension
)
2307 unsigned long insn
, extension
;
2309 /* The dispatching code will add 2 after we return, so
2310 we subtract two here to make things right. */
2312 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2316 void OP_C100 (insn
, extension
)
2317 unsigned long insn
, extension
;
2319 /* The dispatching code will add 2 after we return, so
2320 we subtract two here to make things right. */
2322 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)))
2323 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2327 void OP_C200 (insn
, extension
)
2328 unsigned long insn
, extension
;
2330 /* The dispatching code will add 2 after we return, so
2331 we subtract two here to make things right. */
2332 if (!(((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
2333 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2337 void OP_C300 (insn
, extension
)
2338 unsigned long insn
, extension
;
2340 /* The dispatching code will add 2 after we return, so
2341 we subtract two here to make things right. */
2343 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
2344 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2348 void OP_C000 (insn
, extension
)
2349 unsigned long insn
, extension
;
2351 /* The dispatching code will add 2 after we return, so
2352 we subtract two here to make things right. */
2353 if (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)
2354 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2358 void OP_C500 (insn
, extension
)
2359 unsigned long insn
, extension
;
2361 /* The dispatching code will add 2 after we return, so
2362 we subtract two here to make things right. */
2363 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2364 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2368 void OP_C600 (insn
, extension
)
2369 unsigned long insn
, extension
;
2371 /* The dispatching code will add 2 after we return, so
2372 we subtract two here to make things right. */
2374 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2378 void OP_C700 (insn
, extension
)
2379 unsigned long insn
, extension
;
2381 /* The dispatching code will add 2 after we return, so
2382 we subtract two here to make things right. */
2383 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2384 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2388 void OP_C400 (insn
, extension
)
2389 unsigned long insn
, extension
;
2391 /* The dispatching code will add 2 after we return, so
2392 we subtract two here to make things right. */
2394 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2398 void OP_F8E800 (insn
, extension
)
2399 unsigned long insn
, extension
;
2401 /* The dispatching code will add 3 after we return, so
2402 we subtract two here to make things right. */
2404 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2408 void OP_F8E900 (insn
, extension
)
2409 unsigned long insn
, extension
;
2411 /* The dispatching code will add 3 after we return, so
2412 we subtract two here to make things right. */
2414 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2418 void OP_F8EA00 (insn
, extension
)
2419 unsigned long insn
, extension
;
2421 /* The dispatching code will add 3 after we return, so
2422 we subtract two here to make things right. */
2424 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2428 void OP_F8EB00 (insn
, extension
)
2429 unsigned long insn
, extension
;
2431 /* The dispatching code will add 3 after we return, so
2432 we subtract two here to make things right. */
2434 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2438 void OP_CA00 (insn
, extension
)
2439 unsigned long insn
, extension
;
2441 /* The dispatching code will add 2 after we return, so
2442 we subtract two here to make things right. */
2443 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2447 void OP_D8 (insn
, extension
)
2448 unsigned long insn
, extension
;
2454 void OP_D9 (insn
, extension
)
2455 unsigned long insn
, extension
;
2461 void OP_D1 (insn
, extension
)
2462 unsigned long insn
, extension
;
2468 void OP_D2 (insn
, extension
)
2469 unsigned long insn
, extension
;
2475 void OP_D3 (insn
, extension
)
2476 unsigned long insn
, extension
;
2482 void OP_D0 (insn
, extension
)
2483 unsigned long insn
, extension
;
2489 void OP_D5 (insn
, extension
)
2490 unsigned long insn
, extension
;
2496 void OP_D6 (insn
, extension
)
2497 unsigned long insn
, extension
;
2503 void OP_D7 (insn
, extension
)
2504 unsigned long insn
, extension
;
2510 void OP_D4 (insn
, extension
)
2511 unsigned long insn
, extension
;
2517 void OP_DA (insn
, extension
)
2518 unsigned long insn
, extension
;
2524 void OP_DB (insn
, extension
)
2525 unsigned long insn
, extension
;
2531 void OP_F0F4 (insn
, extension
)
2532 unsigned long insn
, extension
;
2534 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2538 void OP_CC0000 (insn
, extension
)
2539 unsigned long insn
, extension
;
2541 State
.pc
+= SEXT16 (insn
& 0xffff) - 3;
2545 void OP_DC000000 (insn
, extension
)
2546 unsigned long insn
, extension
;
2548 State
.pc
+= (((insn
& 0xffffff) << 8) | extension
) - 5;
2551 /* call label:16,reg_list,imm8 */
2552 void OP_CD000000 (insn
, extension
)
2553 unsigned long insn
, extension
;
2555 unsigned int next_pc
, sp
, adjust
;
2558 sp
= State
.regs
[REG_SP
];
2559 next_pc
= State
.pc
+ 2;
2560 State
.mem
[sp
] = next_pc
& 0xff;
2561 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2562 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2563 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2571 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2577 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2583 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2589 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2595 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2597 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2599 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2601 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2603 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2605 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2607 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2611 /* And make sure to update the stack pointer. */
2612 State
.regs
[REG_SP
] -= extension
;
2613 State
.regs
[REG_MDR
] = next_pc
;
2614 State
.pc
+= SEXT16 ((insn
& 0xffff00) >> 8) - 5;
2617 /* call label:32,reg_list,imm8*/
2618 void OP_DD000000 (insn
, extension
)
2619 unsigned long insn
, extension
;
2621 unsigned int next_pc
, sp
, adjust
;
2624 sp
= State
.regs
[REG_SP
];
2625 next_pc
= State
.pc
+ 2;
2626 State
.mem
[sp
] = next_pc
& 0xff;
2627 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2628 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2629 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2631 mask
= (extension
& 0xff00) >> 8;
2637 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2643 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2649 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2655 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2661 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2663 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2665 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2667 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2669 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2671 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2673 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2677 /* And make sure to update the stack pointer. */
2678 State
.regs
[REG_SP
] -= (extension
& 0xff);
2679 State
.regs
[REG_MDR
] = next_pc
;
2680 State
.pc
+= (((insn
& 0xffffff) << 8) | ((extension
& 0xff0000) >> 16)) - 7;
2684 void OP_F0F0 (insn
, extension
)
2685 unsigned long insn
, extension
;
2687 unsigned int next_pc
, sp
;
2689 sp
= State
.regs
[REG_SP
];
2690 next_pc
= State
.pc
+ 2;
2691 State
.mem
[sp
] = next_pc
& 0xff;
2692 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2693 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2694 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2695 State
.regs
[REG_MDR
] = next_pc
;
2696 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2699 /* calls label:16 */
2700 void OP_FAFF0000 (insn
, extension
)
2701 unsigned long insn
, extension
;
2703 unsigned int next_pc
, sp
;
2705 sp
= State
.regs
[REG_SP
];
2706 next_pc
= State
.pc
+ 4;
2707 State
.mem
[sp
] = next_pc
& 0xff;
2708 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2709 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2710 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2711 State
.regs
[REG_MDR
] = next_pc
;
2712 State
.pc
+= SEXT16 (insn
& 0xffff) - 4;
2715 /* calls label:32 */
2716 void OP_FCFF0000 (insn
, extension
)
2717 unsigned long insn
, extension
;
2719 unsigned int next_pc
, sp
;
2721 sp
= State
.regs
[REG_SP
];
2722 next_pc
= State
.pc
+ 6;
2723 State
.mem
[sp
] = next_pc
& 0xff;
2724 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2725 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2726 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2727 State
.regs
[REG_MDR
] = next_pc
;
2728 State
.pc
+= (((insn
& 0xffff) << 16) | extension
) - 6;
2731 /* ret reg_list, imm8 */
2732 void OP_DF0000 (insn
, extension
)
2733 unsigned long insn
, extension
;
2738 State
.regs
[REG_SP
] += insn
& 0xff;
2739 State
.pc
= State
.regs
[REG_MDR
] - 3;
2740 sp
= State
.regs
[REG_SP
];
2742 mask
= (insn
& 0xff00) >> 8;
2747 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2749 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2751 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2753 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2755 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2757 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2759 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2765 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2771 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2777 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2783 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2788 /* retf reg_list,imm8 */
2789 void OP_DE0000 (insn
, extension
)
2790 unsigned long insn
, extension
;
2795 State
.regs
[REG_SP
] += insn
& 0xff;
2796 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2797 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2800 sp
= State
.regs
[REG_SP
];
2802 mask
= (insn
& 0xff00) >> 8;
2807 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2809 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2811 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2813 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2815 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2817 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2819 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2825 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2831 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2837 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2843 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2849 void OP_F0FC (insn
, extension
)
2850 unsigned long insn
, extension
;
2854 sp
= State
.regs
[REG_SP
];
2855 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2856 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2861 void OP_F0FD (insn
, extension
)
2862 unsigned long insn
, extension
;
2868 void OP_F0FE (insn
, extension
)
2869 unsigned long insn
, extension
;
2871 /* We use this for simulated system calls; we may need to change
2872 it to a reserved instruction if we conflict with uses at
2874 int save_errno
= errno
;
2877 /* Registers passed to trap 0 */
2879 /* Function number. */
2880 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2883 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2884 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2885 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2887 /* Registers set by trap 0 */
2889 #define RETVAL State.regs[0] /* return value */
2890 #define RETERR State.regs[1] /* return error code */
2892 /* Turn a pointer in a register into a pointer into real memory. */
2894 #define MEMPTR(x) (State.mem + x)
2898 #if !defined(__GO32__) && !defined(_WIN32)
2903 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2904 (char **)MEMPTR (PARM3
));
2907 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2912 RETVAL
= mn10300_callback
->read (mn10300_callback
, PARM1
,
2913 MEMPTR (PARM2
), PARM3
);
2917 RETVAL
= (int)mn10300_callback
->write_stdout (mn10300_callback
,
2918 MEMPTR (PARM2
), PARM3
);
2920 RETVAL
= (int)mn10300_callback
->write (mn10300_callback
, PARM1
,
2921 MEMPTR (PARM2
), PARM3
);
2924 RETVAL
= mn10300_callback
->lseek (mn10300_callback
, PARM1
, PARM2
, PARM3
);
2927 RETVAL
= mn10300_callback
->close (mn10300_callback
, PARM1
);
2930 RETVAL
= mn10300_callback
->open (mn10300_callback
, MEMPTR (PARM1
), PARM2
);
2933 /* EXIT - caller can look in PARM1 to work out the
2935 if (PARM1
== 0xdead || PARM1
== 0x1)
2936 State
.exception
= SIGABRT
;
2938 State
.exception
= SIGQUIT
;
2941 case SYS_stat
: /* added at hmsi */
2942 /* stat system call */
2944 struct stat host_stat
;
2947 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2951 /* Just wild-assed guesses. */
2952 store_mem (buf
, 2, host_stat
.st_dev
);
2953 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2954 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2955 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2956 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2957 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2958 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2959 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2960 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2961 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2962 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2967 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2970 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2973 RETVAL
= time (MEMPTR (PARM1
));
2978 RETVAL
= times (&tms
);
2979 store_mem (PARM1
, 4, tms
.tms_utime
);
2980 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2981 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2982 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2985 case SYS_gettimeofday
:
2989 RETVAL
= gettimeofday (&t
, &tz
);
2990 store_mem (PARM1
, 4, t
.tv_sec
);
2991 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2992 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2993 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2997 /* Cast the second argument to void *, to avoid type mismatch
2998 if a prototype is present. */
2999 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));
3009 void OP_F0FF (insn
, extension
)
3010 unsigned long insn
, extension
;
3016 void OP_CB (insn
, extension
)
3017 unsigned long insn
, extension
;
3022 void OP_F500 (insn
, extension
)
3023 unsigned long insn
, extension
;
3028 void OP_F6F0 (insn
, extension
)
3029 unsigned long insn
, extension
;
3034 void OP_F600 (insn
, extension
)
3035 unsigned long insn
, extension
;
3040 void OP_F90000 (insn
, extension
)
3041 unsigned long insn
, extension
;
3046 void OP_FB000000 (insn
, extension
)
3047 unsigned long insn
, extension
;
3052 void OP_FD000000 (insn
, extension
)
3053 unsigned long insn
, extension
;
3058 void OP_F610 (insn
, extension
)
3059 unsigned long insn
, extension
;
3064 void OP_F91400 (insn
, extension
)
3065 unsigned long insn
, extension
;
3070 void OP_FB140000 (insn
, extension
)
3071 unsigned long insn
, extension
;
3076 void OP_FD140000 (insn
, extension
)
3077 unsigned long insn
, extension
;
3082 void OP_F640 (insn
, extension
)
3083 unsigned long insn
, extension
;
3088 void OP_F650 (insn
, extension
)
3089 unsigned long insn
, extension
;
3094 void OP_F670 (insn
, extension
)
3095 unsigned long insn
, extension
;