7 #include "mn10300_sim.h"
9 #include "sys/syscall.h"
13 #include <sys/times.h>
21 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
22 static void trace_output
PARAMS ((enum op_types result
));
23 static int init_text_p
= 0;
24 static asection
*text
;
25 static bfd_vma text_start
;
26 static bfd_vma text_end
;
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
34 #define SIZE_OPERANDS 16
38 #define SIZE_VALUES 11
42 #define SIZE_LOCATION 40
46 trace_input (name
, type
, size
)
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
68 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = SEXT8 (insn
& 0xff);
74 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
80 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
86 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
92 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] = insn
& 0xff;
98 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
104 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_SP
];
110 State
.regs
[REG_SP
] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
116 State
.regs
[REG_D0
+ (insn
& 0x3)] = PSW
;
122 PSW
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
128 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_MDR
];
134 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
140 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
141 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
144 /* mov (d8,am), dn */
147 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
148 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
149 + SEXT8 (insn
& 0xff)), 4);
152 /* mov (d16,am), dn */
155 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
156 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
157 + SEXT16 (insn
& 0xffff)), 4);
160 /* mov (d32,am), dn */
163 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
164 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
165 + ((insn
& 0xffff) << 16) | extension
), 4);
168 /* mov (d8,sp), dn */
171 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
172 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
175 /* mov (d16,sp), dn */
178 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
179 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
182 /* mov (d32,sp), dn */
185 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
186 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
189 /* mov (di,am), dn */
192 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
193 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
194 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
197 /* mov (abs16), dn */
200 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 4);
203 /* mov (abs32), dn */
206 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
207 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
213 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]
214 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
217 /* mov (d8,am), an */
220 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]
221 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
222 + SEXT8 (insn
& 0xff)), 4);
225 /* mov (d16,am), an */
228 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]
229 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
230 + SEXT16 (insn
& 0xffff)), 4);
233 /* mov (d32,am), an */
236 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]
237 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
238 + ((insn
& 0xffff) << 16) + extension
), 4);
241 /* mov (d8,sp), an */
244 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
245 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4);
248 /* mov (d16,sp), an */
251 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
252 = load_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4);
255 /* mov (d32,sp), an */
258 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
259 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4);
262 /* mov (di,am), an */
265 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
266 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
267 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
270 /* mov (abs16), an */
273 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 4);
276 /* mov (abs32), an */
279 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
280 = load_mem ((((insn
& 0xffff) << 16) + extension
), 4);
283 /* mov (d8,am), sp */
287 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
288 + SEXT8 (insn
& 0xff)), 4);
294 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
295 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
298 /* mov dm, (d8,an) */
301 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
302 + SEXT8 (insn
& 0xff)), 4,
303 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
306 /* mov dm (d16,an) */
309 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
310 + SEXT16 (insn
& 0xffff)), 4,
311 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
314 /* mov dm (d32,an) */
317 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
318 + ((insn
& 0xffff) << 16) + extension
), 4,
319 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
322 /* mov dm, (d8,sp) */
325 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
326 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
329 /* mov dm, (d16,sp) */
332 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
333 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
336 /* mov dm, (d32,sp) */
339 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
340 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
343 /* mov dm, (di,an) */
346 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
347 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
348 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
351 /* mov dm, (abs16) */
354 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
357 /* mov dm, (abs32) */
360 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
366 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
367 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]);
370 /* mov am, (d8,an) */
373 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
374 + SEXT8 (insn
& 0xff)), 4,
375 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
378 /* mov am, (d16,an) */
381 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
382 + SEXT16 (insn
& 0xffff)), 4,
383 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
386 /* mov am, (d32,an) */
389 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
390 + ((insn
& 0xffff) << 16) + extension
), 4,
391 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
394 /* mov am, (d8,sp) */
397 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 4,
398 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
401 /* mov am, (d16,sp) */
404 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 4,
405 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
408 /* mov am, (d32,sp) */
411 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 4,
412 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
415 /* mov am, (di,an) */
418 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
419 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
420 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]);
423 /* mov am, (abs16) */
426 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
429 /* mov am, (abs32) */
432 store_mem ((((insn
& 0xffff) << 16) + extension
), 4, State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 18)]);
435 /* mov sp, (d8,an) */
438 store_mem (State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] + SEXT8 (insn
& 0xff),
439 4, State
.regs
[REG_SP
]);
447 value
= SEXT16 (insn
& 0xffff);
448 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
456 value
= (insn
& 0xffff) << 16 | extension
;
457 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
465 value
= insn
& 0xffff;
466 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
474 value
= (insn
& 0xffff) << 16 | extension
;
475 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
481 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
482 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 1);
485 /* movbu (d8,am), dn */
488 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
489 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
490 + SEXT8 (insn
& 0xff)), 1);
493 /* movbu (d16,am), dn */
496 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
497 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
498 + SEXT16 (insn
& 0xffff)), 1);
501 /* movbu (d32,am), dn */
504 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
505 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
506 + ((insn
& 0xffff) << 16) + extension
), 1);
509 /* movbu (d8,sp), dn */
512 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
513 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 1);
516 /* movbu (d16,sp), dn */
519 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
520 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 1);
523 /* movbu (d32,sp), dn */
526 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
527 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 1);
530 /* movbu (di,am), dn */
533 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
534 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
535 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1);
538 /* movbu (abs16), dn */
541 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 1);
544 /* movbu (abs32), dn */
547 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
548 = load_mem ((((insn
& 0xffff) << 16) + extension
), 1);
554 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 1,
555 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
558 /* movbu dm, (d8,an) */
561 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
562 + SEXT8 (insn
& 0xff)), 1,
563 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
566 /* movbu dm, (d16,an) */
569 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
570 + SEXT16 (insn
& 0xffff)), 1,
571 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
574 /* movbu dm, (d32,an) */
577 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
578 + ((insn
& 0xffff) << 16) + extension
), 1,
579 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
582 /* movbu dm, (d8,sp) */
585 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 1,
586 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
589 /* movbu dm, (d16,sp) */
592 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
593 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
596 /* movbu dm (d32,sp) */
599 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
600 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
603 /* movbu dm, (di,an) */
606 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
607 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1,
608 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
611 /* movbu dm, (abs16) */
614 store_mem ((insn
& 0xffff), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
617 /* movbu dm, (abs32) */
620 store_mem ((((insn
& 0xffff) << 16) + extension
), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
626 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
627 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 2);
630 /* movhu (d8,am), dn */
633 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]
634 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
635 + SEXT8 (insn
& 0xff)), 2);
638 /* movhu (d16,am), dn */
641 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
642 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
643 + SEXT16 (insn
& 0xffff)), 2);
646 /* movhu (d32,am), dn */
649 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]
650 = load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
651 + ((insn
& 0xffff) << 16) + extension
), 2);
654 /* movhu (d8,sp) dn */
657 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
658 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xff)), 2);
661 /* movhu (d16,sp), dn */
664 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
665 = load_mem ((State
.regs
[REG_SP
] + (insn
& 0xffff)), 2);
668 /* movhu (d32,sp), dn */
671 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
672 = load_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2);
675 /* movhu (di,am), dn */
678 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
679 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
680 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2);
683 /* movhu (abs16), dn */
686 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem ((insn
& 0xffff), 2);
689 /* movhu (abs32), dn */
692 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
693 = load_mem ((((insn
& 0xffff) << 16) + extension
), 2);
699 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 2,
700 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
703 /* movhu dm, (d8,an) */
706 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
707 + SEXT8 (insn
& 0xff)), 2,
708 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
711 /* movhu dm, (d16,an) */
714 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
715 + SEXT16 (insn
& 0xffff)), 2,
716 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
719 /* movhu dm, (d32,an) */
722 store_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
723 + ((insn
& 0xffff) << 16) + extension
), 2,
724 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
727 /* movhu dm,(d8,sp) */
730 store_mem (State
.regs
[REG_SP
] + (insn
& 0xff), 2,
731 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
734 /* movhu dm,(d16,sp) */
737 store_mem (State
.regs
[REG_SP
] + (insn
& 0xffff), 2,
738 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
741 /* movhu dm,(d32,sp) */
744 store_mem (State
.regs
[REG_SP
] + (((insn
& 0xffff) << 16) + extension
), 2,
745 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
748 /* movhu dm, (di,an) */
751 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
752 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2,
753 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]);
756 /* movhu dm, (abs16) */
759 store_mem ((insn
& 0xffff), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
762 /* movhu dm, (abs32) */
765 store_mem ((((insn
& 0xffff) << 16) + extension
), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
771 if (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000)
772 State
.regs
[REG_MDR
] = -1;
774 State
.regs
[REG_MDR
] = 0;
780 State
.regs
[REG_D0
+ (insn
& 0x3)] = SEXT8 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
786 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xff;
792 State
.regs
[REG_D0
+ (insn
& 0x3)]
793 = SEXT16 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
799 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xffff;
802 /* movm (sp), reg_list */
805 unsigned long sp
= State
.regs
[REG_SP
];
813 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
815 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
817 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
819 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
821 State
.regs
[REG_A0
] = load_mem (sp
, 4);
823 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
825 State
.regs
[REG_D0
] = load_mem (sp
, 4);
831 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
837 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
843 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
849 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
853 /* And make sure to update the stack pointer. */
854 State
.regs
[REG_SP
] = sp
;
857 /* movm reg_list, (sp) */
860 unsigned long sp
= State
.regs
[REG_SP
];
868 store_mem (sp
, 4, State
.regs
[REG_D0
+ 2]);
874 store_mem (sp
, 4, State
.regs
[REG_D0
+ 3]);
880 store_mem (sp
, 4, State
.regs
[REG_A0
+ 2]);
886 store_mem (sp
, 4, State
.regs
[REG_A0
+ 3]);
892 store_mem (sp
, 4, State
.regs
[REG_D0
]);
894 store_mem (sp
, 4, State
.regs
[REG_D0
+ 1]);
896 store_mem (sp
, 4, State
.regs
[REG_A0
]);
898 store_mem (sp
, 4, State
.regs
[REG_A0
+ 1]);
900 store_mem (sp
, 4, State
.regs
[REG_MDR
]);
902 store_mem (sp
, 4, State
.regs
[REG_LIR
]);
904 store_mem (sp
, 4, State
.regs
[REG_LAR
]);
908 /* And make sure to update the stack pointer. */
909 State
.regs
[REG_SP
] = sp
;
915 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] = 0;
918 PSW
&= ~(PSW_V
| PSW_C
| PSW_N
);
925 unsigned long reg1
, reg2
, value
;
927 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
928 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
930 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
933 n
= (value
& 0x80000000);
935 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
936 && (reg2
& 0x80000000) != (value
& 0x80000000));
938 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
939 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
940 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
947 unsigned long reg1
, reg2
, value
;
949 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
950 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
952 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
955 n
= (value
& 0x80000000);
957 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
958 && (reg2
& 0x80000000) != (value
& 0x80000000));
960 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
961 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
962 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
969 unsigned long reg1
, reg2
, value
;
971 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
972 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
974 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
977 n
= (value
& 0x80000000);
979 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
980 && (reg2
& 0x80000000) != (value
& 0x80000000));
982 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
983 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
984 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
991 unsigned long reg1
, reg2
, value
;
993 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
994 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
996 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
999 n
= (value
& 0x80000000);
1001 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1002 && (reg2
& 0x80000000) != (value
& 0x80000000));
1004 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1005 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1006 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1013 unsigned long reg1
, imm
, value
;
1015 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1016 imm
= SEXT8 (insn
& 0xff);
1018 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = value
;
1021 n
= (value
& 0x80000000);
1023 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1024 && (reg1
& 0x80000000) != (value
& 0x80000000));
1026 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1027 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1028 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1035 unsigned long reg1
, imm
, value
;
1037 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1038 imm
= SEXT16 (insn
& 0xffff);
1040 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
1043 n
= (value
& 0x80000000);
1045 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1046 && (reg1
& 0x80000000) != (value
& 0x80000000));
1048 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1049 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1050 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1057 unsigned long reg1
, imm
, value
;
1059 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1060 imm
= ((insn
& 0xffff) << 16) | extension
;
1062 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
1065 n
= (value
& 0x80000000);
1067 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1068 && (reg1
& 0x80000000) != (value
& 0x80000000));
1070 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1071 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1072 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1079 unsigned long reg1
, imm
, value
;
1081 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1082 imm
= SEXT8 (insn
& 0xff);
1084 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)] = value
;
1087 n
= (value
& 0x80000000);
1089 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1090 && (reg1
& 0x80000000) != (value
& 0x80000000));
1092 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1093 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1094 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1101 unsigned long reg1
, imm
, value
;
1103 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1104 imm
= SEXT16 (insn
& 0xffff);
1106 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
1109 n
= (value
& 0x80000000);
1111 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1112 && (reg1
& 0x80000000) != (value
& 0x80000000));
1114 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1115 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1116 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1123 unsigned long reg1
, imm
, value
;
1125 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1126 imm
= ((insn
& 0xffff) << 16) | extension
;
1128 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
1131 n
= (value
& 0x80000000);
1133 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1134 && (reg1
& 0x80000000) != (value
& 0x80000000));
1136 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1137 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1138 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1145 unsigned long reg1
, imm
, value
;
1147 reg1
= State
.regs
[REG_SP
];
1148 imm
= SEXT8 (insn
& 0xff);
1150 State
.regs
[REG_SP
] = value
;
1157 unsigned long reg1
, imm
, value
;
1159 reg1
= State
.regs
[REG_SP
];
1160 imm
= SEXT16 (insn
& 0xffff);
1162 State
.regs
[REG_SP
] = value
;
1169 unsigned long reg1
, imm
, value
;
1171 reg1
= State
.regs
[REG_SP
];
1172 imm
= ((insn
& 0xffff) << 16) | extension
;
1174 State
.regs
[REG_SP
] = value
;
1181 unsigned long reg1
, reg2
, value
;
1183 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1184 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1185 value
= reg1
+ reg2
+ ((PSW
& PSW_C
) != 0);
1186 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1189 n
= (value
& 0x80000000);
1191 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1192 && (reg2
& 0x80000000) != (value
& 0x80000000));
1194 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1195 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1196 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1203 unsigned long reg1
, reg2
, value
;
1205 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1206 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1207 value
= reg2
- reg1
;
1210 n
= (value
& 0x80000000);
1212 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1213 && (reg2
& 0x80000000) != (value
& 0x80000000));
1215 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1216 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1217 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1218 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1225 unsigned long reg1
, reg2
, value
;
1227 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1228 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1229 value
= reg2
- reg1
;
1232 n
= (value
& 0x80000000);
1234 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1235 && (reg2
& 0x80000000) != (value
& 0x80000000));
1237 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1238 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1239 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1240 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1247 unsigned long reg1
, reg2
, value
;
1249 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1250 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1251 value
= reg2
- reg1
;
1254 n
= (value
& 0x80000000);
1256 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1257 && (reg2
& 0x80000000) != (value
& 0x80000000));
1259 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1260 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1261 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1262 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1269 unsigned long reg1
, reg2
, value
;
1271 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1272 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1273 value
= reg2
- reg1
;
1276 n
= (value
& 0x80000000);
1278 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1279 && (reg2
& 0x80000000) != (value
& 0x80000000));
1281 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1282 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1283 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1284 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1291 unsigned long reg1
, imm
, value
;
1293 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1294 imm
= ((insn
& 0xffff) << 16) | extension
;
1298 n
= (value
& 0x80000000);
1300 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1301 && (reg1
& 0x80000000) != (value
& 0x80000000));
1303 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1304 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1305 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1306 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = value
;
1313 unsigned long reg1
, imm
, value
;
1315 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1316 imm
= ((insn
& 0xffff) << 16) | extension
;
1320 n
= (value
& 0x80000000);
1322 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1323 && (reg1
& 0x80000000) != (value
& 0x80000000));
1325 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1326 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1327 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1328 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
1335 unsigned long reg1
, reg2
, value
;
1337 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1338 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1339 value
= reg2
- reg1
- ((PSW
& PSW_C
) != 0);
1342 n
= (value
& 0x80000000);
1344 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1345 && (reg2
& 0x80000000) != (value
& 0x80000000));
1347 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1348 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1349 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1350 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1356 unsigned long long temp
;
1359 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1360 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1361 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1362 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1363 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1364 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1365 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1366 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1372 unsigned long long temp
;
1375 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1376 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1377 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1378 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1379 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1380 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1381 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1382 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1391 temp
= State
.regs
[REG_MDR
];
1393 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1394 State
.regs
[REG_MDR
] = temp
% (long)State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1395 temp
/= (long)State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1396 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1397 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1398 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1399 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1400 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1401 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1407 unsigned long long temp
;
1410 temp
= State
.regs
[REG_MDR
];
1412 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1413 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1414 temp
/= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1415 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1416 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1417 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1418 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1419 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1420 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1427 unsigned int value
, imm
, reg1
;
1429 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1432 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] = value
;
1435 n
= (value
& 0x80000000);
1437 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1438 && (reg1
& 0x80000000) != (value
& 0x80000000));
1440 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1441 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1442 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1448 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)] += 1;
1454 State
.regs
[REG_A0
+ (insn
& 0x3)] += 4;
1461 unsigned long reg1
, imm
, value
;
1463 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1464 imm
= SEXT8 (insn
& 0xff);
1468 n
= (value
& 0x80000000);
1470 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1471 && (reg1
& 0x80000000) != (value
& 0x80000000));
1473 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1474 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1475 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1482 unsigned long reg1
, reg2
, value
;
1484 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1485 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1486 value
= reg2
- reg1
;
1489 n
= (value
& 0x80000000);
1491 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1492 && (reg2
& 0x80000000) != (value
& 0x80000000));
1494 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1495 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1496 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1503 unsigned long reg1
, reg2
, value
;
1505 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1506 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1507 value
= reg2
- reg1
;
1510 n
= (value
& 0x80000000);
1512 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1513 && (reg2
& 0x80000000) != (value
& 0x80000000));
1515 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1516 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1517 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1524 unsigned long reg1
, reg2
, value
;
1526 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1527 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1528 value
= reg2
- reg1
;
1531 n
= (value
& 0x80000000);
1533 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1534 && (reg2
& 0x80000000) != (value
& 0x80000000));
1536 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1537 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1538 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1545 unsigned long reg1
, imm
, value
;
1547 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1552 n
= (value
& 0x80000000);
1554 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1555 && (reg1
& 0x80000000) != (value
& 0x80000000));
1557 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1558 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1559 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1566 unsigned long reg1
, reg2
, value
;
1568 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1569 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1570 value
= reg2
- reg1
;
1573 n
= (value
& 0x80000000);
1575 v
= ((reg2
& 0x80000000) != (reg1
& 0x80000000)
1576 && (reg2
& 0x80000000) != (value
& 0x80000000));
1578 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1579 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1580 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1587 unsigned long reg1
, imm
, value
;
1589 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1590 imm
= SEXT16 (insn
& 0xffff);
1594 n
= (value
& 0x80000000);
1596 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1597 && (reg1
& 0x80000000) != (value
& 0x80000000));
1599 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1600 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1601 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1608 unsigned long reg1
, imm
, value
;
1610 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1611 imm
= ((insn
& 0xffff) << 16) | extension
;
1615 n
= (value
& 0x80000000);
1617 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1618 && (reg1
& 0x80000000) != (value
& 0x80000000));
1620 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1621 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1622 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1629 unsigned long reg1
, imm
, value
;
1631 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1632 imm
= insn
& 0xffff;
1636 n
= (value
& 0x80000000);
1638 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1639 && (reg1
& 0x80000000) != (value
& 0x80000000));
1641 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1642 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1643 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1650 unsigned long reg1
, imm
, value
;
1652 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)];
1653 imm
= ((insn
& 0xffff) << 16) | extension
;
1657 n
= (value
& 0x80000000);
1659 v
= ((reg1
& 0x80000000) != (imm
& 0x80000000)
1660 && (reg1
& 0x80000000) != (value
& 0x80000000));
1662 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1663 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1664 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1672 State
.regs
[REG_D0
+ (insn
& 0x3)] &= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1673 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1674 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1675 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1676 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1684 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] &= (insn
& 0xff);
1685 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
1686 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
1687 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1688 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1696 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] &= (insn
& 0xffff);
1697 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1698 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1699 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1700 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1708 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1709 &= ((insn
& 0xffff) << 16 | extension
);
1710 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1711 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1712 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1713 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1716 /* and imm16, psw */
1719 PSW
&= (insn
& 0xffff);
1727 State
.regs
[REG_D0
+ (insn
& 0x3)] |= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1728 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1729 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1730 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1731 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1739 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] |= insn
& 0xff;
1740 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
1741 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
1742 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1743 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1751 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] |= insn
& 0xffff;
1752 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1753 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1754 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1755 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1763 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1764 |= ((insn
& 0xffff) << 16 | extension
);
1765 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1766 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1767 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1768 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1774 PSW
|= (insn
& 0xffff);
1782 State
.regs
[REG_D0
+ (insn
& 0x3)] ^= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1783 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1784 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1785 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1786 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1794 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] ^= insn
& 0xffff;
1795 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1796 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1797 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1798 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1806 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)]
1807 ^= ((insn
& 0xffff) << 16 | extension
);
1808 z
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] == 0);
1809 n
= (State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] & 0x80000000) != 0;
1810 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1811 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1819 State
.regs
[REG_D0
+ (insn
& 0x3)] = ~State
.regs
[REG_D0
+ (insn
& 0x3)];
1820 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1821 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1822 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1823 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1832 temp
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1833 temp
&= (insn
& 0xff);
1834 n
= (temp
& 0x80000000) != 0;
1836 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1837 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1840 /* btst imm16, dn */
1846 temp
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1847 temp
&= (insn
& 0xffff);
1848 n
= (temp
& 0x80000000) != 0;
1850 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1851 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1854 /* btst imm32, dn */
1860 temp
= State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)];
1861 temp
&= ((insn
& 0xffff) << 16 | extension
);
1862 n
= (temp
& 0x80000000) != 0;
1864 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1865 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1868 /* btst imm8,(abs32) */
1874 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
1875 temp
&= (extension
& 0xff);
1876 n
= (temp
& 0x80000000) != 0;
1878 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1879 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1882 /* btst imm8,(d8,an) */
1888 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
1889 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
1890 temp
&= (insn
& 0xff);
1891 n
= (temp
& 0x80000000) != 0;
1893 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1894 PSW
|= (z
? PSW_Z
: 0) | (n
? PSW_N
: 0);
1903 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
1904 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
1905 temp
|= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1906 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
1907 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1908 PSW
|= (z
? PSW_Z
: 0);
1911 /* bset imm8, (abs32) */
1917 temp
= load_mem (((insn
& 0xffff) << 16 | (extension
>> 8)), 1);
1918 z
= (temp
& (extension
& 0xff)) == 0;
1919 temp
|= (extension
& 0xff);
1920 store_mem ((((insn
& 0xffff) << 16) | (extension
>> 8)), 1, temp
);
1921 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1922 PSW
|= (z
? PSW_Z
: 0);
1925 /* bset imm8,(d8,an) */
1931 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
1932 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
1933 z
= (temp
& (insn
& 0xff)) == 0;
1934 temp
|= (insn
& 0xff);
1935 store_mem (State
.regs
[REG_A0
+ ((insn
& 30000)>> 16)], 1, temp
);
1936 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1937 PSW
|= (z
? PSW_Z
: 0);
1946 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
1947 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
1948 temp
= ~temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1949 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
1950 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1951 PSW
|= (z
? PSW_Z
: 0);
1954 /* bclr imm8, (abs32) */
1960 temp
= load_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1);
1961 z
= (temp
& (extension
& 0xff)) == 0;
1962 temp
= ~temp
& (extension
& 0xff);
1963 store_mem (((insn
& 0xffff) << 16) | (extension
>> 8), 1, temp
);
1964 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1965 PSW
|= (z
? PSW_Z
: 0);
1968 /* bclr imm8,(d8,an) */
1974 temp
= load_mem ((State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)]
1975 + SEXT8 ((insn
& 0xff00) >> 8)), 1);
1976 z
= (temp
& (insn
& 0xff)) == 0;
1977 temp
= ~temp
& (insn
& 0xff);
1978 store_mem (State
.regs
[REG_A0
+ ((insn
& 30000)>> 16)], 1, temp
);
1979 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1980 PSW
|= (z
? PSW_Z
: 0);
1989 temp
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1991 temp
>>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1992 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
;
1993 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1994 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
1995 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
1996 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2005 temp
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
2007 temp
>>= (insn
& 0xff);
2008 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = temp
;
2009 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
2010 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
2011 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2012 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2020 c
= State
.regs
[REG_D0
+ (insn
& 0x3)] & 1;
2021 State
.regs
[REG_D0
+ (insn
& 0x3)]
2022 >>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2023 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2024 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2025 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2026 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2034 c
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 1;
2035 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] >>= (insn
& 0xff);
2036 z
= (State
.regs
[REG_D0
+ ((insn
& 0x3) >> 8)] == 0);
2037 n
= (State
.regs
[REG_D0
+ ((insn
& 0x3) >> 8)] & 0x80000000) != 0;
2038 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
2039 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2047 State
.regs
[REG_D0
+ (insn
& 0x3)]
2048 <<= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
2049 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2050 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2051 PSW
&= ~(PSW_Z
| PSW_N
);
2052 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2060 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] <<= (insn
& 0xff);
2061 z
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] == 0);
2062 n
= (State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] & 0x80000000) != 0;
2063 PSW
&= ~(PSW_Z
| PSW_N
);
2064 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2072 State
.regs
[REG_D0
+ (insn
& 0x3)] <<= 2;
2073 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
2074 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000) != 0;
2075 PSW
&= ~(PSW_Z
| PSW_N
);
2076 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
2082 unsigned long value
;
2085 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2090 value
|= ((PSW
& PSW_C
) != 0) ? 0x80000000 : 0;
2091 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
2093 n
= (value
& 0x80000000) != 0;
2094 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2095 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2101 unsigned long value
;
2104 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
2105 if (value
& 0x80000000)
2109 value
|= ((PSW
& PSW_C
) != 0);
2110 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
2112 n
= (value
& 0x80000000) != 0;
2113 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
2114 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
2120 /* The dispatching code will add 2 after we return, so
2121 we subtract two here to make things right. */
2123 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2129 /* The dispatching code will add 2 after we return, so
2130 we subtract two here to make things right. */
2132 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2138 /* The dispatching code will add 2 after we return, so
2139 we subtract two here to make things right. */
2141 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)))
2142 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2148 /* The dispatching code will add 2 after we return, so
2149 we subtract two here to make things right. */
2150 if (!(((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
2151 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2157 /* The dispatching code will add 2 after we return, so
2158 we subtract two here to make things right. */
2160 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
2161 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2167 /* The dispatching code will add 2 after we return, so
2168 we subtract two here to make things right. */
2169 if (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)
2170 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2176 /* The dispatching code will add 2 after we return, so
2177 we subtract two here to make things right. */
2178 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
2179 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2185 /* The dispatching code will add 2 after we return, so
2186 we subtract two here to make things right. */
2188 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2194 /* The dispatching code will add 2 after we return, so
2195 we subtract two here to make things right. */
2196 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
2197 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2203 /* The dispatching code will add 2 after we return, so
2204 we subtract two here to make things right. */
2206 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2212 /* The dispatching code will add 3 after we return, so
2213 we subtract two here to make things right. */
2215 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2221 /* The dispatching code will add 3 after we return, so
2222 we subtract two here to make things right. */
2224 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2230 /* The dispatching code will add 3 after we return, so
2231 we subtract two here to make things right. */
2233 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2239 /* The dispatching code will add 3 after we return, so
2240 we subtract two here to make things right. */
2242 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
2248 /* The dispatching code will add 2 after we return, so
2249 we subtract two here to make things right. */
2250 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2328 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2334 State
.pc
+= SEXT16 (insn
& 0xffff) - 3;
2340 State
.pc
+= (((insn
& 0xffffff) << 8) | extension
) - 5;
2343 /* call label:16,reg_list,imm8 */
2346 unsigned int next_pc
, sp
, adjust
;
2349 sp
= State
.regs
[REG_SP
];
2350 next_pc
= State
.pc
+ 2;
2351 State
.mem
[sp
] = next_pc
& 0xff;
2352 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2353 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2354 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2362 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2368 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2374 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2380 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2386 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2388 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2390 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2392 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2394 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2396 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2398 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2402 /* And make sure to update the stack pointer. */
2403 State
.regs
[REG_SP
] -= extension
;
2404 State
.regs
[REG_MDR
] = next_pc
;
2405 State
.pc
+= SEXT16 ((insn
& 0xffff00) >> 8) - 5;
2408 /* call label:32,reg_list,imm8*/
2411 unsigned int next_pc
, sp
, adjust
;
2414 sp
= State
.regs
[REG_SP
];
2415 next_pc
= State
.pc
+ 2;
2416 State
.mem
[sp
] = next_pc
& 0xff;
2417 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2418 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2419 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2421 mask
= (extension
& 0xff00) >> 8;
2427 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2433 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2439 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2445 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2451 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2453 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2455 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2457 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2459 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2461 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2463 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2467 /* And make sure to update the stack pointer. */
2468 State
.regs
[REG_SP
] -= (extension
& 0xff);
2469 State
.regs
[REG_MDR
] = next_pc
;
2470 State
.pc
+= (((insn
& 0xffffff) << 8) | ((extension
& 0xff0000) >> 16)) - 7;
2476 unsigned int next_pc
, sp
;
2478 sp
= State
.regs
[REG_SP
];
2479 next_pc
= State
.pc
+ 2;
2480 State
.mem
[sp
] = next_pc
& 0xff;
2481 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2482 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2483 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2484 State
.regs
[REG_MDR
] = next_pc
;
2485 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2488 /* calls label:16 */
2491 unsigned int next_pc
, sp
;
2493 sp
= State
.regs
[REG_SP
];
2494 next_pc
= State
.pc
+ 4;
2495 State
.mem
[sp
] = next_pc
& 0xff;
2496 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2497 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2498 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2499 State
.regs
[REG_MDR
] = next_pc
;
2500 State
.pc
+= SEXT16 (insn
& 0xffff) - 4;
2503 /* calls label:32 */
2506 unsigned int next_pc
, sp
;
2508 sp
= State
.regs
[REG_SP
];
2509 next_pc
= State
.pc
+ 6;
2510 State
.mem
[sp
] = next_pc
& 0xff;
2511 State
.mem
[sp
+1] = (next_pc
& 0xff00) >> 8;
2512 State
.mem
[sp
+2] = (next_pc
& 0xff0000) >> 16;
2513 State
.mem
[sp
+3] = (next_pc
& 0xff000000) >> 24;
2514 State
.regs
[REG_MDR
] = next_pc
;
2515 State
.pc
+= (((insn
& 0xffff) << 16) | extension
) - 6;
2518 /* ret reg_list, imm8 */
2524 State
.regs
[REG_SP
] += insn
& 0xff;
2525 State
.pc
= State
.regs
[REG_MDR
] - 3;
2526 sp
= State
.regs
[REG_SP
];
2528 mask
= (insn
& 0xff00) >> 8;
2533 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2535 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2537 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2539 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2541 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2543 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2545 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2551 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2557 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2563 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2569 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2574 /* retf reg_list,imm8 */
2580 State
.regs
[REG_SP
] += insn
& 0xff;
2581 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2582 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2585 sp
= State
.regs
[REG_SP
];
2587 mask
= (insn
& 0xff00) >> 8;
2592 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2594 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2596 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2598 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2600 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2602 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2604 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2610 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2616 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2622 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2628 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2638 sp
= State
.regs
[REG_SP
];
2639 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2640 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2653 /* We use this for simulated system calls; we may need to change
2654 it to a reserved instruction if we conflict with uses at
2656 int save_errno
= errno
;
2659 /* Registers passed to trap 0 */
2661 /* Function number. */
2662 #define FUNC (load_mem (State.regs[REG_SP] + 4, 4))
2665 #define PARM1 (load_mem (State.regs[REG_SP] + 8, 4))
2666 #define PARM2 (load_mem (State.regs[REG_SP] + 12, 4))
2667 #define PARM3 (load_mem (State.regs[REG_SP] + 16, 4))
2669 /* Registers set by trap 0 */
2671 #define RETVAL State.regs[0] /* return value */
2672 #define RETERR State.regs[1] /* return error code */
2674 /* Turn a pointer in a register into a pointer into real memory. */
2676 #define MEMPTR(x) (State.mem + x)
2680 #if !defined(__GO32__) && !defined(_WIN32)
2685 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
),
2686 (char **)MEMPTR (PARM3
));
2689 RETVAL
= execve (MEMPTR (PARM1
), (char **) MEMPTR (PARM2
), NULL
);
2694 RETVAL
= mn10300_callback
->read (mn10300_callback
, PARM1
,
2695 MEMPTR (PARM2
), PARM3
);
2699 RETVAL
= (int)mn10300_callback
->write_stdout (mn10300_callback
,
2700 MEMPTR (PARM2
), PARM3
);
2702 RETVAL
= (int)mn10300_callback
->write (mn10300_callback
, PARM1
,
2703 MEMPTR (PARM2
), PARM3
);
2706 RETVAL
= mn10300_callback
->lseek (mn10300_callback
, PARM1
, PARM2
, PARM3
);
2709 RETVAL
= mn10300_callback
->close (mn10300_callback
, PARM1
);
2712 RETVAL
= mn10300_callback
->open (mn10300_callback
, MEMPTR (PARM1
), PARM2
);
2715 /* EXIT - caller can look in PARM1 to work out the
2717 if (PARM1
== 0xdead || PARM1
== 0x1)
2718 State
.exception
= SIGABRT
;
2720 State
.exception
= SIGQUIT
;
2723 case SYS_stat
: /* added at hmsi */
2724 /* stat system call */
2726 struct stat host_stat
;
2729 RETVAL
= stat (MEMPTR (PARM1
), &host_stat
);
2733 /* Just wild-assed guesses. */
2734 store_mem (buf
, 2, host_stat
.st_dev
);
2735 store_mem (buf
+ 2, 2, host_stat
.st_ino
);
2736 store_mem (buf
+ 4, 4, host_stat
.st_mode
);
2737 store_mem (buf
+ 8, 2, host_stat
.st_nlink
);
2738 store_mem (buf
+ 10, 2, host_stat
.st_uid
);
2739 store_mem (buf
+ 12, 2, host_stat
.st_gid
);
2740 store_mem (buf
+ 14, 2, host_stat
.st_rdev
);
2741 store_mem (buf
+ 16, 4, host_stat
.st_size
);
2742 store_mem (buf
+ 20, 4, host_stat
.st_atime
);
2743 store_mem (buf
+ 28, 4, host_stat
.st_mtime
);
2744 store_mem (buf
+ 36, 4, host_stat
.st_ctime
);
2749 RETVAL
= chown (MEMPTR (PARM1
), PARM2
, PARM3
);
2752 RETVAL
= chmod (MEMPTR (PARM1
), PARM2
);
2755 RETVAL
= time (MEMPTR (PARM1
));
2760 RETVAL
= times (&tms
);
2761 store_mem (PARM1
, 4, tms
.tms_utime
);
2762 store_mem (PARM1
+ 4, 4, tms
.tms_stime
);
2763 store_mem (PARM1
+ 8, 4, tms
.tms_cutime
);
2764 store_mem (PARM1
+ 12, 4, tms
.tms_cstime
);
2767 case SYS_gettimeofday
:
2771 RETVAL
= gettimeofday (&t
, &tz
);
2772 store_mem (PARM1
, 4, t
.tv_sec
);
2773 store_mem (PARM1
+ 4, 4, t
.tv_usec
);
2774 store_mem (PARM2
, 4, tz
.tz_minuteswest
);
2775 store_mem (PARM2
+ 4, 4, tz
.tz_dsttime
);
2779 /* Cast the second argument to void *, to avoid type mismatch
2780 if a prototype is present. */
2781 RETVAL
= utime (MEMPTR (PARM1
), (void *) MEMPTR (PARM2
));