7 #include "mn10300_sim.h"
9 #include "sys/syscall.h"
13 #include <sys/times.h>
21 static void trace_input
PARAMS ((char *name
, enum op_types type
, int size
));
22 static void trace_output
PARAMS ((enum op_types result
));
23 static int init_text_p
= 0;
24 static asection
*text
;
25 static bfd_vma text_start
;
26 static bfd_vma text_end
;
29 #ifndef SIZE_INSTRUCTION
30 #define SIZE_INSTRUCTION 6
34 #define SIZE_OPERANDS 16
38 #define SIZE_VALUES 11
42 #define SIZE_LOCATION 40
46 trace_input (name
, type
, size
)
60 #define trace_input(NAME, IN1, IN2)
61 #define trace_output(RESULT)
68 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = SEXT8 (insn
& 0xff);
74 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
80 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)] = State
.regs
[REG_D0
+ (insn
& 0x3)];
86 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
92 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)] = insn
& 0xff;
98 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
104 State
.regs
[REG_A0
+ (insn
& 0x3)] = State
.regs
[REG_SP
];
110 State
.regs
[REG_SP
] = State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
116 State
.regs
[REG_D0
+ (insn
& 0x3)] = PSW
;
122 PSW
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
128 State
.regs
[REG_D0
+ (insn
& 0x3)] = State
.regs
[REG_MDR
];
134 State
.regs
[REG_MDR
] = State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
140 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
141 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
159 /* mov (d8,sp), dn */
162 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)]
163 = load_mem (State
.regs
[REG_SP
] + insn
& 0xff, 4);
176 /* mov (di,am), dn */
179 State
.regs
[REG_D0
+ ((insn
& 0x30) >> 8)]
180 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
181 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
184 /* mov (abs16), dn */
187 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem (insn
& 0xffff, 4);
198 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]
199 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4);
217 /* mov (d8,sp), an */
220 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)]
221 = load_mem (State
.regs
[REG_SP
] + insn
& 0xff, 4);
237 State
.regs
[REG_A0
+ ((insn
& 0x30) >> 8)]
238 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
239 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4);
260 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
261 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
279 /* mov dm, (d8,sp) */
282 store_mem (State
.regs
[REG_SP
] + insn
& 0xff, 4,
283 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 10)]);
296 /* mov dm, (di,an) */
299 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
300 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
301 State
.regs
[REG_D0
+ ((insn
& 0x30) >> 8)]);
304 /* mov dm, (abs16) */
307 store_mem ((insn
& 0xffff), 4, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
318 store_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 4,
319 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)]);
337 /* mov am, (d8,sp) */
340 store_mem (State
.regs
[REG_SP
] + insn
& 0xff, 4,
341 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 10)]);
354 /* mov am, (di,an) */
357 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
358 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 4,
359 State
.regs
[REG_A0
+ ((insn
& 0x30) >> 8)]);
382 value
= SEXT16 (insn
& 0xffff);
383 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
396 value
= insn
& 0xffff;
397 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
405 value
= (insn
& 0xffff) << 16 | extension
;
406 State
.regs
[REG_A0
+ ((insn
& 0x30000) >> 16)] = value
;
412 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
413 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 1);
446 /* movbu (di,am), dn */
449 State
.regs
[REG_D0
+ ((insn
& 0x30) >> 8)]
450 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
451 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1);
454 /* movbu (abs16), dn */
457 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem (insn
& 0xffff, 1);
468 store_mem (State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)], 1,
469 State
.regs
[REG_D0
+ (insn
& 0x3)]);
502 /* movbu dm, (di,an) */
505 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
506 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 1,
507 State
.regs
[REG_D0
+ ((insn
& 0x30) >> 8)]);
510 /* movbu dm, (abs16) */
513 store_mem ((insn
& 0xffff), 1, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
524 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]
525 = load_mem (State
.regs
[REG_A0
+ (insn
& 0x3)], 2);
558 /* movhu (di,am), dn */
561 State
.regs
[REG_D0
+ ((insn
& 0x30) >> 8)]
562 = load_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
563 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2);
566 /* movhu (abs16), dn */
569 State
.regs
[REG_D0
+ ((insn
& 0x30000) >> 16)] = load_mem (insn
& 0xffff, 2);
580 store_mem (State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)], 2,
581 State
.regs
[REG_D0
+ (insn
& 0x3)]);
614 /* movhu dm, (di,an) */
617 store_mem ((State
.regs
[REG_A0
+ (insn
& 0x3)]
618 + State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]), 2,
619 State
.regs
[REG_D0
+ ((insn
& 0x30) >> 8)]);
622 /* movhu dm, (abs16) */
625 store_mem ((insn
& 0xffff), 2, State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 18)]);
636 if (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x80000000)
637 State
.regs
[REG_MDR
] = -1;
639 State
.regs
[REG_MDR
] = 0;
645 State
.regs
[REG_D0
+ (insn
& 0x3)] = SEXT8 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
651 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xff;
657 State
.regs
[REG_D0
+ (insn
& 0x3)]
658 = SEXT16 (State
.regs
[REG_D0
+ (insn
& 0x3)]);
664 State
.regs
[REG_D0
+ (insn
& 0x3)] &= 0xffff;
667 /* movm (sp), reg_list */
670 unsigned long sp
= State
.regs
[REG_SP
];
678 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
680 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
682 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
684 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
686 State
.regs
[REG_A0
] = load_mem (sp
, 4);
688 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
690 State
.regs
[REG_D0
] = load_mem (sp
, 4);
696 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
702 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
708 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
714 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
718 /* And make sure to update the stack pointer. */
719 State
.regs
[REG_SP
] = sp
;
722 /* movm reg_list, (sp) */
725 unsigned long sp
= State
.regs
[REG_SP
];
733 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
739 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
745 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
751 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
757 State
.regs
[REG_D0
] = load_mem (sp
, 4);
759 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
761 State
.regs
[REG_A0
] = load_mem (sp
, 4);
763 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
765 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
767 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
769 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
773 /* And make sure to update the stack pointer. */
774 State
.regs
[REG_SP
] = sp
;
780 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] = 0;
783 PSW
&= ~(PSW_V
| PSW_C
| PSW_N
);
790 unsigned long reg1
, reg2
, value
;
792 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
793 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
795 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
798 n
= (value
& 0x80000000);
800 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
801 && (reg2
& 0x8000000) != (value
& 0x80000000));
803 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
804 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
805 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
812 unsigned long reg1
, reg2
, value
;
814 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
815 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
817 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
820 n
= (value
& 0x80000000);
822 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
823 && (reg2
& 0x8000000) != (value
& 0x80000000));
825 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
826 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
827 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
834 unsigned long reg1
, reg2
, value
;
836 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
837 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
839 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
842 n
= (value
& 0x80000000);
844 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
845 && (reg2
& 0x8000000) != (value
& 0x80000000));
847 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
848 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
849 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
856 unsigned long reg1
, reg2
, value
;
858 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
859 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
861 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
864 n
= (value
& 0x80000000);
866 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
867 && (reg2
& 0x8000000) != (value
& 0x80000000));
869 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
870 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
871 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
878 unsigned long reg1
, imm
, value
;
880 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 8)];
881 imm
= SEXT8 (insn
& 0xff);
883 State
.regs
[REG_D0
+ ((insn
& 0xc00) >> 8)] = value
;
886 n
= (value
& 0x80000000);
888 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
889 && (imm
& 0x8000000) != (value
& 0x80000000));
891 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
892 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
893 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
900 unsigned long reg1
, imm
, value
;
902 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)];
903 imm
= SEXT16 (insn
& 0xffff);
905 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)] = value
;
908 n
= (value
& 0x80000000);
910 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
911 && (imm
& 0x8000000) != (value
& 0x80000000));
913 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
914 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
915 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
922 unsigned long reg1
, imm
, value
;
924 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)];
925 imm
= ((insn
& 0xffff) << 16) | extension
;
927 State
.regs
[REG_D0
+ ((insn
& 0xc0000) >> 16)] = value
;
930 n
= (value
& 0x80000000);
932 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
933 && (imm
& 0x8000000) != (value
& 0x80000000));
935 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
936 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
937 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
944 unsigned long reg1
, imm
, value
;
946 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 8)];
949 State
.regs
[REG_A0
+ ((insn
& 0xc00) >> 8)] = value
;
952 n
= (value
& 0x80000000);
954 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
955 && (imm
& 0x8000000) != (value
& 0x80000000));
957 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
958 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
959 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
966 unsigned long reg1
, imm
, value
;
968 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)];
971 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)] = value
;
974 n
= (value
& 0x80000000);
976 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
977 && (imm
& 0x8000000) != (value
& 0x80000000));
979 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
980 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
981 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
988 unsigned long reg1
, imm
, value
;
990 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)];
991 imm
= ((insn
& 0xffff) << 16) | extension
;
993 State
.regs
[REG_A0
+ ((insn
& 0xc0000) >> 16)] = value
;
996 n
= (value
& 0x80000000);
998 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
999 && (imm
& 0x8000000) != (value
& 0x80000000));
1001 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1002 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1003 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1010 unsigned long reg1
, imm
, value
;
1012 reg1
= State
.regs
[REG_SP
];
1013 imm
= SEXT8 (insn
& 0xff);
1015 State
.regs
[REG_SP
] = value
;
1018 n
= (value
& 0x80000000);
1020 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1021 && (imm
& 0x8000000) != (value
& 0x80000000));
1023 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1024 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1025 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1032 unsigned long reg1
, imm
, value
;
1034 reg1
= State
.regs
[REG_SP
];
1035 imm
= SEXT16 (insn
& 0xffff);
1037 State
.regs
[REG_SP
] = value
;
1040 n
= (value
& 0x80000000);
1042 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1043 && (imm
& 0x8000000) != (value
& 0x80000000));
1045 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1046 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1047 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1054 unsigned long reg1
, imm
, value
;
1056 reg1
= State
.regs
[REG_SP
];
1057 imm
= ((insn
& 0xffff) << 16) | extension
;
1059 State
.regs
[REG_SP
] = value
;
1062 n
= (value
& 0x80000000);
1064 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1065 && (imm
& 0x8000000) != (value
& 0x80000000));
1067 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1068 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1069 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1076 unsigned long reg1
, reg2
, value
;
1078 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1079 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1080 value
= reg1
+ reg2
+ ((PSW
& PSW_C
) != 0);
1081 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1084 n
= (value
& 0x80000000);
1086 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1087 && (reg2
& 0x8000000) != (value
& 0x80000000));
1089 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1090 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1091 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1098 unsigned long reg1
, reg2
, value
;
1100 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1101 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1102 value
= reg2
- reg1
;
1105 n
= (value
& 0x80000000);
1107 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1108 && (reg2
& 0x8000000) != (value
& 0x80000000));
1110 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1111 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1112 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1113 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1120 unsigned long reg1
, reg2
, value
;
1122 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1123 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1124 value
= reg2
- reg1
;
1127 n
= (value
& 0x80000000);
1129 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1130 && (reg2
& 0x8000000) != (value
& 0x80000000));
1132 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1133 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1134 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1135 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1142 unsigned long reg1
, reg2
, value
;
1144 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1145 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1146 value
= reg2
- reg1
;
1149 n
= (value
& 0x80000000);
1151 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1152 && (reg2
& 0x8000000) != (value
& 0x80000000));
1154 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1155 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1156 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1157 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1164 unsigned long reg1
, reg2
, value
;
1166 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1167 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1168 value
= reg2
- reg1
;
1171 n
= (value
& 0x80000000);
1173 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1174 && (reg2
& 0x8000000) != (value
& 0x80000000));
1176 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1177 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1178 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1179 State
.regs
[REG_A0
+ (insn
& 0x3)] = value
;
1186 unsigned long reg1
, imm
, value
;
1188 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)];
1189 imm
= ((insn
& 0xffff) << 16) | extension
;
1193 n
= (value
& 0x80000000);
1195 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1196 && (imm
& 0x8000000) != (value
& 0x80000000));
1198 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1199 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1200 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1201 State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)] = value
;
1208 unsigned long reg1
, imm
, value
;
1210 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)];
1211 imm
= ((insn
& 0xffff) << 16) | extension
;
1215 n
= (value
& 0x80000000);
1217 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1218 && (imm
& 0x8000000) != (value
& 0x80000000));
1220 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1221 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1222 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1223 State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)] = value
;
1230 unsigned long reg1
, reg2
, value
;
1232 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1233 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1234 value
= reg2
- reg1
- ((PSW
& PSW_C
) != 0);
1237 n
= (value
& 0x80000000);
1239 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1240 && (reg2
& 0x8000000) != (value
& 0x80000000));
1242 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1243 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1244 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1245 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1251 unsigned long long temp
;
1254 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1255 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1256 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1257 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1258 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1259 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1260 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1261 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1267 unsigned long long temp
;
1270 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1271 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1272 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1273 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1274 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1275 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1276 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1277 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1286 temp
= State
.regs
[REG_MDR
];
1288 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1289 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1290 temp
/= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1291 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1292 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1293 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1294 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1295 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1296 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1297 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1298 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1304 unsigned long long temp
;
1307 temp
= State
.regs
[REG_MDR
];
1309 temp
|= State
.regs
[REG_D0
+ (insn
& 0x3)];
1310 State
.regs
[REG_MDR
] = temp
% State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1311 temp
/= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1312 temp
= (State
.regs
[REG_D0
+ (insn
& 0x3)]
1313 * State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]);
1314 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
& 0xffffffff;
1315 State
.regs
[REG_MDR
] = temp
& 0xffffffff00000000LL
;
1316 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1317 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1318 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1319 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1325 State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)] += 1;
1331 State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)] += 1;
1337 State
.regs
[REG_A0
+ (insn
& 0x3)] += 4;
1344 unsigned long reg1
, imm
, value
;
1346 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 8)];
1347 imm
= SEXT8 (insn
& 0xff);
1351 n
= (value
& 0x80000000);
1353 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1354 && (imm
& 0x8000000) != (value
& 0x80000000));
1356 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1357 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1358 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1365 unsigned long reg1
, reg2
, value
;
1367 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1368 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1369 value
= reg2
- reg1
;
1372 n
= (value
& 0x80000000);
1374 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1375 && (reg2
& 0x8000000) != (value
& 0x80000000));
1377 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1378 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1379 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1386 unsigned long reg1
, reg2
, value
;
1388 reg1
= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1389 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1390 value
= reg2
- reg1
;
1393 n
= (value
& 0x80000000);
1395 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1396 && (reg2
& 0x8000000) != (value
& 0x80000000));
1398 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1399 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1400 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1407 unsigned long reg1
, reg2
, value
;
1409 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1410 reg2
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1411 value
= reg2
- reg1
;
1414 n
= (value
& 0x80000000);
1416 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1417 && (reg2
& 0x8000000) != (value
& 0x80000000));
1419 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1420 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1421 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1428 unsigned long reg1
, imm
, value
;
1430 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 8)];
1435 n
= (value
& 0x80000000);
1437 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1438 && (imm
& 0x8000000) != (value
& 0x80000000));
1440 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1441 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1442 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1449 unsigned long reg1
, reg2
, value
;
1451 reg1
= State
.regs
[REG_A0
+ ((insn
& 0xc) >> 2)];
1452 reg2
= State
.regs
[REG_A0
+ (insn
& 0x3)];
1453 value
= reg2
- reg1
;
1456 n
= (value
& 0x80000000);
1458 v
= ((reg2
& 0x8000000) != (reg1
& 0x80000000)
1459 && (reg2
& 0x8000000) != (value
& 0x80000000));
1461 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1462 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1463 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1470 unsigned long reg1
, imm
, value
;
1472 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)];
1473 imm
= SEXT16 (insn
& 0xffff);
1477 n
= (value
& 0x80000000);
1479 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1480 && (imm
& 0x8000000) != (value
& 0x80000000));
1482 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1483 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1484 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1491 unsigned long reg1
, imm
, value
;
1493 reg1
= State
.regs
[REG_D0
+ ((insn
& 0x300) >> 16)];
1494 imm
= ((insn
& 0xffff) << 16) | extension
;
1498 n
= (value
& 0x80000000);
1500 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1501 && (imm
& 0x8000000) != (value
& 0x80000000));
1503 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1504 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1505 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1512 unsigned long reg1
, imm
, value
;
1514 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)];
1515 imm
= insn
& 0xffff;
1519 n
= (value
& 0x80000000);
1521 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1522 && (imm
& 0x8000000) != (value
& 0x80000000));
1524 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1525 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1526 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1533 unsigned long reg1
, imm
, value
;
1535 reg1
= State
.regs
[REG_A0
+ ((insn
& 0x300) >> 16)];
1536 imm
= ((insn
& 0xffff) << 16) | extension
;
1540 n
= (value
& 0x80000000);
1542 v
= ((imm
& 0x8000000) != (reg1
& 0x80000000)
1543 && (imm
& 0x8000000) != (value
& 0x80000000));
1545 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1546 PSW
|= ((z
? PSW_Z
: 0) | ( n
? PSW_N
: 0)
1547 | (c
? PSW_C
: 0) | (v
? PSW_V
: 0));
1555 State
.regs
[REG_D0
+ (insn
& 0x3)] &= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1556 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1557 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1558 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1559 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1587 State
.regs
[REG_D0
+ (insn
& 0x3)] |= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1588 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1589 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1590 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1591 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1619 State
.regs
[REG_D0
+ (insn
& 0x3)] ^= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1620 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1621 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1622 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1623 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1641 State
.regs
[REG_D0
+ (insn
& 0x3)] = ~State
.regs
[REG_D0
+ (insn
& 0x3)];
1642 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1643 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1644 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1645 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1679 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
1680 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
1681 temp
|= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1682 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
1683 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1684 PSW
|= (z
? PSW_Z
: 0);
1703 temp
= load_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1);
1704 z
= (temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)]) == 0;
1705 temp
= ~temp
& State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1706 store_mem (State
.regs
[REG_A0
+ (insn
& 3)], 1, temp
);
1707 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1708 PSW
|= (z
? PSW_Z
: 0);
1727 temp
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1729 temp
>>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1730 State
.regs
[REG_D0
+ (insn
& 0x3)] = temp
;
1731 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1732 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1733 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
1734 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
1747 c
= State
.regs
[REG_D0
+ (insn
& 0x3)] & 1;
1748 State
.regs
[REG_D0
+ (insn
& 0x3)]
1749 >>= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1750 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1751 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1752 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
);
1753 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
1766 State
.regs
[REG_D0
+ (insn
& 0x3)]
1767 <<= State
.regs
[REG_D0
+ ((insn
& 0xc) >> 2)];
1768 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1769 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1770 PSW
&= ~(PSW_Z
| PSW_N
);
1771 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1784 State
.regs
[REG_D0
+ (insn
& 0x3)] <<= 2;
1785 z
= (State
.regs
[REG_D0
+ (insn
& 0x3)] == 0);
1786 n
= (State
.regs
[REG_D0
+ (insn
& 0x3)] & 0x8000000) != 0;
1787 PSW
&= ~(PSW_Z
| PSW_N
);
1788 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0));
1794 unsigned long value
;
1797 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1802 value
|= ((PSW
& PSW_C
) != 0) ? 0x80000000 : 0;
1803 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1805 n
= (value
& 0x8000000) != 0;
1806 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1807 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
1813 unsigned long value
;
1816 value
= State
.regs
[REG_D0
+ (insn
& 0x3)];
1817 if (value
& 0x80000000)
1821 value
|= ((PSW
& PSW_C
) != 0);
1822 State
.regs
[REG_D0
+ (insn
& 0x3)] = value
;
1824 n
= (value
& 0x8000000) != 0;
1825 PSW
&= ~(PSW_Z
| PSW_N
| PSW_C
| PSW_V
);
1826 PSW
|= ((z
? PSW_Z
: 0) | (n
? PSW_N
: 0) | (c
? PSW_C
: 0));
1832 /* The dispatching code will add 2 after we return, so
1833 we subtract two here to make things right. */
1835 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1841 /* The dispatching code will add 2 after we return, so
1842 we subtract two here to make things right. */
1844 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1850 /* The dispatching code will add 2 after we return, so
1851 we subtract two here to make things right. */
1853 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)))
1854 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1860 /* The dispatching code will add 2 after we return, so
1861 we subtract two here to make things right. */
1862 if (!(((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
1863 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1869 /* The dispatching code will add 2 after we return, so
1870 we subtract two here to make things right. */
1872 || (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0))
1873 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1879 /* The dispatching code will add 2 after we return, so
1880 we subtract two here to make things right. */
1881 if (((PSW
& PSW_N
) != 0) ^ (PSW
& PSW_V
) != 0)
1882 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1888 /* The dispatching code will add 2 after we return, so
1889 we subtract two here to make things right. */
1890 if (!(((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0))
1891 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1897 /* The dispatching code will add 2 after we return, so
1898 we subtract two here to make things right. */
1900 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1906 /* The dispatching code will add 2 after we return, so
1907 we subtract two here to make things right. */
1908 if (((PSW
& PSW_C
) != 0) || (PSW
& PSW_Z
) != 0)
1909 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1915 /* The dispatching code will add 2 after we return, so
1916 we subtract two here to make things right. */
1918 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
1924 /* The dispatching code will add 3 after we return, so
1925 we subtract two here to make things right. */
1927 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
1933 /* The dispatching code will add 3 after we return, so
1934 we subtract two here to make things right. */
1936 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
1942 /* The dispatching code will add 3 after we return, so
1943 we subtract two here to make things right. */
1945 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
1951 /* The dispatching code will add 3 after we return, so
1952 we subtract two here to make things right. */
1954 State
.pc
+= SEXT8 (insn
& 0xff) - 3;
1960 /* The dispatching code will add 2 after we return, so
1961 we subtract two here to make things right. */
1962 State
.pc
+= SEXT8 (insn
& 0xff) - 2;
2040 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2046 State
.pc
+= SEXT16 (insn
& 0xffff) - 3;
2052 State
.pc
+= (((insn
& 0xffffff) << 8) | extension
) - 5;
2055 /* call label:16,reg_list,imm8 */
2058 unsigned int next_pc
, sp
, adjust
;
2061 sp
= State
.regs
[REG_SP
];
2062 next_pc
= State
.pc
+ 2;
2063 State
.mem
[sp
] = next_pc
& 0xff;
2064 State
.mem
[sp
+1] = next_pc
& 0xff00;
2065 State
.mem
[sp
+2] = next_pc
& 0xff0000;
2066 State
.mem
[sp
+3] = next_pc
& 0xff000000;
2074 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2080 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2086 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2092 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2098 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2100 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2102 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2104 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2106 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2108 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2110 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2114 /* And make sure to update the stack pointer. */
2115 State
.regs
[REG_SP
] -= extension
;
2116 State
.regs
[REG_MDR
] = next_pc
;
2117 State
.pc
+= SEXT16 ((insn
& 0xffff00) >> 8) - 5;
2120 /* call label:32,reg_list,imm8*/
2123 unsigned int next_pc
, sp
, adjust
;
2126 sp
= State
.regs
[REG_SP
];
2127 next_pc
= State
.pc
+ 2;
2128 State
.mem
[sp
] = next_pc
& 0xff;
2129 State
.mem
[sp
+1] = next_pc
& 0xff00;
2130 State
.mem
[sp
+2] = next_pc
& 0xff0000;
2131 State
.mem
[sp
+3] = next_pc
& 0xff000000;
2133 mask
= (extension
& 0xff00) >> 8;
2139 State
.regs
[REG_D0
+ 2] = load_mem (sp
+ adjust
, 4);
2145 State
.regs
[REG_D0
+ 3] = load_mem (sp
+ adjust
, 4);
2151 State
.regs
[REG_A0
+ 2] = load_mem (sp
+ adjust
, 4);
2157 State
.regs
[REG_A0
+ 3] = load_mem (sp
+ adjust
, 4);
2163 State
.regs
[REG_D0
] = load_mem (sp
+ adjust
, 4);
2165 State
.regs
[REG_D0
+ 1] = load_mem (sp
+ adjust
, 4);
2167 State
.regs
[REG_A0
] = load_mem (sp
+ adjust
, 4);
2169 State
.regs
[REG_A0
+ 1] = load_mem (sp
+ adjust
, 4);
2171 State
.regs
[REG_MDR
] = load_mem (sp
+ adjust
, 4);
2173 State
.regs
[REG_LIR
] = load_mem (sp
+ adjust
, 4);
2175 State
.regs
[REG_LAR
] = load_mem (sp
+ adjust
, 4);
2179 /* And make sure to update the stack pointer. */
2180 State
.regs
[REG_SP
] -= (extension
& 0xff);
2181 State
.regs
[REG_MDR
] = next_pc
;
2182 State
.pc
+= (((insn
& 0xffffff) << 8) | ((extension
& 0xff0000) >> 16)) - 7;
2188 unsigned int next_pc
, sp
;
2190 sp
= State
.regs
[REG_SP
];
2191 next_pc
= State
.pc
+ 2;
2192 State
.mem
[sp
] = next_pc
& 0xff;
2193 State
.mem
[sp
+1] = next_pc
& 0xff00;
2194 State
.mem
[sp
+2] = next_pc
& 0xff0000;
2195 State
.mem
[sp
+3] = next_pc
& 0xff000000;
2196 State
.regs
[REG_MDR
] = next_pc
;
2197 State
.pc
= State
.regs
[REG_A0
+ (insn
& 0x3)] - 2;
2200 /* calls label:16 */
2203 unsigned int next_pc
, sp
;
2205 sp
= State
.regs
[REG_SP
];
2206 next_pc
= State
.pc
+ 4;
2207 State
.mem
[sp
] = next_pc
& 0xff;
2208 State
.mem
[sp
+1] = next_pc
& 0xff00;
2209 State
.mem
[sp
+2] = next_pc
& 0xff0000;
2210 State
.mem
[sp
+3] = next_pc
& 0xff000000;
2211 State
.regs
[REG_MDR
] = next_pc
;
2212 State
.pc
+= SEXT16 (insn
& 0xffff) - 4;
2215 /* calls label:32 */
2218 unsigned int next_pc
, sp
;
2220 sp
= State
.regs
[REG_SP
];
2221 next_pc
= State
.pc
+ 6;
2222 State
.mem
[sp
] = next_pc
& 0xff;
2223 State
.mem
[sp
+1] = next_pc
& 0xff00;
2224 State
.mem
[sp
+2] = next_pc
& 0xff0000;
2225 State
.mem
[sp
+3] = next_pc
& 0xff000000;
2226 State
.regs
[REG_MDR
] = next_pc
;
2227 State
.pc
+= (((insn
& 0xffff) << 16) | extension
) - 6;
2236 State
.regs
[REG_SP
] += insn
& 0xff;
2237 State
.pc
= State
.regs
[REG_MDR
] - 3;
2238 sp
= State
.regs
[REG_SP
];
2240 mask
= (insn
& 0xff00) >> 8;
2245 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2247 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2249 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2251 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2253 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2255 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2257 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2263 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2269 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2275 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2281 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2286 /* retf reg_list,imm8 */
2292 State
.regs
[REG_SP
] += insn
& 0xff;
2293 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2294 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));
2297 sp
= State
.regs
[REG_SP
];
2299 mask
= (insn
& 0xff00) >> 8;
2304 State
.regs
[REG_LAR
] = load_mem (sp
, 4);
2306 State
.regs
[REG_LIR
] = load_mem (sp
, 4);
2308 State
.regs
[REG_MDR
] = load_mem (sp
, 4);
2310 State
.regs
[REG_A0
+ 1] = load_mem (sp
, 4);
2312 State
.regs
[REG_A0
] = load_mem (sp
, 4);
2314 State
.regs
[REG_D0
+ 1] = load_mem (sp
, 4);
2316 State
.regs
[REG_D0
] = load_mem (sp
, 4);
2322 State
.regs
[REG_A0
+ 3] = load_mem (sp
, 4);
2328 State
.regs
[REG_A0
+ 2] = load_mem (sp
, 4);
2334 State
.regs
[REG_D0
+ 3] = load_mem (sp
, 4);
2340 State
.regs
[REG_D0
+ 2] = load_mem (sp
, 4);
2350 sp
= State
.regs
[REG_SP
];
2351 State
.pc
= (State
.mem
[sp
] | (State
.mem
[sp
+1] << 8)
2352 | (State
.mem
[sp
+2] << 16) | (State
.mem
[sp
+3] << 24));