1 /* OpenRISC simulator support code
2 Copyright (C) 2017-2021 Free Software Foundation, Inc.
4 This file is part of GDB, the GNU debugger.
6 This program is free software; you can redistribute it and/or modify
7 it under the terms of the GNU General Public License as published by
8 the Free Software Foundation; either version 3 of the License, or
9 (at your option) any later version.
11 This program is distributed in the hope that it will be useful,
12 but WITHOUT ANY WARRANTY; without even the implied warranty of
13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 GNU General Public License for more details.
16 You should have received a copy of the GNU General Public License
17 along with this program. If not, see <http://www.gnu.org/licenses/>. */
19 /* This must come before any other includes. */
22 #define WANT_CPU_OR1K32BF
34 or1k32bf_fetch_register (sim_cpu
*current_cpu
, int rn
, unsigned char *buf
,
38 SETTWI (buf
, GET_H_GPR (rn
));
43 SETTWI (buf
, GET_H_SYS_PPC ());
46 SETTWI (buf
, GET_H_PC ());
49 SETTWI (buf
, GET_H_SYS_SR ());
54 return sizeof (WI
); /* WI from arch.h */
58 or1k32bf_store_register (sim_cpu
*current_cpu
, int rn
, unsigned char *buf
,
62 SET_H_GPR (rn
, GETTWI (buf
));
67 SET_H_SYS_PPC (GETTWI (buf
));
70 SET_H_PC (GETTWI (buf
));
73 SET_H_SYS_SR (GETTWI (buf
));
78 return sizeof (WI
); /* WI from arch.h */
82 or1k32bf_model_or1200_u_exec (sim_cpu
*current_cpu
, const IDESC
*idesc
,
83 int unit_num
, int referenced
)
89 or1k32bf_model_or1200nd_u_exec (sim_cpu
*current_cpu
, const IDESC
*idesc
,
90 int unit_num
, int referenced
)
96 or1k32bf_model_insn_before (sim_cpu
*current_cpu
, int first_p
)
101 or1k32bf_model_insn_after (sim_cpu
*current_cpu
, int last_p
, int cycles
)
106 or1k32bf_h_spr_get_raw (sim_cpu
*current_cpu
, USI addr
)
108 SIM_DESC sd
= CPU_STATE (current_cpu
);
109 SIM_ASSERT (addr
< NUM_SPR
);
110 return current_cpu
->spr
[addr
];
114 or1k32bf_h_spr_set_raw (sim_cpu
*current_cpu
, USI addr
, USI val
)
116 SIM_DESC sd
= CPU_STATE (current_cpu
);
117 SIM_ASSERT (addr
< NUM_SPR
);
118 current_cpu
->spr
[addr
] = val
;
122 or1k32bf_h_spr_field_get_raw (sim_cpu
*current_cpu
, USI addr
, int msb
, int lsb
)
124 SIM_DESC sd
= CPU_STATE (current_cpu
);
125 SIM_ASSERT (addr
< NUM_SPR
);
126 return LSEXTRACTED (current_cpu
->spr
[addr
], msb
, lsb
);
130 or1k32bf_h_spr_field_set_raw (sim_cpu
*current_cpu
, USI addr
, int msb
, int lsb
,
133 current_cpu
->spr
[addr
] &= ~LSMASK32 (msb
, lsb
);
134 current_cpu
->spr
[addr
] |= LSINSERTED (val
, msb
, lsb
);
137 /* Initialize a sim cpu object. */
139 or1k_cpu_init (SIM_DESC sd
, sim_cpu
*current_cpu
, const USI or1k_vr
,
140 const USI or1k_upr
, const USI or1k_cpucfgr
)
142 /* Set the configuration registers passed from the user. */
143 SET_H_SYS_VR (or1k_vr
);
144 SET_H_SYS_UPR (or1k_upr
);
145 SET_H_SYS_CPUCFGR (or1k_cpucfgr
);
147 #define CHECK_SPR_FIELD(GROUP, INDEX, FIELD, test) \
150 USI field = GET_H_##SYS##_##INDEX##_##FIELD (); \
153 (sd, "WARNING: unsupported %s field in %s register: 0x%x\n", \
154 #FIELD, #INDEX, field); \
157 /* Set flags indicating if we are in a delay slot or not. */
158 current_cpu
->next_delay_slot
= 0;
159 current_cpu
->delay_slot
= 0;
161 /* Verify any user passed fields and warn on configurations we don't
163 CHECK_SPR_FIELD (SYS
, UPR
, UP
, field
== 1);
164 CHECK_SPR_FIELD (SYS
, UPR
, DCP
, field
== 0);
165 CHECK_SPR_FIELD (SYS
, UPR
, ICP
, field
== 0);
166 CHECK_SPR_FIELD (SYS
, UPR
, DMP
, field
== 0);
167 CHECK_SPR_FIELD (SYS
, UPR
, MP
, field
== 0);
168 CHECK_SPR_FIELD (SYS
, UPR
, IMP
, field
== 0);
169 CHECK_SPR_FIELD (SYS
, UPR
, DUP
, field
== 0);
170 CHECK_SPR_FIELD (SYS
, UPR
, PCUP
, field
== 0);
171 CHECK_SPR_FIELD (SYS
, UPR
, PICP
, field
== 0);
172 CHECK_SPR_FIELD (SYS
, UPR
, PMP
, field
== 0);
173 CHECK_SPR_FIELD (SYS
, UPR
, TTP
, field
== 0);
174 CHECK_SPR_FIELD (SYS
, UPR
, CUP
, field
== 0);
176 CHECK_SPR_FIELD (SYS
, CPUCFGR
, NSGR
, field
== 0);
177 CHECK_SPR_FIELD (SYS
, CPUCFGR
, CGF
, field
== 0);
178 CHECK_SPR_FIELD (SYS
, CPUCFGR
, OB32S
, field
== 1);
179 CHECK_SPR_FIELD (SYS
, CPUCFGR
, OF32S
, field
== 1);
180 CHECK_SPR_FIELD (SYS
, CPUCFGR
, OB64S
, field
== 0);
181 CHECK_SPR_FIELD (SYS
, CPUCFGR
, OF64S
, field
== 0);
182 CHECK_SPR_FIELD (SYS
, CPUCFGR
, OV64S
, field
== 0);
184 #undef CHECK_SPR_FIELD
186 /* Configure the fpu operations and mark fpu available. */
187 cgen_init_accurate_fpu (current_cpu
, CGEN_CPU_FPU (current_cpu
),
189 SET_H_SYS_CPUCFGR_OF32S (1);
191 /* Set the UPR[UP] flag, even if the user tried to unset it, as we always
192 support the Unit Present Register. */
193 SET_H_SYS_UPR_UP (1);
195 /* Set the supervisor register to indicate we are in supervisor mode and
196 set the Fixed-One bit which must always be set. */
197 SET_H_SYS_SR (SPR_FIELD_MASK_SYS_SR_SM
| SPR_FIELD_MASK_SYS_SR_FO
);
199 /* Clear the floating point control status register. */
204 or1k32bf_insn_before (sim_cpu
*current_cpu
, SEM_PC vpc
, const IDESC
*idesc
)
206 SIM_DESC sd
= CPU_STATE (current_cpu
);
208 current_cpu
->delay_slot
= current_cpu
->next_delay_slot
;
209 current_cpu
->next_delay_slot
= 0;
211 if (current_cpu
->delay_slot
&&
212 CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc
)->idata
)) &
213 CGEN_ATTR_MASK (CGEN_INSN_NOT_IN_DELAY_SLOT
))
217 pc
= vpc
->argbuf
.addr
;
221 sim_io_error (sd
, "invalid instruction in a delay slot at PC 0x%08x",
228 or1k32bf_insn_after (sim_cpu
*current_cpu
, SEM_PC vpc
, const IDESC
*idesc
)
230 SIM_DESC sd
= CPU_STATE (current_cpu
);
234 ppc
= vpc
->argbuf
.addr
;
241 if (!GET_H_SYS_CPUCFGR_ND () &&
242 CGEN_ATTR_BOOLS (CGEN_INSN_ATTRS ((idesc
)->idata
)) &
243 CGEN_ATTR_MASK (CGEN_INSN_DELAYED_CTI
))
245 SIM_ASSERT (!current_cpu
->delay_slot
);
246 current_cpu
->next_delay_slot
= 1;
251 or1k32bf_nop (sim_cpu
*current_cpu
, USI uimm16
)
253 SIM_DESC sd
= CPU_STATE (current_cpu
);
262 sim_io_printf (CPU_STATE (current_cpu
), "exit(%d)\n", GET_H_GPR (3));
264 case NOP_EXIT_SILENT
:
265 sim_engine_halt (sd
, current_cpu
, NULL
, CPU_PC_GET (current_cpu
),
266 sim_exited
, GET_H_GPR (3));
270 sim_io_printf (CPU_STATE (current_cpu
), "report(0x%08x);\n",
275 sim_io_printf (CPU_STATE (current_cpu
), "%c",
276 (char) (GET_H_GPR (3) & 0xff));
280 sim_io_eprintf (sd
, "WARNING: l.nop with unsupported code 0x%08x\n",
287 /* Build an address value used for load and store instructions. For example,
288 the instruction 'l.lws rD, I(rA)' will require to load data from the 4 byte
289 address represented by rA + I. Here the argument base is rA, offset is I
290 and the size is the read size in bytes. Note, OpenRISC requires that word
291 and half-word access be word and half-word aligned respectively, the check
292 for alignment is not needed here. */
295 or1k32bf_make_load_store_addr (sim_cpu
*current_cpu
, USI base
, SI offset
,
298 SIM_DESC sd
= CPU_STATE (current_cpu
);
300 USI addr
= base
+ offset
;
302 /* If little endian load/store is enabled we adjust the byte and half-word
303 addresses to the little endian equivalent. */
304 if (GET_H_SYS_SR_LEE ())
309 case 4: /* We are retrieving the entire word no adjustment. */
312 case 2: /* Perform half-word adjustment 0 -> 2, 2 -> 0. */
316 case 1: /* Perform byte adjustment, 0 -> 3, 2 -> 3, etc. */
329 /* The find first 1 instruction returns the location of the first set bit
330 in the argument register. */
333 or1k32bf_ff1 (sim_cpu
*current_cpu
, USI val
)
337 for (bit
= 1, ret
= 1; bit
; bit
<<= 1, ret
++)
345 /* The find last 1 instruction returns the location of the last set bit in
346 the argument register. */
349 or1k32bf_fl1 (sim_cpu
*current_cpu
, USI val
)
353 for (bit
= 1 << 31, ret
= 32; bit
; bit
>>= 1, ret
--)