1 /* This file is part of the program psim.
3 Copyright (C) 1994-1995, Andrew Cagney <cagney@highland.com.au>
5 This program is free software; you can redistribute it and/or modify
6 it under the terms of the GNU General Public License as published by
7 the Free Software Foundation; either version 2 of the License, or
8 (at your option) any later version.
10 This program is distributed in the hope that it will be useful,
11 but WITHOUT ANY WARRANTY; without even the implied warranty of
12 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 GNU General Public License for more details.
15 You should have received a copy of the GNU General Public License
16 along with this program; if not, write to the Free Software
17 Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
26 /* endianness of the host/target:
28 If the build process is aware (at compile time) of the endianness
29 of the host/target it is able to eliminate slower generic endian
32 Possible values are 0 (unknown), LITTLE_ENDIAN, BIG_ENDIAN */
34 #ifndef WITH_HOST_BYTE_ORDER
35 #define WITH_HOST_BYTE_ORDER 0 /*unknown*/
38 #ifndef WITH_TARGET_BYTE_ORDER
39 #define WITH_TARGET_BYTE_ORDER 0 /*unknown*/
42 extern int current_host_byte_order
;
43 #define CURRENT_HOST_BYTE_ORDER (WITH_HOST_BYTE_ORDER \
44 ? WITH_HOST_BYTE_ORDER \
45 : current_host_byte_order)
46 extern int current_target_byte_order
;
47 #define CURRENT_TARGET_BYTE_ORDER (WITH_TARGET_BYTE_ORDER \
48 ? WITH_TARGET_BYTE_ORDER \
49 : current_target_byte_order)
52 /* Intel host BSWAP support:
54 Whether to use bswap on the 486 and pentiums rather than the 386
55 sequence that uses xchgb/rorl/xchgb */
63 Sets a limit on the number of processors that can be simulated. If
64 WITH_SMP is set to zero (0), the simulator is restricted to
65 suporting only on processor (and as a consequence leaves the SMP
66 code out of the build process).
68 The actual number of processors is taken from the device
69 /options/smp@<nr-cpu> */
75 #define MAX_NR_PROCESSORS WITH_SMP
77 #define MAX_NR_PROCESSORS 1
81 /* Word size of host/target:
83 Set these according to your host and target requirements. At this
84 point in time, I've only compiled (not run) for a 64bit and never
85 built for a 64bit host. This will always remain a compile time
88 #ifndef WITH_TARGET_WORD_BITSIZE
89 #define WITH_TARGET_WORD_BITSIZE 32 /* compiled only */
92 #ifndef WITH_HOST_WORD_BITSIZE
93 #define WITH_HOST_WORD_BITSIZE 32 /* 64bit ready? */
97 /* Program environment:
99 Three environments are available - UEA (user), VEA (virtual) and
100 OEA (perating). The former two are environment that users would
101 expect to see (VEA includes things like coherency and the time
102 base) while OEA is what an operating system expects to see. By
103 setting these to specific values, the build process is able to
104 eliminate non relevent environment code
106 CURRENT_ENVIRONMENT specifies which of vea or oea is required for
107 the current runtime. */
109 #define USER_ENVIRONMENT 1
110 #define VIRTUAL_ENVIRONMENT 2
111 #define OPERATING_ENVIRONMENT 3
113 #ifndef WITH_ENVIRONMENT
114 #define WITH_ENVIRONMENT 0
117 extern int current_environment
;
118 #define CURRENT_ENVIRONMENT (WITH_ENVIRONMENT \
120 : current_environment)
123 /* Optional VEA/OEA code:
125 The below, required for the OEA model may also be included in the
126 VEA model however, as far as I can tell only make things
130 /* Events. Devices modeling real H/W need to be able to efficiently
131 schedule things to do at known times in the future. The event
132 queue implements this. Unfortunatly this adds the need to check
133 for any events once each full instruction cycle. */
135 #define WITH_EVENTS (WITH_ENVIRONMENT != USER_ENVIRONMENT)
140 The PowerPC architecture includes the addition of both a time base
141 register and a decrement timer. Like events adds to the overhead
142 of of some instruction cycles. */
144 #ifndef WITH_TIME_BASE
145 #define WITH_TIME_BASE (WITH_ENVIRONMENT != USER_ENVIRONMENT)
149 /* Callback/Default Memory.
151 Core includes a builtin memory type (raw_memory) that is
152 implemented using an array. raw_memory does not require any
153 additional functions etc.
155 Callback memory is where the core calls a core device for the data
158 Default memory is an extenstion of this where for addresses that do
159 not map into either a callback or core memory range a default map
162 The OEA model uses callback memory for devices and default memory
165 The VEA model uses callback memory to capture `page faults'.
167 While it may be possible to eliminate callback/default memory (and
168 hence also eliminate an additional test per memory fetch) it
169 probably is not worth the effort.
171 BTW, while raw_memory could have been implemented as a callback,
172 profiling has shown that there is a biger win (at least for the
173 x86) in eliminating a function call for the most common
174 (raw_memory) case. */
176 #define WITH_CALLBACK_MEMORY 1
181 The PowerPC may or may not handle miss aligned transfers. An
182 implementation normally handles miss aligned transfers in big
183 endian mode but generates an exception in little endian mode.
185 This model. Instead allows both little and big endian modes to
186 either take exceptions or handle miss aligned transfers.
188 If 0 is specified then for big-endian mode miss alligned accesses
189 are permitted (NONSTRICT_ALIGNMENT) while in little-endian mode the
190 processor will fault on them (STRICT_ALIGNMENT). */
192 #define NONSTRICT_ALIGNMENT 1
193 #define STRICT_ALIGNMENT 2
195 #ifndef WITH_ALIGNMENT
196 #define WITH_ALIGNMENT 0
199 extern int current_alignment
;
200 #define CURRENT_ALIGNMENT (WITH_ALIGNMENT \
205 /* Floating point suport:
207 Still under development. */
209 #define SOFT_FLOATING_POINT 1
210 #define HARD_FLOATING_POINT 2
212 #ifndef WITH_FLOATING_POINT
213 #define WITH_FLOATING_POINT HARD_FLOATING_POINT
215 extern int current_floating_point
;
216 #define CURRENT_FLOATING_POINT (WITH_FLOATING_POINT \
217 ? WITH_FLOATING_POINT \
218 : current_floating_point)
223 Control the inclusion of debugging code. */
225 /* Include the tracing code. Disabling this eliminates all tracing
232 /* include code that checks assertions scattered through out the
236 #define WITH_ASSERT 1
239 /* include monitoring code */
241 #define MONITOR_INSTRUCTION_ISSUE 1
242 #define MONITOR_LOAD_STORE_UNIT 2
244 #define WITH_MON (MONITOR_LOAD_STORE_UNIT \
245 | MONITOR_INSTRUCTION_ISSUE)
249 /* Include code that simulates function units to model particular
250 machines more closely and provide more detailed information about
251 optimization potential. */
253 #ifndef WITH_FUNCTION_UNIT
254 #define WITH_FUNCTION_UNIT 1
257 /* Which specific processor to model */
258 typedef enum _ppc_model
{
271 #ifndef WITH_DEFAULT_PPC_MODEL
272 #define WITH_DEFAULT_PPC_MODEL PPC_MODEL_603e
275 extern ppc_model current_ppc_model
;
277 #ifndef WITH_PPC_MODEL
278 #define WITH_PPC_MODEL 0
281 #define CURRENT_PPC_MODEL (WITH_PPC_MODEL \
285 /* INLINE CODE SELECTION:
287 GCC -O3 attempts to inline any function or procedure in scope. The
288 options below facilitate fine grained control over what is and what
289 isn't made inline. For instance it can control things down to a
290 specific modules static routines. This control is implemented in
291 two parts. Doing this allows the compiler to both eliminate the
292 overhead of function calls and (as a consequence) also eliminate
295 Experementing with CISC (x86) I've found that I can achieve an
296 order of magintude speed improvement (x3-x5). In the case of RISC
297 (sparc) while the performance gain isn't as great it is still
300 Part One - Static functions: It is possible to control how static
301 functions within each module are to be compiled. On a per module
302 or global basis, it is possible to specify that a modules static
303 functions should be compiled inline. This is controled by the the
304 macro's STATIC_INLINE and INLINE_STATIC_<module>.
306 Part Two - External functions: Again it is possible to allow the
307 inlining of calls to external functions. This is far more
308 complicated and much heaver on the compiler. In this case, it is
309 controled by the <module>_INLINE macro's. Where each can have a
312 0 Make a normal external call to functions in the module.
314 1 Include the module but to not inline functions within it.
315 This allows functions within the module to inline functions
316 from other modules that have been included.
318 2 Both include the module and inline functions contained within
321 Finally, this is not for the faint harted. I've seen GCC get up to
322 200mb trying to compile what this can create */
324 /* Your compilers inline reserved word */
327 #if defined(__GNUC__) && defined(__OPTIMIZE__)
328 #define INLINE __inline__
330 #define INLINE /*inline*/
334 /* Default prefix for static functions */
336 #ifndef STATIC_INLINE
337 #define STATIC_INLINE static INLINE
340 /* Default macro to simplify control several of key the inlines */
342 #ifndef DEFAULT_INLINE
343 #define DEFAULT_INLINE 0
346 /* Code that converts between hosts and target byte order. Used on
347 every memory access (instruction and data). (See sim-endian.h for
348 additional byte swapping configuration information) */
350 #ifndef SIM_ENDIAN_INLINE
351 #define SIM_ENDIAN_INLINE DEFAULT_INLINE
354 /* Low level bit manipulation routines used to work around a compiler
358 #define BITS_INLINE DEFAULT_INLINE
361 /* Code that gives access to various CPU internals such as registers.
362 Used every time an instruction is executed */
365 #define CPU_INLINE DEFAULT_INLINE
368 /* Code that translates between an effective and real address. Used
369 by every load or store. */
372 #define VM_INLINE DEFAULT_INLINE
375 /* Code that loads/stores data to/from the memory data structure.
376 Used by every load or store */
379 #define CORE_INLINE DEFAULT_INLINE
382 /* Code to check for and process any events scheduled in the future.
383 Called once per instruction cycle */
385 #ifndef EVENTS_INLINE
386 #define EVENTS_INLINE DEFAULT_INLINE
389 /* Code monotoring the processors performance. It counts events on
390 every instruction cycle */
393 #define MON_INLINE DEFAULT_INLINE
396 /* Code called on the rare occasions that an interrupt occures. */
398 #ifndef INTERRUPTS_INLINE
399 #define INTERRUPTS_INLINE 0
402 /* Code called on the rare occasion that either gdb or the device tree
403 need to manipulate a register within a processor */
405 #ifndef REGISTERS_INLINE
406 #define REGISTERS_INLINE 0
409 /* Code called on the rare occasion that a processor is manipulating
410 real hardware instead of RAM.
412 Also, most of the functions in devices.c are always called through
415 There seems to be some problem with making either device_tree or
416 devices inline. It reports the message: device_tree_find_node()
419 #ifndef DEVICE_TREE_INLINE
420 #define DEVICE_TREE_INLINE 0
423 #ifndef DEVICES_INLINE
424 #define DEVICES_INLINE 0
427 /* Code called whenever information on a Special Purpose Register is
428 required. Called by the mflr/mtlr pseudo instructions */
431 #define SPREG_INLINE DEFAULT_INLINE
434 /* Functions modeling the semantics of each instruction. Two cases to
435 consider, firstly of idecode is implemented with a switch then this
436 allows the idecode function to inline each semantic function
437 (avoiding a call). The second case is when idecode is using a
438 table, even then while the semantic functions can't be inlined,
439 setting it to one still enables each semantic function to inline
440 anything they call (if that code is marked for being inlined).
442 WARNING: you need lots (like 200mb of swap) of swap. Setting this
443 to 1 is useful when using a table as it enables the sematic code to
444 inline all of their called functions */
446 #ifndef SEMANTICS_INLINE
447 #define SEMANTICS_INLINE (DEFAULT_INLINE ? 1 : 0)
450 /* Code to decode an instruction. Normally called on every instruction
453 #ifndef IDECODE_INLINE
454 #define IDECODE_INLINE DEFAULT_INLINE
457 /* Code to simule functional units of real machines */
459 #ifndef FUNCTION_UNIT_INLINE
460 #define FUNCTION_UNIT_INLINE DEFAULT_INLINE
463 #endif /* _CONFIG_H */