Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
[gem5.git] / sim / pseudo_inst.cc
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <errno.h>
30 #include <fcntl.h>
31 #include <unistd.h>
32 #include <cstdio>
33
34 #include <string>
35
36 #include "sim/pseudo_inst.hh"
37 #include "targetarch/vtophys.hh"
38 #include "cpu/base.hh"
39 #include "cpu/sampler/sampler.hh"
40 #include "cpu/exec_context.hh"
41 #include "kern/kernel_stats.hh"
42 #include "sim/param.hh"
43 #include "sim/serialize.hh"
44 #include "sim/sim_exit.hh"
45 #include "sim/stat_control.hh"
46 #include "sim/stats.hh"
47 #include "sim/system.hh"
48 #include "sim/debug.hh"
49 #include "sim/vptr.hh"
50
51 using namespace std;
52
53 extern Sampler *SampCPU;
54
55 using namespace Stats;
56 using namespace TheISA;
57
58 namespace AlphaPseudo
59 {
60 bool doStatisticsInsts;
61 bool doCheckpointInsts;
62 bool doQuiesce;
63
64 void
65 arm(ExecContext *xc)
66 {
67 xc->kernelStats->arm();
68 }
69
70 void
71 quiesce(ExecContext *xc)
72 {
73 if (!doQuiesce)
74 return;
75
76 xc->suspend();
77 xc->kernelStats->quiesce();
78 }
79
80 void
81 ivlb(ExecContext *xc)
82 {
83 xc->kernelStats->ivlb();
84 }
85
86 void
87 ivle(ExecContext *xc)
88 {
89 }
90
91 void
92 m5exit_old(ExecContext *xc)
93 {
94 SimExit(curTick, "m5_exit_old instruction encountered");
95 }
96
97 void
98 m5exit(ExecContext *xc, Tick delay)
99 {
100 Tick when = curTick + delay * Clock::Int::ns;
101 SimExit(when, "m5_exit instruction encountered");
102 }
103
104 void
105 resetstats(ExecContext *xc, Tick delay, Tick period)
106 {
107 if (!doStatisticsInsts)
108 return;
109
110
111 Tick when = curTick + delay * Clock::Int::ns;
112 Tick repeat = period * Clock::Int::ns;
113
114 using namespace Stats;
115 SetupEvent(Reset, when, repeat);
116 }
117
118 void
119 dumpstats(ExecContext *xc, Tick delay, Tick period)
120 {
121 if (!doStatisticsInsts)
122 return;
123
124
125 Tick when = curTick + delay * Clock::Int::ns;
126 Tick repeat = period * Clock::Int::ns;
127
128 using namespace Stats;
129 SetupEvent(Dump, when, repeat);
130 }
131
132 void
133 addsymbol(ExecContext *xc, Addr addr, Addr symbolAddr)
134 {
135 char symb[100];
136 CopyString(xc, symb, symbolAddr, 100);
137 std::string symbol(symb);
138
139 DPRINTF(Loader, "Loaded symbol: %s @ %#llx\n", symbol, addr);
140
141 xc->system->kernelSymtab->insert(addr,symbol);
142 }
143
144 void
145 dumpresetstats(ExecContext *xc, Tick delay, Tick period)
146 {
147 if (!doStatisticsInsts)
148 return;
149
150
151 Tick when = curTick + delay * Clock::Int::ns;
152 Tick repeat = period * Clock::Int::ns;
153
154 using namespace Stats;
155 SetupEvent(Dump|Reset, when, repeat);
156 }
157
158 void
159 m5checkpoint(ExecContext *xc, Tick delay, Tick period)
160 {
161 if (!doCheckpointInsts)
162 return;
163
164
165 Tick when = curTick + delay * Clock::Int::ns;
166 Tick repeat = period * Clock::Int::ns;
167
168 Checkpoint::setup(when, repeat);
169 }
170
171 uint64_t
172 readfile(ExecContext *xc, Addr vaddr, uint64_t len, uint64_t offset)
173 {
174 const string &file = xc->cpu->system->params->readfile;
175 if (file.empty()) {
176 return ULL(0);
177 }
178
179 uint64_t result = 0;
180
181 int fd = ::open(file.c_str(), O_RDONLY, 0);
182 if (fd < 0)
183 panic("could not open file %s\n", file);
184
185 if (::lseek(fd, offset, SEEK_SET) < 0)
186 panic("could not seek: %s", strerror(errno));
187
188 char *buf = new char[len];
189 char *p = buf;
190 while (len > 0) {
191 int bytes = ::read(fd, p, len);
192 if (bytes <= 0)
193 break;
194
195 p += bytes;
196 result += bytes;
197 len -= bytes;
198 }
199
200 close(fd);
201 CopyIn(xc, vaddr, buf, result);
202 delete [] buf;
203 return result;
204 }
205
206 class Context : public ParamContext
207 {
208 public:
209 Context(const string &section) : ParamContext(section) {}
210 void checkParams();
211 };
212
213 Context context("pseudo_inst");
214
215 Param<bool> __quiesce(&context, "quiesce",
216 "enable quiesce instructions",
217 true);
218 Param<bool> __statistics(&context, "statistics",
219 "enable statistics pseudo instructions",
220 true);
221 Param<bool> __checkpoint(&context, "checkpoint",
222 "enable checkpoint pseudo instructions",
223 true);
224
225 void
226 Context::checkParams()
227 {
228 doQuiesce = __quiesce;
229 doStatisticsInsts = __statistics;
230 doCheckpointInsts = __checkpoint;
231 }
232
233 void debugbreak(ExecContext *xc)
234 {
235 debug_break();
236 }
237
238 void switchcpu(ExecContext *xc)
239 {
240 if (SampCPU)
241 SampCPU->switchCPUs();
242 }
243 }