3 Copyright (C) 2005-2021 Free Software Foundation, Inc.
4 Contributed by Mike Frysinger.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
21 /* This file contains the main simulator decoding logic. i.e. everything that
22 is architecture specific. */
24 /* This must come before any other includes. */
31 #include "sim-syscall.h"
33 #include "opcode/riscv.h"
35 #include "gdb/sim-riscv.h"
37 #include "targ-vals.h"
39 #define TRACE_REG(cpu, reg) \
40 TRACE_REGISTER (cpu, "wrote %s = %#" PRIxTW, riscv_gpr_names_abi[reg], \
43 static const struct riscv_opcode
*riscv_hash
[OP_MASK_OP
+ 1];
44 #define OP_HASH_IDX(i) ((i) & (riscv_insn_length (i) == 2 ? 0x3 : 0x7f))
46 #define RISCV_ASSERT_RV32(cpu, fmt, args...) \
48 if (RISCV_XLEN (cpu) != 32) \
50 SIM_DESC sd = CPU_STATE (cpu); \
51 TRACE_INSN (cpu, "RV32I-only " fmt, ## args); \
52 sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); \
56 #define RISCV_ASSERT_RV64(cpu, fmt, args...) \
58 if (RISCV_XLEN (cpu) != 64) \
60 SIM_DESC sd = CPU_STATE (cpu); \
61 TRACE_INSN (cpu, "RV64I-only " fmt, ## args); \
62 sim_engine_halt (sd, cpu, NULL, cpu->pc, sim_signalled, SIM_SIGILL); \
67 store_rd (SIM_CPU
*cpu
, int rd
, unsigned_word val
)
76 static INLINE unsigned_word
77 fetch_csr (SIM_CPU
*cpu
, const char *name
, int csr
, unsigned_word
*reg
)
79 /* Handle pseudo registers. */
82 /* Allow certain registers only in respective modes. */
86 RISCV_ASSERT_RV32 (cpu
, "CSR: %s", name
);
94 store_csr (SIM_CPU
*cpu
, const char *name
, int csr
, unsigned_word
*reg
,
99 /* These are pseudo registers that modify sub-fields of fcsr. */
103 cpu
->csr
.fcsr
= (cpu
->csr
.fcsr
& ~0xe0) | (val
<< 5);
108 cpu
->csr
.fcsr
= (cpu
->csr
.fcsr
& ~0x1f) | val
;
110 /* Keep the sub-fields in sync. */
113 cpu
->csr
.frm
= (val
>> 5) & 0x7;
114 cpu
->csr
.fflags
= val
& 0x1f;
117 /* Allow certain registers only in respective modes. */
121 RISCV_ASSERT_RV32 (cpu
, "CSR: %s", name
);
123 /* All the rest are immutable. */
129 TRACE_REGISTER (cpu
, "wrote CSR %s = %#" PRIxTW
, name
, val
);
132 static inline unsigned_word
133 ashiftrt (unsigned_word val
, unsigned_word shift
)
135 unsigned32 sign
= (val
& 0x80000000) ? ~(0xfffffffful
>> shift
) : 0;
136 return (val
>> shift
) | sign
;
139 static inline unsigned_word
140 ashiftrt64 (unsigned_word val
, unsigned_word shift
)
143 (val
& 0x8000000000000000ull
) ? ~(0xffffffffffffffffull
>> shift
) : 0;
144 return (val
>> shift
) | sign
;
148 execute_i (SIM_CPU
*cpu
, unsigned_word iw
, const struct riscv_opcode
*op
)
150 SIM_DESC sd
= CPU_STATE (cpu
);
151 int rd
= (iw
>> OP_SH_RD
) & OP_MASK_RD
;
152 int rs1
= (iw
>> OP_SH_RS1
) & OP_MASK_RS1
;
153 int rs2
= (iw
>> OP_SH_RS2
) & OP_MASK_RS2
;
154 const char *rd_name
= riscv_gpr_names_abi
[rd
];
155 const char *rs1_name
= riscv_gpr_names_abi
[rs1
];
156 const char *rs2_name
= riscv_gpr_names_abi
[rs2
];
157 unsigned int csr
= (iw
>> OP_SH_CSR
) & OP_MASK_CSR
;
158 unsigned_word i_imm
= EXTRACT_ITYPE_IMM (iw
);
159 unsigned_word u_imm
= EXTRACT_UTYPE_IMM ((unsigned64
) iw
);
160 unsigned_word s_imm
= EXTRACT_STYPE_IMM (iw
);
161 unsigned_word sb_imm
= EXTRACT_BTYPE_IMM (iw
);
162 unsigned_word shamt_imm
= ((iw
>> OP_SH_SHAMT
) & OP_MASK_SHAMT
);
164 sim_cia pc
= cpu
->pc
+ 4;
168 "rs1:%-2i:%-4s %0*" PRIxTW
" "
169 "rs2:%-2i:%-4s %0*" PRIxTW
" "
170 "match:%#x mask:%#x",
172 rs1
, rs1_name
, (int) sizeof (unsigned_word
) * 2, cpu
->regs
[rs1
],
173 rs2
, rs2_name
, (int) sizeof (unsigned_word
) * 2, cpu
->regs
[rs2
],
174 (unsigned) op
->match
, (unsigned) op
->mask
);
179 TRACE_INSN (cpu
, "add %s, %s, %s; // %s = %s + %s",
180 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
181 store_rd (cpu
, rd
, cpu
->regs
[rs1
] + cpu
->regs
[rs2
]);
184 TRACE_INSN (cpu
, "addw %s, %s, %s; // %s = %s + %s",
185 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
186 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
187 store_rd (cpu
, rd
, EXTEND32 (cpu
->regs
[rs1
] + cpu
->regs
[rs2
]));
190 TRACE_INSN (cpu
, "addi %s, %s, %#" PRIxTW
"; // %s = %s + %#" PRIxTW
,
191 rd_name
, rs1_name
, i_imm
, rd_name
, rs1_name
, i_imm
);
192 store_rd (cpu
, rd
, cpu
->regs
[rs1
] + i_imm
);
195 TRACE_INSN (cpu
, "addiw %s, %s, %#" PRIxTW
"; // %s = %s + %#" PRIxTW
,
196 rd_name
, rs1_name
, i_imm
, rd_name
, rs1_name
, i_imm
);
197 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
198 store_rd (cpu
, rd
, EXTEND32 (cpu
->regs
[rs1
] + i_imm
));
201 TRACE_INSN (cpu
, "and %s, %s, %s; // %s = %s & %s",
202 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
203 store_rd (cpu
, rd
, cpu
->regs
[rs1
] & cpu
->regs
[rs2
]);
206 TRACE_INSN (cpu
, "andi %s, %s, %" PRIiTW
"; // %s = %s & %#" PRIxTW
,
207 rd_name
, rs1_name
, i_imm
, rd_name
, rs1_name
, i_imm
);
208 store_rd (cpu
, rd
, cpu
->regs
[rs1
] & i_imm
);
211 TRACE_INSN (cpu
, "or %s, %s, %s; // %s = %s | %s",
212 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
213 store_rd (cpu
, rd
, cpu
->regs
[rs1
] | cpu
->regs
[rs2
]);
216 TRACE_INSN (cpu
, "ori %s, %s, %" PRIiTW
"; // %s = %s | %#" PRIxTW
,
217 rd_name
, rs1_name
, i_imm
, rd_name
, rs1_name
, i_imm
);
218 store_rd (cpu
, rd
, cpu
->regs
[rs1
] | i_imm
);
221 TRACE_INSN (cpu
, "xor %s, %s, %s; // %s = %s ^ %s",
222 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
223 store_rd (cpu
, rd
, cpu
->regs
[rs1
] ^ cpu
->regs
[rs2
]);
226 TRACE_INSN (cpu
, "xori %s, %s, %" PRIiTW
"; // %s = %s ^ %#" PRIxTW
,
227 rd_name
, rs1_name
, i_imm
, rd_name
, rs1_name
, i_imm
);
228 store_rd (cpu
, rd
, cpu
->regs
[rs1
] ^ i_imm
);
231 TRACE_INSN (cpu
, "sub %s, %s, %s; // %s = %s - %s",
232 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
233 store_rd (cpu
, rd
, cpu
->regs
[rs1
] - cpu
->regs
[rs2
]);
236 TRACE_INSN (cpu
, "subw %s, %s, %s; // %s = %s - %s",
237 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
238 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
239 store_rd (cpu
, rd
, EXTEND32 (cpu
->regs
[rs1
] - cpu
->regs
[rs2
]));
242 TRACE_INSN (cpu
, "lui %s, %#" PRIxTW
";", rd_name
, u_imm
);
243 store_rd (cpu
, rd
, u_imm
);
246 TRACE_INSN (cpu
, "sll %s, %s, %s; // %s = %s << %s",
247 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
248 u_imm
= RISCV_XLEN (cpu
) == 32 ? 0x1f : 0x3f;
249 store_rd (cpu
, rd
, cpu
->regs
[rs1
] << (cpu
->regs
[rs2
] & u_imm
));
252 TRACE_INSN (cpu
, "sllw %s, %s, %s; // %s = %s << %s",
253 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
254 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
255 store_rd (cpu
, rd
, EXTEND32 (
256 (unsigned32
) cpu
->regs
[rs1
] << (cpu
->regs
[rs2
] & 0x1f)));
259 TRACE_INSN (cpu
, "slli %s, %s, %" PRIiTW
"; // %s = %s << %#" PRIxTW
,
260 rd_name
, rs1_name
, shamt_imm
, rd_name
, rs1_name
, shamt_imm
);
261 if (RISCV_XLEN (cpu
) == 32 && shamt_imm
> 0x1f)
262 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
263 store_rd (cpu
, rd
, cpu
->regs
[rs1
] << shamt_imm
);
266 TRACE_INSN (cpu
, "slliw %s, %s, %" PRIiTW
"; // %s = %s << %#" PRIxTW
,
267 rd_name
, rs1_name
, shamt_imm
, rd_name
, rs1_name
, shamt_imm
);
268 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
269 store_rd (cpu
, rd
, EXTEND32 ((unsigned32
) cpu
->regs
[rs1
] << shamt_imm
));
272 TRACE_INSN (cpu
, "srl %s, %s, %s; // %s = %s >> %s",
273 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
274 u_imm
= RISCV_XLEN (cpu
) == 32 ? 0x1f : 0x3f;
275 store_rd (cpu
, rd
, cpu
->regs
[rs1
] >> (cpu
->regs
[rs2
] & u_imm
));
278 TRACE_INSN (cpu
, "srlw %s, %s, %s; // %s = %s >> %s",
279 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
280 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
281 store_rd (cpu
, rd
, EXTEND32 (
282 (unsigned32
) cpu
->regs
[rs1
] >> (cpu
->regs
[rs2
] & 0x1f)));
285 TRACE_INSN (cpu
, "srli %s, %s, %" PRIiTW
"; // %s = %s >> %#" PRIxTW
,
286 rd_name
, rs1_name
, shamt_imm
, rd_name
, rs1_name
, shamt_imm
);
287 if (RISCV_XLEN (cpu
) == 32 && shamt_imm
> 0x1f)
288 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
289 store_rd (cpu
, rd
, cpu
->regs
[rs1
] >> shamt_imm
);
292 TRACE_INSN (cpu
, "srliw %s, %s, %" PRIiTW
"; // %s = %s >> %#" PRIxTW
,
293 rd_name
, rs1_name
, shamt_imm
, rd_name
, rs1_name
, shamt_imm
);
294 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
295 store_rd (cpu
, rd
, EXTEND32 ((unsigned32
) cpu
->regs
[rs1
] >> shamt_imm
));
298 TRACE_INSN (cpu
, "sra %s, %s, %s; // %s = %s >>> %s",
299 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
300 if (RISCV_XLEN (cpu
) == 32)
301 tmp
= ashiftrt (cpu
->regs
[rs1
], cpu
->regs
[rs2
] & 0x1f);
303 tmp
= ashiftrt64 (cpu
->regs
[rs1
], cpu
->regs
[rs2
] & 0x3f);
304 store_rd (cpu
, rd
, tmp
);
307 TRACE_INSN (cpu
, "sraw %s, %s, %s; // %s = %s >>> %s",
308 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
309 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
310 store_rd (cpu
, rd
, EXTEND32 (
311 ashiftrt ((signed32
) cpu
->regs
[rs1
], cpu
->regs
[rs2
] & 0x1f)));
314 TRACE_INSN (cpu
, "srai %s, %s, %" PRIiTW
"; // %s = %s >>> %#" PRIxTW
,
315 rd_name
, rs1_name
, shamt_imm
, rd_name
, rs1_name
, shamt_imm
);
316 if (RISCV_XLEN (cpu
) == 32)
318 if (shamt_imm
> 0x1f)
319 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
320 tmp
= ashiftrt (cpu
->regs
[rs1
], shamt_imm
);
323 tmp
= ashiftrt64 (cpu
->regs
[rs1
], shamt_imm
);
324 store_rd (cpu
, rd
, tmp
);
327 TRACE_INSN (cpu
, "sraiw %s, %s, %" PRIiTW
"; // %s = %s >>> %#" PRIxTW
,
328 rd_name
, rs1_name
, shamt_imm
, rd_name
, rs1_name
, shamt_imm
);
329 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
330 store_rd (cpu
, rd
, EXTEND32 (
331 ashiftrt ((signed32
) cpu
->regs
[rs1
], shamt_imm
)));
334 TRACE_INSN (cpu
, "slt");
336 !!((signed_word
) cpu
->regs
[rs1
] < (signed_word
) cpu
->regs
[rs2
]));
339 TRACE_INSN (cpu
, "sltu");
340 store_rd (cpu
, rd
, !!((unsigned_word
) cpu
->regs
[rs1
] <
341 (unsigned_word
) cpu
->regs
[rs2
]));
344 TRACE_INSN (cpu
, "slti");
345 store_rd (cpu
, rd
, !!((signed_word
) cpu
->regs
[rs1
] <
346 (signed_word
) i_imm
));
349 TRACE_INSN (cpu
, "sltiu");
350 store_rd (cpu
, rd
, !!((unsigned_word
) cpu
->regs
[rs1
] <
351 (unsigned_word
) i_imm
));
354 TRACE_INSN (cpu
, "auipc %s, %" PRIiTW
"; // %s = pc + %" PRIiTW
,
355 rd_name
, u_imm
, rd_name
, u_imm
);
356 store_rd (cpu
, rd
, cpu
->pc
+ u_imm
);
359 TRACE_INSN (cpu
, "beq %s, %s, %#" PRIxTW
"; "
360 "// if (%s == %s) goto %#" PRIxTW
,
361 rs1_name
, rs2_name
, sb_imm
, rs1_name
, rs2_name
, sb_imm
);
362 if (cpu
->regs
[rs1
] == cpu
->regs
[rs2
])
364 pc
= cpu
->pc
+ sb_imm
;
365 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
369 TRACE_INSN (cpu
, "blt %s, %s, %#" PRIxTW
"; "
370 "// if (%s < %s) goto %#" PRIxTW
,
371 rs1_name
, rs2_name
, sb_imm
, rs1_name
, rs2_name
, sb_imm
);
372 if ((signed_word
) cpu
->regs
[rs1
] < (signed_word
) cpu
->regs
[rs2
])
374 pc
= cpu
->pc
+ sb_imm
;
375 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
379 TRACE_INSN (cpu
, "bltu %s, %s, %#" PRIxTW
"; "
380 "// if (%s < %s) goto %#" PRIxTW
,
381 rs1_name
, rs2_name
, sb_imm
, rs1_name
, rs2_name
, sb_imm
);
382 if ((unsigned_word
) cpu
->regs
[rs1
] < (unsigned_word
) cpu
->regs
[rs2
])
384 pc
= cpu
->pc
+ sb_imm
;
385 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
389 TRACE_INSN (cpu
, "bge %s, %s, %#" PRIxTW
"; "
390 "// if (%s >= %s) goto %#" PRIxTW
,
391 rs1_name
, rs2_name
, sb_imm
, rs1_name
, rs2_name
, sb_imm
);
392 if ((signed_word
) cpu
->regs
[rs1
] >= (signed_word
) cpu
->regs
[rs2
])
394 pc
= cpu
->pc
+ sb_imm
;
395 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
399 TRACE_INSN (cpu
, "bgeu %s, %s, %#" PRIxTW
"; "
400 "// if (%s >= %s) goto %#" PRIxTW
,
401 rs1_name
, rs2_name
, sb_imm
, rs1_name
, rs2_name
, sb_imm
);
402 if ((unsigned_word
) cpu
->regs
[rs1
] >= (unsigned_word
) cpu
->regs
[rs2
])
404 pc
= cpu
->pc
+ sb_imm
;
405 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
409 TRACE_INSN (cpu
, "bne %s, %s, %#" PRIxTW
"; "
410 "// if (%s != %s) goto %#" PRIxTW
,
411 rs1_name
, rs2_name
, sb_imm
, rs1_name
, rs2_name
, sb_imm
);
412 if (cpu
->regs
[rs1
] != cpu
->regs
[rs2
])
414 pc
= cpu
->pc
+ sb_imm
;
415 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
419 TRACE_INSN (cpu
, "jal %s, %" PRIiTW
";", rd_name
,
420 EXTRACT_JTYPE_IMM (iw
));
421 store_rd (cpu
, rd
, cpu
->pc
+ 4);
422 pc
= cpu
->pc
+ EXTRACT_JTYPE_IMM (iw
);
423 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
426 TRACE_INSN (cpu
, "jalr %s, %s, %" PRIiTW
";", rd_name
, rs1_name
, i_imm
);
427 store_rd (cpu
, rd
, cpu
->pc
+ 4);
428 pc
= cpu
->regs
[rs1
] + i_imm
;
429 TRACE_BRANCH (cpu
, "to %#" PRIxTW
, pc
);
433 TRACE_INSN (cpu
, "ld %s, %" PRIiTW
"(%s);",
434 rd_name
, i_imm
, rs1_name
);
435 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
437 sim_core_read_unaligned_8 (cpu
, cpu
->pc
, read_map
,
438 cpu
->regs
[rs1
] + i_imm
));
441 TRACE_INSN (cpu
, "lw %s, %" PRIiTW
"(%s);",
442 rd_name
, i_imm
, rs1_name
);
443 store_rd (cpu
, rd
, EXTEND32 (
444 sim_core_read_unaligned_4 (cpu
, cpu
->pc
, read_map
,
445 cpu
->regs
[rs1
] + i_imm
)));
448 TRACE_INSN (cpu
, "lwu %s, %" PRIiTW
"(%s);",
449 rd_name
, i_imm
, rs1_name
);
451 sim_core_read_unaligned_4 (cpu
, cpu
->pc
, read_map
,
452 cpu
->regs
[rs1
] + i_imm
));
455 TRACE_INSN (cpu
, "lh %s, %" PRIiTW
"(%s);",
456 rd_name
, i_imm
, rs1_name
);
457 store_rd (cpu
, rd
, EXTEND16 (
458 sim_core_read_unaligned_2 (cpu
, cpu
->pc
, read_map
,
459 cpu
->regs
[rs1
] + i_imm
)));
462 TRACE_INSN (cpu
, "lbu %s, %" PRIiTW
"(%s);",
463 rd_name
, i_imm
, rs1_name
);
465 sim_core_read_unaligned_2 (cpu
, cpu
->pc
, read_map
,
466 cpu
->regs
[rs1
] + i_imm
));
469 TRACE_INSN (cpu
, "lb %s, %" PRIiTW
"(%s);",
470 rd_name
, i_imm
, rs1_name
);
471 store_rd (cpu
, rd
, EXTEND8 (
472 sim_core_read_unaligned_1 (cpu
, cpu
->pc
, read_map
,
473 cpu
->regs
[rs1
] + i_imm
)));
476 TRACE_INSN (cpu
, "lbu %s, %" PRIiTW
"(%s);",
477 rd_name
, i_imm
, rs1_name
);
479 sim_core_read_unaligned_1 (cpu
, cpu
->pc
, read_map
,
480 cpu
->regs
[rs1
] + i_imm
));
483 TRACE_INSN (cpu
, "sd %s, %" PRIiTW
"(%s);",
484 rs2_name
, s_imm
, rs1_name
);
485 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
486 sim_core_write_unaligned_8 (cpu
, cpu
->pc
, write_map
,
487 cpu
->regs
[rs1
] + s_imm
, cpu
->regs
[rs2
]);
490 TRACE_INSN (cpu
, "sw %s, %" PRIiTW
"(%s);",
491 rs2_name
, s_imm
, rs1_name
);
492 sim_core_write_unaligned_4 (cpu
, cpu
->pc
, write_map
,
493 cpu
->regs
[rs1
] + s_imm
, cpu
->regs
[rs2
]);
496 TRACE_INSN (cpu
, "sh %s, %" PRIiTW
"(%s);",
497 rs2_name
, s_imm
, rs1_name
);
498 sim_core_write_unaligned_2 (cpu
, cpu
->pc
, write_map
,
499 cpu
->regs
[rs1
] + s_imm
, cpu
->regs
[rs2
]);
502 TRACE_INSN (cpu
, "sb %s, %" PRIiTW
"(%s);",
503 rs2_name
, s_imm
, rs1_name
);
504 sim_core_write_unaligned_1 (cpu
, cpu
->pc
, write_map
,
505 cpu
->regs
[rs1
] + s_imm
, cpu
->regs
[rs2
]);
509 TRACE_INSN (cpu
, "csrrc");
512 #define DECLARE_CSR(name, num, ...) \
514 store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
515 store_csr (cpu, #name, num, &cpu->csr.name, \
516 cpu->csr.name & !cpu->regs[rs1]); \
518 #include "opcode/riscv-opc.h"
523 TRACE_INSN (cpu
, "csrrs");
526 #define DECLARE_CSR(name, num, ...) \
528 store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
529 store_csr (cpu, #name, num, &cpu->csr.name, \
530 cpu->csr.name | cpu->regs[rs1]); \
532 #include "opcode/riscv-opc.h"
537 TRACE_INSN (cpu
, "csrrw");
540 #define DECLARE_CSR(name, num, ...) \
542 store_rd (cpu, rd, fetch_csr (cpu, #name, num, &cpu->csr.name)); \
543 store_csr (cpu, #name, num, &cpu->csr.name, cpu->regs[rs1]); \
545 #include "opcode/riscv-opc.h"
551 TRACE_INSN (cpu
, "rdcycle %s;", rd_name
);
552 store_rd (cpu
, rd
, fetch_csr (cpu
, "cycle", CSR_CYCLE
, &cpu
->csr
.cycle
));
555 TRACE_INSN (cpu
, "rdcycleh %s;", rd_name
);
556 RISCV_ASSERT_RV32 (cpu
, "insn: %s", op
->name
);
558 fetch_csr (cpu
, "cycleh", CSR_CYCLEH
, &cpu
->csr
.cycleh
));
560 case MATCH_RDINSTRET
:
561 TRACE_INSN (cpu
, "rdinstret %s;", rd_name
);
563 fetch_csr (cpu
, "instret", CSR_INSTRET
, &cpu
->csr
.instret
));
565 case MATCH_RDINSTRETH
:
566 TRACE_INSN (cpu
, "rdinstreth %s;", rd_name
);
567 RISCV_ASSERT_RV32 (cpu
, "insn: %s", op
->name
);
569 fetch_csr (cpu
, "instreth", CSR_INSTRETH
, &cpu
->csr
.instreth
));
572 TRACE_INSN (cpu
, "rdtime %s;", rd_name
);
573 store_rd (cpu
, rd
, fetch_csr (cpu
, "time", CSR_TIME
, &cpu
->csr
.time
));
576 TRACE_INSN (cpu
, "rdtimeh %s;", rd_name
);
577 RISCV_ASSERT_RV32 (cpu
, "insn: %s", op
->name
);
578 store_rd (cpu
, rd
, fetch_csr (cpu
, "timeh", CSR_TIMEH
, &cpu
->csr
.timeh
));
582 TRACE_INSN (cpu
, "fence;");
585 TRACE_INSN (cpu
, "fence.i;");
588 TRACE_INSN (cpu
, "sbreak;");
589 /* GDB expects us to step over SBREAK. */
590 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
+ 4, sim_stopped
, SIM_SIGTRAP
);
593 TRACE_INSN (cpu
, "ecall;");
594 cpu
->a0
= sim_syscall (cpu
, cpu
->a7
, cpu
->a0
, cpu
->a1
, cpu
->a2
, cpu
->a3
);
597 TRACE_INSN (cpu
, "UNHANDLED INSN: %s", op
->name
);
598 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
605 mulhu (unsigned64 a
, unsigned64 b
)
608 return ((__int128
)a
* b
) >> 64;
612 uint64_t a0
= (uint32_t)a
, a1
= a
>> 32;
613 uint64_t b0
= (uint32_t)b
, b1
= b
>> 32;
615 t
= a1
*b0
+ ((a0
*b0
) >> 32);
622 t
= a1
*b1
+ y2
+ (t
>> 32);
626 return ((uint64_t)y3
<< 32) | y2
;
631 mulh (signed64 a
, signed64 b
)
633 int negate
= (a
< 0) != (b
< 0);
634 uint64_t res
= mulhu (a
< 0 ? -a
: a
, b
< 0 ? -b
: b
);
635 return negate
? ~res
+ (a
* b
== 0) : res
;
639 mulhsu (signed64 a
, unsigned64 b
)
642 uint64_t res
= mulhu (a
< 0 ? -a
: a
, b
);
643 return negate
? ~res
+ (a
* b
== 0) : res
;
647 execute_m (SIM_CPU
*cpu
, unsigned_word iw
, const struct riscv_opcode
*op
)
649 SIM_DESC sd
= CPU_STATE (cpu
);
650 int rd
= (iw
>> OP_SH_RD
) & OP_MASK_RD
;
651 int rs1
= (iw
>> OP_SH_RS1
) & OP_MASK_RS1
;
652 int rs2
= (iw
>> OP_SH_RS2
) & OP_MASK_RS2
;
653 const char *rd_name
= riscv_gpr_names_abi
[rd
];
654 const char *rs1_name
= riscv_gpr_names_abi
[rs1
];
655 const char *rs2_name
= riscv_gpr_names_abi
[rs2
];
656 unsigned_word tmp
, dividend_max
;
657 sim_cia pc
= cpu
->pc
+ 4;
659 dividend_max
= -((unsigned_word
) 1 << (WITH_TARGET_WORD_BITSIZE
- 1));
664 TRACE_INSN (cpu
, "div %s, %s, %s; // %s = %s / %s",
665 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
666 if (cpu
->regs
[rs1
] == dividend_max
&& cpu
->regs
[rs2
] == -1)
668 else if (cpu
->regs
[rs2
])
669 tmp
= (signed_word
) cpu
->regs
[rs1
] / (signed_word
) cpu
->regs
[rs2
];
672 store_rd (cpu
, rd
, tmp
);
675 TRACE_INSN (cpu
, "divw %s, %s, %s; // %s = %s / %s",
676 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
677 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
678 if (EXTEND32 (cpu
->regs
[rs2
]) == -1)
680 else if (EXTEND32 (cpu
->regs
[rs2
]))
681 tmp
= EXTEND32 (cpu
->regs
[rs1
]) / EXTEND32 (cpu
->regs
[rs2
]);
684 store_rd (cpu
, rd
, EXTEND32 (tmp
));
687 TRACE_INSN (cpu
, "divu %s, %s, %s; // %s = %s / %s",
688 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
690 store_rd (cpu
, rd
, (unsigned_word
) cpu
->regs
[rs1
]
691 / (unsigned_word
) cpu
->regs
[rs2
]);
693 store_rd (cpu
, rd
, -1);
696 TRACE_INSN (cpu
, "divuw %s, %s, %s; // %s = %s / %s",
697 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
698 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
699 if ((unsigned32
) cpu
->regs
[rs2
])
700 tmp
= (unsigned32
) cpu
->regs
[rs1
] / (unsigned32
) cpu
->regs
[rs2
];
703 store_rd (cpu
, rd
, EXTEND32 (tmp
));
706 TRACE_INSN (cpu
, "mul %s, %s, %s; // %s = %s * %s",
707 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
708 store_rd (cpu
, rd
, cpu
->regs
[rs1
] * cpu
->regs
[rs2
]);
711 TRACE_INSN (cpu
, "mulw %s, %s, %s; // %s = %s * %s",
712 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
713 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
714 store_rd (cpu
, rd
, EXTEND32 ((signed32
) cpu
->regs
[rs1
]
715 * (signed32
) cpu
->regs
[rs2
]));
718 TRACE_INSN (cpu
, "mulh %s, %s, %s; // %s = %s * %s",
719 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
720 if (RISCV_XLEN (cpu
) == 32)
721 store_rd (cpu
, rd
, ((signed64
)(signed_word
) cpu
->regs
[rs1
]
722 * (signed64
)(signed_word
) cpu
->regs
[rs2
]) >> 32);
724 store_rd (cpu
, rd
, mulh (cpu
->regs
[rs1
], cpu
->regs
[rs2
]));
727 TRACE_INSN (cpu
, "mulhu %s, %s, %s; // %s = %s * %s",
728 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
729 if (RISCV_XLEN (cpu
) == 32)
730 store_rd (cpu
, rd
, ((unsigned64
)cpu
->regs
[rs1
]
731 * (unsigned64
)cpu
->regs
[rs2
]) >> 32);
733 store_rd (cpu
, rd
, mulhu (cpu
->regs
[rs1
], cpu
->regs
[rs2
]));
736 TRACE_INSN (cpu
, "mulhsu %s, %s, %s; // %s = %s * %s",
737 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
738 if (RISCV_XLEN (cpu
) == 32)
739 store_rd (cpu
, rd
, ((signed64
)(signed_word
) cpu
->regs
[rs1
]
740 * (unsigned64
)cpu
->regs
[rs2
]) >> 32);
742 store_rd (cpu
, rd
, mulhsu (cpu
->regs
[rs1
], cpu
->regs
[rs2
]));
745 TRACE_INSN (cpu
, "rem %s, %s, %s; // %s = %s %% %s",
746 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
747 if (cpu
->regs
[rs1
] == dividend_max
&& cpu
->regs
[rs2
] == -1)
749 else if (cpu
->regs
[rs2
])
750 tmp
= (signed_word
) cpu
->regs
[rs1
] % (signed_word
) cpu
->regs
[rs2
];
752 tmp
= cpu
->regs
[rs1
];
753 store_rd (cpu
, rd
, tmp
);
756 TRACE_INSN (cpu
, "remw %s, %s, %s; // %s = %s %% %s",
757 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
758 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
759 if (EXTEND32 (cpu
->regs
[rs2
]) == -1)
761 else if (EXTEND32 (cpu
->regs
[rs2
]))
762 tmp
= EXTEND32 (cpu
->regs
[rs1
]) % EXTEND32 (cpu
->regs
[rs2
]);
764 tmp
= cpu
->regs
[rs1
];
765 store_rd (cpu
, rd
, EXTEND32 (tmp
));
768 TRACE_INSN (cpu
, "remu %s, %s, %s; // %s = %s %% %s",
769 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
771 store_rd (cpu
, rd
, cpu
->regs
[rs1
] % cpu
->regs
[rs2
]);
773 store_rd (cpu
, rd
, cpu
->regs
[rs1
]);
776 TRACE_INSN (cpu
, "remuw %s, %s, %s; // %s = %s %% %s",
777 rd_name
, rs1_name
, rs2_name
, rd_name
, rs1_name
, rs2_name
);
778 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
779 if ((unsigned32
) cpu
->regs
[rs2
])
780 tmp
= (unsigned32
) cpu
->regs
[rs1
] % (unsigned32
) cpu
->regs
[rs2
];
782 tmp
= cpu
->regs
[rs1
];
783 store_rd (cpu
, rd
, EXTEND32 (tmp
));
786 TRACE_INSN (cpu
, "UNHANDLED INSN: %s", op
->name
);
787 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
794 execute_a (SIM_CPU
*cpu
, unsigned_word iw
, const struct riscv_opcode
*op
)
796 SIM_DESC sd
= CPU_STATE (cpu
);
797 struct riscv_sim_state
*state
= RISCV_SIM_STATE (sd
);
798 int rd
= (iw
>> OP_SH_RD
) & OP_MASK_RD
;
799 int rs1
= (iw
>> OP_SH_RS1
) & OP_MASK_RS1
;
800 int rs2
= (iw
>> OP_SH_RS2
) & OP_MASK_RS2
;
801 const char *rd_name
= riscv_gpr_names_abi
[rd
];
802 const char *rs1_name
= riscv_gpr_names_abi
[rs1
];
803 const char *rs2_name
= riscv_gpr_names_abi
[rs2
];
804 struct atomic_mem_reserved_list
*amo_prev
, *amo_curr
;
806 sim_cia pc
= cpu
->pc
+ 4;
808 /* Handle these two load/store operations specifically. */
812 TRACE_INSN (cpu
, "%s %s, (%s);", op
->name
, rd_name
, rs1_name
);
814 sim_core_read_unaligned_4 (cpu
, cpu
->pc
, read_map
, cpu
->regs
[rs1
]));
816 /* Walk the reservation list to find an existing match. */
817 amo_curr
= state
->amo_reserved_list
;
820 if (amo_curr
->addr
== cpu
->regs
[rs1
])
822 amo_curr
= amo_curr
->next
;
825 /* No reservation exists, so add one. */
826 amo_curr
= xmalloc (sizeof (*amo_curr
));
827 amo_curr
->addr
= cpu
->regs
[rs1
];
828 amo_curr
->next
= state
->amo_reserved_list
;
829 state
->amo_reserved_list
= amo_curr
;
832 TRACE_INSN (cpu
, "%s %s, %s, (%s);", op
->name
, rd_name
, rs2_name
,
835 /* Walk the reservation list to find a match. */
836 amo_curr
= amo_prev
= state
->amo_reserved_list
;
839 if (amo_curr
->addr
== cpu
->regs
[rs1
])
841 /* We found a reservation, so operate it. */
842 sim_core_write_unaligned_4 (cpu
, cpu
->pc
, write_map
,
843 cpu
->regs
[rs1
], cpu
->regs
[rs2
]);
844 store_rd (cpu
, rd
, 0);
845 if (amo_curr
== state
->amo_reserved_list
)
846 state
->amo_reserved_list
= amo_curr
->next
;
848 amo_prev
->next
= amo_curr
->next
;
853 amo_curr
= amo_curr
->next
;
856 /* If we're still here, then no reservation exists, so mark as failed. */
857 store_rd (cpu
, rd
, 1);
861 /* Handle the rest of the atomic insns with common code paths. */
862 TRACE_INSN (cpu
, "%s %s, %s, (%s);",
863 op
->name
, rd_name
, rs2_name
, rs1_name
);
864 if (op
->xlen_requirement
== 64)
865 tmp
= sim_core_read_unaligned_8 (cpu
, cpu
->pc
, read_map
, cpu
->regs
[rs1
]);
867 tmp
= EXTEND32 (sim_core_read_unaligned_4 (cpu
, cpu
->pc
, read_map
,
869 store_rd (cpu
, rd
, tmp
);
875 tmp
= cpu
->regs
[rd
] + cpu
->regs
[rs2
];
879 tmp
= cpu
->regs
[rd
] & cpu
->regs
[rs2
];
883 tmp
= max ((signed_word
) cpu
->regs
[rd
], (signed_word
) cpu
->regs
[rs2
]);
885 case MATCH_AMOMAXU_D
:
886 case MATCH_AMOMAXU_W
:
887 tmp
= max ((unsigned_word
) cpu
->regs
[rd
], (unsigned_word
) cpu
->regs
[rs2
]);
891 tmp
= min ((signed_word
) cpu
->regs
[rd
], (signed_word
) cpu
->regs
[rs2
]);
893 case MATCH_AMOMINU_D
:
894 case MATCH_AMOMINU_W
:
895 tmp
= min ((unsigned_word
) cpu
->regs
[rd
], (unsigned_word
) cpu
->regs
[rs2
]);
899 tmp
= cpu
->regs
[rd
] | cpu
->regs
[rs2
];
901 case MATCH_AMOSWAP_D
:
902 case MATCH_AMOSWAP_W
:
903 tmp
= cpu
->regs
[rs2
];
907 tmp
= cpu
->regs
[rd
] ^ cpu
->regs
[rs2
];
910 TRACE_INSN (cpu
, "UNHANDLED INSN: %s", op
->name
);
911 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
914 if (op
->xlen_requirement
== 64)
915 sim_core_write_unaligned_8 (cpu
, cpu
->pc
, write_map
, cpu
->regs
[rs1
], tmp
);
917 sim_core_write_unaligned_4 (cpu
, cpu
->pc
, write_map
, cpu
->regs
[rs1
], tmp
);
924 execute_one (SIM_CPU
*cpu
, unsigned_word iw
, const struct riscv_opcode
*op
)
926 SIM_DESC sd
= CPU_STATE (cpu
);
928 if (op
->xlen_requirement
== 32)
929 RISCV_ASSERT_RV32 (cpu
, "insn: %s", op
->name
);
930 else if (op
->xlen_requirement
== 64)
931 RISCV_ASSERT_RV64 (cpu
, "insn: %s", op
->name
);
933 switch (op
->insn_class
)
936 return execute_a (cpu
, iw
, op
);
938 return execute_i (cpu
, iw
, op
);
940 return execute_m (cpu
, iw
, op
);
942 TRACE_INSN (cpu
, "UNHANDLED EXTENSION: %d", op
->insn_class
);
943 sim_engine_halt (sd
, cpu
, NULL
, cpu
->pc
, sim_signalled
, SIM_SIGILL
);
946 return cpu
->pc
+ riscv_insn_length (iw
);
949 /* Decode & execute a single instruction. */
950 void step_once (SIM_CPU
*cpu
)
952 SIM_DESC sd
= CPU_STATE (cpu
);
955 sim_cia pc
= cpu
->pc
;
956 const struct riscv_opcode
*op
;
957 int xlen
= RISCV_XLEN (cpu
);
959 if (TRACE_ANY_P (cpu
))
960 trace_prefix (sd
, cpu
, NULL_CIA
, pc
, TRACE_LINENUM_P (cpu
),
961 NULL
, 0, " "); /* Use a space for gcc warnings. */
963 iw
= sim_core_read_aligned_2 (cpu
, pc
, exec_map
, pc
);
965 /* Reject non-32-bit opcodes first. */
966 len
= riscv_insn_length (iw
);
969 sim_io_printf (sd
, "sim: bad insn len %#x @ %#" PRIxTA
": %#" PRIxTW
"\n",
971 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_signalled
, SIM_SIGILL
);
974 iw
|= ((unsigned_word
) sim_core_read_aligned_2 (
975 cpu
, pc
, exec_map
, pc
+ 2) << 16);
977 TRACE_CORE (cpu
, "0x%08" PRIxTW
, iw
);
979 op
= riscv_hash
[OP_HASH_IDX (iw
)];
981 sim_engine_halt (sd
, cpu
, NULL
, pc
, sim_signalled
, SIM_SIGILL
);
983 /* NB: Same loop logic as riscv_disassemble_insn. */
984 for (; op
->name
; op
++)
986 /* Does the opcode match? */
987 if (! op
->match_func (op
, iw
))
989 /* Is this a pseudo-instruction and may we print it as such? */
990 if (op
->pinfo
& INSN_ALIAS
)
992 /* Is this instruction restricted to a certain value of XLEN? */
993 if (op
->xlen_requirement
!= 0 && op
->xlen_requirement
!= xlen
)
997 pc
= execute_one (cpu
, iw
, op
);
1001 /* TODO: Handle overflow into high 32 bits. */
1002 /* TODO: Try to use a common counter and only update on demand (reads). */
1009 /* Return the program counter for this cpu. */
1011 pc_get (sim_cpu
*cpu
)
1016 /* Set the program counter for this cpu to the new pc value. */
1018 pc_set (sim_cpu
*cpu
, sim_cia pc
)
1024 reg_fetch (sim_cpu
*cpu
, int rn
, unsigned char *buf
, int len
)
1026 if (len
<= 0 || len
> sizeof (unsigned_word
))
1031 case SIM_RISCV_ZERO_REGNUM
:
1032 memset (buf
, 0, len
);
1034 case SIM_RISCV_RA_REGNUM
... SIM_RISCV_T6_REGNUM
:
1035 memcpy (buf
, &cpu
->regs
[rn
], len
);
1037 case SIM_RISCV_FIRST_FP_REGNUM
... SIM_RISCV_LAST_FP_REGNUM
:
1038 memcpy (buf
, &cpu
->fpregs
[rn
- SIM_RISCV_FIRST_FP_REGNUM
], len
);
1040 case SIM_RISCV_PC_REGNUM
:
1041 memcpy (buf
, &cpu
->pc
, len
);
1044 #define DECLARE_CSR(name, num, ...) \
1045 case SIM_RISCV_ ## num ## _REGNUM: \
1046 memcpy (buf, &cpu->csr.name, len); \
1048 #include "opcode/riscv-opc.h"
1057 reg_store (sim_cpu
*cpu
, int rn
, unsigned char *buf
, int len
)
1059 if (len
<= 0 || len
> sizeof (unsigned_word
))
1064 case SIM_RISCV_ZERO_REGNUM
:
1065 /* Ignore writes. */
1067 case SIM_RISCV_RA_REGNUM
... SIM_RISCV_T6_REGNUM
:
1068 memcpy (&cpu
->regs
[rn
], buf
, len
);
1070 case SIM_RISCV_FIRST_FP_REGNUM
... SIM_RISCV_LAST_FP_REGNUM
:
1071 memcpy (&cpu
->fpregs
[rn
- SIM_RISCV_FIRST_FP_REGNUM
], buf
, len
);
1073 case SIM_RISCV_PC_REGNUM
:
1074 memcpy (&cpu
->pc
, buf
, len
);
1077 #define DECLARE_CSR(name, num, ...) \
1078 case SIM_RISCV_ ## num ## _REGNUM: \
1079 memcpy (&cpu->csr.name, buf, len); \
1081 #include "opcode/riscv-opc.h"
1089 /* Initialize the state for a single cpu. Usuaully this involves clearing all
1090 registers back to their reset state. Should also hook up the fetch/store
1091 helper functions too. */
1093 initialize_cpu (SIM_DESC sd
, SIM_CPU
*cpu
, int mhartid
)
1095 const char *extensions
;
1098 memset (cpu
->regs
, 0, sizeof (cpu
->regs
));
1100 CPU_PC_FETCH (cpu
) = pc_get
;
1101 CPU_PC_STORE (cpu
) = pc_set
;
1102 CPU_REG_FETCH (cpu
) = reg_fetch
;
1103 CPU_REG_STORE (cpu
) = reg_store
;
1107 const struct riscv_opcode
*op
;
1109 for (op
= riscv_opcodes
; op
->name
; op
++)
1110 if (!riscv_hash
[OP_HASH_IDX (op
->match
)])
1111 riscv_hash
[OP_HASH_IDX (op
->match
)] = op
;
1115 /* RV32 sets this field to 0, and we don't really support RV128 yet. */
1116 if (RISCV_XLEN (cpu
) == 64)
1117 cpu
->csr
.misa
|= (unsigned64
)2 << 62;
1119 /* Skip the leading "rv" prefix and the two numbers. */
1120 extensions
= MODEL_NAME (CPU_MODEL (cpu
)) + 4;
1121 for (i
= 0; i
< 26; ++i
)
1127 else if (strchr (extensions
, ext
) != NULL
)
1130 cpu
->csr
.misa
|= 0x1129; /* G = IMAFD. */
1132 cpu
->csr
.misa
|= (1 << i
);
1136 cpu
->csr
.mimpid
= 0x8000;
1137 cpu
->csr
.mhartid
= mhartid
;
1140 /* Some utils don't like having a NULL environ. */
1141 static const char * const simple_env
[] = { "HOME=/", "PATH=/bin", NULL
};
1143 /* Count the number of arguments in an argv. */
1145 count_argv (const char * const *argv
)
1152 for (i
= 0; argv
[i
] != NULL
; ++i
)
1158 initialize_env (SIM_DESC sd
, const char * const *argv
, const char * const *env
)
1160 SIM_CPU
*cpu
= STATE_CPU (sd
, 0);
1162 int argc
, argv_flat
;
1164 address_word sp
, sp_flat
;
1165 unsigned char null
[8] = { 0, 0, 0, 0, 0, 0, 0, 0, };
1167 /* Figure out how many bytes the argv strings take up. */
1168 argc
= count_argv (argv
);
1171 argv_flat
= argc
; /* NUL bytes. */
1172 for (i
= 0; i
< argc
; ++i
)
1173 argv_flat
+= strlen (argv
[i
]);
1175 /* Figure out how many bytes the environ strings take up. */
1178 envc
= count_argv (env
);
1179 env_flat
= envc
; /* NUL bytes. */
1180 for (i
= 0; i
< envc
; ++i
)
1181 env_flat
+= strlen (env
[i
]);
1183 /* Make space for the strings themselves. */
1184 sp_flat
= (DEFAULT_MEM_SIZE
- argv_flat
- env_flat
) & -sizeof (address_word
);
1185 /* Then the pointers to the strings. */
1186 sp
= sp_flat
- ((argc
+ 1 + envc
+ 1) * sizeof (address_word
));
1187 /* Then the argc. */
1188 sp
-= sizeof (unsigned_word
);
1190 /* Set up the regs the libgloss crt0 expects. */
1194 /* First push the argc value. */
1195 sim_write (sd
, sp
, (void *)&argc
, sizeof (unsigned_word
));
1196 sp
+= sizeof (unsigned_word
);
1198 /* Then the actual argv strings so we know where to point argv[]. */
1199 for (i
= 0; i
< argc
; ++i
)
1201 unsigned len
= strlen (argv
[i
]) + 1;
1202 sim_write (sd
, sp_flat
, (void *)argv
[i
], len
);
1203 sim_write (sd
, sp
, (void *)&sp_flat
, sizeof (address_word
));
1205 sp
+= sizeof (address_word
);
1207 sim_write (sd
, sp
, null
, sizeof (address_word
));
1208 sp
+= sizeof (address_word
);
1210 /* Then the actual env strings so we know where to point env[]. */
1211 for (i
= 0; i
< envc
; ++i
)
1213 unsigned len
= strlen (env
[i
]) + 1;
1214 sim_write (sd
, sp_flat
, (void *)env
[i
], len
);
1215 sim_write (sd
, sp
, (void *)&sp_flat
, sizeof (address_word
));
1217 sp
+= sizeof (address_word
);