3 Copyright (C) 2005-2021 Free Software Foundation, Inc.
4 Contributed by Mike Frysinger.
6 This file is part of simulators.
8 This program is free software; you can redistribute it and/or modify
9 it under the terms of the GNU General Public License as published by
10 the Free Software Foundation; either version 3 of the License, or
11 (at your option) any later version.
13 This program is distributed in the hope that it will be useful,
14 but WITHOUT ANY WARRANTY; without even the implied warranty of
15 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16 GNU General Public License for more details.
18 You should have received a copy of the GNU General Public License
19 along with this program. If not, see <http://www.gnu.org/licenses/>. */
24 #define SIM_HAVE_COMMON_SIM_STATE
26 #include "sim-basics.h"
32 unsigned_word regs
[32];
34 /* These are the ABI names. */
35 unsigned_word zero
, ra
, sp
, gp
, tp
;
36 unsigned_word t0
, t1
, t2
;
38 unsigned_word a0
, a1
, a2
, a3
, a4
, a5
, a6
, a7
;
39 unsigned_word s2
, s3
, s4
, s5
, s6
, s7
, s8
, s9
, s10
, s11
;
40 unsigned_word t3
, t4
, t5
, t6
;
44 unsigned_word fpregs
[32];
46 /* These are the ABI names. */
47 unsigned_word ft0
, ft1
, ft2
, ft3
, ft4
, ft5
, ft6
, ft7
;
48 unsigned_word fs0
, fs1
;
49 unsigned_word fa0
, fa1
, fa2
, fa3
, fa4
, fa5
, fa6
, fa7
;
50 unsigned_word fs2
, fs3
, fs4
, fs5
, fs6
, fs7
, fs8
, fs9
, fs10
, fs11
;
51 unsigned_word ft8
, ft9
, ft10
, ft11
;
57 #define DECLARE_CSR(name, ...) unsigned_word name;
58 #include "opcode/riscv-opc.h"
65 struct atomic_mem_reserved_list
;
66 struct atomic_mem_reserved_list
{
67 struct atomic_mem_reserved_list
*next
;
71 struct riscv_sim_state
{
72 struct atomic_mem_reserved_list
*amo_reserved_list
;
74 #define RISCV_SIM_STATE(sd) ((struct riscv_sim_state *) STATE_ARCH_DATA (sd))
76 extern void step_once (SIM_CPU
*);
77 extern void initialize_cpu (SIM_DESC
, SIM_CPU
*, int);
78 extern void initialize_env (SIM_DESC
, const char * const *argv
,
79 const char * const *env
);
81 #define DEFAULT_MEM_SIZE (64 * 1024 * 1024)
83 #define RISCV_XLEN(cpu) MACH_WORD_BITSIZE (CPU_MACH (cpu))