1 /* Simulator for the Hitachi SH architecture.
3 Written by Steve Chamberlain of Cygnus Support.
6 This file is part of SH sim
9 THIS SOFTWARE IS NOT COPYRIGHTED
11 Cygnus offers the following for use in the public domain. Cygnus
12 makes no warranty with regard to the software or it's performance
13 and the user accepts the software "AS IS" with all faults.
15 CYGNUS DISCLAIMS ANY WARRANTIES, EXPRESS OR IMPLIED, WITH REGARD TO
16 THIS SOFTWARE INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
17 MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE.
31 #include "remote-sim.h"
33 /* This file is local - if newlib changes, then so should this. */
39 #include <float.h> /* Needed for _isnan() */
44 #define SIGBUS SIGSEGV
48 #define SIGQUIT SIGTERM
55 extern unsigned char sh_jump_table
[], sh_dsp_table
[0x1000], ppi_table
[];
57 #define O_RECOMPILE 85
59 #define DISASSEMBLER_TABLE
61 /* Define the rate at which the simulator should poll the host
63 #define POLL_QUIT_INTERVAL 0x60000
73 /* System registers. For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
74 which are located in fregs, i.e. strictly speaking, these are
75 out-of-bounds accesses of sregs.i . This wart of the code could be
76 fixed by making fregs part of sregs, and including pc too - to avoid
77 alignment repercussions - but this would cause very onerous union /
78 structure nesting, which would only be managable with anonymous
79 unions and structs. */
88 int fpul
; /* A1 for sh-dsp - but only for movs etc. */
89 int fpscr
; /* dsr for sh-dsp */
103 /* Control registers; on the SH4, ldc / stc is privileged, except when
124 unsigned char *insn_end
;
136 int end_of_registers
;
139 #define PROFILE_FREQ 1
140 #define PROFILE_SHIFT 2
142 unsigned short *profile_hist
;
143 unsigned char *memory
;
144 int xyram_select
, xram_start
, yram_start
;
147 unsigned char *xmem_offset
;
148 unsigned char *ymem_offset
;
154 saved_state_type saved_state
;
156 struct loop_bounds
{ unsigned char *start
, *end
; };
158 /* These variables are at file scope so that functions other than
159 sim_resume can use the fetch/store macros */
161 static int target_little_endian
;
162 static int global_endianw
, endianb
;
163 static int target_dsp
;
164 static int host_little_endian
;
167 static int maskw
= 0;
170 static SIM_OPEN_KIND sim_kind
;
174 /* Short hand definitions of the registers */
176 #define SBIT(x) ((x)&sbit)
177 #define R0 saved_state.asregs.regs[0]
178 #define Rn saved_state.asregs.regs[n]
179 #define Rm saved_state.asregs.regs[m]
180 #define UR0 (unsigned int)(saved_state.asregs.regs[0])
181 #define UR (unsigned int)R
182 #define UR (unsigned int)R
183 #define SR0 saved_state.asregs.regs[0]
184 #define CREG(n) (saved_state.asregs.cregs.i[(n)])
185 #define GBR saved_state.asregs.cregs.named.gbr
186 #define VBR saved_state.asregs.cregs.named.vbr
187 #define SSR saved_state.asregs.cregs.named.ssr
188 #define SPC saved_state.asregs.cregs.named.spc
189 #define SREG(n) (saved_state.asregs.sregs.i[(n)])
190 #define MACH saved_state.asregs.sregs.named.mach
191 #define MACL saved_state.asregs.sregs.named.macl
192 #define PR saved_state.asregs.sregs.named.pr
193 #define FPUL saved_state.asregs.sregs.named.fpul
199 /* Alternate bank of registers r0-r7 */
201 /* Note: code controling SR handles flips between BANK0 and BANK1 */
202 #define Rn_BANK(n) (saved_state.asregs.cregs.named.bank[(n)])
203 #define SET_Rn_BANK(n, EXP) do { saved_state.asregs.cregs.named.bank[(n)] = (EXP); } while (0)
208 #define SR_MASK_DMY (1 << 11)
209 #define SR_MASK_DMX (1 << 10)
210 #define SR_MASK_M (1 << 9)
211 #define SR_MASK_Q (1 << 8)
212 #define SR_MASK_I (0xf << 4)
213 #define SR_MASK_S (1 << 1)
214 #define SR_MASK_T (1 << 0)
216 #define SR_MASK_BL (1 << 28)
217 #define SR_MASK_RB (1 << 29)
218 #define SR_MASK_MD (1 << 30)
219 #define SR_MASK_RC 0x0fff0000
220 #define SR_RC_INCREMENT -0x00010000
222 #define M ((saved_state.asregs.cregs.named.sr & SR_MASK_M) != 0)
223 #define Q ((saved_state.asregs.cregs.named.sr & SR_MASK_Q) != 0)
224 #define S ((saved_state.asregs.cregs.named.sr & SR_MASK_S) != 0)
225 #define T ((saved_state.asregs.cregs.named.sr & SR_MASK_T) != 0)
227 #define SR_BL ((saved_state.asregs.cregs.named.sr & SR_MASK_BL) != 0)
228 #define SR_RB ((saved_state.asregs.cregs.named.sr & SR_MASK_RB) != 0)
229 #define SR_MD ((saved_state.asregs.cregs.named.sr & SR_MASK_MD) != 0)
230 #define SR_DMY ((saved_state.asregs.cregs.named.sr & SR_MASK_DMY) != 0)
231 #define SR_DMX ((saved_state.asregs.cregs.named.sr & SR_MASK_DMX) != 0)
232 #define SR_RC ((saved_state.asregs.cregs.named.sr & SR_MASK_RC))
234 /* Note: don't use this for privileged bits */
235 #define SET_SR_BIT(EXP, BIT) \
238 saved_state.asregs.cregs.named.sr |= (BIT); \
240 saved_state.asregs.cregs.named.sr &= ~(BIT); \
243 #define SET_SR_M(EXP) SET_SR_BIT ((EXP), SR_MASK_M)
244 #define SET_SR_Q(EXP) SET_SR_BIT ((EXP), SR_MASK_Q)
245 #define SET_SR_S(EXP) SET_SR_BIT ((EXP), SR_MASK_S)
246 #define SET_SR_T(EXP) SET_SR_BIT ((EXP), SR_MASK_T)
248 /* stc currently relies on being able to read SR without modifications. */
249 #define GET_SR() (saved_state.asregs.cregs.named.sr - 0)
251 #define SET_SR(x) set_sr (x)
254 (saved_state.asregs.cregs.named.sr \
255 = saved_state.asregs.cregs.named.sr & 0xf000ffff | ((x) & 0xfff) << 16)
257 /* Manipulate FPSCR */
259 #define FPSCR_MASK_FR (1 << 21)
260 #define FPSCR_MASK_SZ (1 << 20)
261 #define FPSCR_MASK_PR (1 << 19)
263 #define FPSCR_FR ((GET_FPSCR() & FPSCR_MASK_FR) != 0)
264 #define FPSCR_SZ ((GET_FPSCR() & FPSCR_MASK_SZ) != 0)
265 #define FPSCR_PR ((GET_FPSCR() & FPSCR_MASK_PR) != 0)
271 int old
= saved_state
.asregs
.sregs
.named
.fpscr
;
272 saved_state
.asregs
.sregs
.named
.fpscr
= (x
);
273 /* swap the floating point register banks */
274 if ((saved_state
.asregs
.sregs
.named
.fpscr
^ old
) & FPSCR_MASK_FR
275 /* Ignore bit change if simulating sh-dsp. */
278 union fregs_u tmpf
= saved_state
.asregs
.fregs
[0];
279 saved_state
.asregs
.fregs
[0] = saved_state
.asregs
.fregs
[1];
280 saved_state
.asregs
.fregs
[1] = tmpf
;
284 /* sts relies on being able to read fpscr directly. */
285 #define GET_FPSCR() (saved_state.asregs.sregs.named.fpscr)
286 #define SET_FPSCR(x) \
291 #define DSR (saved_state.asregs.sregs.named.fpscr)
299 #define RAISE_EXCEPTION(x) \
300 (saved_state.asregs.exception = x, saved_state.asregs.insn_end = 0)
302 /* This function exists mainly for the purpose of setting a breakpoint to
303 catch simulated bus errors when running the simulator under GDB. */
315 raise_exception (SIGBUS
);
318 #define PROCESS_SPECIAL_ADDRESS(addr, endian, ptr, bits_written, \
319 forbidden_addr_bits, data, retval) \
321 if (addr & forbidden_addr_bits) \
326 else if ((addr & saved_state.asregs.xyram_select) \
327 == saved_state.asregs.xram_start) \
328 ptr = (void *) &saved_state.asregs.xmem_offset[addr ^ endian]; \
329 else if ((addr & saved_state.asregs.xyram_select) \
330 == saved_state.asregs.yram_start) \
331 ptr = (void *) &saved_state.asregs.ymem_offset[addr ^ endian]; \
332 else if ((unsigned) addr >> 24 == 0xf0 \
333 && bits_written == 32 && (data & 1) == 0) \
334 /* This invalidates (if not associative) or might invalidate \
335 (if associative) an instruction cache line. This is used for \
336 trampolines. Since we don't simulate the cache, this is a no-op \
337 as far as the simulator is concerned. */ \
341 if (bits_written == 8 && addr > 0x5000000) \
342 IOMEM (addr, 1, data); \
343 /* We can't do anything useful with the other stuff, so fail. */ \
349 /* FIXME: sim_resume should be renamed to sim_engine_run. sim_resume
350 being implemented by ../common/sim_resume.c and the below should
351 make a call to sim_engine_halt */
353 #define BUSERROR(addr, mask) ((addr) & (mask))
355 #define WRITE_BUSERROR(addr, mask, data, addr_func) \
360 addr_func (addr, data); \
366 #define READ_BUSERROR(addr, mask, addr_func) \
370 return addr_func (addr); \
374 /* Define this to enable register lifetime checking.
375 The compiler generates "add #0,rn" insns to mark registers as invalid,
376 the simulator uses this info to call fail if it finds a ref to an invalid
377 register before a def
384 #define CREF(x) if(!valid[x]) fail();
385 #define CDEF(x) valid[x] = 1;
386 #define UNDEF(x) valid[x] = 0;
393 static void parse_and_set_memory_size
PARAMS ((char *str
));
394 static int IOMEM
PARAMS ((int addr
, int write
, int value
));
395 static struct loop_bounds get_loop_bounds
PARAMS((int, int, unsigned char *,
396 unsigned char *, int, int));
397 static void process_wlat_addr
PARAMS((int, int));
398 static void process_wwat_addr
PARAMS((int, int));
399 static void process_wbat_addr
PARAMS((int, int));
400 static int process_rlat_addr
PARAMS((int));
401 static int process_rwat_addr
PARAMS((int));
402 static int process_rbat_addr
PARAMS((int));
403 static void INLINE wlat_fast
PARAMS ((unsigned char *, int, int, int));
404 static void INLINE wwat_fast
PARAMS ((unsigned char *, int, int, int, int));
405 static void INLINE wbat_fast
PARAMS ((unsigned char *, int, int, int));
406 static int INLINE rlat_fast
PARAMS ((unsigned char *, int, int));
407 static int INLINE rwat_fast
PARAMS ((unsigned char *, int, int, int));
408 static int INLINE rbat_fast
PARAMS ((unsigned char *, int, int));
410 static host_callback
*callback
;
414 /* Floating point registers */
416 #define DR(n) (get_dr (n))
422 if (host_little_endian
)
429 dr
.i
[1] = saved_state
.asregs
.fregs
[0].i
[n
+ 0];
430 dr
.i
[0] = saved_state
.asregs
.fregs
[0].i
[n
+ 1];
434 return (saved_state
.asregs
.fregs
[0].d
[n
>> 1]);
437 #define SET_DR(n, EXP) set_dr ((n), (EXP))
444 if (host_little_endian
)
452 saved_state
.asregs
.fregs
[0].i
[n
+ 0] = dr
.i
[1];
453 saved_state
.asregs
.fregs
[0].i
[n
+ 1] = dr
.i
[0];
456 saved_state
.asregs
.fregs
[0].d
[n
>> 1] = exp
;
459 #define SET_FI(n,EXP) (saved_state.asregs.fregs[0].i[(n)] = (EXP))
460 #define FI(n) (saved_state.asregs.fregs[0].i[(n)])
462 #define FR(n) (saved_state.asregs.fregs[0].f[(n)])
463 #define SET_FR(n,EXP) (saved_state.asregs.fregs[0].f[(n)] = (EXP))
465 #define XD_TO_XF(n) ((((n) & 1) << 5) | ((n) & 0x1e))
466 #define XF(n) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f])
467 #define SET_XF(n,EXP) (saved_state.asregs.fregs[(n) >> 5].i[(n) & 0x1f] = (EXP))
469 #define RS saved_state.asregs.cregs.named.rs
470 #define RE saved_state.asregs.cregs.named.re
471 #define MOD (saved_state.asregs.cregs.named.mod)
474 MOD_ME = (unsigned) MOD >> 16 | (SR_DMY ? ~0xffff : (SR_DMX ? 0 : 0x10000)), \
475 MOD_DELTA = (MOD & 0xffff) - ((unsigned) MOD >> 16))
477 #define DSP_R(n) saved_state.asregs.sregs.i[(n)]
478 #define DSP_GRD(n) DSP_R ((n) + 8)
479 #define GET_DSP_GRD(n) ((n | 2) == 7 ? SEXT (DSP_GRD (n)) : SIGN32 (DSP_R (n)))
484 #define Y0 DSP_R (10)
485 #define Y1 DSP_R (11)
486 #define M0 DSP_R (12)
487 #define A1G DSP_R (13)
488 #define M1 DSP_R (14)
489 #define A0G DSP_R (15)
490 /* DSP_R (16) / DSP_GRD (16) are used as a fake destination for pcmp. */
491 #define MOD_ME DSP_GRD (17)
492 #define MOD_DELTA DSP_GRD (18)
494 #define FP_OP(n, OP, m) \
498 if (((n) & 1) || ((m) & 1)) \
499 RAISE_EXCEPTION (SIGILL); \
501 SET_DR(n, (DR(n) OP DR(m))); \
504 SET_FR(n, (FR(n) OP FR(m))); \
507 #define FP_UNARY(n, OP) \
512 RAISE_EXCEPTION (SIGILL); \
514 SET_DR(n, (OP (DR(n)))); \
517 SET_FR(n, (OP (FR(n)))); \
520 #define FP_CMP(n, OP, m) \
524 if (((n) & 1) || ((m) & 1)) \
525 RAISE_EXCEPTION (SIGILL); \
527 SET_SR_T (DR(n) OP DR(m)); \
530 SET_SR_T (FR(n) OP FR(m)); \
537 /* do we need to swap banks */
538 int old_gpr
= SR_MD
&& SR_RB
;
539 int new_gpr
= (new_sr
& SR_MASK_MD
) && (new_sr
& SR_MASK_RB
);
540 if (old_gpr
!= new_gpr
)
543 for (i
= 0; i
< 8; i
++)
545 tmp
= saved_state
.asregs
.cregs
.named
.bank
[i
];
546 saved_state
.asregs
.cregs
.named
.bank
[i
] = saved_state
.asregs
.regs
[i
];
547 saved_state
.asregs
.regs
[i
] = tmp
;
550 saved_state
.asregs
.cregs
.named
.sr
= new_sr
;
555 wlat_fast (memory
, x
, value
, maskl
)
556 unsigned char *memory
;
559 unsigned int *p
= (unsigned int *)(memory
+ x
);
560 WRITE_BUSERROR (x
, maskl
, v
, process_wlat_addr
);
565 wwat_fast (memory
, x
, value
, maskw
, endianw
)
566 unsigned char *memory
;
569 unsigned short *p
= (unsigned short *)(memory
+ (x
^ endianw
));
570 WRITE_BUSERROR (x
, maskw
, v
, process_wwat_addr
);
575 wbat_fast (memory
, x
, value
, maskb
)
576 unsigned char *memory
;
578 unsigned char *p
= memory
+ (x
^ endianb
);
579 WRITE_BUSERROR (x
, maskb
, value
, process_wbat_addr
);
587 rlat_fast (memory
, x
, maskl
)
588 unsigned char *memory
;
590 unsigned int *p
= (unsigned int *)(memory
+ x
);
591 READ_BUSERROR (x
, maskl
, process_rlat_addr
);
597 rwat_fast (memory
, x
, maskw
, endianw
)
598 unsigned char *memory
;
599 int x
, maskw
, endianw
;
601 unsigned short *p
= (unsigned short *)(memory
+ (x
^ endianw
));
602 READ_BUSERROR (x
, maskw
, process_rwat_addr
);
608 riat_fast (insn_ptr
, endianw
)
609 unsigned char *insn_ptr
;
611 unsigned short *p
= (unsigned short *)((size_t) insn_ptr
^ endianw
);
617 rbat_fast (memory
, x
, maskb
)
618 unsigned char *memory
;
620 unsigned char *p
= memory
+ (x
^ endianb
);
621 READ_BUSERROR (x
, maskb
, process_rbat_addr
);
626 #define RWAT(x) (rwat_fast (memory, x, maskw, endianw))
627 #define RLAT(x) (rlat_fast (memory, x, maskl))
628 #define RBAT(x) (rbat_fast (memory, x, maskb))
629 #define RIAT(p) (riat_fast ((p), endianw))
630 #define WWAT(x,v) (wwat_fast (memory, x, v, maskw, endianw))
631 #define WLAT(x,v) (wlat_fast (memory, x, v, maskl))
632 #define WBAT(x,v) (wbat_fast (memory, x, v, maskb))
634 #define RUWAT(x) (RWAT(x) & 0xffff)
635 #define RSWAT(x) ((short)(RWAT(x)))
636 #define RSBAT(x) (SEXT(RBAT(x)))
638 #define RDAT(x, n) (do_rdat (memory, (x), (n), (maskl)))
640 do_rdat (memory
, x
, n
, maskl
)
650 f0
= rlat_fast (memory
, x
+ 0, maskl
);
651 f1
= rlat_fast (memory
, x
+ 4, maskl
);
652 saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)] = f0
;
653 saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)] = f1
;
657 #define WDAT(x, n) (do_wdat (memory, (x), (n), (maskl)))
659 do_wdat (memory
, x
, n
, maskl
)
669 f0
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 0)];
670 f1
= saved_state
.asregs
.fregs
[i
].i
[(j
+ 1)];
671 wlat_fast (memory
, (x
+ 0), f0
, maskl
);
672 wlat_fast (memory
, (x
+ 4), f1
, maskl
);
677 process_wlat_addr (addr
, value
)
683 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 32, 3, value
, );
688 process_wwat_addr (addr
, value
)
694 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 16, 1, value
, );
699 process_wbat_addr (addr
, value
)
705 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, 8, 0, value
, );
710 process_rlat_addr (addr
)
715 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -32, 3, -1, 0);
720 process_rwat_addr (addr
)
725 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -16, 1, -1, 0);
730 process_rbat_addr (addr
)
735 PROCESS_SPECIAL_ADDRESS (addr
, endianb
, ptr
, -8, 0, -1, 0);
739 #define SEXT(x) (((x & 0xff) ^ (~0x7f))+0x80)
740 #define SEXT12(x) (((x & 0xfff) ^ 0x800) - 0x800)
741 #define SEXTW(y) ((int)((short)y))
743 #define SEXT32(x) ((int)((x & 0xffffffff) ^ 0x80000000U) - 0x7fffffff - 1)
745 #define SEXT32(x) ((int)(x))
747 #define SIGN32(x) (SEXT32 (x) >> 31)
749 /* convert pointer from target to host value. */
750 #define PT2H(x) ((x) + memory)
751 /* convert pointer from host to target value. */
752 #define PH2T(x) ((x) - memory)
754 #define SKIP_INSN(p) ((p) += ((RIAT (p) & 0xfc00) == 0xf800 ? 4 : 2))
756 #define SET_NIP(x) nip = (x); CHECK_INSN_PTR (nip);
758 #define Delay_Slot(TEMPPC) iword = RIAT (TEMPPC); goto top;
760 #define CHECK_INSN_PTR(p) \
762 if (saved_state.asregs.exception || PH2T (p) & maskw) \
763 saved_state.asregs.insn_end = 0; \
764 else if (p < loop.end) \
765 saved_state.asregs.insn_end = loop.end; \
767 saved_state.asregs.insn_end = mem_end; \
780 do { memstalls += ((((int) PC & 3) != 0) ? (n) : ((n) - 1)); } while (0)
782 #define L(x) thislock = x;
783 #define TL(x) if ((x) == prevlock) stalls++;
784 #define TB(x,y) if ((x) == prevlock || (y)==prevlock) stalls++;
788 #if defined(__GO32__) || defined(_WIN32)
789 int sim_memory_size
= 19;
791 int sim_memory_size
= 24;
794 static int sim_profile_size
= 17;
800 #define SMR1 (0x05FFFEC8) /* Channel 1 serial mode register */
801 #define BRR1 (0x05FFFEC9) /* Channel 1 bit rate register */
802 #define SCR1 (0x05FFFECA) /* Channel 1 serial control register */
803 #define TDR1 (0x05FFFECB) /* Channel 1 transmit data register */
804 #define SSR1 (0x05FFFECC) /* Channel 1 serial status register */
805 #define RDR1 (0x05FFFECD) /* Channel 1 receive data register */
807 #define SCI_RDRF 0x40 /* Recieve data register full */
808 #define SCI_TDRE 0x80 /* Transmit data register empty */
811 IOMEM (addr
, write
, value
)
843 return time ((long *) 0);
852 static FILE *profile_file
;
854 static unsigned INLINE
859 n
= (n
<< 24 | (n
& 0xff00) << 8
860 | (n
& 0xff0000) >> 8 | (n
& 0xff000000) >> 24);
864 static unsigned short INLINE
869 n
= n
<< 8 | (n
& 0xff00) >> 8;
879 union { char b
[4]; int n
; } u
;
881 fwrite (u
.b
, 4, 1, profile_file
);
889 union { char b
[4]; int n
; } u
;
891 fwrite (u
.b
, 2, 1, profile_file
);
894 /* Turn a pointer in a register into a pointer into real memory. */
900 return (char *) (x
+ saved_state
.asregs
.memory
);
907 unsigned char *memory
= saved_state
.asregs
.memory
;
909 int endian
= endianb
;
914 for (end
= str
; memory
[end
^ endian
]; end
++) ;
925 if (! endianb
|| ! len
)
927 start
= (int *) ptr (str
& ~3);
928 end
= (int *) ptr (str
+ len
);
932 *start
= (old
<< 24 | (old
& 0xff00) << 8
933 | (old
& 0xff0000) >> 8 | (old
& 0xff000000) >> 24);
939 /* Simulate a monitor trap, put the result into r0 and errno into r1 */
942 trap (i
, regs
, memory
, maskl
, maskw
, endianw
)
945 unsigned char *memory
;
950 printf ("%c", regs
[0]);
953 raise_exception (SIGQUIT
);
955 case 3: /* FIXME: for backwards compat, should be removed */
965 #if !defined(__GO32__) && !defined(_WIN32)
969 /* This would work only if endianness matched between host and target.
970 Besides, it's quite dangerous. */
973 regs
[0] = execve (ptr (regs
[5]), (char **)ptr (regs
[6]), (char **)ptr (regs
[7]));
976 regs
[0] = execve (ptr (regs
[5]),(char **) ptr (regs
[6]), 0);
981 regs
[0] = (BUSERROR (regs
[5], maskl
)
983 : pipe ((int *) ptr (regs
[5])));
988 regs
[0] = wait (ptr (regs
[5]));
990 #endif /* !defined(__GO32__) && !defined(_WIN32) */
993 strnswap (regs
[6], regs
[7]);
995 = callback
->read (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
996 strnswap (regs
[6], regs
[7]);
999 strnswap (regs
[6], regs
[7]);
1001 regs
[0] = (int)callback
->write_stdout (callback
, ptr(regs
[6]), regs
[7]);
1003 regs
[0] = (int)callback
->write (callback
, regs
[5], ptr (regs
[6]), regs
[7]);
1004 strnswap (regs
[6], regs
[7]);
1007 regs
[0] = callback
->lseek (callback
,regs
[5], regs
[6], regs
[7]);
1010 regs
[0] = callback
->close (callback
,regs
[5]);
1014 int len
= strswaplen (regs
[5]);
1015 strnswap (regs
[5], len
);
1016 regs
[0] = callback
->open (callback
,ptr (regs
[5]), regs
[6]);
1017 strnswap (regs
[5], len
);
1021 /* EXIT - caller can look in r5 to work out the reason */
1022 raise_exception (SIGQUIT
);
1026 case SYS_stat
: /* added at hmsi */
1027 /* stat system call */
1029 struct stat host_stat
;
1031 int len
= strswaplen (regs
[5]);
1033 strnswap (regs
[5], len
);
1034 regs
[0] = stat (ptr (regs
[5]), &host_stat
);
1035 strnswap (regs
[5], len
);
1039 WWAT (buf
, host_stat
.st_dev
);
1041 WWAT (buf
, host_stat
.st_ino
);
1043 WLAT (buf
, host_stat
.st_mode
);
1045 WWAT (buf
, host_stat
.st_nlink
);
1047 WWAT (buf
, host_stat
.st_uid
);
1049 WWAT (buf
, host_stat
.st_gid
);
1051 WWAT (buf
, host_stat
.st_rdev
);
1053 WLAT (buf
, host_stat
.st_size
);
1055 WLAT (buf
, host_stat
.st_atime
);
1059 WLAT (buf
, host_stat
.st_mtime
);
1063 WLAT (buf
, host_stat
.st_ctime
);
1077 int len
= strswaplen (regs
[5]);
1079 strnswap (regs
[5], len
);
1080 regs
[0] = chown (ptr (regs
[5]), regs
[6], regs
[7]);
1081 strnswap (regs
[5], len
);
1087 int len
= strswaplen (regs
[5]);
1089 strnswap (regs
[5], len
);
1090 regs
[0] = chmod (ptr (regs
[5]), regs
[6]);
1091 strnswap (regs
[5], len
);
1096 /* Cast the second argument to void *, to avoid type mismatch
1097 if a prototype is present. */
1098 int len
= strswaplen (regs
[5]);
1100 strnswap (regs
[5], len
);
1101 regs
[0] = utime (ptr (regs
[5]), (void *) ptr (regs
[6]));
1102 strnswap (regs
[5], len
);
1108 regs
[1] = callback
->get_errno (callback
);
1115 raise_exception (SIGTRAP
);
1122 control_c (sig
, code
, scp
, addr
)
1128 raise_exception (SIGINT
);
1132 div1 (R
, iRn2
, iRn1
/*, T*/)
1139 unsigned char old_q
, tmp1
;
1142 SET_SR_Q ((unsigned char) ((0x80000000 & R
[iRn1
]) != 0));
1144 R
[iRn1
] |= (unsigned long) T
;
1154 tmp1
= (R
[iRn1
] > tmp0
);
1161 SET_SR_Q ((unsigned char) (tmp1
== 0));
1168 tmp1
= (R
[iRn1
] < tmp0
);
1172 SET_SR_Q ((unsigned char) (tmp1
== 0));
1187 tmp1
= (R
[iRn1
] < tmp0
);
1194 SET_SR_Q ((unsigned char) (tmp1
== 0));
1201 tmp1
= (R
[iRn1
] > tmp0
);
1205 SET_SR_Q ((unsigned char) (tmp1
== 0));
1226 unsigned long RnL
, RnH
;
1227 unsigned long RmL
, RmH
;
1228 unsigned long temp0
, temp1
, temp2
, temp3
;
1229 unsigned long Res2
, Res1
, Res0
;
1232 RnH
= (rn
>> 16) & 0xffff;
1234 RmH
= (rm
>> 16) & 0xffff;
1240 Res1
= temp1
+ temp2
;
1243 temp1
= (Res1
<< 16) & 0xffff0000;
1244 Res0
= temp0
+ temp1
;
1247 Res2
+= ((Res1
>> 16) & 0xffff) + temp3
;
1251 if (rn
& 0x80000000)
1253 if (rm
& 0x80000000)
1262 macw (regs
, memory
, n
, m
, endianw
)
1264 unsigned char *memory
;
1269 long prod
, macl
, sum
;
1271 tempm
=RSWAT(regs
[m
]); regs
[m
]+=2;
1272 tempn
=RSWAT(regs
[n
]); regs
[n
]+=2;
1275 prod
= (long)(short) tempm
* (long)(short) tempn
;
1279 if ((~(prod
^ macl
) & (sum
^ prod
)) < 0)
1281 /* MACH's lsb is a sticky overflow bit. */
1283 /* Store the smallest negative number in MACL if prod is
1284 negative, and the largest positive number otherwise. */
1285 sum
= 0x7fffffff + (prod
< 0);
1291 /* Add to MACH the sign extended product, and carry from low sum. */
1292 mach
= MACH
+ (-(prod
< 0)) + ((unsigned long) sum
< prod
);
1293 /* Sign extend at 10:th bit in MACH. */
1294 MACH
= (mach
& 0x1ff) | -(mach
& 0x200);
1299 static struct loop_bounds
1300 get_loop_bounds (rs
, re
, memory
, mem_end
, maskw
, endianw
)
1302 unsigned char *memory
, *mem_end
;
1305 struct loop_bounds loop
;
1311 loop
.start
= PT2H (RE
- 4);
1312 SKIP_INSN (loop
.start
);
1313 loop
.end
= loop
.start
;
1315 SKIP_INSN (loop
.end
);
1317 SKIP_INSN (loop
.end
);
1318 SKIP_INSN (loop
.end
);
1322 loop
.start
= PT2H (RS
);
1323 loop
.end
= PT2H (RE
- 4);
1324 SKIP_INSN (loop
.end
);
1325 SKIP_INSN (loop
.end
);
1326 SKIP_INSN (loop
.end
);
1327 SKIP_INSN (loop
.end
);
1329 if (loop
.end
>= mem_end
)
1330 loop
.end
= PT2H (0);
1333 loop
.end
= PT2H (0);
1343 /* Set the memory size to the power of two provided. */
1350 saved_state
.asregs
.msize
= 1 << power
;
1352 sim_memory_size
= power
;
1354 if (saved_state
.asregs
.memory
)
1356 free (saved_state
.asregs
.memory
);
1359 saved_state
.asregs
.memory
=
1360 (unsigned char *) calloc (64, saved_state
.asregs
.msize
/ 64);
1362 if (!saved_state
.asregs
.memory
)
1365 "Not enough VM for simulation of %d bytes of RAM\n",
1366 saved_state
.asregs
.msize
);
1368 saved_state
.asregs
.msize
= 1;
1369 saved_state
.asregs
.memory
= (unsigned char *) calloc (1, 1);
1377 int was_dsp
= target_dsp
;
1378 unsigned long mach
= bfd_get_mach (abfd
);
1380 if (mach
== bfd_mach_sh_dsp
|| mach
== bfd_mach_sh3_dsp
)
1382 int ram_area_size
, xram_start
, yram_start
;
1386 if (mach
== bfd_mach_sh_dsp
)
1388 /* SH7410 (orig. sh-sdp):
1389 4KB each for X & Y memory;
1390 On-chip X RAM 0x0800f000-0x0800ffff
1391 On-chip Y RAM 0x0801f000-0x0801ffff */
1392 xram_start
= 0x0800f000;
1393 ram_area_size
= 0x1000;
1395 if (mach
== bfd_mach_sh3_dsp
)
1398 8KB each for X & Y memory;
1399 On-chip X RAM 0x1000e000-0x1000ffff
1400 On-chip Y RAM 0x1001e000-0x1001ffff */
1401 xram_start
= 0x1000e000;
1402 ram_area_size
= 0x2000;
1404 yram_start
= xram_start
+ 0x10000;
1405 new_select
= ~(ram_area_size
- 1);
1406 if (saved_state
.asregs
.xyram_select
!= new_select
)
1408 saved_state
.asregs
.xyram_select
= new_select
;
1409 free (saved_state
.asregs
.xmem
);
1410 free (saved_state
.asregs
.ymem
);
1411 saved_state
.asregs
.xmem
= (unsigned char *) calloc (1, ram_area_size
);
1412 saved_state
.asregs
.ymem
= (unsigned char *) calloc (1, ram_area_size
);
1414 /* Disable use of X / Y mmeory if not allocated. */
1415 if (! saved_state
.asregs
.xmem
|| ! saved_state
.asregs
.ymem
)
1417 saved_state
.asregs
.xyram_select
= 0;
1418 if (saved_state
.asregs
.xmem
)
1419 free (saved_state
.asregs
.xmem
);
1420 if (saved_state
.asregs
.ymem
)
1421 free (saved_state
.asregs
.ymem
);
1424 saved_state
.asregs
.xram_start
= xram_start
;
1425 saved_state
.asregs
.yram_start
= yram_start
;
1426 saved_state
.asregs
.xmem_offset
= saved_state
.asregs
.xmem
- xram_start
;
1427 saved_state
.asregs
.ymem_offset
= saved_state
.asregs
.ymem
- yram_start
;
1432 if (saved_state
.asregs
.xyram_select
)
1434 saved_state
.asregs
.xyram_select
= 0;
1435 free (saved_state
.asregs
.xmem
);
1436 free (saved_state
.asregs
.ymem
);
1440 if (! saved_state
.asregs
.xyram_select
)
1442 saved_state
.asregs
.xram_start
= 1;
1443 saved_state
.asregs
.yram_start
= 1;
1446 if (target_dsp
!= was_dsp
)
1450 for (i
= sizeof sh_dsp_table
- 1; i
>= 0; i
--)
1452 tmp
= sh_jump_table
[0xf000 + i
];
1453 sh_jump_table
[0xf000 + i
] = sh_dsp_table
[i
];
1454 sh_dsp_table
[i
] = tmp
;
1462 host_little_endian
= 0;
1463 *(char*)&host_little_endian
= 1;
1464 host_little_endian
&= 1;
1466 if (saved_state
.asregs
.msize
!= 1 << sim_memory_size
)
1468 sim_size (sim_memory_size
);
1471 if (saved_state
.asregs
.profile
&& !profile_file
)
1473 profile_file
= fopen ("gmon.out", "wb");
1474 /* Seek to where to put the call arc data */
1475 nsamples
= (1 << sim_profile_size
);
1477 fseek (profile_file
, nsamples
* 2 + 12, 0);
1481 fprintf (stderr
, "Can't open gmon.out\n");
1485 saved_state
.asregs
.profile_hist
=
1486 (unsigned short *) calloc (64, (nsamples
* sizeof (short) / 64));
1499 p
= saved_state
.asregs
.profile_hist
;
1501 maxpc
= (1 << sim_profile_size
);
1503 fseek (profile_file
, 0L, 0);
1504 swapout (minpc
<< PROFILE_SHIFT
);
1505 swapout (maxpc
<< PROFILE_SHIFT
);
1506 swapout (nsamples
* 2 + 12);
1507 for (i
= 0; i
< nsamples
; i
++)
1508 swapout16 (saved_state
.asregs
.profile_hist
[i
]);
1522 #define MMASKB ((saved_state.asregs.msize -1) & ~0)
1528 raise_exception (SIGINT
);
1533 sim_resume (sd
, step
, siggnal
)
1537 register unsigned char *insn_ptr
;
1538 unsigned char *mem_end
;
1539 struct loop_bounds loop
;
1540 register int cycles
= 0;
1541 register int stalls
= 0;
1542 register int memstalls
= 0;
1543 register int insts
= 0;
1544 register int prevlock
;
1545 register int thislock
;
1546 register unsigned int doprofile
;
1547 register int pollcount
= 0;
1548 /* endianw is used for every insn fetch, hence it makes sense to cache it.
1549 endianb is used less often. */
1550 register int endianw
= global_endianw
;
1552 int tick_start
= get_now ();
1554 void (*prev_fpe
) ();
1556 register unsigned char *jump_table
= sh_jump_table
;
1558 register int *R
= &(saved_state
.asregs
.regs
[0]);
1564 register int maskb
= ~((saved_state
.asregs
.msize
- 1) & ~0);
1565 register int maskw
= ~((saved_state
.asregs
.msize
- 1) & ~1);
1566 register int maskl
= ~((saved_state
.asregs
.msize
- 1) & ~3);
1567 register unsigned char *memory
;
1568 register unsigned int sbit
= ((unsigned int) 1 << 31);
1570 prev
= signal (SIGINT
, control_c
);
1571 prev_fpe
= signal (SIGFPE
, SIG_IGN
);
1574 saved_state
.asregs
.exception
= 0;
1576 memory
= saved_state
.asregs
.memory
;
1577 mem_end
= memory
+ saved_state
.asregs
.msize
;
1579 loop
= get_loop_bounds (RS
, RE
, memory
, mem_end
, maskw
, endianw
);
1580 insn_ptr
= PT2H (saved_state
.asregs
.pc
);
1581 CHECK_INSN_PTR (insn_ptr
);
1584 PR
= saved_state
.asregs
.sregs
.named
.pr
;
1586 /*T = GET_SR () & SR_MASK_T;*/
1587 prevlock
= saved_state
.asregs
.prevlock
;
1588 thislock
= saved_state
.asregs
.thislock
;
1589 doprofile
= saved_state
.asregs
.profile
;
1591 /* If profiling not enabled, disable it by asking for
1592 profiles infrequently. */
1597 if (step
&& insn_ptr
< saved_state
.asregs
.insn_end
)
1599 if (saved_state
.asregs
.exception
)
1600 /* This can happen if we've already been single-stepping and
1601 encountered a loop end. */
1602 saved_state
.asregs
.insn_end
= insn_ptr
;
1605 saved_state
.asregs
.exception
= SIGTRAP
;
1606 saved_state
.asregs
.insn_end
= insn_ptr
+ 2;
1610 while (insn_ptr
< saved_state
.asregs
.insn_end
)
1612 register unsigned int iword
= RIAT (insn_ptr
);
1613 register unsigned int ult
;
1614 register unsigned char *nip
= insn_ptr
+ 2;
1626 if (--pollcount
< 0)
1628 pollcount
= POLL_QUIT_INTERVAL
;
1629 if ((*callback
->poll_quit
) != NULL
1630 && (*callback
->poll_quit
) (callback
))
1637 prevlock
= thislock
;
1641 if (cycles
>= doprofile
)
1644 saved_state
.asregs
.cycles
+= doprofile
;
1645 cycles
-= doprofile
;
1646 if (saved_state
.asregs
.profile_hist
)
1648 int n
= PH2T (insn_ptr
) >> PROFILE_SHIFT
;
1651 int i
= saved_state
.asregs
.profile_hist
[n
];
1653 saved_state
.asregs
.profile_hist
[n
] = i
+ 1;
1660 if (saved_state
.asregs
.insn_end
== loop
.end
)
1662 saved_state
.asregs
.cregs
.named
.sr
+= SR_RC_INCREMENT
;
1664 insn_ptr
= loop
.start
;
1667 saved_state
.asregs
.insn_end
= mem_end
;
1668 loop
.end
= PT2H (0);
1673 if (saved_state
.asregs
.exception
== SIGILL
1674 || saved_state
.asregs
.exception
== SIGBUS
)
1678 /* Check for SIGBUS due to insn fetch. */
1679 else if (! saved_state
.asregs
.exception
)
1680 saved_state
.asregs
.exception
== SIGBUS
;
1682 saved_state
.asregs
.ticks
+= get_now () - tick_start
;
1683 saved_state
.asregs
.cycles
+= cycles
;
1684 saved_state
.asregs
.stalls
+= stalls
;
1685 saved_state
.asregs
.memstalls
+= memstalls
;
1686 saved_state
.asregs
.insts
+= insts
;
1687 saved_state
.asregs
.pc
= PH2T (insn_ptr
);
1689 saved_state
.asregs
.sregs
.named
.pr
= PR
;
1692 saved_state
.asregs
.prevlock
= prevlock
;
1693 saved_state
.asregs
.thislock
= thislock
;
1700 signal (SIGFPE
, prev_fpe
);
1701 signal (SIGINT
, prev
);
1705 sim_write (sd
, addr
, buffer
, size
)
1708 unsigned char *buffer
;
1715 for (i
= 0; i
< size
; i
++)
1717 saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
] = buffer
[i
];
1723 sim_read (sd
, addr
, buffer
, size
)
1726 unsigned char *buffer
;
1733 for (i
= 0; i
< size
; i
++)
1735 buffer
[i
] = saved_state
.asregs
.memory
[(MMASKB
& (addr
+ i
)) ^ endianb
];
1741 sim_store_register (sd
, rn
, memory
, length
)
1744 unsigned char *memory
;
1750 val
= swap (* (int *)memory
);
1753 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
1754 case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
1755 saved_state
.asregs
.regs
[rn
] = val
;
1758 saved_state
.asregs
.pc
= val
;
1817 else case 35: case 36: case 37: case 38: case 39:
1818 SET_FI (rn
- 25, val
);
1826 /* The rn_bank idiosyncracies are not due to hardware differences, but to
1827 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
1834 else case 45: case 46: case 47: case 48: case 49: case 50:
1836 Rn_BANK (rn
- 43) = val
;
1838 saved_state
.asregs
.regs
[rn
- 43] = val
;
1840 case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
1841 if (target_dsp
|| ! SR_MD
|| ! SR_RB
)
1842 SET_Rn_BANK (rn
- 51, val
);
1844 saved_state
.asregs
.regs
[rn
- 51] = val
;
1853 sim_fetch_register (sd
, rn
, memory
, length
)
1856 unsigned char *memory
;
1864 case 0: case 1: case 2: case 3: case 4: case 5: case 6: case 7:
1865 case 8: case 9: case 10: case 11: case 12: case 13: case 14: case 15:
1866 val
= saved_state
.asregs
.regs
[rn
];
1869 val
= saved_state
.asregs
.pc
;
1896 val
= target_dsp
? SEXT (A0G
) : FI (0);
1899 val
= target_dsp
? A0
: FI (1);
1902 val
= target_dsp
? SEXT (A1G
) : FI (2);
1905 val
= target_dsp
? A1
: FI (3);
1908 val
= target_dsp
? M0
: FI (4);
1911 val
= target_dsp
? M1
: FI (5);
1914 val
= target_dsp
? X0
: FI (6);
1917 val
= target_dsp
? X1
: FI (7);
1920 val
= target_dsp
? Y0
: FI (8);
1923 val
= target_dsp
? Y1
: FI (9);
1925 case 35: case 36: case 37: case 38: case 39:
1929 val
= target_dsp
? MOD
: FI (15);
1937 /* The rn_bank idiosyncracies are not due to hardware differences, but to
1938 a weird aliasing naming scheme for sh3 / sh3e / sh4. */
1945 else case 45: case 46: case 47: case 48: case 49: case 50:
1946 val
= (SR_MD
&& SR_RB
1948 : saved_state
.asregs
.regs
[rn
- 43]);
1950 case 51: case 52: case 53: case 54: case 55: case 56: case 57: case 58:
1951 val
= (target_dsp
|| ! SR_MD
|| ! SR_RB
1953 : saved_state
.asregs
.regs
[rn
- 51]);
1958 * (int *) memory
= swap (val
);
1970 sim_stop_reason (sd
, reason
, sigrc
)
1972 enum sim_stop
*reason
;
1975 /* The SH simulator uses SIGQUIT to indicate that the program has
1976 exited, so we must check for it here and translate it to exit. */
1977 if (saved_state
.asregs
.exception
== SIGQUIT
)
1979 *reason
= sim_exited
;
1980 *sigrc
= saved_state
.asregs
.regs
[5];
1984 *reason
= sim_stopped
;
1985 *sigrc
= saved_state
.asregs
.exception
;
1990 sim_info (sd
, verbose
)
1994 double timetaken
= (double) saved_state
.asregs
.ticks
/ (double) now_persec ();
1995 double virttime
= saved_state
.asregs
.cycles
/ 36.0e6
;
1997 callback
->printf_filtered (callback
, "\n\n# instructions executed %10d\n",
1998 saved_state
.asregs
.insts
);
1999 callback
->printf_filtered (callback
, "# cycles %10d\n",
2000 saved_state
.asregs
.cycles
);
2001 callback
->printf_filtered (callback
, "# pipeline stalls %10d\n",
2002 saved_state
.asregs
.stalls
);
2003 callback
->printf_filtered (callback
, "# misaligned load/store %10d\n",
2004 saved_state
.asregs
.memstalls
);
2005 callback
->printf_filtered (callback
, "# real time taken %10.4f\n",
2007 callback
->printf_filtered (callback
, "# virtual time taken %10.4f\n",
2009 callback
->printf_filtered (callback
, "# profiling size %10d\n",
2011 callback
->printf_filtered (callback
, "# profiling frequency %10d\n",
2012 saved_state
.asregs
.profile
);
2013 callback
->printf_filtered (callback
, "# profile maxpc %10x\n",
2014 (1 << sim_profile_size
) << PROFILE_SHIFT
);
2018 callback
->printf_filtered (callback
, "# cycles/second %10d\n",
2019 (int) (saved_state
.asregs
.cycles
/ timetaken
));
2020 callback
->printf_filtered (callback
, "# simulation ratio %10.4f\n",
2021 virttime
/ timetaken
);
2029 saved_state
.asregs
.profile
= n
;
2033 sim_set_profile_size (n
)
2036 sim_profile_size
= n
;
2040 sim_open (kind
, cb
, abfd
, argv
)
2061 for (p
= argv
+ 1; *p
!= NULL
; ++p
)
2063 if (strcmp (*p
, "-E") == 0)
2068 /* FIXME: This doesn't use stderr, but then the rest of the
2069 file doesn't either. */
2070 callback
->printf_filtered (callback
, "Missing argument to `-E'.\n");
2073 target_little_endian
= strcmp (*p
, "big") != 0;
2076 else if (isdigit (**p
))
2077 parse_and_set_memory_size (*p
);
2080 if (abfd
!= NULL
&& ! endian_set
)
2081 target_little_endian
= ! bfd_big_endian (abfd
);
2086 for (i
= 4; (i
-= 2) >= 0; )
2087 mem_word
.s
[i
>> 1] = i
;
2088 global_endianw
= mem_word
.i
>> (target_little_endian
? 0 : 16) & 0xffff;
2090 for (i
= 4; --i
>= 0; )
2092 endianb
= mem_word
.i
>> (target_little_endian
? 0 : 24) & 0xff;
2094 /* fudge our descriptor for now */
2095 return (SIM_DESC
) 1;
2099 parse_and_set_memory_size (str
)
2104 n
= strtol (str
, NULL
, 10);
2105 if (n
> 0 && n
<= 24)
2106 sim_memory_size
= n
;
2108 callback
->printf_filtered (callback
, "Bad memory size %d; must be 1 to 24, inclusive\n", n
);
2112 sim_close (sd
, quitting
)
2120 sim_load (sd
, prog
, abfd
, from_tty
)
2126 extern bfd
*sim_load_file (); /* ??? Don't know where this should live. */
2129 prog_bfd
= sim_load_file (sd
, myname
, callback
, prog
, abfd
,
2130 sim_kind
== SIM_OPEN_DEBUG
,
2132 if (prog_bfd
== NULL
)
2135 bfd_close (prog_bfd
);
2140 sim_create_inferior (sd
, prog_bfd
, argv
, env
)
2142 struct _bfd
*prog_bfd
;
2146 /* clear the registers */
2147 memset (&saved_state
, 0,
2148 (char*)&saved_state
.asregs
.end_of_registers
- (char*)&saved_state
);
2150 if (prog_bfd
!= NULL
)
2151 saved_state
.asregs
.pc
= bfd_get_start_address (prog_bfd
);
2156 sim_do_command (sd
, cmd
)
2160 char *sms_cmd
= "set-memory-size";
2163 if (cmd
== NULL
|| *cmd
== '\0')
2168 cmdsize
= strlen (sms_cmd
);
2169 if (strncmp (cmd
, sms_cmd
, cmdsize
) == 0 && strchr (" \t", cmd
[cmdsize
]) != NULL
)
2171 parse_and_set_memory_size (cmd
+ cmdsize
+ 1);
2173 else if (strcmp (cmd
, "help") == 0)
2175 (callback
->printf_filtered
) (callback
, "List of SH simulator commands:\n\n");
2176 (callback
->printf_filtered
) (callback
, "set-memory-size <n> -- Set the number of address bits to use\n");
2177 (callback
->printf_filtered
) (callback
, "\n");
2181 (callback
->printf_filtered
) (callback
, "Error: \"%s\" is not a valid SH simulator command.\n", cmd
);
2186 sim_set_callbacks (p
)