sim/sh/sim-main.h

   1 /* Moxie Simulator definition.
   2    Copyright (C) 2009-2015 Free Software Foundation, Inc.
   3
   4 This file is part of GDB, the GNU debugger.
   5
   6 This program is free software; you can redistribute it and/or modify
   7 it under the terms of the GNU General Public License as published by
   8 the Free Software Foundation; either version 3 of the License, or
   9 (at your option) any later version.
  10
  11 This program is distributed in the hope that it will be useful,
  12 but WITHOUT ANY WARRANTY; without even the implied warranty of
  13 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14 GNU General Public License for more details.
  15
  16 You should have received a copy of the GNU General Public License
  17 along with this program.  If not, see <http://www.gnu.org/licenses/>.  */
  18
  19 #ifndef SIM_MAIN_H
  20 #define SIM_MAIN_H
  21
  22 #include "sim-basics.h"
  23
  24 typedef address_word sim_cia;
  25
  26 #define CIA_GET(cpu)     saved_state.asregs.pc
  27 #define CIA_SET(cpu,val) saved_state.asregs.pc = (val)
  28
  29 typedef struct _sim_cpu SIM_CPU;
  30
  31 #include "sim-base.h"
  32
  33 typedef struct
  34 {
  35   int regs[20];
  36 } regstacktype;
  37
  38 typedef union
  39 {
  40
  41   struct
  42   {
  43     int regs[16];
  44     int pc;
  45
  46     /* System registers.  For sh-dsp this also includes A0 / X0 / X1 / Y0 / Y1
  47        which are located in fregs, i.e. strictly speaking, these are
  48        out-of-bounds accesses of sregs.i .  This wart of the code could be
  49        fixed by making fregs part of sregs, and including pc too - to avoid
  50        alignment repercussions - but this would cause very onerous union /
  51        structure nesting, which would only be managable with anonymous
  52        unions and structs.  */
  53     union
  54       {
  55         struct
  56           {
  57             int mach;
  58             int macl;
  59             int pr;
  60             int dummy3, dummy4;
  61             int fpul; /* A1 for sh-dsp -  but only for movs etc.  */
  62             int fpscr; /* dsr for sh-dsp */
  63           } named;
  64         int i[7];
  65       } sregs;
  66
  67     /* sh3e / sh-dsp */
  68     union fregs_u
  69       {
  70         float f[16];
  71         double d[8];
  72         int i[16];
  73       }
  74     fregs[2];
  75
  76     /* Control registers; on the SH4, ldc / stc is privileged, except when
  77        accessing gbr.  */
  78     union
  79       {
  80         struct
  81           {
  82             int sr;
  83             int gbr;
  84             int vbr;
  85             int ssr;
  86             int spc;
  87             int mod;
  88             /* sh-dsp */
  89             int rs;
  90             int re;
  91             /* sh3 */
  92             int bank[8];
  93             int dbr;            /* debug base register */
  94             int sgr;            /* saved gr15 */
  95             int ldst;           /* load/store flag (boolean) */
  96             int tbr;
  97             int ibcr;           /* sh2a bank control register */
  98             int ibnr;           /* sh2a bank number register */
  99           } named;
 100         int i[16];
 101       } cregs;
 102
 103     unsigned char *insn_end;
 104
 105     int ticks;
 106     int stalls;
 107     int memstalls;
 108     int cycles;
 109     int insts;
 110
 111     int prevlock;
 112     int thislock;
 113     int exception;
 114
 115     int end_of_registers;
 116
 117     int msize;
 118 #define PROFILE_FREQ 1
 119 #define PROFILE_SHIFT 2
 120     int profile;
 121     unsigned short *profile_hist;
 122     unsigned char *memory;
 123     int xyram_select, xram_start, yram_start;
 124     unsigned char *xmem;
 125     unsigned char *ymem;
 126     unsigned char *xmem_offset;
 127     unsigned char *ymem_offset;
 128     unsigned long bfd_mach;
 129     regstacktype *regstack;
 130   } asregs;
 131   int asints[40];
 132 } saved_state_type;
 133
 134 /* TODO: Move into sim_cpu.  */
 135 extern saved_state_type saved_state;
 136
 137 struct _sim_cpu {
 138
 139   sim_cpu_base base;
 140 };
 141
 142 struct sim_state {
 143
 144   sim_cpu *cpu[MAX_NR_PROCESSORS];
 145
 146   sim_state_base base;
 147 };
 148
 149 #endif