2 * Copyright (c) 2003 The Regents of The University of Michigan
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29 #ifndef __SIMPLE_CPU_HH__
30 #define __SIMPLE_CPU_HH__
32 #include "base_cpu.hh"
35 #include "pc_event.hh"
36 #include "statistics.hh"
39 // forward declarations
58 class SimpleCPU : public BaseCPU
61 // main simulation loop (one cycle)
65 class TickEvent : public Event
71 TickEvent(SimpleCPU *c)
72 : Event(&mainEventQueue, 100), cpu(c) { }
73 void process() { cpu->tick(); }
74 virtual const char *description() { return "tick event"; }
80 Trace::InstRecord *traceData;
82 void trace_data(T data) {
84 traceData->setData(data);
102 void post_interrupt(int int_num, int index);
104 void zero_fill_64(Addr addr) {
105 static int warned = 0;
107 warn ("WH64 is not implemented");
114 SimpleCPU(const std::string &_name,
116 Counter max_insts_any_thread, Counter max_insts_all_threads,
117 AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
118 MemInterface *icache_interface, MemInterface *dcache_interface,
119 int cpu_id, Tick freq);
123 SimpleCPU(const std::string &_name, Process *_process,
124 Counter max_insts_any_thread,
125 Counter max_insts_all_threads,
126 MemInterface *icache_interface, MemInterface *dcache_interface);
130 virtual ~SimpleCPU();
136 Addr dbg_vtophys(Addr addr);
141 // L1 instruction cache
142 MemInterface *icacheInterface;
145 MemInterface *dcacheInterface;
147 // current instruction
150 // current fault status
153 // Refcounted pointer to the one memory request.
156 class CacheCompletionEvent : public Event
162 CacheCompletionEvent(SimpleCPU *_cpu);
164 virtual void process();
165 virtual const char *description();
168 CacheCompletionEvent cacheCompletionEvent;
170 Status status() const { return _status; }
171 virtual void execCtxStatusChg() {
173 if (xc->status() == ExecContext::Active)
180 void setStatus(Status new_status) {
181 Status old_status = status();
182 _status = new_status;
185 case IcacheMissStall:
186 assert(old_status == Running);
187 lastIcacheStall = curTick;
188 if (tickEvent.scheduled())
192 case IcacheMissComplete:
193 assert(old_status == IcacheMissStall);
194 if (tickEvent.squashed())
195 tickEvent.reschedule(curTick + 1);
196 else if (!tickEvent.scheduled())
197 tickEvent.schedule(curTick + 1);
200 case DcacheMissStall:
201 assert(old_status == Running);
202 lastDcacheStall = curTick;
203 if (tickEvent.scheduled())
208 assert(old_status == Running);
210 if (tickEvent.scheduled())
215 assert(old_status == Idle ||
216 old_status == DcacheMissStall ||
217 old_status == IcacheMissComplete);
218 if (old_status == Idle)
219 idleCycles += curTick - last_idle;
221 if (tickEvent.squashed())
222 tickEvent.reschedule(curTick + 1);
223 else if (!tickEvent.scheduled())
224 tickEvent.schedule(curTick + 1);
228 panic("can't get here");
235 // number of simulated instructions
237 Statistics::Formula numInsts;
239 // number of simulated memory references
240 Statistics::Scalar<> numMemRefs;
242 // number of idle cycles
243 Statistics::Scalar<> idleCycles;
244 Statistics::Formula idleFraction;
247 // number of cycles stalled for I-cache misses
248 Statistics::Scalar<> icacheStallCycles;
249 Counter lastIcacheStall;
251 // number of cycles stalled for D-cache misses
252 Statistics::Scalar<> dcacheStallCycles;
253 Counter lastDcacheStall;
255 void processCacheCompletion();
257 virtual void serialize();
258 virtual void unserialize(IniFile &db, const std::string &category,
262 Fault read(Addr addr, T& data, unsigned flags);
265 Fault write(T data, Addr addr, unsigned flags,
268 Fault prefetch(Addr addr, unsigned flags)
270 // need to do this...
274 void writeHint(Addr addr, int size)
276 // need to do this...
280 #endif // __SIMPLE_CPU_HH__