Even more instruction tests
[binutils-gdb.git] / sim / testsuite / ChangeLog
1 Thu Feb 19 11:15:45 1998 Nick Clifton <nickc@cygnus.com>
2
3 * sim/m32r/bl24.cgs: Test long BL instruction.
4 * sim/m32r/bl8.cgs: Test short BL instruction.
5 * sim/m32r/blez.cgs: Test BLEZ instruction.
6 * sim/m32r/bltz.cgs: Test BLTZ instruction.
7 * sim/m32r/bne.cgs: Test BNE instruction.
8 * sim/m32r/bnez.cgs: Test BNEZ instruction.
9 * sim/m32r/bra24.cgs: Test long BRA instruction.
10 * sim/m32r/bra8.cgs: Test short BRA instruction.
11 * sim/m32r/jl.cgs: Test JL instruction.
12 * sim/m32r/or.cgs: Test OR instruction.
13 * sim/m32r/jmp.cgs: Test JMP instruction.
14 * sim/m32r/and.cgs: Test AND instruction.
15 * sim/m32r/and3.cgs: Test AND3 instruction.
16 * sim/m32r/beq.cgs: Test BEQ instruction.
17 * sim/m32r/beqz.cgs: Test BEQZ instruction.
18 * sim/m32r/bgez.cgs: Test BGEZ instruction.
19 * sim/m32r/bgtz.cgs: Test BGTZ instruction.
20 * sim/m32r/cmp.cgs: Test CMP instruction.
21 * sim/m32r/cmpi.cgs: Test CMPI instruction.
22 * sim/m32r/cmpu.cgs: Test CMPU instruction.
23 * sim/m32r/cmpui.cgs: Test CMPUI instruction.
24 * sim/m32r/div.cgs: Test DIV instruction.
25 * sim/m32r/divu.cgs: Test DIVU instruction.
26 * sim/m32r/cmpeq.cgs: Test CMPEQ instruction.
27 * sim/m32r/sll.cgs: Test SLL instruction.
28 * sim/m32r/sll3.cgs: Test SLL3 instruction.
29 * sim/m32r/slli.cgs: Test SLLI instruction.
30 * sim/m32r/sra.cgs: Test SRA instruction.
31 * sim/m32r/sra3.cgs: Test SRA3 instruction.
32 * sim/m32r/srai.cgs: Test SRAI instruction.
33 * sim/m32r/srl.cgs: Test SRL instruction.
34 * sim/m32r/srl3.cgs: Test SRL3 instruction.
35 * sim/m32r/srli.cgs: Test SRLI instruction.
36 * sim/m32r/xor3.cgs: Test XOR3 instruction.
37 * sim/m32r/xor.cgs: Test XOR instruction.
38 start-sanitize-m342rx
39 * sim/m32r/jnc.cgs: Test JNC instruction.
40 * sim/m32r/jc.cgs: Test JC instruction.
41 * sim/m32r/cmpz.cgs: Test CMPZ instruction.
42 * sim/m32r/bcl24.cgs: Test long version of BCL instruction
43 * sim/m32r/bcl8.cgs: Test short BCL instruction.
44 * sim/m32r/bncl24.cgs: Test long BNCL instruction.
45 * sim/m32r/bncl8.cgs: Test short BNCL instruction.
46 * sim/m32r/divh.cgs: Test DIVH instruction.
47 end-sanitize-m342rx
48 Tue Feb 17 12:46:05 1998 Doug Evans <devans@seba.cygnus.com>
49
50 * config/default.exp: New file.
51 * lib/sim-defs.exp: New file.
52 * sim/m32r/*: m32r dejagnu simulator testsuite.
53
54 * Makefile.in (build_alias): Define.
55 (arch): Define.
56 (RUNTEST_FOR_TARGET): Delete.
57 (RUNTEST): Fix.
58 (SCHEME,SCHEMEFLAGS,CGENDIR,CGENFLAGS): Define.
59 (check): Depend on site.exp. Run dejagnu.
60 (site.exp): New target.
61 (cgen): New target.
62 * configure.in: Call AC_CHECK_PROG(SCHEME) if using cgen.
63 (arch): Define from target_cpu.
64 * configure: Regenerate.
65
66 Wed Sep 17 10:21:26 1997 Andrew Cagney <cagney@b1.cygnus.com>
67
68 * common/bits-gen.c (gen_bit): Pass in the full name of the macro.
69 (gen_mask): Ditto.
70
71 * common/bits-tst.c (main): Add tests for LSSEXT, MSSEXT.
72 (calc): Add support for 8 bit version of macros.
73 (main): Add tests for 8 bit versions of macros.
74 (check_sext): Check SEXT of zero clears bits.
75
76 * common/bits-gen.c (main): Generate tests for 8 bit versions of
77 macros.
78
79 Thu Sep 11 13:04:40 1997 Andrew Cagney <cagney@b1.cygnus.com>
80
81 * common/Make-common.in: New file, provide generic rules for
82 running checks.
83
84 Mon Sep 1 16:43:55 1997 Andrew Cagney <cagney@b1.cygnus.com>
85
86 * configure.in (configdirs): Test for the target directory instead
87 of matching on a target.
88
89 start-sanitize-r5900
90 Tue Jul 15 13:43:20 1997 Andrew Cagney <cagney@sendai.cygnus.com>
91
92 * configure.in (configdirs): Configure mips64vr5900el
93 directory.
94 * configure: Regenerate.
95
96 end-sanitize-r5900